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Generate the Verilog code corresponding to this FIRRTL code module Queue1_RegMapperInput_i23_m8 :
input clock : Clock
input reset : Reset
output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<23>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<23>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}}, count : UInt<1>}
cmem ram : { read : UInt<1>, index : UInt<23>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}} [1]
wire enq_ptr_value : UInt
connect enq_ptr_value, UInt<1>(0h0)
wire deq_ptr_value : UInt
connect deq_ptr_value, UInt<1>(0h0)
regreset maybe_full : UInt<1>, clock, reset, UInt<1>(0h0)
node ptr_match = eq(enq_ptr_value, deq_ptr_value)
node _empty_T = eq(maybe_full, UInt<1>(0h0))
node empty = and(ptr_match, _empty_T)
node full = and(ptr_match, maybe_full)
node _do_enq_T = and(io.enq.ready, io.enq.valid)
wire do_enq : UInt<1>
connect do_enq, _do_enq_T
node _do_deq_T = and(io.deq.ready, io.deq.valid)
wire do_deq : UInt<1>
connect do_deq, _do_deq_T
when do_enq :
wire _WIRE : UInt
connect _WIRE, UInt<1>(0h0)
infer mport MPORT = ram[_WIRE], clock
connect MPORT.extra, io.enq.bits.extra
connect MPORT.mask, io.enq.bits.mask
connect MPORT.data, io.enq.bits.data
connect MPORT.index, io.enq.bits.index
connect MPORT.read, io.enq.bits.read
when do_deq :
skip
node _T = neq(do_enq, do_deq)
when _T :
connect maybe_full, do_enq
when UInt<1>(0h0) :
connect enq_ptr_value, UInt<1>(0h0)
connect deq_ptr_value, UInt<1>(0h0)
connect maybe_full, UInt<1>(0h0)
node _io_deq_valid_T = eq(empty, UInt<1>(0h0))
connect io.deq.valid, _io_deq_valid_T
node _io_enq_ready_T = eq(full, UInt<1>(0h0))
connect io.enq.ready, _io_enq_ready_T
wire _io_deq_bits_WIRE : UInt
connect _io_deq_bits_WIRE, UInt<1>(0h0)
infer mport io_deq_bits_MPORT = ram[_io_deq_bits_WIRE], clock
connect io.deq.bits, io_deq_bits_MPORT
node _ptr_diff_T = sub(enq_ptr_value, deq_ptr_value)
node ptr_diff = tail(_ptr_diff_T, 1)
node _io_count_T = and(maybe_full, ptr_match)
node _io_count_T_1 = mux(_io_count_T, UInt<1>(0h1), UInt<1>(0h0))
node _io_count_T_2 = or(_io_count_T_1, ptr_diff)
connect io.count, _io_count_T_2 | module Queue1_RegMapperInput_i23_m8( // @[RegMapper.scala:71:32]
input clock, // @[RegMapper.scala:71:32]
input reset, // @[RegMapper.scala:71:32]
output io_enq_ready, // @[Decoupled.scala:255:14]
input io_enq_valid, // @[Decoupled.scala:255:14]
input io_enq_bits_read, // @[Decoupled.scala:255:14]
input [22:0] io_enq_bits_index, // @[Decoupled.scala:255:14]
input [63:0] io_enq_bits_data, // @[Decoupled.scala:255:14]
input [7:0] io_enq_bits_mask, // @[Decoupled.scala:255:14]
input [10:0] io_enq_bits_extra_tlrr_extra_source, // @[Decoupled.scala:255:14]
input [1:0] io_enq_bits_extra_tlrr_extra_size, // @[Decoupled.scala:255:14]
input io_deq_ready, // @[Decoupled.scala:255:14]
output io_deq_valid, // @[Decoupled.scala:255:14]
output io_deq_bits_read, // @[Decoupled.scala:255:14]
output [22:0] io_deq_bits_index, // @[Decoupled.scala:255:14]
output [63:0] io_deq_bits_data, // @[Decoupled.scala:255:14]
output [7:0] io_deq_bits_mask, // @[Decoupled.scala:255:14]
output [10:0] io_deq_bits_extra_tlrr_extra_source, // @[Decoupled.scala:255:14]
output [1:0] io_deq_bits_extra_tlrr_extra_size // @[Decoupled.scala:255:14]
);
reg [108:0] ram; // @[Decoupled.scala:256:91]
reg full; // @[Decoupled.scala:259:27]
wire do_enq = ~full & io_enq_valid; // @[Decoupled.scala:51:35, :259:27, :286:19]
always @(posedge clock) begin // @[RegMapper.scala:71:32]
if (do_enq) // @[Decoupled.scala:51:35]
ram <= {io_enq_bits_extra_tlrr_extra_size, io_enq_bits_extra_tlrr_extra_source, io_enq_bits_mask, io_enq_bits_data, io_enq_bits_index, io_enq_bits_read}; // @[Decoupled.scala:256:91]
if (reset) // @[RegMapper.scala:71:32]
full <= 1'h0; // @[Decoupled.scala:259:27]
else if (~(do_enq == (io_deq_ready & full))) // @[Decoupled.scala:51:35, :259:27, :276:{15,27}, :277:16]
full <= do_enq; // @[Decoupled.scala:51:35, :259:27]
always @(posedge) |
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_164 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>}
node _io_out_d_T = mul(io.in_a, io.in_b)
node _io_out_d_T_1 = add(_io_out_d_T, io.in_c)
node _io_out_d_T_2 = tail(_io_out_d_T_1, 1)
node _io_out_d_T_3 = asSInt(_io_out_d_T_2)
connect io.out_d, _io_out_d_T_3 | module MacUnit_164( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [31:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7]
wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54]
wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_18 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_18
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_18( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_18 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_252 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<20>, out_d : SInt<20>}
node _io_out_d_T = mul(io.in_a, io.in_b)
node _io_out_d_T_1 = add(_io_out_d_T, io.in_c)
node _io_out_d_T_2 = tail(_io_out_d_T_1, 1)
node _io_out_d_T_3 = asSInt(_io_out_d_T_2)
connect io.out_d, _io_out_d_T_3 | module MacUnit_252( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [19:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7]
wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54]
assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_47 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<6>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 5, 0)
node _source_ok_T = shr(io.in.a.bits.source, 6)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h1))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<6>(0h3f))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<6>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 5, 0)
node _source_ok_T_6 = shr(io.in.a.bits.source, 6)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<6>(0h3f))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
wire _source_ok_WIRE : UInt<1>[2]
connect _source_ok_WIRE[0], _source_ok_T_5
connect _source_ok_WIRE[1], _source_ok_T_11
node source_ok = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<4>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 3, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<3>(0h4))
node mask_sub_sub_sub_size = bits(mask_sizeOH, 3, 3)
node mask_sub_sub_sub_bit = bits(io.in.a.bits.address, 3, 3)
node mask_sub_sub_sub_nbit = eq(mask_sub_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_sub_nbit)
node _mask_sub_sub_sub_acc_T = and(mask_sub_sub_sub_size, mask_sub_sub_sub_0_2)
node mask_sub_sub_sub_0_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T)
node mask_sub_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_sub_bit)
node _mask_sub_sub_sub_acc_T_1 = and(mask_sub_sub_sub_size, mask_sub_sub_sub_1_2)
node mask_sub_sub_sub_1_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T_1)
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_sub_2_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_nbit)
node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size, mask_sub_sub_2_2)
node mask_sub_sub_2_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_2)
node mask_sub_sub_3_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_bit)
node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size, mask_sub_sub_3_2)
node mask_sub_sub_3_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_3)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_sub_4_2 = and(mask_sub_sub_2_2, mask_sub_nbit)
node _mask_sub_acc_T_4 = and(mask_sub_size, mask_sub_4_2)
node mask_sub_4_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_4)
node mask_sub_5_2 = and(mask_sub_sub_2_2, mask_sub_bit)
node _mask_sub_acc_T_5 = and(mask_sub_size, mask_sub_5_2)
node mask_sub_5_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_5)
node mask_sub_6_2 = and(mask_sub_sub_3_2, mask_sub_nbit)
node _mask_sub_acc_T_6 = and(mask_sub_size, mask_sub_6_2)
node mask_sub_6_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_6)
node mask_sub_7_2 = and(mask_sub_sub_3_2, mask_sub_bit)
node _mask_sub_acc_T_7 = and(mask_sub_size, mask_sub_7_2)
node mask_sub_7_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_7)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_eq_8 = and(mask_sub_4_2, mask_nbit)
node _mask_acc_T_8 = and(mask_size, mask_eq_8)
node mask_acc_8 = or(mask_sub_4_1, _mask_acc_T_8)
node mask_eq_9 = and(mask_sub_4_2, mask_bit)
node _mask_acc_T_9 = and(mask_size, mask_eq_9)
node mask_acc_9 = or(mask_sub_4_1, _mask_acc_T_9)
node mask_eq_10 = and(mask_sub_5_2, mask_nbit)
node _mask_acc_T_10 = and(mask_size, mask_eq_10)
node mask_acc_10 = or(mask_sub_5_1, _mask_acc_T_10)
node mask_eq_11 = and(mask_sub_5_2, mask_bit)
node _mask_acc_T_11 = and(mask_size, mask_eq_11)
node mask_acc_11 = or(mask_sub_5_1, _mask_acc_T_11)
node mask_eq_12 = and(mask_sub_6_2, mask_nbit)
node _mask_acc_T_12 = and(mask_size, mask_eq_12)
node mask_acc_12 = or(mask_sub_6_1, _mask_acc_T_12)
node mask_eq_13 = and(mask_sub_6_2, mask_bit)
node _mask_acc_T_13 = and(mask_size, mask_eq_13)
node mask_acc_13 = or(mask_sub_6_1, _mask_acc_T_13)
node mask_eq_14 = and(mask_sub_7_2, mask_nbit)
node _mask_acc_T_14 = and(mask_size, mask_eq_14)
node mask_acc_14 = or(mask_sub_7_1, _mask_acc_T_14)
node mask_eq_15 = and(mask_sub_7_2, mask_bit)
node _mask_acc_T_15 = and(mask_size, mask_eq_15)
node mask_acc_15 = or(mask_sub_7_1, _mask_acc_T_15)
node mask_lo_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo_lo = cat(mask_lo_lo_hi, mask_lo_lo_lo)
node mask_lo_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_lo_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_lo_hi = cat(mask_lo_hi_hi, mask_lo_hi_lo)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo_lo = cat(mask_acc_9, mask_acc_8)
node mask_hi_lo_hi = cat(mask_acc_11, mask_acc_10)
node mask_hi_lo = cat(mask_hi_lo_hi, mask_hi_lo_lo)
node mask_hi_hi_lo = cat(mask_acc_13, mask_acc_12)
node mask_hi_hi_hi = cat(mask_acc_15, mask_acc_14)
node mask_hi_hi = cat(mask_hi_hi_hi, mask_hi_hi_lo)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits = bits(_uncommonBits_T, 5, 0)
node _T_4 = shr(io.in.a.bits.source, 6)
node _T_5 = eq(_T_4, UInt<1>(0h1))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<6>(0h3f))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 5, 0)
node _T_17 = shr(io.in.a.bits.source, 6)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_20 = and(_T_18, _T_19)
node _T_21 = leq(uncommonBits_1, UInt<6>(0h3f))
node _T_22 = and(_T_20, _T_21)
node _T_23 = eq(_T_22, UInt<1>(0h0))
node _T_24 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_25 = cvt(_T_24)
node _T_26 = and(_T_25, asSInt(UInt<1>(0h0)))
node _T_27 = asSInt(_T_26)
node _T_28 = eq(_T_27, asSInt(UInt<1>(0h0)))
node _T_29 = or(_T_23, _T_28)
node _T_30 = and(_T_16, _T_29)
node _T_31 = asUInt(reset)
node _T_32 = eq(_T_31, UInt<1>(0h0))
when _T_32 :
node _T_33 = eq(_T_30, UInt<1>(0h0))
when _T_33 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_30, UInt<1>(0h1), "") : assert_1
node _T_34 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_34 :
node _T_35 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_36 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_37 = and(_T_35, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 5, 0)
node _T_38 = shr(io.in.a.bits.source, 6)
node _T_39 = eq(_T_38, UInt<1>(0h1))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<6>(0h3f))
node _T_43 = and(_T_41, _T_42)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 5, 0)
node _T_44 = shr(io.in.a.bits.source, 6)
node _T_45 = eq(_T_44, UInt<1>(0h0))
node _T_46 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_47 = and(_T_45, _T_46)
node _T_48 = leq(uncommonBits_3, UInt<6>(0h3f))
node _T_49 = and(_T_47, _T_48)
node _T_50 = or(_T_43, _T_49)
node _T_51 = and(_T_37, _T_50)
node _T_52 = or(UInt<1>(0h0), _T_51)
node _T_53 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_54 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_55 = cvt(_T_54)
node _T_56 = and(_T_55, asSInt(UInt<14>(0h2000)))
node _T_57 = asSInt(_T_56)
node _T_58 = eq(_T_57, asSInt(UInt<1>(0h0)))
node _T_59 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_60 = cvt(_T_59)
node _T_61 = and(_T_60, asSInt(UInt<13>(0h1000)))
node _T_62 = asSInt(_T_61)
node _T_63 = eq(_T_62, asSInt(UInt<1>(0h0)))
node _T_64 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_65 = cvt(_T_64)
node _T_66 = and(_T_65, asSInt(UInt<17>(0h10000)))
node _T_67 = asSInt(_T_66)
node _T_68 = eq(_T_67, asSInt(UInt<1>(0h0)))
node _T_69 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_70 = cvt(_T_69)
node _T_71 = and(_T_70, asSInt(UInt<18>(0h2f000)))
node _T_72 = asSInt(_T_71)
node _T_73 = eq(_T_72, asSInt(UInt<1>(0h0)))
node _T_74 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_75 = cvt(_T_74)
node _T_76 = and(_T_75, asSInt(UInt<17>(0h10000)))
node _T_77 = asSInt(_T_76)
node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0)))
node _T_79 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_80 = cvt(_T_79)
node _T_81 = and(_T_80, asSInt(UInt<13>(0h1000)))
node _T_82 = asSInt(_T_81)
node _T_83 = eq(_T_82, asSInt(UInt<1>(0h0)))
node _T_84 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_85 = cvt(_T_84)
node _T_86 = and(_T_85, asSInt(UInt<27>(0h4000000)))
node _T_87 = asSInt(_T_86)
node _T_88 = eq(_T_87, asSInt(UInt<1>(0h0)))
node _T_89 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_90 = cvt(_T_89)
node _T_91 = and(_T_90, asSInt(UInt<13>(0h1000)))
node _T_92 = asSInt(_T_91)
node _T_93 = eq(_T_92, asSInt(UInt<1>(0h0)))
node _T_94 = or(_T_58, _T_63)
node _T_95 = or(_T_94, _T_68)
node _T_96 = or(_T_95, _T_73)
node _T_97 = or(_T_96, _T_78)
node _T_98 = or(_T_97, _T_83)
node _T_99 = or(_T_98, _T_88)
node _T_100 = or(_T_99, _T_93)
node _T_101 = and(_T_53, _T_100)
node _T_102 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_103 = or(UInt<1>(0h0), _T_102)
node _T_104 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_105 = cvt(_T_104)
node _T_106 = and(_T_105, asSInt(UInt<17>(0h10000)))
node _T_107 = asSInt(_T_106)
node _T_108 = eq(_T_107, asSInt(UInt<1>(0h0)))
node _T_109 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_110 = cvt(_T_109)
node _T_111 = and(_T_110, asSInt(UInt<29>(0h10000000)))
node _T_112 = asSInt(_T_111)
node _T_113 = eq(_T_112, asSInt(UInt<1>(0h0)))
node _T_114 = or(_T_108, _T_113)
node _T_115 = and(_T_103, _T_114)
node _T_116 = or(UInt<1>(0h0), _T_101)
node _T_117 = or(_T_116, _T_115)
node _T_118 = and(_T_52, _T_117)
node _T_119 = asUInt(reset)
node _T_120 = eq(_T_119, UInt<1>(0h0))
when _T_120 :
node _T_121 = eq(_T_118, UInt<1>(0h0))
when _T_121 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_118, UInt<1>(0h1), "") : assert_2
node _T_122 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_123 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_124 = and(_T_122, _T_123)
node _T_125 = or(UInt<1>(0h0), _T_124)
node _T_126 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_127 = cvt(_T_126)
node _T_128 = and(_T_127, asSInt(UInt<14>(0h2000)))
node _T_129 = asSInt(_T_128)
node _T_130 = eq(_T_129, asSInt(UInt<1>(0h0)))
node _T_131 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_132 = cvt(_T_131)
node _T_133 = and(_T_132, asSInt(UInt<13>(0h1000)))
node _T_134 = asSInt(_T_133)
node _T_135 = eq(_T_134, asSInt(UInt<1>(0h0)))
node _T_136 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_137 = cvt(_T_136)
node _T_138 = and(_T_137, asSInt(UInt<17>(0h10000)))
node _T_139 = asSInt(_T_138)
node _T_140 = eq(_T_139, asSInt(UInt<1>(0h0)))
node _T_141 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_142 = cvt(_T_141)
node _T_143 = and(_T_142, asSInt(UInt<18>(0h2f000)))
node _T_144 = asSInt(_T_143)
node _T_145 = eq(_T_144, asSInt(UInt<1>(0h0)))
node _T_146 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_147 = cvt(_T_146)
node _T_148 = and(_T_147, asSInt(UInt<17>(0h10000)))
node _T_149 = asSInt(_T_148)
node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0)))
node _T_151 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_152 = cvt(_T_151)
node _T_153 = and(_T_152, asSInt(UInt<13>(0h1000)))
node _T_154 = asSInt(_T_153)
node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0)))
node _T_156 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_157 = cvt(_T_156)
node _T_158 = and(_T_157, asSInt(UInt<17>(0h10000)))
node _T_159 = asSInt(_T_158)
node _T_160 = eq(_T_159, asSInt(UInt<1>(0h0)))
node _T_161 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_162 = cvt(_T_161)
node _T_163 = and(_T_162, asSInt(UInt<27>(0h4000000)))
node _T_164 = asSInt(_T_163)
node _T_165 = eq(_T_164, asSInt(UInt<1>(0h0)))
node _T_166 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_167 = cvt(_T_166)
node _T_168 = and(_T_167, asSInt(UInt<13>(0h1000)))
node _T_169 = asSInt(_T_168)
node _T_170 = eq(_T_169, asSInt(UInt<1>(0h0)))
node _T_171 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_172 = cvt(_T_171)
node _T_173 = and(_T_172, asSInt(UInt<29>(0h10000000)))
node _T_174 = asSInt(_T_173)
node _T_175 = eq(_T_174, asSInt(UInt<1>(0h0)))
node _T_176 = or(_T_130, _T_135)
node _T_177 = or(_T_176, _T_140)
node _T_178 = or(_T_177, _T_145)
node _T_179 = or(_T_178, _T_150)
node _T_180 = or(_T_179, _T_155)
node _T_181 = or(_T_180, _T_160)
node _T_182 = or(_T_181, _T_165)
node _T_183 = or(_T_182, _T_170)
node _T_184 = or(_T_183, _T_175)
node _T_185 = and(_T_125, _T_184)
node _T_186 = or(UInt<1>(0h0), _T_185)
node _T_187 = and(UInt<1>(0h0), _T_186)
node _T_188 = asUInt(reset)
node _T_189 = eq(_T_188, UInt<1>(0h0))
when _T_189 :
node _T_190 = eq(_T_187, UInt<1>(0h0))
when _T_190 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_187, UInt<1>(0h1), "") : assert_3
node _T_191 = asUInt(reset)
node _T_192 = eq(_T_191, UInt<1>(0h0))
when _T_192 :
node _T_193 = eq(source_ok, UInt<1>(0h0))
when _T_193 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_194 = geq(io.in.a.bits.size, UInt<3>(0h4))
node _T_195 = asUInt(reset)
node _T_196 = eq(_T_195, UInt<1>(0h0))
when _T_196 :
node _T_197 = eq(_T_194, UInt<1>(0h0))
when _T_197 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_194, UInt<1>(0h1), "") : assert_5
node _T_198 = asUInt(reset)
node _T_199 = eq(_T_198, UInt<1>(0h0))
when _T_199 :
node _T_200 = eq(is_aligned, UInt<1>(0h0))
when _T_200 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_201 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_202 = asUInt(reset)
node _T_203 = eq(_T_202, UInt<1>(0h0))
when _T_203 :
node _T_204 = eq(_T_201, UInt<1>(0h0))
when _T_204 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_201, UInt<1>(0h1), "") : assert_7
node _T_205 = not(io.in.a.bits.mask)
node _T_206 = eq(_T_205, UInt<1>(0h0))
node _T_207 = asUInt(reset)
node _T_208 = eq(_T_207, UInt<1>(0h0))
when _T_208 :
node _T_209 = eq(_T_206, UInt<1>(0h0))
when _T_209 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_206, UInt<1>(0h1), "") : assert_8
node _T_210 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_211 = asUInt(reset)
node _T_212 = eq(_T_211, UInt<1>(0h0))
when _T_212 :
node _T_213 = eq(_T_210, UInt<1>(0h0))
when _T_213 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_210, UInt<1>(0h1), "") : assert_9
node _T_214 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_214 :
node _T_215 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_216 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_217 = and(_T_215, _T_216)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 5, 0)
node _T_218 = shr(io.in.a.bits.source, 6)
node _T_219 = eq(_T_218, UInt<1>(0h1))
node _T_220 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_221 = and(_T_219, _T_220)
node _T_222 = leq(uncommonBits_4, UInt<6>(0h3f))
node _T_223 = and(_T_221, _T_222)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 5, 0)
node _T_224 = shr(io.in.a.bits.source, 6)
node _T_225 = eq(_T_224, UInt<1>(0h0))
node _T_226 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_227 = and(_T_225, _T_226)
node _T_228 = leq(uncommonBits_5, UInt<6>(0h3f))
node _T_229 = and(_T_227, _T_228)
node _T_230 = or(_T_223, _T_229)
node _T_231 = and(_T_217, _T_230)
node _T_232 = or(UInt<1>(0h0), _T_231)
node _T_233 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_234 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_235 = cvt(_T_234)
node _T_236 = and(_T_235, asSInt(UInt<14>(0h2000)))
node _T_237 = asSInt(_T_236)
node _T_238 = eq(_T_237, asSInt(UInt<1>(0h0)))
node _T_239 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_240 = cvt(_T_239)
node _T_241 = and(_T_240, asSInt(UInt<13>(0h1000)))
node _T_242 = asSInt(_T_241)
node _T_243 = eq(_T_242, asSInt(UInt<1>(0h0)))
node _T_244 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_245 = cvt(_T_244)
node _T_246 = and(_T_245, asSInt(UInt<17>(0h10000)))
node _T_247 = asSInt(_T_246)
node _T_248 = eq(_T_247, asSInt(UInt<1>(0h0)))
node _T_249 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_250 = cvt(_T_249)
node _T_251 = and(_T_250, asSInt(UInt<18>(0h2f000)))
node _T_252 = asSInt(_T_251)
node _T_253 = eq(_T_252, asSInt(UInt<1>(0h0)))
node _T_254 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_255 = cvt(_T_254)
node _T_256 = and(_T_255, asSInt(UInt<17>(0h10000)))
node _T_257 = asSInt(_T_256)
node _T_258 = eq(_T_257, asSInt(UInt<1>(0h0)))
node _T_259 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_260 = cvt(_T_259)
node _T_261 = and(_T_260, asSInt(UInt<13>(0h1000)))
node _T_262 = asSInt(_T_261)
node _T_263 = eq(_T_262, asSInt(UInt<1>(0h0)))
node _T_264 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_265 = cvt(_T_264)
node _T_266 = and(_T_265, asSInt(UInt<27>(0h4000000)))
node _T_267 = asSInt(_T_266)
node _T_268 = eq(_T_267, asSInt(UInt<1>(0h0)))
node _T_269 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_270 = cvt(_T_269)
node _T_271 = and(_T_270, asSInt(UInt<13>(0h1000)))
node _T_272 = asSInt(_T_271)
node _T_273 = eq(_T_272, asSInt(UInt<1>(0h0)))
node _T_274 = or(_T_238, _T_243)
node _T_275 = or(_T_274, _T_248)
node _T_276 = or(_T_275, _T_253)
node _T_277 = or(_T_276, _T_258)
node _T_278 = or(_T_277, _T_263)
node _T_279 = or(_T_278, _T_268)
node _T_280 = or(_T_279, _T_273)
node _T_281 = and(_T_233, _T_280)
node _T_282 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_283 = or(UInt<1>(0h0), _T_282)
node _T_284 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_285 = cvt(_T_284)
node _T_286 = and(_T_285, asSInt(UInt<17>(0h10000)))
node _T_287 = asSInt(_T_286)
node _T_288 = eq(_T_287, asSInt(UInt<1>(0h0)))
node _T_289 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_290 = cvt(_T_289)
node _T_291 = and(_T_290, asSInt(UInt<29>(0h10000000)))
node _T_292 = asSInt(_T_291)
node _T_293 = eq(_T_292, asSInt(UInt<1>(0h0)))
node _T_294 = or(_T_288, _T_293)
node _T_295 = and(_T_283, _T_294)
node _T_296 = or(UInt<1>(0h0), _T_281)
node _T_297 = or(_T_296, _T_295)
node _T_298 = and(_T_232, _T_297)
node _T_299 = asUInt(reset)
node _T_300 = eq(_T_299, UInt<1>(0h0))
when _T_300 :
node _T_301 = eq(_T_298, UInt<1>(0h0))
when _T_301 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_298, UInt<1>(0h1), "") : assert_10
node _T_302 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_303 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_304 = and(_T_302, _T_303)
node _T_305 = or(UInt<1>(0h0), _T_304)
node _T_306 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_307 = cvt(_T_306)
node _T_308 = and(_T_307, asSInt(UInt<14>(0h2000)))
node _T_309 = asSInt(_T_308)
node _T_310 = eq(_T_309, asSInt(UInt<1>(0h0)))
node _T_311 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_312 = cvt(_T_311)
node _T_313 = and(_T_312, asSInt(UInt<13>(0h1000)))
node _T_314 = asSInt(_T_313)
node _T_315 = eq(_T_314, asSInt(UInt<1>(0h0)))
node _T_316 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_317 = cvt(_T_316)
node _T_318 = and(_T_317, asSInt(UInt<17>(0h10000)))
node _T_319 = asSInt(_T_318)
node _T_320 = eq(_T_319, asSInt(UInt<1>(0h0)))
node _T_321 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_322 = cvt(_T_321)
node _T_323 = and(_T_322, asSInt(UInt<18>(0h2f000)))
node _T_324 = asSInt(_T_323)
node _T_325 = eq(_T_324, asSInt(UInt<1>(0h0)))
node _T_326 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_327 = cvt(_T_326)
node _T_328 = and(_T_327, asSInt(UInt<17>(0h10000)))
node _T_329 = asSInt(_T_328)
node _T_330 = eq(_T_329, asSInt(UInt<1>(0h0)))
node _T_331 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_332 = cvt(_T_331)
node _T_333 = and(_T_332, asSInt(UInt<13>(0h1000)))
node _T_334 = asSInt(_T_333)
node _T_335 = eq(_T_334, asSInt(UInt<1>(0h0)))
node _T_336 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_337 = cvt(_T_336)
node _T_338 = and(_T_337, asSInt(UInt<17>(0h10000)))
node _T_339 = asSInt(_T_338)
node _T_340 = eq(_T_339, asSInt(UInt<1>(0h0)))
node _T_341 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_342 = cvt(_T_341)
node _T_343 = and(_T_342, asSInt(UInt<27>(0h4000000)))
node _T_344 = asSInt(_T_343)
node _T_345 = eq(_T_344, asSInt(UInt<1>(0h0)))
node _T_346 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_347 = cvt(_T_346)
node _T_348 = and(_T_347, asSInt(UInt<13>(0h1000)))
node _T_349 = asSInt(_T_348)
node _T_350 = eq(_T_349, asSInt(UInt<1>(0h0)))
node _T_351 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_352 = cvt(_T_351)
node _T_353 = and(_T_352, asSInt(UInt<29>(0h10000000)))
node _T_354 = asSInt(_T_353)
node _T_355 = eq(_T_354, asSInt(UInt<1>(0h0)))
node _T_356 = or(_T_310, _T_315)
node _T_357 = or(_T_356, _T_320)
node _T_358 = or(_T_357, _T_325)
node _T_359 = or(_T_358, _T_330)
node _T_360 = or(_T_359, _T_335)
node _T_361 = or(_T_360, _T_340)
node _T_362 = or(_T_361, _T_345)
node _T_363 = or(_T_362, _T_350)
node _T_364 = or(_T_363, _T_355)
node _T_365 = and(_T_305, _T_364)
node _T_366 = or(UInt<1>(0h0), _T_365)
node _T_367 = and(UInt<1>(0h0), _T_366)
node _T_368 = asUInt(reset)
node _T_369 = eq(_T_368, UInt<1>(0h0))
when _T_369 :
node _T_370 = eq(_T_367, UInt<1>(0h0))
when _T_370 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_367, UInt<1>(0h1), "") : assert_11
node _T_371 = asUInt(reset)
node _T_372 = eq(_T_371, UInt<1>(0h0))
when _T_372 :
node _T_373 = eq(source_ok, UInt<1>(0h0))
when _T_373 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_374 = geq(io.in.a.bits.size, UInt<3>(0h4))
node _T_375 = asUInt(reset)
node _T_376 = eq(_T_375, UInt<1>(0h0))
when _T_376 :
node _T_377 = eq(_T_374, UInt<1>(0h0))
when _T_377 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_374, UInt<1>(0h1), "") : assert_13
node _T_378 = asUInt(reset)
node _T_379 = eq(_T_378, UInt<1>(0h0))
when _T_379 :
node _T_380 = eq(is_aligned, UInt<1>(0h0))
when _T_380 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_381 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_382 = asUInt(reset)
node _T_383 = eq(_T_382, UInt<1>(0h0))
when _T_383 :
node _T_384 = eq(_T_381, UInt<1>(0h0))
when _T_384 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_381, UInt<1>(0h1), "") : assert_15
node _T_385 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_386 = asUInt(reset)
node _T_387 = eq(_T_386, UInt<1>(0h0))
when _T_387 :
node _T_388 = eq(_T_385, UInt<1>(0h0))
when _T_388 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_385, UInt<1>(0h1), "") : assert_16
node _T_389 = not(io.in.a.bits.mask)
node _T_390 = eq(_T_389, UInt<1>(0h0))
node _T_391 = asUInt(reset)
node _T_392 = eq(_T_391, UInt<1>(0h0))
when _T_392 :
node _T_393 = eq(_T_390, UInt<1>(0h0))
when _T_393 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_390, UInt<1>(0h1), "") : assert_17
node _T_394 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_395 = asUInt(reset)
node _T_396 = eq(_T_395, UInt<1>(0h0))
when _T_396 :
node _T_397 = eq(_T_394, UInt<1>(0h0))
when _T_397 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_394, UInt<1>(0h1), "") : assert_18
node _T_398 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_398 :
node _T_399 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_400 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_401 = and(_T_399, _T_400)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 5, 0)
node _T_402 = shr(io.in.a.bits.source, 6)
node _T_403 = eq(_T_402, UInt<1>(0h1))
node _T_404 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_405 = and(_T_403, _T_404)
node _T_406 = leq(uncommonBits_6, UInt<6>(0h3f))
node _T_407 = and(_T_405, _T_406)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 5, 0)
node _T_408 = shr(io.in.a.bits.source, 6)
node _T_409 = eq(_T_408, UInt<1>(0h0))
node _T_410 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_411 = and(_T_409, _T_410)
node _T_412 = leq(uncommonBits_7, UInt<6>(0h3f))
node _T_413 = and(_T_411, _T_412)
node _T_414 = or(_T_407, _T_413)
node _T_415 = and(_T_401, _T_414)
node _T_416 = or(UInt<1>(0h0), _T_415)
node _T_417 = asUInt(reset)
node _T_418 = eq(_T_417, UInt<1>(0h0))
when _T_418 :
node _T_419 = eq(_T_416, UInt<1>(0h0))
when _T_419 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_416, UInt<1>(0h1), "") : assert_19
node _T_420 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_421 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_422 = and(_T_420, _T_421)
node _T_423 = or(UInt<1>(0h0), _T_422)
node _T_424 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_425 = cvt(_T_424)
node _T_426 = and(_T_425, asSInt(UInt<13>(0h1000)))
node _T_427 = asSInt(_T_426)
node _T_428 = eq(_T_427, asSInt(UInt<1>(0h0)))
node _T_429 = and(_T_423, _T_428)
node _T_430 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_431 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_432 = and(_T_430, _T_431)
node _T_433 = or(UInt<1>(0h0), _T_432)
node _T_434 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_435 = cvt(_T_434)
node _T_436 = and(_T_435, asSInt(UInt<14>(0h2000)))
node _T_437 = asSInt(_T_436)
node _T_438 = eq(_T_437, asSInt(UInt<1>(0h0)))
node _T_439 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_440 = cvt(_T_439)
node _T_441 = and(_T_440, asSInt(UInt<17>(0h10000)))
node _T_442 = asSInt(_T_441)
node _T_443 = eq(_T_442, asSInt(UInt<1>(0h0)))
node _T_444 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_445 = cvt(_T_444)
node _T_446 = and(_T_445, asSInt(UInt<18>(0h2f000)))
node _T_447 = asSInt(_T_446)
node _T_448 = eq(_T_447, asSInt(UInt<1>(0h0)))
node _T_449 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_450 = cvt(_T_449)
node _T_451 = and(_T_450, asSInt(UInt<17>(0h10000)))
node _T_452 = asSInt(_T_451)
node _T_453 = eq(_T_452, asSInt(UInt<1>(0h0)))
node _T_454 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_455 = cvt(_T_454)
node _T_456 = and(_T_455, asSInt(UInt<13>(0h1000)))
node _T_457 = asSInt(_T_456)
node _T_458 = eq(_T_457, asSInt(UInt<1>(0h0)))
node _T_459 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_460 = cvt(_T_459)
node _T_461 = and(_T_460, asSInt(UInt<17>(0h10000)))
node _T_462 = asSInt(_T_461)
node _T_463 = eq(_T_462, asSInt(UInt<1>(0h0)))
node _T_464 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_465 = cvt(_T_464)
node _T_466 = and(_T_465, asSInt(UInt<27>(0h4000000)))
node _T_467 = asSInt(_T_466)
node _T_468 = eq(_T_467, asSInt(UInt<1>(0h0)))
node _T_469 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_470 = cvt(_T_469)
node _T_471 = and(_T_470, asSInt(UInt<13>(0h1000)))
node _T_472 = asSInt(_T_471)
node _T_473 = eq(_T_472, asSInt(UInt<1>(0h0)))
node _T_474 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_475 = cvt(_T_474)
node _T_476 = and(_T_475, asSInt(UInt<29>(0h10000000)))
node _T_477 = asSInt(_T_476)
node _T_478 = eq(_T_477, asSInt(UInt<1>(0h0)))
node _T_479 = or(_T_438, _T_443)
node _T_480 = or(_T_479, _T_448)
node _T_481 = or(_T_480, _T_453)
node _T_482 = or(_T_481, _T_458)
node _T_483 = or(_T_482, _T_463)
node _T_484 = or(_T_483, _T_468)
node _T_485 = or(_T_484, _T_473)
node _T_486 = or(_T_485, _T_478)
node _T_487 = and(_T_433, _T_486)
node _T_488 = or(UInt<1>(0h0), _T_429)
node _T_489 = or(_T_488, _T_487)
node _T_490 = asUInt(reset)
node _T_491 = eq(_T_490, UInt<1>(0h0))
when _T_491 :
node _T_492 = eq(_T_489, UInt<1>(0h0))
when _T_492 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_489, UInt<1>(0h1), "") : assert_20
node _T_493 = asUInt(reset)
node _T_494 = eq(_T_493, UInt<1>(0h0))
when _T_494 :
node _T_495 = eq(source_ok, UInt<1>(0h0))
when _T_495 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(is_aligned, UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_499 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_500 = asUInt(reset)
node _T_501 = eq(_T_500, UInt<1>(0h0))
when _T_501 :
node _T_502 = eq(_T_499, UInt<1>(0h0))
when _T_502 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_499, UInt<1>(0h1), "") : assert_23
node _T_503 = eq(io.in.a.bits.mask, mask)
node _T_504 = asUInt(reset)
node _T_505 = eq(_T_504, UInt<1>(0h0))
when _T_505 :
node _T_506 = eq(_T_503, UInt<1>(0h0))
when _T_506 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_503, UInt<1>(0h1), "") : assert_24
node _T_507 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_508 = asUInt(reset)
node _T_509 = eq(_T_508, UInt<1>(0h0))
when _T_509 :
node _T_510 = eq(_T_507, UInt<1>(0h0))
when _T_510 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_507, UInt<1>(0h1), "") : assert_25
node _T_511 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_511 :
node _T_512 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_513 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_514 = and(_T_512, _T_513)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 5, 0)
node _T_515 = shr(io.in.a.bits.source, 6)
node _T_516 = eq(_T_515, UInt<1>(0h1))
node _T_517 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_518 = and(_T_516, _T_517)
node _T_519 = leq(uncommonBits_8, UInt<6>(0h3f))
node _T_520 = and(_T_518, _T_519)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 5, 0)
node _T_521 = shr(io.in.a.bits.source, 6)
node _T_522 = eq(_T_521, UInt<1>(0h0))
node _T_523 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_524 = and(_T_522, _T_523)
node _T_525 = leq(uncommonBits_9, UInt<6>(0h3f))
node _T_526 = and(_T_524, _T_525)
node _T_527 = or(_T_520, _T_526)
node _T_528 = and(_T_514, _T_527)
node _T_529 = or(UInt<1>(0h0), _T_528)
node _T_530 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_531 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_532 = and(_T_530, _T_531)
node _T_533 = or(UInt<1>(0h0), _T_532)
node _T_534 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_535 = cvt(_T_534)
node _T_536 = and(_T_535, asSInt(UInt<13>(0h1000)))
node _T_537 = asSInt(_T_536)
node _T_538 = eq(_T_537, asSInt(UInt<1>(0h0)))
node _T_539 = and(_T_533, _T_538)
node _T_540 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_541 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_542 = and(_T_540, _T_541)
node _T_543 = or(UInt<1>(0h0), _T_542)
node _T_544 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_545 = cvt(_T_544)
node _T_546 = and(_T_545, asSInt(UInt<14>(0h2000)))
node _T_547 = asSInt(_T_546)
node _T_548 = eq(_T_547, asSInt(UInt<1>(0h0)))
node _T_549 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_550 = cvt(_T_549)
node _T_551 = and(_T_550, asSInt(UInt<18>(0h2f000)))
node _T_552 = asSInt(_T_551)
node _T_553 = eq(_T_552, asSInt(UInt<1>(0h0)))
node _T_554 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_555 = cvt(_T_554)
node _T_556 = and(_T_555, asSInt(UInt<17>(0h10000)))
node _T_557 = asSInt(_T_556)
node _T_558 = eq(_T_557, asSInt(UInt<1>(0h0)))
node _T_559 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_560 = cvt(_T_559)
node _T_561 = and(_T_560, asSInt(UInt<13>(0h1000)))
node _T_562 = asSInt(_T_561)
node _T_563 = eq(_T_562, asSInt(UInt<1>(0h0)))
node _T_564 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_565 = cvt(_T_564)
node _T_566 = and(_T_565, asSInt(UInt<17>(0h10000)))
node _T_567 = asSInt(_T_566)
node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0)))
node _T_569 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_570 = cvt(_T_569)
node _T_571 = and(_T_570, asSInt(UInt<27>(0h4000000)))
node _T_572 = asSInt(_T_571)
node _T_573 = eq(_T_572, asSInt(UInt<1>(0h0)))
node _T_574 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_575 = cvt(_T_574)
node _T_576 = and(_T_575, asSInt(UInt<13>(0h1000)))
node _T_577 = asSInt(_T_576)
node _T_578 = eq(_T_577, asSInt(UInt<1>(0h0)))
node _T_579 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_580 = cvt(_T_579)
node _T_581 = and(_T_580, asSInt(UInt<29>(0h10000000)))
node _T_582 = asSInt(_T_581)
node _T_583 = eq(_T_582, asSInt(UInt<1>(0h0)))
node _T_584 = or(_T_548, _T_553)
node _T_585 = or(_T_584, _T_558)
node _T_586 = or(_T_585, _T_563)
node _T_587 = or(_T_586, _T_568)
node _T_588 = or(_T_587, _T_573)
node _T_589 = or(_T_588, _T_578)
node _T_590 = or(_T_589, _T_583)
node _T_591 = and(_T_543, _T_590)
node _T_592 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_593 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_594 = cvt(_T_593)
node _T_595 = and(_T_594, asSInt(UInt<17>(0h10000)))
node _T_596 = asSInt(_T_595)
node _T_597 = eq(_T_596, asSInt(UInt<1>(0h0)))
node _T_598 = and(_T_592, _T_597)
node _T_599 = or(UInt<1>(0h0), _T_539)
node _T_600 = or(_T_599, _T_591)
node _T_601 = or(_T_600, _T_598)
node _T_602 = and(_T_529, _T_601)
node _T_603 = asUInt(reset)
node _T_604 = eq(_T_603, UInt<1>(0h0))
when _T_604 :
node _T_605 = eq(_T_602, UInt<1>(0h0))
when _T_605 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_602, UInt<1>(0h1), "") : assert_26
node _T_606 = asUInt(reset)
node _T_607 = eq(_T_606, UInt<1>(0h0))
when _T_607 :
node _T_608 = eq(source_ok, UInt<1>(0h0))
when _T_608 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_609 = asUInt(reset)
node _T_610 = eq(_T_609, UInt<1>(0h0))
when _T_610 :
node _T_611 = eq(is_aligned, UInt<1>(0h0))
when _T_611 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_612 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_613 = asUInt(reset)
node _T_614 = eq(_T_613, UInt<1>(0h0))
when _T_614 :
node _T_615 = eq(_T_612, UInt<1>(0h0))
when _T_615 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_612, UInt<1>(0h1), "") : assert_29
node _T_616 = eq(io.in.a.bits.mask, mask)
node _T_617 = asUInt(reset)
node _T_618 = eq(_T_617, UInt<1>(0h0))
when _T_618 :
node _T_619 = eq(_T_616, UInt<1>(0h0))
when _T_619 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_616, UInt<1>(0h1), "") : assert_30
node _T_620 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_620 :
node _T_621 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_622 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_623 = and(_T_621, _T_622)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 5, 0)
node _T_624 = shr(io.in.a.bits.source, 6)
node _T_625 = eq(_T_624, UInt<1>(0h1))
node _T_626 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_627 = and(_T_625, _T_626)
node _T_628 = leq(uncommonBits_10, UInt<6>(0h3f))
node _T_629 = and(_T_627, _T_628)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 5, 0)
node _T_630 = shr(io.in.a.bits.source, 6)
node _T_631 = eq(_T_630, UInt<1>(0h0))
node _T_632 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_633 = and(_T_631, _T_632)
node _T_634 = leq(uncommonBits_11, UInt<6>(0h3f))
node _T_635 = and(_T_633, _T_634)
node _T_636 = or(_T_629, _T_635)
node _T_637 = and(_T_623, _T_636)
node _T_638 = or(UInt<1>(0h0), _T_637)
node _T_639 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_640 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_641 = and(_T_639, _T_640)
node _T_642 = or(UInt<1>(0h0), _T_641)
node _T_643 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_644 = cvt(_T_643)
node _T_645 = and(_T_644, asSInt(UInt<13>(0h1000)))
node _T_646 = asSInt(_T_645)
node _T_647 = eq(_T_646, asSInt(UInt<1>(0h0)))
node _T_648 = and(_T_642, _T_647)
node _T_649 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_650 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_651 = and(_T_649, _T_650)
node _T_652 = or(UInt<1>(0h0), _T_651)
node _T_653 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_654 = cvt(_T_653)
node _T_655 = and(_T_654, asSInt(UInt<14>(0h2000)))
node _T_656 = asSInt(_T_655)
node _T_657 = eq(_T_656, asSInt(UInt<1>(0h0)))
node _T_658 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_659 = cvt(_T_658)
node _T_660 = and(_T_659, asSInt(UInt<18>(0h2f000)))
node _T_661 = asSInt(_T_660)
node _T_662 = eq(_T_661, asSInt(UInt<1>(0h0)))
node _T_663 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_664 = cvt(_T_663)
node _T_665 = and(_T_664, asSInt(UInt<17>(0h10000)))
node _T_666 = asSInt(_T_665)
node _T_667 = eq(_T_666, asSInt(UInt<1>(0h0)))
node _T_668 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_669 = cvt(_T_668)
node _T_670 = and(_T_669, asSInt(UInt<13>(0h1000)))
node _T_671 = asSInt(_T_670)
node _T_672 = eq(_T_671, asSInt(UInt<1>(0h0)))
node _T_673 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_674 = cvt(_T_673)
node _T_675 = and(_T_674, asSInt(UInt<17>(0h10000)))
node _T_676 = asSInt(_T_675)
node _T_677 = eq(_T_676, asSInt(UInt<1>(0h0)))
node _T_678 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_679 = cvt(_T_678)
node _T_680 = and(_T_679, asSInt(UInt<27>(0h4000000)))
node _T_681 = asSInt(_T_680)
node _T_682 = eq(_T_681, asSInt(UInt<1>(0h0)))
node _T_683 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_684 = cvt(_T_683)
node _T_685 = and(_T_684, asSInt(UInt<13>(0h1000)))
node _T_686 = asSInt(_T_685)
node _T_687 = eq(_T_686, asSInt(UInt<1>(0h0)))
node _T_688 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_689 = cvt(_T_688)
node _T_690 = and(_T_689, asSInt(UInt<29>(0h10000000)))
node _T_691 = asSInt(_T_690)
node _T_692 = eq(_T_691, asSInt(UInt<1>(0h0)))
node _T_693 = or(_T_657, _T_662)
node _T_694 = or(_T_693, _T_667)
node _T_695 = or(_T_694, _T_672)
node _T_696 = or(_T_695, _T_677)
node _T_697 = or(_T_696, _T_682)
node _T_698 = or(_T_697, _T_687)
node _T_699 = or(_T_698, _T_692)
node _T_700 = and(_T_652, _T_699)
node _T_701 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_702 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_703 = cvt(_T_702)
node _T_704 = and(_T_703, asSInt(UInt<17>(0h10000)))
node _T_705 = asSInt(_T_704)
node _T_706 = eq(_T_705, asSInt(UInt<1>(0h0)))
node _T_707 = and(_T_701, _T_706)
node _T_708 = or(UInt<1>(0h0), _T_648)
node _T_709 = or(_T_708, _T_700)
node _T_710 = or(_T_709, _T_707)
node _T_711 = and(_T_638, _T_710)
node _T_712 = asUInt(reset)
node _T_713 = eq(_T_712, UInt<1>(0h0))
when _T_713 :
node _T_714 = eq(_T_711, UInt<1>(0h0))
when _T_714 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_711, UInt<1>(0h1), "") : assert_31
node _T_715 = asUInt(reset)
node _T_716 = eq(_T_715, UInt<1>(0h0))
when _T_716 :
node _T_717 = eq(source_ok, UInt<1>(0h0))
when _T_717 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_718 = asUInt(reset)
node _T_719 = eq(_T_718, UInt<1>(0h0))
when _T_719 :
node _T_720 = eq(is_aligned, UInt<1>(0h0))
when _T_720 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_721 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_722 = asUInt(reset)
node _T_723 = eq(_T_722, UInt<1>(0h0))
when _T_723 :
node _T_724 = eq(_T_721, UInt<1>(0h0))
when _T_724 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_721, UInt<1>(0h1), "") : assert_34
node _T_725 = not(mask)
node _T_726 = and(io.in.a.bits.mask, _T_725)
node _T_727 = eq(_T_726, UInt<1>(0h0))
node _T_728 = asUInt(reset)
node _T_729 = eq(_T_728, UInt<1>(0h0))
when _T_729 :
node _T_730 = eq(_T_727, UInt<1>(0h0))
when _T_730 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_727, UInt<1>(0h1), "") : assert_35
node _T_731 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_731 :
node _T_732 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_733 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_734 = and(_T_732, _T_733)
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 5, 0)
node _T_735 = shr(io.in.a.bits.source, 6)
node _T_736 = eq(_T_735, UInt<1>(0h1))
node _T_737 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_738 = and(_T_736, _T_737)
node _T_739 = leq(uncommonBits_12, UInt<6>(0h3f))
node _T_740 = and(_T_738, _T_739)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 5, 0)
node _T_741 = shr(io.in.a.bits.source, 6)
node _T_742 = eq(_T_741, UInt<1>(0h0))
node _T_743 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_744 = and(_T_742, _T_743)
node _T_745 = leq(uncommonBits_13, UInt<6>(0h3f))
node _T_746 = and(_T_744, _T_745)
node _T_747 = or(_T_740, _T_746)
node _T_748 = and(_T_734, _T_747)
node _T_749 = or(UInt<1>(0h0), _T_748)
node _T_750 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_751 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_752 = and(_T_750, _T_751)
node _T_753 = or(UInt<1>(0h0), _T_752)
node _T_754 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_755 = cvt(_T_754)
node _T_756 = and(_T_755, asSInt(UInt<14>(0h2000)))
node _T_757 = asSInt(_T_756)
node _T_758 = eq(_T_757, asSInt(UInt<1>(0h0)))
node _T_759 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_760 = cvt(_T_759)
node _T_761 = and(_T_760, asSInt(UInt<13>(0h1000)))
node _T_762 = asSInt(_T_761)
node _T_763 = eq(_T_762, asSInt(UInt<1>(0h0)))
node _T_764 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_765 = cvt(_T_764)
node _T_766 = and(_T_765, asSInt(UInt<18>(0h2f000)))
node _T_767 = asSInt(_T_766)
node _T_768 = eq(_T_767, asSInt(UInt<1>(0h0)))
node _T_769 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_770 = cvt(_T_769)
node _T_771 = and(_T_770, asSInt(UInt<17>(0h10000)))
node _T_772 = asSInt(_T_771)
node _T_773 = eq(_T_772, asSInt(UInt<1>(0h0)))
node _T_774 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_775 = cvt(_T_774)
node _T_776 = and(_T_775, asSInt(UInt<13>(0h1000)))
node _T_777 = asSInt(_T_776)
node _T_778 = eq(_T_777, asSInt(UInt<1>(0h0)))
node _T_779 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_780 = cvt(_T_779)
node _T_781 = and(_T_780, asSInt(UInt<27>(0h4000000)))
node _T_782 = asSInt(_T_781)
node _T_783 = eq(_T_782, asSInt(UInt<1>(0h0)))
node _T_784 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_785 = cvt(_T_784)
node _T_786 = and(_T_785, asSInt(UInt<13>(0h1000)))
node _T_787 = asSInt(_T_786)
node _T_788 = eq(_T_787, asSInt(UInt<1>(0h0)))
node _T_789 = or(_T_758, _T_763)
node _T_790 = or(_T_789, _T_768)
node _T_791 = or(_T_790, _T_773)
node _T_792 = or(_T_791, _T_778)
node _T_793 = or(_T_792, _T_783)
node _T_794 = or(_T_793, _T_788)
node _T_795 = and(_T_753, _T_794)
node _T_796 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_797 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_798 = cvt(_T_797)
node _T_799 = and(_T_798, asSInt(UInt<17>(0h10000)))
node _T_800 = asSInt(_T_799)
node _T_801 = eq(_T_800, asSInt(UInt<1>(0h0)))
node _T_802 = and(_T_796, _T_801)
node _T_803 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_804 = leq(io.in.a.bits.size, UInt<3>(0h4))
node _T_805 = and(_T_803, _T_804)
node _T_806 = or(UInt<1>(0h0), _T_805)
node _T_807 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_808 = cvt(_T_807)
node _T_809 = and(_T_808, asSInt(UInt<17>(0h10000)))
node _T_810 = asSInt(_T_809)
node _T_811 = eq(_T_810, asSInt(UInt<1>(0h0)))
node _T_812 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_813 = cvt(_T_812)
node _T_814 = and(_T_813, asSInt(UInt<29>(0h10000000)))
node _T_815 = asSInt(_T_814)
node _T_816 = eq(_T_815, asSInt(UInt<1>(0h0)))
node _T_817 = or(_T_811, _T_816)
node _T_818 = and(_T_806, _T_817)
node _T_819 = or(UInt<1>(0h0), _T_795)
node _T_820 = or(_T_819, _T_802)
node _T_821 = or(_T_820, _T_818)
node _T_822 = and(_T_749, _T_821)
node _T_823 = asUInt(reset)
node _T_824 = eq(_T_823, UInt<1>(0h0))
when _T_824 :
node _T_825 = eq(_T_822, UInt<1>(0h0))
when _T_825 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_822, UInt<1>(0h1), "") : assert_36
node _T_826 = asUInt(reset)
node _T_827 = eq(_T_826, UInt<1>(0h0))
when _T_827 :
node _T_828 = eq(source_ok, UInt<1>(0h0))
when _T_828 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_829 = asUInt(reset)
node _T_830 = eq(_T_829, UInt<1>(0h0))
when _T_830 :
node _T_831 = eq(is_aligned, UInt<1>(0h0))
when _T_831 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_832 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_833 = asUInt(reset)
node _T_834 = eq(_T_833, UInt<1>(0h0))
when _T_834 :
node _T_835 = eq(_T_832, UInt<1>(0h0))
when _T_835 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_832, UInt<1>(0h1), "") : assert_39
node _T_836 = eq(io.in.a.bits.mask, mask)
node _T_837 = asUInt(reset)
node _T_838 = eq(_T_837, UInt<1>(0h0))
when _T_838 :
node _T_839 = eq(_T_836, UInt<1>(0h0))
when _T_839 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_836, UInt<1>(0h1), "") : assert_40
node _T_840 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_840 :
node _T_841 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_842 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_843 = and(_T_841, _T_842)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 5, 0)
node _T_844 = shr(io.in.a.bits.source, 6)
node _T_845 = eq(_T_844, UInt<1>(0h1))
node _T_846 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_847 = and(_T_845, _T_846)
node _T_848 = leq(uncommonBits_14, UInt<6>(0h3f))
node _T_849 = and(_T_847, _T_848)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 5, 0)
node _T_850 = shr(io.in.a.bits.source, 6)
node _T_851 = eq(_T_850, UInt<1>(0h0))
node _T_852 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_853 = and(_T_851, _T_852)
node _T_854 = leq(uncommonBits_15, UInt<6>(0h3f))
node _T_855 = and(_T_853, _T_854)
node _T_856 = or(_T_849, _T_855)
node _T_857 = and(_T_843, _T_856)
node _T_858 = or(UInt<1>(0h0), _T_857)
node _T_859 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_860 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_861 = and(_T_859, _T_860)
node _T_862 = or(UInt<1>(0h0), _T_861)
node _T_863 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_864 = cvt(_T_863)
node _T_865 = and(_T_864, asSInt(UInt<14>(0h2000)))
node _T_866 = asSInt(_T_865)
node _T_867 = eq(_T_866, asSInt(UInt<1>(0h0)))
node _T_868 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_869 = cvt(_T_868)
node _T_870 = and(_T_869, asSInt(UInt<13>(0h1000)))
node _T_871 = asSInt(_T_870)
node _T_872 = eq(_T_871, asSInt(UInt<1>(0h0)))
node _T_873 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_874 = cvt(_T_873)
node _T_875 = and(_T_874, asSInt(UInt<18>(0h2f000)))
node _T_876 = asSInt(_T_875)
node _T_877 = eq(_T_876, asSInt(UInt<1>(0h0)))
node _T_878 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_879 = cvt(_T_878)
node _T_880 = and(_T_879, asSInt(UInt<17>(0h10000)))
node _T_881 = asSInt(_T_880)
node _T_882 = eq(_T_881, asSInt(UInt<1>(0h0)))
node _T_883 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_884 = cvt(_T_883)
node _T_885 = and(_T_884, asSInt(UInt<13>(0h1000)))
node _T_886 = asSInt(_T_885)
node _T_887 = eq(_T_886, asSInt(UInt<1>(0h0)))
node _T_888 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_889 = cvt(_T_888)
node _T_890 = and(_T_889, asSInt(UInt<27>(0h4000000)))
node _T_891 = asSInt(_T_890)
node _T_892 = eq(_T_891, asSInt(UInt<1>(0h0)))
node _T_893 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_894 = cvt(_T_893)
node _T_895 = and(_T_894, asSInt(UInt<13>(0h1000)))
node _T_896 = asSInt(_T_895)
node _T_897 = eq(_T_896, asSInt(UInt<1>(0h0)))
node _T_898 = or(_T_867, _T_872)
node _T_899 = or(_T_898, _T_877)
node _T_900 = or(_T_899, _T_882)
node _T_901 = or(_T_900, _T_887)
node _T_902 = or(_T_901, _T_892)
node _T_903 = or(_T_902, _T_897)
node _T_904 = and(_T_862, _T_903)
node _T_905 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_906 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_907 = cvt(_T_906)
node _T_908 = and(_T_907, asSInt(UInt<17>(0h10000)))
node _T_909 = asSInt(_T_908)
node _T_910 = eq(_T_909, asSInt(UInt<1>(0h0)))
node _T_911 = and(_T_905, _T_910)
node _T_912 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_913 = leq(io.in.a.bits.size, UInt<3>(0h4))
node _T_914 = and(_T_912, _T_913)
node _T_915 = or(UInt<1>(0h0), _T_914)
node _T_916 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_917 = cvt(_T_916)
node _T_918 = and(_T_917, asSInt(UInt<17>(0h10000)))
node _T_919 = asSInt(_T_918)
node _T_920 = eq(_T_919, asSInt(UInt<1>(0h0)))
node _T_921 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_922 = cvt(_T_921)
node _T_923 = and(_T_922, asSInt(UInt<29>(0h10000000)))
node _T_924 = asSInt(_T_923)
node _T_925 = eq(_T_924, asSInt(UInt<1>(0h0)))
node _T_926 = or(_T_920, _T_925)
node _T_927 = and(_T_915, _T_926)
node _T_928 = or(UInt<1>(0h0), _T_904)
node _T_929 = or(_T_928, _T_911)
node _T_930 = or(_T_929, _T_927)
node _T_931 = and(_T_858, _T_930)
node _T_932 = asUInt(reset)
node _T_933 = eq(_T_932, UInt<1>(0h0))
when _T_933 :
node _T_934 = eq(_T_931, UInt<1>(0h0))
when _T_934 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_931, UInt<1>(0h1), "") : assert_41
node _T_935 = asUInt(reset)
node _T_936 = eq(_T_935, UInt<1>(0h0))
when _T_936 :
node _T_937 = eq(source_ok, UInt<1>(0h0))
when _T_937 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_938 = asUInt(reset)
node _T_939 = eq(_T_938, UInt<1>(0h0))
when _T_939 :
node _T_940 = eq(is_aligned, UInt<1>(0h0))
when _T_940 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_941 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_942 = asUInt(reset)
node _T_943 = eq(_T_942, UInt<1>(0h0))
when _T_943 :
node _T_944 = eq(_T_941, UInt<1>(0h0))
when _T_944 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_941, UInt<1>(0h1), "") : assert_44
node _T_945 = eq(io.in.a.bits.mask, mask)
node _T_946 = asUInt(reset)
node _T_947 = eq(_T_946, UInt<1>(0h0))
when _T_947 :
node _T_948 = eq(_T_945, UInt<1>(0h0))
when _T_948 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_945, UInt<1>(0h1), "") : assert_45
node _T_949 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_949 :
node _T_950 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_951 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_952 = and(_T_950, _T_951)
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 5, 0)
node _T_953 = shr(io.in.a.bits.source, 6)
node _T_954 = eq(_T_953, UInt<1>(0h1))
node _T_955 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_956 = and(_T_954, _T_955)
node _T_957 = leq(uncommonBits_16, UInt<6>(0h3f))
node _T_958 = and(_T_956, _T_957)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 5, 0)
node _T_959 = shr(io.in.a.bits.source, 6)
node _T_960 = eq(_T_959, UInt<1>(0h0))
node _T_961 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_962 = and(_T_960, _T_961)
node _T_963 = leq(uncommonBits_17, UInt<6>(0h3f))
node _T_964 = and(_T_962, _T_963)
node _T_965 = or(_T_958, _T_964)
node _T_966 = and(_T_952, _T_965)
node _T_967 = or(UInt<1>(0h0), _T_966)
node _T_968 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_969 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_970 = and(_T_968, _T_969)
node _T_971 = or(UInt<1>(0h0), _T_970)
node _T_972 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_973 = cvt(_T_972)
node _T_974 = and(_T_973, asSInt(UInt<13>(0h1000)))
node _T_975 = asSInt(_T_974)
node _T_976 = eq(_T_975, asSInt(UInt<1>(0h0)))
node _T_977 = and(_T_971, _T_976)
node _T_978 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_979 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_980 = cvt(_T_979)
node _T_981 = and(_T_980, asSInt(UInt<14>(0h2000)))
node _T_982 = asSInt(_T_981)
node _T_983 = eq(_T_982, asSInt(UInt<1>(0h0)))
node _T_984 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_985 = cvt(_T_984)
node _T_986 = and(_T_985, asSInt(UInt<17>(0h10000)))
node _T_987 = asSInt(_T_986)
node _T_988 = eq(_T_987, asSInt(UInt<1>(0h0)))
node _T_989 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_990 = cvt(_T_989)
node _T_991 = and(_T_990, asSInt(UInt<18>(0h2f000)))
node _T_992 = asSInt(_T_991)
node _T_993 = eq(_T_992, asSInt(UInt<1>(0h0)))
node _T_994 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_995 = cvt(_T_994)
node _T_996 = and(_T_995, asSInt(UInt<17>(0h10000)))
node _T_997 = asSInt(_T_996)
node _T_998 = eq(_T_997, asSInt(UInt<1>(0h0)))
node _T_999 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1000 = cvt(_T_999)
node _T_1001 = and(_T_1000, asSInt(UInt<13>(0h1000)))
node _T_1002 = asSInt(_T_1001)
node _T_1003 = eq(_T_1002, asSInt(UInt<1>(0h0)))
node _T_1004 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1005 = cvt(_T_1004)
node _T_1006 = and(_T_1005, asSInt(UInt<27>(0h4000000)))
node _T_1007 = asSInt(_T_1006)
node _T_1008 = eq(_T_1007, asSInt(UInt<1>(0h0)))
node _T_1009 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1010 = cvt(_T_1009)
node _T_1011 = and(_T_1010, asSInt(UInt<13>(0h1000)))
node _T_1012 = asSInt(_T_1011)
node _T_1013 = eq(_T_1012, asSInt(UInt<1>(0h0)))
node _T_1014 = or(_T_983, _T_988)
node _T_1015 = or(_T_1014, _T_993)
node _T_1016 = or(_T_1015, _T_998)
node _T_1017 = or(_T_1016, _T_1003)
node _T_1018 = or(_T_1017, _T_1008)
node _T_1019 = or(_T_1018, _T_1013)
node _T_1020 = and(_T_978, _T_1019)
node _T_1021 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1022 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_1023 = and(_T_1021, _T_1022)
node _T_1024 = or(UInt<1>(0h0), _T_1023)
node _T_1025 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_1026 = cvt(_T_1025)
node _T_1027 = and(_T_1026, asSInt(UInt<17>(0h10000)))
node _T_1028 = asSInt(_T_1027)
node _T_1029 = eq(_T_1028, asSInt(UInt<1>(0h0)))
node _T_1030 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_1031 = cvt(_T_1030)
node _T_1032 = and(_T_1031, asSInt(UInt<29>(0h10000000)))
node _T_1033 = asSInt(_T_1032)
node _T_1034 = eq(_T_1033, asSInt(UInt<1>(0h0)))
node _T_1035 = or(_T_1029, _T_1034)
node _T_1036 = and(_T_1024, _T_1035)
node _T_1037 = or(UInt<1>(0h0), _T_977)
node _T_1038 = or(_T_1037, _T_1020)
node _T_1039 = or(_T_1038, _T_1036)
node _T_1040 = and(_T_967, _T_1039)
node _T_1041 = asUInt(reset)
node _T_1042 = eq(_T_1041, UInt<1>(0h0))
when _T_1042 :
node _T_1043 = eq(_T_1040, UInt<1>(0h0))
when _T_1043 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_1040, UInt<1>(0h1), "") : assert_46
node _T_1044 = asUInt(reset)
node _T_1045 = eq(_T_1044, UInt<1>(0h0))
when _T_1045 :
node _T_1046 = eq(source_ok, UInt<1>(0h0))
when _T_1046 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_1047 = asUInt(reset)
node _T_1048 = eq(_T_1047, UInt<1>(0h0))
when _T_1048 :
node _T_1049 = eq(is_aligned, UInt<1>(0h0))
when _T_1049 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_1050 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_1051 = asUInt(reset)
node _T_1052 = eq(_T_1051, UInt<1>(0h0))
when _T_1052 :
node _T_1053 = eq(_T_1050, UInt<1>(0h0))
when _T_1053 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_1050, UInt<1>(0h1), "") : assert_49
node _T_1054 = eq(io.in.a.bits.mask, mask)
node _T_1055 = asUInt(reset)
node _T_1056 = eq(_T_1055, UInt<1>(0h0))
when _T_1056 :
node _T_1057 = eq(_T_1054, UInt<1>(0h0))
when _T_1057 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_1054, UInt<1>(0h1), "") : assert_50
node _T_1058 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1059 = asUInt(reset)
node _T_1060 = eq(_T_1059, UInt<1>(0h0))
when _T_1060 :
node _T_1061 = eq(_T_1058, UInt<1>(0h0))
when _T_1061 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_1058, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_1062 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1063 = asUInt(reset)
node _T_1064 = eq(_T_1063, UInt<1>(0h0))
when _T_1064 :
node _T_1065 = eq(_T_1062, UInt<1>(0h0))
when _T_1065 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_1062, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_2 = or(io.in.d.bits.source, UInt<6>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 5, 0)
node _source_ok_T_12 = shr(io.in.d.bits.source, 6)
node _source_ok_T_13 = eq(_source_ok_T_12, UInt<1>(0h1))
node _source_ok_T_14 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_15 = and(_source_ok_T_13, _source_ok_T_14)
node _source_ok_T_16 = leq(source_ok_uncommonBits_2, UInt<6>(0h3f))
node _source_ok_T_17 = and(_source_ok_T_15, _source_ok_T_16)
node _source_ok_uncommonBits_T_3 = or(io.in.d.bits.source, UInt<6>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 5, 0)
node _source_ok_T_18 = shr(io.in.d.bits.source, 6)
node _source_ok_T_19 = eq(_source_ok_T_18, UInt<1>(0h0))
node _source_ok_T_20 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_21 = and(_source_ok_T_19, _source_ok_T_20)
node _source_ok_T_22 = leq(source_ok_uncommonBits_3, UInt<6>(0h3f))
node _source_ok_T_23 = and(_source_ok_T_21, _source_ok_T_22)
wire _source_ok_WIRE_1 : UInt<1>[2]
connect _source_ok_WIRE_1[0], _source_ok_T_17
connect _source_ok_WIRE_1[1], _source_ok_T_23
node source_ok_1 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node sink_ok = lt(io.in.d.bits.sink, UInt<5>(0h10))
node _T_1066 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1066 :
node _T_1067 = asUInt(reset)
node _T_1068 = eq(_T_1067, UInt<1>(0h0))
when _T_1068 :
node _T_1069 = eq(source_ok_1, UInt<1>(0h0))
when _T_1069 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_1070 = geq(io.in.d.bits.size, UInt<3>(0h4))
node _T_1071 = asUInt(reset)
node _T_1072 = eq(_T_1071, UInt<1>(0h0))
when _T_1072 :
node _T_1073 = eq(_T_1070, UInt<1>(0h0))
when _T_1073 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1070, UInt<1>(0h1), "") : assert_54
node _T_1074 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1075 = asUInt(reset)
node _T_1076 = eq(_T_1075, UInt<1>(0h0))
when _T_1076 :
node _T_1077 = eq(_T_1074, UInt<1>(0h0))
when _T_1077 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1074, UInt<1>(0h1), "") : assert_55
node _T_1078 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1079 = asUInt(reset)
node _T_1080 = eq(_T_1079, UInt<1>(0h0))
when _T_1080 :
node _T_1081 = eq(_T_1078, UInt<1>(0h0))
when _T_1081 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1078, UInt<1>(0h1), "") : assert_56
node _T_1082 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1083 = asUInt(reset)
node _T_1084 = eq(_T_1083, UInt<1>(0h0))
when _T_1084 :
node _T_1085 = eq(_T_1082, UInt<1>(0h0))
when _T_1085 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1082, UInt<1>(0h1), "") : assert_57
node _T_1086 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1086 :
node _T_1087 = asUInt(reset)
node _T_1088 = eq(_T_1087, UInt<1>(0h0))
when _T_1088 :
node _T_1089 = eq(source_ok_1, UInt<1>(0h0))
when _T_1089 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1090 = asUInt(reset)
node _T_1091 = eq(_T_1090, UInt<1>(0h0))
when _T_1091 :
node _T_1092 = eq(sink_ok, UInt<1>(0h0))
when _T_1092 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1093 = geq(io.in.d.bits.size, UInt<3>(0h4))
node _T_1094 = asUInt(reset)
node _T_1095 = eq(_T_1094, UInt<1>(0h0))
when _T_1095 :
node _T_1096 = eq(_T_1093, UInt<1>(0h0))
when _T_1096 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1093, UInt<1>(0h1), "") : assert_60
node _T_1097 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1098 = asUInt(reset)
node _T_1099 = eq(_T_1098, UInt<1>(0h0))
when _T_1099 :
node _T_1100 = eq(_T_1097, UInt<1>(0h0))
when _T_1100 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1097, UInt<1>(0h1), "") : assert_61
node _T_1101 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1102 = asUInt(reset)
node _T_1103 = eq(_T_1102, UInt<1>(0h0))
when _T_1103 :
node _T_1104 = eq(_T_1101, UInt<1>(0h0))
when _T_1104 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1101, UInt<1>(0h1), "") : assert_62
node _T_1105 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1106 = asUInt(reset)
node _T_1107 = eq(_T_1106, UInt<1>(0h0))
when _T_1107 :
node _T_1108 = eq(_T_1105, UInt<1>(0h0))
when _T_1108 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1105, UInt<1>(0h1), "") : assert_63
node _T_1109 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1110 = or(UInt<1>(0h1), _T_1109)
node _T_1111 = asUInt(reset)
node _T_1112 = eq(_T_1111, UInt<1>(0h0))
when _T_1112 :
node _T_1113 = eq(_T_1110, UInt<1>(0h0))
when _T_1113 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1110, UInt<1>(0h1), "") : assert_64
node _T_1114 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1114 :
node _T_1115 = asUInt(reset)
node _T_1116 = eq(_T_1115, UInt<1>(0h0))
when _T_1116 :
node _T_1117 = eq(source_ok_1, UInt<1>(0h0))
when _T_1117 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1118 = asUInt(reset)
node _T_1119 = eq(_T_1118, UInt<1>(0h0))
when _T_1119 :
node _T_1120 = eq(sink_ok, UInt<1>(0h0))
when _T_1120 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1121 = geq(io.in.d.bits.size, UInt<3>(0h4))
node _T_1122 = asUInt(reset)
node _T_1123 = eq(_T_1122, UInt<1>(0h0))
when _T_1123 :
node _T_1124 = eq(_T_1121, UInt<1>(0h0))
when _T_1124 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1121, UInt<1>(0h1), "") : assert_67
node _T_1125 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1126 = asUInt(reset)
node _T_1127 = eq(_T_1126, UInt<1>(0h0))
when _T_1127 :
node _T_1128 = eq(_T_1125, UInt<1>(0h0))
when _T_1128 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1125, UInt<1>(0h1), "") : assert_68
node _T_1129 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1130 = asUInt(reset)
node _T_1131 = eq(_T_1130, UInt<1>(0h0))
when _T_1131 :
node _T_1132 = eq(_T_1129, UInt<1>(0h0))
when _T_1132 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1129, UInt<1>(0h1), "") : assert_69
node _T_1133 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1134 = or(_T_1133, io.in.d.bits.corrupt)
node _T_1135 = asUInt(reset)
node _T_1136 = eq(_T_1135, UInt<1>(0h0))
when _T_1136 :
node _T_1137 = eq(_T_1134, UInt<1>(0h0))
when _T_1137 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1134, UInt<1>(0h1), "") : assert_70
node _T_1138 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1139 = or(UInt<1>(0h1), _T_1138)
node _T_1140 = asUInt(reset)
node _T_1141 = eq(_T_1140, UInt<1>(0h0))
when _T_1141 :
node _T_1142 = eq(_T_1139, UInt<1>(0h0))
when _T_1142 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1139, UInt<1>(0h1), "") : assert_71
node _T_1143 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1143 :
node _T_1144 = asUInt(reset)
node _T_1145 = eq(_T_1144, UInt<1>(0h0))
when _T_1145 :
node _T_1146 = eq(source_ok_1, UInt<1>(0h0))
when _T_1146 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1147 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1148 = asUInt(reset)
node _T_1149 = eq(_T_1148, UInt<1>(0h0))
when _T_1149 :
node _T_1150 = eq(_T_1147, UInt<1>(0h0))
when _T_1150 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1147, UInt<1>(0h1), "") : assert_73
node _T_1151 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1152 = asUInt(reset)
node _T_1153 = eq(_T_1152, UInt<1>(0h0))
when _T_1153 :
node _T_1154 = eq(_T_1151, UInt<1>(0h0))
when _T_1154 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1151, UInt<1>(0h1), "") : assert_74
node _T_1155 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1156 = or(UInt<1>(0h1), _T_1155)
node _T_1157 = asUInt(reset)
node _T_1158 = eq(_T_1157, UInt<1>(0h0))
when _T_1158 :
node _T_1159 = eq(_T_1156, UInt<1>(0h0))
when _T_1159 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1156, UInt<1>(0h1), "") : assert_75
node _T_1160 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1160 :
node _T_1161 = asUInt(reset)
node _T_1162 = eq(_T_1161, UInt<1>(0h0))
when _T_1162 :
node _T_1163 = eq(source_ok_1, UInt<1>(0h0))
when _T_1163 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1164 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1165 = asUInt(reset)
node _T_1166 = eq(_T_1165, UInt<1>(0h0))
when _T_1166 :
node _T_1167 = eq(_T_1164, UInt<1>(0h0))
when _T_1167 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1164, UInt<1>(0h1), "") : assert_77
node _T_1168 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1169 = or(_T_1168, io.in.d.bits.corrupt)
node _T_1170 = asUInt(reset)
node _T_1171 = eq(_T_1170, UInt<1>(0h0))
when _T_1171 :
node _T_1172 = eq(_T_1169, UInt<1>(0h0))
when _T_1172 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1169, UInt<1>(0h1), "") : assert_78
node _T_1173 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1174 = or(UInt<1>(0h1), _T_1173)
node _T_1175 = asUInt(reset)
node _T_1176 = eq(_T_1175, UInt<1>(0h0))
when _T_1176 :
node _T_1177 = eq(_T_1174, UInt<1>(0h0))
when _T_1177 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1174, UInt<1>(0h1), "") : assert_79
node _T_1178 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1178 :
node _T_1179 = asUInt(reset)
node _T_1180 = eq(_T_1179, UInt<1>(0h0))
when _T_1180 :
node _T_1181 = eq(source_ok_1, UInt<1>(0h0))
when _T_1181 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1182 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1183 = asUInt(reset)
node _T_1184 = eq(_T_1183, UInt<1>(0h0))
when _T_1184 :
node _T_1185 = eq(_T_1182, UInt<1>(0h0))
when _T_1185 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1182, UInt<1>(0h1), "") : assert_81
node _T_1186 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1187 = asUInt(reset)
node _T_1188 = eq(_T_1187, UInt<1>(0h0))
when _T_1188 :
node _T_1189 = eq(_T_1186, UInt<1>(0h0))
when _T_1189 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1186, UInt<1>(0h1), "") : assert_82
node _T_1190 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1191 = or(UInt<1>(0h1), _T_1190)
node _T_1192 = asUInt(reset)
node _T_1193 = eq(_T_1192, UInt<1>(0h0))
when _T_1193 :
node _T_1194 = eq(_T_1191, UInt<1>(0h0))
when _T_1194 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1191, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<128>(0h0)
connect _WIRE.bits.mask, UInt<16>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<7>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_1195 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_1196 = asUInt(reset)
node _T_1197 = eq(_T_1196, UInt<1>(0h0))
when _T_1197 :
node _T_1198 = eq(_T_1195, UInt<1>(0h0))
when _T_1198 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1195, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<128>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<7>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_1199 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_1200 = asUInt(reset)
node _T_1201 = eq(_T_1200, UInt<1>(0h0))
when _T_1201 :
node _T_1202 = eq(_T_1199, UInt<1>(0h0))
when _T_1202 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1199, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _WIRE_4.bits.sink, UInt<4>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1203 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1204 = asUInt(reset)
node _T_1205 = eq(_T_1204, UInt<1>(0h0))
when _T_1205 :
node _T_1206 = eq(_T_1203, UInt<1>(0h0))
when _T_1206 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1203, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 4)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<8>, clock, reset, UInt<8>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1207 = eq(a_first, UInt<1>(0h0))
node _T_1208 = and(io.in.a.valid, _T_1207)
when _T_1208 :
node _T_1209 = eq(io.in.a.bits.opcode, opcode)
node _T_1210 = asUInt(reset)
node _T_1211 = eq(_T_1210, UInt<1>(0h0))
when _T_1211 :
node _T_1212 = eq(_T_1209, UInt<1>(0h0))
when _T_1212 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1209, UInt<1>(0h1), "") : assert_87
node _T_1213 = eq(io.in.a.bits.param, param)
node _T_1214 = asUInt(reset)
node _T_1215 = eq(_T_1214, UInt<1>(0h0))
when _T_1215 :
node _T_1216 = eq(_T_1213, UInt<1>(0h0))
when _T_1216 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1213, UInt<1>(0h1), "") : assert_88
node _T_1217 = eq(io.in.a.bits.size, size)
node _T_1218 = asUInt(reset)
node _T_1219 = eq(_T_1218, UInt<1>(0h0))
when _T_1219 :
node _T_1220 = eq(_T_1217, UInt<1>(0h0))
when _T_1220 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1217, UInt<1>(0h1), "") : assert_89
node _T_1221 = eq(io.in.a.bits.source, source)
node _T_1222 = asUInt(reset)
node _T_1223 = eq(_T_1222, UInt<1>(0h0))
when _T_1223 :
node _T_1224 = eq(_T_1221, UInt<1>(0h0))
when _T_1224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1221, UInt<1>(0h1), "") : assert_90
node _T_1225 = eq(io.in.a.bits.address, address)
node _T_1226 = asUInt(reset)
node _T_1227 = eq(_T_1226, UInt<1>(0h0))
when _T_1227 :
node _T_1228 = eq(_T_1225, UInt<1>(0h0))
when _T_1228 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1225, UInt<1>(0h1), "") : assert_91
node _T_1229 = and(io.in.a.ready, io.in.a.valid)
node _T_1230 = and(_T_1229, a_first)
when _T_1230 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 4)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<8>, clock, reset, UInt<8>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1231 = eq(d_first, UInt<1>(0h0))
node _T_1232 = and(io.in.d.valid, _T_1231)
when _T_1232 :
node _T_1233 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1234 = asUInt(reset)
node _T_1235 = eq(_T_1234, UInt<1>(0h0))
when _T_1235 :
node _T_1236 = eq(_T_1233, UInt<1>(0h0))
when _T_1236 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1233, UInt<1>(0h1), "") : assert_92
node _T_1237 = eq(io.in.d.bits.param, param_1)
node _T_1238 = asUInt(reset)
node _T_1239 = eq(_T_1238, UInt<1>(0h0))
when _T_1239 :
node _T_1240 = eq(_T_1237, UInt<1>(0h0))
when _T_1240 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1237, UInt<1>(0h1), "") : assert_93
node _T_1241 = eq(io.in.d.bits.size, size_1)
node _T_1242 = asUInt(reset)
node _T_1243 = eq(_T_1242, UInt<1>(0h0))
when _T_1243 :
node _T_1244 = eq(_T_1241, UInt<1>(0h0))
when _T_1244 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1241, UInt<1>(0h1), "") : assert_94
node _T_1245 = eq(io.in.d.bits.source, source_1)
node _T_1246 = asUInt(reset)
node _T_1247 = eq(_T_1246, UInt<1>(0h0))
when _T_1247 :
node _T_1248 = eq(_T_1245, UInt<1>(0h0))
when _T_1248 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1245, UInt<1>(0h1), "") : assert_95
node _T_1249 = eq(io.in.d.bits.sink, sink)
node _T_1250 = asUInt(reset)
node _T_1251 = eq(_T_1250, UInt<1>(0h0))
when _T_1251 :
node _T_1252 = eq(_T_1249, UInt<1>(0h0))
when _T_1252 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1249, UInt<1>(0h1), "") : assert_96
node _T_1253 = eq(io.in.d.bits.denied, denied)
node _T_1254 = asUInt(reset)
node _T_1255 = eq(_T_1254, UInt<1>(0h0))
when _T_1255 :
node _T_1256 = eq(_T_1253, UInt<1>(0h0))
when _T_1256 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1253, UInt<1>(0h1), "") : assert_97
node _T_1257 = and(io.in.d.ready, io.in.d.valid)
node _T_1258 = and(_T_1257, d_first)
when _T_1258 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<128>, clock, reset, UInt<128>(0h0)
regreset inflight_opcodes : UInt<512>, clock, reset, UInt<512>(0h0)
regreset inflight_sizes : UInt<1024>, clock, reset, UInt<1024>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 4)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 4)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<128>
connect a_set, UInt<128>(0h0)
wire a_set_wo_ready : UInt<128>
connect a_set_wo_ready, UInt<128>(0h0)
wire a_opcodes_set : UInt<512>
connect a_opcodes_set, UInt<512>(0h0)
wire a_sizes_set : UInt<1024>
connect a_sizes_set, UInt<1024>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<8>
connect a_size_lookup, UInt<8>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<5>
connect a_sizes_set_interm, UInt<5>(0h0)
node _T_1259 = and(io.in.a.valid, a_first_1)
node _T_1260 = and(_T_1259, UInt<1>(0h1))
when _T_1260 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1261 = and(io.in.a.ready, io.in.a.valid)
node _T_1262 = and(_T_1261, a_first_1)
node _T_1263 = and(_T_1262, UInt<1>(0h1))
when _T_1263 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1264 = dshr(inflight, io.in.a.bits.source)
node _T_1265 = bits(_T_1264, 0, 0)
node _T_1266 = eq(_T_1265, UInt<1>(0h0))
node _T_1267 = asUInt(reset)
node _T_1268 = eq(_T_1267, UInt<1>(0h0))
when _T_1268 :
node _T_1269 = eq(_T_1266, UInt<1>(0h0))
when _T_1269 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1266, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<128>
connect d_clr, UInt<128>(0h0)
wire d_clr_wo_ready : UInt<128>
connect d_clr_wo_ready, UInt<128>(0h0)
wire d_opcodes_clr : UInt<512>
connect d_opcodes_clr, UInt<512>(0h0)
wire d_sizes_clr : UInt<1024>
connect d_sizes_clr, UInt<1024>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1270 = and(io.in.d.valid, d_first_1)
node _T_1271 = and(_T_1270, UInt<1>(0h1))
node _T_1272 = eq(d_release_ack, UInt<1>(0h0))
node _T_1273 = and(_T_1271, _T_1272)
when _T_1273 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1274 = and(io.in.d.ready, io.in.d.valid)
node _T_1275 = and(_T_1274, d_first_1)
node _T_1276 = and(_T_1275, UInt<1>(0h1))
node _T_1277 = eq(d_release_ack, UInt<1>(0h0))
node _T_1278 = and(_T_1276, _T_1277)
when _T_1278 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1279 = and(io.in.d.valid, d_first_1)
node _T_1280 = and(_T_1279, UInt<1>(0h1))
node _T_1281 = eq(d_release_ack, UInt<1>(0h0))
node _T_1282 = and(_T_1280, _T_1281)
when _T_1282 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1283 = dshr(inflight, io.in.d.bits.source)
node _T_1284 = bits(_T_1283, 0, 0)
node _T_1285 = or(_T_1284, same_cycle_resp)
node _T_1286 = asUInt(reset)
node _T_1287 = eq(_T_1286, UInt<1>(0h0))
when _T_1287 :
node _T_1288 = eq(_T_1285, UInt<1>(0h0))
when _T_1288 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1285, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1289 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1290 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1291 = or(_T_1289, _T_1290)
node _T_1292 = asUInt(reset)
node _T_1293 = eq(_T_1292, UInt<1>(0h0))
when _T_1293 :
node _T_1294 = eq(_T_1291, UInt<1>(0h0))
when _T_1294 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1291, UInt<1>(0h1), "") : assert_100
node _T_1295 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1296 = asUInt(reset)
node _T_1297 = eq(_T_1296, UInt<1>(0h0))
when _T_1297 :
node _T_1298 = eq(_T_1295, UInt<1>(0h0))
when _T_1298 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1295, UInt<1>(0h1), "") : assert_101
else :
node _T_1299 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1300 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1301 = or(_T_1299, _T_1300)
node _T_1302 = asUInt(reset)
node _T_1303 = eq(_T_1302, UInt<1>(0h0))
when _T_1303 :
node _T_1304 = eq(_T_1301, UInt<1>(0h0))
when _T_1304 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1301, UInt<1>(0h1), "") : assert_102
node _T_1305 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1306 = asUInt(reset)
node _T_1307 = eq(_T_1306, UInt<1>(0h0))
when _T_1307 :
node _T_1308 = eq(_T_1305, UInt<1>(0h0))
when _T_1308 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1305, UInt<1>(0h1), "") : assert_103
node _T_1309 = and(io.in.d.valid, d_first_1)
node _T_1310 = and(_T_1309, a_first_1)
node _T_1311 = and(_T_1310, io.in.a.valid)
node _T_1312 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1313 = and(_T_1311, _T_1312)
node _T_1314 = eq(d_release_ack, UInt<1>(0h0))
node _T_1315 = and(_T_1313, _T_1314)
when _T_1315 :
node _T_1316 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1317 = or(_T_1316, io.in.a.ready)
node _T_1318 = asUInt(reset)
node _T_1319 = eq(_T_1318, UInt<1>(0h0))
when _T_1319 :
node _T_1320 = eq(_T_1317, UInt<1>(0h0))
when _T_1320 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1317, UInt<1>(0h1), "") : assert_104
node _T_1321 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_1322 = orr(a_set_wo_ready)
node _T_1323 = eq(_T_1322, UInt<1>(0h0))
node _T_1324 = or(_T_1321, _T_1323)
node _T_1325 = asUInt(reset)
node _T_1326 = eq(_T_1325, UInt<1>(0h0))
when _T_1326 :
node _T_1327 = eq(_T_1324, UInt<1>(0h0))
when _T_1327 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_1324, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_94
node _T_1328 = orr(inflight)
node _T_1329 = eq(_T_1328, UInt<1>(0h0))
node _T_1330 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1331 = or(_T_1329, _T_1330)
node _T_1332 = lt(watchdog, plusarg_reader.out)
node _T_1333 = or(_T_1331, _T_1332)
node _T_1334 = asUInt(reset)
node _T_1335 = eq(_T_1334, UInt<1>(0h0))
when _T_1335 :
node _T_1336 = eq(_T_1333, UInt<1>(0h0))
when _T_1336 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1333, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1337 = and(io.in.a.ready, io.in.a.valid)
node _T_1338 = and(io.in.d.ready, io.in.d.valid)
node _T_1339 = or(_T_1337, _T_1338)
when _T_1339 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<128>, clock, reset, UInt<128>(0h0)
regreset inflight_opcodes_1 : UInt<512>, clock, reset, UInt<512>(0h0)
regreset inflight_sizes_1 : UInt<1024>, clock, reset, UInt<1024>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<128>(0h0)
connect _c_first_WIRE.bits.address, UInt<32>(0h0)
connect _c_first_WIRE.bits.source, UInt<7>(0h0)
connect _c_first_WIRE.bits.size, UInt<4>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<128>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 4)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<8>, clock, reset, UInt<8>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 4)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<8>, clock, reset, UInt<8>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<128>
connect c_set, UInt<128>(0h0)
wire c_set_wo_ready : UInt<128>
connect c_set_wo_ready, UInt<128>(0h0)
wire c_opcodes_set : UInt<512>
connect c_opcodes_set, UInt<512>(0h0)
wire c_sizes_set : UInt<1024>
connect c_sizes_set, UInt<1024>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<8>
connect c_size_lookup, UInt<8>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<5>
connect c_sizes_set_interm, UInt<5>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<128>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<7>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1340 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<128>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<7>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1341 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_1342 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_1343 = and(_T_1341, _T_1342)
node _T_1344 = and(_T_1340, _T_1343)
when _T_1344 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<128>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<128>(0h0)
connect _WIRE_10.bits.address, UInt<32>(0h0)
connect _WIRE_10.bits.source, UInt<7>(0h0)
connect _WIRE_10.bits.size, UInt<4>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1345 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_1346 = and(_T_1345, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<128>(0h0)
connect _WIRE_12.bits.address, UInt<32>(0h0)
connect _WIRE_12.bits.source, UInt<7>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1347 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1348 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1349 = and(_T_1347, _T_1348)
node _T_1350 = and(_T_1346, _T_1349)
when _T_1350 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<128>(0h0)
connect _c_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<128>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<128>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<128>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<128>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<128>(0h0)
connect _WIRE_14.bits.address, UInt<32>(0h0)
connect _WIRE_14.bits.source, UInt<7>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1351 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_1352 = bits(_T_1351, 0, 0)
node _T_1353 = eq(_T_1352, UInt<1>(0h0))
node _T_1354 = asUInt(reset)
node _T_1355 = eq(_T_1354, UInt<1>(0h0))
when _T_1355 :
node _T_1356 = eq(_T_1353, UInt<1>(0h0))
when _T_1356 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_1353, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<128>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<128>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<128>
connect d_clr_1, UInt<128>(0h0)
wire d_clr_wo_ready_1 : UInt<128>
connect d_clr_wo_ready_1, UInt<128>(0h0)
wire d_opcodes_clr_1 : UInt<512>
connect d_opcodes_clr_1, UInt<512>(0h0)
wire d_sizes_clr_1 : UInt<1024>
connect d_sizes_clr_1, UInt<1024>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1357 = and(io.in.d.valid, d_first_2)
node _T_1358 = and(_T_1357, UInt<1>(0h1))
node _T_1359 = and(_T_1358, d_release_ack_1)
when _T_1359 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1360 = and(io.in.d.ready, io.in.d.valid)
node _T_1361 = and(_T_1360, d_first_2)
node _T_1362 = and(_T_1361, UInt<1>(0h1))
node _T_1363 = and(_T_1362, d_release_ack_1)
when _T_1363 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1364 = and(io.in.d.valid, d_first_2)
node _T_1365 = and(_T_1364, UInt<1>(0h1))
node _T_1366 = and(_T_1365, d_release_ack_1)
when _T_1366 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<128>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<128>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<128>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1367 = dshr(inflight_1, io.in.d.bits.source)
node _T_1368 = bits(_T_1367, 0, 0)
node _T_1369 = or(_T_1368, same_cycle_resp_1)
node _T_1370 = asUInt(reset)
node _T_1371 = eq(_T_1370, UInt<1>(0h0))
when _T_1371 :
node _T_1372 = eq(_T_1369, UInt<1>(0h0))
when _T_1372 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1369, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<128>(0h0)
connect _WIRE_16.bits.address, UInt<32>(0h0)
connect _WIRE_16.bits.source, UInt<7>(0h0)
connect _WIRE_16.bits.size, UInt<4>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1373 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_1374 = asUInt(reset)
node _T_1375 = eq(_T_1374, UInt<1>(0h0))
when _T_1375 :
node _T_1376 = eq(_T_1373, UInt<1>(0h0))
when _T_1376 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1373, UInt<1>(0h1), "") : assert_109
else :
node _T_1377 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1378 = asUInt(reset)
node _T_1379 = eq(_T_1378, UInt<1>(0h0))
when _T_1379 :
node _T_1380 = eq(_T_1377, UInt<1>(0h0))
when _T_1380 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1377, UInt<1>(0h1), "") : assert_110
node _T_1381 = and(io.in.d.valid, d_first_2)
node _T_1382 = and(_T_1381, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<128>(0h0)
connect _WIRE_18.bits.address, UInt<32>(0h0)
connect _WIRE_18.bits.source, UInt<7>(0h0)
connect _WIRE_18.bits.size, UInt<4>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1383 = and(_T_1382, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<128>(0h0)
connect _WIRE_20.bits.address, UInt<32>(0h0)
connect _WIRE_20.bits.source, UInt<7>(0h0)
connect _WIRE_20.bits.size, UInt<4>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1384 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_1385 = and(_T_1383, _T_1384)
node _T_1386 = and(_T_1385, d_release_ack_1)
node _T_1387 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1388 = and(_T_1386, _T_1387)
when _T_1388 :
node _T_1389 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<128>(0h0)
connect _WIRE_22.bits.address, UInt<32>(0h0)
connect _WIRE_22.bits.source, UInt<7>(0h0)
connect _WIRE_22.bits.size, UInt<4>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1390 = or(_T_1389, _WIRE_23.ready)
node _T_1391 = asUInt(reset)
node _T_1392 = eq(_T_1391, UInt<1>(0h0))
when _T_1392 :
node _T_1393 = eq(_T_1390, UInt<1>(0h0))
when _T_1393 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_1390, UInt<1>(0h1), "") : assert_111
node _T_1394 = orr(c_set_wo_ready)
when _T_1394 :
node _T_1395 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_1396 = asUInt(reset)
node _T_1397 = eq(_T_1396, UInt<1>(0h0))
when _T_1397 :
node _T_1398 = eq(_T_1395, UInt<1>(0h0))
when _T_1398 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_1395, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_95
node _T_1399 = orr(inflight_1)
node _T_1400 = eq(_T_1399, UInt<1>(0h0))
node _T_1401 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1402 = or(_T_1400, _T_1401)
node _T_1403 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1404 = or(_T_1402, _T_1403)
node _T_1405 = asUInt(reset)
node _T_1406 = eq(_T_1405, UInt<1>(0h0))
when _T_1406 :
node _T_1407 = eq(_T_1404, UInt<1>(0h0))
when _T_1407 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_1404, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<128>(0h0)
connect _WIRE_24.bits.address, UInt<32>(0h0)
connect _WIRE_24.bits.source, UInt<7>(0h0)
connect _WIRE_24.bits.size, UInt<4>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1408 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_1409 = and(io.in.d.ready, io.in.d.valid)
node _T_1410 = or(_T_1408, _T_1409)
when _T_1410 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_47( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [15:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [127:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [127:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [15:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [127:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [127:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [7:0] c_first_beats1_decode = 8'h0; // @[Edges.scala:220:59]
wire [7:0] c_first_beats1 = 8'h0; // @[Edges.scala:221:14]
wire [7:0] _c_first_count_T = 8'h0; // @[Edges.scala:234:27]
wire [7:0] c_first_count = 8'h0; // @[Edges.scala:234:25]
wire [7:0] _c_first_counter_T = 8'h0; // @[Edges.scala:236:21]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_10 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_14 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_16 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_20 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_22 = 1'h1; // @[Parameters.scala:57:20]
wire sink_ok = 1'h1; // @[Monitor.scala:309:31]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [7:0] c_first_counter1 = 8'hFF; // @[Edges.scala:230:28]
wire [8:0] _c_first_counter1_T = 9'h1FF; // @[Edges.scala:230:28]
wire [127:0] _c_first_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_first_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_first_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_first_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] c_set = 128'h0; // @[Monitor.scala:738:34]
wire [127:0] c_set_wo_ready = 128'h0; // @[Monitor.scala:739:34]
wire [127:0] _c_set_wo_ready_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_set_wo_ready_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_opcodes_set_interm_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_opcodes_set_interm_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_sizes_set_interm_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_sizes_set_interm_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_opcodes_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_opcodes_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_sizes_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_sizes_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_probe_ack_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_probe_ack_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_probe_ack_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_probe_ack_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _same_cycle_resp_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _same_cycle_resp_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _same_cycle_resp_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _same_cycle_resp_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _same_cycle_resp_WIRE_4_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _same_cycle_resp_WIRE_5_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [1027:0] _c_sizes_set_T_1 = 1028'h0; // @[Monitor.scala:768:52]
wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79]
wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77]
wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35]
wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35]
wire [1023:0] c_sizes_set = 1024'h0; // @[Monitor.scala:741:34]
wire [511:0] c_opcodes_set = 512'h0; // @[Monitor.scala:740:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_2 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_3 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[5:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T = io_in_a_bits_source_0[6]; // @[Monitor.scala:36:7]
wire _source_ok_T_6 = io_in_a_bits_source_0[6]; // @[Monitor.scala:36:7]
wire _source_ok_T_1 = _source_ok_T; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_3 = _source_ok_T_1; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_5 = _source_ok_T_3; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire [5:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[5:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_7 = ~_source_ok_T_6; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_9 = _source_ok_T_7; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_11 = _source_ok_T_9; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_11; // @[Parameters.scala:1138:31]
wire source_ok = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [3:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}]
wire [3:0] mask_sizeOH = {_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_sub_0_1 = |(io_in_a_bits_size_0[3:2]); // @[Misc.scala:206:21]
wire mask_sub_sub_sub_size = mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26]
wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_sub_acc_T = mask_sub_sub_sub_size & mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_size & mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size & mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_2_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size & mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_3_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_4 = mask_sub_size & mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_4_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_5 = mask_sub_size & mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_5_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_6 = mask_sub_size & mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_6_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_7 = mask_sub_size & mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_7_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_8 = mask_size & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_8 = mask_sub_4_1 | _mask_acc_T_8; // @[Misc.scala:215:{29,38}]
wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_9 = mask_size & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_9 = mask_sub_4_1 | _mask_acc_T_9; // @[Misc.scala:215:{29,38}]
wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_10 = mask_size & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_10 = mask_sub_5_1 | _mask_acc_T_10; // @[Misc.scala:215:{29,38}]
wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_11 = mask_size & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_11 = mask_sub_5_1 | _mask_acc_T_11; // @[Misc.scala:215:{29,38}]
wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_12 = mask_size & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_12 = mask_sub_6_1 | _mask_acc_T_12; // @[Misc.scala:215:{29,38}]
wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_13 = mask_size & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_13 = mask_sub_6_1 | _mask_acc_T_13; // @[Misc.scala:215:{29,38}]
wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_14 = mask_size & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_14 = mask_sub_7_1 | _mask_acc_T_14; // @[Misc.scala:215:{29,38}]
wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_15 = mask_size & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_15 = mask_sub_7_1 | _mask_acc_T_15; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo_lo = {mask_lo_lo_hi, mask_lo_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_lo_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo_hi = {mask_lo_hi_hi, mask_lo_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo_lo = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_lo_hi = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi_lo = {mask_hi_lo_hi, mask_hi_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_hi_lo = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi_hi = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi_hi = {mask_hi_hi_hi, mask_hi_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [15:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [5:0] uncommonBits = _uncommonBits_T[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_1 = _uncommonBits_T_1[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_2 = _uncommonBits_T_2[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_3 = _uncommonBits_T_3[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_4 = _uncommonBits_T_4[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_5 = _uncommonBits_T_5[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_6 = _uncommonBits_T_6[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_7 = _uncommonBits_T_7[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_8 = _uncommonBits_T_8[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_9 = _uncommonBits_T_9[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_10 = _uncommonBits_T_10[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_11 = _uncommonBits_T_11[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_12 = _uncommonBits_T_12[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_13 = _uncommonBits_T_13[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_14 = _uncommonBits_T_14[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_15 = _uncommonBits_T_15[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_16 = _uncommonBits_T_16[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_17 = _uncommonBits_T_17[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[5:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_12 = io_in_d_bits_source_0[6]; // @[Monitor.scala:36:7]
wire _source_ok_T_18 = io_in_d_bits_source_0[6]; // @[Monitor.scala:36:7]
wire _source_ok_T_13 = _source_ok_T_12; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_15 = _source_ok_T_13; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_17 = _source_ok_T_15; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_0 = _source_ok_T_17; // @[Parameters.scala:1138:31]
wire [5:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[5:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_19 = ~_source_ok_T_18; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_21 = _source_ok_T_19; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_23 = _source_ok_T_21; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_23; // @[Parameters.scala:1138:31]
wire source_ok_1 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1337 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1337; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1337; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [7:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [7:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [7:0] a_first_counter; // @[Edges.scala:229:27]
wire [8:0] _a_first_counter1_T = {1'h0, a_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28]
wire [7:0] a_first_counter1 = _a_first_counter1_T[7:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [7:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [7:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [7:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [6:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_1410 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1410; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1410; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1410; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [7:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [7:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [7:0] d_first_counter; // @[Edges.scala:229:27]
wire [8:0] _d_first_counter1_T = {1'h0, d_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28]
wire [7:0] d_first_counter1 = _d_first_counter1_T[7:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [7:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [7:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [7:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [6:0] source_1; // @[Monitor.scala:541:22]
reg [3:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [127:0] inflight; // @[Monitor.scala:614:27]
reg [511:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [1023:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [7:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [7:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [7:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [8:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28]
wire [7:0] a_first_counter1_1 = _a_first_counter1_T_1[7:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [7:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [7:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [7:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [7:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46]
wire [7:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [7:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [8:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28]
wire [7:0] d_first_counter1_1 = _d_first_counter1_T_1[7:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [7:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [7:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [7:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [127:0] a_set; // @[Monitor.scala:626:34]
wire [127:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [511:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [1023:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [511:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [511:0] _a_opcode_lookup_T_6 = {508'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [511:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[511:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [9:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [1023:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [1023:0] _a_size_lookup_T_6 = {1016'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}]
wire [1023:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[1023:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [127:0] _GEN_3 = {121'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35]
wire [127:0] _GEN_4 = 128'h1 << _GEN_3; // @[OneHot.scala:58:35]
wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35]
wire [127:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 128'h0; // @[OneHot.scala:58:35]
wire _T_1263 = _T_1337 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1263 ? _a_set_T : 128'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1263 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1263 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [9:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1263 ? _a_opcodes_set_T_1[511:0] : 512'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [9:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [1027:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1263 ? _a_sizes_set_T_1[1023:0] : 1024'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [127:0] d_clr; // @[Monitor.scala:664:34]
wire [127:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [511:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [1023:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46]
wire _T_1309 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [127:0] _GEN_6 = {121'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35]
wire [127:0] _GEN_7 = 128'h1 << _GEN_6; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1309 & ~d_release_ack ? _d_clr_wo_ready_T : 128'h0; // @[OneHot.scala:58:35]
wire _T_1278 = _T_1410 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1278 ? _d_clr_T : 128'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1278 ? _d_opcodes_clr_T_5[511:0] : 512'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [1038:0] _d_sizes_clr_T_5 = 1039'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1278 ? _d_sizes_clr_T_5[1023:0] : 1024'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [127:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [127:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [127:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [511:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [511:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [511:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [1023:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [1023:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [1023:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [127:0] inflight_1; // @[Monitor.scala:726:35]
wire [127:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [511:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [511:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [1023:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [1023:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [7:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:4]; // @[package.scala:243:46]
wire [7:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [7:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [8:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 9'h1; // @[Edges.scala:229:27, :230:28]
wire [7:0] d_first_counter1_2 = _d_first_counter1_T_2[7:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 8'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 8'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 8'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [7:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [7:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [7:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [511:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [511:0] _c_opcode_lookup_T_6 = {508'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [511:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[511:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [1023:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [1023:0] _c_size_lookup_T_6 = {1016'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}]
wire [1023:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[1023:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [127:0] d_clr_1; // @[Monitor.scala:774:34]
wire [127:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [511:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [1023:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1381 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1381 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 128'h0; // @[OneHot.scala:58:35]
wire _T_1363 = _T_1410 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1363 ? _d_clr_T_1 : 128'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1363 ? _d_opcodes_clr_T_11[511:0] : 512'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [1038:0] _d_sizes_clr_T_11 = 1039'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1363 ? _d_sizes_clr_T_11[1023:0] : 1024'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113]
wire [127:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [127:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [511:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [511:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [1023:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [1023:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module ForwardingAgeLogic :
input clock : Clock
input reset : Reset
output io : { flip matches : UInt<24>, flip youngest : UInt<5>, found : UInt<1>, found_idx : UInt<5>}
wire age_mask : UInt<1>[24]
connect age_mask[0], UInt<1>(0h1)
node _T = geq(UInt<1>(0h0), io.youngest)
when _T :
connect age_mask[0], UInt<1>(0h0)
connect age_mask[1], UInt<1>(0h1)
node _T_1 = geq(UInt<1>(0h1), io.youngest)
when _T_1 :
connect age_mask[1], UInt<1>(0h0)
connect age_mask[2], UInt<1>(0h1)
node _T_2 = geq(UInt<2>(0h2), io.youngest)
when _T_2 :
connect age_mask[2], UInt<1>(0h0)
connect age_mask[3], UInt<1>(0h1)
node _T_3 = geq(UInt<2>(0h3), io.youngest)
when _T_3 :
connect age_mask[3], UInt<1>(0h0)
connect age_mask[4], UInt<1>(0h1)
node _T_4 = geq(UInt<3>(0h4), io.youngest)
when _T_4 :
connect age_mask[4], UInt<1>(0h0)
connect age_mask[5], UInt<1>(0h1)
node _T_5 = geq(UInt<3>(0h5), io.youngest)
when _T_5 :
connect age_mask[5], UInt<1>(0h0)
connect age_mask[6], UInt<1>(0h1)
node _T_6 = geq(UInt<3>(0h6), io.youngest)
when _T_6 :
connect age_mask[6], UInt<1>(0h0)
connect age_mask[7], UInt<1>(0h1)
node _T_7 = geq(UInt<3>(0h7), io.youngest)
when _T_7 :
connect age_mask[7], UInt<1>(0h0)
connect age_mask[8], UInt<1>(0h1)
node _T_8 = geq(UInt<4>(0h8), io.youngest)
when _T_8 :
connect age_mask[8], UInt<1>(0h0)
connect age_mask[9], UInt<1>(0h1)
node _T_9 = geq(UInt<4>(0h9), io.youngest)
when _T_9 :
connect age_mask[9], UInt<1>(0h0)
connect age_mask[10], UInt<1>(0h1)
node _T_10 = geq(UInt<4>(0ha), io.youngest)
when _T_10 :
connect age_mask[10], UInt<1>(0h0)
connect age_mask[11], UInt<1>(0h1)
node _T_11 = geq(UInt<4>(0hb), io.youngest)
when _T_11 :
connect age_mask[11], UInt<1>(0h0)
connect age_mask[12], UInt<1>(0h1)
node _T_12 = geq(UInt<4>(0hc), io.youngest)
when _T_12 :
connect age_mask[12], UInt<1>(0h0)
connect age_mask[13], UInt<1>(0h1)
node _T_13 = geq(UInt<4>(0hd), io.youngest)
when _T_13 :
connect age_mask[13], UInt<1>(0h0)
connect age_mask[14], UInt<1>(0h1)
node _T_14 = geq(UInt<4>(0he), io.youngest)
when _T_14 :
connect age_mask[14], UInt<1>(0h0)
connect age_mask[15], UInt<1>(0h1)
node _T_15 = geq(UInt<4>(0hf), io.youngest)
when _T_15 :
connect age_mask[15], UInt<1>(0h0)
connect age_mask[16], UInt<1>(0h1)
node _T_16 = geq(UInt<5>(0h10), io.youngest)
when _T_16 :
connect age_mask[16], UInt<1>(0h0)
connect age_mask[17], UInt<1>(0h1)
node _T_17 = geq(UInt<5>(0h11), io.youngest)
when _T_17 :
connect age_mask[17], UInt<1>(0h0)
connect age_mask[18], UInt<1>(0h1)
node _T_18 = geq(UInt<5>(0h12), io.youngest)
when _T_18 :
connect age_mask[18], UInt<1>(0h0)
connect age_mask[19], UInt<1>(0h1)
node _T_19 = geq(UInt<5>(0h13), io.youngest)
when _T_19 :
connect age_mask[19], UInt<1>(0h0)
connect age_mask[20], UInt<1>(0h1)
node _T_20 = geq(UInt<5>(0h14), io.youngest)
when _T_20 :
connect age_mask[20], UInt<1>(0h0)
connect age_mask[21], UInt<1>(0h1)
node _T_21 = geq(UInt<5>(0h15), io.youngest)
when _T_21 :
connect age_mask[21], UInt<1>(0h0)
connect age_mask[22], UInt<1>(0h1)
node _T_22 = geq(UInt<5>(0h16), io.youngest)
when _T_22 :
connect age_mask[22], UInt<1>(0h0)
connect age_mask[23], UInt<1>(0h1)
node _T_23 = geq(UInt<5>(0h17), io.youngest)
when _T_23 :
connect age_mask[23], UInt<1>(0h0)
wire matches : UInt<48>
node matches_lo_lo_lo_hi = cat(age_mask[2], age_mask[1])
node matches_lo_lo_lo = cat(matches_lo_lo_lo_hi, age_mask[0])
node matches_lo_lo_hi_hi = cat(age_mask[5], age_mask[4])
node matches_lo_lo_hi = cat(matches_lo_lo_hi_hi, age_mask[3])
node matches_lo_lo = cat(matches_lo_lo_hi, matches_lo_lo_lo)
node matches_lo_hi_lo_hi = cat(age_mask[8], age_mask[7])
node matches_lo_hi_lo = cat(matches_lo_hi_lo_hi, age_mask[6])
node matches_lo_hi_hi_hi = cat(age_mask[11], age_mask[10])
node matches_lo_hi_hi = cat(matches_lo_hi_hi_hi, age_mask[9])
node matches_lo_hi = cat(matches_lo_hi_hi, matches_lo_hi_lo)
node matches_lo = cat(matches_lo_hi, matches_lo_lo)
node matches_hi_lo_lo_hi = cat(age_mask[14], age_mask[13])
node matches_hi_lo_lo = cat(matches_hi_lo_lo_hi, age_mask[12])
node matches_hi_lo_hi_hi = cat(age_mask[17], age_mask[16])
node matches_hi_lo_hi = cat(matches_hi_lo_hi_hi, age_mask[15])
node matches_hi_lo = cat(matches_hi_lo_hi, matches_hi_lo_lo)
node matches_hi_hi_lo_hi = cat(age_mask[20], age_mask[19])
node matches_hi_hi_lo = cat(matches_hi_hi_lo_hi, age_mask[18])
node matches_hi_hi_hi_hi = cat(age_mask[23], age_mask[22])
node matches_hi_hi_hi = cat(matches_hi_hi_hi_hi, age_mask[21])
node matches_hi_hi = cat(matches_hi_hi_hi, matches_hi_hi_lo)
node matches_hi = cat(matches_hi_hi, matches_hi_lo)
node _matches_T = cat(matches_hi, matches_lo)
node _matches_T_1 = and(io.matches, _matches_T)
node _matches_T_2 = cat(_matches_T_1, io.matches)
connect matches, _matches_T_2
reg found_match : UInt<1>, clock
reg found_idx : UInt<5>, clock
connect found_match, UInt<1>(0h0)
connect found_idx, UInt<1>(0h0)
connect io.found_idx, found_idx
connect io.found, found_match
node _T_24 = bits(matches, 0, 0)
when _T_24 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<1>(0h0)
node _T_25 = bits(matches, 1, 1)
when _T_25 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<1>(0h1)
node _T_26 = bits(matches, 2, 2)
when _T_26 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<2>(0h2)
node _T_27 = bits(matches, 3, 3)
when _T_27 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<2>(0h3)
node _T_28 = bits(matches, 4, 4)
when _T_28 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<3>(0h4)
node _T_29 = bits(matches, 5, 5)
when _T_29 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<3>(0h5)
node _T_30 = bits(matches, 6, 6)
when _T_30 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<3>(0h6)
node _T_31 = bits(matches, 7, 7)
when _T_31 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<3>(0h7)
node _T_32 = bits(matches, 8, 8)
when _T_32 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<4>(0h8)
node _T_33 = bits(matches, 9, 9)
when _T_33 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<4>(0h9)
node _T_34 = bits(matches, 10, 10)
when _T_34 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<4>(0ha)
node _T_35 = bits(matches, 11, 11)
when _T_35 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<4>(0hb)
node _T_36 = bits(matches, 12, 12)
when _T_36 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<4>(0hc)
node _T_37 = bits(matches, 13, 13)
when _T_37 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<4>(0hd)
node _T_38 = bits(matches, 14, 14)
when _T_38 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<4>(0he)
node _T_39 = bits(matches, 15, 15)
when _T_39 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<4>(0hf)
node _T_40 = bits(matches, 16, 16)
when _T_40 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<5>(0h10)
node _T_41 = bits(matches, 17, 17)
when _T_41 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<5>(0h11)
node _T_42 = bits(matches, 18, 18)
when _T_42 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<5>(0h12)
node _T_43 = bits(matches, 19, 19)
when _T_43 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<5>(0h13)
node _T_44 = bits(matches, 20, 20)
when _T_44 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<5>(0h14)
node _T_45 = bits(matches, 21, 21)
when _T_45 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<5>(0h15)
node _T_46 = bits(matches, 22, 22)
when _T_46 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<5>(0h16)
node _T_47 = bits(matches, 23, 23)
when _T_47 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<5>(0h17)
node _T_48 = bits(matches, 24, 24)
when _T_48 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<1>(0h0)
node _T_49 = bits(matches, 25, 25)
when _T_49 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<1>(0h1)
node _T_50 = bits(matches, 26, 26)
when _T_50 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<2>(0h2)
node _T_51 = bits(matches, 27, 27)
when _T_51 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<2>(0h3)
node _T_52 = bits(matches, 28, 28)
when _T_52 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<3>(0h4)
node _T_53 = bits(matches, 29, 29)
when _T_53 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<3>(0h5)
node _T_54 = bits(matches, 30, 30)
when _T_54 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<3>(0h6)
node _T_55 = bits(matches, 31, 31)
when _T_55 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<3>(0h7)
node _T_56 = bits(matches, 32, 32)
when _T_56 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<4>(0h8)
node _T_57 = bits(matches, 33, 33)
when _T_57 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<4>(0h9)
node _T_58 = bits(matches, 34, 34)
when _T_58 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<4>(0ha)
node _T_59 = bits(matches, 35, 35)
when _T_59 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<4>(0hb)
node _T_60 = bits(matches, 36, 36)
when _T_60 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<4>(0hc)
node _T_61 = bits(matches, 37, 37)
when _T_61 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<4>(0hd)
node _T_62 = bits(matches, 38, 38)
when _T_62 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<4>(0he)
node _T_63 = bits(matches, 39, 39)
when _T_63 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<4>(0hf)
node _T_64 = bits(matches, 40, 40)
when _T_64 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<5>(0h10)
node _T_65 = bits(matches, 41, 41)
when _T_65 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<5>(0h11)
node _T_66 = bits(matches, 42, 42)
when _T_66 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<5>(0h12)
node _T_67 = bits(matches, 43, 43)
when _T_67 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<5>(0h13)
node _T_68 = bits(matches, 44, 44)
when _T_68 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<5>(0h14)
node _T_69 = bits(matches, 45, 45)
when _T_69 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<5>(0h15)
node _T_70 = bits(matches, 46, 46)
when _T_70 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<5>(0h16)
node _T_71 = bits(matches, 47, 47)
when _T_71 :
connect found_match, UInt<1>(0h1)
connect found_idx, UInt<5>(0h17) | module ForwardingAgeLogic( // @[lsu.scala:1972:7]
input clock, // @[lsu.scala:1972:7]
input reset, // @[lsu.scala:1972:7]
input [23:0] io_matches, // @[lsu.scala:1974:14]
input [4:0] io_youngest, // @[lsu.scala:1974:14]
output io_found, // @[lsu.scala:1974:14]
output [4:0] io_found_idx // @[lsu.scala:1974:14]
);
wire [23:0] io_matches_0 = io_matches; // @[lsu.scala:1972:7]
wire [4:0] io_youngest_0 = io_youngest; // @[lsu.scala:1972:7]
wire io_found_0; // @[lsu.scala:1972:7]
wire [4:0] io_found_idx_0; // @[lsu.scala:1972:7]
wire age_mask_0; // @[lsu.scala:1985:22]
wire age_mask_1; // @[lsu.scala:1985:22]
wire age_mask_2; // @[lsu.scala:1985:22]
wire age_mask_3; // @[lsu.scala:1985:22]
wire age_mask_4; // @[lsu.scala:1985:22]
wire age_mask_5; // @[lsu.scala:1985:22]
wire age_mask_6; // @[lsu.scala:1985:22]
wire age_mask_7; // @[lsu.scala:1985:22]
wire age_mask_8; // @[lsu.scala:1985:22]
wire age_mask_9; // @[lsu.scala:1985:22]
wire age_mask_10; // @[lsu.scala:1985:22]
wire age_mask_11; // @[lsu.scala:1985:22]
wire age_mask_12; // @[lsu.scala:1985:22]
wire age_mask_13; // @[lsu.scala:1985:22]
wire age_mask_14; // @[lsu.scala:1985:22]
wire age_mask_15; // @[lsu.scala:1985:22]
wire age_mask_16; // @[lsu.scala:1985:22]
wire age_mask_17; // @[lsu.scala:1985:22]
wire age_mask_18; // @[lsu.scala:1985:22]
wire age_mask_19; // @[lsu.scala:1985:22]
wire age_mask_20; // @[lsu.scala:1985:22]
wire age_mask_21; // @[lsu.scala:1985:22]
wire age_mask_22; // @[lsu.scala:1985:22]
wire age_mask_23; // @[lsu.scala:1985:22]
assign age_mask_0 = |io_youngest_0; // @[lsu.scala:1972:7, :1985:22, :1988:17, :1989:15, :1990:5, :1991:19]
assign age_mask_1 = |(io_youngest_0[4:1]); // @[lsu.scala:1972:7, :1985:22, :1988:17, :1989:15, :1990:5, :1991:19]
assign age_mask_2 = io_youngest_0 > 5'h2; // @[lsu.scala:1972:7, :1985:22, :1988:17, :1989:15, :1990:5, :1991:19]
assign age_mask_3 = |(io_youngest_0[4:2]); // @[lsu.scala:1972:7, :1985:22, :1988:17, :1989:15, :1990:5, :1991:19]
assign age_mask_4 = io_youngest_0 > 5'h4; // @[lsu.scala:1972:7, :1985:22, :1988:17, :1989:15, :1990:5, :1991:19]
assign age_mask_5 = io_youngest_0 > 5'h5; // @[lsu.scala:1972:7, :1985:22, :1988:17, :1989:15, :1990:5, :1991:19]
assign age_mask_6 = io_youngest_0 > 5'h6; // @[lsu.scala:1972:7, :1985:22, :1988:17, :1989:15, :1990:5, :1991:19]
assign age_mask_7 = |(io_youngest_0[4:3]); // @[lsu.scala:1972:7, :1985:22, :1988:17, :1989:15, :1990:5, :1991:19]
assign age_mask_8 = io_youngest_0 > 5'h8; // @[lsu.scala:1972:7, :1985:22, :1988:17, :1989:15, :1990:5, :1991:19]
assign age_mask_9 = io_youngest_0 > 5'h9; // @[lsu.scala:1972:7, :1985:22, :1988:17, :1989:15, :1990:5, :1991:19]
assign age_mask_10 = io_youngest_0 > 5'hA; // @[lsu.scala:1972:7, :1985:22, :1988:17, :1989:15, :1990:5, :1991:19]
assign age_mask_11 = io_youngest_0 > 5'hB; // @[lsu.scala:1972:7, :1985:22, :1988:17, :1989:15, :1990:5, :1991:19]
assign age_mask_12 = io_youngest_0 > 5'hC; // @[lsu.scala:1972:7, :1985:22, :1988:17, :1989:15, :1990:5, :1991:19]
assign age_mask_13 = io_youngest_0 > 5'hD; // @[lsu.scala:1972:7, :1985:22, :1988:17, :1989:15, :1990:5, :1991:19]
assign age_mask_14 = io_youngest_0 > 5'hE; // @[lsu.scala:1972:7, :1985:22, :1988:17, :1989:15, :1990:5, :1991:19]
assign age_mask_15 = io_youngest_0[4]; // @[lsu.scala:1972:7, :1985:22, :1988:17, :1989:15, :1990:5, :1991:19]
assign age_mask_16 = io_youngest_0 > 5'h10; // @[lsu.scala:1972:7, :1985:22, :1988:17, :1989:15, :1990:5, :1991:19]
assign age_mask_17 = io_youngest_0 > 5'h11; // @[lsu.scala:1972:7, :1985:22, :1988:17, :1989:15, :1990:5, :1991:19]
assign age_mask_18 = io_youngest_0 > 5'h12; // @[lsu.scala:1972:7, :1985:22, :1988:17, :1989:15, :1990:5, :1991:19]
assign age_mask_19 = io_youngest_0 > 5'h13; // @[lsu.scala:1972:7, :1985:22, :1988:17, :1989:15, :1990:5, :1991:19]
assign age_mask_20 = io_youngest_0 > 5'h14; // @[lsu.scala:1972:7, :1985:22, :1988:17, :1989:15, :1990:5, :1991:19]
assign age_mask_21 = io_youngest_0 > 5'h15; // @[lsu.scala:1972:7, :1985:22, :1988:17, :1989:15, :1990:5, :1991:19]
assign age_mask_22 = io_youngest_0 > 5'h16; // @[lsu.scala:1972:7, :1985:22, :1988:17, :1989:15, :1990:5, :1991:19]
assign age_mask_23 = io_youngest_0 > 5'h17; // @[lsu.scala:1972:7, :1985:22, :1988:17, :1989:15, :1990:5, :1991:19]
wire [47:0] _matches_T_2; // @[lsu.scala:1997:17]
wire [47:0] matches_0; // @[lsu.scala:1996:21]
wire [1:0] matches_lo_lo_lo_hi = {age_mask_2, age_mask_1}; // @[lsu.scala:1985:22, :1997:40]
wire [2:0] matches_lo_lo_lo = {matches_lo_lo_lo_hi, age_mask_0}; // @[lsu.scala:1985:22, :1997:40]
wire [1:0] matches_lo_lo_hi_hi = {age_mask_5, age_mask_4}; // @[lsu.scala:1985:22, :1997:40]
wire [2:0] matches_lo_lo_hi = {matches_lo_lo_hi_hi, age_mask_3}; // @[lsu.scala:1985:22, :1997:40]
wire [5:0] matches_lo_lo = {matches_lo_lo_hi, matches_lo_lo_lo}; // @[lsu.scala:1997:40]
wire [1:0] matches_lo_hi_lo_hi = {age_mask_8, age_mask_7}; // @[lsu.scala:1985:22, :1997:40]
wire [2:0] matches_lo_hi_lo = {matches_lo_hi_lo_hi, age_mask_6}; // @[lsu.scala:1985:22, :1997:40]
wire [1:0] matches_lo_hi_hi_hi = {age_mask_11, age_mask_10}; // @[lsu.scala:1985:22, :1997:40]
wire [2:0] matches_lo_hi_hi = {matches_lo_hi_hi_hi, age_mask_9}; // @[lsu.scala:1985:22, :1997:40]
wire [5:0] matches_lo_hi = {matches_lo_hi_hi, matches_lo_hi_lo}; // @[lsu.scala:1997:40]
wire [11:0] matches_lo = {matches_lo_hi, matches_lo_lo}; // @[lsu.scala:1997:40]
wire [1:0] matches_hi_lo_lo_hi = {age_mask_14, age_mask_13}; // @[lsu.scala:1985:22, :1997:40]
wire [2:0] matches_hi_lo_lo = {matches_hi_lo_lo_hi, age_mask_12}; // @[lsu.scala:1985:22, :1997:40]
wire [1:0] matches_hi_lo_hi_hi = {age_mask_17, age_mask_16}; // @[lsu.scala:1985:22, :1997:40]
wire [2:0] matches_hi_lo_hi = {matches_hi_lo_hi_hi, age_mask_15}; // @[lsu.scala:1985:22, :1997:40]
wire [5:0] matches_hi_lo = {matches_hi_lo_hi, matches_hi_lo_lo}; // @[lsu.scala:1997:40]
wire [1:0] matches_hi_hi_lo_hi = {age_mask_20, age_mask_19}; // @[lsu.scala:1985:22, :1997:40]
wire [2:0] matches_hi_hi_lo = {matches_hi_hi_lo_hi, age_mask_18}; // @[lsu.scala:1985:22, :1997:40]
wire [1:0] matches_hi_hi_hi_hi = {age_mask_23, age_mask_22}; // @[lsu.scala:1985:22, :1997:40]
wire [2:0] matches_hi_hi_hi = {matches_hi_hi_hi_hi, age_mask_21}; // @[lsu.scala:1985:22, :1997:40]
wire [5:0] matches_hi_hi = {matches_hi_hi_hi, matches_hi_hi_lo}; // @[lsu.scala:1997:40]
wire [11:0] matches_hi = {matches_hi_hi, matches_hi_lo}; // @[lsu.scala:1997:40]
wire [23:0] _matches_T = {matches_hi, matches_lo}; // @[lsu.scala:1997:40]
wire [23:0] _matches_T_1 = io_matches_0 & _matches_T; // @[lsu.scala:1972:7, :1997:{29,40}]
assign _matches_T_2 = {_matches_T_1, io_matches_0}; // @[lsu.scala:1972:7, :1997:{17,29}]
assign matches_0 = _matches_T_2; // @[lsu.scala:1996:21, :1997:17]
reg found_match; // @[lsu.scala:2000:24]
assign io_found_0 = found_match; // @[lsu.scala:1972:7, :2000:24]
reg [4:0] found_idx; // @[lsu.scala:2001:22]
assign io_found_idx_0 = found_idx; // @[lsu.scala:1972:7, :2001:22]
always @(posedge clock) begin // @[lsu.scala:1972:7]
found_match <= |matches_0; // @[lsu.scala:1996:21, :2000:24, :2012:7, :2013:22]
found_idx <= matches_0[47] ? 5'h17 : matches_0[46] ? 5'h16 : matches_0[45] ? 5'h15 : matches_0[44] ? 5'h14 : matches_0[43] ? 5'h13 : matches_0[42] ? 5'h12 : matches_0[41] ? 5'h11 : matches_0[40] ? 5'h10 : matches_0[39] ? 5'hF : matches_0[38] ? 5'hE : matches_0[37] ? 5'hD : matches_0[36] ? 5'hC : matches_0[35] ? 5'hB : matches_0[34] ? 5'hA : matches_0[33] ? 5'h9 : matches_0[32] ? 5'h8 : matches_0[31] ? 5'h7 : matches_0[30] ? 5'h6 : matches_0[29] ? 5'h5 : matches_0[28] ? 5'h4 : matches_0[27] ? 5'h3 : matches_0[26] ? 5'h2 : matches_0[25] ? 5'h1 : matches_0[24] ? 5'h0 : matches_0[23] ? 5'h17 : matches_0[22] ? 5'h16 : matches_0[21] ? 5'h15 : matches_0[20] ? 5'h14 : matches_0[19] ? 5'h13 : matches_0[18] ? 5'h12 : matches_0[17] ? 5'h11 : matches_0[16] ? 5'h10 : matches_0[15] ? 5'hF : matches_0[14] ? 5'hE : matches_0[13] ? 5'hD : matches_0[12] ? 5'hC : matches_0[11] ? 5'hB : matches_0[10] ? 5'hA : matches_0[9] ? 5'h9 : matches_0[8] ? 5'h8 : matches_0[7] ? 5'h7 : matches_0[6] ? 5'h6 : matches_0[5] ? 5'h5 : matches_0[4] ? 5'h4 : matches_0[3] ? 5'h3 : matches_0[2] ? 5'h2 : {4'h0, matches_0[1]}; // @[lsu.scala:1988:17, :1989:15, :1990:5, :1991:19, :1996:21, :2001:22, :2011:20, :2012:7, :2014:20]
always @(posedge)
assign io_found = io_found_0; // @[lsu.scala:1972:7]
assign io_found_idx = io_found_idx_0; // @[lsu.scala:1972:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_postMul_e8_s24_13 :
output io : { flip fromPreMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}, flip mulAddResult : UInt<49>, flip roundingMode : UInt<3>, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}}
node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2))
node opSignC = xor(io.fromPreMul.signProd, io.fromPreMul.doSubMags)
node _sigSum_T = bits(io.mulAddResult, 48, 48)
node _sigSum_T_1 = add(io.fromPreMul.highAlignedSigC, UInt<1>(0h1))
node _sigSum_T_2 = tail(_sigSum_T_1, 1)
node _sigSum_T_3 = mux(_sigSum_T, _sigSum_T_2, io.fromPreMul.highAlignedSigC)
node _sigSum_T_4 = bits(io.mulAddResult, 47, 0)
node sigSum_hi = cat(_sigSum_T_3, _sigSum_T_4)
node sigSum = cat(sigSum_hi, io.fromPreMul.bit0AlignedSigC)
node _CDom_sExp_T = cvt(io.fromPreMul.doSubMags)
node _CDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _CDom_sExp_T)
node _CDom_sExp_T_2 = tail(_CDom_sExp_T_1, 1)
node CDom_sExp = asSInt(_CDom_sExp_T_2)
node _CDom_absSigSum_T = bits(sigSum, 74, 25)
node _CDom_absSigSum_T_1 = not(_CDom_absSigSum_T)
node _CDom_absSigSum_T_2 = bits(io.fromPreMul.highAlignedSigC, 25, 24)
node _CDom_absSigSum_T_3 = cat(UInt<1>(0h0), _CDom_absSigSum_T_2)
node _CDom_absSigSum_T_4 = bits(sigSum, 72, 26)
node _CDom_absSigSum_T_5 = cat(_CDom_absSigSum_T_3, _CDom_absSigSum_T_4)
node CDom_absSigSum = mux(io.fromPreMul.doSubMags, _CDom_absSigSum_T_1, _CDom_absSigSum_T_5)
node _CDom_absSigSumExtra_T = bits(sigSum, 24, 1)
node _CDom_absSigSumExtra_T_1 = not(_CDom_absSigSumExtra_T)
node _CDom_absSigSumExtra_T_2 = orr(_CDom_absSigSumExtra_T_1)
node _CDom_absSigSumExtra_T_3 = bits(sigSum, 25, 1)
node _CDom_absSigSumExtra_T_4 = orr(_CDom_absSigSumExtra_T_3)
node CDom_absSigSumExtra = mux(io.fromPreMul.doSubMags, _CDom_absSigSumExtra_T_2, _CDom_absSigSumExtra_T_4)
node _CDom_mainSig_T = dshl(CDom_absSigSum, io.fromPreMul.CDom_CAlignDist)
node CDom_mainSig = bits(_CDom_mainSig_T, 49, 21)
node _CDom_reduced4SigExtra_T = bits(CDom_absSigSum, 23, 0)
node _CDom_reduced4SigExtra_T_1 = shl(_CDom_reduced4SigExtra_T, 3)
wire CDom_reduced4SigExtra_reducedVec : UInt<1>[7]
node _CDom_reduced4SigExtra_reducedVec_0_T = bits(_CDom_reduced4SigExtra_T_1, 3, 0)
node _CDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_0_T)
connect CDom_reduced4SigExtra_reducedVec[0], _CDom_reduced4SigExtra_reducedVec_0_T_1
node _CDom_reduced4SigExtra_reducedVec_1_T = bits(_CDom_reduced4SigExtra_T_1, 7, 4)
node _CDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_1_T)
connect CDom_reduced4SigExtra_reducedVec[1], _CDom_reduced4SigExtra_reducedVec_1_T_1
node _CDom_reduced4SigExtra_reducedVec_2_T = bits(_CDom_reduced4SigExtra_T_1, 11, 8)
node _CDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_2_T)
connect CDom_reduced4SigExtra_reducedVec[2], _CDom_reduced4SigExtra_reducedVec_2_T_1
node _CDom_reduced4SigExtra_reducedVec_3_T = bits(_CDom_reduced4SigExtra_T_1, 15, 12)
node _CDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_3_T)
connect CDom_reduced4SigExtra_reducedVec[3], _CDom_reduced4SigExtra_reducedVec_3_T_1
node _CDom_reduced4SigExtra_reducedVec_4_T = bits(_CDom_reduced4SigExtra_T_1, 19, 16)
node _CDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_4_T)
connect CDom_reduced4SigExtra_reducedVec[4], _CDom_reduced4SigExtra_reducedVec_4_T_1
node _CDom_reduced4SigExtra_reducedVec_5_T = bits(_CDom_reduced4SigExtra_T_1, 23, 20)
node _CDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_5_T)
connect CDom_reduced4SigExtra_reducedVec[5], _CDom_reduced4SigExtra_reducedVec_5_T_1
node _CDom_reduced4SigExtra_reducedVec_6_T = bits(_CDom_reduced4SigExtra_T_1, 26, 24)
node _CDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_6_T)
connect CDom_reduced4SigExtra_reducedVec[6], _CDom_reduced4SigExtra_reducedVec_6_T_1
node CDom_reduced4SigExtra_lo_hi = cat(CDom_reduced4SigExtra_reducedVec[2], CDom_reduced4SigExtra_reducedVec[1])
node CDom_reduced4SigExtra_lo = cat(CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec[0])
node CDom_reduced4SigExtra_hi_lo = cat(CDom_reduced4SigExtra_reducedVec[4], CDom_reduced4SigExtra_reducedVec[3])
node CDom_reduced4SigExtra_hi_hi = cat(CDom_reduced4SigExtra_reducedVec[6], CDom_reduced4SigExtra_reducedVec[5])
node CDom_reduced4SigExtra_hi = cat(CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo)
node _CDom_reduced4SigExtra_T_2 = cat(CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo)
node _CDom_reduced4SigExtra_T_3 = shr(io.fromPreMul.CDom_CAlignDist, 2)
node _CDom_reduced4SigExtra_T_4 = not(_CDom_reduced4SigExtra_T_3)
node CDom_reduced4SigExtra_shift = dshr(asSInt(UInt<9>(0h100)), _CDom_reduced4SigExtra_T_4)
node _CDom_reduced4SigExtra_T_5 = bits(CDom_reduced4SigExtra_shift, 6, 1)
node _CDom_reduced4SigExtra_T_6 = bits(_CDom_reduced4SigExtra_T_5, 3, 0)
node _CDom_reduced4SigExtra_T_7 = bits(_CDom_reduced4SigExtra_T_6, 1, 0)
node _CDom_reduced4SigExtra_T_8 = bits(_CDom_reduced4SigExtra_T_7, 0, 0)
node _CDom_reduced4SigExtra_T_9 = bits(_CDom_reduced4SigExtra_T_7, 1, 1)
node _CDom_reduced4SigExtra_T_10 = cat(_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9)
node _CDom_reduced4SigExtra_T_11 = bits(_CDom_reduced4SigExtra_T_6, 3, 2)
node _CDom_reduced4SigExtra_T_12 = bits(_CDom_reduced4SigExtra_T_11, 0, 0)
node _CDom_reduced4SigExtra_T_13 = bits(_CDom_reduced4SigExtra_T_11, 1, 1)
node _CDom_reduced4SigExtra_T_14 = cat(_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13)
node _CDom_reduced4SigExtra_T_15 = cat(_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14)
node _CDom_reduced4SigExtra_T_16 = bits(_CDom_reduced4SigExtra_T_5, 5, 4)
node _CDom_reduced4SigExtra_T_17 = bits(_CDom_reduced4SigExtra_T_16, 0, 0)
node _CDom_reduced4SigExtra_T_18 = bits(_CDom_reduced4SigExtra_T_16, 1, 1)
node _CDom_reduced4SigExtra_T_19 = cat(_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18)
node _CDom_reduced4SigExtra_T_20 = cat(_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19)
node _CDom_reduced4SigExtra_T_21 = and(_CDom_reduced4SigExtra_T_2, _CDom_reduced4SigExtra_T_20)
node CDom_reduced4SigExtra = orr(_CDom_reduced4SigExtra_T_21)
node _CDom_sig_T = shr(CDom_mainSig, 3)
node _CDom_sig_T_1 = bits(CDom_mainSig, 2, 0)
node _CDom_sig_T_2 = orr(_CDom_sig_T_1)
node _CDom_sig_T_3 = or(_CDom_sig_T_2, CDom_reduced4SigExtra)
node _CDom_sig_T_4 = or(_CDom_sig_T_3, CDom_absSigSumExtra)
node CDom_sig = cat(_CDom_sig_T, _CDom_sig_T_4)
node notCDom_signSigSum = bits(sigSum, 51, 51)
node _notCDom_absSigSum_T = bits(sigSum, 50, 0)
node _notCDom_absSigSum_T_1 = not(_notCDom_absSigSum_T)
node _notCDom_absSigSum_T_2 = bits(sigSum, 50, 0)
node _notCDom_absSigSum_T_3 = add(_notCDom_absSigSum_T_2, io.fromPreMul.doSubMags)
node _notCDom_absSigSum_T_4 = tail(_notCDom_absSigSum_T_3, 1)
node notCDom_absSigSum = mux(notCDom_signSigSum, _notCDom_absSigSum_T_1, _notCDom_absSigSum_T_4)
wire notCDom_reduced2AbsSigSum_reducedVec : UInt<1>[26]
node _notCDom_reduced2AbsSigSum_reducedVec_0_T = bits(notCDom_absSigSum, 1, 0)
node _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_0_T)
connect notCDom_reduced2AbsSigSum_reducedVec[0], _notCDom_reduced2AbsSigSum_reducedVec_0_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_1_T = bits(notCDom_absSigSum, 3, 2)
node _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_1_T)
connect notCDom_reduced2AbsSigSum_reducedVec[1], _notCDom_reduced2AbsSigSum_reducedVec_1_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_2_T = bits(notCDom_absSigSum, 5, 4)
node _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_2_T)
connect notCDom_reduced2AbsSigSum_reducedVec[2], _notCDom_reduced2AbsSigSum_reducedVec_2_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_3_T = bits(notCDom_absSigSum, 7, 6)
node _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_3_T)
connect notCDom_reduced2AbsSigSum_reducedVec[3], _notCDom_reduced2AbsSigSum_reducedVec_3_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_4_T = bits(notCDom_absSigSum, 9, 8)
node _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_4_T)
connect notCDom_reduced2AbsSigSum_reducedVec[4], _notCDom_reduced2AbsSigSum_reducedVec_4_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_5_T = bits(notCDom_absSigSum, 11, 10)
node _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_5_T)
connect notCDom_reduced2AbsSigSum_reducedVec[5], _notCDom_reduced2AbsSigSum_reducedVec_5_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_6_T = bits(notCDom_absSigSum, 13, 12)
node _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_6_T)
connect notCDom_reduced2AbsSigSum_reducedVec[6], _notCDom_reduced2AbsSigSum_reducedVec_6_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_7_T = bits(notCDom_absSigSum, 15, 14)
node _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_7_T)
connect notCDom_reduced2AbsSigSum_reducedVec[7], _notCDom_reduced2AbsSigSum_reducedVec_7_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_8_T = bits(notCDom_absSigSum, 17, 16)
node _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_8_T)
connect notCDom_reduced2AbsSigSum_reducedVec[8], _notCDom_reduced2AbsSigSum_reducedVec_8_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_9_T = bits(notCDom_absSigSum, 19, 18)
node _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_9_T)
connect notCDom_reduced2AbsSigSum_reducedVec[9], _notCDom_reduced2AbsSigSum_reducedVec_9_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_10_T = bits(notCDom_absSigSum, 21, 20)
node _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_10_T)
connect notCDom_reduced2AbsSigSum_reducedVec[10], _notCDom_reduced2AbsSigSum_reducedVec_10_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_11_T = bits(notCDom_absSigSum, 23, 22)
node _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_11_T)
connect notCDom_reduced2AbsSigSum_reducedVec[11], _notCDom_reduced2AbsSigSum_reducedVec_11_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_12_T = bits(notCDom_absSigSum, 25, 24)
node _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_12_T)
connect notCDom_reduced2AbsSigSum_reducedVec[12], _notCDom_reduced2AbsSigSum_reducedVec_12_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_13_T = bits(notCDom_absSigSum, 27, 26)
node _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_13_T)
connect notCDom_reduced2AbsSigSum_reducedVec[13], _notCDom_reduced2AbsSigSum_reducedVec_13_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_14_T = bits(notCDom_absSigSum, 29, 28)
node _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_14_T)
connect notCDom_reduced2AbsSigSum_reducedVec[14], _notCDom_reduced2AbsSigSum_reducedVec_14_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_15_T = bits(notCDom_absSigSum, 31, 30)
node _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_15_T)
connect notCDom_reduced2AbsSigSum_reducedVec[15], _notCDom_reduced2AbsSigSum_reducedVec_15_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_16_T = bits(notCDom_absSigSum, 33, 32)
node _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_16_T)
connect notCDom_reduced2AbsSigSum_reducedVec[16], _notCDom_reduced2AbsSigSum_reducedVec_16_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_17_T = bits(notCDom_absSigSum, 35, 34)
node _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_17_T)
connect notCDom_reduced2AbsSigSum_reducedVec[17], _notCDom_reduced2AbsSigSum_reducedVec_17_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_18_T = bits(notCDom_absSigSum, 37, 36)
node _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_18_T)
connect notCDom_reduced2AbsSigSum_reducedVec[18], _notCDom_reduced2AbsSigSum_reducedVec_18_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_19_T = bits(notCDom_absSigSum, 39, 38)
node _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_19_T)
connect notCDom_reduced2AbsSigSum_reducedVec[19], _notCDom_reduced2AbsSigSum_reducedVec_19_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_20_T = bits(notCDom_absSigSum, 41, 40)
node _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_20_T)
connect notCDom_reduced2AbsSigSum_reducedVec[20], _notCDom_reduced2AbsSigSum_reducedVec_20_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_21_T = bits(notCDom_absSigSum, 43, 42)
node _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_21_T)
connect notCDom_reduced2AbsSigSum_reducedVec[21], _notCDom_reduced2AbsSigSum_reducedVec_21_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_22_T = bits(notCDom_absSigSum, 45, 44)
node _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_22_T)
connect notCDom_reduced2AbsSigSum_reducedVec[22], _notCDom_reduced2AbsSigSum_reducedVec_22_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_23_T = bits(notCDom_absSigSum, 47, 46)
node _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_23_T)
connect notCDom_reduced2AbsSigSum_reducedVec[23], _notCDom_reduced2AbsSigSum_reducedVec_23_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_24_T = bits(notCDom_absSigSum, 49, 48)
node _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_24_T)
connect notCDom_reduced2AbsSigSum_reducedVec[24], _notCDom_reduced2AbsSigSum_reducedVec_24_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_25_T = bits(notCDom_absSigSum, 50, 50)
node _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_25_T)
connect notCDom_reduced2AbsSigSum_reducedVec[25], _notCDom_reduced2AbsSigSum_reducedVec_25_T_1
node notCDom_reduced2AbsSigSum_lo_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[2], notCDom_reduced2AbsSigSum_reducedVec[1])
node notCDom_reduced2AbsSigSum_lo_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[0])
node notCDom_reduced2AbsSigSum_lo_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[5], notCDom_reduced2AbsSigSum_reducedVec[4])
node notCDom_reduced2AbsSigSum_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[3])
node notCDom_reduced2AbsSigSum_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo)
node notCDom_reduced2AbsSigSum_lo_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[8], notCDom_reduced2AbsSigSum_reducedVec[7])
node notCDom_reduced2AbsSigSum_lo_hi_lo = cat(notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[6])
node notCDom_reduced2AbsSigSum_lo_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[10], notCDom_reduced2AbsSigSum_reducedVec[9])
node notCDom_reduced2AbsSigSum_lo_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[12], notCDom_reduced2AbsSigSum_reducedVec[11])
node notCDom_reduced2AbsSigSum_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo)
node notCDom_reduced2AbsSigSum_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo)
node notCDom_reduced2AbsSigSum_lo = cat(notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo)
node notCDom_reduced2AbsSigSum_hi_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[15], notCDom_reduced2AbsSigSum_reducedVec[14])
node notCDom_reduced2AbsSigSum_hi_lo_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[13])
node notCDom_reduced2AbsSigSum_hi_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[18], notCDom_reduced2AbsSigSum_reducedVec[17])
node notCDom_reduced2AbsSigSum_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[16])
node notCDom_reduced2AbsSigSum_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo)
node notCDom_reduced2AbsSigSum_hi_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[21], notCDom_reduced2AbsSigSum_reducedVec[20])
node notCDom_reduced2AbsSigSum_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[19])
node notCDom_reduced2AbsSigSum_hi_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[23], notCDom_reduced2AbsSigSum_reducedVec[22])
node notCDom_reduced2AbsSigSum_hi_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[25], notCDom_reduced2AbsSigSum_reducedVec[24])
node notCDom_reduced2AbsSigSum_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo)
node notCDom_reduced2AbsSigSum_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo)
node notCDom_reduced2AbsSigSum_hi = cat(notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo)
node notCDom_reduced2AbsSigSum = cat(notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo)
node _notCDom_normDistReduced2_T = bits(notCDom_reduced2AbsSigSum, 0, 0)
node _notCDom_normDistReduced2_T_1 = bits(notCDom_reduced2AbsSigSum, 1, 1)
node _notCDom_normDistReduced2_T_2 = bits(notCDom_reduced2AbsSigSum, 2, 2)
node _notCDom_normDistReduced2_T_3 = bits(notCDom_reduced2AbsSigSum, 3, 3)
node _notCDom_normDistReduced2_T_4 = bits(notCDom_reduced2AbsSigSum, 4, 4)
node _notCDom_normDistReduced2_T_5 = bits(notCDom_reduced2AbsSigSum, 5, 5)
node _notCDom_normDistReduced2_T_6 = bits(notCDom_reduced2AbsSigSum, 6, 6)
node _notCDom_normDistReduced2_T_7 = bits(notCDom_reduced2AbsSigSum, 7, 7)
node _notCDom_normDistReduced2_T_8 = bits(notCDom_reduced2AbsSigSum, 8, 8)
node _notCDom_normDistReduced2_T_9 = bits(notCDom_reduced2AbsSigSum, 9, 9)
node _notCDom_normDistReduced2_T_10 = bits(notCDom_reduced2AbsSigSum, 10, 10)
node _notCDom_normDistReduced2_T_11 = bits(notCDom_reduced2AbsSigSum, 11, 11)
node _notCDom_normDistReduced2_T_12 = bits(notCDom_reduced2AbsSigSum, 12, 12)
node _notCDom_normDistReduced2_T_13 = bits(notCDom_reduced2AbsSigSum, 13, 13)
node _notCDom_normDistReduced2_T_14 = bits(notCDom_reduced2AbsSigSum, 14, 14)
node _notCDom_normDistReduced2_T_15 = bits(notCDom_reduced2AbsSigSum, 15, 15)
node _notCDom_normDistReduced2_T_16 = bits(notCDom_reduced2AbsSigSum, 16, 16)
node _notCDom_normDistReduced2_T_17 = bits(notCDom_reduced2AbsSigSum, 17, 17)
node _notCDom_normDistReduced2_T_18 = bits(notCDom_reduced2AbsSigSum, 18, 18)
node _notCDom_normDistReduced2_T_19 = bits(notCDom_reduced2AbsSigSum, 19, 19)
node _notCDom_normDistReduced2_T_20 = bits(notCDom_reduced2AbsSigSum, 20, 20)
node _notCDom_normDistReduced2_T_21 = bits(notCDom_reduced2AbsSigSum, 21, 21)
node _notCDom_normDistReduced2_T_22 = bits(notCDom_reduced2AbsSigSum, 22, 22)
node _notCDom_normDistReduced2_T_23 = bits(notCDom_reduced2AbsSigSum, 23, 23)
node _notCDom_normDistReduced2_T_24 = bits(notCDom_reduced2AbsSigSum, 24, 24)
node _notCDom_normDistReduced2_T_25 = bits(notCDom_reduced2AbsSigSum, 25, 25)
node _notCDom_normDistReduced2_T_26 = mux(_notCDom_normDistReduced2_T_1, UInt<5>(0h18), UInt<5>(0h19))
node _notCDom_normDistReduced2_T_27 = mux(_notCDom_normDistReduced2_T_2, UInt<5>(0h17), _notCDom_normDistReduced2_T_26)
node _notCDom_normDistReduced2_T_28 = mux(_notCDom_normDistReduced2_T_3, UInt<5>(0h16), _notCDom_normDistReduced2_T_27)
node _notCDom_normDistReduced2_T_29 = mux(_notCDom_normDistReduced2_T_4, UInt<5>(0h15), _notCDom_normDistReduced2_T_28)
node _notCDom_normDistReduced2_T_30 = mux(_notCDom_normDistReduced2_T_5, UInt<5>(0h14), _notCDom_normDistReduced2_T_29)
node _notCDom_normDistReduced2_T_31 = mux(_notCDom_normDistReduced2_T_6, UInt<5>(0h13), _notCDom_normDistReduced2_T_30)
node _notCDom_normDistReduced2_T_32 = mux(_notCDom_normDistReduced2_T_7, UInt<5>(0h12), _notCDom_normDistReduced2_T_31)
node _notCDom_normDistReduced2_T_33 = mux(_notCDom_normDistReduced2_T_8, UInt<5>(0h11), _notCDom_normDistReduced2_T_32)
node _notCDom_normDistReduced2_T_34 = mux(_notCDom_normDistReduced2_T_9, UInt<5>(0h10), _notCDom_normDistReduced2_T_33)
node _notCDom_normDistReduced2_T_35 = mux(_notCDom_normDistReduced2_T_10, UInt<4>(0hf), _notCDom_normDistReduced2_T_34)
node _notCDom_normDistReduced2_T_36 = mux(_notCDom_normDistReduced2_T_11, UInt<4>(0he), _notCDom_normDistReduced2_T_35)
node _notCDom_normDistReduced2_T_37 = mux(_notCDom_normDistReduced2_T_12, UInt<4>(0hd), _notCDom_normDistReduced2_T_36)
node _notCDom_normDistReduced2_T_38 = mux(_notCDom_normDistReduced2_T_13, UInt<4>(0hc), _notCDom_normDistReduced2_T_37)
node _notCDom_normDistReduced2_T_39 = mux(_notCDom_normDistReduced2_T_14, UInt<4>(0hb), _notCDom_normDistReduced2_T_38)
node _notCDom_normDistReduced2_T_40 = mux(_notCDom_normDistReduced2_T_15, UInt<4>(0ha), _notCDom_normDistReduced2_T_39)
node _notCDom_normDistReduced2_T_41 = mux(_notCDom_normDistReduced2_T_16, UInt<4>(0h9), _notCDom_normDistReduced2_T_40)
node _notCDom_normDistReduced2_T_42 = mux(_notCDom_normDistReduced2_T_17, UInt<4>(0h8), _notCDom_normDistReduced2_T_41)
node _notCDom_normDistReduced2_T_43 = mux(_notCDom_normDistReduced2_T_18, UInt<3>(0h7), _notCDom_normDistReduced2_T_42)
node _notCDom_normDistReduced2_T_44 = mux(_notCDom_normDistReduced2_T_19, UInt<3>(0h6), _notCDom_normDistReduced2_T_43)
node _notCDom_normDistReduced2_T_45 = mux(_notCDom_normDistReduced2_T_20, UInt<3>(0h5), _notCDom_normDistReduced2_T_44)
node _notCDom_normDistReduced2_T_46 = mux(_notCDom_normDistReduced2_T_21, UInt<3>(0h4), _notCDom_normDistReduced2_T_45)
node _notCDom_normDistReduced2_T_47 = mux(_notCDom_normDistReduced2_T_22, UInt<2>(0h3), _notCDom_normDistReduced2_T_46)
node _notCDom_normDistReduced2_T_48 = mux(_notCDom_normDistReduced2_T_23, UInt<2>(0h2), _notCDom_normDistReduced2_T_47)
node _notCDom_normDistReduced2_T_49 = mux(_notCDom_normDistReduced2_T_24, UInt<1>(0h1), _notCDom_normDistReduced2_T_48)
node notCDom_normDistReduced2 = mux(_notCDom_normDistReduced2_T_25, UInt<1>(0h0), _notCDom_normDistReduced2_T_49)
node notCDom_nearNormDist = shl(notCDom_normDistReduced2, 1)
node _notCDom_sExp_T = cvt(notCDom_nearNormDist)
node _notCDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _notCDom_sExp_T)
node _notCDom_sExp_T_2 = tail(_notCDom_sExp_T_1, 1)
node notCDom_sExp = asSInt(_notCDom_sExp_T_2)
node _notCDom_mainSig_T = dshl(notCDom_absSigSum, notCDom_nearNormDist)
node notCDom_mainSig = bits(_notCDom_mainSig_T, 51, 23)
node _notCDom_reduced4SigExtra_T = bits(notCDom_reduced2AbsSigSum, 12, 0)
node _notCDom_reduced4SigExtra_T_1 = shl(_notCDom_reduced4SigExtra_T, 0)
wire notCDom_reduced4SigExtra_reducedVec : UInt<1>[7]
node _notCDom_reduced4SigExtra_reducedVec_0_T = bits(_notCDom_reduced4SigExtra_T_1, 1, 0)
node _notCDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_0_T)
connect notCDom_reduced4SigExtra_reducedVec[0], _notCDom_reduced4SigExtra_reducedVec_0_T_1
node _notCDom_reduced4SigExtra_reducedVec_1_T = bits(_notCDom_reduced4SigExtra_T_1, 3, 2)
node _notCDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_1_T)
connect notCDom_reduced4SigExtra_reducedVec[1], _notCDom_reduced4SigExtra_reducedVec_1_T_1
node _notCDom_reduced4SigExtra_reducedVec_2_T = bits(_notCDom_reduced4SigExtra_T_1, 5, 4)
node _notCDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_2_T)
connect notCDom_reduced4SigExtra_reducedVec[2], _notCDom_reduced4SigExtra_reducedVec_2_T_1
node _notCDom_reduced4SigExtra_reducedVec_3_T = bits(_notCDom_reduced4SigExtra_T_1, 7, 6)
node _notCDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_3_T)
connect notCDom_reduced4SigExtra_reducedVec[3], _notCDom_reduced4SigExtra_reducedVec_3_T_1
node _notCDom_reduced4SigExtra_reducedVec_4_T = bits(_notCDom_reduced4SigExtra_T_1, 9, 8)
node _notCDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_4_T)
connect notCDom_reduced4SigExtra_reducedVec[4], _notCDom_reduced4SigExtra_reducedVec_4_T_1
node _notCDom_reduced4SigExtra_reducedVec_5_T = bits(_notCDom_reduced4SigExtra_T_1, 11, 10)
node _notCDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_5_T)
connect notCDom_reduced4SigExtra_reducedVec[5], _notCDom_reduced4SigExtra_reducedVec_5_T_1
node _notCDom_reduced4SigExtra_reducedVec_6_T = bits(_notCDom_reduced4SigExtra_T_1, 12, 12)
node _notCDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_6_T)
connect notCDom_reduced4SigExtra_reducedVec[6], _notCDom_reduced4SigExtra_reducedVec_6_T_1
node notCDom_reduced4SigExtra_lo_hi = cat(notCDom_reduced4SigExtra_reducedVec[2], notCDom_reduced4SigExtra_reducedVec[1])
node notCDom_reduced4SigExtra_lo = cat(notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec[0])
node notCDom_reduced4SigExtra_hi_lo = cat(notCDom_reduced4SigExtra_reducedVec[4], notCDom_reduced4SigExtra_reducedVec[3])
node notCDom_reduced4SigExtra_hi_hi = cat(notCDom_reduced4SigExtra_reducedVec[6], notCDom_reduced4SigExtra_reducedVec[5])
node notCDom_reduced4SigExtra_hi = cat(notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo)
node _notCDom_reduced4SigExtra_T_2 = cat(notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo)
node _notCDom_reduced4SigExtra_T_3 = shr(notCDom_normDistReduced2, 1)
node _notCDom_reduced4SigExtra_T_4 = not(_notCDom_reduced4SigExtra_T_3)
node notCDom_reduced4SigExtra_shift = dshr(asSInt(UInt<17>(0h10000)), _notCDom_reduced4SigExtra_T_4)
node _notCDom_reduced4SigExtra_T_5 = bits(notCDom_reduced4SigExtra_shift, 6, 1)
node _notCDom_reduced4SigExtra_T_6 = bits(_notCDom_reduced4SigExtra_T_5, 3, 0)
node _notCDom_reduced4SigExtra_T_7 = bits(_notCDom_reduced4SigExtra_T_6, 1, 0)
node _notCDom_reduced4SigExtra_T_8 = bits(_notCDom_reduced4SigExtra_T_7, 0, 0)
node _notCDom_reduced4SigExtra_T_9 = bits(_notCDom_reduced4SigExtra_T_7, 1, 1)
node _notCDom_reduced4SigExtra_T_10 = cat(_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9)
node _notCDom_reduced4SigExtra_T_11 = bits(_notCDom_reduced4SigExtra_T_6, 3, 2)
node _notCDom_reduced4SigExtra_T_12 = bits(_notCDom_reduced4SigExtra_T_11, 0, 0)
node _notCDom_reduced4SigExtra_T_13 = bits(_notCDom_reduced4SigExtra_T_11, 1, 1)
node _notCDom_reduced4SigExtra_T_14 = cat(_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13)
node _notCDom_reduced4SigExtra_T_15 = cat(_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14)
node _notCDom_reduced4SigExtra_T_16 = bits(_notCDom_reduced4SigExtra_T_5, 5, 4)
node _notCDom_reduced4SigExtra_T_17 = bits(_notCDom_reduced4SigExtra_T_16, 0, 0)
node _notCDom_reduced4SigExtra_T_18 = bits(_notCDom_reduced4SigExtra_T_16, 1, 1)
node _notCDom_reduced4SigExtra_T_19 = cat(_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18)
node _notCDom_reduced4SigExtra_T_20 = cat(_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19)
node _notCDom_reduced4SigExtra_T_21 = and(_notCDom_reduced4SigExtra_T_2, _notCDom_reduced4SigExtra_T_20)
node notCDom_reduced4SigExtra = orr(_notCDom_reduced4SigExtra_T_21)
node _notCDom_sig_T = shr(notCDom_mainSig, 3)
node _notCDom_sig_T_1 = bits(notCDom_mainSig, 2, 0)
node _notCDom_sig_T_2 = orr(_notCDom_sig_T_1)
node _notCDom_sig_T_3 = or(_notCDom_sig_T_2, notCDom_reduced4SigExtra)
node notCDom_sig = cat(_notCDom_sig_T, _notCDom_sig_T_3)
node _notCDom_completeCancellation_T = bits(notCDom_sig, 26, 25)
node notCDom_completeCancellation = eq(_notCDom_completeCancellation_T, UInt<1>(0h0))
node _notCDom_sign_T = xor(io.fromPreMul.signProd, notCDom_signSigSum)
node notCDom_sign = mux(notCDom_completeCancellation, roundingMode_min, _notCDom_sign_T)
node notNaN_isInfProd = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB)
node notNaN_isInfOut = or(notNaN_isInfProd, io.fromPreMul.isInfC)
node _notNaN_addZeros_T = or(io.fromPreMul.isZeroA, io.fromPreMul.isZeroB)
node notNaN_addZeros = and(_notNaN_addZeros_T, io.fromPreMul.isZeroC)
node _io_invalidExc_T = and(io.fromPreMul.isInfA, io.fromPreMul.isZeroB)
node _io_invalidExc_T_1 = or(io.fromPreMul.isSigNaNAny, _io_invalidExc_T)
node _io_invalidExc_T_2 = and(io.fromPreMul.isZeroA, io.fromPreMul.isInfB)
node _io_invalidExc_T_3 = or(_io_invalidExc_T_1, _io_invalidExc_T_2)
node _io_invalidExc_T_4 = eq(io.fromPreMul.isNaNAOrB, UInt<1>(0h0))
node _io_invalidExc_T_5 = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB)
node _io_invalidExc_T_6 = and(_io_invalidExc_T_4, _io_invalidExc_T_5)
node _io_invalidExc_T_7 = and(_io_invalidExc_T_6, io.fromPreMul.isInfC)
node _io_invalidExc_T_8 = and(_io_invalidExc_T_7, io.fromPreMul.doSubMags)
node _io_invalidExc_T_9 = or(_io_invalidExc_T_3, _io_invalidExc_T_8)
connect io.invalidExc, _io_invalidExc_T_9
node _io_rawOut_isNaN_T = or(io.fromPreMul.isNaNAOrB, io.fromPreMul.isNaNC)
connect io.rawOut.isNaN, _io_rawOut_isNaN_T
connect io.rawOut.isInf, notNaN_isInfOut
node _io_rawOut_isZero_T = eq(io.fromPreMul.CIsDominant, UInt<1>(0h0))
node _io_rawOut_isZero_T_1 = and(_io_rawOut_isZero_T, notCDom_completeCancellation)
node _io_rawOut_isZero_T_2 = or(notNaN_addZeros, _io_rawOut_isZero_T_1)
connect io.rawOut.isZero, _io_rawOut_isZero_T_2
node _io_rawOut_sign_T = and(notNaN_isInfProd, io.fromPreMul.signProd)
node _io_rawOut_sign_T_1 = and(io.fromPreMul.isInfC, opSignC)
node _io_rawOut_sign_T_2 = or(_io_rawOut_sign_T, _io_rawOut_sign_T_1)
node _io_rawOut_sign_T_3 = eq(roundingMode_min, UInt<1>(0h0))
node _io_rawOut_sign_T_4 = and(notNaN_addZeros, _io_rawOut_sign_T_3)
node _io_rawOut_sign_T_5 = and(_io_rawOut_sign_T_4, io.fromPreMul.signProd)
node _io_rawOut_sign_T_6 = and(_io_rawOut_sign_T_5, opSignC)
node _io_rawOut_sign_T_7 = or(_io_rawOut_sign_T_2, _io_rawOut_sign_T_6)
node _io_rawOut_sign_T_8 = and(notNaN_addZeros, roundingMode_min)
node _io_rawOut_sign_T_9 = or(io.fromPreMul.signProd, opSignC)
node _io_rawOut_sign_T_10 = and(_io_rawOut_sign_T_8, _io_rawOut_sign_T_9)
node _io_rawOut_sign_T_11 = or(_io_rawOut_sign_T_7, _io_rawOut_sign_T_10)
node _io_rawOut_sign_T_12 = eq(notNaN_isInfOut, UInt<1>(0h0))
node _io_rawOut_sign_T_13 = eq(notNaN_addZeros, UInt<1>(0h0))
node _io_rawOut_sign_T_14 = and(_io_rawOut_sign_T_12, _io_rawOut_sign_T_13)
node _io_rawOut_sign_T_15 = mux(io.fromPreMul.CIsDominant, opSignC, notCDom_sign)
node _io_rawOut_sign_T_16 = and(_io_rawOut_sign_T_14, _io_rawOut_sign_T_15)
node _io_rawOut_sign_T_17 = or(_io_rawOut_sign_T_11, _io_rawOut_sign_T_16)
connect io.rawOut.sign, _io_rawOut_sign_T_17
node _io_rawOut_sExp_T = mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp)
connect io.rawOut.sExp, _io_rawOut_sExp_T
node _io_rawOut_sig_T = mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig)
connect io.rawOut.sig, _io_rawOut_sig_T | module MulAddRecFNToRaw_postMul_e8_s24_13( // @[MulAddRecFN.scala:169:7]
input io_fromPreMul_isSigNaNAny, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isNaNAOrB, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isInfA, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isZeroA, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_signProd, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isNaNC, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isInfC, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isZeroC, // @[MulAddRecFN.scala:172:16]
input [9:0] io_fromPreMul_sExpSum, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_doSubMags, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_CIsDominant, // @[MulAddRecFN.scala:172:16]
input [4:0] io_fromPreMul_CDom_CAlignDist, // @[MulAddRecFN.scala:172:16]
input [25:0] io_fromPreMul_highAlignedSigC, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_bit0AlignedSigC, // @[MulAddRecFN.scala:172:16]
input [48:0] io_mulAddResult, // @[MulAddRecFN.scala:172:16]
output io_invalidExc, // @[MulAddRecFN.scala:172:16]
output io_rawOut_isNaN, // @[MulAddRecFN.scala:172:16]
output io_rawOut_isInf, // @[MulAddRecFN.scala:172:16]
output io_rawOut_isZero, // @[MulAddRecFN.scala:172:16]
output io_rawOut_sign, // @[MulAddRecFN.scala:172:16]
output [9:0] io_rawOut_sExp, // @[MulAddRecFN.scala:172:16]
output [26:0] io_rawOut_sig // @[MulAddRecFN.scala:172:16]
);
wire io_fromPreMul_isSigNaNAny_0 = io_fromPreMul_isSigNaNAny; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isNaNAOrB_0 = io_fromPreMul_isNaNAOrB; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isInfA_0 = io_fromPreMul_isInfA; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isZeroA_0 = io_fromPreMul_isZeroA; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_signProd_0 = io_fromPreMul_signProd; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isNaNC_0 = io_fromPreMul_isNaNC; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isInfC_0 = io_fromPreMul_isInfC; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isZeroC_0 = io_fromPreMul_isZeroC; // @[MulAddRecFN.scala:169:7]
wire [9:0] io_fromPreMul_sExpSum_0 = io_fromPreMul_sExpSum; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_doSubMags_0 = io_fromPreMul_doSubMags; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_CIsDominant_0 = io_fromPreMul_CIsDominant; // @[MulAddRecFN.scala:169:7]
wire [4:0] io_fromPreMul_CDom_CAlignDist_0 = io_fromPreMul_CDom_CAlignDist; // @[MulAddRecFN.scala:169:7]
wire [25:0] io_fromPreMul_highAlignedSigC_0 = io_fromPreMul_highAlignedSigC; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_bit0AlignedSigC_0 = io_fromPreMul_bit0AlignedSigC; // @[MulAddRecFN.scala:169:7]
wire [48:0] io_mulAddResult_0 = io_mulAddResult; // @[MulAddRecFN.scala:169:7]
wire _io_rawOut_sign_T_3 = 1'h1; // @[MulAddRecFN.scala:287:29]
wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:169:7, :172:16]
wire io_fromPreMul_isInfB = 1'h0; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isZeroB = 1'h0; // @[MulAddRecFN.scala:169:7]
wire roundingMode_min = 1'h0; // @[MulAddRecFN.scala:186:45]
wire _io_invalidExc_T = 1'h0; // @[MulAddRecFN.scala:272:31]
wire _io_invalidExc_T_2 = 1'h0; // @[MulAddRecFN.scala:273:32]
wire _io_rawOut_sign_T_8 = 1'h0; // @[MulAddRecFN.scala:289:26]
wire _io_rawOut_sign_T_10 = 1'h0; // @[MulAddRecFN.scala:289:46]
wire _io_invalidExc_T_1 = io_fromPreMul_isSigNaNAny_0; // @[MulAddRecFN.scala:169:7, :271:35]
wire notNaN_isInfProd = io_fromPreMul_isInfA_0; // @[MulAddRecFN.scala:169:7, :264:49]
wire _io_invalidExc_T_5 = io_fromPreMul_isInfA_0; // @[MulAddRecFN.scala:169:7, :275:36]
wire _notNaN_addZeros_T = io_fromPreMul_isZeroA_0; // @[MulAddRecFN.scala:169:7, :267:32]
wire _io_invalidExc_T_9; // @[MulAddRecFN.scala:273:57]
wire _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:278:48]
wire notNaN_isInfOut; // @[MulAddRecFN.scala:265:44]
wire _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:282:25]
wire _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:290:50]
wire [9:0] _io_rawOut_sExp_T; // @[MulAddRecFN.scala:293:26]
wire [26:0] _io_rawOut_sig_T; // @[MulAddRecFN.scala:294:25]
wire io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7]
wire io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7]
wire io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7]
wire io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7]
wire [9:0] io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7]
wire [26:0] io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7]
wire io_invalidExc_0; // @[MulAddRecFN.scala:169:7]
wire opSignC = io_fromPreMul_signProd_0 ^ io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :190:42]
wire _sigSum_T = io_mulAddResult_0[48]; // @[MulAddRecFN.scala:169:7, :192:32]
wire [26:0] _sigSum_T_1 = {1'h0, io_fromPreMul_highAlignedSigC_0} + 27'h1; // @[MulAddRecFN.scala:169:7, :193:47]
wire [25:0] _sigSum_T_2 = _sigSum_T_1[25:0]; // @[MulAddRecFN.scala:193:47]
wire [25:0] _sigSum_T_3 = _sigSum_T ? _sigSum_T_2 : io_fromPreMul_highAlignedSigC_0; // @[MulAddRecFN.scala:169:7, :192:{16,32}, :193:47]
wire [47:0] _sigSum_T_4 = io_mulAddResult_0[47:0]; // @[MulAddRecFN.scala:169:7, :196:28]
wire [73:0] sigSum_hi = {_sigSum_T_3, _sigSum_T_4}; // @[MulAddRecFN.scala:192:{12,16}, :196:28]
wire [74:0] sigSum = {sigSum_hi, io_fromPreMul_bit0AlignedSigC_0}; // @[MulAddRecFN.scala:169:7, :192:12]
wire [1:0] _CDom_sExp_T = {1'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :203:69]
wire [10:0] _GEN = {io_fromPreMul_sExpSum_0[9], io_fromPreMul_sExpSum_0}; // @[MulAddRecFN.scala:169:7, :203:43]
wire [10:0] _CDom_sExp_T_1 = _GEN - {{9{_CDom_sExp_T[1]}}, _CDom_sExp_T}; // @[MulAddRecFN.scala:203:{43,69}]
wire [9:0] _CDom_sExp_T_2 = _CDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:203:43]
wire [9:0] CDom_sExp = _CDom_sExp_T_2; // @[MulAddRecFN.scala:203:43]
wire [49:0] _CDom_absSigSum_T = sigSum[74:25]; // @[MulAddRecFN.scala:192:12, :206:20]
wire [49:0] _CDom_absSigSum_T_1 = ~_CDom_absSigSum_T; // @[MulAddRecFN.scala:206:{13,20}]
wire [1:0] _CDom_absSigSum_T_2 = io_fromPreMul_highAlignedSigC_0[25:24]; // @[MulAddRecFN.scala:169:7, :209:46]
wire [2:0] _CDom_absSigSum_T_3 = {1'h0, _CDom_absSigSum_T_2}; // @[MulAddRecFN.scala:207:22, :209:46]
wire [46:0] _CDom_absSigSum_T_4 = sigSum[72:26]; // @[MulAddRecFN.scala:192:12, :210:23]
wire [49:0] _CDom_absSigSum_T_5 = {_CDom_absSigSum_T_3, _CDom_absSigSum_T_4}; // @[MulAddRecFN.scala:207:22, :209:71, :210:23]
wire [49:0] CDom_absSigSum = io_fromPreMul_doSubMags_0 ? _CDom_absSigSum_T_1 : _CDom_absSigSum_T_5; // @[MulAddRecFN.scala:169:7, :205:12, :206:13, :209:71]
wire [23:0] _CDom_absSigSumExtra_T = sigSum[24:1]; // @[MulAddRecFN.scala:192:12, :215:21]
wire [23:0] _CDom_absSigSumExtra_T_1 = ~_CDom_absSigSumExtra_T; // @[MulAddRecFN.scala:215:{14,21}]
wire _CDom_absSigSumExtra_T_2 = |_CDom_absSigSumExtra_T_1; // @[MulAddRecFN.scala:215:{14,36}]
wire [24:0] _CDom_absSigSumExtra_T_3 = sigSum[25:1]; // @[MulAddRecFN.scala:192:12, :216:19]
wire _CDom_absSigSumExtra_T_4 = |_CDom_absSigSumExtra_T_3; // @[MulAddRecFN.scala:216:{19,37}]
wire CDom_absSigSumExtra = io_fromPreMul_doSubMags_0 ? _CDom_absSigSumExtra_T_2 : _CDom_absSigSumExtra_T_4; // @[MulAddRecFN.scala:169:7, :214:12, :215:36, :216:37]
wire [80:0] _CDom_mainSig_T = {31'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:169:7, :205:12, :219:24]
wire [28:0] CDom_mainSig = _CDom_mainSig_T[49:21]; // @[MulAddRecFN.scala:219:{24,56}]
wire [23:0] _CDom_reduced4SigExtra_T = CDom_absSigSum[23:0]; // @[MulAddRecFN.scala:205:12, :222:36]
wire [26:0] _CDom_reduced4SigExtra_T_1 = {_CDom_reduced4SigExtra_T, 3'h0}; // @[MulAddRecFN.scala:169:7, :172:16, :222:{36,53}]
wire _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:123:57]
wire CDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:118:30]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_0_T = _CDom_reduced4SigExtra_T_1[3:0]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_0_T_1 = |_CDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_0 = _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_1_T = _CDom_reduced4SigExtra_T_1[7:4]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_1_T_1 = |_CDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_1 = _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_2_T = _CDom_reduced4SigExtra_T_1[11:8]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_2_T_1 = |_CDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_2 = _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_3_T = _CDom_reduced4SigExtra_T_1[15:12]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_3_T_1 = |_CDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_3 = _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_4_T = _CDom_reduced4SigExtra_T_1[19:16]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_4_T_1 = |_CDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_4 = _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_5_T = _CDom_reduced4SigExtra_T_1[23:20]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_5_T_1 = |_CDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_5 = _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54]
wire [2:0] _CDom_reduced4SigExtra_reducedVec_6_T = _CDom_reduced4SigExtra_T_1[26:24]; // @[primitives.scala:123:15]
assign _CDom_reduced4SigExtra_reducedVec_6_T_1 = |_CDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}]
assign CDom_reduced4SigExtra_reducedVec_6 = _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57]
wire [1:0] CDom_reduced4SigExtra_lo_hi = {CDom_reduced4SigExtra_reducedVec_2, CDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20]
wire [2:0] CDom_reduced4SigExtra_lo = {CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20]
wire [1:0] CDom_reduced4SigExtra_hi_lo = {CDom_reduced4SigExtra_reducedVec_4, CDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20]
wire [1:0] CDom_reduced4SigExtra_hi_hi = {CDom_reduced4SigExtra_reducedVec_6, CDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20]
wire [3:0] CDom_reduced4SigExtra_hi = {CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:124:20]
wire [6:0] _CDom_reduced4SigExtra_T_2 = {CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo}; // @[primitives.scala:124:20]
wire [2:0] _CDom_reduced4SigExtra_T_3 = io_fromPreMul_CDom_CAlignDist_0[4:2]; // @[MulAddRecFN.scala:169:7, :223:51]
wire [2:0] _CDom_reduced4SigExtra_T_4 = ~_CDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21]
wire [8:0] CDom_reduced4SigExtra_shift = $signed(9'sh100 >>> _CDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56]
wire [5:0] _CDom_reduced4SigExtra_T_5 = CDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22]
wire [3:0] _CDom_reduced4SigExtra_T_6 = _CDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22]
wire [1:0] _CDom_reduced4SigExtra_T_7 = _CDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_8 = _CDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_9 = _CDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_10 = {_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_11 = _CDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_12 = _CDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_13 = _CDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_14 = {_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20]
wire [3:0] _CDom_reduced4SigExtra_T_15 = {_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_16 = _CDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22]
wire _CDom_reduced4SigExtra_T_17 = _CDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_18 = _CDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_19 = {_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20]
wire [5:0] _CDom_reduced4SigExtra_T_20 = {_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20]
wire [6:0] _CDom_reduced4SigExtra_T_21 = {1'h0, _CDom_reduced4SigExtra_T_2[5:0] & _CDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :124:20]
wire CDom_reduced4SigExtra = |_CDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:222:72, :223:73]
wire [25:0] _CDom_sig_T = CDom_mainSig[28:3]; // @[MulAddRecFN.scala:219:56, :225:25]
wire [2:0] _CDom_sig_T_1 = CDom_mainSig[2:0]; // @[MulAddRecFN.scala:219:56, :226:25]
wire _CDom_sig_T_2 = |_CDom_sig_T_1; // @[MulAddRecFN.scala:226:{25,32}]
wire _CDom_sig_T_3 = _CDom_sig_T_2 | CDom_reduced4SigExtra; // @[MulAddRecFN.scala:223:73, :226:{32,36}]
wire _CDom_sig_T_4 = _CDom_sig_T_3 | CDom_absSigSumExtra; // @[MulAddRecFN.scala:214:12, :226:{36,61}]
wire [26:0] CDom_sig = {_CDom_sig_T, _CDom_sig_T_4}; // @[MulAddRecFN.scala:225:{12,25}, :226:61]
wire notCDom_signSigSum = sigSum[51]; // @[MulAddRecFN.scala:192:12, :232:36]
wire [50:0] _notCDom_absSigSum_T = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20]
wire [50:0] _notCDom_absSigSum_T_2 = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20, :236:19]
wire [50:0] _notCDom_absSigSum_T_1 = ~_notCDom_absSigSum_T; // @[MulAddRecFN.scala:235:{13,20}]
wire [51:0] _notCDom_absSigSum_T_3 = {1'h0, _notCDom_absSigSum_T_2} + {51'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :236:{19,41}]
wire [50:0] _notCDom_absSigSum_T_4 = _notCDom_absSigSum_T_3[50:0]; // @[MulAddRecFN.scala:236:41]
wire [50:0] notCDom_absSigSum = notCDom_signSigSum ? _notCDom_absSigSum_T_1 : _notCDom_absSigSum_T_4; // @[MulAddRecFN.scala:232:36, :234:12, :235:13, :236:41]
wire _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:106:57]
wire notCDom_reduced2AbsSigSum_reducedVec_0; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_1; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_2; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_3; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_4; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_5; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_6; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_7; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_8; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_9; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_10; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_11; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_12; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_13; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_14; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_15; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_16; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_17; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_18; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_19; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_20; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_21; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_22; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_23; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_24; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_25; // @[primitives.scala:101:30]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_0_T = notCDom_absSigSum[1:0]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_0_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_0 = _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_1_T = notCDom_absSigSum[3:2]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_1_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_1 = _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_2_T = notCDom_absSigSum[5:4]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_2_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_2 = _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_3_T = notCDom_absSigSum[7:6]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_3_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_3 = _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_4_T = notCDom_absSigSum[9:8]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_4_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_4 = _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_5_T = notCDom_absSigSum[11:10]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_5_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_5 = _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_6_T = notCDom_absSigSum[13:12]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_6_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_6 = _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_7_T = notCDom_absSigSum[15:14]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_7_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_7 = _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_8_T = notCDom_absSigSum[17:16]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_8_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_8 = _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_9_T = notCDom_absSigSum[19:18]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_9_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_9 = _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_10_T = notCDom_absSigSum[21:20]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_10_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_10 = _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_11_T = notCDom_absSigSum[23:22]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_11_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_11 = _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_12_T = notCDom_absSigSum[25:24]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_12_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_12 = _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_13_T = notCDom_absSigSum[27:26]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_13_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_13 = _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_14_T = notCDom_absSigSum[29:28]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_14_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_14 = _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_15_T = notCDom_absSigSum[31:30]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_15_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_15 = _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_16_T = notCDom_absSigSum[33:32]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_16_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_16 = _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_17_T = notCDom_absSigSum[35:34]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_17_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_17 = _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_18_T = notCDom_absSigSum[37:36]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_18_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_18 = _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_19_T = notCDom_absSigSum[39:38]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_19_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_19 = _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_20_T = notCDom_absSigSum[41:40]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_20_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_20 = _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_21_T = notCDom_absSigSum[43:42]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_21_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_21 = _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_22_T = notCDom_absSigSum[45:44]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_22_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_22 = _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_23_T = notCDom_absSigSum[47:46]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_23_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_23 = _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_24_T = notCDom_absSigSum[49:48]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_24_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_24 = _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:101:30, :103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_25_T = notCDom_absSigSum[50]; // @[primitives.scala:106:15]
assign _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = _notCDom_reduced2AbsSigSum_reducedVec_25_T; // @[primitives.scala:106:{15,57}]
assign notCDom_reduced2AbsSigSum_reducedVec_25 = _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:101:30, :106:57]
wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_2, notCDom_reduced2AbsSigSum_reducedVec_1}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_0}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_5, notCDom_reduced2AbsSigSum_reducedVec_4}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_hi = {notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_3}; // @[primitives.scala:101:30, :107:20]
wire [5:0] notCDom_reduced2AbsSigSum_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo}; // @[primitives.scala:107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_8, notCDom_reduced2AbsSigSum_reducedVec_7}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_lo_hi_lo = {notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_6}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_10, notCDom_reduced2AbsSigSum_reducedVec_9}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_12, notCDom_reduced2AbsSigSum_reducedVec_11}; // @[primitives.scala:101:30, :107:20]
wire [3:0] notCDom_reduced2AbsSigSum_lo_hi_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo}; // @[primitives.scala:107:20]
wire [6:0] notCDom_reduced2AbsSigSum_lo_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo}; // @[primitives.scala:107:20]
wire [12:0] notCDom_reduced2AbsSigSum_lo = {notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo}; // @[primitives.scala:107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_15, notCDom_reduced2AbsSigSum_reducedVec_14}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_lo = {notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_13}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_18, notCDom_reduced2AbsSigSum_reducedVec_17}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_hi = {notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_16}; // @[primitives.scala:101:30, :107:20]
wire [5:0] notCDom_reduced2AbsSigSum_hi_lo = {notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo}; // @[primitives.scala:107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_21, notCDom_reduced2AbsSigSum_reducedVec_20}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_hi_hi_lo = {notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_19}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_23, notCDom_reduced2AbsSigSum_reducedVec_22}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_25, notCDom_reduced2AbsSigSum_reducedVec_24}; // @[primitives.scala:101:30, :107:20]
wire [3:0] notCDom_reduced2AbsSigSum_hi_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo}; // @[primitives.scala:107:20]
wire [6:0] notCDom_reduced2AbsSigSum_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo}; // @[primitives.scala:107:20]
wire [12:0] notCDom_reduced2AbsSigSum_hi = {notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo}; // @[primitives.scala:107:20]
wire [25:0] notCDom_reduced2AbsSigSum = {notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo}; // @[primitives.scala:107:20]
wire _notCDom_normDistReduced2_T = notCDom_reduced2AbsSigSum[0]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_1 = notCDom_reduced2AbsSigSum[1]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_2 = notCDom_reduced2AbsSigSum[2]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_3 = notCDom_reduced2AbsSigSum[3]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_4 = notCDom_reduced2AbsSigSum[4]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_5 = notCDom_reduced2AbsSigSum[5]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_6 = notCDom_reduced2AbsSigSum[6]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_7 = notCDom_reduced2AbsSigSum[7]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_8 = notCDom_reduced2AbsSigSum[8]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_9 = notCDom_reduced2AbsSigSum[9]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_10 = notCDom_reduced2AbsSigSum[10]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_11 = notCDom_reduced2AbsSigSum[11]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_12 = notCDom_reduced2AbsSigSum[12]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_13 = notCDom_reduced2AbsSigSum[13]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_14 = notCDom_reduced2AbsSigSum[14]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_15 = notCDom_reduced2AbsSigSum[15]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_16 = notCDom_reduced2AbsSigSum[16]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_17 = notCDom_reduced2AbsSigSum[17]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_18 = notCDom_reduced2AbsSigSum[18]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_19 = notCDom_reduced2AbsSigSum[19]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_20 = notCDom_reduced2AbsSigSum[20]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_21 = notCDom_reduced2AbsSigSum[21]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_22 = notCDom_reduced2AbsSigSum[22]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_23 = notCDom_reduced2AbsSigSum[23]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_24 = notCDom_reduced2AbsSigSum[24]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_25 = notCDom_reduced2AbsSigSum[25]; // @[primitives.scala:91:52, :107:20]
wire [4:0] _notCDom_normDistReduced2_T_26 = {4'hC, ~_notCDom_normDistReduced2_T_1}; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_27 = _notCDom_normDistReduced2_T_2 ? 5'h17 : _notCDom_normDistReduced2_T_26; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_28 = _notCDom_normDistReduced2_T_3 ? 5'h16 : _notCDom_normDistReduced2_T_27; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_29 = _notCDom_normDistReduced2_T_4 ? 5'h15 : _notCDom_normDistReduced2_T_28; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_30 = _notCDom_normDistReduced2_T_5 ? 5'h14 : _notCDom_normDistReduced2_T_29; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_31 = _notCDom_normDistReduced2_T_6 ? 5'h13 : _notCDom_normDistReduced2_T_30; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_32 = _notCDom_normDistReduced2_T_7 ? 5'h12 : _notCDom_normDistReduced2_T_31; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_33 = _notCDom_normDistReduced2_T_8 ? 5'h11 : _notCDom_normDistReduced2_T_32; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_34 = _notCDom_normDistReduced2_T_9 ? 5'h10 : _notCDom_normDistReduced2_T_33; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_35 = _notCDom_normDistReduced2_T_10 ? 5'hF : _notCDom_normDistReduced2_T_34; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_36 = _notCDom_normDistReduced2_T_11 ? 5'hE : _notCDom_normDistReduced2_T_35; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_37 = _notCDom_normDistReduced2_T_12 ? 5'hD : _notCDom_normDistReduced2_T_36; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_38 = _notCDom_normDistReduced2_T_13 ? 5'hC : _notCDom_normDistReduced2_T_37; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_39 = _notCDom_normDistReduced2_T_14 ? 5'hB : _notCDom_normDistReduced2_T_38; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_40 = _notCDom_normDistReduced2_T_15 ? 5'hA : _notCDom_normDistReduced2_T_39; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_41 = _notCDom_normDistReduced2_T_16 ? 5'h9 : _notCDom_normDistReduced2_T_40; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_42 = _notCDom_normDistReduced2_T_17 ? 5'h8 : _notCDom_normDistReduced2_T_41; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_43 = _notCDom_normDistReduced2_T_18 ? 5'h7 : _notCDom_normDistReduced2_T_42; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_44 = _notCDom_normDistReduced2_T_19 ? 5'h6 : _notCDom_normDistReduced2_T_43; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_45 = _notCDom_normDistReduced2_T_20 ? 5'h5 : _notCDom_normDistReduced2_T_44; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_46 = _notCDom_normDistReduced2_T_21 ? 5'h4 : _notCDom_normDistReduced2_T_45; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_47 = _notCDom_normDistReduced2_T_22 ? 5'h3 : _notCDom_normDistReduced2_T_46; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_48 = _notCDom_normDistReduced2_T_23 ? 5'h2 : _notCDom_normDistReduced2_T_47; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_49 = _notCDom_normDistReduced2_T_24 ? 5'h1 : _notCDom_normDistReduced2_T_48; // @[Mux.scala:50:70]
wire [4:0] notCDom_normDistReduced2 = _notCDom_normDistReduced2_T_25 ? 5'h0 : _notCDom_normDistReduced2_T_49; // @[Mux.scala:50:70]
wire [5:0] notCDom_nearNormDist = {notCDom_normDistReduced2, 1'h0}; // @[Mux.scala:50:70]
wire [6:0] _notCDom_sExp_T = {1'h0, notCDom_nearNormDist}; // @[MulAddRecFN.scala:240:56, :241:76]
wire [10:0] _notCDom_sExp_T_1 = _GEN - {{4{_notCDom_sExp_T[6]}}, _notCDom_sExp_T}; // @[MulAddRecFN.scala:203:43, :241:{46,76}]
wire [9:0] _notCDom_sExp_T_2 = _notCDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:241:46]
wire [9:0] notCDom_sExp = _notCDom_sExp_T_2; // @[MulAddRecFN.scala:241:46]
wire [113:0] _notCDom_mainSig_T = {63'h0, notCDom_absSigSum} << notCDom_nearNormDist; // @[MulAddRecFN.scala:234:12, :240:56, :243:27]
wire [28:0] notCDom_mainSig = _notCDom_mainSig_T[51:23]; // @[MulAddRecFN.scala:243:{27,50}]
wire [12:0] _notCDom_reduced4SigExtra_T = notCDom_reduced2AbsSigSum[12:0]; // @[primitives.scala:107:20]
wire [12:0] _notCDom_reduced4SigExtra_T_1 = _notCDom_reduced4SigExtra_T; // @[MulAddRecFN.scala:247:{39,55}]
wire _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:106:57]
wire notCDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:101:30]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_0_T = _notCDom_reduced4SigExtra_T_1[1:0]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_0_T_1 = |_notCDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_0 = _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_1_T = _notCDom_reduced4SigExtra_T_1[3:2]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_1_T_1 = |_notCDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_1 = _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_2_T = _notCDom_reduced4SigExtra_T_1[5:4]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_2_T_1 = |_notCDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_2 = _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_3_T = _notCDom_reduced4SigExtra_T_1[7:6]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_3_T_1 = |_notCDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_3 = _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_4_T = _notCDom_reduced4SigExtra_T_1[9:8]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_4_T_1 = |_notCDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_4 = _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_5_T = _notCDom_reduced4SigExtra_T_1[11:10]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_5_T_1 = |_notCDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_5 = _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54]
wire _notCDom_reduced4SigExtra_reducedVec_6_T = _notCDom_reduced4SigExtra_T_1[12]; // @[primitives.scala:106:15]
assign _notCDom_reduced4SigExtra_reducedVec_6_T_1 = _notCDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:106:{15,57}]
assign notCDom_reduced4SigExtra_reducedVec_6 = _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:101:30, :106:57]
wire [1:0] notCDom_reduced4SigExtra_lo_hi = {notCDom_reduced4SigExtra_reducedVec_2, notCDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced4SigExtra_lo = {notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced4SigExtra_hi_lo = {notCDom_reduced4SigExtra_reducedVec_4, notCDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced4SigExtra_hi_hi = {notCDom_reduced4SigExtra_reducedVec_6, notCDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:101:30, :107:20]
wire [3:0] notCDom_reduced4SigExtra_hi = {notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:107:20]
wire [6:0] _notCDom_reduced4SigExtra_T_2 = {notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo}; // @[primitives.scala:107:20]
wire [3:0] _notCDom_reduced4SigExtra_T_3 = notCDom_normDistReduced2[4:1]; // @[Mux.scala:50:70]
wire [3:0] _notCDom_reduced4SigExtra_T_4 = ~_notCDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21]
wire [16:0] notCDom_reduced4SigExtra_shift = $signed(17'sh10000 >>> _notCDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56]
wire [5:0] _notCDom_reduced4SigExtra_T_5 = notCDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22]
wire [3:0] _notCDom_reduced4SigExtra_T_6 = _notCDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22]
wire [1:0] _notCDom_reduced4SigExtra_T_7 = _notCDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_8 = _notCDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_9 = _notCDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_10 = {_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_11 = _notCDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_12 = _notCDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_13 = _notCDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_14 = {_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20]
wire [3:0] _notCDom_reduced4SigExtra_T_15 = {_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_16 = _notCDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22]
wire _notCDom_reduced4SigExtra_T_17 = _notCDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_18 = _notCDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_19 = {_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20]
wire [5:0] _notCDom_reduced4SigExtra_T_20 = {_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20]
wire [6:0] _notCDom_reduced4SigExtra_T_21 = {1'h0, _notCDom_reduced4SigExtra_T_2[5:0] & _notCDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :107:20]
wire notCDom_reduced4SigExtra = |_notCDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:247:78, :249:11]
wire [25:0] _notCDom_sig_T = notCDom_mainSig[28:3]; // @[MulAddRecFN.scala:243:50, :251:28]
wire [2:0] _notCDom_sig_T_1 = notCDom_mainSig[2:0]; // @[MulAddRecFN.scala:243:50, :252:28]
wire _notCDom_sig_T_2 = |_notCDom_sig_T_1; // @[MulAddRecFN.scala:252:{28,35}]
wire _notCDom_sig_T_3 = _notCDom_sig_T_2 | notCDom_reduced4SigExtra; // @[MulAddRecFN.scala:249:11, :252:{35,39}]
wire [26:0] notCDom_sig = {_notCDom_sig_T, _notCDom_sig_T_3}; // @[MulAddRecFN.scala:251:{12,28}, :252:39]
wire [1:0] _notCDom_completeCancellation_T = notCDom_sig[26:25]; // @[MulAddRecFN.scala:251:12, :255:21]
wire notCDom_completeCancellation = _notCDom_completeCancellation_T == 2'h0; // @[primitives.scala:103:54]
wire _notCDom_sign_T = io_fromPreMul_signProd_0 ^ notCDom_signSigSum; // @[MulAddRecFN.scala:169:7, :232:36, :259:36]
wire notCDom_sign = ~notCDom_completeCancellation & _notCDom_sign_T; // @[MulAddRecFN.scala:255:50, :257:12, :259:36]
assign notNaN_isInfOut = notNaN_isInfProd | io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :264:49, :265:44]
assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulAddRecFN.scala:169:7, :265:44]
wire notNaN_addZeros = _notNaN_addZeros_T & io_fromPreMul_isZeroC_0; // @[MulAddRecFN.scala:169:7, :267:{32,58}]
wire _io_rawOut_sign_T_4 = notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :287:26]
wire _io_invalidExc_T_3 = _io_invalidExc_T_1; // @[MulAddRecFN.scala:271:35, :272:57]
wire _io_invalidExc_T_4 = ~io_fromPreMul_isNaNAOrB_0; // @[MulAddRecFN.scala:169:7, :274:10]
wire _io_invalidExc_T_6 = _io_invalidExc_T_4 & _io_invalidExc_T_5; // @[MulAddRecFN.scala:274:{10,36}, :275:36]
wire _io_invalidExc_T_7 = _io_invalidExc_T_6 & io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :274:36, :275:61]
wire _io_invalidExc_T_8 = _io_invalidExc_T_7 & io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :275:61, :276:35]
assign _io_invalidExc_T_9 = _io_invalidExc_T_3 | _io_invalidExc_T_8; // @[MulAddRecFN.scala:272:57, :273:57, :276:35]
assign io_invalidExc_0 = _io_invalidExc_T_9; // @[MulAddRecFN.scala:169:7, :273:57]
assign _io_rawOut_isNaN_T = io_fromPreMul_isNaNAOrB_0 | io_fromPreMul_isNaNC_0; // @[MulAddRecFN.scala:169:7, :278:48]
assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:169:7, :278:48]
wire _io_rawOut_isZero_T = ~io_fromPreMul_CIsDominant_0; // @[MulAddRecFN.scala:169:7, :283:14]
wire _io_rawOut_isZero_T_1 = _io_rawOut_isZero_T & notCDom_completeCancellation; // @[MulAddRecFN.scala:255:50, :283:{14,42}]
assign _io_rawOut_isZero_T_2 = notNaN_addZeros | _io_rawOut_isZero_T_1; // @[MulAddRecFN.scala:267:58, :282:25, :283:42]
assign io_rawOut_isZero_0 = _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:169:7, :282:25]
wire _io_rawOut_sign_T = notNaN_isInfProd & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :264:49, :285:27]
wire _io_rawOut_sign_T_1 = io_fromPreMul_isInfC_0 & opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :286:31]
wire _io_rawOut_sign_T_2 = _io_rawOut_sign_T | _io_rawOut_sign_T_1; // @[MulAddRecFN.scala:285:{27,54}, :286:31]
wire _io_rawOut_sign_T_5 = _io_rawOut_sign_T_4 & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :287:{26,48}]
wire _io_rawOut_sign_T_6 = _io_rawOut_sign_T_5 & opSignC; // @[MulAddRecFN.scala:190:42, :287:48, :288:36]
wire _io_rawOut_sign_T_7 = _io_rawOut_sign_T_2 | _io_rawOut_sign_T_6; // @[MulAddRecFN.scala:285:54, :286:43, :288:36]
wire _io_rawOut_sign_T_11 = _io_rawOut_sign_T_7; // @[MulAddRecFN.scala:286:43, :288:48]
wire _io_rawOut_sign_T_9 = io_fromPreMul_signProd_0 | opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :290:37]
wire _io_rawOut_sign_T_12 = ~notNaN_isInfOut; // @[MulAddRecFN.scala:265:44, :291:10]
wire _io_rawOut_sign_T_13 = ~notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :291:31]
wire _io_rawOut_sign_T_14 = _io_rawOut_sign_T_12 & _io_rawOut_sign_T_13; // @[MulAddRecFN.scala:291:{10,28,31}]
wire _io_rawOut_sign_T_15 = io_fromPreMul_CIsDominant_0 ? opSignC : notCDom_sign; // @[MulAddRecFN.scala:169:7, :190:42, :257:12, :292:17]
wire _io_rawOut_sign_T_16 = _io_rawOut_sign_T_14 & _io_rawOut_sign_T_15; // @[MulAddRecFN.scala:291:{28,49}, :292:17]
assign _io_rawOut_sign_T_17 = _io_rawOut_sign_T_11 | _io_rawOut_sign_T_16; // @[MulAddRecFN.scala:288:48, :290:50, :291:49]
assign io_rawOut_sign_0 = _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:169:7, :290:50]
assign _io_rawOut_sExp_T = io_fromPreMul_CIsDominant_0 ? CDom_sExp : notCDom_sExp; // @[MulAddRecFN.scala:169:7, :203:43, :241:46, :293:26]
assign io_rawOut_sExp_0 = _io_rawOut_sExp_T; // @[MulAddRecFN.scala:169:7, :293:26]
assign _io_rawOut_sig_T = io_fromPreMul_CIsDominant_0 ? CDom_sig : notCDom_sig; // @[MulAddRecFN.scala:169:7, :225:12, :251:12, :294:25]
assign io_rawOut_sig_0 = _io_rawOut_sig_T; // @[MulAddRecFN.scala:169:7, :294:25]
assign io_invalidExc = io_invalidExc_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_sign = io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_sig = io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_36 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>}
node _io_out_d_T = mul(io.in_a, io.in_b)
node _io_out_d_T_1 = add(_io_out_d_T, io.in_c)
node _io_out_d_T_2 = tail(_io_out_d_T_1, 1)
node _io_out_d_T_3 = asSInt(_io_out_d_T_2)
connect io.out_d, _io_out_d_T_3 | module MacUnit_36( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [31:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7]
wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54]
wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_44 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T
node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_11, UInt<1>(0h1), "") : assert_1
node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_15 :
node _T_16 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_17 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_18 = and(_T_16, _T_17)
node _T_19 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_20 = and(_T_18, _T_19)
node _T_21 = or(UInt<1>(0h0), _T_20)
node _T_22 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_24 = cvt(_T_23)
node _T_25 = and(_T_24, asSInt(UInt<14>(0h2000)))
node _T_26 = asSInt(_T_25)
node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0)))
node _T_28 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_29 = cvt(_T_28)
node _T_30 = and(_T_29, asSInt(UInt<13>(0h1000)))
node _T_31 = asSInt(_T_30)
node _T_32 = eq(_T_31, asSInt(UInt<1>(0h0)))
node _T_33 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_34 = cvt(_T_33)
node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000)))
node _T_36 = asSInt(_T_35)
node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0)))
node _T_38 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_39 = cvt(_T_38)
node _T_40 = and(_T_39, asSInt(UInt<18>(0h2f000)))
node _T_41 = asSInt(_T_40)
node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0)))
node _T_43 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_44 = cvt(_T_43)
node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000)))
node _T_46 = asSInt(_T_45)
node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_49 = cvt(_T_48)
node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000)))
node _T_51 = asSInt(_T_50)
node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0)))
node _T_53 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_54 = cvt(_T_53)
node _T_55 = and(_T_54, asSInt(UInt<27>(0h4000000)))
node _T_56 = asSInt(_T_55)
node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0)))
node _T_58 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_27, _T_32)
node _T_64 = or(_T_63, _T_37)
node _T_65 = or(_T_64, _T_42)
node _T_66 = or(_T_65, _T_47)
node _T_67 = or(_T_66, _T_52)
node _T_68 = or(_T_67, _T_57)
node _T_69 = or(_T_68, _T_62)
node _T_70 = and(_T_22, _T_69)
node _T_71 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_72 = or(UInt<1>(0h0), _T_71)
node _T_73 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_74 = cvt(_T_73)
node _T_75 = and(_T_74, asSInt(UInt<17>(0h10000)))
node _T_76 = asSInt(_T_75)
node _T_77 = eq(_T_76, asSInt(UInt<1>(0h0)))
node _T_78 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_79 = cvt(_T_78)
node _T_80 = and(_T_79, asSInt(UInt<29>(0h10000000)))
node _T_81 = asSInt(_T_80)
node _T_82 = eq(_T_81, asSInt(UInt<1>(0h0)))
node _T_83 = or(_T_77, _T_82)
node _T_84 = and(_T_72, _T_83)
node _T_85 = or(UInt<1>(0h0), _T_70)
node _T_86 = or(_T_85, _T_84)
node _T_87 = and(_T_21, _T_86)
node _T_88 = asUInt(reset)
node _T_89 = eq(_T_88, UInt<1>(0h0))
when _T_89 :
node _T_90 = eq(_T_87, UInt<1>(0h0))
when _T_90 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_87, UInt<1>(0h1), "") : assert_2
node _T_91 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_92 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_93 = and(_T_91, _T_92)
node _T_94 = or(UInt<1>(0h0), _T_93)
node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_96 = cvt(_T_95)
node _T_97 = and(_T_96, asSInt(UInt<14>(0h2000)))
node _T_98 = asSInt(_T_97)
node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_101 = cvt(_T_100)
node _T_102 = and(_T_101, asSInt(UInt<13>(0h1000)))
node _T_103 = asSInt(_T_102)
node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0)))
node _T_105 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_106 = cvt(_T_105)
node _T_107 = and(_T_106, asSInt(UInt<17>(0h10000)))
node _T_108 = asSInt(_T_107)
node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0)))
node _T_110 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_111 = cvt(_T_110)
node _T_112 = and(_T_111, asSInt(UInt<18>(0h2f000)))
node _T_113 = asSInt(_T_112)
node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0)))
node _T_115 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_116 = cvt(_T_115)
node _T_117 = and(_T_116, asSInt(UInt<17>(0h10000)))
node _T_118 = asSInt(_T_117)
node _T_119 = eq(_T_118, asSInt(UInt<1>(0h0)))
node _T_120 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_121 = cvt(_T_120)
node _T_122 = and(_T_121, asSInt(UInt<13>(0h1000)))
node _T_123 = asSInt(_T_122)
node _T_124 = eq(_T_123, asSInt(UInt<1>(0h0)))
node _T_125 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_126 = cvt(_T_125)
node _T_127 = and(_T_126, asSInt(UInt<17>(0h10000)))
node _T_128 = asSInt(_T_127)
node _T_129 = eq(_T_128, asSInt(UInt<1>(0h0)))
node _T_130 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_131 = cvt(_T_130)
node _T_132 = and(_T_131, asSInt(UInt<27>(0h4000000)))
node _T_133 = asSInt(_T_132)
node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0)))
node _T_135 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_136 = cvt(_T_135)
node _T_137 = and(_T_136, asSInt(UInt<13>(0h1000)))
node _T_138 = asSInt(_T_137)
node _T_139 = eq(_T_138, asSInt(UInt<1>(0h0)))
node _T_140 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_141 = cvt(_T_140)
node _T_142 = and(_T_141, asSInt(UInt<29>(0h10000000)))
node _T_143 = asSInt(_T_142)
node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0)))
node _T_145 = or(_T_99, _T_104)
node _T_146 = or(_T_145, _T_109)
node _T_147 = or(_T_146, _T_114)
node _T_148 = or(_T_147, _T_119)
node _T_149 = or(_T_148, _T_124)
node _T_150 = or(_T_149, _T_129)
node _T_151 = or(_T_150, _T_134)
node _T_152 = or(_T_151, _T_139)
node _T_153 = or(_T_152, _T_144)
node _T_154 = and(_T_94, _T_153)
node _T_155 = or(UInt<1>(0h0), _T_154)
node _T_156 = and(UInt<1>(0h0), _T_155)
node _T_157 = asUInt(reset)
node _T_158 = eq(_T_157, UInt<1>(0h0))
when _T_158 :
node _T_159 = eq(_T_156, UInt<1>(0h0))
when _T_159 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_156, UInt<1>(0h1), "") : assert_3
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_163 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_164 = asUInt(reset)
node _T_165 = eq(_T_164, UInt<1>(0h0))
when _T_165 :
node _T_166 = eq(_T_163, UInt<1>(0h0))
when _T_166 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_163, UInt<1>(0h1), "") : assert_5
node _T_167 = asUInt(reset)
node _T_168 = eq(_T_167, UInt<1>(0h0))
when _T_168 :
node _T_169 = eq(is_aligned, UInt<1>(0h0))
when _T_169 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_170 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_171 = asUInt(reset)
node _T_172 = eq(_T_171, UInt<1>(0h0))
when _T_172 :
node _T_173 = eq(_T_170, UInt<1>(0h0))
when _T_173 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_170, UInt<1>(0h1), "") : assert_7
node _T_174 = not(io.in.a.bits.mask)
node _T_175 = eq(_T_174, UInt<1>(0h0))
node _T_176 = asUInt(reset)
node _T_177 = eq(_T_176, UInt<1>(0h0))
when _T_177 :
node _T_178 = eq(_T_175, UInt<1>(0h0))
when _T_178 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_175, UInt<1>(0h1), "") : assert_8
node _T_179 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_180 = asUInt(reset)
node _T_181 = eq(_T_180, UInt<1>(0h0))
when _T_181 :
node _T_182 = eq(_T_179, UInt<1>(0h0))
when _T_182 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_179, UInt<1>(0h1), "") : assert_9
node _T_183 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_183 :
node _T_184 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_185 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_186 = and(_T_184, _T_185)
node _T_187 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_188 = and(_T_186, _T_187)
node _T_189 = or(UInt<1>(0h0), _T_188)
node _T_190 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_191 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_192 = cvt(_T_191)
node _T_193 = and(_T_192, asSInt(UInt<14>(0h2000)))
node _T_194 = asSInt(_T_193)
node _T_195 = eq(_T_194, asSInt(UInt<1>(0h0)))
node _T_196 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_197 = cvt(_T_196)
node _T_198 = and(_T_197, asSInt(UInt<13>(0h1000)))
node _T_199 = asSInt(_T_198)
node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0)))
node _T_201 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_202 = cvt(_T_201)
node _T_203 = and(_T_202, asSInt(UInt<17>(0h10000)))
node _T_204 = asSInt(_T_203)
node _T_205 = eq(_T_204, asSInt(UInt<1>(0h0)))
node _T_206 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_207 = cvt(_T_206)
node _T_208 = and(_T_207, asSInt(UInt<18>(0h2f000)))
node _T_209 = asSInt(_T_208)
node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0)))
node _T_211 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_212 = cvt(_T_211)
node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000)))
node _T_214 = asSInt(_T_213)
node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0)))
node _T_216 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_217 = cvt(_T_216)
node _T_218 = and(_T_217, asSInt(UInt<13>(0h1000)))
node _T_219 = asSInt(_T_218)
node _T_220 = eq(_T_219, asSInt(UInt<1>(0h0)))
node _T_221 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_222 = cvt(_T_221)
node _T_223 = and(_T_222, asSInt(UInt<27>(0h4000000)))
node _T_224 = asSInt(_T_223)
node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0)))
node _T_226 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_227 = cvt(_T_226)
node _T_228 = and(_T_227, asSInt(UInt<13>(0h1000)))
node _T_229 = asSInt(_T_228)
node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0)))
node _T_231 = or(_T_195, _T_200)
node _T_232 = or(_T_231, _T_205)
node _T_233 = or(_T_232, _T_210)
node _T_234 = or(_T_233, _T_215)
node _T_235 = or(_T_234, _T_220)
node _T_236 = or(_T_235, _T_225)
node _T_237 = or(_T_236, _T_230)
node _T_238 = and(_T_190, _T_237)
node _T_239 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_240 = or(UInt<1>(0h0), _T_239)
node _T_241 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_242 = cvt(_T_241)
node _T_243 = and(_T_242, asSInt(UInt<17>(0h10000)))
node _T_244 = asSInt(_T_243)
node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0)))
node _T_246 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_247 = cvt(_T_246)
node _T_248 = and(_T_247, asSInt(UInt<29>(0h10000000)))
node _T_249 = asSInt(_T_248)
node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0)))
node _T_251 = or(_T_245, _T_250)
node _T_252 = and(_T_240, _T_251)
node _T_253 = or(UInt<1>(0h0), _T_238)
node _T_254 = or(_T_253, _T_252)
node _T_255 = and(_T_189, _T_254)
node _T_256 = asUInt(reset)
node _T_257 = eq(_T_256, UInt<1>(0h0))
when _T_257 :
node _T_258 = eq(_T_255, UInt<1>(0h0))
when _T_258 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_255, UInt<1>(0h1), "") : assert_10
node _T_259 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_260 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_261 = and(_T_259, _T_260)
node _T_262 = or(UInt<1>(0h0), _T_261)
node _T_263 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_264 = cvt(_T_263)
node _T_265 = and(_T_264, asSInt(UInt<14>(0h2000)))
node _T_266 = asSInt(_T_265)
node _T_267 = eq(_T_266, asSInt(UInt<1>(0h0)))
node _T_268 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_269 = cvt(_T_268)
node _T_270 = and(_T_269, asSInt(UInt<13>(0h1000)))
node _T_271 = asSInt(_T_270)
node _T_272 = eq(_T_271, asSInt(UInt<1>(0h0)))
node _T_273 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_274 = cvt(_T_273)
node _T_275 = and(_T_274, asSInt(UInt<17>(0h10000)))
node _T_276 = asSInt(_T_275)
node _T_277 = eq(_T_276, asSInt(UInt<1>(0h0)))
node _T_278 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_279 = cvt(_T_278)
node _T_280 = and(_T_279, asSInt(UInt<18>(0h2f000)))
node _T_281 = asSInt(_T_280)
node _T_282 = eq(_T_281, asSInt(UInt<1>(0h0)))
node _T_283 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_284 = cvt(_T_283)
node _T_285 = and(_T_284, asSInt(UInt<17>(0h10000)))
node _T_286 = asSInt(_T_285)
node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0)))
node _T_288 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_289 = cvt(_T_288)
node _T_290 = and(_T_289, asSInt(UInt<13>(0h1000)))
node _T_291 = asSInt(_T_290)
node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0)))
node _T_293 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_294 = cvt(_T_293)
node _T_295 = and(_T_294, asSInt(UInt<17>(0h10000)))
node _T_296 = asSInt(_T_295)
node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0)))
node _T_298 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_299 = cvt(_T_298)
node _T_300 = and(_T_299, asSInt(UInt<27>(0h4000000)))
node _T_301 = asSInt(_T_300)
node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0)))
node _T_303 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_304 = cvt(_T_303)
node _T_305 = and(_T_304, asSInt(UInt<13>(0h1000)))
node _T_306 = asSInt(_T_305)
node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0)))
node _T_308 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_309 = cvt(_T_308)
node _T_310 = and(_T_309, asSInt(UInt<29>(0h10000000)))
node _T_311 = asSInt(_T_310)
node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0)))
node _T_313 = or(_T_267, _T_272)
node _T_314 = or(_T_313, _T_277)
node _T_315 = or(_T_314, _T_282)
node _T_316 = or(_T_315, _T_287)
node _T_317 = or(_T_316, _T_292)
node _T_318 = or(_T_317, _T_297)
node _T_319 = or(_T_318, _T_302)
node _T_320 = or(_T_319, _T_307)
node _T_321 = or(_T_320, _T_312)
node _T_322 = and(_T_262, _T_321)
node _T_323 = or(UInt<1>(0h0), _T_322)
node _T_324 = and(UInt<1>(0h0), _T_323)
node _T_325 = asUInt(reset)
node _T_326 = eq(_T_325, UInt<1>(0h0))
when _T_326 :
node _T_327 = eq(_T_324, UInt<1>(0h0))
when _T_327 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_324, UInt<1>(0h1), "") : assert_11
node _T_328 = asUInt(reset)
node _T_329 = eq(_T_328, UInt<1>(0h0))
when _T_329 :
node _T_330 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_330 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_331 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_332 = asUInt(reset)
node _T_333 = eq(_T_332, UInt<1>(0h0))
when _T_333 :
node _T_334 = eq(_T_331, UInt<1>(0h0))
when _T_334 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_331, UInt<1>(0h1), "") : assert_13
node _T_335 = asUInt(reset)
node _T_336 = eq(_T_335, UInt<1>(0h0))
when _T_336 :
node _T_337 = eq(is_aligned, UInt<1>(0h0))
when _T_337 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_338 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_339 = asUInt(reset)
node _T_340 = eq(_T_339, UInt<1>(0h0))
when _T_340 :
node _T_341 = eq(_T_338, UInt<1>(0h0))
when _T_341 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_338, UInt<1>(0h1), "") : assert_15
node _T_342 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_343 = asUInt(reset)
node _T_344 = eq(_T_343, UInt<1>(0h0))
when _T_344 :
node _T_345 = eq(_T_342, UInt<1>(0h0))
when _T_345 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_342, UInt<1>(0h1), "") : assert_16
node _T_346 = not(io.in.a.bits.mask)
node _T_347 = eq(_T_346, UInt<1>(0h0))
node _T_348 = asUInt(reset)
node _T_349 = eq(_T_348, UInt<1>(0h0))
when _T_349 :
node _T_350 = eq(_T_347, UInt<1>(0h0))
when _T_350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_347, UInt<1>(0h1), "") : assert_17
node _T_351 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_352 = asUInt(reset)
node _T_353 = eq(_T_352, UInt<1>(0h0))
when _T_353 :
node _T_354 = eq(_T_351, UInt<1>(0h0))
when _T_354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_351, UInt<1>(0h1), "") : assert_18
node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_355 :
node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_358 = and(_T_356, _T_357)
node _T_359 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_360 = and(_T_358, _T_359)
node _T_361 = or(UInt<1>(0h0), _T_360)
node _T_362 = asUInt(reset)
node _T_363 = eq(_T_362, UInt<1>(0h0))
when _T_363 :
node _T_364 = eq(_T_361, UInt<1>(0h0))
when _T_364 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_361, UInt<1>(0h1), "") : assert_19
node _T_365 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_366 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_367 = and(_T_365, _T_366)
node _T_368 = or(UInt<1>(0h0), _T_367)
node _T_369 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_370 = cvt(_T_369)
node _T_371 = and(_T_370, asSInt(UInt<13>(0h1000)))
node _T_372 = asSInt(_T_371)
node _T_373 = eq(_T_372, asSInt(UInt<1>(0h0)))
node _T_374 = and(_T_368, _T_373)
node _T_375 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_376 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_377 = and(_T_375, _T_376)
node _T_378 = or(UInt<1>(0h0), _T_377)
node _T_379 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_380 = cvt(_T_379)
node _T_381 = and(_T_380, asSInt(UInt<14>(0h2000)))
node _T_382 = asSInt(_T_381)
node _T_383 = eq(_T_382, asSInt(UInt<1>(0h0)))
node _T_384 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_385 = cvt(_T_384)
node _T_386 = and(_T_385, asSInt(UInt<17>(0h10000)))
node _T_387 = asSInt(_T_386)
node _T_388 = eq(_T_387, asSInt(UInt<1>(0h0)))
node _T_389 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_390 = cvt(_T_389)
node _T_391 = and(_T_390, asSInt(UInt<18>(0h2f000)))
node _T_392 = asSInt(_T_391)
node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0)))
node _T_394 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_395 = cvt(_T_394)
node _T_396 = and(_T_395, asSInt(UInt<17>(0h10000)))
node _T_397 = asSInt(_T_396)
node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0)))
node _T_399 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_400 = cvt(_T_399)
node _T_401 = and(_T_400, asSInt(UInt<13>(0h1000)))
node _T_402 = asSInt(_T_401)
node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0)))
node _T_404 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_405 = cvt(_T_404)
node _T_406 = and(_T_405, asSInt(UInt<17>(0h10000)))
node _T_407 = asSInt(_T_406)
node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0)))
node _T_409 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_410 = cvt(_T_409)
node _T_411 = and(_T_410, asSInt(UInt<27>(0h4000000)))
node _T_412 = asSInt(_T_411)
node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0)))
node _T_414 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_415 = cvt(_T_414)
node _T_416 = and(_T_415, asSInt(UInt<13>(0h1000)))
node _T_417 = asSInt(_T_416)
node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0)))
node _T_419 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_420 = cvt(_T_419)
node _T_421 = and(_T_420, asSInt(UInt<29>(0h10000000)))
node _T_422 = asSInt(_T_421)
node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0)))
node _T_424 = or(_T_383, _T_388)
node _T_425 = or(_T_424, _T_393)
node _T_426 = or(_T_425, _T_398)
node _T_427 = or(_T_426, _T_403)
node _T_428 = or(_T_427, _T_408)
node _T_429 = or(_T_428, _T_413)
node _T_430 = or(_T_429, _T_418)
node _T_431 = or(_T_430, _T_423)
node _T_432 = and(_T_378, _T_431)
node _T_433 = or(UInt<1>(0h0), _T_374)
node _T_434 = or(_T_433, _T_432)
node _T_435 = asUInt(reset)
node _T_436 = eq(_T_435, UInt<1>(0h0))
when _T_436 :
node _T_437 = eq(_T_434, UInt<1>(0h0))
when _T_437 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_434, UInt<1>(0h1), "") : assert_20
node _T_438 = asUInt(reset)
node _T_439 = eq(_T_438, UInt<1>(0h0))
when _T_439 :
node _T_440 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_440 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_441 = asUInt(reset)
node _T_442 = eq(_T_441, UInt<1>(0h0))
when _T_442 :
node _T_443 = eq(is_aligned, UInt<1>(0h0))
when _T_443 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_444 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_445 = asUInt(reset)
node _T_446 = eq(_T_445, UInt<1>(0h0))
when _T_446 :
node _T_447 = eq(_T_444, UInt<1>(0h0))
when _T_447 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_444, UInt<1>(0h1), "") : assert_23
node _T_448 = eq(io.in.a.bits.mask, mask)
node _T_449 = asUInt(reset)
node _T_450 = eq(_T_449, UInt<1>(0h0))
when _T_450 :
node _T_451 = eq(_T_448, UInt<1>(0h0))
when _T_451 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_448, UInt<1>(0h1), "") : assert_24
node _T_452 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(_T_452, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_452, UInt<1>(0h1), "") : assert_25
node _T_456 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_456 :
node _T_457 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_458 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_459 = and(_T_457, _T_458)
node _T_460 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_461 = and(_T_459, _T_460)
node _T_462 = or(UInt<1>(0h0), _T_461)
node _T_463 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_464 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_465 = and(_T_463, _T_464)
node _T_466 = or(UInt<1>(0h0), _T_465)
node _T_467 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_468 = cvt(_T_467)
node _T_469 = and(_T_468, asSInt(UInt<13>(0h1000)))
node _T_470 = asSInt(_T_469)
node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0)))
node _T_472 = and(_T_466, _T_471)
node _T_473 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_474 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_475 = and(_T_473, _T_474)
node _T_476 = or(UInt<1>(0h0), _T_475)
node _T_477 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_478 = cvt(_T_477)
node _T_479 = and(_T_478, asSInt(UInt<14>(0h2000)))
node _T_480 = asSInt(_T_479)
node _T_481 = eq(_T_480, asSInt(UInt<1>(0h0)))
node _T_482 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_483 = cvt(_T_482)
node _T_484 = and(_T_483, asSInt(UInt<18>(0h2f000)))
node _T_485 = asSInt(_T_484)
node _T_486 = eq(_T_485, asSInt(UInt<1>(0h0)))
node _T_487 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_488 = cvt(_T_487)
node _T_489 = and(_T_488, asSInt(UInt<17>(0h10000)))
node _T_490 = asSInt(_T_489)
node _T_491 = eq(_T_490, asSInt(UInt<1>(0h0)))
node _T_492 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_493 = cvt(_T_492)
node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000)))
node _T_495 = asSInt(_T_494)
node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0)))
node _T_497 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_498 = cvt(_T_497)
node _T_499 = and(_T_498, asSInt(UInt<17>(0h10000)))
node _T_500 = asSInt(_T_499)
node _T_501 = eq(_T_500, asSInt(UInt<1>(0h0)))
node _T_502 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_503 = cvt(_T_502)
node _T_504 = and(_T_503, asSInt(UInt<27>(0h4000000)))
node _T_505 = asSInt(_T_504)
node _T_506 = eq(_T_505, asSInt(UInt<1>(0h0)))
node _T_507 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_508 = cvt(_T_507)
node _T_509 = and(_T_508, asSInt(UInt<13>(0h1000)))
node _T_510 = asSInt(_T_509)
node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0)))
node _T_512 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_513 = cvt(_T_512)
node _T_514 = and(_T_513, asSInt(UInt<29>(0h10000000)))
node _T_515 = asSInt(_T_514)
node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0)))
node _T_517 = or(_T_481, _T_486)
node _T_518 = or(_T_517, _T_491)
node _T_519 = or(_T_518, _T_496)
node _T_520 = or(_T_519, _T_501)
node _T_521 = or(_T_520, _T_506)
node _T_522 = or(_T_521, _T_511)
node _T_523 = or(_T_522, _T_516)
node _T_524 = and(_T_476, _T_523)
node _T_525 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_526 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_527 = cvt(_T_526)
node _T_528 = and(_T_527, asSInt(UInt<17>(0h10000)))
node _T_529 = asSInt(_T_528)
node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0)))
node _T_531 = and(_T_525, _T_530)
node _T_532 = or(UInt<1>(0h0), _T_472)
node _T_533 = or(_T_532, _T_524)
node _T_534 = or(_T_533, _T_531)
node _T_535 = and(_T_462, _T_534)
node _T_536 = asUInt(reset)
node _T_537 = eq(_T_536, UInt<1>(0h0))
when _T_537 :
node _T_538 = eq(_T_535, UInt<1>(0h0))
when _T_538 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_535, UInt<1>(0h1), "") : assert_26
node _T_539 = asUInt(reset)
node _T_540 = eq(_T_539, UInt<1>(0h0))
when _T_540 :
node _T_541 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_541 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_542 = asUInt(reset)
node _T_543 = eq(_T_542, UInt<1>(0h0))
when _T_543 :
node _T_544 = eq(is_aligned, UInt<1>(0h0))
when _T_544 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_545 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_546 = asUInt(reset)
node _T_547 = eq(_T_546, UInt<1>(0h0))
when _T_547 :
node _T_548 = eq(_T_545, UInt<1>(0h0))
when _T_548 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_545, UInt<1>(0h1), "") : assert_29
node _T_549 = eq(io.in.a.bits.mask, mask)
node _T_550 = asUInt(reset)
node _T_551 = eq(_T_550, UInt<1>(0h0))
when _T_551 :
node _T_552 = eq(_T_549, UInt<1>(0h0))
when _T_552 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_549, UInt<1>(0h1), "") : assert_30
node _T_553 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_553 :
node _T_554 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_555 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_556 = and(_T_554, _T_555)
node _T_557 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_558 = and(_T_556, _T_557)
node _T_559 = or(UInt<1>(0h0), _T_558)
node _T_560 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_561 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_562 = and(_T_560, _T_561)
node _T_563 = or(UInt<1>(0h0), _T_562)
node _T_564 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_565 = cvt(_T_564)
node _T_566 = and(_T_565, asSInt(UInt<13>(0h1000)))
node _T_567 = asSInt(_T_566)
node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0)))
node _T_569 = and(_T_563, _T_568)
node _T_570 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_571 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_572 = and(_T_570, _T_571)
node _T_573 = or(UInt<1>(0h0), _T_572)
node _T_574 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_575 = cvt(_T_574)
node _T_576 = and(_T_575, asSInt(UInt<14>(0h2000)))
node _T_577 = asSInt(_T_576)
node _T_578 = eq(_T_577, asSInt(UInt<1>(0h0)))
node _T_579 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_580 = cvt(_T_579)
node _T_581 = and(_T_580, asSInt(UInt<18>(0h2f000)))
node _T_582 = asSInt(_T_581)
node _T_583 = eq(_T_582, asSInt(UInt<1>(0h0)))
node _T_584 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_585 = cvt(_T_584)
node _T_586 = and(_T_585, asSInt(UInt<17>(0h10000)))
node _T_587 = asSInt(_T_586)
node _T_588 = eq(_T_587, asSInt(UInt<1>(0h0)))
node _T_589 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_590 = cvt(_T_589)
node _T_591 = and(_T_590, asSInt(UInt<13>(0h1000)))
node _T_592 = asSInt(_T_591)
node _T_593 = eq(_T_592, asSInt(UInt<1>(0h0)))
node _T_594 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_595 = cvt(_T_594)
node _T_596 = and(_T_595, asSInt(UInt<17>(0h10000)))
node _T_597 = asSInt(_T_596)
node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0)))
node _T_599 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_600 = cvt(_T_599)
node _T_601 = and(_T_600, asSInt(UInt<27>(0h4000000)))
node _T_602 = asSInt(_T_601)
node _T_603 = eq(_T_602, asSInt(UInt<1>(0h0)))
node _T_604 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_605 = cvt(_T_604)
node _T_606 = and(_T_605, asSInt(UInt<13>(0h1000)))
node _T_607 = asSInt(_T_606)
node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0)))
node _T_609 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_610 = cvt(_T_609)
node _T_611 = and(_T_610, asSInt(UInt<29>(0h10000000)))
node _T_612 = asSInt(_T_611)
node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0)))
node _T_614 = or(_T_578, _T_583)
node _T_615 = or(_T_614, _T_588)
node _T_616 = or(_T_615, _T_593)
node _T_617 = or(_T_616, _T_598)
node _T_618 = or(_T_617, _T_603)
node _T_619 = or(_T_618, _T_608)
node _T_620 = or(_T_619, _T_613)
node _T_621 = and(_T_573, _T_620)
node _T_622 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_623 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_624 = cvt(_T_623)
node _T_625 = and(_T_624, asSInt(UInt<17>(0h10000)))
node _T_626 = asSInt(_T_625)
node _T_627 = eq(_T_626, asSInt(UInt<1>(0h0)))
node _T_628 = and(_T_622, _T_627)
node _T_629 = or(UInt<1>(0h0), _T_569)
node _T_630 = or(_T_629, _T_621)
node _T_631 = or(_T_630, _T_628)
node _T_632 = and(_T_559, _T_631)
node _T_633 = asUInt(reset)
node _T_634 = eq(_T_633, UInt<1>(0h0))
when _T_634 :
node _T_635 = eq(_T_632, UInt<1>(0h0))
when _T_635 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_632, UInt<1>(0h1), "") : assert_31
node _T_636 = asUInt(reset)
node _T_637 = eq(_T_636, UInt<1>(0h0))
when _T_637 :
node _T_638 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_638 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_639 = asUInt(reset)
node _T_640 = eq(_T_639, UInt<1>(0h0))
when _T_640 :
node _T_641 = eq(is_aligned, UInt<1>(0h0))
when _T_641 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_642 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_643 = asUInt(reset)
node _T_644 = eq(_T_643, UInt<1>(0h0))
when _T_644 :
node _T_645 = eq(_T_642, UInt<1>(0h0))
when _T_645 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_642, UInt<1>(0h1), "") : assert_34
node _T_646 = not(mask)
node _T_647 = and(io.in.a.bits.mask, _T_646)
node _T_648 = eq(_T_647, UInt<1>(0h0))
node _T_649 = asUInt(reset)
node _T_650 = eq(_T_649, UInt<1>(0h0))
when _T_650 :
node _T_651 = eq(_T_648, UInt<1>(0h0))
when _T_651 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_648, UInt<1>(0h1), "") : assert_35
node _T_652 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_652 :
node _T_653 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_654 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_655 = and(_T_653, _T_654)
node _T_656 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_657 = and(_T_655, _T_656)
node _T_658 = or(UInt<1>(0h0), _T_657)
node _T_659 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_660 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_661 = and(_T_659, _T_660)
node _T_662 = or(UInt<1>(0h0), _T_661)
node _T_663 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_664 = cvt(_T_663)
node _T_665 = and(_T_664, asSInt(UInt<14>(0h2000)))
node _T_666 = asSInt(_T_665)
node _T_667 = eq(_T_666, asSInt(UInt<1>(0h0)))
node _T_668 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_669 = cvt(_T_668)
node _T_670 = and(_T_669, asSInt(UInt<13>(0h1000)))
node _T_671 = asSInt(_T_670)
node _T_672 = eq(_T_671, asSInt(UInt<1>(0h0)))
node _T_673 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_674 = cvt(_T_673)
node _T_675 = and(_T_674, asSInt(UInt<18>(0h2f000)))
node _T_676 = asSInt(_T_675)
node _T_677 = eq(_T_676, asSInt(UInt<1>(0h0)))
node _T_678 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_679 = cvt(_T_678)
node _T_680 = and(_T_679, asSInt(UInt<17>(0h10000)))
node _T_681 = asSInt(_T_680)
node _T_682 = eq(_T_681, asSInt(UInt<1>(0h0)))
node _T_683 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_684 = cvt(_T_683)
node _T_685 = and(_T_684, asSInt(UInt<13>(0h1000)))
node _T_686 = asSInt(_T_685)
node _T_687 = eq(_T_686, asSInt(UInt<1>(0h0)))
node _T_688 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_689 = cvt(_T_688)
node _T_690 = and(_T_689, asSInt(UInt<17>(0h10000)))
node _T_691 = asSInt(_T_690)
node _T_692 = eq(_T_691, asSInt(UInt<1>(0h0)))
node _T_693 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_694 = cvt(_T_693)
node _T_695 = and(_T_694, asSInt(UInt<27>(0h4000000)))
node _T_696 = asSInt(_T_695)
node _T_697 = eq(_T_696, asSInt(UInt<1>(0h0)))
node _T_698 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_699 = cvt(_T_698)
node _T_700 = and(_T_699, asSInt(UInt<13>(0h1000)))
node _T_701 = asSInt(_T_700)
node _T_702 = eq(_T_701, asSInt(UInt<1>(0h0)))
node _T_703 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_704 = cvt(_T_703)
node _T_705 = and(_T_704, asSInt(UInt<29>(0h10000000)))
node _T_706 = asSInt(_T_705)
node _T_707 = eq(_T_706, asSInt(UInt<1>(0h0)))
node _T_708 = or(_T_667, _T_672)
node _T_709 = or(_T_708, _T_677)
node _T_710 = or(_T_709, _T_682)
node _T_711 = or(_T_710, _T_687)
node _T_712 = or(_T_711, _T_692)
node _T_713 = or(_T_712, _T_697)
node _T_714 = or(_T_713, _T_702)
node _T_715 = or(_T_714, _T_707)
node _T_716 = and(_T_662, _T_715)
node _T_717 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_718 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_719 = cvt(_T_718)
node _T_720 = and(_T_719, asSInt(UInt<17>(0h10000)))
node _T_721 = asSInt(_T_720)
node _T_722 = eq(_T_721, asSInt(UInt<1>(0h0)))
node _T_723 = and(_T_717, _T_722)
node _T_724 = or(UInt<1>(0h0), _T_716)
node _T_725 = or(_T_724, _T_723)
node _T_726 = and(_T_658, _T_725)
node _T_727 = asUInt(reset)
node _T_728 = eq(_T_727, UInt<1>(0h0))
when _T_728 :
node _T_729 = eq(_T_726, UInt<1>(0h0))
when _T_729 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_726, UInt<1>(0h1), "") : assert_36
node _T_730 = asUInt(reset)
node _T_731 = eq(_T_730, UInt<1>(0h0))
when _T_731 :
node _T_732 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_732 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_733 = asUInt(reset)
node _T_734 = eq(_T_733, UInt<1>(0h0))
when _T_734 :
node _T_735 = eq(is_aligned, UInt<1>(0h0))
when _T_735 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_736 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_737 = asUInt(reset)
node _T_738 = eq(_T_737, UInt<1>(0h0))
when _T_738 :
node _T_739 = eq(_T_736, UInt<1>(0h0))
when _T_739 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_736, UInt<1>(0h1), "") : assert_39
node _T_740 = eq(io.in.a.bits.mask, mask)
node _T_741 = asUInt(reset)
node _T_742 = eq(_T_741, UInt<1>(0h0))
when _T_742 :
node _T_743 = eq(_T_740, UInt<1>(0h0))
when _T_743 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_740, UInt<1>(0h1), "") : assert_40
node _T_744 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_744 :
node _T_745 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_746 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_747 = and(_T_745, _T_746)
node _T_748 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_749 = and(_T_747, _T_748)
node _T_750 = or(UInt<1>(0h0), _T_749)
node _T_751 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_752 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_753 = and(_T_751, _T_752)
node _T_754 = or(UInt<1>(0h0), _T_753)
node _T_755 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_756 = cvt(_T_755)
node _T_757 = and(_T_756, asSInt(UInt<14>(0h2000)))
node _T_758 = asSInt(_T_757)
node _T_759 = eq(_T_758, asSInt(UInt<1>(0h0)))
node _T_760 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_761 = cvt(_T_760)
node _T_762 = and(_T_761, asSInt(UInt<13>(0h1000)))
node _T_763 = asSInt(_T_762)
node _T_764 = eq(_T_763, asSInt(UInt<1>(0h0)))
node _T_765 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_766 = cvt(_T_765)
node _T_767 = and(_T_766, asSInt(UInt<18>(0h2f000)))
node _T_768 = asSInt(_T_767)
node _T_769 = eq(_T_768, asSInt(UInt<1>(0h0)))
node _T_770 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_771 = cvt(_T_770)
node _T_772 = and(_T_771, asSInt(UInt<17>(0h10000)))
node _T_773 = asSInt(_T_772)
node _T_774 = eq(_T_773, asSInt(UInt<1>(0h0)))
node _T_775 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_776 = cvt(_T_775)
node _T_777 = and(_T_776, asSInt(UInt<13>(0h1000)))
node _T_778 = asSInt(_T_777)
node _T_779 = eq(_T_778, asSInt(UInt<1>(0h0)))
node _T_780 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_781 = cvt(_T_780)
node _T_782 = and(_T_781, asSInt(UInt<17>(0h10000)))
node _T_783 = asSInt(_T_782)
node _T_784 = eq(_T_783, asSInt(UInt<1>(0h0)))
node _T_785 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_786 = cvt(_T_785)
node _T_787 = and(_T_786, asSInt(UInt<27>(0h4000000)))
node _T_788 = asSInt(_T_787)
node _T_789 = eq(_T_788, asSInt(UInt<1>(0h0)))
node _T_790 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_791 = cvt(_T_790)
node _T_792 = and(_T_791, asSInt(UInt<13>(0h1000)))
node _T_793 = asSInt(_T_792)
node _T_794 = eq(_T_793, asSInt(UInt<1>(0h0)))
node _T_795 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_796 = cvt(_T_795)
node _T_797 = and(_T_796, asSInt(UInt<29>(0h10000000)))
node _T_798 = asSInt(_T_797)
node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0)))
node _T_800 = or(_T_759, _T_764)
node _T_801 = or(_T_800, _T_769)
node _T_802 = or(_T_801, _T_774)
node _T_803 = or(_T_802, _T_779)
node _T_804 = or(_T_803, _T_784)
node _T_805 = or(_T_804, _T_789)
node _T_806 = or(_T_805, _T_794)
node _T_807 = or(_T_806, _T_799)
node _T_808 = and(_T_754, _T_807)
node _T_809 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_810 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_811 = cvt(_T_810)
node _T_812 = and(_T_811, asSInt(UInt<17>(0h10000)))
node _T_813 = asSInt(_T_812)
node _T_814 = eq(_T_813, asSInt(UInt<1>(0h0)))
node _T_815 = and(_T_809, _T_814)
node _T_816 = or(UInt<1>(0h0), _T_808)
node _T_817 = or(_T_816, _T_815)
node _T_818 = and(_T_750, _T_817)
node _T_819 = asUInt(reset)
node _T_820 = eq(_T_819, UInt<1>(0h0))
when _T_820 :
node _T_821 = eq(_T_818, UInt<1>(0h0))
when _T_821 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_818, UInt<1>(0h1), "") : assert_41
node _T_822 = asUInt(reset)
node _T_823 = eq(_T_822, UInt<1>(0h0))
when _T_823 :
node _T_824 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_824 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_825 = asUInt(reset)
node _T_826 = eq(_T_825, UInt<1>(0h0))
when _T_826 :
node _T_827 = eq(is_aligned, UInt<1>(0h0))
when _T_827 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_828 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_829 = asUInt(reset)
node _T_830 = eq(_T_829, UInt<1>(0h0))
when _T_830 :
node _T_831 = eq(_T_828, UInt<1>(0h0))
when _T_831 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_828, UInt<1>(0h1), "") : assert_44
node _T_832 = eq(io.in.a.bits.mask, mask)
node _T_833 = asUInt(reset)
node _T_834 = eq(_T_833, UInt<1>(0h0))
when _T_834 :
node _T_835 = eq(_T_832, UInt<1>(0h0))
when _T_835 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_832, UInt<1>(0h1), "") : assert_45
node _T_836 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_836 :
node _T_837 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_838 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_839 = and(_T_837, _T_838)
node _T_840 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_841 = and(_T_839, _T_840)
node _T_842 = or(UInt<1>(0h0), _T_841)
node _T_843 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_844 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_845 = and(_T_843, _T_844)
node _T_846 = or(UInt<1>(0h0), _T_845)
node _T_847 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_848 = cvt(_T_847)
node _T_849 = and(_T_848, asSInt(UInt<13>(0h1000)))
node _T_850 = asSInt(_T_849)
node _T_851 = eq(_T_850, asSInt(UInt<1>(0h0)))
node _T_852 = and(_T_846, _T_851)
node _T_853 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_854 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_855 = cvt(_T_854)
node _T_856 = and(_T_855, asSInt(UInt<14>(0h2000)))
node _T_857 = asSInt(_T_856)
node _T_858 = eq(_T_857, asSInt(UInt<1>(0h0)))
node _T_859 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_860 = cvt(_T_859)
node _T_861 = and(_T_860, asSInt(UInt<17>(0h10000)))
node _T_862 = asSInt(_T_861)
node _T_863 = eq(_T_862, asSInt(UInt<1>(0h0)))
node _T_864 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_865 = cvt(_T_864)
node _T_866 = and(_T_865, asSInt(UInt<18>(0h2f000)))
node _T_867 = asSInt(_T_866)
node _T_868 = eq(_T_867, asSInt(UInt<1>(0h0)))
node _T_869 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_870 = cvt(_T_869)
node _T_871 = and(_T_870, asSInt(UInt<17>(0h10000)))
node _T_872 = asSInt(_T_871)
node _T_873 = eq(_T_872, asSInt(UInt<1>(0h0)))
node _T_874 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_875 = cvt(_T_874)
node _T_876 = and(_T_875, asSInt(UInt<13>(0h1000)))
node _T_877 = asSInt(_T_876)
node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0)))
node _T_879 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_880 = cvt(_T_879)
node _T_881 = and(_T_880, asSInt(UInt<27>(0h4000000)))
node _T_882 = asSInt(_T_881)
node _T_883 = eq(_T_882, asSInt(UInt<1>(0h0)))
node _T_884 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_885 = cvt(_T_884)
node _T_886 = and(_T_885, asSInt(UInt<13>(0h1000)))
node _T_887 = asSInt(_T_886)
node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0)))
node _T_889 = or(_T_858, _T_863)
node _T_890 = or(_T_889, _T_868)
node _T_891 = or(_T_890, _T_873)
node _T_892 = or(_T_891, _T_878)
node _T_893 = or(_T_892, _T_883)
node _T_894 = or(_T_893, _T_888)
node _T_895 = and(_T_853, _T_894)
node _T_896 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_897 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_898 = and(_T_896, _T_897)
node _T_899 = or(UInt<1>(0h0), _T_898)
node _T_900 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_901 = cvt(_T_900)
node _T_902 = and(_T_901, asSInt(UInt<17>(0h10000)))
node _T_903 = asSInt(_T_902)
node _T_904 = eq(_T_903, asSInt(UInt<1>(0h0)))
node _T_905 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_906 = cvt(_T_905)
node _T_907 = and(_T_906, asSInt(UInt<29>(0h10000000)))
node _T_908 = asSInt(_T_907)
node _T_909 = eq(_T_908, asSInt(UInt<1>(0h0)))
node _T_910 = or(_T_904, _T_909)
node _T_911 = and(_T_899, _T_910)
node _T_912 = or(UInt<1>(0h0), _T_852)
node _T_913 = or(_T_912, _T_895)
node _T_914 = or(_T_913, _T_911)
node _T_915 = and(_T_842, _T_914)
node _T_916 = asUInt(reset)
node _T_917 = eq(_T_916, UInt<1>(0h0))
when _T_917 :
node _T_918 = eq(_T_915, UInt<1>(0h0))
when _T_918 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_915, UInt<1>(0h1), "") : assert_46
node _T_919 = asUInt(reset)
node _T_920 = eq(_T_919, UInt<1>(0h0))
when _T_920 :
node _T_921 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_921 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_922 = asUInt(reset)
node _T_923 = eq(_T_922, UInt<1>(0h0))
when _T_923 :
node _T_924 = eq(is_aligned, UInt<1>(0h0))
when _T_924 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_925 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_926 = asUInt(reset)
node _T_927 = eq(_T_926, UInt<1>(0h0))
when _T_927 :
node _T_928 = eq(_T_925, UInt<1>(0h0))
when _T_928 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_925, UInt<1>(0h1), "") : assert_49
node _T_929 = eq(io.in.a.bits.mask, mask)
node _T_930 = asUInt(reset)
node _T_931 = eq(_T_930, UInt<1>(0h0))
when _T_931 :
node _T_932 = eq(_T_929, UInt<1>(0h0))
when _T_932 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_929, UInt<1>(0h1), "") : assert_50
node _T_933 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_934 = asUInt(reset)
node _T_935 = eq(_T_934, UInt<1>(0h0))
when _T_935 :
node _T_936 = eq(_T_933, UInt<1>(0h0))
when _T_936 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_933, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_937 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_938 = asUInt(reset)
node _T_939 = eq(_T_938, UInt<1>(0h0))
when _T_939 :
node _T_940 = eq(_T_937, UInt<1>(0h0))
when _T_940 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_937, UInt<1>(0h1), "") : assert_52
node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_1
node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8))
node _T_941 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_941 :
node _T_942 = asUInt(reset)
node _T_943 = eq(_T_942, UInt<1>(0h0))
when _T_943 :
node _T_944 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_944 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_945 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_946 = asUInt(reset)
node _T_947 = eq(_T_946, UInt<1>(0h0))
when _T_947 :
node _T_948 = eq(_T_945, UInt<1>(0h0))
when _T_948 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_945, UInt<1>(0h1), "") : assert_54
node _T_949 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_950 = asUInt(reset)
node _T_951 = eq(_T_950, UInt<1>(0h0))
when _T_951 :
node _T_952 = eq(_T_949, UInt<1>(0h0))
when _T_952 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_949, UInt<1>(0h1), "") : assert_55
node _T_953 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_954 = asUInt(reset)
node _T_955 = eq(_T_954, UInt<1>(0h0))
when _T_955 :
node _T_956 = eq(_T_953, UInt<1>(0h0))
when _T_956 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_953, UInt<1>(0h1), "") : assert_56
node _T_957 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_958 = asUInt(reset)
node _T_959 = eq(_T_958, UInt<1>(0h0))
when _T_959 :
node _T_960 = eq(_T_957, UInt<1>(0h0))
when _T_960 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_957, UInt<1>(0h1), "") : assert_57
node _T_961 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_961 :
node _T_962 = asUInt(reset)
node _T_963 = eq(_T_962, UInt<1>(0h0))
when _T_963 :
node _T_964 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_964 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_965 = asUInt(reset)
node _T_966 = eq(_T_965, UInt<1>(0h0))
when _T_966 :
node _T_967 = eq(sink_ok, UInt<1>(0h0))
when _T_967 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_968 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_969 = asUInt(reset)
node _T_970 = eq(_T_969, UInt<1>(0h0))
when _T_970 :
node _T_971 = eq(_T_968, UInt<1>(0h0))
when _T_971 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_968, UInt<1>(0h1), "") : assert_60
node _T_972 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_973 = asUInt(reset)
node _T_974 = eq(_T_973, UInt<1>(0h0))
when _T_974 :
node _T_975 = eq(_T_972, UInt<1>(0h0))
when _T_975 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_972, UInt<1>(0h1), "") : assert_61
node _T_976 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_977 = asUInt(reset)
node _T_978 = eq(_T_977, UInt<1>(0h0))
when _T_978 :
node _T_979 = eq(_T_976, UInt<1>(0h0))
when _T_979 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_976, UInt<1>(0h1), "") : assert_62
node _T_980 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_981 = asUInt(reset)
node _T_982 = eq(_T_981, UInt<1>(0h0))
when _T_982 :
node _T_983 = eq(_T_980, UInt<1>(0h0))
when _T_983 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_980, UInt<1>(0h1), "") : assert_63
node _T_984 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_985 = or(UInt<1>(0h1), _T_984)
node _T_986 = asUInt(reset)
node _T_987 = eq(_T_986, UInt<1>(0h0))
when _T_987 :
node _T_988 = eq(_T_985, UInt<1>(0h0))
when _T_988 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_985, UInt<1>(0h1), "") : assert_64
node _T_989 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_989 :
node _T_990 = asUInt(reset)
node _T_991 = eq(_T_990, UInt<1>(0h0))
when _T_991 :
node _T_992 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_992 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_993 = asUInt(reset)
node _T_994 = eq(_T_993, UInt<1>(0h0))
when _T_994 :
node _T_995 = eq(sink_ok, UInt<1>(0h0))
when _T_995 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_996 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_997 = asUInt(reset)
node _T_998 = eq(_T_997, UInt<1>(0h0))
when _T_998 :
node _T_999 = eq(_T_996, UInt<1>(0h0))
when _T_999 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_996, UInt<1>(0h1), "") : assert_67
node _T_1000 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1001 = asUInt(reset)
node _T_1002 = eq(_T_1001, UInt<1>(0h0))
when _T_1002 :
node _T_1003 = eq(_T_1000, UInt<1>(0h0))
when _T_1003 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1000, UInt<1>(0h1), "") : assert_68
node _T_1004 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1005 = asUInt(reset)
node _T_1006 = eq(_T_1005, UInt<1>(0h0))
when _T_1006 :
node _T_1007 = eq(_T_1004, UInt<1>(0h0))
when _T_1007 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1004, UInt<1>(0h1), "") : assert_69
node _T_1008 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1009 = or(_T_1008, io.in.d.bits.corrupt)
node _T_1010 = asUInt(reset)
node _T_1011 = eq(_T_1010, UInt<1>(0h0))
when _T_1011 :
node _T_1012 = eq(_T_1009, UInt<1>(0h0))
when _T_1012 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1009, UInt<1>(0h1), "") : assert_70
node _T_1013 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1014 = or(UInt<1>(0h1), _T_1013)
node _T_1015 = asUInt(reset)
node _T_1016 = eq(_T_1015, UInt<1>(0h0))
when _T_1016 :
node _T_1017 = eq(_T_1014, UInt<1>(0h0))
when _T_1017 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1014, UInt<1>(0h1), "") : assert_71
node _T_1018 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1018 :
node _T_1019 = asUInt(reset)
node _T_1020 = eq(_T_1019, UInt<1>(0h0))
when _T_1020 :
node _T_1021 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1021 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_1022 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1023 = asUInt(reset)
node _T_1024 = eq(_T_1023, UInt<1>(0h0))
when _T_1024 :
node _T_1025 = eq(_T_1022, UInt<1>(0h0))
when _T_1025 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1022, UInt<1>(0h1), "") : assert_73
node _T_1026 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1027 = asUInt(reset)
node _T_1028 = eq(_T_1027, UInt<1>(0h0))
when _T_1028 :
node _T_1029 = eq(_T_1026, UInt<1>(0h0))
when _T_1029 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1026, UInt<1>(0h1), "") : assert_74
node _T_1030 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1031 = or(UInt<1>(0h1), _T_1030)
node _T_1032 = asUInt(reset)
node _T_1033 = eq(_T_1032, UInt<1>(0h0))
when _T_1033 :
node _T_1034 = eq(_T_1031, UInt<1>(0h0))
when _T_1034 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1031, UInt<1>(0h1), "") : assert_75
node _T_1035 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1035 :
node _T_1036 = asUInt(reset)
node _T_1037 = eq(_T_1036, UInt<1>(0h0))
when _T_1037 :
node _T_1038 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1038 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_1039 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1040 = asUInt(reset)
node _T_1041 = eq(_T_1040, UInt<1>(0h0))
when _T_1041 :
node _T_1042 = eq(_T_1039, UInt<1>(0h0))
when _T_1042 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1039, UInt<1>(0h1), "") : assert_77
node _T_1043 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1044 = or(_T_1043, io.in.d.bits.corrupt)
node _T_1045 = asUInt(reset)
node _T_1046 = eq(_T_1045, UInt<1>(0h0))
when _T_1046 :
node _T_1047 = eq(_T_1044, UInt<1>(0h0))
when _T_1047 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1044, UInt<1>(0h1), "") : assert_78
node _T_1048 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1049 = or(UInt<1>(0h1), _T_1048)
node _T_1050 = asUInt(reset)
node _T_1051 = eq(_T_1050, UInt<1>(0h0))
when _T_1051 :
node _T_1052 = eq(_T_1049, UInt<1>(0h0))
when _T_1052 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1049, UInt<1>(0h1), "") : assert_79
node _T_1053 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1053 :
node _T_1054 = asUInt(reset)
node _T_1055 = eq(_T_1054, UInt<1>(0h0))
when _T_1055 :
node _T_1056 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1056 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_1057 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1058 = asUInt(reset)
node _T_1059 = eq(_T_1058, UInt<1>(0h0))
when _T_1059 :
node _T_1060 = eq(_T_1057, UInt<1>(0h0))
when _T_1060 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1057, UInt<1>(0h1), "") : assert_81
node _T_1061 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1062 = asUInt(reset)
node _T_1063 = eq(_T_1062, UInt<1>(0h0))
when _T_1063 :
node _T_1064 = eq(_T_1061, UInt<1>(0h0))
when _T_1064 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1061, UInt<1>(0h1), "") : assert_82
node _T_1065 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1066 = or(UInt<1>(0h1), _T_1065)
node _T_1067 = asUInt(reset)
node _T_1068 = eq(_T_1067, UInt<1>(0h0))
when _T_1068 :
node _T_1069 = eq(_T_1066, UInt<1>(0h0))
when _T_1069 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1066, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<1>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_1070 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_1071 = asUInt(reset)
node _T_1072 = eq(_T_1071, UInt<1>(0h0))
when _T_1072 :
node _T_1073 = eq(_T_1070, UInt<1>(0h0))
when _T_1073 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1070, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<1>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_1074 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_1075 = asUInt(reset)
node _T_1076 = eq(_T_1075, UInt<1>(0h0))
when _T_1076 :
node _T_1077 = eq(_T_1074, UInt<1>(0h0))
when _T_1077 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1074, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_4.bits.sink, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1078 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1079 = asUInt(reset)
node _T_1080 = eq(_T_1079, UInt<1>(0h0))
when _T_1080 :
node _T_1081 = eq(_T_1078, UInt<1>(0h0))
when _T_1081 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1078, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1082 = eq(a_first, UInt<1>(0h0))
node _T_1083 = and(io.in.a.valid, _T_1082)
when _T_1083 :
node _T_1084 = eq(io.in.a.bits.opcode, opcode)
node _T_1085 = asUInt(reset)
node _T_1086 = eq(_T_1085, UInt<1>(0h0))
when _T_1086 :
node _T_1087 = eq(_T_1084, UInt<1>(0h0))
when _T_1087 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1084, UInt<1>(0h1), "") : assert_87
node _T_1088 = eq(io.in.a.bits.param, param)
node _T_1089 = asUInt(reset)
node _T_1090 = eq(_T_1089, UInt<1>(0h0))
when _T_1090 :
node _T_1091 = eq(_T_1088, UInt<1>(0h0))
when _T_1091 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1088, UInt<1>(0h1), "") : assert_88
node _T_1092 = eq(io.in.a.bits.size, size)
node _T_1093 = asUInt(reset)
node _T_1094 = eq(_T_1093, UInt<1>(0h0))
when _T_1094 :
node _T_1095 = eq(_T_1092, UInt<1>(0h0))
when _T_1095 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1092, UInt<1>(0h1), "") : assert_89
node _T_1096 = eq(io.in.a.bits.source, source)
node _T_1097 = asUInt(reset)
node _T_1098 = eq(_T_1097, UInt<1>(0h0))
when _T_1098 :
node _T_1099 = eq(_T_1096, UInt<1>(0h0))
when _T_1099 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1096, UInt<1>(0h1), "") : assert_90
node _T_1100 = eq(io.in.a.bits.address, address)
node _T_1101 = asUInt(reset)
node _T_1102 = eq(_T_1101, UInt<1>(0h0))
when _T_1102 :
node _T_1103 = eq(_T_1100, UInt<1>(0h0))
when _T_1103 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1100, UInt<1>(0h1), "") : assert_91
node _T_1104 = and(io.in.a.ready, io.in.a.valid)
node _T_1105 = and(_T_1104, a_first)
when _T_1105 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1106 = eq(d_first, UInt<1>(0h0))
node _T_1107 = and(io.in.d.valid, _T_1106)
when _T_1107 :
node _T_1108 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1109 = asUInt(reset)
node _T_1110 = eq(_T_1109, UInt<1>(0h0))
when _T_1110 :
node _T_1111 = eq(_T_1108, UInt<1>(0h0))
when _T_1111 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1108, UInt<1>(0h1), "") : assert_92
node _T_1112 = eq(io.in.d.bits.param, param_1)
node _T_1113 = asUInt(reset)
node _T_1114 = eq(_T_1113, UInt<1>(0h0))
when _T_1114 :
node _T_1115 = eq(_T_1112, UInt<1>(0h0))
when _T_1115 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1112, UInt<1>(0h1), "") : assert_93
node _T_1116 = eq(io.in.d.bits.size, size_1)
node _T_1117 = asUInt(reset)
node _T_1118 = eq(_T_1117, UInt<1>(0h0))
when _T_1118 :
node _T_1119 = eq(_T_1116, UInt<1>(0h0))
when _T_1119 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1116, UInt<1>(0h1), "") : assert_94
node _T_1120 = eq(io.in.d.bits.source, source_1)
node _T_1121 = asUInt(reset)
node _T_1122 = eq(_T_1121, UInt<1>(0h0))
when _T_1122 :
node _T_1123 = eq(_T_1120, UInt<1>(0h0))
when _T_1123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1120, UInt<1>(0h1), "") : assert_95
node _T_1124 = eq(io.in.d.bits.sink, sink)
node _T_1125 = asUInt(reset)
node _T_1126 = eq(_T_1125, UInt<1>(0h0))
when _T_1126 :
node _T_1127 = eq(_T_1124, UInt<1>(0h0))
when _T_1127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1124, UInt<1>(0h1), "") : assert_96
node _T_1128 = eq(io.in.d.bits.denied, denied)
node _T_1129 = asUInt(reset)
node _T_1130 = eq(_T_1129, UInt<1>(0h0))
when _T_1130 :
node _T_1131 = eq(_T_1128, UInt<1>(0h0))
when _T_1131 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1128, UInt<1>(0h1), "") : assert_97
node _T_1132 = and(io.in.d.ready, io.in.d.valid)
node _T_1133 = and(_T_1132, d_first)
when _T_1133 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes : UInt<8>, clock, reset, UInt<8>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<1>
connect a_set, UInt<1>(0h0)
wire a_set_wo_ready : UInt<1>
connect a_set_wo_ready, UInt<1>(0h0)
wire a_opcodes_set : UInt<4>
connect a_opcodes_set, UInt<4>(0h0)
wire a_sizes_set : UInt<8>
connect a_sizes_set, UInt<8>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<8>
connect a_size_lookup, UInt<8>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<5>
connect a_sizes_set_interm, UInt<5>(0h0)
node _T_1134 = and(io.in.a.valid, a_first_1)
node _T_1135 = and(_T_1134, UInt<1>(0h1))
when _T_1135 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1136 = and(io.in.a.ready, io.in.a.valid)
node _T_1137 = and(_T_1136, a_first_1)
node _T_1138 = and(_T_1137, UInt<1>(0h1))
when _T_1138 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1139 = dshr(inflight, io.in.a.bits.source)
node _T_1140 = bits(_T_1139, 0, 0)
node _T_1141 = eq(_T_1140, UInt<1>(0h0))
node _T_1142 = asUInt(reset)
node _T_1143 = eq(_T_1142, UInt<1>(0h0))
when _T_1143 :
node _T_1144 = eq(_T_1141, UInt<1>(0h0))
when _T_1144 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1141, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<1>
connect d_clr, UInt<1>(0h0)
wire d_clr_wo_ready : UInt<1>
connect d_clr_wo_ready, UInt<1>(0h0)
wire d_opcodes_clr : UInt<4>
connect d_opcodes_clr, UInt<4>(0h0)
wire d_sizes_clr : UInt<8>
connect d_sizes_clr, UInt<8>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1145 = and(io.in.d.valid, d_first_1)
node _T_1146 = and(_T_1145, UInt<1>(0h1))
node _T_1147 = eq(d_release_ack, UInt<1>(0h0))
node _T_1148 = and(_T_1146, _T_1147)
when _T_1148 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1149 = and(io.in.d.ready, io.in.d.valid)
node _T_1150 = and(_T_1149, d_first_1)
node _T_1151 = and(_T_1150, UInt<1>(0h1))
node _T_1152 = eq(d_release_ack, UInt<1>(0h0))
node _T_1153 = and(_T_1151, _T_1152)
when _T_1153 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1154 = and(io.in.d.valid, d_first_1)
node _T_1155 = and(_T_1154, UInt<1>(0h1))
node _T_1156 = eq(d_release_ack, UInt<1>(0h0))
node _T_1157 = and(_T_1155, _T_1156)
when _T_1157 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1158 = dshr(inflight, io.in.d.bits.source)
node _T_1159 = bits(_T_1158, 0, 0)
node _T_1160 = or(_T_1159, same_cycle_resp)
node _T_1161 = asUInt(reset)
node _T_1162 = eq(_T_1161, UInt<1>(0h0))
when _T_1162 :
node _T_1163 = eq(_T_1160, UInt<1>(0h0))
when _T_1163 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1160, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1164 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1165 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1166 = or(_T_1164, _T_1165)
node _T_1167 = asUInt(reset)
node _T_1168 = eq(_T_1167, UInt<1>(0h0))
when _T_1168 :
node _T_1169 = eq(_T_1166, UInt<1>(0h0))
when _T_1169 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1166, UInt<1>(0h1), "") : assert_100
node _T_1170 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1171 = asUInt(reset)
node _T_1172 = eq(_T_1171, UInt<1>(0h0))
when _T_1172 :
node _T_1173 = eq(_T_1170, UInt<1>(0h0))
when _T_1173 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1170, UInt<1>(0h1), "") : assert_101
else :
node _T_1174 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1175 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1176 = or(_T_1174, _T_1175)
node _T_1177 = asUInt(reset)
node _T_1178 = eq(_T_1177, UInt<1>(0h0))
when _T_1178 :
node _T_1179 = eq(_T_1176, UInt<1>(0h0))
when _T_1179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1176, UInt<1>(0h1), "") : assert_102
node _T_1180 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1181 = asUInt(reset)
node _T_1182 = eq(_T_1181, UInt<1>(0h0))
when _T_1182 :
node _T_1183 = eq(_T_1180, UInt<1>(0h0))
when _T_1183 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1180, UInt<1>(0h1), "") : assert_103
node _T_1184 = and(io.in.d.valid, d_first_1)
node _T_1185 = and(_T_1184, a_first_1)
node _T_1186 = and(_T_1185, io.in.a.valid)
node _T_1187 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1188 = and(_T_1186, _T_1187)
node _T_1189 = eq(d_release_ack, UInt<1>(0h0))
node _T_1190 = and(_T_1188, _T_1189)
when _T_1190 :
node _T_1191 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1192 = or(_T_1191, io.in.a.ready)
node _T_1193 = asUInt(reset)
node _T_1194 = eq(_T_1193, UInt<1>(0h0))
when _T_1194 :
node _T_1195 = eq(_T_1192, UInt<1>(0h0))
when _T_1195 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1192, UInt<1>(0h1), "") : assert_104
node _T_1196 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_1197 = orr(a_set_wo_ready)
node _T_1198 = eq(_T_1197, UInt<1>(0h0))
node _T_1199 = or(_T_1196, _T_1198)
node _T_1200 = asUInt(reset)
node _T_1201 = eq(_T_1200, UInt<1>(0h0))
when _T_1201 :
node _T_1202 = eq(_T_1199, UInt<1>(0h0))
when _T_1202 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_1199, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_88
node _T_1203 = orr(inflight)
node _T_1204 = eq(_T_1203, UInt<1>(0h0))
node _T_1205 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1206 = or(_T_1204, _T_1205)
node _T_1207 = lt(watchdog, plusarg_reader.out)
node _T_1208 = or(_T_1206, _T_1207)
node _T_1209 = asUInt(reset)
node _T_1210 = eq(_T_1209, UInt<1>(0h0))
when _T_1210 :
node _T_1211 = eq(_T_1208, UInt<1>(0h0))
when _T_1211 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1208, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1212 = and(io.in.a.ready, io.in.a.valid)
node _T_1213 = and(io.in.d.ready, io.in.d.valid)
node _T_1214 = or(_T_1212, _T_1213)
when _T_1214 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes_1 : UInt<8>, clock, reset, UInt<8>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<32>(0h0)
connect _c_first_WIRE.bits.source, UInt<1>(0h0)
connect _c_first_WIRE.bits.size, UInt<4>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<1>
connect c_set, UInt<1>(0h0)
wire c_set_wo_ready : UInt<1>
connect c_set_wo_ready, UInt<1>(0h0)
wire c_opcodes_set : UInt<4>
connect c_opcodes_set, UInt<4>(0h0)
wire c_sizes_set : UInt<8>
connect c_sizes_set, UInt<8>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<8>
connect c_size_lookup, UInt<8>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<5>
connect c_sizes_set_interm, UInt<5>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<1>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1215 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<1>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1216 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_1217 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_1218 = and(_T_1216, _T_1217)
node _T_1219 = and(_T_1215, _T_1218)
when _T_1219 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<32>(0h0)
connect _WIRE_10.bits.source, UInt<1>(0h0)
connect _WIRE_10.bits.size, UInt<4>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1220 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_1221 = and(_T_1220, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<32>(0h0)
connect _WIRE_12.bits.source, UInt<1>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1222 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1223 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1224 = and(_T_1222, _T_1223)
node _T_1225 = and(_T_1221, _T_1224)
when _T_1225 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<32>(0h0)
connect _WIRE_14.bits.source, UInt<1>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1226 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_1227 = bits(_T_1226, 0, 0)
node _T_1228 = eq(_T_1227, UInt<1>(0h0))
node _T_1229 = asUInt(reset)
node _T_1230 = eq(_T_1229, UInt<1>(0h0))
when _T_1230 :
node _T_1231 = eq(_T_1228, UInt<1>(0h0))
when _T_1231 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_1228, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<1>
connect d_clr_1, UInt<1>(0h0)
wire d_clr_wo_ready_1 : UInt<1>
connect d_clr_wo_ready_1, UInt<1>(0h0)
wire d_opcodes_clr_1 : UInt<4>
connect d_opcodes_clr_1, UInt<4>(0h0)
wire d_sizes_clr_1 : UInt<8>
connect d_sizes_clr_1, UInt<8>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1232 = and(io.in.d.valid, d_first_2)
node _T_1233 = and(_T_1232, UInt<1>(0h1))
node _T_1234 = and(_T_1233, d_release_ack_1)
when _T_1234 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1235 = and(io.in.d.ready, io.in.d.valid)
node _T_1236 = and(_T_1235, d_first_2)
node _T_1237 = and(_T_1236, UInt<1>(0h1))
node _T_1238 = and(_T_1237, d_release_ack_1)
when _T_1238 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1239 = and(io.in.d.valid, d_first_2)
node _T_1240 = and(_T_1239, UInt<1>(0h1))
node _T_1241 = and(_T_1240, d_release_ack_1)
when _T_1241 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1242 = dshr(inflight_1, io.in.d.bits.source)
node _T_1243 = bits(_T_1242, 0, 0)
node _T_1244 = or(_T_1243, same_cycle_resp_1)
node _T_1245 = asUInt(reset)
node _T_1246 = eq(_T_1245, UInt<1>(0h0))
when _T_1246 :
node _T_1247 = eq(_T_1244, UInt<1>(0h0))
when _T_1247 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1244, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<32>(0h0)
connect _WIRE_16.bits.source, UInt<1>(0h0)
connect _WIRE_16.bits.size, UInt<4>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1248 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_1249 = asUInt(reset)
node _T_1250 = eq(_T_1249, UInt<1>(0h0))
when _T_1250 :
node _T_1251 = eq(_T_1248, UInt<1>(0h0))
when _T_1251 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1248, UInt<1>(0h1), "") : assert_109
else :
node _T_1252 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1253 = asUInt(reset)
node _T_1254 = eq(_T_1253, UInt<1>(0h0))
when _T_1254 :
node _T_1255 = eq(_T_1252, UInt<1>(0h0))
when _T_1255 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1252, UInt<1>(0h1), "") : assert_110
node _T_1256 = and(io.in.d.valid, d_first_2)
node _T_1257 = and(_T_1256, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<32>(0h0)
connect _WIRE_18.bits.source, UInt<1>(0h0)
connect _WIRE_18.bits.size, UInt<4>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1258 = and(_T_1257, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<32>(0h0)
connect _WIRE_20.bits.source, UInt<1>(0h0)
connect _WIRE_20.bits.size, UInt<4>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1259 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_1260 = and(_T_1258, _T_1259)
node _T_1261 = and(_T_1260, d_release_ack_1)
node _T_1262 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1263 = and(_T_1261, _T_1262)
when _T_1263 :
node _T_1264 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<32>(0h0)
connect _WIRE_22.bits.source, UInt<1>(0h0)
connect _WIRE_22.bits.size, UInt<4>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1265 = or(_T_1264, _WIRE_23.ready)
node _T_1266 = asUInt(reset)
node _T_1267 = eq(_T_1266, UInt<1>(0h0))
when _T_1267 :
node _T_1268 = eq(_T_1265, UInt<1>(0h0))
when _T_1268 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_1265, UInt<1>(0h1), "") : assert_111
node _T_1269 = orr(c_set_wo_ready)
when _T_1269 :
node _T_1270 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_1271 = asUInt(reset)
node _T_1272 = eq(_T_1271, UInt<1>(0h0))
when _T_1272 :
node _T_1273 = eq(_T_1270, UInt<1>(0h0))
when _T_1273 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_1270, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_89
node _T_1274 = orr(inflight_1)
node _T_1275 = eq(_T_1274, UInt<1>(0h0))
node _T_1276 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1277 = or(_T_1275, _T_1276)
node _T_1278 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1279 = or(_T_1277, _T_1278)
node _T_1280 = asUInt(reset)
node _T_1281 = eq(_T_1280, UInt<1>(0h0))
when _T_1281 :
node _T_1282 = eq(_T_1279, UInt<1>(0h0))
when _T_1282 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_1279, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<32>(0h0)
connect _WIRE_24.bits.source, UInt<1>(0h0)
connect _WIRE_24.bits.size, UInt<4>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1283 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_1284 = and(io.in.d.ready, io.in.d.valid)
node _T_1285 = or(_T_1283, _T_1284)
when _T_1285 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_44( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready = 1'h1; // @[Monitor.scala:36:7]
wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9]
wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31]
wire mask_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21]
wire mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26]
wire mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_2_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_3_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_size = 1'h1; // @[Misc.scala:209:26]
wire mask_acc = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_2 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_3 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_4 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_5 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_6 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_7 = 1'h1; // @[Misc.scala:215:29]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9]
wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31]
wire sink_ok = 1'h1; // @[Monitor.scala:309:31]
wire _a_first_beats1_opdata_T = 1'h1; // @[Edges.scala:92:37]
wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last = 1'h1; // @[Edges.scala:232:33]
wire _a_first_beats1_opdata_T_1 = 1'h1; // @[Edges.scala:92:37]
wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113]
wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7]
wire mask_sub_size = 1'h0; // @[Misc.scala:209:26]
wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38]
wire a_first_beats1_opdata = 1'h0; // @[Edges.scala:92:28]
wire a_first_beats1_opdata_1 = 1'h0; // @[Edges.scala:92:28]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire c_set = 1'h0; // @[Monitor.scala:738:34]
wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [8:0] a_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] a_first_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] a_first_beats1_1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] a_first_count_1 = 9'h0; // @[Edges.scala:234:25]
wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27]
wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21]
wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28]
wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28]
wire [3:0] io_in_a_bits_size = 4'h6; // @[Monitor.scala:36:7]
wire [3:0] _mask_sizeOH_T = 4'h6; // @[Misc.scala:202:34]
wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] io_in_a_bits_opcode = 3'h4; // @[Monitor.scala:36:7]
wire [2:0] _mask_sizeOH_T_2 = 3'h4; // @[OneHot.scala:65:27]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [7:0] io_in_a_bits_mask = 8'hFF; // @[Monitor.scala:36:7]
wire [7:0] mask = 8'hFF; // @[Misc.scala:222:10]
wire [63:0] io_in_a_bits_data = 64'h0; // @[Monitor.scala:36:7]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69]
wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65]
wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79]
wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77]
wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101]
wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34]
wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69]
wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101]
wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [30:0] _d_sizes_clr_T_5 = 31'hFF; // @[Monitor.scala:681:74]
wire [30:0] _d_sizes_clr_T_11 = 31'hFF; // @[Monitor.scala:791:74]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _a_opcodes_set_interm_T = 4'h8; // @[Monitor.scala:657:53]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] mask_lo = 4'hF; // @[Misc.scala:222:10]
wire [3:0] mask_hi = 4'hF; // @[Misc.scala:222:10]
wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76]
wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [3:0] _mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35]
wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52]
wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [4:0] _a_sizes_set_interm_T_1 = 5'hD; // @[Monitor.scala:658:59]
wire [4:0] _a_sizes_set_interm_T = 5'hC; // @[Monitor.scala:658:51]
wire [3:0] _a_opcodes_set_interm_T_1 = 4'h9; // @[Monitor.scala:657:61]
wire [2:0] mask_sizeOH = 3'h5; // @[Misc.scala:202:81]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [8:0] a_first_beats1_decode = 9'h7; // @[Edges.scala:220:59]
wire [8:0] a_first_beats1_decode_1 = 9'h7; // @[Edges.scala:220:59]
wire [11:0] is_aligned_mask = 12'h3F; // @[package.scala:243:46]
wire [11:0] _a_first_beats1_decode_T_2 = 12'h3F; // @[package.scala:243:46]
wire [11:0] _a_first_beats1_decode_T_5 = 12'h3F; // @[package.scala:243:46]
wire [11:0] _is_aligned_mask_T_1 = 12'hFC0; // @[package.scala:243:76]
wire [11:0] _a_first_beats1_decode_T_1 = 12'hFC0; // @[package.scala:243:76]
wire [11:0] _a_first_beats1_decode_T_4 = 12'hFC0; // @[package.scala:243:76]
wire [26:0] _is_aligned_mask_T = 27'h3FFC0; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T = 27'h3FFC0; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3 = 27'h3FFC0; // @[package.scala:243:71]
wire [1:0] mask_lo_lo = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_lo_hi = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_hi_hi = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49]
wire _d_first_T = io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T_1 = io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T_2 = io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0]}; // @[Monitor.scala:36:7]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_0_2; // @[Misc.scala:214:27, :215:38]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_1_2; // @[Misc.scala:214:27, :215:38]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_eq_4; // @[Misc.scala:214:27, :215:38]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_eq_5; // @[Misc.scala:214:27, :215:38]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_eq_6; // @[Misc.scala:214:27, :215:38]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_eq_7; // @[Misc.scala:214:27, :215:38]
wire _T_1212 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1212; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1212; // @[Decoupled.scala:51:35]
wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] _a_first_counter_T = a_first ? 9'h0 : a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [31:0] address; // @[Monitor.scala:391:22]
wire [26:0] _GEN = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [2:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [1:0] inflight; // @[Monitor.scala:614:27]
reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35]
wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44]
reg [7:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [7:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40]
wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? 9'h0 : a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire a_set; // @[Monitor.scala:626:34]
wire a_set_wo_ready; // @[Monitor.scala:627:34]
wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [7:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}]
wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}]
wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _T_1135 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26]
assign a_set_wo_ready = _T_1135; // @[Monitor.scala:627:34, :651:26]
wire _same_cycle_resp_T; // @[Monitor.scala:684:44]
assign _same_cycle_resp_T = _T_1135; // @[Monitor.scala:651:26, :684:44]
assign a_set = _T_1212 & a_first_1; // @[Decoupled.scala:51:35]
assign a_opcodes_set_interm = a_set ? 4'h9 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:28]
assign a_sizes_set_interm = a_set ? 5'hD : 5'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:28]
wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[package.scala:243:71]
assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}]
wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[package.scala:243:71]
assign a_sizes_set = a_set ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}]
wire d_clr; // @[Monitor.scala:664:34]
wire d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_0 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_0; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_0; // @[Monitor.scala:673:46, :783:46]
wire _T_1184 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
assign d_clr_wo_ready = _T_1184 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}]
assign d_clr = io_in_d_valid_0 & d_first_1 & ~d_release_ack; // @[Monitor.scala:36:7, :664:34, :673:46, :674:74, :678:{25,70}]
assign d_opcodes_clr = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21]
assign d_sizes_clr = {8{d_clr}}; // @[Monitor.scala:664:34, :670:31, :678:89, :681:21]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}]
wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27]
wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}]
wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [7:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [1:0] inflight_1; // @[Monitor.scala:726:35]
wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44]
wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42]
wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}]
wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}]
wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire d_clr_1; // @[Monitor.scala:774:34]
wire d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1256 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1256 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}]
assign d_clr_1 = io_in_d_valid_0 & d_first_2 & d_release_ack_1; // @[Monitor.scala:36:7, :774:34, :783:46, :788:{25,70}]
assign d_opcodes_clr_1 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21]
assign d_sizes_clr_1 = {8{d_clr_1}}; // @[Monitor.scala:774:34, :777:34, :788:88, :791:21]
wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}]
wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_230 :
input clock : Clock
input reset : Reset
output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}}
regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff)
reg value_reg : { symbol : UInt<10>}, clock
connect io.output_prev.key, key_reg
connect io.output_prev.value, value_reg
connect io.output_nxt.key, key_reg
connect io.output_nxt.value, value_reg
connect io.cur_output_keyval.key, key_reg
connect io.cur_output_keyval.value, value_reg
when io.cmd.valid :
node _T = eq(UInt<1>(0h0), io.cmd.bits)
when _T :
connect key_reg, io.input_nxt.key
connect value_reg, io.input_nxt.value
else :
node _T_1 = eq(UInt<1>(0h1), io.cmd.bits)
when _T_1 :
when io.insert_here :
connect key_reg, io.cur_input_keyval.key
connect value_reg, io.cur_input_keyval.value
else :
node _T_2 = geq(key_reg, io.cur_input_keyval.key)
when _T_2 :
connect key_reg, io.input_prev.key
connect value_reg, io.input_prev.value
else :
skip | module PriorityQueueStage_230( // @[ShiftRegisterPriorityQueue.scala:21:7]
input clock, // @[ShiftRegisterPriorityQueue.scala:21:7]
input reset, // @[ShiftRegisterPriorityQueue.scala:21:7]
output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14]
);
wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24]
assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22]
assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30]
always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24]
else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
always @(posedge)
assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module SourceB :
input clock : Clock
input reset : Reset
output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<13>, set : UInt<10>, clients : UInt<1>}}, b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}}
connect io.req.ready, UInt<1>(0h1)
connect io.b.valid, UInt<1>(0h0)
invalidate io.b.bits.corrupt
invalidate io.b.bits.data
invalidate io.b.bits.mask
invalidate io.b.bits.address
invalidate io.b.bits.source
invalidate io.b.bits.size
invalidate io.b.bits.param
invalidate io.b.bits.opcode | module SourceB( // @[SourceB.scala:33:7]
input clock, // @[SourceB.scala:33:7]
input reset, // @[SourceB.scala:33:7]
input [2:0] io_req_bits_param, // @[SourceB.scala:35:14]
input [12:0] io_req_bits_tag, // @[SourceB.scala:35:14]
input [9:0] io_req_bits_set, // @[SourceB.scala:35:14]
input io_req_bits_clients // @[SourceB.scala:35:14]
);
wire [2:0] io_req_bits_param_0 = io_req_bits_param; // @[SourceB.scala:33:7]
wire [12:0] io_req_bits_tag_0 = io_req_bits_tag; // @[SourceB.scala:33:7]
wire [9:0] io_req_bits_set_0 = io_req_bits_set; // @[SourceB.scala:33:7]
wire io_req_bits_clients_0 = io_req_bits_clients; // @[SourceB.scala:33:7]
wire [63:0] io_b_bits_data = 64'h0; // @[SourceB.scala:33:7]
wire [7:0] io_b_bits_mask = 8'h0; // @[SourceB.scala:33:7]
wire [31:0] io_b_bits_address = 32'h0; // @[SourceB.scala:33:7]
wire [5:0] io_b_bits_source = 6'h0; // @[SourceB.scala:33:7]
wire [1:0] io_b_bits_param = 2'h0; // @[SourceB.scala:33:7]
wire [2:0] io_b_bits_opcode = 3'h0; // @[SourceB.scala:33:7]
wire [2:0] io_b_bits_size = 3'h0; // @[SourceB.scala:33:7]
wire io_req_valid = 1'h0; // @[SourceB.scala:33:7]
wire io_b_ready = 1'h0; // @[SourceB.scala:33:7]
wire io_b_valid = 1'h0; // @[SourceB.scala:33:7]
wire io_b_bits_corrupt = 1'h0; // @[SourceB.scala:33:7]
wire io_req_ready = 1'h1; // @[SourceB.scala:33:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_42 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_42( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module Repeater_TLBundleA_a28d64s8k1z3u :
input clock : Clock
input reset : Reset
output io : { flip repeat : UInt<1>, full : UInt<1>, flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}}
regreset full : UInt<1>, clock, reset, UInt<1>(0h0)
reg saved : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}, clock
node _io_deq_valid_T = or(io.enq.valid, full)
connect io.deq.valid, _io_deq_valid_T
node _io_enq_ready_T = eq(full, UInt<1>(0h0))
node _io_enq_ready_T_1 = and(io.deq.ready, _io_enq_ready_T)
connect io.enq.ready, _io_enq_ready_T_1
node _io_deq_bits_T = mux(full, saved, io.enq.bits)
connect io.deq.bits, _io_deq_bits_T
connect io.full, full
node _T = and(io.enq.ready, io.enq.valid)
node _T_1 = and(_T, io.repeat)
when _T_1 :
connect full, UInt<1>(0h1)
connect saved, io.enq.bits
node _T_2 = and(io.deq.ready, io.deq.valid)
node _T_3 = eq(io.repeat, UInt<1>(0h0))
node _T_4 = and(_T_2, _T_3)
when _T_4 :
connect full, UInt<1>(0h0) | module Repeater_TLBundleA_a28d64s8k1z3u( // @[Repeater.scala:10:7]
input clock, // @[Repeater.scala:10:7]
input reset, // @[Repeater.scala:10:7]
input io_repeat, // @[Repeater.scala:13:14]
output io_full, // @[Repeater.scala:13:14]
output io_enq_ready, // @[Repeater.scala:13:14]
input io_enq_valid, // @[Repeater.scala:13:14]
input [2:0] io_enq_bits_opcode, // @[Repeater.scala:13:14]
input [2:0] io_enq_bits_param, // @[Repeater.scala:13:14]
input [2:0] io_enq_bits_size, // @[Repeater.scala:13:14]
input [7:0] io_enq_bits_source, // @[Repeater.scala:13:14]
input [27:0] io_enq_bits_address, // @[Repeater.scala:13:14]
input [7:0] io_enq_bits_mask, // @[Repeater.scala:13:14]
input [63:0] io_enq_bits_data, // @[Repeater.scala:13:14]
input io_enq_bits_corrupt, // @[Repeater.scala:13:14]
input io_deq_ready, // @[Repeater.scala:13:14]
output io_deq_valid, // @[Repeater.scala:13:14]
output [2:0] io_deq_bits_opcode, // @[Repeater.scala:13:14]
output [2:0] io_deq_bits_param, // @[Repeater.scala:13:14]
output [2:0] io_deq_bits_size, // @[Repeater.scala:13:14]
output [7:0] io_deq_bits_source, // @[Repeater.scala:13:14]
output [27:0] io_deq_bits_address, // @[Repeater.scala:13:14]
output [7:0] io_deq_bits_mask, // @[Repeater.scala:13:14]
output io_deq_bits_corrupt // @[Repeater.scala:13:14]
);
wire io_repeat_0 = io_repeat; // @[Repeater.scala:10:7]
wire io_enq_valid_0 = io_enq_valid; // @[Repeater.scala:10:7]
wire [2:0] io_enq_bits_opcode_0 = io_enq_bits_opcode; // @[Repeater.scala:10:7]
wire [2:0] io_enq_bits_param_0 = io_enq_bits_param; // @[Repeater.scala:10:7]
wire [2:0] io_enq_bits_size_0 = io_enq_bits_size; // @[Repeater.scala:10:7]
wire [7:0] io_enq_bits_source_0 = io_enq_bits_source; // @[Repeater.scala:10:7]
wire [27:0] io_enq_bits_address_0 = io_enq_bits_address; // @[Repeater.scala:10:7]
wire [7:0] io_enq_bits_mask_0 = io_enq_bits_mask; // @[Repeater.scala:10:7]
wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[Repeater.scala:10:7]
wire io_enq_bits_corrupt_0 = io_enq_bits_corrupt; // @[Repeater.scala:10:7]
wire io_deq_ready_0 = io_deq_ready; // @[Repeater.scala:10:7]
wire _io_enq_ready_T_1; // @[Repeater.scala:25:32]
wire _io_deq_valid_T; // @[Repeater.scala:24:32]
wire [2:0] _io_deq_bits_T_opcode; // @[Repeater.scala:26:21]
wire [2:0] _io_deq_bits_T_param; // @[Repeater.scala:26:21]
wire [2:0] _io_deq_bits_T_size; // @[Repeater.scala:26:21]
wire [7:0] _io_deq_bits_T_source; // @[Repeater.scala:26:21]
wire [27:0] _io_deq_bits_T_address; // @[Repeater.scala:26:21]
wire [7:0] _io_deq_bits_T_mask; // @[Repeater.scala:26:21]
wire [63:0] _io_deq_bits_T_data; // @[Repeater.scala:26:21]
wire _io_deq_bits_T_corrupt; // @[Repeater.scala:26:21]
wire io_enq_ready_0; // @[Repeater.scala:10:7]
wire [2:0] io_deq_bits_opcode_0; // @[Repeater.scala:10:7]
wire [2:0] io_deq_bits_param_0; // @[Repeater.scala:10:7]
wire [2:0] io_deq_bits_size_0; // @[Repeater.scala:10:7]
wire [7:0] io_deq_bits_source_0; // @[Repeater.scala:10:7]
wire [27:0] io_deq_bits_address_0; // @[Repeater.scala:10:7]
wire [7:0] io_deq_bits_mask_0; // @[Repeater.scala:10:7]
wire [63:0] io_deq_bits_data; // @[Repeater.scala:10:7]
wire io_deq_bits_corrupt_0; // @[Repeater.scala:10:7]
wire io_deq_valid_0; // @[Repeater.scala:10:7]
wire io_full_0; // @[Repeater.scala:10:7]
reg full; // @[Repeater.scala:20:21]
assign io_full_0 = full; // @[Repeater.scala:10:7, :20:21]
reg [2:0] saved_opcode; // @[Repeater.scala:21:18]
reg [2:0] saved_param; // @[Repeater.scala:21:18]
reg [2:0] saved_size; // @[Repeater.scala:21:18]
reg [7:0] saved_source; // @[Repeater.scala:21:18]
reg [27:0] saved_address; // @[Repeater.scala:21:18]
reg [7:0] saved_mask; // @[Repeater.scala:21:18]
reg [63:0] saved_data; // @[Repeater.scala:21:18]
reg saved_corrupt; // @[Repeater.scala:21:18]
assign _io_deq_valid_T = io_enq_valid_0 | full; // @[Repeater.scala:10:7, :20:21, :24:32]
assign io_deq_valid_0 = _io_deq_valid_T; // @[Repeater.scala:10:7, :24:32]
wire _io_enq_ready_T = ~full; // @[Repeater.scala:20:21, :25:35]
assign _io_enq_ready_T_1 = io_deq_ready_0 & _io_enq_ready_T; // @[Repeater.scala:10:7, :25:{32,35}]
assign io_enq_ready_0 = _io_enq_ready_T_1; // @[Repeater.scala:10:7, :25:32]
assign _io_deq_bits_T_opcode = full ? saved_opcode : io_enq_bits_opcode_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_param = full ? saved_param : io_enq_bits_param_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_size = full ? saved_size : io_enq_bits_size_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_source = full ? saved_source : io_enq_bits_source_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_address = full ? saved_address : io_enq_bits_address_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_mask = full ? saved_mask : io_enq_bits_mask_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_data = full ? saved_data : io_enq_bits_data_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_corrupt = full ? saved_corrupt : io_enq_bits_corrupt_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign io_deq_bits_opcode_0 = _io_deq_bits_T_opcode; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_param_0 = _io_deq_bits_T_param; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_size_0 = _io_deq_bits_T_size; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_source_0 = _io_deq_bits_T_source; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_address_0 = _io_deq_bits_T_address; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_mask_0 = _io_deq_bits_T_mask; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_data = _io_deq_bits_T_data; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_corrupt_0 = _io_deq_bits_T_corrupt; // @[Repeater.scala:10:7, :26:21]
wire _T_1 = io_enq_ready_0 & io_enq_valid_0 & io_repeat_0; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[Repeater.scala:10:7]
if (reset) // @[Repeater.scala:10:7]
full <= 1'h0; // @[Repeater.scala:20:21]
else // @[Repeater.scala:10:7]
full <= ~(io_deq_ready_0 & io_deq_valid_0 & ~io_repeat_0) & (_T_1 | full); // @[Decoupled.scala:51:35]
if (_T_1) begin // @[Decoupled.scala:51:35]
saved_opcode <= io_enq_bits_opcode_0; // @[Repeater.scala:10:7, :21:18]
saved_param <= io_enq_bits_param_0; // @[Repeater.scala:10:7, :21:18]
saved_size <= io_enq_bits_size_0; // @[Repeater.scala:10:7, :21:18]
saved_source <= io_enq_bits_source_0; // @[Repeater.scala:10:7, :21:18]
saved_address <= io_enq_bits_address_0; // @[Repeater.scala:10:7, :21:18]
saved_mask <= io_enq_bits_mask_0; // @[Repeater.scala:10:7, :21:18]
saved_data <= io_enq_bits_data_0; // @[Repeater.scala:10:7, :21:18]
saved_corrupt <= io_enq_bits_corrupt_0; // @[Repeater.scala:10:7, :21:18]
end
always @(posedge)
assign io_full = io_full_0; // @[Repeater.scala:10:7]
assign io_enq_ready = io_enq_ready_0; // @[Repeater.scala:10:7]
assign io_deq_valid = io_deq_valid_0; // @[Repeater.scala:10:7]
assign io_deq_bits_opcode = io_deq_bits_opcode_0; // @[Repeater.scala:10:7]
assign io_deq_bits_param = io_deq_bits_param_0; // @[Repeater.scala:10:7]
assign io_deq_bits_size = io_deq_bits_size_0; // @[Repeater.scala:10:7]
assign io_deq_bits_source = io_deq_bits_source_0; // @[Repeater.scala:10:7]
assign io_deq_bits_address = io_deq_bits_address_0; // @[Repeater.scala:10:7]
assign io_deq_bits_mask = io_deq_bits_mask_0; // @[Repeater.scala:10:7]
assign io_deq_bits_corrupt = io_deq_bits_corrupt_0; // @[Repeater.scala:10:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module ProbePicker :
input clock : Clock
input reset : Reset
output auto : { flip in_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip in_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeIn.d.bits.corrupt
invalidate nodeIn.d.bits.data
invalidate nodeIn.d.bits.denied
invalidate nodeIn.d.bits.sink
invalidate nodeIn.d.bits.source
invalidate nodeIn.d.bits.size
invalidate nodeIn.d.bits.param
invalidate nodeIn.d.bits.opcode
invalidate nodeIn.d.valid
invalidate nodeIn.d.ready
invalidate nodeIn.a.bits.corrupt
invalidate nodeIn.a.bits.data
invalidate nodeIn.a.bits.mask
invalidate nodeIn.a.bits.address
invalidate nodeIn.a.bits.source
invalidate nodeIn.a.bits.size
invalidate nodeIn.a.bits.param
invalidate nodeIn.a.bits.opcode
invalidate nodeIn.a.valid
invalidate nodeIn.a.ready
wire nodeIn_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeIn_1.d.bits.corrupt
invalidate nodeIn_1.d.bits.data
invalidate nodeIn_1.d.bits.denied
invalidate nodeIn_1.d.bits.sink
invalidate nodeIn_1.d.bits.source
invalidate nodeIn_1.d.bits.size
invalidate nodeIn_1.d.bits.param
invalidate nodeIn_1.d.bits.opcode
invalidate nodeIn_1.d.valid
invalidate nodeIn_1.d.ready
invalidate nodeIn_1.a.bits.corrupt
invalidate nodeIn_1.a.bits.data
invalidate nodeIn_1.a.bits.mask
invalidate nodeIn_1.a.bits.address
invalidate nodeIn_1.a.bits.source
invalidate nodeIn_1.a.bits.size
invalidate nodeIn_1.a.bits.param
invalidate nodeIn_1.a.bits.opcode
invalidate nodeIn_1.a.valid
invalidate nodeIn_1.a.ready
inst monitor of TLMonitor_29
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, nodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, nodeIn.d.bits.source
connect monitor.io.in.d.bits.size, nodeIn.d.bits.size
connect monitor.io.in.d.bits.param, nodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode
connect monitor.io.in.d.valid, nodeIn.d.valid
connect monitor.io.in.d.ready, nodeIn.d.ready
connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, nodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, nodeIn.a.bits.address
connect monitor.io.in.a.bits.source, nodeIn.a.bits.source
connect monitor.io.in.a.bits.size, nodeIn.a.bits.size
connect monitor.io.in.a.bits.param, nodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode
connect monitor.io.in.a.valid, nodeIn.a.valid
connect monitor.io.in.a.ready, nodeIn.a.ready
inst monitor_1 of TLMonitor_30
connect monitor_1.clock, clock
connect monitor_1.reset, reset
connect monitor_1.io.in.d.bits.corrupt, nodeIn_1.d.bits.corrupt
connect monitor_1.io.in.d.bits.data, nodeIn_1.d.bits.data
connect monitor_1.io.in.d.bits.denied, nodeIn_1.d.bits.denied
connect monitor_1.io.in.d.bits.sink, nodeIn_1.d.bits.sink
connect monitor_1.io.in.d.bits.source, nodeIn_1.d.bits.source
connect monitor_1.io.in.d.bits.size, nodeIn_1.d.bits.size
connect monitor_1.io.in.d.bits.param, nodeIn_1.d.bits.param
connect monitor_1.io.in.d.bits.opcode, nodeIn_1.d.bits.opcode
connect monitor_1.io.in.d.valid, nodeIn_1.d.valid
connect monitor_1.io.in.d.ready, nodeIn_1.d.ready
connect monitor_1.io.in.a.bits.corrupt, nodeIn_1.a.bits.corrupt
connect monitor_1.io.in.a.bits.data, nodeIn_1.a.bits.data
connect monitor_1.io.in.a.bits.mask, nodeIn_1.a.bits.mask
connect monitor_1.io.in.a.bits.address, nodeIn_1.a.bits.address
connect monitor_1.io.in.a.bits.source, nodeIn_1.a.bits.source
connect monitor_1.io.in.a.bits.size, nodeIn_1.a.bits.size
connect monitor_1.io.in.a.bits.param, nodeIn_1.a.bits.param
connect monitor_1.io.in.a.bits.opcode, nodeIn_1.a.bits.opcode
connect monitor_1.io.in.a.valid, nodeIn_1.a.valid
connect monitor_1.io.in.a.ready, nodeIn_1.a.ready
wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeOut.d.bits.corrupt
invalidate nodeOut.d.bits.data
invalidate nodeOut.d.bits.denied
invalidate nodeOut.d.bits.sink
invalidate nodeOut.d.bits.source
invalidate nodeOut.d.bits.size
invalidate nodeOut.d.bits.param
invalidate nodeOut.d.bits.opcode
invalidate nodeOut.d.valid
invalidate nodeOut.d.ready
invalidate nodeOut.a.bits.corrupt
invalidate nodeOut.a.bits.data
invalidate nodeOut.a.bits.mask
invalidate nodeOut.a.bits.address
invalidate nodeOut.a.bits.source
invalidate nodeOut.a.bits.size
invalidate nodeOut.a.bits.param
invalidate nodeOut.a.bits.opcode
invalidate nodeOut.a.valid
invalidate nodeOut.a.ready
wire x1_nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate x1_nodeOut.d.bits.corrupt
invalidate x1_nodeOut.d.bits.data
invalidate x1_nodeOut.d.bits.denied
invalidate x1_nodeOut.d.bits.sink
invalidate x1_nodeOut.d.bits.source
invalidate x1_nodeOut.d.bits.size
invalidate x1_nodeOut.d.bits.param
invalidate x1_nodeOut.d.bits.opcode
invalidate x1_nodeOut.d.valid
invalidate x1_nodeOut.d.ready
invalidate x1_nodeOut.a.bits.corrupt
invalidate x1_nodeOut.a.bits.data
invalidate x1_nodeOut.a.bits.mask
invalidate x1_nodeOut.a.bits.address
invalidate x1_nodeOut.a.bits.source
invalidate x1_nodeOut.a.bits.size
invalidate x1_nodeOut.a.bits.param
invalidate x1_nodeOut.a.bits.opcode
invalidate x1_nodeOut.a.valid
invalidate x1_nodeOut.a.ready
connect auto.out_0, nodeOut
connect auto.out_1, x1_nodeOut
connect nodeIn, auto.in_0
connect nodeIn_1, auto.in_1
connect nodeOut, nodeIn
connect x1_nodeOut, nodeIn_1 | module ProbePicker( // @[ProbePicker.scala:42:9]
input clock, // @[ProbePicker.scala:42:9]
input reset, // @[ProbePicker.scala:42:9]
output auto_in_1_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_1_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_1_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_1_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_1_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [27:0] auto_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_1_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_1_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_1_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_1_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_in_1_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_0_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_0_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_0_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_0_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_0_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_0_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_0_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_1_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_1_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [27:0] auto_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_1_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_1_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_0_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_0_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_0_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_0_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_0_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_0_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
TLMonitor_29 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (auto_out_0_a_ready),
.io_in_a_valid (auto_in_0_a_valid),
.io_in_a_bits_opcode (auto_in_0_a_bits_opcode),
.io_in_a_bits_param (auto_in_0_a_bits_param),
.io_in_a_bits_size (auto_in_0_a_bits_size),
.io_in_a_bits_source (auto_in_0_a_bits_source),
.io_in_a_bits_address (auto_in_0_a_bits_address),
.io_in_a_bits_mask (auto_in_0_a_bits_mask),
.io_in_a_bits_corrupt (auto_in_0_a_bits_corrupt),
.io_in_d_ready (auto_in_0_d_ready),
.io_in_d_valid (auto_out_0_d_valid),
.io_in_d_bits_opcode (auto_out_0_d_bits_opcode),
.io_in_d_bits_size (auto_out_0_d_bits_size),
.io_in_d_bits_source (auto_out_0_d_bits_source),
.io_in_d_bits_denied (auto_out_0_d_bits_denied),
.io_in_d_bits_corrupt (auto_out_0_d_bits_corrupt)
); // @[Nodes.scala:27:25]
TLMonitor_30 monitor_1 ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (auto_out_1_a_ready),
.io_in_a_valid (auto_in_1_a_valid),
.io_in_a_bits_opcode (auto_in_1_a_bits_opcode),
.io_in_a_bits_param (auto_in_1_a_bits_param),
.io_in_a_bits_size (auto_in_1_a_bits_size),
.io_in_a_bits_source (auto_in_1_a_bits_source),
.io_in_a_bits_address (auto_in_1_a_bits_address),
.io_in_a_bits_mask (auto_in_1_a_bits_mask),
.io_in_a_bits_corrupt (auto_in_1_a_bits_corrupt),
.io_in_d_ready (auto_in_1_d_ready),
.io_in_d_valid (auto_out_1_d_valid),
.io_in_d_bits_opcode (auto_out_1_d_bits_opcode),
.io_in_d_bits_param (auto_out_1_d_bits_param),
.io_in_d_bits_size (auto_out_1_d_bits_size),
.io_in_d_bits_source (auto_out_1_d_bits_source),
.io_in_d_bits_sink (auto_out_1_d_bits_sink),
.io_in_d_bits_denied (auto_out_1_d_bits_denied),
.io_in_d_bits_corrupt (auto_out_1_d_bits_corrupt)
); // @[Nodes.scala:27:25]
assign auto_in_1_a_ready = auto_out_1_a_ready; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_valid = auto_out_1_d_valid; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_opcode = auto_out_1_d_bits_opcode; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_param = auto_out_1_d_bits_param; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_size = auto_out_1_d_bits_size; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_source = auto_out_1_d_bits_source; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_sink = auto_out_1_d_bits_sink; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_denied = auto_out_1_d_bits_denied; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_data = auto_out_1_d_bits_data; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_corrupt = auto_out_1_d_bits_corrupt; // @[ProbePicker.scala:42:9]
assign auto_in_0_a_ready = auto_out_0_a_ready; // @[ProbePicker.scala:42:9]
assign auto_in_0_d_valid = auto_out_0_d_valid; // @[ProbePicker.scala:42:9]
assign auto_in_0_d_bits_opcode = auto_out_0_d_bits_opcode; // @[ProbePicker.scala:42:9]
assign auto_in_0_d_bits_size = auto_out_0_d_bits_size; // @[ProbePicker.scala:42:9]
assign auto_in_0_d_bits_source = auto_out_0_d_bits_source; // @[ProbePicker.scala:42:9]
assign auto_in_0_d_bits_denied = auto_out_0_d_bits_denied; // @[ProbePicker.scala:42:9]
assign auto_in_0_d_bits_data = auto_out_0_d_bits_data; // @[ProbePicker.scala:42:9]
assign auto_in_0_d_bits_corrupt = auto_out_0_d_bits_corrupt; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_valid = auto_in_1_a_valid; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_opcode = auto_in_1_a_bits_opcode; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_param = auto_in_1_a_bits_param; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_size = auto_in_1_a_bits_size; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_source = auto_in_1_a_bits_source; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_address = auto_in_1_a_bits_address; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_mask = auto_in_1_a_bits_mask; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_data = auto_in_1_a_bits_data; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_corrupt = auto_in_1_a_bits_corrupt; // @[ProbePicker.scala:42:9]
assign auto_out_1_d_ready = auto_in_1_d_ready; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_valid = auto_in_0_a_valid; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_opcode = auto_in_0_a_bits_opcode; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_param = auto_in_0_a_bits_param; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_size = auto_in_0_a_bits_size; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_source = auto_in_0_a_bits_source; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_address = auto_in_0_a_bits_address; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_mask = auto_in_0_a_bits_mask; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_data = auto_in_0_a_bits_data; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_corrupt = auto_in_0_a_bits_corrupt; // @[ProbePicker.scala:42:9]
assign auto_out_0_d_ready = auto_in_0_d_ready; // @[ProbePicker.scala:42:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_66 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_66( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module Router_1 :
input clock : Clock
input reset : Reset
output auto : { debug_out : { va_stall : UInt[5], sa_stall : UInt[5]}, egress_nodes_out : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, ingress_id : UInt}}}, flip ingress_nodes_in_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, egress_id : UInt}}}, flip ingress_nodes_in_0 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, egress_id : UInt}}}, source_nodes_out_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}, source_nodes_out_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}, source_nodes_out_0 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}, flip dest_nodes_in_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}, flip dest_nodes_in_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}, flip dest_nodes_in_0 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}}
wire destNodesIn : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}
invalidate destNodesIn.vc_free
invalidate destNodesIn.credit_return
invalidate destNodesIn.flit[0].bits.virt_channel_id
invalidate destNodesIn.flit[0].bits.flow.egress_node_id
invalidate destNodesIn.flit[0].bits.flow.egress_node
invalidate destNodesIn.flit[0].bits.flow.ingress_node_id
invalidate destNodesIn.flit[0].bits.flow.ingress_node
invalidate destNodesIn.flit[0].bits.flow.vnet_id
invalidate destNodesIn.flit[0].bits.payload
invalidate destNodesIn.flit[0].bits.tail
invalidate destNodesIn.flit[0].bits.head
invalidate destNodesIn.flit[0].valid
inst monitor of NoCMonitor_2
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.vc_free, destNodesIn.vc_free
connect monitor.io.in.credit_return, destNodesIn.credit_return
connect monitor.io.in.flit[0].bits.virt_channel_id, destNodesIn.flit[0].bits.virt_channel_id
connect monitor.io.in.flit[0].bits.flow.egress_node_id, destNodesIn.flit[0].bits.flow.egress_node_id
connect monitor.io.in.flit[0].bits.flow.egress_node, destNodesIn.flit[0].bits.flow.egress_node
connect monitor.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn.flit[0].bits.flow.ingress_node_id
connect monitor.io.in.flit[0].bits.flow.ingress_node, destNodesIn.flit[0].bits.flow.ingress_node
connect monitor.io.in.flit[0].bits.flow.vnet_id, destNodesIn.flit[0].bits.flow.vnet_id
connect monitor.io.in.flit[0].bits.payload, destNodesIn.flit[0].bits.payload
connect monitor.io.in.flit[0].bits.tail, destNodesIn.flit[0].bits.tail
connect monitor.io.in.flit[0].bits.head, destNodesIn.flit[0].bits.head
connect monitor.io.in.flit[0].valid, destNodesIn.flit[0].valid
wire destNodesIn_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}
invalidate destNodesIn_1.vc_free
invalidate destNodesIn_1.credit_return
invalidate destNodesIn_1.flit[0].bits.virt_channel_id
invalidate destNodesIn_1.flit[0].bits.flow.egress_node_id
invalidate destNodesIn_1.flit[0].bits.flow.egress_node
invalidate destNodesIn_1.flit[0].bits.flow.ingress_node_id
invalidate destNodesIn_1.flit[0].bits.flow.ingress_node
invalidate destNodesIn_1.flit[0].bits.flow.vnet_id
invalidate destNodesIn_1.flit[0].bits.payload
invalidate destNodesIn_1.flit[0].bits.tail
invalidate destNodesIn_1.flit[0].bits.head
invalidate destNodesIn_1.flit[0].valid
inst monitor_1 of NoCMonitor_3
connect monitor_1.clock, clock
connect monitor_1.reset, reset
connect monitor_1.io.in.vc_free, destNodesIn_1.vc_free
connect monitor_1.io.in.credit_return, destNodesIn_1.credit_return
connect monitor_1.io.in.flit[0].bits.virt_channel_id, destNodesIn_1.flit[0].bits.virt_channel_id
connect monitor_1.io.in.flit[0].bits.flow.egress_node_id, destNodesIn_1.flit[0].bits.flow.egress_node_id
connect monitor_1.io.in.flit[0].bits.flow.egress_node, destNodesIn_1.flit[0].bits.flow.egress_node
connect monitor_1.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn_1.flit[0].bits.flow.ingress_node_id
connect monitor_1.io.in.flit[0].bits.flow.ingress_node, destNodesIn_1.flit[0].bits.flow.ingress_node
connect monitor_1.io.in.flit[0].bits.flow.vnet_id, destNodesIn_1.flit[0].bits.flow.vnet_id
connect monitor_1.io.in.flit[0].bits.payload, destNodesIn_1.flit[0].bits.payload
connect monitor_1.io.in.flit[0].bits.tail, destNodesIn_1.flit[0].bits.tail
connect monitor_1.io.in.flit[0].bits.head, destNodesIn_1.flit[0].bits.head
connect monitor_1.io.in.flit[0].valid, destNodesIn_1.flit[0].valid
wire destNodesIn_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}
invalidate destNodesIn_2.vc_free
invalidate destNodesIn_2.credit_return
invalidate destNodesIn_2.flit[0].bits.virt_channel_id
invalidate destNodesIn_2.flit[0].bits.flow.egress_node_id
invalidate destNodesIn_2.flit[0].bits.flow.egress_node
invalidate destNodesIn_2.flit[0].bits.flow.ingress_node_id
invalidate destNodesIn_2.flit[0].bits.flow.ingress_node
invalidate destNodesIn_2.flit[0].bits.flow.vnet_id
invalidate destNodesIn_2.flit[0].bits.payload
invalidate destNodesIn_2.flit[0].bits.tail
invalidate destNodesIn_2.flit[0].bits.head
invalidate destNodesIn_2.flit[0].valid
inst monitor_2 of NoCMonitor_4
connect monitor_2.clock, clock
connect monitor_2.reset, reset
connect monitor_2.io.in.vc_free, destNodesIn_2.vc_free
connect monitor_2.io.in.credit_return, destNodesIn_2.credit_return
connect monitor_2.io.in.flit[0].bits.virt_channel_id, destNodesIn_2.flit[0].bits.virt_channel_id
connect monitor_2.io.in.flit[0].bits.flow.egress_node_id, destNodesIn_2.flit[0].bits.flow.egress_node_id
connect monitor_2.io.in.flit[0].bits.flow.egress_node, destNodesIn_2.flit[0].bits.flow.egress_node
connect monitor_2.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn_2.flit[0].bits.flow.ingress_node_id
connect monitor_2.io.in.flit[0].bits.flow.ingress_node, destNodesIn_2.flit[0].bits.flow.ingress_node
connect monitor_2.io.in.flit[0].bits.flow.vnet_id, destNodesIn_2.flit[0].bits.flow.vnet_id
connect monitor_2.io.in.flit[0].bits.payload, destNodesIn_2.flit[0].bits.payload
connect monitor_2.io.in.flit[0].bits.tail, destNodesIn_2.flit[0].bits.tail
connect monitor_2.io.in.flit[0].bits.head, destNodesIn_2.flit[0].bits.head
connect monitor_2.io.in.flit[0].valid, destNodesIn_2.flit[0].valid
wire sourceNodesOut : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}
invalidate sourceNodesOut.vc_free
invalidate sourceNodesOut.credit_return
invalidate sourceNodesOut.flit[0].bits.virt_channel_id
invalidate sourceNodesOut.flit[0].bits.flow.egress_node_id
invalidate sourceNodesOut.flit[0].bits.flow.egress_node
invalidate sourceNodesOut.flit[0].bits.flow.ingress_node_id
invalidate sourceNodesOut.flit[0].bits.flow.ingress_node
invalidate sourceNodesOut.flit[0].bits.flow.vnet_id
invalidate sourceNodesOut.flit[0].bits.payload
invalidate sourceNodesOut.flit[0].bits.tail
invalidate sourceNodesOut.flit[0].bits.head
invalidate sourceNodesOut.flit[0].valid
wire sourceNodesOut_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}
invalidate sourceNodesOut_1.vc_free
invalidate sourceNodesOut_1.credit_return
invalidate sourceNodesOut_1.flit[0].bits.virt_channel_id
invalidate sourceNodesOut_1.flit[0].bits.flow.egress_node_id
invalidate sourceNodesOut_1.flit[0].bits.flow.egress_node
invalidate sourceNodesOut_1.flit[0].bits.flow.ingress_node_id
invalidate sourceNodesOut_1.flit[0].bits.flow.ingress_node
invalidate sourceNodesOut_1.flit[0].bits.flow.vnet_id
invalidate sourceNodesOut_1.flit[0].bits.payload
invalidate sourceNodesOut_1.flit[0].bits.tail
invalidate sourceNodesOut_1.flit[0].bits.head
invalidate sourceNodesOut_1.flit[0].valid
wire sourceNodesOut_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}
invalidate sourceNodesOut_2.vc_free
invalidate sourceNodesOut_2.credit_return
invalidate sourceNodesOut_2.flit[0].bits.virt_channel_id
invalidate sourceNodesOut_2.flit[0].bits.flow.egress_node_id
invalidate sourceNodesOut_2.flit[0].bits.flow.egress_node
invalidate sourceNodesOut_2.flit[0].bits.flow.ingress_node_id
invalidate sourceNodesOut_2.flit[0].bits.flow.ingress_node
invalidate sourceNodesOut_2.flit[0].bits.flow.vnet_id
invalidate sourceNodesOut_2.flit[0].bits.payload
invalidate sourceNodesOut_2.flit[0].bits.tail
invalidate sourceNodesOut_2.flit[0].bits.head
invalidate sourceNodesOut_2.flit[0].valid
wire ingressNodesIn : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, egress_id : UInt}}}
invalidate ingressNodesIn.flit.bits.egress_id
invalidate ingressNodesIn.flit.bits.payload
invalidate ingressNodesIn.flit.bits.tail
invalidate ingressNodesIn.flit.bits.head
invalidate ingressNodesIn.flit.valid
invalidate ingressNodesIn.flit.ready
wire ingressNodesIn_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, egress_id : UInt}}}
invalidate ingressNodesIn_1.flit.bits.egress_id
invalidate ingressNodesIn_1.flit.bits.payload
invalidate ingressNodesIn_1.flit.bits.tail
invalidate ingressNodesIn_1.flit.bits.head
invalidate ingressNodesIn_1.flit.valid
invalidate ingressNodesIn_1.flit.ready
wire egressNodesOut : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, ingress_id : UInt}}}
invalidate egressNodesOut.flit.bits.ingress_id
invalidate egressNodesOut.flit.bits.payload
invalidate egressNodesOut.flit.bits.tail
invalidate egressNodesOut.flit.bits.head
invalidate egressNodesOut.flit.valid
invalidate egressNodesOut.flit.ready
wire debugNodeOut : { va_stall : UInt[5], sa_stall : UInt[5]}
invalidate debugNodeOut.sa_stall[0]
invalidate debugNodeOut.sa_stall[1]
invalidate debugNodeOut.sa_stall[2]
invalidate debugNodeOut.sa_stall[3]
invalidate debugNodeOut.sa_stall[4]
invalidate debugNodeOut.va_stall[0]
invalidate debugNodeOut.va_stall[1]
invalidate debugNodeOut.va_stall[2]
invalidate debugNodeOut.va_stall[3]
invalidate debugNodeOut.va_stall[4]
connect destNodesIn, auto.dest_nodes_in_0
connect destNodesIn_1, auto.dest_nodes_in_1
connect destNodesIn_2, auto.dest_nodes_in_2
connect auto.source_nodes_out_0, sourceNodesOut
connect auto.source_nodes_out_1, sourceNodesOut_1
connect auto.source_nodes_out_2, sourceNodesOut_2
connect ingressNodesIn, auto.ingress_nodes_in_0
connect ingressNodesIn_1, auto.ingress_nodes_in_1
connect auto.egress_nodes_out, egressNodesOut
connect auto.debug_out, debugNodeOut
inst input_unit_0_from_0 of InputUnit_2
connect input_unit_0_from_0.clock, clock
connect input_unit_0_from_0.reset, reset
inst input_unit_1_from_2 of InputUnit_3
connect input_unit_1_from_2.clock, clock
connect input_unit_1_from_2.reset, reset
inst input_unit_2_from_5 of InputUnit_4
connect input_unit_2_from_5.clock, clock
connect input_unit_2_from_5.reset, reset
inst ingress_unit_3_from_4 of IngressUnit_5
connect ingress_unit_3_from_4.clock, clock
connect ingress_unit_3_from_4.reset, reset
inst ingress_unit_4_from_5 of IngressUnit_6
connect ingress_unit_4_from_5.clock, clock
connect ingress_unit_4_from_5.reset, reset
inst output_unit_0_to_0 of OutputUnit_2
connect output_unit_0_to_0.clock, clock
connect output_unit_0_to_0.reset, reset
inst output_unit_1_to_2 of OutputUnit_3
connect output_unit_1_to_2.clock, clock
connect output_unit_1_to_2.reset, reset
inst output_unit_2_to_5 of OutputUnit_4
connect output_unit_2_to_5.clock, clock
connect output_unit_2_to_5.reset, reset
inst egress_unit_3_to_2 of EgressUnit_4
connect egress_unit_3_to_2.clock, clock
connect egress_unit_3_to_2.reset, reset
inst switch of Switch_1
connect switch.clock, clock
connect switch.reset, reset
inst switch_allocator of SwitchAllocator_1
connect switch_allocator.clock, clock
connect switch_allocator.reset, reset
inst vc_allocator of RotatingSingleVCAllocator_1
connect vc_allocator.clock, clock
connect vc_allocator.reset, reset
inst route_computer of RouteComputer_1
connect route_computer.clock, clock
connect route_computer.reset, reset
node _fires_count_T = and(vc_allocator.io.req.`0`.ready, vc_allocator.io.req.`0`.valid)
node _fires_count_T_1 = and(vc_allocator.io.req.`1`.ready, vc_allocator.io.req.`1`.valid)
node _fires_count_T_2 = and(vc_allocator.io.req.`2`.ready, vc_allocator.io.req.`2`.valid)
node _fires_count_T_3 = and(vc_allocator.io.req.`3`.ready, vc_allocator.io.req.`3`.valid)
node _fires_count_T_4 = and(vc_allocator.io.req.`4`.ready, vc_allocator.io.req.`4`.valid)
node _fires_count_T_5 = add(_fires_count_T, _fires_count_T_1)
node _fires_count_T_6 = bits(_fires_count_T_5, 1, 0)
node _fires_count_T_7 = add(_fires_count_T_3, _fires_count_T_4)
node _fires_count_T_8 = bits(_fires_count_T_7, 1, 0)
node _fires_count_T_9 = add(_fires_count_T_2, _fires_count_T_8)
node _fires_count_T_10 = bits(_fires_count_T_9, 1, 0)
node _fires_count_T_11 = add(_fires_count_T_6, _fires_count_T_10)
node _fires_count_T_12 = bits(_fires_count_T_11, 2, 0)
wire fires_count : UInt
connect fires_count, _fires_count_T_12
connect input_unit_0_from_0.io.in, destNodesIn
connect input_unit_1_from_2.io.in, destNodesIn_1
connect input_unit_2_from_5.io.in, destNodesIn_2
connect ingress_unit_3_from_4.io.in, ingressNodesIn.flit
connect ingress_unit_4_from_5.io.in, ingressNodesIn_1.flit
connect output_unit_0_to_0.io.out.vc_free, sourceNodesOut.vc_free
connect output_unit_0_to_0.io.out.credit_return, sourceNodesOut.credit_return
connect sourceNodesOut.flit, output_unit_0_to_0.io.out.flit
connect output_unit_1_to_2.io.out.vc_free, sourceNodesOut_1.vc_free
connect output_unit_1_to_2.io.out.credit_return, sourceNodesOut_1.credit_return
connect sourceNodesOut_1.flit, output_unit_1_to_2.io.out.flit
connect output_unit_2_to_5.io.out.vc_free, sourceNodesOut_2.vc_free
connect output_unit_2_to_5.io.out.credit_return, sourceNodesOut_2.credit_return
connect sourceNodesOut_2.flit, output_unit_2_to_5.io.out.flit
connect egressNodesOut.flit.bits, egress_unit_3_to_2.io.out.bits
connect egressNodesOut.flit.valid, egress_unit_3_to_2.io.out.valid
connect egress_unit_3_to_2.io.out.ready, egressNodesOut.flit.ready
connect route_computer.io.req.`0`, input_unit_0_from_0.io.router_req
connect route_computer.io.req.`1`, input_unit_1_from_2.io.router_req
connect route_computer.io.req.`2`, input_unit_2_from_5.io.router_req
connect route_computer.io.req.`3`, ingress_unit_3_from_4.io.router_req
connect route_computer.io.req.`4`, ingress_unit_4_from_5.io.router_req
connect input_unit_0_from_0.io.router_resp, route_computer.io.resp.`0`
connect input_unit_1_from_2.io.router_resp, route_computer.io.resp.`1`
connect input_unit_2_from_5.io.router_resp, route_computer.io.resp.`2`
connect ingress_unit_3_from_4.io.router_resp, route_computer.io.resp.`3`
connect ingress_unit_4_from_5.io.router_resp, route_computer.io.resp.`4`
connect vc_allocator.io.req.`0`, input_unit_0_from_0.io.vcalloc_req
connect vc_allocator.io.req.`1`, input_unit_1_from_2.io.vcalloc_req
connect vc_allocator.io.req.`2`, input_unit_2_from_5.io.vcalloc_req
connect vc_allocator.io.req.`3`, ingress_unit_3_from_4.io.vcalloc_req
connect vc_allocator.io.req.`4`, ingress_unit_4_from_5.io.vcalloc_req
connect input_unit_0_from_0.io.vcalloc_resp, vc_allocator.io.resp.`0`
connect input_unit_1_from_2.io.vcalloc_resp, vc_allocator.io.resp.`1`
connect input_unit_2_from_5.io.vcalloc_resp, vc_allocator.io.resp.`2`
connect ingress_unit_3_from_4.io.vcalloc_resp, vc_allocator.io.resp.`3`
connect ingress_unit_4_from_5.io.vcalloc_resp, vc_allocator.io.resp.`4`
connect output_unit_0_to_0.io.allocs, vc_allocator.io.out_allocs.`0`
connect output_unit_1_to_2.io.allocs, vc_allocator.io.out_allocs.`1`
connect output_unit_2_to_5.io.allocs, vc_allocator.io.out_allocs.`2`
connect egress_unit_3_to_2.io.allocs, vc_allocator.io.out_allocs.`3`
connect vc_allocator.io.channel_status.`0`[0].flow.egress_node_id, output_unit_0_to_0.io.channel_status[0].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[0].flow.egress_node, output_unit_0_to_0.io.channel_status[0].flow.egress_node
connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node_id, output_unit_0_to_0.io.channel_status[0].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node, output_unit_0_to_0.io.channel_status[0].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[0].flow.vnet_id, output_unit_0_to_0.io.channel_status[0].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[0].occupied, output_unit_0_to_0.io.channel_status[0].occupied
connect vc_allocator.io.channel_status.`0`[1].flow.egress_node_id, output_unit_0_to_0.io.channel_status[1].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[1].flow.egress_node, output_unit_0_to_0.io.channel_status[1].flow.egress_node
connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node_id, output_unit_0_to_0.io.channel_status[1].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node, output_unit_0_to_0.io.channel_status[1].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[1].flow.vnet_id, output_unit_0_to_0.io.channel_status[1].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[1].occupied, output_unit_0_to_0.io.channel_status[1].occupied
connect vc_allocator.io.channel_status.`0`[2].flow.egress_node_id, output_unit_0_to_0.io.channel_status[2].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[2].flow.egress_node, output_unit_0_to_0.io.channel_status[2].flow.egress_node
connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node_id, output_unit_0_to_0.io.channel_status[2].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node, output_unit_0_to_0.io.channel_status[2].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[2].flow.vnet_id, output_unit_0_to_0.io.channel_status[2].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[2].occupied, output_unit_0_to_0.io.channel_status[2].occupied
connect vc_allocator.io.channel_status.`1`[0].flow.egress_node_id, output_unit_1_to_2.io.channel_status[0].flow.egress_node_id
connect vc_allocator.io.channel_status.`1`[0].flow.egress_node, output_unit_1_to_2.io.channel_status[0].flow.egress_node
connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node_id, output_unit_1_to_2.io.channel_status[0].flow.ingress_node_id
connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node, output_unit_1_to_2.io.channel_status[0].flow.ingress_node
connect vc_allocator.io.channel_status.`1`[0].flow.vnet_id, output_unit_1_to_2.io.channel_status[0].flow.vnet_id
connect vc_allocator.io.channel_status.`1`[0].occupied, output_unit_1_to_2.io.channel_status[0].occupied
connect vc_allocator.io.channel_status.`1`[1].flow.egress_node_id, output_unit_1_to_2.io.channel_status[1].flow.egress_node_id
connect vc_allocator.io.channel_status.`1`[1].flow.egress_node, output_unit_1_to_2.io.channel_status[1].flow.egress_node
connect vc_allocator.io.channel_status.`1`[1].flow.ingress_node_id, output_unit_1_to_2.io.channel_status[1].flow.ingress_node_id
connect vc_allocator.io.channel_status.`1`[1].flow.ingress_node, output_unit_1_to_2.io.channel_status[1].flow.ingress_node
connect vc_allocator.io.channel_status.`1`[1].flow.vnet_id, output_unit_1_to_2.io.channel_status[1].flow.vnet_id
connect vc_allocator.io.channel_status.`1`[1].occupied, output_unit_1_to_2.io.channel_status[1].occupied
connect vc_allocator.io.channel_status.`1`[2].flow.egress_node_id, output_unit_1_to_2.io.channel_status[2].flow.egress_node_id
connect vc_allocator.io.channel_status.`1`[2].flow.egress_node, output_unit_1_to_2.io.channel_status[2].flow.egress_node
connect vc_allocator.io.channel_status.`1`[2].flow.ingress_node_id, output_unit_1_to_2.io.channel_status[2].flow.ingress_node_id
connect vc_allocator.io.channel_status.`1`[2].flow.ingress_node, output_unit_1_to_2.io.channel_status[2].flow.ingress_node
connect vc_allocator.io.channel_status.`1`[2].flow.vnet_id, output_unit_1_to_2.io.channel_status[2].flow.vnet_id
connect vc_allocator.io.channel_status.`1`[2].occupied, output_unit_1_to_2.io.channel_status[2].occupied
connect vc_allocator.io.channel_status.`2`[0].flow.egress_node_id, output_unit_2_to_5.io.channel_status[0].flow.egress_node_id
connect vc_allocator.io.channel_status.`2`[0].flow.egress_node, output_unit_2_to_5.io.channel_status[0].flow.egress_node
connect vc_allocator.io.channel_status.`2`[0].flow.ingress_node_id, output_unit_2_to_5.io.channel_status[0].flow.ingress_node_id
connect vc_allocator.io.channel_status.`2`[0].flow.ingress_node, output_unit_2_to_5.io.channel_status[0].flow.ingress_node
connect vc_allocator.io.channel_status.`2`[0].flow.vnet_id, output_unit_2_to_5.io.channel_status[0].flow.vnet_id
connect vc_allocator.io.channel_status.`2`[0].occupied, output_unit_2_to_5.io.channel_status[0].occupied
connect vc_allocator.io.channel_status.`2`[1].flow.egress_node_id, output_unit_2_to_5.io.channel_status[1].flow.egress_node_id
connect vc_allocator.io.channel_status.`2`[1].flow.egress_node, output_unit_2_to_5.io.channel_status[1].flow.egress_node
connect vc_allocator.io.channel_status.`2`[1].flow.ingress_node_id, output_unit_2_to_5.io.channel_status[1].flow.ingress_node_id
connect vc_allocator.io.channel_status.`2`[1].flow.ingress_node, output_unit_2_to_5.io.channel_status[1].flow.ingress_node
connect vc_allocator.io.channel_status.`2`[1].flow.vnet_id, output_unit_2_to_5.io.channel_status[1].flow.vnet_id
connect vc_allocator.io.channel_status.`2`[1].occupied, output_unit_2_to_5.io.channel_status[1].occupied
connect vc_allocator.io.channel_status.`2`[2].flow.egress_node_id, output_unit_2_to_5.io.channel_status[2].flow.egress_node_id
connect vc_allocator.io.channel_status.`2`[2].flow.egress_node, output_unit_2_to_5.io.channel_status[2].flow.egress_node
connect vc_allocator.io.channel_status.`2`[2].flow.ingress_node_id, output_unit_2_to_5.io.channel_status[2].flow.ingress_node_id
connect vc_allocator.io.channel_status.`2`[2].flow.ingress_node, output_unit_2_to_5.io.channel_status[2].flow.ingress_node
connect vc_allocator.io.channel_status.`2`[2].flow.vnet_id, output_unit_2_to_5.io.channel_status[2].flow.vnet_id
connect vc_allocator.io.channel_status.`2`[2].occupied, output_unit_2_to_5.io.channel_status[2].occupied
connect vc_allocator.io.channel_status.`3`[0].flow.egress_node_id, egress_unit_3_to_2.io.channel_status[0].flow.egress_node_id
connect vc_allocator.io.channel_status.`3`[0].flow.egress_node, egress_unit_3_to_2.io.channel_status[0].flow.egress_node
connect vc_allocator.io.channel_status.`3`[0].flow.ingress_node_id, egress_unit_3_to_2.io.channel_status[0].flow.ingress_node_id
connect vc_allocator.io.channel_status.`3`[0].flow.ingress_node, egress_unit_3_to_2.io.channel_status[0].flow.ingress_node
connect vc_allocator.io.channel_status.`3`[0].flow.vnet_id, egress_unit_3_to_2.io.channel_status[0].flow.vnet_id
connect vc_allocator.io.channel_status.`3`[0].occupied, egress_unit_3_to_2.io.channel_status[0].occupied
connect input_unit_0_from_0.io.out_credit_available.`0`[0], output_unit_0_to_0.io.credit_available[0]
connect input_unit_0_from_0.io.out_credit_available.`0`[1], output_unit_0_to_0.io.credit_available[1]
connect input_unit_0_from_0.io.out_credit_available.`0`[2], output_unit_0_to_0.io.credit_available[2]
connect input_unit_0_from_0.io.out_credit_available.`1`[0], output_unit_1_to_2.io.credit_available[0]
connect input_unit_0_from_0.io.out_credit_available.`1`[1], output_unit_1_to_2.io.credit_available[1]
connect input_unit_0_from_0.io.out_credit_available.`1`[2], output_unit_1_to_2.io.credit_available[2]
connect input_unit_0_from_0.io.out_credit_available.`2`[0], output_unit_2_to_5.io.credit_available[0]
connect input_unit_0_from_0.io.out_credit_available.`2`[1], output_unit_2_to_5.io.credit_available[1]
connect input_unit_0_from_0.io.out_credit_available.`2`[2], output_unit_2_to_5.io.credit_available[2]
connect input_unit_0_from_0.io.out_credit_available.`3`[0], egress_unit_3_to_2.io.credit_available[0]
connect input_unit_1_from_2.io.out_credit_available.`0`[0], output_unit_0_to_0.io.credit_available[0]
connect input_unit_1_from_2.io.out_credit_available.`0`[1], output_unit_0_to_0.io.credit_available[1]
connect input_unit_1_from_2.io.out_credit_available.`0`[2], output_unit_0_to_0.io.credit_available[2]
connect input_unit_1_from_2.io.out_credit_available.`1`[0], output_unit_1_to_2.io.credit_available[0]
connect input_unit_1_from_2.io.out_credit_available.`1`[1], output_unit_1_to_2.io.credit_available[1]
connect input_unit_1_from_2.io.out_credit_available.`1`[2], output_unit_1_to_2.io.credit_available[2]
connect input_unit_1_from_2.io.out_credit_available.`2`[0], output_unit_2_to_5.io.credit_available[0]
connect input_unit_1_from_2.io.out_credit_available.`2`[1], output_unit_2_to_5.io.credit_available[1]
connect input_unit_1_from_2.io.out_credit_available.`2`[2], output_unit_2_to_5.io.credit_available[2]
connect input_unit_1_from_2.io.out_credit_available.`3`[0], egress_unit_3_to_2.io.credit_available[0]
connect input_unit_2_from_5.io.out_credit_available.`0`[0], output_unit_0_to_0.io.credit_available[0]
connect input_unit_2_from_5.io.out_credit_available.`0`[1], output_unit_0_to_0.io.credit_available[1]
connect input_unit_2_from_5.io.out_credit_available.`0`[2], output_unit_0_to_0.io.credit_available[2]
connect input_unit_2_from_5.io.out_credit_available.`1`[0], output_unit_1_to_2.io.credit_available[0]
connect input_unit_2_from_5.io.out_credit_available.`1`[1], output_unit_1_to_2.io.credit_available[1]
connect input_unit_2_from_5.io.out_credit_available.`1`[2], output_unit_1_to_2.io.credit_available[2]
connect input_unit_2_from_5.io.out_credit_available.`2`[0], output_unit_2_to_5.io.credit_available[0]
connect input_unit_2_from_5.io.out_credit_available.`2`[1], output_unit_2_to_5.io.credit_available[1]
connect input_unit_2_from_5.io.out_credit_available.`2`[2], output_unit_2_to_5.io.credit_available[2]
connect input_unit_2_from_5.io.out_credit_available.`3`[0], egress_unit_3_to_2.io.credit_available[0]
connect ingress_unit_3_from_4.io.out_credit_available.`0`[0], output_unit_0_to_0.io.credit_available[0]
connect ingress_unit_3_from_4.io.out_credit_available.`0`[1], output_unit_0_to_0.io.credit_available[1]
connect ingress_unit_3_from_4.io.out_credit_available.`0`[2], output_unit_0_to_0.io.credit_available[2]
connect ingress_unit_3_from_4.io.out_credit_available.`1`[0], output_unit_1_to_2.io.credit_available[0]
connect ingress_unit_3_from_4.io.out_credit_available.`1`[1], output_unit_1_to_2.io.credit_available[1]
connect ingress_unit_3_from_4.io.out_credit_available.`1`[2], output_unit_1_to_2.io.credit_available[2]
connect ingress_unit_3_from_4.io.out_credit_available.`2`[0], output_unit_2_to_5.io.credit_available[0]
connect ingress_unit_3_from_4.io.out_credit_available.`2`[1], output_unit_2_to_5.io.credit_available[1]
connect ingress_unit_3_from_4.io.out_credit_available.`2`[2], output_unit_2_to_5.io.credit_available[2]
connect ingress_unit_3_from_4.io.out_credit_available.`3`[0], egress_unit_3_to_2.io.credit_available[0]
connect ingress_unit_4_from_5.io.out_credit_available.`0`[0], output_unit_0_to_0.io.credit_available[0]
connect ingress_unit_4_from_5.io.out_credit_available.`0`[1], output_unit_0_to_0.io.credit_available[1]
connect ingress_unit_4_from_5.io.out_credit_available.`0`[2], output_unit_0_to_0.io.credit_available[2]
connect ingress_unit_4_from_5.io.out_credit_available.`1`[0], output_unit_1_to_2.io.credit_available[0]
connect ingress_unit_4_from_5.io.out_credit_available.`1`[1], output_unit_1_to_2.io.credit_available[1]
connect ingress_unit_4_from_5.io.out_credit_available.`1`[2], output_unit_1_to_2.io.credit_available[2]
connect ingress_unit_4_from_5.io.out_credit_available.`2`[0], output_unit_2_to_5.io.credit_available[0]
connect ingress_unit_4_from_5.io.out_credit_available.`2`[1], output_unit_2_to_5.io.credit_available[1]
connect ingress_unit_4_from_5.io.out_credit_available.`2`[2], output_unit_2_to_5.io.credit_available[2]
connect ingress_unit_4_from_5.io.out_credit_available.`3`[0], egress_unit_3_to_2.io.credit_available[0]
connect switch_allocator.io.req.`0`[0], input_unit_0_from_0.io.salloc_req[0]
connect switch_allocator.io.req.`1`[0], input_unit_1_from_2.io.salloc_req[0]
connect switch_allocator.io.req.`2`[0], input_unit_2_from_5.io.salloc_req[0]
connect switch_allocator.io.req.`3`[0], ingress_unit_3_from_4.io.salloc_req[0]
connect switch_allocator.io.req.`4`[0], ingress_unit_4_from_5.io.salloc_req[0]
connect output_unit_0_to_0.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`0`[0].tail
connect output_unit_0_to_0.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`0`[0].alloc
connect output_unit_0_to_0.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`0`[1].tail
connect output_unit_0_to_0.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`0`[1].alloc
connect output_unit_0_to_0.io.credit_alloc[2].tail, switch_allocator.io.credit_alloc.`0`[2].tail
connect output_unit_0_to_0.io.credit_alloc[2].alloc, switch_allocator.io.credit_alloc.`0`[2].alloc
connect output_unit_1_to_2.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`1`[0].tail
connect output_unit_1_to_2.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`1`[0].alloc
connect output_unit_1_to_2.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`1`[1].tail
connect output_unit_1_to_2.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`1`[1].alloc
connect output_unit_1_to_2.io.credit_alloc[2].tail, switch_allocator.io.credit_alloc.`1`[2].tail
connect output_unit_1_to_2.io.credit_alloc[2].alloc, switch_allocator.io.credit_alloc.`1`[2].alloc
connect output_unit_2_to_5.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`2`[0].tail
connect output_unit_2_to_5.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`2`[0].alloc
connect output_unit_2_to_5.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`2`[1].tail
connect output_unit_2_to_5.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`2`[1].alloc
connect output_unit_2_to_5.io.credit_alloc[2].tail, switch_allocator.io.credit_alloc.`2`[2].tail
connect output_unit_2_to_5.io.credit_alloc[2].alloc, switch_allocator.io.credit_alloc.`2`[2].alloc
connect egress_unit_3_to_2.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`3`[0].tail
connect egress_unit_3_to_2.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`3`[0].alloc
connect switch.io.in.`0`[0], input_unit_0_from_0.io.out[0]
connect switch.io.in.`1`[0], input_unit_1_from_2.io.out[0]
connect switch.io.in.`2`[0], input_unit_2_from_5.io.out[0]
connect switch.io.in.`3`[0], ingress_unit_3_from_4.io.out[0]
connect switch.io.in.`4`[0], ingress_unit_4_from_5.io.out[0]
connect output_unit_0_to_0.io.in, switch.io.out.`0`
connect output_unit_1_to_2.io.in, switch.io.out.`1`
connect output_unit_2_to_5.io.in, switch.io.out.`2`
connect egress_unit_3_to_2.io.in, switch.io.out.`3`
connect switch.io.sel.`0`[0].`0`[0], switch_allocator.io.switch_sel.`0`[0].`0`[0]
connect switch.io.sel.`0`[0].`1`[0], switch_allocator.io.switch_sel.`0`[0].`1`[0]
connect switch.io.sel.`0`[0].`2`[0], switch_allocator.io.switch_sel.`0`[0].`2`[0]
connect switch.io.sel.`0`[0].`3`[0], switch_allocator.io.switch_sel.`0`[0].`3`[0]
connect switch.io.sel.`0`[0].`4`[0], switch_allocator.io.switch_sel.`0`[0].`4`[0]
connect switch.io.sel.`1`[0].`0`[0], switch_allocator.io.switch_sel.`1`[0].`0`[0]
connect switch.io.sel.`1`[0].`1`[0], switch_allocator.io.switch_sel.`1`[0].`1`[0]
connect switch.io.sel.`1`[0].`2`[0], switch_allocator.io.switch_sel.`1`[0].`2`[0]
connect switch.io.sel.`1`[0].`3`[0], switch_allocator.io.switch_sel.`1`[0].`3`[0]
connect switch.io.sel.`1`[0].`4`[0], switch_allocator.io.switch_sel.`1`[0].`4`[0]
connect switch.io.sel.`2`[0].`0`[0], switch_allocator.io.switch_sel.`2`[0].`0`[0]
connect switch.io.sel.`2`[0].`1`[0], switch_allocator.io.switch_sel.`2`[0].`1`[0]
connect switch.io.sel.`2`[0].`2`[0], switch_allocator.io.switch_sel.`2`[0].`2`[0]
connect switch.io.sel.`2`[0].`3`[0], switch_allocator.io.switch_sel.`2`[0].`3`[0]
connect switch.io.sel.`2`[0].`4`[0], switch_allocator.io.switch_sel.`2`[0].`4`[0]
connect switch.io.sel.`3`[0].`0`[0], switch_allocator.io.switch_sel.`3`[0].`0`[0]
connect switch.io.sel.`3`[0].`1`[0], switch_allocator.io.switch_sel.`3`[0].`1`[0]
connect switch.io.sel.`3`[0].`2`[0], switch_allocator.io.switch_sel.`3`[0].`2`[0]
connect switch.io.sel.`3`[0].`3`[0], switch_allocator.io.switch_sel.`3`[0].`3`[0]
connect switch.io.sel.`3`[0].`4`[0], switch_allocator.io.switch_sel.`3`[0].`4`[0]
connect input_unit_0_from_0.io.block, UInt<1>(0h0)
connect input_unit_1_from_2.io.block, UInt<1>(0h0)
connect input_unit_2_from_5.io.block, UInt<1>(0h0)
connect ingress_unit_3_from_4.io.block, UInt<1>(0h0)
connect ingress_unit_4_from_5.io.block, UInt<1>(0h0)
connect debugNodeOut.va_stall[0], input_unit_0_from_0.io.debug.va_stall
connect debugNodeOut.va_stall[1], input_unit_1_from_2.io.debug.va_stall
connect debugNodeOut.va_stall[2], input_unit_2_from_5.io.debug.va_stall
connect debugNodeOut.va_stall[3], ingress_unit_3_from_4.io.debug.va_stall
connect debugNodeOut.va_stall[4], ingress_unit_4_from_5.io.debug.va_stall
connect debugNodeOut.sa_stall[0], input_unit_0_from_0.io.debug.sa_stall
connect debugNodeOut.sa_stall[1], input_unit_1_from_2.io.debug.sa_stall
connect debugNodeOut.sa_stall[2], input_unit_2_from_5.io.debug.sa_stall
connect debugNodeOut.sa_stall[3], ingress_unit_3_from_4.io.debug.sa_stall
connect debugNodeOut.sa_stall[4], ingress_unit_4_from_5.io.debug.sa_stall
regreset debug_tsc : UInt<64>, clock, reset, UInt<64>(0h0)
node _debug_tsc_T = add(debug_tsc, UInt<1>(0h1))
node _debug_tsc_T_1 = tail(_debug_tsc_T, 1)
connect debug_tsc, _debug_tsc_T_1
regreset debug_sample : UInt<64>, clock, reset, UInt<64>(0h0)
node _debug_sample_T = add(debug_sample, UInt<1>(0h1))
node _debug_sample_T_1 = tail(_debug_sample_T, 1)
connect debug_sample, _debug_sample_T_1
inst plusarg_reader of plusarg_reader_27
node _T = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_1 = tail(_T, 1)
node _T_2 = eq(debug_sample, _T_1)
when _T_2 :
connect debug_sample, UInt<1>(0h0)
regreset util_ctr : UInt<64>, clock, reset, UInt<64>(0h0)
regreset fired : UInt<1>, clock, reset, UInt<1>(0h0)
node _util_ctr_T = add(util_ctr, destNodesIn.flit[0].valid)
node _util_ctr_T_1 = tail(_util_ctr_T, 1)
connect util_ctr, _util_ctr_T_1
node _fired_T = or(fired, destNodesIn.flit[0].valid)
connect fired, _fired_T
node _T_3 = neq(plusarg_reader.out, UInt<1>(0h0))
node _T_4 = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_5 = tail(_T_4, 1)
node _T_6 = eq(debug_sample, _T_5)
node _T_7 = and(_T_3, _T_6)
node _T_8 = and(_T_7, fired)
when _T_8 :
node _T_9 = asUInt(reset)
node _T_10 = eq(_T_9, UInt<1>(0h0))
when _T_10 :
printf(clock, UInt<1>(0h1), "nocsample %d 0 1 %d\n", debug_tsc, util_ctr) : printf
connect fired, destNodesIn.flit[0].valid
regreset util_ctr_1 : UInt<64>, clock, reset, UInt<64>(0h0)
regreset fired_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _util_ctr_T_2 = add(util_ctr_1, destNodesIn_1.flit[0].valid)
node _util_ctr_T_3 = tail(_util_ctr_T_2, 1)
connect util_ctr_1, _util_ctr_T_3
node _fired_T_1 = or(fired_1, destNodesIn_1.flit[0].valid)
connect fired_1, _fired_T_1
node _T_11 = neq(plusarg_reader.out, UInt<1>(0h0))
node _T_12 = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_13 = tail(_T_12, 1)
node _T_14 = eq(debug_sample, _T_13)
node _T_15 = and(_T_11, _T_14)
node _T_16 = and(_T_15, fired_1)
when _T_16 :
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
printf(clock, UInt<1>(0h1), "nocsample %d 2 1 %d\n", debug_tsc, util_ctr_1) : printf_1
connect fired_1, destNodesIn_1.flit[0].valid
regreset util_ctr_2 : UInt<64>, clock, reset, UInt<64>(0h0)
regreset fired_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _util_ctr_T_4 = add(util_ctr_2, destNodesIn_2.flit[0].valid)
node _util_ctr_T_5 = tail(_util_ctr_T_4, 1)
connect util_ctr_2, _util_ctr_T_5
node _fired_T_2 = or(fired_2, destNodesIn_2.flit[0].valid)
connect fired_2, _fired_T_2
node _T_19 = neq(plusarg_reader.out, UInt<1>(0h0))
node _T_20 = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_21 = tail(_T_20, 1)
node _T_22 = eq(debug_sample, _T_21)
node _T_23 = and(_T_19, _T_22)
node _T_24 = and(_T_23, fired_2)
when _T_24 :
node _T_25 = asUInt(reset)
node _T_26 = eq(_T_25, UInt<1>(0h0))
when _T_26 :
printf(clock, UInt<1>(0h1), "nocsample %d 5 1 %d\n", debug_tsc, util_ctr_2) : printf_2
connect fired_2, destNodesIn_2.flit[0].valid
node _T_27 = and(ingressNodesIn.flit.ready, ingressNodesIn.flit.valid)
regreset util_ctr_3 : UInt<64>, clock, reset, UInt<64>(0h0)
regreset fired_3 : UInt<1>, clock, reset, UInt<1>(0h0)
node _util_ctr_T_6 = add(util_ctr_3, _T_27)
node _util_ctr_T_7 = tail(_util_ctr_T_6, 1)
connect util_ctr_3, _util_ctr_T_7
node _fired_T_3 = or(fired_3, _T_27)
connect fired_3, _fired_T_3
node _T_28 = neq(plusarg_reader.out, UInt<1>(0h0))
node _T_29 = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_30 = tail(_T_29, 1)
node _T_31 = eq(debug_sample, _T_30)
node _T_32 = and(_T_28, _T_31)
node _T_33 = and(_T_32, fired_3)
when _T_33 :
node _T_34 = asUInt(reset)
node _T_35 = eq(_T_34, UInt<1>(0h0))
when _T_35 :
printf(clock, UInt<1>(0h1), "nocsample %d i4 1 %d\n", debug_tsc, util_ctr_3) : printf_3
connect fired_3, _T_27
node _T_36 = and(ingressNodesIn_1.flit.ready, ingressNodesIn_1.flit.valid)
regreset util_ctr_4 : UInt<64>, clock, reset, UInt<64>(0h0)
regreset fired_4 : UInt<1>, clock, reset, UInt<1>(0h0)
node _util_ctr_T_8 = add(util_ctr_4, _T_36)
node _util_ctr_T_9 = tail(_util_ctr_T_8, 1)
connect util_ctr_4, _util_ctr_T_9
node _fired_T_4 = or(fired_4, _T_36)
connect fired_4, _fired_T_4
node _T_37 = neq(plusarg_reader.out, UInt<1>(0h0))
node _T_38 = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_39 = tail(_T_38, 1)
node _T_40 = eq(debug_sample, _T_39)
node _T_41 = and(_T_37, _T_40)
node _T_42 = and(_T_41, fired_4)
when _T_42 :
node _T_43 = asUInt(reset)
node _T_44 = eq(_T_43, UInt<1>(0h0))
when _T_44 :
printf(clock, UInt<1>(0h1), "nocsample %d i5 1 %d\n", debug_tsc, util_ctr_4) : printf_4
connect fired_4, _T_36
node _T_45 = and(egressNodesOut.flit.ready, egressNodesOut.flit.valid)
regreset util_ctr_5 : UInt<64>, clock, reset, UInt<64>(0h0)
regreset fired_5 : UInt<1>, clock, reset, UInt<1>(0h0)
node _util_ctr_T_10 = add(util_ctr_5, _T_45)
node _util_ctr_T_11 = tail(_util_ctr_T_10, 1)
connect util_ctr_5, _util_ctr_T_11
node _fired_T_5 = or(fired_5, _T_45)
connect fired_5, _fired_T_5
node _T_46 = neq(plusarg_reader.out, UInt<1>(0h0))
node _T_47 = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_48 = tail(_T_47, 1)
node _T_49 = eq(debug_sample, _T_48)
node _T_50 = and(_T_46, _T_49)
node _T_51 = and(_T_50, fired_5)
when _T_51 :
node _T_52 = asUInt(reset)
node _T_53 = eq(_T_52, UInt<1>(0h0))
when _T_53 :
printf(clock, UInt<1>(0h1), "nocsample %d 1 e2 %d\n", debug_tsc, util_ctr_5) : printf_5
connect fired_5, _T_45 | module Router_1( // @[Router.scala:89:25]
input clock, // @[Router.scala:89:25]
input reset, // @[Router.scala:89:25]
output [1:0] auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_debug_out_va_stall_3, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_debug_out_va_stall_4, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_debug_out_sa_stall_3, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_debug_out_sa_stall_4, // @[LazyModuleImp.scala:107:25]
input auto_egress_nodes_out_flit_ready, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
output [144:0] auto_egress_nodes_out_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
output auto_ingress_nodes_in_1_flit_ready, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_1_flit_valid, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_1_flit_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
input [144:0] auto_ingress_nodes_in_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_ingress_nodes_in_1_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25]
output auto_ingress_nodes_in_0_flit_ready, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_0_flit_valid, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_0_flit_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
input [144:0] auto_ingress_nodes_in_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_ingress_nodes_in_0_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_2_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [144:0] auto_source_nodes_out_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_source_nodes_out_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_source_nodes_out_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_source_nodes_out_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_source_nodes_out_2_credit_return, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_source_nodes_out_2_vc_free, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_1_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [144:0] auto_source_nodes_out_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_source_nodes_out_1_credit_return, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_source_nodes_out_1_vc_free, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_0_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [144:0] auto_source_nodes_out_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_source_nodes_out_0_credit_return, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_source_nodes_out_0_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_2_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [144:0] auto_dest_nodes_in_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_dest_nodes_in_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_dest_nodes_in_2_credit_return, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_dest_nodes_in_2_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_1_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [144:0] auto_dest_nodes_in_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_dest_nodes_in_1_credit_return, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_dest_nodes_in_1_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_0_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [144:0] auto_dest_nodes_in_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_dest_nodes_in_0_credit_return, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_dest_nodes_in_0_vc_free // @[LazyModuleImp.scala:107:25]
);
wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire _route_computer_io_resp_4_vc_sel_2_0; // @[Router.scala:136:32]
wire _route_computer_io_resp_4_vc_sel_2_1; // @[Router.scala:136:32]
wire _route_computer_io_resp_4_vc_sel_2_2; // @[Router.scala:136:32]
wire _route_computer_io_resp_4_vc_sel_1_0; // @[Router.scala:136:32]
wire _route_computer_io_resp_4_vc_sel_1_1; // @[Router.scala:136:32]
wire _route_computer_io_resp_4_vc_sel_1_2; // @[Router.scala:136:32]
wire _route_computer_io_resp_4_vc_sel_0_0; // @[Router.scala:136:32]
wire _route_computer_io_resp_4_vc_sel_0_1; // @[Router.scala:136:32]
wire _route_computer_io_resp_4_vc_sel_0_2; // @[Router.scala:136:32]
wire _route_computer_io_resp_3_vc_sel_2_0; // @[Router.scala:136:32]
wire _route_computer_io_resp_3_vc_sel_2_1; // @[Router.scala:136:32]
wire _route_computer_io_resp_3_vc_sel_2_2; // @[Router.scala:136:32]
wire _route_computer_io_resp_3_vc_sel_1_0; // @[Router.scala:136:32]
wire _route_computer_io_resp_3_vc_sel_1_1; // @[Router.scala:136:32]
wire _route_computer_io_resp_3_vc_sel_1_2; // @[Router.scala:136:32]
wire _route_computer_io_resp_3_vc_sel_0_0; // @[Router.scala:136:32]
wire _route_computer_io_resp_3_vc_sel_0_1; // @[Router.scala:136:32]
wire _route_computer_io_resp_3_vc_sel_0_2; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_2_0; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_2_1; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_2_2; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_1_0; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_1_1; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_1_2; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_0_0; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_0_1; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_0_2; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_2_0; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_2_1; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_2_2; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_1_0; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_1_1; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_1_2; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_0_0; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_0_1; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_0_2; // @[Router.scala:136:32]
wire _vc_allocator_io_req_4_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_req_3_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_req_2_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_req_1_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_4_vc_sel_3_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_4_vc_sel_2_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_4_vc_sel_2_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_4_vc_sel_2_2; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_4_vc_sel_1_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_4_vc_sel_1_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_4_vc_sel_1_2; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_4_vc_sel_0_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_4_vc_sel_0_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_4_vc_sel_0_2; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_3_vc_sel_3_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_3_vc_sel_2_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_3_vc_sel_2_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_3_vc_sel_2_2; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_3_vc_sel_1_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_3_vc_sel_1_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_3_vc_sel_1_2; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_3_vc_sel_0_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_3_vc_sel_0_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_3_vc_sel_0_2; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_3_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_3_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_2_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_2_2; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_2; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_3_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_2_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_2_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_2_2; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_1_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_1_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_1_2; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_3_0_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_2_0_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_2_1_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_2_2_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_1_0_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_1_1_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_1_2_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_2_alloc; // @[Router.scala:133:30]
wire _switch_allocator_io_req_4_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_req_3_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_req_2_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_req_1_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_3_0_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_3_0_tail; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_2_0_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_2_1_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_2_2_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_1_0_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_1_1_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_1_2_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_2_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_3_0_4_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_3_0_3_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_3_0_2_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_3_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_3_0_0_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_2_0_4_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_2_0_3_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_2_0_2_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_2_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_2_0_0_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_4_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_3_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_2_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_0_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_4_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_3_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_2_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_0_0; // @[Router.scala:132:34]
wire _switch_io_out_3_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_3_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_3_0_bits_tail; // @[Router.scala:131:24]
wire [144:0] _switch_io_out_3_0_bits_payload; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_3_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_3_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire _switch_io_out_2_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_2_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_2_0_bits_tail; // @[Router.scala:131:24]
wire [144:0] _switch_io_out_2_0_bits_payload; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_2_0_bits_flow_vnet_id; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_2_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_2_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_2_0_bits_flow_egress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_2_0_bits_flow_egress_node_id; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_2_0_bits_virt_channel_id; // @[Router.scala:131:24]
wire _switch_io_out_1_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24]
wire [144:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_1_0_bits_flow_vnet_id; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_1_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_1_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_1_0_bits_flow_egress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_1_0_bits_flow_egress_node_id; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_1_0_bits_virt_channel_id; // @[Router.scala:131:24]
wire _switch_io_out_0_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24]
wire [144:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24]
wire _egress_unit_3_to_2_io_credit_available_0; // @[Router.scala:125:13]
wire _egress_unit_3_to_2_io_channel_status_0_occupied; // @[Router.scala:125:13]
wire _egress_unit_3_to_2_io_out_valid; // @[Router.scala:125:13]
wire _output_unit_2_to_5_io_credit_available_0; // @[Router.scala:122:13]
wire _output_unit_2_to_5_io_credit_available_1; // @[Router.scala:122:13]
wire _output_unit_2_to_5_io_credit_available_2; // @[Router.scala:122:13]
wire _output_unit_2_to_5_io_channel_status_0_occupied; // @[Router.scala:122:13]
wire _output_unit_2_to_5_io_channel_status_1_occupied; // @[Router.scala:122:13]
wire _output_unit_2_to_5_io_channel_status_2_occupied; // @[Router.scala:122:13]
wire _output_unit_1_to_2_io_credit_available_0; // @[Router.scala:122:13]
wire _output_unit_1_to_2_io_credit_available_1; // @[Router.scala:122:13]
wire _output_unit_1_to_2_io_credit_available_2; // @[Router.scala:122:13]
wire _output_unit_1_to_2_io_channel_status_0_occupied; // @[Router.scala:122:13]
wire _output_unit_1_to_2_io_channel_status_1_occupied; // @[Router.scala:122:13]
wire _output_unit_1_to_2_io_channel_status_2_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_0_io_credit_available_2; // @[Router.scala:122:13]
wire _output_unit_0_to_0_io_channel_status_2_occupied; // @[Router.scala:122:13]
wire [3:0] _ingress_unit_4_from_5_io_router_req_bits_flow_egress_node; // @[Router.scala:116:13]
wire [1:0] _ingress_unit_4_from_5_io_router_req_bits_flow_egress_node_id; // @[Router.scala:116:13]
wire _ingress_unit_4_from_5_io_vcalloc_req_valid; // @[Router.scala:116:13]
wire _ingress_unit_4_from_5_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:116:13]
wire _ingress_unit_4_from_5_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:116:13]
wire _ingress_unit_4_from_5_io_vcalloc_req_bits_vc_sel_2_1; // @[Router.scala:116:13]
wire _ingress_unit_4_from_5_io_vcalloc_req_bits_vc_sel_2_2; // @[Router.scala:116:13]
wire _ingress_unit_4_from_5_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13]
wire _ingress_unit_4_from_5_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:116:13]
wire _ingress_unit_4_from_5_io_vcalloc_req_bits_vc_sel_1_2; // @[Router.scala:116:13]
wire _ingress_unit_4_from_5_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13]
wire _ingress_unit_4_from_5_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13]
wire _ingress_unit_4_from_5_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:116:13]
wire _ingress_unit_4_from_5_io_salloc_req_0_valid; // @[Router.scala:116:13]
wire _ingress_unit_4_from_5_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:116:13]
wire _ingress_unit_4_from_5_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:116:13]
wire _ingress_unit_4_from_5_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:116:13]
wire _ingress_unit_4_from_5_io_salloc_req_0_bits_vc_sel_2_2; // @[Router.scala:116:13]
wire _ingress_unit_4_from_5_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13]
wire _ingress_unit_4_from_5_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:116:13]
wire _ingress_unit_4_from_5_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:116:13]
wire _ingress_unit_4_from_5_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13]
wire _ingress_unit_4_from_5_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13]
wire _ingress_unit_4_from_5_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:116:13]
wire _ingress_unit_4_from_5_io_salloc_req_0_bits_tail; // @[Router.scala:116:13]
wire _ingress_unit_4_from_5_io_out_0_valid; // @[Router.scala:116:13]
wire _ingress_unit_4_from_5_io_out_0_bits_flit_head; // @[Router.scala:116:13]
wire _ingress_unit_4_from_5_io_out_0_bits_flit_tail; // @[Router.scala:116:13]
wire [144:0] _ingress_unit_4_from_5_io_out_0_bits_flit_payload; // @[Router.scala:116:13]
wire [1:0] _ingress_unit_4_from_5_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13]
wire [3:0] _ingress_unit_4_from_5_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13]
wire [2:0] _ingress_unit_4_from_5_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13]
wire [3:0] _ingress_unit_4_from_5_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13]
wire [1:0] _ingress_unit_4_from_5_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13]
wire [1:0] _ingress_unit_4_from_5_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13]
wire _ingress_unit_4_from_5_io_in_ready; // @[Router.scala:116:13]
wire [3:0] _ingress_unit_3_from_4_io_router_req_bits_flow_egress_node; // @[Router.scala:116:13]
wire [1:0] _ingress_unit_3_from_4_io_router_req_bits_flow_egress_node_id; // @[Router.scala:116:13]
wire _ingress_unit_3_from_4_io_vcalloc_req_valid; // @[Router.scala:116:13]
wire _ingress_unit_3_from_4_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:116:13]
wire _ingress_unit_3_from_4_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:116:13]
wire _ingress_unit_3_from_4_io_vcalloc_req_bits_vc_sel_2_1; // @[Router.scala:116:13]
wire _ingress_unit_3_from_4_io_vcalloc_req_bits_vc_sel_2_2; // @[Router.scala:116:13]
wire _ingress_unit_3_from_4_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13]
wire _ingress_unit_3_from_4_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:116:13]
wire _ingress_unit_3_from_4_io_vcalloc_req_bits_vc_sel_1_2; // @[Router.scala:116:13]
wire _ingress_unit_3_from_4_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13]
wire _ingress_unit_3_from_4_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13]
wire _ingress_unit_3_from_4_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:116:13]
wire _ingress_unit_3_from_4_io_salloc_req_0_valid; // @[Router.scala:116:13]
wire _ingress_unit_3_from_4_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:116:13]
wire _ingress_unit_3_from_4_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:116:13]
wire _ingress_unit_3_from_4_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:116:13]
wire _ingress_unit_3_from_4_io_salloc_req_0_bits_vc_sel_2_2; // @[Router.scala:116:13]
wire _ingress_unit_3_from_4_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13]
wire _ingress_unit_3_from_4_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:116:13]
wire _ingress_unit_3_from_4_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:116:13]
wire _ingress_unit_3_from_4_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13]
wire _ingress_unit_3_from_4_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13]
wire _ingress_unit_3_from_4_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:116:13]
wire _ingress_unit_3_from_4_io_salloc_req_0_bits_tail; // @[Router.scala:116:13]
wire _ingress_unit_3_from_4_io_out_0_valid; // @[Router.scala:116:13]
wire _ingress_unit_3_from_4_io_out_0_bits_flit_head; // @[Router.scala:116:13]
wire _ingress_unit_3_from_4_io_out_0_bits_flit_tail; // @[Router.scala:116:13]
wire [144:0] _ingress_unit_3_from_4_io_out_0_bits_flit_payload; // @[Router.scala:116:13]
wire [1:0] _ingress_unit_3_from_4_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13]
wire [3:0] _ingress_unit_3_from_4_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13]
wire [2:0] _ingress_unit_3_from_4_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13]
wire [3:0] _ingress_unit_3_from_4_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13]
wire [1:0] _ingress_unit_3_from_4_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13]
wire [1:0] _ingress_unit_3_from_4_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13]
wire _ingress_unit_3_from_4_io_in_ready; // @[Router.scala:116:13]
wire _input_unit_2_from_5_io_vcalloc_req_valid; // @[Router.scala:112:13]
wire _input_unit_2_from_5_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:112:13]
wire _input_unit_2_from_5_io_salloc_req_0_valid; // @[Router.scala:112:13]
wire _input_unit_2_from_5_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:112:13]
wire _input_unit_2_from_5_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13]
wire _input_unit_2_from_5_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:112:13]
wire _input_unit_2_from_5_io_salloc_req_0_bits_vc_sel_2_2; // @[Router.scala:112:13]
wire _input_unit_2_from_5_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13]
wire _input_unit_2_from_5_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13]
wire _input_unit_2_from_5_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:112:13]
wire _input_unit_2_from_5_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:112:13]
wire _input_unit_2_from_5_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13]
wire _input_unit_2_from_5_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13]
wire _input_unit_2_from_5_io_salloc_req_0_bits_tail; // @[Router.scala:112:13]
wire _input_unit_2_from_5_io_out_0_valid; // @[Router.scala:112:13]
wire _input_unit_2_from_5_io_out_0_bits_flit_head; // @[Router.scala:112:13]
wire _input_unit_2_from_5_io_out_0_bits_flit_tail; // @[Router.scala:112:13]
wire [144:0] _input_unit_2_from_5_io_out_0_bits_flit_payload; // @[Router.scala:112:13]
wire [1:0] _input_unit_2_from_5_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_2_from_5_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13]
wire [2:0] _input_unit_2_from_5_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_2_from_5_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_2_from_5_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13]
wire [1:0] _input_unit_1_from_2_io_router_req_bits_src_virt_id; // @[Router.scala:112:13]
wire [1:0] _input_unit_1_from_2_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_1_from_2_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13]
wire [2:0] _input_unit_1_from_2_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_1_from_2_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_1_from_2_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13]
wire _input_unit_1_from_2_io_vcalloc_req_valid; // @[Router.scala:112:13]
wire _input_unit_1_from_2_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:112:13]
wire _input_unit_1_from_2_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:112:13]
wire _input_unit_1_from_2_io_vcalloc_req_bits_vc_sel_2_1; // @[Router.scala:112:13]
wire _input_unit_1_from_2_io_vcalloc_req_bits_vc_sel_2_2; // @[Router.scala:112:13]
wire _input_unit_1_from_2_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:112:13]
wire _input_unit_1_from_2_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:112:13]
wire _input_unit_1_from_2_io_vcalloc_req_bits_vc_sel_1_2; // @[Router.scala:112:13]
wire _input_unit_1_from_2_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:112:13]
wire _input_unit_1_from_2_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:112:13]
wire _input_unit_1_from_2_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:112:13]
wire _input_unit_1_from_2_io_salloc_req_0_valid; // @[Router.scala:112:13]
wire _input_unit_1_from_2_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:112:13]
wire _input_unit_1_from_2_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13]
wire _input_unit_1_from_2_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:112:13]
wire _input_unit_1_from_2_io_salloc_req_0_bits_vc_sel_2_2; // @[Router.scala:112:13]
wire _input_unit_1_from_2_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13]
wire _input_unit_1_from_2_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13]
wire _input_unit_1_from_2_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:112:13]
wire _input_unit_1_from_2_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:112:13]
wire _input_unit_1_from_2_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13]
wire _input_unit_1_from_2_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13]
wire _input_unit_1_from_2_io_salloc_req_0_bits_tail; // @[Router.scala:112:13]
wire _input_unit_1_from_2_io_out_0_valid; // @[Router.scala:112:13]
wire _input_unit_1_from_2_io_out_0_bits_flit_head; // @[Router.scala:112:13]
wire _input_unit_1_from_2_io_out_0_bits_flit_tail; // @[Router.scala:112:13]
wire [144:0] _input_unit_1_from_2_io_out_0_bits_flit_payload; // @[Router.scala:112:13]
wire [1:0] _input_unit_1_from_2_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_1_from_2_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13]
wire [2:0] _input_unit_1_from_2_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_1_from_2_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_1_from_2_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13]
wire [1:0] _input_unit_1_from_2_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13]
wire [1:0] _input_unit_0_from_0_io_router_req_bits_src_virt_id; // @[Router.scala:112:13]
wire [1:0] _input_unit_0_from_0_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_0_from_0_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13]
wire [2:0] _input_unit_0_from_0_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_0_from_0_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_0_from_0_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13]
wire _input_unit_0_from_0_io_vcalloc_req_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_0_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:112:13]
wire _input_unit_0_from_0_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:112:13]
wire _input_unit_0_from_0_io_vcalloc_req_bits_vc_sel_2_1; // @[Router.scala:112:13]
wire _input_unit_0_from_0_io_vcalloc_req_bits_vc_sel_2_2; // @[Router.scala:112:13]
wire _input_unit_0_from_0_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:112:13]
wire _input_unit_0_from_0_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:112:13]
wire _input_unit_0_from_0_io_vcalloc_req_bits_vc_sel_1_2; // @[Router.scala:112:13]
wire _input_unit_0_from_0_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:112:13]
wire _input_unit_0_from_0_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:112:13]
wire _input_unit_0_from_0_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:112:13]
wire _input_unit_0_from_0_io_salloc_req_0_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_0_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:112:13]
wire _input_unit_0_from_0_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13]
wire _input_unit_0_from_0_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:112:13]
wire _input_unit_0_from_0_io_salloc_req_0_bits_vc_sel_2_2; // @[Router.scala:112:13]
wire _input_unit_0_from_0_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13]
wire _input_unit_0_from_0_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13]
wire _input_unit_0_from_0_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:112:13]
wire _input_unit_0_from_0_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:112:13]
wire _input_unit_0_from_0_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13]
wire _input_unit_0_from_0_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13]
wire _input_unit_0_from_0_io_salloc_req_0_bits_tail; // @[Router.scala:112:13]
wire _input_unit_0_from_0_io_out_0_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_0_io_out_0_bits_flit_head; // @[Router.scala:112:13]
wire _input_unit_0_from_0_io_out_0_bits_flit_tail; // @[Router.scala:112:13]
wire [144:0] _input_unit_0_from_0_io_out_0_bits_flit_payload; // @[Router.scala:112:13]
wire [1:0] _input_unit_0_from_0_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_0_from_0_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13]
wire [2:0] _input_unit_0_from_0_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_0_from_0_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_0_from_0_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13]
wire [1:0] _input_unit_0_from_0_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13]
wire [2:0] fires_count = {1'h0, {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_0_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_1_ready & _input_unit_1_from_2_io_vcalloc_req_valid}} + {1'h0, {1'h0, _vc_allocator_io_req_2_ready & _input_unit_2_from_5_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_3_ready & _ingress_unit_3_from_4_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_4_ready & _ingress_unit_4_from_5_io_vcalloc_req_valid}}; // @[Decoupled.scala:51:35]
reg [63:0] debug_tsc; // @[Router.scala:195:28]
reg [63:0] debug_sample; // @[Router.scala:197:31]
wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11]
reg [63:0] util_ctr; // @[Router.scala:203:29]
reg fired; // @[Router.scala:204:26]
wire _GEN_0 = (|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11]
wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_1; // @[Router.scala:203:29]
reg fired_1; // @[Router.scala:204:26]
wire _GEN_2 = _GEN_0 & fired_1; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_2; // @[Router.scala:203:29]
reg fired_2; // @[Router.scala:204:26]
wire _GEN_3 = _GEN_0 & fired_2; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_3; // @[Router.scala:203:29]
reg fired_3; // @[Router.scala:204:26]
wire _GEN_4 = _GEN_0 & fired_3; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_4; // @[Router.scala:203:29]
reg fired_4; // @[Router.scala:204:26]
wire _GEN_5 = _GEN_0 & fired_4; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_5; // @[Router.scala:203:29]
reg fired_5; // @[Router.scala:204:26]
wire _GEN_6 = _GEN_0 & fired_5; // @[Router.scala:204:26, :207:{33,71}] |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_59 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 10, 0)
node _source_ok_T = shr(io.in.a.bits.source, 11)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<11>(0h40f))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T_5
node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits = bits(_uncommonBits_T, 10, 0)
node _T_4 = shr(io.in.a.bits.source, 11)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<11>(0h40f))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_16, UInt<1>(0h1), "") : assert_1
node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_20 :
node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_23 = and(_T_21, _T_22)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 10, 0)
node _T_24 = shr(io.in.a.bits.source, 11)
node _T_25 = eq(_T_24, UInt<1>(0h0))
node _T_26 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_27 = and(_T_25, _T_26)
node _T_28 = leq(uncommonBits_1, UInt<11>(0h40f))
node _T_29 = and(_T_27, _T_28)
node _T_30 = and(_T_23, _T_29)
node _T_31 = or(UInt<1>(0h0), _T_30)
node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_33 = xor(io.in.a.bits.address, UInt<14>(0h2000))
node _T_34 = cvt(_T_33)
node _T_35 = and(_T_34, asSInt(UInt<10>(0h200)))
node _T_36 = asSInt(_T_35)
node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0)))
node _T_38 = and(_T_32, _T_37)
node _T_39 = or(UInt<1>(0h0), _T_38)
node _T_40 = and(_T_31, _T_39)
node _T_41 = asUInt(reset)
node _T_42 = eq(_T_41, UInt<1>(0h0))
when _T_42 :
node _T_43 = eq(_T_40, UInt<1>(0h0))
when _T_43 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_40, UInt<1>(0h1), "") : assert_2
node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_46 = and(_T_44, _T_45)
node _T_47 = or(UInt<1>(0h0), _T_46)
node _T_48 = xor(io.in.a.bits.address, UInt<14>(0h2000))
node _T_49 = cvt(_T_48)
node _T_50 = and(_T_49, asSInt(UInt<10>(0h200)))
node _T_51 = asSInt(_T_50)
node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0)))
node _T_53 = and(_T_47, _T_52)
node _T_54 = or(UInt<1>(0h0), _T_53)
node _T_55 = and(UInt<1>(0h0), _T_54)
node _T_56 = asUInt(reset)
node _T_57 = eq(_T_56, UInt<1>(0h0))
when _T_57 :
node _T_58 = eq(_T_55, UInt<1>(0h0))
when _T_58 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_55, UInt<1>(0h1), "") : assert_3
node _T_59 = asUInt(reset)
node _T_60 = eq(_T_59, UInt<1>(0h0))
when _T_60 :
node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_61 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_63 = asUInt(reset)
node _T_64 = eq(_T_63, UInt<1>(0h0))
when _T_64 :
node _T_65 = eq(_T_62, UInt<1>(0h0))
when _T_65 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_62, UInt<1>(0h1), "") : assert_5
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(is_aligned, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_70 = asUInt(reset)
node _T_71 = eq(_T_70, UInt<1>(0h0))
when _T_71 :
node _T_72 = eq(_T_69, UInt<1>(0h0))
when _T_72 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_69, UInt<1>(0h1), "") : assert_7
node _T_73 = not(io.in.a.bits.mask)
node _T_74 = eq(_T_73, UInt<1>(0h0))
node _T_75 = asUInt(reset)
node _T_76 = eq(_T_75, UInt<1>(0h0))
when _T_76 :
node _T_77 = eq(_T_74, UInt<1>(0h0))
when _T_77 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_74, UInt<1>(0h1), "") : assert_8
node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_79 = asUInt(reset)
node _T_80 = eq(_T_79, UInt<1>(0h0))
when _T_80 :
node _T_81 = eq(_T_78, UInt<1>(0h0))
when _T_81 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_78, UInt<1>(0h1), "") : assert_9
node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_82 :
node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_85 = and(_T_83, _T_84)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 10, 0)
node _T_86 = shr(io.in.a.bits.source, 11)
node _T_87 = eq(_T_86, UInt<1>(0h0))
node _T_88 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_89 = and(_T_87, _T_88)
node _T_90 = leq(uncommonBits_2, UInt<11>(0h40f))
node _T_91 = and(_T_89, _T_90)
node _T_92 = and(_T_85, _T_91)
node _T_93 = or(UInt<1>(0h0), _T_92)
node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_95 = xor(io.in.a.bits.address, UInt<14>(0h2000))
node _T_96 = cvt(_T_95)
node _T_97 = and(_T_96, asSInt(UInt<10>(0h200)))
node _T_98 = asSInt(_T_97)
node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = and(_T_94, _T_99)
node _T_101 = or(UInt<1>(0h0), _T_100)
node _T_102 = and(_T_93, _T_101)
node _T_103 = asUInt(reset)
node _T_104 = eq(_T_103, UInt<1>(0h0))
when _T_104 :
node _T_105 = eq(_T_102, UInt<1>(0h0))
when _T_105 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_102, UInt<1>(0h1), "") : assert_10
node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_108 = and(_T_106, _T_107)
node _T_109 = or(UInt<1>(0h0), _T_108)
node _T_110 = xor(io.in.a.bits.address, UInt<14>(0h2000))
node _T_111 = cvt(_T_110)
node _T_112 = and(_T_111, asSInt(UInt<10>(0h200)))
node _T_113 = asSInt(_T_112)
node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0)))
node _T_115 = and(_T_109, _T_114)
node _T_116 = or(UInt<1>(0h0), _T_115)
node _T_117 = and(UInt<1>(0h0), _T_116)
node _T_118 = asUInt(reset)
node _T_119 = eq(_T_118, UInt<1>(0h0))
when _T_119 :
node _T_120 = eq(_T_117, UInt<1>(0h0))
when _T_120 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_117, UInt<1>(0h1), "") : assert_11
node _T_121 = asUInt(reset)
node _T_122 = eq(_T_121, UInt<1>(0h0))
when _T_122 :
node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_125 = asUInt(reset)
node _T_126 = eq(_T_125, UInt<1>(0h0))
when _T_126 :
node _T_127 = eq(_T_124, UInt<1>(0h0))
when _T_127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_124, UInt<1>(0h1), "") : assert_13
node _T_128 = asUInt(reset)
node _T_129 = eq(_T_128, UInt<1>(0h0))
when _T_129 :
node _T_130 = eq(is_aligned, UInt<1>(0h0))
when _T_130 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_132 = asUInt(reset)
node _T_133 = eq(_T_132, UInt<1>(0h0))
when _T_133 :
node _T_134 = eq(_T_131, UInt<1>(0h0))
when _T_134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_131, UInt<1>(0h1), "") : assert_15
node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_136 = asUInt(reset)
node _T_137 = eq(_T_136, UInt<1>(0h0))
when _T_137 :
node _T_138 = eq(_T_135, UInt<1>(0h0))
when _T_138 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_135, UInt<1>(0h1), "") : assert_16
node _T_139 = not(io.in.a.bits.mask)
node _T_140 = eq(_T_139, UInt<1>(0h0))
node _T_141 = asUInt(reset)
node _T_142 = eq(_T_141, UInt<1>(0h0))
when _T_142 :
node _T_143 = eq(_T_140, UInt<1>(0h0))
when _T_143 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_140, UInt<1>(0h1), "") : assert_17
node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_145 = asUInt(reset)
node _T_146 = eq(_T_145, UInt<1>(0h0))
when _T_146 :
node _T_147 = eq(_T_144, UInt<1>(0h0))
when _T_147 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_144, UInt<1>(0h1), "") : assert_18
node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_148 :
node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_151 = and(_T_149, _T_150)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 10, 0)
node _T_152 = shr(io.in.a.bits.source, 11)
node _T_153 = eq(_T_152, UInt<1>(0h0))
node _T_154 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_155 = and(_T_153, _T_154)
node _T_156 = leq(uncommonBits_3, UInt<11>(0h40f))
node _T_157 = and(_T_155, _T_156)
node _T_158 = and(_T_151, _T_157)
node _T_159 = or(UInt<1>(0h0), _T_158)
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(_T_159, UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_159, UInt<1>(0h1), "") : assert_19
node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_165 = and(_T_163, _T_164)
node _T_166 = or(UInt<1>(0h0), _T_165)
node _T_167 = xor(io.in.a.bits.address, UInt<14>(0h2000))
node _T_168 = cvt(_T_167)
node _T_169 = and(_T_168, asSInt(UInt<10>(0h200)))
node _T_170 = asSInt(_T_169)
node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0)))
node _T_172 = and(_T_166, _T_171)
node _T_173 = or(UInt<1>(0h0), _T_172)
node _T_174 = asUInt(reset)
node _T_175 = eq(_T_174, UInt<1>(0h0))
when _T_175 :
node _T_176 = eq(_T_173, UInt<1>(0h0))
when _T_176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_173, UInt<1>(0h1), "") : assert_20
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_180 = asUInt(reset)
node _T_181 = eq(_T_180, UInt<1>(0h0))
when _T_181 :
node _T_182 = eq(is_aligned, UInt<1>(0h0))
when _T_182 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_183, UInt<1>(0h1), "") : assert_23
node _T_187 = eq(io.in.a.bits.mask, mask)
node _T_188 = asUInt(reset)
node _T_189 = eq(_T_188, UInt<1>(0h0))
when _T_189 :
node _T_190 = eq(_T_187, UInt<1>(0h0))
when _T_190 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_187, UInt<1>(0h1), "") : assert_24
node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_192 = asUInt(reset)
node _T_193 = eq(_T_192, UInt<1>(0h0))
when _T_193 :
node _T_194 = eq(_T_191, UInt<1>(0h0))
when _T_194 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_191, UInt<1>(0h1), "") : assert_25
node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_195 :
node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_198 = and(_T_196, _T_197)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 10, 0)
node _T_199 = shr(io.in.a.bits.source, 11)
node _T_200 = eq(_T_199, UInt<1>(0h0))
node _T_201 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_202 = and(_T_200, _T_201)
node _T_203 = leq(uncommonBits_4, UInt<11>(0h40f))
node _T_204 = and(_T_202, _T_203)
node _T_205 = and(_T_198, _T_204)
node _T_206 = or(UInt<1>(0h0), _T_205)
node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_209 = and(_T_207, _T_208)
node _T_210 = or(UInt<1>(0h0), _T_209)
node _T_211 = xor(io.in.a.bits.address, UInt<14>(0h2000))
node _T_212 = cvt(_T_211)
node _T_213 = and(_T_212, asSInt(UInt<10>(0h200)))
node _T_214 = asSInt(_T_213)
node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0)))
node _T_216 = and(_T_210, _T_215)
node _T_217 = or(UInt<1>(0h0), _T_216)
node _T_218 = and(_T_206, _T_217)
node _T_219 = asUInt(reset)
node _T_220 = eq(_T_219, UInt<1>(0h0))
when _T_220 :
node _T_221 = eq(_T_218, UInt<1>(0h0))
when _T_221 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_218, UInt<1>(0h1), "") : assert_26
node _T_222 = asUInt(reset)
node _T_223 = eq(_T_222, UInt<1>(0h0))
when _T_223 :
node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_225 = asUInt(reset)
node _T_226 = eq(_T_225, UInt<1>(0h0))
when _T_226 :
node _T_227 = eq(is_aligned, UInt<1>(0h0))
when _T_227 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_229 = asUInt(reset)
node _T_230 = eq(_T_229, UInt<1>(0h0))
when _T_230 :
node _T_231 = eq(_T_228, UInt<1>(0h0))
when _T_231 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_228, UInt<1>(0h1), "") : assert_29
node _T_232 = eq(io.in.a.bits.mask, mask)
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_232, UInt<1>(0h1), "") : assert_30
node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_236 :
node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_239 = and(_T_237, _T_238)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 10, 0)
node _T_240 = shr(io.in.a.bits.source, 11)
node _T_241 = eq(_T_240, UInt<1>(0h0))
node _T_242 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_243 = and(_T_241, _T_242)
node _T_244 = leq(uncommonBits_5, UInt<11>(0h40f))
node _T_245 = and(_T_243, _T_244)
node _T_246 = and(_T_239, _T_245)
node _T_247 = or(UInt<1>(0h0), _T_246)
node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_250 = and(_T_248, _T_249)
node _T_251 = or(UInt<1>(0h0), _T_250)
node _T_252 = xor(io.in.a.bits.address, UInt<14>(0h2000))
node _T_253 = cvt(_T_252)
node _T_254 = and(_T_253, asSInt(UInt<10>(0h200)))
node _T_255 = asSInt(_T_254)
node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0)))
node _T_257 = and(_T_251, _T_256)
node _T_258 = or(UInt<1>(0h0), _T_257)
node _T_259 = and(_T_247, _T_258)
node _T_260 = asUInt(reset)
node _T_261 = eq(_T_260, UInt<1>(0h0))
when _T_261 :
node _T_262 = eq(_T_259, UInt<1>(0h0))
when _T_262 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_259, UInt<1>(0h1), "") : assert_31
node _T_263 = asUInt(reset)
node _T_264 = eq(_T_263, UInt<1>(0h0))
when _T_264 :
node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_265 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_266 = asUInt(reset)
node _T_267 = eq(_T_266, UInt<1>(0h0))
when _T_267 :
node _T_268 = eq(is_aligned, UInt<1>(0h0))
when _T_268 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_270 = asUInt(reset)
node _T_271 = eq(_T_270, UInt<1>(0h0))
when _T_271 :
node _T_272 = eq(_T_269, UInt<1>(0h0))
when _T_272 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_269, UInt<1>(0h1), "") : assert_34
node _T_273 = not(mask)
node _T_274 = and(io.in.a.bits.mask, _T_273)
node _T_275 = eq(_T_274, UInt<1>(0h0))
node _T_276 = asUInt(reset)
node _T_277 = eq(_T_276, UInt<1>(0h0))
when _T_277 :
node _T_278 = eq(_T_275, UInt<1>(0h0))
when _T_278 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_275, UInt<1>(0h1), "") : assert_35
node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_279 :
node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_282 = and(_T_280, _T_281)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 10, 0)
node _T_283 = shr(io.in.a.bits.source, 11)
node _T_284 = eq(_T_283, UInt<1>(0h0))
node _T_285 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_286 = and(_T_284, _T_285)
node _T_287 = leq(uncommonBits_6, UInt<11>(0h40f))
node _T_288 = and(_T_286, _T_287)
node _T_289 = and(_T_282, _T_288)
node _T_290 = or(UInt<1>(0h0), _T_289)
node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_292 = xor(io.in.a.bits.address, UInt<14>(0h2000))
node _T_293 = cvt(_T_292)
node _T_294 = and(_T_293, asSInt(UInt<10>(0h200)))
node _T_295 = asSInt(_T_294)
node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0)))
node _T_297 = and(_T_291, _T_296)
node _T_298 = or(UInt<1>(0h0), _T_297)
node _T_299 = and(_T_290, _T_298)
node _T_300 = asUInt(reset)
node _T_301 = eq(_T_300, UInt<1>(0h0))
when _T_301 :
node _T_302 = eq(_T_299, UInt<1>(0h0))
when _T_302 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_299, UInt<1>(0h1), "") : assert_36
node _T_303 = asUInt(reset)
node _T_304 = eq(_T_303, UInt<1>(0h0))
when _T_304 :
node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_305 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_306 = asUInt(reset)
node _T_307 = eq(_T_306, UInt<1>(0h0))
when _T_307 :
node _T_308 = eq(is_aligned, UInt<1>(0h0))
when _T_308 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_310 = asUInt(reset)
node _T_311 = eq(_T_310, UInt<1>(0h0))
when _T_311 :
node _T_312 = eq(_T_309, UInt<1>(0h0))
when _T_312 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_309, UInt<1>(0h1), "") : assert_39
node _T_313 = eq(io.in.a.bits.mask, mask)
node _T_314 = asUInt(reset)
node _T_315 = eq(_T_314, UInt<1>(0h0))
when _T_315 :
node _T_316 = eq(_T_313, UInt<1>(0h0))
when _T_316 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_313, UInt<1>(0h1), "") : assert_40
node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_317 :
node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_320 = and(_T_318, _T_319)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 10, 0)
node _T_321 = shr(io.in.a.bits.source, 11)
node _T_322 = eq(_T_321, UInt<1>(0h0))
node _T_323 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_324 = and(_T_322, _T_323)
node _T_325 = leq(uncommonBits_7, UInt<11>(0h40f))
node _T_326 = and(_T_324, _T_325)
node _T_327 = and(_T_320, _T_326)
node _T_328 = or(UInt<1>(0h0), _T_327)
node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_330 = xor(io.in.a.bits.address, UInt<14>(0h2000))
node _T_331 = cvt(_T_330)
node _T_332 = and(_T_331, asSInt(UInt<10>(0h200)))
node _T_333 = asSInt(_T_332)
node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0)))
node _T_335 = and(_T_329, _T_334)
node _T_336 = or(UInt<1>(0h0), _T_335)
node _T_337 = and(_T_328, _T_336)
node _T_338 = asUInt(reset)
node _T_339 = eq(_T_338, UInt<1>(0h0))
when _T_339 :
node _T_340 = eq(_T_337, UInt<1>(0h0))
when _T_340 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_337, UInt<1>(0h1), "") : assert_41
node _T_341 = asUInt(reset)
node _T_342 = eq(_T_341, UInt<1>(0h0))
when _T_342 :
node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_343 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_344 = asUInt(reset)
node _T_345 = eq(_T_344, UInt<1>(0h0))
when _T_345 :
node _T_346 = eq(is_aligned, UInt<1>(0h0))
when _T_346 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_348 = asUInt(reset)
node _T_349 = eq(_T_348, UInt<1>(0h0))
when _T_349 :
node _T_350 = eq(_T_347, UInt<1>(0h0))
when _T_350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_347, UInt<1>(0h1), "") : assert_44
node _T_351 = eq(io.in.a.bits.mask, mask)
node _T_352 = asUInt(reset)
node _T_353 = eq(_T_352, UInt<1>(0h0))
when _T_353 :
node _T_354 = eq(_T_351, UInt<1>(0h0))
when _T_354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_351, UInt<1>(0h1), "") : assert_45
node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_355 :
node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_358 = and(_T_356, _T_357)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 10, 0)
node _T_359 = shr(io.in.a.bits.source, 11)
node _T_360 = eq(_T_359, UInt<1>(0h0))
node _T_361 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_362 = and(_T_360, _T_361)
node _T_363 = leq(uncommonBits_8, UInt<11>(0h40f))
node _T_364 = and(_T_362, _T_363)
node _T_365 = and(_T_358, _T_364)
node _T_366 = or(UInt<1>(0h0), _T_365)
node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_368 = xor(io.in.a.bits.address, UInt<14>(0h2000))
node _T_369 = cvt(_T_368)
node _T_370 = and(_T_369, asSInt(UInt<10>(0h200)))
node _T_371 = asSInt(_T_370)
node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0)))
node _T_373 = and(_T_367, _T_372)
node _T_374 = or(UInt<1>(0h0), _T_373)
node _T_375 = and(_T_366, _T_374)
node _T_376 = asUInt(reset)
node _T_377 = eq(_T_376, UInt<1>(0h0))
when _T_377 :
node _T_378 = eq(_T_375, UInt<1>(0h0))
when _T_378 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_375, UInt<1>(0h1), "") : assert_46
node _T_379 = asUInt(reset)
node _T_380 = eq(_T_379, UInt<1>(0h0))
when _T_380 :
node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_381 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_382 = asUInt(reset)
node _T_383 = eq(_T_382, UInt<1>(0h0))
when _T_383 :
node _T_384 = eq(is_aligned, UInt<1>(0h0))
when _T_384 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_386 = asUInt(reset)
node _T_387 = eq(_T_386, UInt<1>(0h0))
when _T_387 :
node _T_388 = eq(_T_385, UInt<1>(0h0))
when _T_388 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_385, UInt<1>(0h1), "") : assert_49
node _T_389 = eq(io.in.a.bits.mask, mask)
node _T_390 = asUInt(reset)
node _T_391 = eq(_T_390, UInt<1>(0h0))
when _T_391 :
node _T_392 = eq(_T_389, UInt<1>(0h0))
when _T_392 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_389, UInt<1>(0h1), "") : assert_50
node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_394 = asUInt(reset)
node _T_395 = eq(_T_394, UInt<1>(0h0))
when _T_395 :
node _T_396 = eq(_T_393, UInt<1>(0h0))
when _T_396 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_393, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(_T_397, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_397, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<11>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 10, 0)
node _source_ok_T_6 = shr(io.in.d.bits.source, 11)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<11>(0h40f))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_11
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_401 :
node _T_402 = asUInt(reset)
node _T_403 = eq(_T_402, UInt<1>(0h0))
when _T_403 :
node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_404 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_406 = asUInt(reset)
node _T_407 = eq(_T_406, UInt<1>(0h0))
when _T_407 :
node _T_408 = eq(_T_405, UInt<1>(0h0))
when _T_408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_405, UInt<1>(0h1), "") : assert_54
node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_410 = asUInt(reset)
node _T_411 = eq(_T_410, UInt<1>(0h0))
when _T_411 :
node _T_412 = eq(_T_409, UInt<1>(0h0))
when _T_412 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_409, UInt<1>(0h1), "") : assert_55
node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_414 = asUInt(reset)
node _T_415 = eq(_T_414, UInt<1>(0h0))
when _T_415 :
node _T_416 = eq(_T_413, UInt<1>(0h0))
when _T_416 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_413, UInt<1>(0h1), "") : assert_56
node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_418 = asUInt(reset)
node _T_419 = eq(_T_418, UInt<1>(0h0))
when _T_419 :
node _T_420 = eq(_T_417, UInt<1>(0h0))
when _T_420 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_417, UInt<1>(0h1), "") : assert_57
node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_421 :
node _T_422 = asUInt(reset)
node _T_423 = eq(_T_422, UInt<1>(0h0))
when _T_423 :
node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_424 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_425 = asUInt(reset)
node _T_426 = eq(_T_425, UInt<1>(0h0))
when _T_426 :
node _T_427 = eq(sink_ok, UInt<1>(0h0))
when _T_427 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_429 = asUInt(reset)
node _T_430 = eq(_T_429, UInt<1>(0h0))
when _T_430 :
node _T_431 = eq(_T_428, UInt<1>(0h0))
when _T_431 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_428, UInt<1>(0h1), "") : assert_60
node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_433 = asUInt(reset)
node _T_434 = eq(_T_433, UInt<1>(0h0))
when _T_434 :
node _T_435 = eq(_T_432, UInt<1>(0h0))
when _T_435 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_432, UInt<1>(0h1), "") : assert_61
node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_437 = asUInt(reset)
node _T_438 = eq(_T_437, UInt<1>(0h0))
when _T_438 :
node _T_439 = eq(_T_436, UInt<1>(0h0))
when _T_439 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_436, UInt<1>(0h1), "") : assert_62
node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_441 = asUInt(reset)
node _T_442 = eq(_T_441, UInt<1>(0h0))
when _T_442 :
node _T_443 = eq(_T_440, UInt<1>(0h0))
when _T_443 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_440, UInt<1>(0h1), "") : assert_63
node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_445 = or(UInt<1>(0h0), _T_444)
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_445, UInt<1>(0h1), "") : assert_64
node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_449 :
node _T_450 = asUInt(reset)
node _T_451 = eq(_T_450, UInt<1>(0h0))
when _T_451 :
node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_452 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(sink_ok, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_457 = asUInt(reset)
node _T_458 = eq(_T_457, UInt<1>(0h0))
when _T_458 :
node _T_459 = eq(_T_456, UInt<1>(0h0))
when _T_459 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_456, UInt<1>(0h1), "") : assert_67
node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_461 = asUInt(reset)
node _T_462 = eq(_T_461, UInt<1>(0h0))
when _T_462 :
node _T_463 = eq(_T_460, UInt<1>(0h0))
when _T_463 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_460, UInt<1>(0h1), "") : assert_68
node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_465 = asUInt(reset)
node _T_466 = eq(_T_465, UInt<1>(0h0))
when _T_466 :
node _T_467 = eq(_T_464, UInt<1>(0h0))
when _T_467 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_464, UInt<1>(0h1), "") : assert_69
node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_469 = or(_T_468, io.in.d.bits.corrupt)
node _T_470 = asUInt(reset)
node _T_471 = eq(_T_470, UInt<1>(0h0))
when _T_471 :
node _T_472 = eq(_T_469, UInt<1>(0h0))
when _T_472 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_469, UInt<1>(0h1), "") : assert_70
node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_474 = or(UInt<1>(0h0), _T_473)
node _T_475 = asUInt(reset)
node _T_476 = eq(_T_475, UInt<1>(0h0))
when _T_476 :
node _T_477 = eq(_T_474, UInt<1>(0h0))
when _T_477 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_474, UInt<1>(0h1), "") : assert_71
node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_478 :
node _T_479 = asUInt(reset)
node _T_480 = eq(_T_479, UInt<1>(0h0))
when _T_480 :
node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_481 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_483 = asUInt(reset)
node _T_484 = eq(_T_483, UInt<1>(0h0))
when _T_484 :
node _T_485 = eq(_T_482, UInt<1>(0h0))
when _T_485 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_482, UInt<1>(0h1), "") : assert_73
node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_487 = asUInt(reset)
node _T_488 = eq(_T_487, UInt<1>(0h0))
when _T_488 :
node _T_489 = eq(_T_486, UInt<1>(0h0))
when _T_489 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_486, UInt<1>(0h1), "") : assert_74
node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_491 = or(UInt<1>(0h0), _T_490)
node _T_492 = asUInt(reset)
node _T_493 = eq(_T_492, UInt<1>(0h0))
when _T_493 :
node _T_494 = eq(_T_491, UInt<1>(0h0))
when _T_494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_491, UInt<1>(0h1), "") : assert_75
node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_495 :
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_500 = asUInt(reset)
node _T_501 = eq(_T_500, UInt<1>(0h0))
when _T_501 :
node _T_502 = eq(_T_499, UInt<1>(0h0))
when _T_502 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_499, UInt<1>(0h1), "") : assert_77
node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_504 = or(_T_503, io.in.d.bits.corrupt)
node _T_505 = asUInt(reset)
node _T_506 = eq(_T_505, UInt<1>(0h0))
when _T_506 :
node _T_507 = eq(_T_504, UInt<1>(0h0))
when _T_507 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_504, UInt<1>(0h1), "") : assert_78
node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_509 = or(UInt<1>(0h0), _T_508)
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_T_509, UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_509, UInt<1>(0h1), "") : assert_79
node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_513 :
node _T_514 = asUInt(reset)
node _T_515 = eq(_T_514, UInt<1>(0h0))
when _T_515 :
node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_516 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_518 = asUInt(reset)
node _T_519 = eq(_T_518, UInt<1>(0h0))
when _T_519 :
node _T_520 = eq(_T_517, UInt<1>(0h0))
when _T_520 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_517, UInt<1>(0h1), "") : assert_81
node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_522 = asUInt(reset)
node _T_523 = eq(_T_522, UInt<1>(0h0))
when _T_523 :
node _T_524 = eq(_T_521, UInt<1>(0h0))
when _T_524 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_521, UInt<1>(0h1), "") : assert_82
node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_526 = or(UInt<1>(0h0), _T_525)
node _T_527 = asUInt(reset)
node _T_528 = eq(_T_527, UInt<1>(0h0))
when _T_528 :
node _T_529 = eq(_T_526, UInt<1>(0h0))
when _T_529 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_526, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<14>(0h0)
connect _WIRE.bits.source, UInt<11>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_531 = asUInt(reset)
node _T_532 = eq(_T_531, UInt<1>(0h0))
when _T_532 :
node _T_533 = eq(_T_530, UInt<1>(0h0))
when _T_533 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_530, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<14>(0h0)
connect _WIRE_2.bits.source, UInt<11>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_535 = asUInt(reset)
node _T_536 = eq(_T_535, UInt<1>(0h0))
when _T_536 :
node _T_537 = eq(_T_534, UInt<1>(0h0))
when _T_537 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_534, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_539 = asUInt(reset)
node _T_540 = eq(_T_539, UInt<1>(0h0))
when _T_540 :
node _T_541 = eq(_T_538, UInt<1>(0h0))
when _T_541 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_538, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_542 = eq(a_first, UInt<1>(0h0))
node _T_543 = and(io.in.a.valid, _T_542)
when _T_543 :
node _T_544 = eq(io.in.a.bits.opcode, opcode)
node _T_545 = asUInt(reset)
node _T_546 = eq(_T_545, UInt<1>(0h0))
when _T_546 :
node _T_547 = eq(_T_544, UInt<1>(0h0))
when _T_547 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_544, UInt<1>(0h1), "") : assert_87
node _T_548 = eq(io.in.a.bits.param, param)
node _T_549 = asUInt(reset)
node _T_550 = eq(_T_549, UInt<1>(0h0))
when _T_550 :
node _T_551 = eq(_T_548, UInt<1>(0h0))
when _T_551 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_548, UInt<1>(0h1), "") : assert_88
node _T_552 = eq(io.in.a.bits.size, size)
node _T_553 = asUInt(reset)
node _T_554 = eq(_T_553, UInt<1>(0h0))
when _T_554 :
node _T_555 = eq(_T_552, UInt<1>(0h0))
when _T_555 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_552, UInt<1>(0h1), "") : assert_89
node _T_556 = eq(io.in.a.bits.source, source)
node _T_557 = asUInt(reset)
node _T_558 = eq(_T_557, UInt<1>(0h0))
when _T_558 :
node _T_559 = eq(_T_556, UInt<1>(0h0))
when _T_559 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_556, UInt<1>(0h1), "") : assert_90
node _T_560 = eq(io.in.a.bits.address, address)
node _T_561 = asUInt(reset)
node _T_562 = eq(_T_561, UInt<1>(0h0))
when _T_562 :
node _T_563 = eq(_T_560, UInt<1>(0h0))
when _T_563 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_560, UInt<1>(0h1), "") : assert_91
node _T_564 = and(io.in.a.ready, io.in.a.valid)
node _T_565 = and(_T_564, a_first)
when _T_565 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_566 = eq(d_first, UInt<1>(0h0))
node _T_567 = and(io.in.d.valid, _T_566)
when _T_567 :
node _T_568 = eq(io.in.d.bits.opcode, opcode_1)
node _T_569 = asUInt(reset)
node _T_570 = eq(_T_569, UInt<1>(0h0))
when _T_570 :
node _T_571 = eq(_T_568, UInt<1>(0h0))
when _T_571 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_568, UInt<1>(0h1), "") : assert_92
node _T_572 = eq(io.in.d.bits.param, param_1)
node _T_573 = asUInt(reset)
node _T_574 = eq(_T_573, UInt<1>(0h0))
when _T_574 :
node _T_575 = eq(_T_572, UInt<1>(0h0))
when _T_575 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_572, UInt<1>(0h1), "") : assert_93
node _T_576 = eq(io.in.d.bits.size, size_1)
node _T_577 = asUInt(reset)
node _T_578 = eq(_T_577, UInt<1>(0h0))
when _T_578 :
node _T_579 = eq(_T_576, UInt<1>(0h0))
when _T_579 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_576, UInt<1>(0h1), "") : assert_94
node _T_580 = eq(io.in.d.bits.source, source_1)
node _T_581 = asUInt(reset)
node _T_582 = eq(_T_581, UInt<1>(0h0))
when _T_582 :
node _T_583 = eq(_T_580, UInt<1>(0h0))
when _T_583 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_580, UInt<1>(0h1), "") : assert_95
node _T_584 = eq(io.in.d.bits.sink, sink)
node _T_585 = asUInt(reset)
node _T_586 = eq(_T_585, UInt<1>(0h0))
when _T_586 :
node _T_587 = eq(_T_584, UInt<1>(0h0))
when _T_587 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_584, UInt<1>(0h1), "") : assert_96
node _T_588 = eq(io.in.d.bits.denied, denied)
node _T_589 = asUInt(reset)
node _T_590 = eq(_T_589, UInt<1>(0h0))
when _T_590 :
node _T_591 = eq(_T_588, UInt<1>(0h0))
when _T_591 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_588, UInt<1>(0h1), "") : assert_97
node _T_592 = and(io.in.d.ready, io.in.d.valid)
node _T_593 = and(_T_592, d_first)
when _T_593 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<1040>, clock, reset, UInt<1040>(0h0)
regreset inflight_opcodes : UInt<4160>, clock, reset, UInt<4160>(0h0)
regreset inflight_sizes : UInt<4160>, clock, reset, UInt<4160>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<1040>
connect a_set, UInt<1040>(0h0)
wire a_set_wo_ready : UInt<1040>
connect a_set_wo_ready, UInt<1040>(0h0)
wire a_opcodes_set : UInt<4160>
connect a_opcodes_set, UInt<4160>(0h0)
wire a_sizes_set : UInt<4160>
connect a_sizes_set, UInt<4160>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<3>
connect a_sizes_set_interm, UInt<3>(0h0)
node _T_594 = and(io.in.a.valid, a_first_1)
node _T_595 = and(_T_594, UInt<1>(0h1))
when _T_595 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_596 = and(io.in.a.ready, io.in.a.valid)
node _T_597 = and(_T_596, a_first_1)
node _T_598 = and(_T_597, UInt<1>(0h1))
when _T_598 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_599 = dshr(inflight, io.in.a.bits.source)
node _T_600 = bits(_T_599, 0, 0)
node _T_601 = eq(_T_600, UInt<1>(0h0))
node _T_602 = asUInt(reset)
node _T_603 = eq(_T_602, UInt<1>(0h0))
when _T_603 :
node _T_604 = eq(_T_601, UInt<1>(0h0))
when _T_604 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_601, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<1040>
connect d_clr, UInt<1040>(0h0)
wire d_clr_wo_ready : UInt<1040>
connect d_clr_wo_ready, UInt<1040>(0h0)
wire d_opcodes_clr : UInt<4160>
connect d_opcodes_clr, UInt<4160>(0h0)
wire d_sizes_clr : UInt<4160>
connect d_sizes_clr, UInt<4160>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_605 = and(io.in.d.valid, d_first_1)
node _T_606 = and(_T_605, UInt<1>(0h1))
node _T_607 = eq(d_release_ack, UInt<1>(0h0))
node _T_608 = and(_T_606, _T_607)
when _T_608 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_609 = and(io.in.d.ready, io.in.d.valid)
node _T_610 = and(_T_609, d_first_1)
node _T_611 = and(_T_610, UInt<1>(0h1))
node _T_612 = eq(d_release_ack, UInt<1>(0h0))
node _T_613 = and(_T_611, _T_612)
when _T_613 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_614 = and(io.in.d.valid, d_first_1)
node _T_615 = and(_T_614, UInt<1>(0h1))
node _T_616 = eq(d_release_ack, UInt<1>(0h0))
node _T_617 = and(_T_615, _T_616)
when _T_617 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_618 = dshr(inflight, io.in.d.bits.source)
node _T_619 = bits(_T_618, 0, 0)
node _T_620 = or(_T_619, same_cycle_resp)
node _T_621 = asUInt(reset)
node _T_622 = eq(_T_621, UInt<1>(0h0))
when _T_622 :
node _T_623 = eq(_T_620, UInt<1>(0h0))
when _T_623 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_620, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_626 = or(_T_624, _T_625)
node _T_627 = asUInt(reset)
node _T_628 = eq(_T_627, UInt<1>(0h0))
when _T_628 :
node _T_629 = eq(_T_626, UInt<1>(0h0))
when _T_629 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_626, UInt<1>(0h1), "") : assert_100
node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_631 = asUInt(reset)
node _T_632 = eq(_T_631, UInt<1>(0h0))
when _T_632 :
node _T_633 = eq(_T_630, UInt<1>(0h0))
when _T_633 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_630, UInt<1>(0h1), "") : assert_101
else :
node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_636 = or(_T_634, _T_635)
node _T_637 = asUInt(reset)
node _T_638 = eq(_T_637, UInt<1>(0h0))
when _T_638 :
node _T_639 = eq(_T_636, UInt<1>(0h0))
when _T_639 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_636, UInt<1>(0h1), "") : assert_102
node _T_640 = eq(io.in.d.bits.size, a_size_lookup)
node _T_641 = asUInt(reset)
node _T_642 = eq(_T_641, UInt<1>(0h0))
when _T_642 :
node _T_643 = eq(_T_640, UInt<1>(0h0))
when _T_643 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_640, UInt<1>(0h1), "") : assert_103
node _T_644 = and(io.in.d.valid, d_first_1)
node _T_645 = and(_T_644, a_first_1)
node _T_646 = and(_T_645, io.in.a.valid)
node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_648 = and(_T_646, _T_647)
node _T_649 = eq(d_release_ack, UInt<1>(0h0))
node _T_650 = and(_T_648, _T_649)
when _T_650 :
node _T_651 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_652 = or(_T_651, io.in.a.ready)
node _T_653 = asUInt(reset)
node _T_654 = eq(_T_653, UInt<1>(0h0))
when _T_654 :
node _T_655 = eq(_T_652, UInt<1>(0h0))
when _T_655 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_652, UInt<1>(0h1), "") : assert_104
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_121
node _T_656 = orr(inflight)
node _T_657 = eq(_T_656, UInt<1>(0h0))
node _T_658 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_659 = or(_T_657, _T_658)
node _T_660 = lt(watchdog, plusarg_reader.out)
node _T_661 = or(_T_659, _T_660)
node _T_662 = asUInt(reset)
node _T_663 = eq(_T_662, UInt<1>(0h0))
when _T_663 :
node _T_664 = eq(_T_661, UInt<1>(0h0))
when _T_664 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_661, UInt<1>(0h1), "") : assert_105
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_665 = and(io.in.a.ready, io.in.a.valid)
node _T_666 = and(io.in.d.ready, io.in.d.valid)
node _T_667 = or(_T_665, _T_666)
when _T_667 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<1040>, clock, reset, UInt<1040>(0h0)
regreset inflight_opcodes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0)
regreset inflight_sizes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<14>(0h0)
connect _c_first_WIRE.bits.source, UInt<11>(0h0)
connect _c_first_WIRE.bits.size, UInt<2>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<14>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<11>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<1040>
connect c_set, UInt<1040>(0h0)
wire c_set_wo_ready : UInt<1040>
connect c_set_wo_ready, UInt<1040>(0h0)
wire c_opcodes_set : UInt<4160>
connect c_opcodes_set, UInt<4160>(0h0)
wire c_sizes_set : UInt<4160>
connect c_sizes_set, UInt<4160>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<3>
connect c_sizes_set_interm, UInt<3>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<14>(0h0)
connect _WIRE_6.bits.source, UInt<11>(0h0)
connect _WIRE_6.bits.size, UInt<2>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_668 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<14>(0h0)
connect _WIRE_8.bits.source, UInt<11>(0h0)
connect _WIRE_8.bits.size, UInt<2>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_669 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_670 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_671 = and(_T_669, _T_670)
node _T_672 = and(_T_668, _T_671)
when _T_672 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<14>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<11>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<14>(0h0)
connect _WIRE_10.bits.source, UInt<11>(0h0)
connect _WIRE_10.bits.size, UInt<2>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_673 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_674 = and(_T_673, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<14>(0h0)
connect _WIRE_12.bits.source, UInt<11>(0h0)
connect _WIRE_12.bits.size, UInt<2>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_675 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_676 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_677 = and(_T_675, _T_676)
node _T_678 = and(_T_674, _T_677)
when _T_678 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<14>(0h0)
connect _c_set_WIRE.bits.source, UInt<11>(0h0)
connect _c_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<14>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<11>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<14>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<11>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<14>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<11>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<14>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<11>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<14>(0h0)
connect _WIRE_14.bits.source, UInt<11>(0h0)
connect _WIRE_14.bits.size, UInt<2>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_679 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_680 = bits(_T_679, 0, 0)
node _T_681 = eq(_T_680, UInt<1>(0h0))
node _T_682 = asUInt(reset)
node _T_683 = eq(_T_682, UInt<1>(0h0))
when _T_683 :
node _T_684 = eq(_T_681, UInt<1>(0h0))
when _T_684 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_681, UInt<1>(0h1), "") : assert_106
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<14>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<11>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<14>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<11>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<1040>
connect d_clr_1, UInt<1040>(0h0)
wire d_clr_wo_ready_1 : UInt<1040>
connect d_clr_wo_ready_1, UInt<1040>(0h0)
wire d_opcodes_clr_1 : UInt<4160>
connect d_opcodes_clr_1, UInt<4160>(0h0)
wire d_sizes_clr_1 : UInt<4160>
connect d_sizes_clr_1, UInt<4160>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_685 = and(io.in.d.valid, d_first_2)
node _T_686 = and(_T_685, UInt<1>(0h1))
node _T_687 = and(_T_686, d_release_ack_1)
when _T_687 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_688 = and(io.in.d.ready, io.in.d.valid)
node _T_689 = and(_T_688, d_first_2)
node _T_690 = and(_T_689, UInt<1>(0h1))
node _T_691 = and(_T_690, d_release_ack_1)
when _T_691 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_692 = and(io.in.d.valid, d_first_2)
node _T_693 = and(_T_692, UInt<1>(0h1))
node _T_694 = and(_T_693, d_release_ack_1)
when _T_694 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<14>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<11>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<14>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<11>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<14>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<11>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_695 = dshr(inflight_1, io.in.d.bits.source)
node _T_696 = bits(_T_695, 0, 0)
node _T_697 = or(_T_696, same_cycle_resp_1)
node _T_698 = asUInt(reset)
node _T_699 = eq(_T_698, UInt<1>(0h0))
when _T_699 :
node _T_700 = eq(_T_697, UInt<1>(0h0))
when _T_700 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107
assert(clock, _T_697, UInt<1>(0h1), "") : assert_107
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<14>(0h0)
connect _WIRE_16.bits.source, UInt<11>(0h0)
connect _WIRE_16.bits.size, UInt<2>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_701 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_702 = asUInt(reset)
node _T_703 = eq(_T_702, UInt<1>(0h0))
when _T_703 :
node _T_704 = eq(_T_701, UInt<1>(0h0))
when _T_704 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_701, UInt<1>(0h1), "") : assert_108
else :
node _T_705 = eq(io.in.d.bits.size, c_size_lookup)
node _T_706 = asUInt(reset)
node _T_707 = eq(_T_706, UInt<1>(0h0))
when _T_707 :
node _T_708 = eq(_T_705, UInt<1>(0h0))
when _T_708 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_705, UInt<1>(0h1), "") : assert_109
node _T_709 = and(io.in.d.valid, d_first_2)
node _T_710 = and(_T_709, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<14>(0h0)
connect _WIRE_18.bits.source, UInt<11>(0h0)
connect _WIRE_18.bits.size, UInt<2>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_711 = and(_T_710, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<14>(0h0)
connect _WIRE_20.bits.source, UInt<11>(0h0)
connect _WIRE_20.bits.size, UInt<2>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_712 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_713 = and(_T_711, _T_712)
node _T_714 = and(_T_713, d_release_ack_1)
node _T_715 = eq(c_probe_ack, UInt<1>(0h0))
node _T_716 = and(_T_714, _T_715)
when _T_716 :
node _T_717 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<14>(0h0)
connect _WIRE_22.bits.source, UInt<11>(0h0)
connect _WIRE_22.bits.size, UInt<2>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_718 = or(_T_717, _WIRE_23.ready)
node _T_719 = asUInt(reset)
node _T_720 = eq(_T_719, UInt<1>(0h0))
when _T_720 :
node _T_721 = eq(_T_718, UInt<1>(0h0))
when _T_721 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_718, UInt<1>(0h1), "") : assert_110
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_122
node _T_722 = orr(inflight_1)
node _T_723 = eq(_T_722, UInt<1>(0h0))
node _T_724 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_725 = or(_T_723, _T_724)
node _T_726 = lt(watchdog_1, plusarg_reader_1.out)
node _T_727 = or(_T_725, _T_726)
node _T_728 = asUInt(reset)
node _T_729 = eq(_T_728, UInt<1>(0h0))
when _T_729 :
node _T_730 = eq(_T_727, UInt<1>(0h0))
when _T_730 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala:209:86)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_727, UInt<1>(0h1), "") : assert_111
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<14>(0h0)
connect _WIRE_24.bits.source, UInt<11>(0h0)
connect _WIRE_24.bits.size, UInt<2>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_731 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_732 = and(io.in.d.ready, io.in.d.valid)
node _T_733 = or(_T_731, _T_732)
when _T_733 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_59( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [13:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [10:0] io_in_d_bits_source // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [1:0] size; // @[Monitor.scala:389:22]
reg [10:0] source; // @[Monitor.scala:390:22]
reg [13:0] address; // @[Monitor.scala:391:22]
reg d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg [10:0] source_1; // @[Monitor.scala:541:22]
reg [1039:0] inflight; // @[Monitor.scala:614:27]
reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33]
reg a_first_counter_1; // @[Edges.scala:229:27]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire _GEN = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_0 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [1039:0] inflight_1; // @[Monitor.scala:726:35]
reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg d_first_counter_2; // @[Edges.scala:229:27]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_92 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T
node _is_aligned_mask_T = dshl(UInt<2>(0h3), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 1, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<2>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 0, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 1, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h2))
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(UInt<1>(0h1), mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(UInt<1>(0h1), mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_lo = cat(mask_acc_1, mask_acc)
node mask_hi = cat(mask_acc_3, mask_acc_2)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_11, UInt<1>(0h1), "") : assert_1
node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_15 :
node _T_16 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_17 = and(UInt<1>(0h0), _T_16)
node _T_18 = or(UInt<1>(0h0), _T_17)
node _T_19 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_20 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_21 = cvt(_T_20)
node _T_22 = and(_T_21, asSInt(UInt<7>(0h40)))
node _T_23 = asSInt(_T_22)
node _T_24 = eq(_T_23, asSInt(UInt<1>(0h0)))
node _T_25 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_26 = cvt(_T_25)
node _T_27 = and(_T_26, asSInt(UInt<5>(0h14)))
node _T_28 = asSInt(_T_27)
node _T_29 = eq(_T_28, asSInt(UInt<1>(0h0)))
node _T_30 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_31 = cvt(_T_30)
node _T_32 = and(_T_31, asSInt(UInt<4>(0h8)))
node _T_33 = asSInt(_T_32)
node _T_34 = eq(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_36 = cvt(_T_35)
node _T_37 = and(_T_36, asSInt(UInt<6>(0h20)))
node _T_38 = asSInt(_T_37)
node _T_39 = eq(_T_38, asSInt(UInt<1>(0h0)))
node _T_40 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_41 = cvt(_T_40)
node _T_42 = and(_T_41, asSInt(UInt<8>(0h80)))
node _T_43 = asSInt(_T_42)
node _T_44 = eq(_T_43, asSInt(UInt<1>(0h0)))
node _T_45 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<9>(0h100)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_24, _T_29)
node _T_51 = or(_T_50, _T_34)
node _T_52 = or(_T_51, _T_39)
node _T_53 = or(_T_52, _T_44)
node _T_54 = or(_T_53, _T_49)
node _T_55 = and(_T_19, _T_54)
node _T_56 = or(UInt<1>(0h0), _T_55)
node _T_57 = and(_T_18, _T_56)
node _T_58 = asUInt(reset)
node _T_59 = eq(_T_58, UInt<1>(0h0))
when _T_59 :
node _T_60 = eq(_T_57, UInt<1>(0h0))
when _T_60 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_57, UInt<1>(0h1), "") : assert_2
node _T_61 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_62 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_63 = and(_T_61, _T_62)
node _T_64 = or(UInt<1>(0h0), _T_63)
node _T_65 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_66 = cvt(_T_65)
node _T_67 = and(_T_66, asSInt(UInt<7>(0h40)))
node _T_68 = asSInt(_T_67)
node _T_69 = eq(_T_68, asSInt(UInt<1>(0h0)))
node _T_70 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_71 = cvt(_T_70)
node _T_72 = and(_T_71, asSInt(UInt<5>(0h14)))
node _T_73 = asSInt(_T_72)
node _T_74 = eq(_T_73, asSInt(UInt<1>(0h0)))
node _T_75 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_76 = cvt(_T_75)
node _T_77 = and(_T_76, asSInt(UInt<4>(0h8)))
node _T_78 = asSInt(_T_77)
node _T_79 = eq(_T_78, asSInt(UInt<1>(0h0)))
node _T_80 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_81 = cvt(_T_80)
node _T_82 = and(_T_81, asSInt(UInt<6>(0h20)))
node _T_83 = asSInt(_T_82)
node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0)))
node _T_85 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_86 = cvt(_T_85)
node _T_87 = and(_T_86, asSInt(UInt<8>(0h80)))
node _T_88 = asSInt(_T_87)
node _T_89 = eq(_T_88, asSInt(UInt<1>(0h0)))
node _T_90 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_91 = cvt(_T_90)
node _T_92 = and(_T_91, asSInt(UInt<9>(0h100)))
node _T_93 = asSInt(_T_92)
node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0)))
node _T_95 = or(_T_69, _T_74)
node _T_96 = or(_T_95, _T_79)
node _T_97 = or(_T_96, _T_84)
node _T_98 = or(_T_97, _T_89)
node _T_99 = or(_T_98, _T_94)
node _T_100 = and(_T_64, _T_99)
node _T_101 = or(UInt<1>(0h0), _T_100)
node _T_102 = and(UInt<1>(0h0), _T_101)
node _T_103 = asUInt(reset)
node _T_104 = eq(_T_103, UInt<1>(0h0))
when _T_104 :
node _T_105 = eq(_T_102, UInt<1>(0h0))
when _T_105 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_102, UInt<1>(0h1), "") : assert_3
node _T_106 = asUInt(reset)
node _T_107 = eq(_T_106, UInt<1>(0h0))
when _T_107 :
node _T_108 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_108 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_109 = geq(io.in.a.bits.size, UInt<2>(0h2))
node _T_110 = asUInt(reset)
node _T_111 = eq(_T_110, UInt<1>(0h0))
when _T_111 :
node _T_112 = eq(_T_109, UInt<1>(0h0))
when _T_112 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_109, UInt<1>(0h1), "") : assert_5
node _T_113 = asUInt(reset)
node _T_114 = eq(_T_113, UInt<1>(0h0))
when _T_114 :
node _T_115 = eq(is_aligned, UInt<1>(0h0))
when _T_115 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_116 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_117 = asUInt(reset)
node _T_118 = eq(_T_117, UInt<1>(0h0))
when _T_118 :
node _T_119 = eq(_T_116, UInt<1>(0h0))
when _T_119 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_116, UInt<1>(0h1), "") : assert_7
node _T_120 = not(io.in.a.bits.mask)
node _T_121 = eq(_T_120, UInt<1>(0h0))
node _T_122 = asUInt(reset)
node _T_123 = eq(_T_122, UInt<1>(0h0))
when _T_123 :
node _T_124 = eq(_T_121, UInt<1>(0h0))
when _T_124 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_121, UInt<1>(0h1), "") : assert_8
node _T_125 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_126 = asUInt(reset)
node _T_127 = eq(_T_126, UInt<1>(0h0))
when _T_127 :
node _T_128 = eq(_T_125, UInt<1>(0h0))
when _T_128 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_125, UInt<1>(0h1), "") : assert_9
node _T_129 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_129 :
node _T_130 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_131 = and(UInt<1>(0h0), _T_130)
node _T_132 = or(UInt<1>(0h0), _T_131)
node _T_133 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_134 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_135 = cvt(_T_134)
node _T_136 = and(_T_135, asSInt(UInt<7>(0h40)))
node _T_137 = asSInt(_T_136)
node _T_138 = eq(_T_137, asSInt(UInt<1>(0h0)))
node _T_139 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_140 = cvt(_T_139)
node _T_141 = and(_T_140, asSInt(UInt<5>(0h14)))
node _T_142 = asSInt(_T_141)
node _T_143 = eq(_T_142, asSInt(UInt<1>(0h0)))
node _T_144 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_145 = cvt(_T_144)
node _T_146 = and(_T_145, asSInt(UInt<4>(0h8)))
node _T_147 = asSInt(_T_146)
node _T_148 = eq(_T_147, asSInt(UInt<1>(0h0)))
node _T_149 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_150 = cvt(_T_149)
node _T_151 = and(_T_150, asSInt(UInt<6>(0h20)))
node _T_152 = asSInt(_T_151)
node _T_153 = eq(_T_152, asSInt(UInt<1>(0h0)))
node _T_154 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_155 = cvt(_T_154)
node _T_156 = and(_T_155, asSInt(UInt<8>(0h80)))
node _T_157 = asSInt(_T_156)
node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0)))
node _T_159 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_160 = cvt(_T_159)
node _T_161 = and(_T_160, asSInt(UInt<9>(0h100)))
node _T_162 = asSInt(_T_161)
node _T_163 = eq(_T_162, asSInt(UInt<1>(0h0)))
node _T_164 = or(_T_138, _T_143)
node _T_165 = or(_T_164, _T_148)
node _T_166 = or(_T_165, _T_153)
node _T_167 = or(_T_166, _T_158)
node _T_168 = or(_T_167, _T_163)
node _T_169 = and(_T_133, _T_168)
node _T_170 = or(UInt<1>(0h0), _T_169)
node _T_171 = and(_T_132, _T_170)
node _T_172 = asUInt(reset)
node _T_173 = eq(_T_172, UInt<1>(0h0))
when _T_173 :
node _T_174 = eq(_T_171, UInt<1>(0h0))
when _T_174 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_171, UInt<1>(0h1), "") : assert_10
node _T_175 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_176 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_177 = and(_T_175, _T_176)
node _T_178 = or(UInt<1>(0h0), _T_177)
node _T_179 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_180 = cvt(_T_179)
node _T_181 = and(_T_180, asSInt(UInt<7>(0h40)))
node _T_182 = asSInt(_T_181)
node _T_183 = eq(_T_182, asSInt(UInt<1>(0h0)))
node _T_184 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_185 = cvt(_T_184)
node _T_186 = and(_T_185, asSInt(UInt<5>(0h14)))
node _T_187 = asSInt(_T_186)
node _T_188 = eq(_T_187, asSInt(UInt<1>(0h0)))
node _T_189 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_190 = cvt(_T_189)
node _T_191 = and(_T_190, asSInt(UInt<4>(0h8)))
node _T_192 = asSInt(_T_191)
node _T_193 = eq(_T_192, asSInt(UInt<1>(0h0)))
node _T_194 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_195 = cvt(_T_194)
node _T_196 = and(_T_195, asSInt(UInt<6>(0h20)))
node _T_197 = asSInt(_T_196)
node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0)))
node _T_199 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_200 = cvt(_T_199)
node _T_201 = and(_T_200, asSInt(UInt<8>(0h80)))
node _T_202 = asSInt(_T_201)
node _T_203 = eq(_T_202, asSInt(UInt<1>(0h0)))
node _T_204 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_205 = cvt(_T_204)
node _T_206 = and(_T_205, asSInt(UInt<9>(0h100)))
node _T_207 = asSInt(_T_206)
node _T_208 = eq(_T_207, asSInt(UInt<1>(0h0)))
node _T_209 = or(_T_183, _T_188)
node _T_210 = or(_T_209, _T_193)
node _T_211 = or(_T_210, _T_198)
node _T_212 = or(_T_211, _T_203)
node _T_213 = or(_T_212, _T_208)
node _T_214 = and(_T_178, _T_213)
node _T_215 = or(UInt<1>(0h0), _T_214)
node _T_216 = and(UInt<1>(0h0), _T_215)
node _T_217 = asUInt(reset)
node _T_218 = eq(_T_217, UInt<1>(0h0))
when _T_218 :
node _T_219 = eq(_T_216, UInt<1>(0h0))
when _T_219 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_216, UInt<1>(0h1), "") : assert_11
node _T_220 = asUInt(reset)
node _T_221 = eq(_T_220, UInt<1>(0h0))
when _T_221 :
node _T_222 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_222 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_223 = geq(io.in.a.bits.size, UInt<2>(0h2))
node _T_224 = asUInt(reset)
node _T_225 = eq(_T_224, UInt<1>(0h0))
when _T_225 :
node _T_226 = eq(_T_223, UInt<1>(0h0))
when _T_226 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_223, UInt<1>(0h1), "") : assert_13
node _T_227 = asUInt(reset)
node _T_228 = eq(_T_227, UInt<1>(0h0))
when _T_228 :
node _T_229 = eq(is_aligned, UInt<1>(0h0))
when _T_229 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_230 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_231 = asUInt(reset)
node _T_232 = eq(_T_231, UInt<1>(0h0))
when _T_232 :
node _T_233 = eq(_T_230, UInt<1>(0h0))
when _T_233 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_230, UInt<1>(0h1), "") : assert_15
node _T_234 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_235 = asUInt(reset)
node _T_236 = eq(_T_235, UInt<1>(0h0))
when _T_236 :
node _T_237 = eq(_T_234, UInt<1>(0h0))
when _T_237 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_234, UInt<1>(0h1), "") : assert_16
node _T_238 = not(io.in.a.bits.mask)
node _T_239 = eq(_T_238, UInt<1>(0h0))
node _T_240 = asUInt(reset)
node _T_241 = eq(_T_240, UInt<1>(0h0))
when _T_241 :
node _T_242 = eq(_T_239, UInt<1>(0h0))
when _T_242 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_239, UInt<1>(0h1), "") : assert_17
node _T_243 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_244 = asUInt(reset)
node _T_245 = eq(_T_244, UInt<1>(0h0))
when _T_245 :
node _T_246 = eq(_T_243, UInt<1>(0h0))
when _T_246 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_243, UInt<1>(0h1), "") : assert_18
node _T_247 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_247 :
node _T_248 = eq(UInt<2>(0h2), io.in.a.bits.size)
node _T_249 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_250 = and(_T_248, _T_249)
node _T_251 = or(UInt<1>(0h0), _T_250)
node _T_252 = asUInt(reset)
node _T_253 = eq(_T_252, UInt<1>(0h0))
when _T_253 :
node _T_254 = eq(_T_251, UInt<1>(0h0))
when _T_254 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_251, UInt<1>(0h1), "") : assert_19
node _T_255 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_256 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_257 = and(_T_255, _T_256)
node _T_258 = or(UInt<1>(0h0), _T_257)
node _T_259 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_260 = cvt(_T_259)
node _T_261 = and(_T_260, asSInt(UInt<7>(0h40)))
node _T_262 = asSInt(_T_261)
node _T_263 = eq(_T_262, asSInt(UInt<1>(0h0)))
node _T_264 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_265 = cvt(_T_264)
node _T_266 = and(_T_265, asSInt(UInt<5>(0h14)))
node _T_267 = asSInt(_T_266)
node _T_268 = eq(_T_267, asSInt(UInt<1>(0h0)))
node _T_269 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_270 = cvt(_T_269)
node _T_271 = and(_T_270, asSInt(UInt<4>(0h8)))
node _T_272 = asSInt(_T_271)
node _T_273 = eq(_T_272, asSInt(UInt<1>(0h0)))
node _T_274 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_275 = cvt(_T_274)
node _T_276 = and(_T_275, asSInt(UInt<6>(0h20)))
node _T_277 = asSInt(_T_276)
node _T_278 = eq(_T_277, asSInt(UInt<1>(0h0)))
node _T_279 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_280 = cvt(_T_279)
node _T_281 = and(_T_280, asSInt(UInt<8>(0h80)))
node _T_282 = asSInt(_T_281)
node _T_283 = eq(_T_282, asSInt(UInt<1>(0h0)))
node _T_284 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_285 = cvt(_T_284)
node _T_286 = and(_T_285, asSInt(UInt<9>(0h100)))
node _T_287 = asSInt(_T_286)
node _T_288 = eq(_T_287, asSInt(UInt<1>(0h0)))
node _T_289 = or(_T_263, _T_268)
node _T_290 = or(_T_289, _T_273)
node _T_291 = or(_T_290, _T_278)
node _T_292 = or(_T_291, _T_283)
node _T_293 = or(_T_292, _T_288)
node _T_294 = and(_T_258, _T_293)
node _T_295 = or(UInt<1>(0h0), _T_294)
node _T_296 = asUInt(reset)
node _T_297 = eq(_T_296, UInt<1>(0h0))
when _T_297 :
node _T_298 = eq(_T_295, UInt<1>(0h0))
when _T_298 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_295, UInt<1>(0h1), "") : assert_20
node _T_299 = asUInt(reset)
node _T_300 = eq(_T_299, UInt<1>(0h0))
when _T_300 :
node _T_301 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_301 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_302 = asUInt(reset)
node _T_303 = eq(_T_302, UInt<1>(0h0))
when _T_303 :
node _T_304 = eq(is_aligned, UInt<1>(0h0))
when _T_304 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_305 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_306 = asUInt(reset)
node _T_307 = eq(_T_306, UInt<1>(0h0))
when _T_307 :
node _T_308 = eq(_T_305, UInt<1>(0h0))
when _T_308 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_305, UInt<1>(0h1), "") : assert_23
node _T_309 = eq(io.in.a.bits.mask, mask)
node _T_310 = asUInt(reset)
node _T_311 = eq(_T_310, UInt<1>(0h0))
when _T_311 :
node _T_312 = eq(_T_309, UInt<1>(0h0))
when _T_312 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_309, UInt<1>(0h1), "") : assert_24
node _T_313 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_314 = asUInt(reset)
node _T_315 = eq(_T_314, UInt<1>(0h0))
when _T_315 :
node _T_316 = eq(_T_313, UInt<1>(0h0))
when _T_316 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_313, UInt<1>(0h1), "") : assert_25
node _T_317 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_317 :
node _T_318 = eq(UInt<2>(0h2), io.in.a.bits.size)
node _T_319 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_320 = and(_T_318, _T_319)
node _T_321 = or(UInt<1>(0h0), _T_320)
node _T_322 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_323 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_324 = and(_T_322, _T_323)
node _T_325 = or(UInt<1>(0h0), _T_324)
node _T_326 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_327 = cvt(_T_326)
node _T_328 = and(_T_327, asSInt(UInt<7>(0h40)))
node _T_329 = asSInt(_T_328)
node _T_330 = eq(_T_329, asSInt(UInt<1>(0h0)))
node _T_331 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_332 = cvt(_T_331)
node _T_333 = and(_T_332, asSInt(UInt<5>(0h14)))
node _T_334 = asSInt(_T_333)
node _T_335 = eq(_T_334, asSInt(UInt<1>(0h0)))
node _T_336 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_337 = cvt(_T_336)
node _T_338 = and(_T_337, asSInt(UInt<4>(0h8)))
node _T_339 = asSInt(_T_338)
node _T_340 = eq(_T_339, asSInt(UInt<1>(0h0)))
node _T_341 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_342 = cvt(_T_341)
node _T_343 = and(_T_342, asSInt(UInt<6>(0h20)))
node _T_344 = asSInt(_T_343)
node _T_345 = eq(_T_344, asSInt(UInt<1>(0h0)))
node _T_346 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_347 = cvt(_T_346)
node _T_348 = and(_T_347, asSInt(UInt<8>(0h80)))
node _T_349 = asSInt(_T_348)
node _T_350 = eq(_T_349, asSInt(UInt<1>(0h0)))
node _T_351 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_352 = cvt(_T_351)
node _T_353 = and(_T_352, asSInt(UInt<9>(0h100)))
node _T_354 = asSInt(_T_353)
node _T_355 = eq(_T_354, asSInt(UInt<1>(0h0)))
node _T_356 = or(_T_330, _T_335)
node _T_357 = or(_T_356, _T_340)
node _T_358 = or(_T_357, _T_345)
node _T_359 = or(_T_358, _T_350)
node _T_360 = or(_T_359, _T_355)
node _T_361 = and(_T_325, _T_360)
node _T_362 = or(UInt<1>(0h0), _T_361)
node _T_363 = and(_T_321, _T_362)
node _T_364 = asUInt(reset)
node _T_365 = eq(_T_364, UInt<1>(0h0))
when _T_365 :
node _T_366 = eq(_T_363, UInt<1>(0h0))
when _T_366 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_363, UInt<1>(0h1), "") : assert_26
node _T_367 = asUInt(reset)
node _T_368 = eq(_T_367, UInt<1>(0h0))
when _T_368 :
node _T_369 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_369 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_370 = asUInt(reset)
node _T_371 = eq(_T_370, UInt<1>(0h0))
when _T_371 :
node _T_372 = eq(is_aligned, UInt<1>(0h0))
when _T_372 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_373 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_374 = asUInt(reset)
node _T_375 = eq(_T_374, UInt<1>(0h0))
when _T_375 :
node _T_376 = eq(_T_373, UInt<1>(0h0))
when _T_376 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_373, UInt<1>(0h1), "") : assert_29
node _T_377 = eq(io.in.a.bits.mask, mask)
node _T_378 = asUInt(reset)
node _T_379 = eq(_T_378, UInt<1>(0h0))
when _T_379 :
node _T_380 = eq(_T_377, UInt<1>(0h0))
when _T_380 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_377, UInt<1>(0h1), "") : assert_30
node _T_381 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_381 :
node _T_382 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_383 = and(UInt<1>(0h0), _T_382)
node _T_384 = or(UInt<1>(0h0), _T_383)
node _T_385 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_386 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_387 = and(_T_385, _T_386)
node _T_388 = or(UInt<1>(0h0), _T_387)
node _T_389 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_390 = cvt(_T_389)
node _T_391 = and(_T_390, asSInt(UInt<7>(0h40)))
node _T_392 = asSInt(_T_391)
node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0)))
node _T_394 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_395 = cvt(_T_394)
node _T_396 = and(_T_395, asSInt(UInt<5>(0h14)))
node _T_397 = asSInt(_T_396)
node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0)))
node _T_399 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_400 = cvt(_T_399)
node _T_401 = and(_T_400, asSInt(UInt<4>(0h8)))
node _T_402 = asSInt(_T_401)
node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0)))
node _T_404 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_405 = cvt(_T_404)
node _T_406 = and(_T_405, asSInt(UInt<6>(0h20)))
node _T_407 = asSInt(_T_406)
node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0)))
node _T_409 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_410 = cvt(_T_409)
node _T_411 = and(_T_410, asSInt(UInt<8>(0h80)))
node _T_412 = asSInt(_T_411)
node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0)))
node _T_414 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_415 = cvt(_T_414)
node _T_416 = and(_T_415, asSInt(UInt<9>(0h100)))
node _T_417 = asSInt(_T_416)
node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0)))
node _T_419 = or(_T_393, _T_398)
node _T_420 = or(_T_419, _T_403)
node _T_421 = or(_T_420, _T_408)
node _T_422 = or(_T_421, _T_413)
node _T_423 = or(_T_422, _T_418)
node _T_424 = and(_T_388, _T_423)
node _T_425 = or(UInt<1>(0h0), _T_424)
node _T_426 = and(_T_384, _T_425)
node _T_427 = asUInt(reset)
node _T_428 = eq(_T_427, UInt<1>(0h0))
when _T_428 :
node _T_429 = eq(_T_426, UInt<1>(0h0))
when _T_429 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_426, UInt<1>(0h1), "") : assert_31
node _T_430 = asUInt(reset)
node _T_431 = eq(_T_430, UInt<1>(0h0))
when _T_431 :
node _T_432 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_432 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_433 = asUInt(reset)
node _T_434 = eq(_T_433, UInt<1>(0h0))
when _T_434 :
node _T_435 = eq(is_aligned, UInt<1>(0h0))
when _T_435 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_436 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_437 = asUInt(reset)
node _T_438 = eq(_T_437, UInt<1>(0h0))
when _T_438 :
node _T_439 = eq(_T_436, UInt<1>(0h0))
when _T_439 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_436, UInt<1>(0h1), "") : assert_34
node _T_440 = not(mask)
node _T_441 = and(io.in.a.bits.mask, _T_440)
node _T_442 = eq(_T_441, UInt<1>(0h0))
node _T_443 = asUInt(reset)
node _T_444 = eq(_T_443, UInt<1>(0h0))
when _T_444 :
node _T_445 = eq(_T_442, UInt<1>(0h0))
when _T_445 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_442, UInt<1>(0h1), "") : assert_35
node _T_446 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_446 :
node _T_447 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_448 = and(UInt<1>(0h0), _T_447)
node _T_449 = or(UInt<1>(0h0), _T_448)
node _T_450 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_451 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_452 = cvt(_T_451)
node _T_453 = and(_T_452, asSInt(UInt<7>(0h40)))
node _T_454 = asSInt(_T_453)
node _T_455 = eq(_T_454, asSInt(UInt<1>(0h0)))
node _T_456 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_457 = cvt(_T_456)
node _T_458 = and(_T_457, asSInt(UInt<5>(0h14)))
node _T_459 = asSInt(_T_458)
node _T_460 = eq(_T_459, asSInt(UInt<1>(0h0)))
node _T_461 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_462 = cvt(_T_461)
node _T_463 = and(_T_462, asSInt(UInt<4>(0h8)))
node _T_464 = asSInt(_T_463)
node _T_465 = eq(_T_464, asSInt(UInt<1>(0h0)))
node _T_466 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_467 = cvt(_T_466)
node _T_468 = and(_T_467, asSInt(UInt<6>(0h20)))
node _T_469 = asSInt(_T_468)
node _T_470 = eq(_T_469, asSInt(UInt<1>(0h0)))
node _T_471 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_472 = cvt(_T_471)
node _T_473 = and(_T_472, asSInt(UInt<8>(0h80)))
node _T_474 = asSInt(_T_473)
node _T_475 = eq(_T_474, asSInt(UInt<1>(0h0)))
node _T_476 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_477 = cvt(_T_476)
node _T_478 = and(_T_477, asSInt(UInt<9>(0h100)))
node _T_479 = asSInt(_T_478)
node _T_480 = eq(_T_479, asSInt(UInt<1>(0h0)))
node _T_481 = or(_T_455, _T_460)
node _T_482 = or(_T_481, _T_465)
node _T_483 = or(_T_482, _T_470)
node _T_484 = or(_T_483, _T_475)
node _T_485 = or(_T_484, _T_480)
node _T_486 = and(_T_450, _T_485)
node _T_487 = or(UInt<1>(0h0), _T_486)
node _T_488 = and(_T_449, _T_487)
node _T_489 = asUInt(reset)
node _T_490 = eq(_T_489, UInt<1>(0h0))
when _T_490 :
node _T_491 = eq(_T_488, UInt<1>(0h0))
when _T_491 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_488, UInt<1>(0h1), "") : assert_36
node _T_492 = asUInt(reset)
node _T_493 = eq(_T_492, UInt<1>(0h0))
when _T_493 :
node _T_494 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_495 = asUInt(reset)
node _T_496 = eq(_T_495, UInt<1>(0h0))
when _T_496 :
node _T_497 = eq(is_aligned, UInt<1>(0h0))
when _T_497 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_498 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_499 = asUInt(reset)
node _T_500 = eq(_T_499, UInt<1>(0h0))
when _T_500 :
node _T_501 = eq(_T_498, UInt<1>(0h0))
when _T_501 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_498, UInt<1>(0h1), "") : assert_39
node _T_502 = eq(io.in.a.bits.mask, mask)
node _T_503 = asUInt(reset)
node _T_504 = eq(_T_503, UInt<1>(0h0))
when _T_504 :
node _T_505 = eq(_T_502, UInt<1>(0h0))
when _T_505 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_502, UInt<1>(0h1), "") : assert_40
node _T_506 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_506 :
node _T_507 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_508 = and(UInt<1>(0h0), _T_507)
node _T_509 = or(UInt<1>(0h0), _T_508)
node _T_510 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_511 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_512 = cvt(_T_511)
node _T_513 = and(_T_512, asSInt(UInt<7>(0h40)))
node _T_514 = asSInt(_T_513)
node _T_515 = eq(_T_514, asSInt(UInt<1>(0h0)))
node _T_516 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_517 = cvt(_T_516)
node _T_518 = and(_T_517, asSInt(UInt<5>(0h14)))
node _T_519 = asSInt(_T_518)
node _T_520 = eq(_T_519, asSInt(UInt<1>(0h0)))
node _T_521 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_522 = cvt(_T_521)
node _T_523 = and(_T_522, asSInt(UInt<4>(0h8)))
node _T_524 = asSInt(_T_523)
node _T_525 = eq(_T_524, asSInt(UInt<1>(0h0)))
node _T_526 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_527 = cvt(_T_526)
node _T_528 = and(_T_527, asSInt(UInt<6>(0h20)))
node _T_529 = asSInt(_T_528)
node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0)))
node _T_531 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_532 = cvt(_T_531)
node _T_533 = and(_T_532, asSInt(UInt<8>(0h80)))
node _T_534 = asSInt(_T_533)
node _T_535 = eq(_T_534, asSInt(UInt<1>(0h0)))
node _T_536 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_537 = cvt(_T_536)
node _T_538 = and(_T_537, asSInt(UInt<9>(0h100)))
node _T_539 = asSInt(_T_538)
node _T_540 = eq(_T_539, asSInt(UInt<1>(0h0)))
node _T_541 = or(_T_515, _T_520)
node _T_542 = or(_T_541, _T_525)
node _T_543 = or(_T_542, _T_530)
node _T_544 = or(_T_543, _T_535)
node _T_545 = or(_T_544, _T_540)
node _T_546 = and(_T_510, _T_545)
node _T_547 = or(UInt<1>(0h0), _T_546)
node _T_548 = and(_T_509, _T_547)
node _T_549 = asUInt(reset)
node _T_550 = eq(_T_549, UInt<1>(0h0))
when _T_550 :
node _T_551 = eq(_T_548, UInt<1>(0h0))
when _T_551 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_548, UInt<1>(0h1), "") : assert_41
node _T_552 = asUInt(reset)
node _T_553 = eq(_T_552, UInt<1>(0h0))
when _T_553 :
node _T_554 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_554 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_555 = asUInt(reset)
node _T_556 = eq(_T_555, UInt<1>(0h0))
when _T_556 :
node _T_557 = eq(is_aligned, UInt<1>(0h0))
when _T_557 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_558 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_559 = asUInt(reset)
node _T_560 = eq(_T_559, UInt<1>(0h0))
when _T_560 :
node _T_561 = eq(_T_558, UInt<1>(0h0))
when _T_561 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_558, UInt<1>(0h1), "") : assert_44
node _T_562 = eq(io.in.a.bits.mask, mask)
node _T_563 = asUInt(reset)
node _T_564 = eq(_T_563, UInt<1>(0h0))
when _T_564 :
node _T_565 = eq(_T_562, UInt<1>(0h0))
when _T_565 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_562, UInt<1>(0h1), "") : assert_45
node _T_566 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_566 :
node _T_567 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_568 = and(UInt<1>(0h0), _T_567)
node _T_569 = or(UInt<1>(0h0), _T_568)
node _T_570 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_571 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_572 = cvt(_T_571)
node _T_573 = and(_T_572, asSInt(UInt<7>(0h40)))
node _T_574 = asSInt(_T_573)
node _T_575 = eq(_T_574, asSInt(UInt<1>(0h0)))
node _T_576 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_577 = cvt(_T_576)
node _T_578 = and(_T_577, asSInt(UInt<5>(0h14)))
node _T_579 = asSInt(_T_578)
node _T_580 = eq(_T_579, asSInt(UInt<1>(0h0)))
node _T_581 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_582 = cvt(_T_581)
node _T_583 = and(_T_582, asSInt(UInt<4>(0h8)))
node _T_584 = asSInt(_T_583)
node _T_585 = eq(_T_584, asSInt(UInt<1>(0h0)))
node _T_586 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_587 = cvt(_T_586)
node _T_588 = and(_T_587, asSInt(UInt<6>(0h20)))
node _T_589 = asSInt(_T_588)
node _T_590 = eq(_T_589, asSInt(UInt<1>(0h0)))
node _T_591 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_592 = cvt(_T_591)
node _T_593 = and(_T_592, asSInt(UInt<8>(0h80)))
node _T_594 = asSInt(_T_593)
node _T_595 = eq(_T_594, asSInt(UInt<1>(0h0)))
node _T_596 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_597 = cvt(_T_596)
node _T_598 = and(_T_597, asSInt(UInt<9>(0h100)))
node _T_599 = asSInt(_T_598)
node _T_600 = eq(_T_599, asSInt(UInt<1>(0h0)))
node _T_601 = or(_T_575, _T_580)
node _T_602 = or(_T_601, _T_585)
node _T_603 = or(_T_602, _T_590)
node _T_604 = or(_T_603, _T_595)
node _T_605 = or(_T_604, _T_600)
node _T_606 = and(_T_570, _T_605)
node _T_607 = or(UInt<1>(0h0), _T_606)
node _T_608 = and(_T_569, _T_607)
node _T_609 = asUInt(reset)
node _T_610 = eq(_T_609, UInt<1>(0h0))
when _T_610 :
node _T_611 = eq(_T_608, UInt<1>(0h0))
when _T_611 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_608, UInt<1>(0h1), "") : assert_46
node _T_612 = asUInt(reset)
node _T_613 = eq(_T_612, UInt<1>(0h0))
when _T_613 :
node _T_614 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_614 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_615 = asUInt(reset)
node _T_616 = eq(_T_615, UInt<1>(0h0))
when _T_616 :
node _T_617 = eq(is_aligned, UInt<1>(0h0))
when _T_617 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_618 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_619 = asUInt(reset)
node _T_620 = eq(_T_619, UInt<1>(0h0))
when _T_620 :
node _T_621 = eq(_T_618, UInt<1>(0h0))
when _T_621 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_618, UInt<1>(0h1), "") : assert_49
node _T_622 = eq(io.in.a.bits.mask, mask)
node _T_623 = asUInt(reset)
node _T_624 = eq(_T_623, UInt<1>(0h0))
when _T_624 :
node _T_625 = eq(_T_622, UInt<1>(0h0))
when _T_625 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_622, UInt<1>(0h1), "") : assert_50
node _T_626 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_627 = asUInt(reset)
node _T_628 = eq(_T_627, UInt<1>(0h0))
when _T_628 :
node _T_629 = eq(_T_626, UInt<1>(0h0))
when _T_629 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_626, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_630 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_631 = asUInt(reset)
node _T_632 = eq(_T_631, UInt<1>(0h0))
when _T_632 :
node _T_633 = eq(_T_630, UInt<1>(0h0))
when _T_633 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_630, UInt<1>(0h1), "") : assert_52
node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_1
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_634 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_634 :
node _T_635 = asUInt(reset)
node _T_636 = eq(_T_635, UInt<1>(0h0))
when _T_636 :
node _T_637 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_637 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_638 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_639 = asUInt(reset)
node _T_640 = eq(_T_639, UInt<1>(0h0))
when _T_640 :
node _T_641 = eq(_T_638, UInt<1>(0h0))
when _T_641 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_638, UInt<1>(0h1), "") : assert_54
node _T_642 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_643 = asUInt(reset)
node _T_644 = eq(_T_643, UInt<1>(0h0))
when _T_644 :
node _T_645 = eq(_T_642, UInt<1>(0h0))
when _T_645 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_642, UInt<1>(0h1), "") : assert_55
node _T_646 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_647 = asUInt(reset)
node _T_648 = eq(_T_647, UInt<1>(0h0))
when _T_648 :
node _T_649 = eq(_T_646, UInt<1>(0h0))
when _T_649 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_646, UInt<1>(0h1), "") : assert_56
node _T_650 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_651 = asUInt(reset)
node _T_652 = eq(_T_651, UInt<1>(0h0))
when _T_652 :
node _T_653 = eq(_T_650, UInt<1>(0h0))
when _T_653 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_650, UInt<1>(0h1), "") : assert_57
node _T_654 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_654 :
node _T_655 = asUInt(reset)
node _T_656 = eq(_T_655, UInt<1>(0h0))
when _T_656 :
node _T_657 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_657 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_658 = asUInt(reset)
node _T_659 = eq(_T_658, UInt<1>(0h0))
when _T_659 :
node _T_660 = eq(sink_ok, UInt<1>(0h0))
when _T_660 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_661 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_662 = asUInt(reset)
node _T_663 = eq(_T_662, UInt<1>(0h0))
when _T_663 :
node _T_664 = eq(_T_661, UInt<1>(0h0))
when _T_664 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_661, UInt<1>(0h1), "") : assert_60
node _T_665 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_666 = asUInt(reset)
node _T_667 = eq(_T_666, UInt<1>(0h0))
when _T_667 :
node _T_668 = eq(_T_665, UInt<1>(0h0))
when _T_668 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_665, UInt<1>(0h1), "") : assert_61
node _T_669 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_670 = asUInt(reset)
node _T_671 = eq(_T_670, UInt<1>(0h0))
when _T_671 :
node _T_672 = eq(_T_669, UInt<1>(0h0))
when _T_672 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_669, UInt<1>(0h1), "") : assert_62
node _T_673 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_674 = asUInt(reset)
node _T_675 = eq(_T_674, UInt<1>(0h0))
when _T_675 :
node _T_676 = eq(_T_673, UInt<1>(0h0))
when _T_676 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_673, UInt<1>(0h1), "") : assert_63
node _T_677 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_678 = or(UInt<1>(0h0), _T_677)
node _T_679 = asUInt(reset)
node _T_680 = eq(_T_679, UInt<1>(0h0))
when _T_680 :
node _T_681 = eq(_T_678, UInt<1>(0h0))
when _T_681 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_678, UInt<1>(0h1), "") : assert_64
node _T_682 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_682 :
node _T_683 = asUInt(reset)
node _T_684 = eq(_T_683, UInt<1>(0h0))
when _T_684 :
node _T_685 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_685 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_686 = asUInt(reset)
node _T_687 = eq(_T_686, UInt<1>(0h0))
when _T_687 :
node _T_688 = eq(sink_ok, UInt<1>(0h0))
when _T_688 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_689 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_690 = asUInt(reset)
node _T_691 = eq(_T_690, UInt<1>(0h0))
when _T_691 :
node _T_692 = eq(_T_689, UInt<1>(0h0))
when _T_692 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_689, UInt<1>(0h1), "") : assert_67
node _T_693 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_694 = asUInt(reset)
node _T_695 = eq(_T_694, UInt<1>(0h0))
when _T_695 :
node _T_696 = eq(_T_693, UInt<1>(0h0))
when _T_696 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_693, UInt<1>(0h1), "") : assert_68
node _T_697 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_698 = asUInt(reset)
node _T_699 = eq(_T_698, UInt<1>(0h0))
when _T_699 :
node _T_700 = eq(_T_697, UInt<1>(0h0))
when _T_700 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_697, UInt<1>(0h1), "") : assert_69
node _T_701 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_702 = or(_T_701, io.in.d.bits.corrupt)
node _T_703 = asUInt(reset)
node _T_704 = eq(_T_703, UInt<1>(0h0))
when _T_704 :
node _T_705 = eq(_T_702, UInt<1>(0h0))
when _T_705 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_702, UInt<1>(0h1), "") : assert_70
node _T_706 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_707 = or(UInt<1>(0h0), _T_706)
node _T_708 = asUInt(reset)
node _T_709 = eq(_T_708, UInt<1>(0h0))
when _T_709 :
node _T_710 = eq(_T_707, UInt<1>(0h0))
when _T_710 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_707, UInt<1>(0h1), "") : assert_71
node _T_711 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_711 :
node _T_712 = asUInt(reset)
node _T_713 = eq(_T_712, UInt<1>(0h0))
when _T_713 :
node _T_714 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_714 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_715 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_716 = asUInt(reset)
node _T_717 = eq(_T_716, UInt<1>(0h0))
when _T_717 :
node _T_718 = eq(_T_715, UInt<1>(0h0))
when _T_718 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_715, UInt<1>(0h1), "") : assert_73
node _T_719 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_720 = asUInt(reset)
node _T_721 = eq(_T_720, UInt<1>(0h0))
when _T_721 :
node _T_722 = eq(_T_719, UInt<1>(0h0))
when _T_722 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_719, UInt<1>(0h1), "") : assert_74
node _T_723 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_724 = or(UInt<1>(0h0), _T_723)
node _T_725 = asUInt(reset)
node _T_726 = eq(_T_725, UInt<1>(0h0))
when _T_726 :
node _T_727 = eq(_T_724, UInt<1>(0h0))
when _T_727 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_724, UInt<1>(0h1), "") : assert_75
node _T_728 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_728 :
node _T_729 = asUInt(reset)
node _T_730 = eq(_T_729, UInt<1>(0h0))
when _T_730 :
node _T_731 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_731 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_732 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_733 = asUInt(reset)
node _T_734 = eq(_T_733, UInt<1>(0h0))
when _T_734 :
node _T_735 = eq(_T_732, UInt<1>(0h0))
when _T_735 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_732, UInt<1>(0h1), "") : assert_77
node _T_736 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_737 = or(_T_736, io.in.d.bits.corrupt)
node _T_738 = asUInt(reset)
node _T_739 = eq(_T_738, UInt<1>(0h0))
when _T_739 :
node _T_740 = eq(_T_737, UInt<1>(0h0))
when _T_740 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_737, UInt<1>(0h1), "") : assert_78
node _T_741 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_742 = or(UInt<1>(0h0), _T_741)
node _T_743 = asUInt(reset)
node _T_744 = eq(_T_743, UInt<1>(0h0))
when _T_744 :
node _T_745 = eq(_T_742, UInt<1>(0h0))
when _T_745 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_742, UInt<1>(0h1), "") : assert_79
node _T_746 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_746 :
node _T_747 = asUInt(reset)
node _T_748 = eq(_T_747, UInt<1>(0h0))
when _T_748 :
node _T_749 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_749 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_750 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_751 = asUInt(reset)
node _T_752 = eq(_T_751, UInt<1>(0h0))
when _T_752 :
node _T_753 = eq(_T_750, UInt<1>(0h0))
when _T_753 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_750, UInt<1>(0h1), "") : assert_81
node _T_754 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_755 = asUInt(reset)
node _T_756 = eq(_T_755, UInt<1>(0h0))
when _T_756 :
node _T_757 = eq(_T_754, UInt<1>(0h0))
when _T_757 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_754, UInt<1>(0h1), "") : assert_82
node _T_758 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_759 = or(UInt<1>(0h0), _T_758)
node _T_760 = asUInt(reset)
node _T_761 = eq(_T_760, UInt<1>(0h0))
when _T_761 :
node _T_762 = eq(_T_759, UInt<1>(0h0))
when _T_762 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_759, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<32>(0h0)
connect _WIRE.bits.mask, UInt<4>(0h0)
connect _WIRE.bits.address, UInt<9>(0h0)
connect _WIRE.bits.source, UInt<1>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_763 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_764 = asUInt(reset)
node _T_765 = eq(_T_764, UInt<1>(0h0))
when _T_765 :
node _T_766 = eq(_T_763, UInt<1>(0h0))
when _T_766 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_763, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<32>(0h0)
connect _WIRE_2.bits.address, UInt<9>(0h0)
connect _WIRE_2.bits.source, UInt<1>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_767 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_768 = asUInt(reset)
node _T_769 = eq(_T_768, UInt<1>(0h0))
when _T_769 :
node _T_770 = eq(_T_767, UInt<1>(0h0))
when _T_770 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_767, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_771 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_772 = asUInt(reset)
node _T_773 = eq(_T_772, UInt<1>(0h0))
when _T_773 :
node _T_774 = eq(_T_771, UInt<1>(0h0))
when _T_774 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_771, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 1, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 2)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_775 = eq(a_first, UInt<1>(0h0))
node _T_776 = and(io.in.a.valid, _T_775)
when _T_776 :
node _T_777 = eq(io.in.a.bits.opcode, opcode)
node _T_778 = asUInt(reset)
node _T_779 = eq(_T_778, UInt<1>(0h0))
when _T_779 :
node _T_780 = eq(_T_777, UInt<1>(0h0))
when _T_780 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_777, UInt<1>(0h1), "") : assert_87
node _T_781 = eq(io.in.a.bits.param, param)
node _T_782 = asUInt(reset)
node _T_783 = eq(_T_782, UInt<1>(0h0))
when _T_783 :
node _T_784 = eq(_T_781, UInt<1>(0h0))
when _T_784 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_781, UInt<1>(0h1), "") : assert_88
node _T_785 = eq(io.in.a.bits.size, size)
node _T_786 = asUInt(reset)
node _T_787 = eq(_T_786, UInt<1>(0h0))
when _T_787 :
node _T_788 = eq(_T_785, UInt<1>(0h0))
when _T_788 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_785, UInt<1>(0h1), "") : assert_89
node _T_789 = eq(io.in.a.bits.source, source)
node _T_790 = asUInt(reset)
node _T_791 = eq(_T_790, UInt<1>(0h0))
when _T_791 :
node _T_792 = eq(_T_789, UInt<1>(0h0))
when _T_792 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_789, UInt<1>(0h1), "") : assert_90
node _T_793 = eq(io.in.a.bits.address, address)
node _T_794 = asUInt(reset)
node _T_795 = eq(_T_794, UInt<1>(0h0))
when _T_795 :
node _T_796 = eq(_T_793, UInt<1>(0h0))
when _T_796 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_793, UInt<1>(0h1), "") : assert_91
node _T_797 = and(io.in.a.ready, io.in.a.valid)
node _T_798 = and(_T_797, a_first)
when _T_798 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 1, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 2)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_799 = eq(d_first, UInt<1>(0h0))
node _T_800 = and(io.in.d.valid, _T_799)
when _T_800 :
node _T_801 = eq(io.in.d.bits.opcode, opcode_1)
node _T_802 = asUInt(reset)
node _T_803 = eq(_T_802, UInt<1>(0h0))
when _T_803 :
node _T_804 = eq(_T_801, UInt<1>(0h0))
when _T_804 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_801, UInt<1>(0h1), "") : assert_92
node _T_805 = eq(io.in.d.bits.param, param_1)
node _T_806 = asUInt(reset)
node _T_807 = eq(_T_806, UInt<1>(0h0))
when _T_807 :
node _T_808 = eq(_T_805, UInt<1>(0h0))
when _T_808 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_805, UInt<1>(0h1), "") : assert_93
node _T_809 = eq(io.in.d.bits.size, size_1)
node _T_810 = asUInt(reset)
node _T_811 = eq(_T_810, UInt<1>(0h0))
when _T_811 :
node _T_812 = eq(_T_809, UInt<1>(0h0))
when _T_812 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_809, UInt<1>(0h1), "") : assert_94
node _T_813 = eq(io.in.d.bits.source, source_1)
node _T_814 = asUInt(reset)
node _T_815 = eq(_T_814, UInt<1>(0h0))
when _T_815 :
node _T_816 = eq(_T_813, UInt<1>(0h0))
when _T_816 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_813, UInt<1>(0h1), "") : assert_95
node _T_817 = eq(io.in.d.bits.sink, sink)
node _T_818 = asUInt(reset)
node _T_819 = eq(_T_818, UInt<1>(0h0))
when _T_819 :
node _T_820 = eq(_T_817, UInt<1>(0h0))
when _T_820 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_817, UInt<1>(0h1), "") : assert_96
node _T_821 = eq(io.in.d.bits.denied, denied)
node _T_822 = asUInt(reset)
node _T_823 = eq(_T_822, UInt<1>(0h0))
when _T_823 :
node _T_824 = eq(_T_821, UInt<1>(0h0))
when _T_824 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_821, UInt<1>(0h1), "") : assert_97
node _T_825 = and(io.in.d.ready, io.in.d.valid)
node _T_826 = and(_T_825, d_first)
when _T_826 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes : UInt<4>, clock, reset, UInt<4>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 1, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 2)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 1, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 2)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<1>
connect a_set, UInt<1>(0h0)
wire a_set_wo_ready : UInt<1>
connect a_set_wo_ready, UInt<1>(0h0)
wire a_opcodes_set : UInt<4>
connect a_opcodes_set, UInt<4>(0h0)
wire a_sizes_set : UInt<4>
connect a_sizes_set, UInt<4>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<3>
connect a_sizes_set_interm, UInt<3>(0h0)
node _T_827 = and(io.in.a.valid, a_first_1)
node _T_828 = and(_T_827, UInt<1>(0h1))
when _T_828 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_829 = and(io.in.a.ready, io.in.a.valid)
node _T_830 = and(_T_829, a_first_1)
node _T_831 = and(_T_830, UInt<1>(0h1))
when _T_831 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_832 = dshr(inflight, io.in.a.bits.source)
node _T_833 = bits(_T_832, 0, 0)
node _T_834 = eq(_T_833, UInt<1>(0h0))
node _T_835 = asUInt(reset)
node _T_836 = eq(_T_835, UInt<1>(0h0))
when _T_836 :
node _T_837 = eq(_T_834, UInt<1>(0h0))
when _T_837 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_834, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<1>
connect d_clr, UInt<1>(0h0)
wire d_clr_wo_ready : UInt<1>
connect d_clr_wo_ready, UInt<1>(0h0)
wire d_opcodes_clr : UInt<4>
connect d_opcodes_clr, UInt<4>(0h0)
wire d_sizes_clr : UInt<4>
connect d_sizes_clr, UInt<4>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_838 = and(io.in.d.valid, d_first_1)
node _T_839 = and(_T_838, UInt<1>(0h1))
node _T_840 = eq(d_release_ack, UInt<1>(0h0))
node _T_841 = and(_T_839, _T_840)
when _T_841 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_842 = and(io.in.d.ready, io.in.d.valid)
node _T_843 = and(_T_842, d_first_1)
node _T_844 = and(_T_843, UInt<1>(0h1))
node _T_845 = eq(d_release_ack, UInt<1>(0h0))
node _T_846 = and(_T_844, _T_845)
when _T_846 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_847 = and(io.in.d.valid, d_first_1)
node _T_848 = and(_T_847, UInt<1>(0h1))
node _T_849 = eq(d_release_ack, UInt<1>(0h0))
node _T_850 = and(_T_848, _T_849)
when _T_850 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_851 = dshr(inflight, io.in.d.bits.source)
node _T_852 = bits(_T_851, 0, 0)
node _T_853 = or(_T_852, same_cycle_resp)
node _T_854 = asUInt(reset)
node _T_855 = eq(_T_854, UInt<1>(0h0))
when _T_855 :
node _T_856 = eq(_T_853, UInt<1>(0h0))
when _T_856 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_853, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_857 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_858 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_859 = or(_T_857, _T_858)
node _T_860 = asUInt(reset)
node _T_861 = eq(_T_860, UInt<1>(0h0))
when _T_861 :
node _T_862 = eq(_T_859, UInt<1>(0h0))
when _T_862 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_859, UInt<1>(0h1), "") : assert_100
node _T_863 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_864 = asUInt(reset)
node _T_865 = eq(_T_864, UInt<1>(0h0))
when _T_865 :
node _T_866 = eq(_T_863, UInt<1>(0h0))
when _T_866 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_863, UInt<1>(0h1), "") : assert_101
else :
node _T_867 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_868 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_869 = or(_T_867, _T_868)
node _T_870 = asUInt(reset)
node _T_871 = eq(_T_870, UInt<1>(0h0))
when _T_871 :
node _T_872 = eq(_T_869, UInt<1>(0h0))
when _T_872 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_869, UInt<1>(0h1), "") : assert_102
node _T_873 = eq(io.in.d.bits.size, a_size_lookup)
node _T_874 = asUInt(reset)
node _T_875 = eq(_T_874, UInt<1>(0h0))
when _T_875 :
node _T_876 = eq(_T_873, UInt<1>(0h0))
when _T_876 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_873, UInt<1>(0h1), "") : assert_103
node _T_877 = and(io.in.d.valid, d_first_1)
node _T_878 = and(_T_877, a_first_1)
node _T_879 = and(_T_878, io.in.a.valid)
node _T_880 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_881 = and(_T_879, _T_880)
node _T_882 = eq(d_release_ack, UInt<1>(0h0))
node _T_883 = and(_T_881, _T_882)
when _T_883 :
node _T_884 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_885 = or(_T_884, io.in.a.ready)
node _T_886 = asUInt(reset)
node _T_887 = eq(_T_886, UInt<1>(0h0))
when _T_887 :
node _T_888 = eq(_T_885, UInt<1>(0h0))
when _T_888 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_885, UInt<1>(0h1), "") : assert_104
node _T_889 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_890 = orr(a_set_wo_ready)
node _T_891 = eq(_T_890, UInt<1>(0h0))
node _T_892 = or(_T_889, _T_891)
node _T_893 = asUInt(reset)
node _T_894 = eq(_T_893, UInt<1>(0h0))
when _T_894 :
node _T_895 = eq(_T_892, UInt<1>(0h0))
when _T_895 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_892, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_185
node _T_896 = orr(inflight)
node _T_897 = eq(_T_896, UInt<1>(0h0))
node _T_898 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_899 = or(_T_897, _T_898)
node _T_900 = lt(watchdog, plusarg_reader.out)
node _T_901 = or(_T_899, _T_900)
node _T_902 = asUInt(reset)
node _T_903 = eq(_T_902, UInt<1>(0h0))
when _T_903 :
node _T_904 = eq(_T_901, UInt<1>(0h0))
when _T_904 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_901, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_905 = and(io.in.a.ready, io.in.a.valid)
node _T_906 = and(io.in.d.ready, io.in.d.valid)
node _T_907 = or(_T_905, _T_906)
when _T_907 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes_1 : UInt<4>, clock, reset, UInt<4>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<32>(0h0)
connect _c_first_WIRE.bits.address, UInt<9>(0h0)
connect _c_first_WIRE.bits.source, UInt<1>(0h0)
connect _c_first_WIRE.bits.size, UInt<2>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<9>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<2>(0h3), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 1, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 2)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<2>(0h3), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 1, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 2)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<1>
connect c_set, UInt<1>(0h0)
wire c_set_wo_ready : UInt<1>
connect c_set_wo_ready, UInt<1>(0h0)
wire c_opcodes_set : UInt<4>
connect c_opcodes_set, UInt<4>(0h0)
wire c_sizes_set : UInt<4>
connect c_sizes_set, UInt<4>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<3>
connect c_sizes_set_interm, UInt<3>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<32>(0h0)
connect _WIRE_6.bits.address, UInt<9>(0h0)
connect _WIRE_6.bits.source, UInt<1>(0h0)
connect _WIRE_6.bits.size, UInt<2>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_908 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<32>(0h0)
connect _WIRE_8.bits.address, UInt<9>(0h0)
connect _WIRE_8.bits.source, UInt<1>(0h0)
connect _WIRE_8.bits.size, UInt<2>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_909 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_910 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_911 = and(_T_909, _T_910)
node _T_912 = and(_T_908, _T_911)
when _T_912 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<9>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<32>(0h0)
connect _WIRE_10.bits.address, UInt<9>(0h0)
connect _WIRE_10.bits.source, UInt<1>(0h0)
connect _WIRE_10.bits.size, UInt<2>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_913 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_914 = and(_T_913, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<32>(0h0)
connect _WIRE_12.bits.address, UInt<9>(0h0)
connect _WIRE_12.bits.source, UInt<1>(0h0)
connect _WIRE_12.bits.size, UInt<2>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_915 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_916 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_917 = and(_T_915, _T_916)
node _T_918 = and(_T_914, _T_917)
when _T_918 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_set_WIRE.bits.address, UInt<9>(0h0)
connect _c_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<9>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<9>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<9>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<9>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<32>(0h0)
connect _WIRE_14.bits.address, UInt<9>(0h0)
connect _WIRE_14.bits.source, UInt<1>(0h0)
connect _WIRE_14.bits.size, UInt<2>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_919 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_920 = bits(_T_919, 0, 0)
node _T_921 = eq(_T_920, UInt<1>(0h0))
node _T_922 = asUInt(reset)
node _T_923 = eq(_T_922, UInt<1>(0h0))
when _T_923 :
node _T_924 = eq(_T_921, UInt<1>(0h0))
when _T_924 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_921, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<9>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<9>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<1>
connect d_clr_1, UInt<1>(0h0)
wire d_clr_wo_ready_1 : UInt<1>
connect d_clr_wo_ready_1, UInt<1>(0h0)
wire d_opcodes_clr_1 : UInt<4>
connect d_opcodes_clr_1, UInt<4>(0h0)
wire d_sizes_clr_1 : UInt<4>
connect d_sizes_clr_1, UInt<4>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_925 = and(io.in.d.valid, d_first_2)
node _T_926 = and(_T_925, UInt<1>(0h1))
node _T_927 = and(_T_926, d_release_ack_1)
when _T_927 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_928 = and(io.in.d.ready, io.in.d.valid)
node _T_929 = and(_T_928, d_first_2)
node _T_930 = and(_T_929, UInt<1>(0h1))
node _T_931 = and(_T_930, d_release_ack_1)
when _T_931 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_932 = and(io.in.d.valid, d_first_2)
node _T_933 = and(_T_932, UInt<1>(0h1))
node _T_934 = and(_T_933, d_release_ack_1)
when _T_934 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<9>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<9>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<9>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_935 = dshr(inflight_1, io.in.d.bits.source)
node _T_936 = bits(_T_935, 0, 0)
node _T_937 = or(_T_936, same_cycle_resp_1)
node _T_938 = asUInt(reset)
node _T_939 = eq(_T_938, UInt<1>(0h0))
when _T_939 :
node _T_940 = eq(_T_937, UInt<1>(0h0))
when _T_940 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_937, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<32>(0h0)
connect _WIRE_16.bits.address, UInt<9>(0h0)
connect _WIRE_16.bits.source, UInt<1>(0h0)
connect _WIRE_16.bits.size, UInt<2>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_941 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_942 = asUInt(reset)
node _T_943 = eq(_T_942, UInt<1>(0h0))
when _T_943 :
node _T_944 = eq(_T_941, UInt<1>(0h0))
when _T_944 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_941, UInt<1>(0h1), "") : assert_109
else :
node _T_945 = eq(io.in.d.bits.size, c_size_lookup)
node _T_946 = asUInt(reset)
node _T_947 = eq(_T_946, UInt<1>(0h0))
when _T_947 :
node _T_948 = eq(_T_945, UInt<1>(0h0))
when _T_948 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_945, UInt<1>(0h1), "") : assert_110
node _T_949 = and(io.in.d.valid, d_first_2)
node _T_950 = and(_T_949, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<32>(0h0)
connect _WIRE_18.bits.address, UInt<9>(0h0)
connect _WIRE_18.bits.source, UInt<1>(0h0)
connect _WIRE_18.bits.size, UInt<2>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_951 = and(_T_950, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<32>(0h0)
connect _WIRE_20.bits.address, UInt<9>(0h0)
connect _WIRE_20.bits.source, UInt<1>(0h0)
connect _WIRE_20.bits.size, UInt<2>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_952 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_953 = and(_T_951, _T_952)
node _T_954 = and(_T_953, d_release_ack_1)
node _T_955 = eq(c_probe_ack, UInt<1>(0h0))
node _T_956 = and(_T_954, _T_955)
when _T_956 :
node _T_957 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<32>(0h0)
connect _WIRE_22.bits.address, UInt<9>(0h0)
connect _WIRE_22.bits.source, UInt<1>(0h0)
connect _WIRE_22.bits.size, UInt<2>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_958 = or(_T_957, _WIRE_23.ready)
node _T_959 = asUInt(reset)
node _T_960 = eq(_T_959, UInt<1>(0h0))
when _T_960 :
node _T_961 = eq(_T_958, UInt<1>(0h0))
when _T_961 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_958, UInt<1>(0h1), "") : assert_111
node _T_962 = orr(c_set_wo_ready)
when _T_962 :
node _T_963 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_964 = asUInt(reset)
node _T_965 = eq(_T_964, UInt<1>(0h0))
when _T_965 :
node _T_966 = eq(_T_963, UInt<1>(0h0))
when _T_966 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_963, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_186
node _T_967 = orr(inflight_1)
node _T_968 = eq(_T_967, UInt<1>(0h0))
node _T_969 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_970 = or(_T_968, _T_969)
node _T_971 = lt(watchdog_1, plusarg_reader_1.out)
node _T_972 = or(_T_970, _T_971)
node _T_973 = asUInt(reset)
node _T_974 = eq(_T_973, UInt<1>(0h0))
when _T_974 :
node _T_975 = eq(_T_972, UInt<1>(0h0))
when _T_975 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_972, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<32>(0h0)
connect _WIRE_24.bits.address, UInt<9>(0h0)
connect _WIRE_24.bits.source, UInt<1>(0h0)
connect _WIRE_24.bits.size, UInt<2>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_976 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_977 = and(io.in.d.ready, io.in.d.valid)
node _T_978 = or(_T_976, _T_977)
when _T_978 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_92( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [8:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [31:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [8:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [31:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire mask_sizeOH_shiftAmount = 1'h0; // @[OneHot.scala:64:49]
wire mask_sub_size = 1'h0; // @[Misc.scala:209:26]
wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count = 1'h0; // @[Edges.scala:234:25]
wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27]
wire c_first_count = 1'h0; // @[Edges.scala:234:25]
wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21]
wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25]
wire c_set = 1'h0; // @[Monitor.scala:738:34]
wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9]
wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31]
wire mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21]
wire mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_size = 1'h1; // @[Misc.scala:209:26]
wire mask_acc = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_2 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_3 = 1'h1; // @[Misc.scala:215:29]
wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last = 1'h1; // @[Edges.scala:232:33]
wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33]
wire [1:0] is_aligned_mask = 2'h3; // @[package.scala:243:46]
wire [1:0] mask_lo = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_hi = 2'h3; // @[Misc.scala:222:10]
wire [1:0] _a_first_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46]
wire [1:0] _a_first_beats1_decode_T_5 = 2'h3; // @[package.scala:243:46]
wire [1:0] _c_first_beats1_decode_T_1 = 2'h3; // @[package.scala:243:76]
wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28]
wire [1:0] io_in_a_bits_size = 2'h2; // @[Monitor.scala:36:7]
wire [1:0] _mask_sizeOH_T = 2'h2; // @[Misc.scala:202:34]
wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [3:0] io_in_a_bits_mask = 4'hF; // @[Monitor.scala:36:7]
wire [3:0] mask = 4'hF; // @[Misc.scala:222:10]
wire [31:0] _c_first_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_first_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_first_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_first_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_first_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_set_wo_ready_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_set_wo_ready_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_opcodes_set_interm_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_opcodes_set_interm_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_sizes_set_interm_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_sizes_set_interm_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_opcodes_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_opcodes_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_sizes_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_sizes_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_probe_ack_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_probe_ack_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_probe_ack_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_probe_ack_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _same_cycle_resp_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _same_cycle_resp_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _same_cycle_resp_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _same_cycle_resp_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _same_cycle_resp_WIRE_4_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _same_cycle_resp_WIRE_5_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [1:0] _is_aligned_mask_T_1 = 2'h0; // @[package.scala:243:76]
wire [1:0] _a_first_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76]
wire [1:0] _a_first_beats1_decode_T_4 = 2'h0; // @[package.scala:243:76]
wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_first_beats1_decode_T_2 = 2'h0; // @[package.scala:243:46]
wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [17:0] _c_sizes_set_T_1 = 18'h0; // @[Monitor.scala:768:52]
wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79]
wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77]
wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34]
wire [3:0] c_sizes_set = 4'h0; // @[Monitor.scala:741:34]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79]
wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77]
wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [1:0] _mask_sizeOH_T_1 = 2'h1; // @[OneHot.scala:65:12]
wire [1:0] _mask_sizeOH_T_2 = 2'h1; // @[OneHot.scala:65:27]
wire [1:0] mask_sizeOH = 2'h1; // @[Misc.scala:202:81]
wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35]
wire [4:0] _c_first_beats1_decode_T = 5'h3; // @[package.scala:243:71]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] _a_sizes_set_interm_T_1 = 3'h5; // @[Monitor.scala:658:59]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] _a_sizes_set_interm_T = 3'h4; // @[Monitor.scala:658:51]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [4:0] _is_aligned_mask_T = 5'hC; // @[package.scala:243:71]
wire [4:0] _a_first_beats1_decode_T = 5'hC; // @[package.scala:243:71]
wire [4:0] _a_first_beats1_decode_T_3 = 5'hC; // @[package.scala:243:71]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [8:0] _is_aligned_T = {7'h0, io_in_a_bits_address_0[1:0]}; // @[Monitor.scala:36:7]
wire is_aligned = _is_aligned_T == 9'h0; // @[Edges.scala:21:{16,24}]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_1_2 = mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38]
wire _source_ok_T_1 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_1; // @[Parameters.scala:1138:31]
wire _T_905 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_905; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_905; // @[Decoupled.scala:51:35]
wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
reg a_first_counter; // @[Edges.scala:229:27]
wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28]
wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [8:0] address; // @[Monitor.scala:391:22]
wire _T_978 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_978; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_978; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_978; // @[Decoupled.scala:51:35]
wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35]
wire [4:0] _GEN = 5'h3 << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [4:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [4:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [4:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN; // @[package.scala:243:71]
wire [1:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
reg d_first_counter; // @[Edges.scala:229:27]
wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28]
wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [1:0] inflight; // @[Monitor.scala:614:27]
reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [3:0] inflight_sizes; // @[Monitor.scala:618:33]
wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
reg a_first_counter_1; // @[Edges.scala:229:27]
wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35]
wire [1:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire a_set; // @[Monitor.scala:626:34]
wire a_set_wo_ready; // @[Monitor.scala:627:34]
wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [3:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [3:0] _GEN_0 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_0; // @[Monitor.scala:637:69]
wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_0; // @[Monitor.scala:637:69, :641:65]
wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_0; // @[Monitor.scala:637:69, :680:101]
wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_0; // @[Monitor.scala:637:69, :681:99]
wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_0; // @[Monitor.scala:637:69, :749:69]
wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_0; // @[Monitor.scala:637:69, :750:67]
wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_0; // @[Monitor.scala:637:69, :790:101]
wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_0; // @[Monitor.scala:637:69, :791:99]
wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}]
wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [3:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [15:0] _a_size_lookup_T_6 = {12'h0, _a_size_lookup_T_1}; // @[Monitor.scala:637:97, :641:{40,91}]
wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _T_828 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26]
assign a_set_wo_ready = _T_828; // @[Monitor.scala:627:34, :651:26]
wire _same_cycle_resp_T; // @[Monitor.scala:684:44]
assign _same_cycle_resp_T = _T_828; // @[Monitor.scala:651:26, :684:44]
assign a_set = _T_905 & a_first_1; // @[Decoupled.scala:51:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}]
assign a_sizes_set_interm = a_set ? 3'h5 : 3'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:28]
wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54]
assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}]
wire [17:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :659:54, :660:52]
assign a_sizes_set = a_set ? _a_sizes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}]
wire d_clr; // @[Monitor.scala:664:34]
wire d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [3:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_1 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_1; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_1; // @[Monitor.scala:673:46, :783:46]
wire _T_877 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [1:0] _GEN_2 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35]
wire [1:0] _GEN_3 = 2'h1 << _GEN_2; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_3; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_3; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_3; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_877 & ~d_release_ack & _d_clr_wo_ready_T[0]; // @[OneHot.scala:58:35]
wire _T_846 = _T_978 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_846 & _d_clr_T[0]; // @[OneHot.scala:58:35]
wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_846 ? _d_opcodes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [30:0] _d_sizes_clr_T_5 = 31'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_846 ? _d_sizes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27]
wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}]
wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [3:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [3:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [1:0] inflight_1; // @[Monitor.scala:726:35]
wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [3:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35]
wire [1:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
reg d_first_counter_2; // @[Edges.scala:229:27]
wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28]
wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:637:97, :749:{44,97}]
wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [3:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [15:0] _c_size_lookup_T_6 = {12'h0, _c_size_lookup_T_1}; // @[Monitor.scala:637:97, :750:{42,93}]
wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire d_clr_1; // @[Monitor.scala:774:34]
wire d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [3:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_949 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_949 & d_release_ack_1 & _d_clr_wo_ready_T_1[0]; // @[OneHot.scala:58:35]
wire _T_931 = _T_978 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_931 & _d_clr_T_1[0]; // @[OneHot.scala:58:35]
wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_931 ? _d_opcodes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [30:0] _d_sizes_clr_T_11 = 31'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_931 ? _d_sizes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113]
wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}]
wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [3:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [3:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie4_is8_oe8_os24_2 :
output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<6>, sig : UInt<9>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0))
node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1))
node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2))
node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3))
node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4))
node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6))
node _roundMagUp_T = and(roundingMode_min, io.in.sign)
node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0))
node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1)
node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2)
node _sAdjustedExp_T = add(io.in.sExp, asSInt(UInt<9>(0hf0)))
node _sAdjustedExp_T_1 = bits(_sAdjustedExp_T, 8, 0)
node sAdjustedExp = cvt(_sAdjustedExp_T_1)
node adjustedSig = shl(io.in.sig, 18)
wire common_expOut : UInt<9>
wire common_fractOut : UInt<23>
wire common_overflow : UInt<1>
wire common_totalUnderflow : UInt<1>
wire common_underflow : UInt<1>
wire common_inexact : UInt<1>
node _common_expOut_T = bits(sAdjustedExp, 8, 0)
node _common_expOut_T_1 = add(_common_expOut_T, UInt<1>(0h0))
node _common_expOut_T_2 = tail(_common_expOut_T_1, 1)
connect common_expOut, _common_expOut_T_2
node _common_fractOut_T = bits(adjustedSig, 25, 3)
node _common_fractOut_T_1 = bits(adjustedSig, 24, 2)
node _common_fractOut_T_2 = mux(UInt<1>(0h0), _common_fractOut_T, _common_fractOut_T_1)
connect common_fractOut, _common_fractOut_T_2
connect common_overflow, UInt<1>(0h0)
connect common_totalUnderflow, UInt<1>(0h0)
connect common_underflow, UInt<1>(0h0)
connect common_inexact, UInt<1>(0h0)
node isNaNOut = or(io.invalidExc, io.in.isNaN)
node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf)
node _commonCase_T = eq(isNaNOut, UInt<1>(0h0))
node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0))
node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1)
node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0))
node commonCase = and(_commonCase_T_2, _commonCase_T_3)
node overflow = and(commonCase, common_overflow)
node underflow = and(commonCase, common_underflow)
node _inexact_T = and(commonCase, common_inexact)
node inexact = or(overflow, _inexact_T)
node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp)
node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow)
node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd)
node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1)
node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0))
node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T)
node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp)
node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T)
node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign)
node _expOut_T = or(io.in.isZero, common_totalUnderflow)
node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0))
node _expOut_T_2 = not(_expOut_T_1)
node _expOut_T_3 = and(common_expOut, _expOut_T_2)
node _expOut_T_4 = not(UInt<9>(0h6b))
node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0))
node _expOut_T_6 = not(_expOut_T_5)
node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6)
node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0))
node _expOut_T_9 = not(_expOut_T_8)
node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9)
node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0))
node _expOut_T_12 = not(_expOut_T_11)
node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12)
node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0))
node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14)
node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0))
node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16)
node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0))
node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18)
node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0))
node expOut = or(_expOut_T_19, _expOut_T_20)
node _fractOut_T = or(isNaNOut, io.in.isZero)
node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow)
node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0))
node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut)
node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0))
node fractOut = or(_fractOut_T_3, _fractOut_T_4)
node _io_out_T = cat(signOut, expOut)
node _io_out_T_1 = cat(_io_out_T, fractOut)
connect io.out, _io_out_T_1
node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc)
node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow)
node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact)
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RoundAnyRawFNToRecFN_ie4_is8_oe8_os24_2( // @[RoundAnyRawFNToRecFN.scala:48:5]
input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [5:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [8:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [32:0] io_out // @[RoundAnyRawFNToRecFN.scala:58:16]
);
wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [5:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [8:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19]
wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14, :265:14]
wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14, :265:14]
wire [8:0] _expOut_T_12 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14, :265:14]
wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:257:18]
wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:261:18]
wire [8:0] _expOut_T_11 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:265:18]
wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:269:16]
wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:273:16]
wire [8:0] _expOut_T_18 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:277:16]
wire [8:0] _expOut_T_20 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:278:16]
wire [22:0] _fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:281:16, :284:13]
wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:281:16, :284:13]
wire [1:0] _io_exceptionFlags_T = 2'h0; // @[RoundAnyRawFNToRecFN.scala:288:23]
wire [3:0] _io_exceptionFlags_T_2 = 4'h0; // @[RoundAnyRawFNToRecFN.scala:288:53]
wire [4:0] io_exceptionFlags = 5'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:66]
wire [4:0] _io_exceptionFlags_T_3 = 5'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:66]
wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :237:{22,33,36}, :243:{32,60}]
wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :237:{22,33,36}, :243:{32,60}]
wire _commonCase_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :237:{22,33,36}, :243:{32,60}]
wire _commonCase_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :237:{22,33,36}, :243:{32,60}]
wire _commonCase_T_2 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :237:{22,33,36}, :243:{32,60}]
wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :237:{22,33,36}, :243:{32,60}]
wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :237:{22,33,36}, :243:{32,60}]
wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41]
wire [2:0] _io_exceptionFlags_T_1 = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41]
wire io_invalidExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isNaN = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isInf = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53]
wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53]
wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53]
wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53]
wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53]
wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27]
wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63]
wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42]
wire common_overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:124:37]
wire common_totalUnderflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:125:37]
wire common_underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:126:37]
wire common_inexact = 1'h0; // @[RoundAnyRawFNToRecFN.scala:127:37]
wire isNaNOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:235:34]
wire notNaN_isSpecialInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:236:49]
wire overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:238:32]
wire underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:239:32]
wire _inexact_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:240:43]
wire inexact = 1'h0; // @[RoundAnyRawFNToRecFN.scala:240:28]
wire _pegMinNonzeroMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:20]
wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60]
wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45]
wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42]
wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39]
wire _notNaN_isInfOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:45]
wire notNaN_isInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:32]
wire _expOut_T = io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :253:32]
wire _fractOut_T = io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :280:22]
wire signOut = io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :250:22]
wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33]
wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66]
wire [9:0] _sAdjustedExp_T = {{4{io_in_sExp_0[5]}}, io_in_sExp_0} + 10'hF0; // @[RoundAnyRawFNToRecFN.scala:48:5, :104:25]
wire [8:0] _sAdjustedExp_T_1 = _sAdjustedExp_T[8:0]; // @[RoundAnyRawFNToRecFN.scala:104:25, :106:14]
wire [9:0] sAdjustedExp = {1'h0, _sAdjustedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:106:{14,31}]
wire [26:0] adjustedSig = {io_in_sig_0, 18'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22]
wire [8:0] _common_expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:136:55]
wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31]
wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:138:16]
wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31]
wire [8:0] _common_expOut_T = sAdjustedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:106:31, :136:38]
wire [9:0] _common_expOut_T_1 = {1'h0, _common_expOut_T}; // @[RoundAnyRawFNToRecFN.scala:136:{38,55}]
assign _common_expOut_T_2 = _common_expOut_T_1[8:0]; // @[RoundAnyRawFNToRecFN.scala:136:55]
assign common_expOut = _common_expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :136:55]
wire [22:0] _common_fractOut_T = adjustedSig[25:3]; // @[RoundAnyRawFNToRecFN.scala:114:22, :139:28]
wire [22:0] _common_fractOut_T_1 = adjustedSig[24:2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :140:28]
assign _common_fractOut_T_2 = _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:138:16, :140:28]
assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16]
wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64]
wire commonCase = _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{61,64}]
wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}]
wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}]
wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14]
wire [8:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17]
wire [8:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17]
wire [8:0] _expOut_T_13 = _expOut_T_10; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17]
wire [8:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18]
wire [8:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15]
wire [8:0] _expOut_T_19 = _expOut_T_17; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15]
wire [8:0] expOut = _expOut_T_19; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73]
wire _fractOut_T_1 = _fractOut_T; // @[RoundAnyRawFNToRecFN.scala:280:{22,38}]
wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? 23'h0 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16, :284:13]
wire [22:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11]
wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23]
assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}]
assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33]
assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MSHR_6 :
input clock : Clock
input reset : Reset
output io : { flip allocate : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, repeat : UInt<1>}}, flip directory : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}}, status : { valid : UInt<1>, bits : { set : UInt<10>, tag : UInt<13>, way : UInt<3>, blockB : UInt<1>, nestB : UInt<1>, blockC : UInt<1>, nestC : UInt<1>}}, schedule : { flip ready : UInt<1>, valid : UInt<1>, bits : { a : { valid : UInt<1>, bits : { tag : UInt<13>, set : UInt<10>, param : UInt<3>, source : UInt<3>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<13>, set : UInt<10>, clients : UInt<1>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<3>, tag : UInt<13>, set : UInt<10>, way : UInt<3>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<10>, way : UInt<3>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>}}}, reload : UInt<1>}}, flip sinkc : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<10>, tag : UInt<13>, source : UInt<6>, param : UInt<3>, data : UInt<1>}}, flip sinkd : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>}}, flip sinke : { valid : UInt<1>, bits : { sink : UInt<3>}}, flip nestedwb : { set : UInt<10>, tag : UInt<13>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}}
regreset request_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg request : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>}, clock
regreset meta_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg meta : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}, clock
when meta_valid :
node _T = eq(meta.state, UInt<2>(0h0))
when _T :
node _T_1 = orr(meta.clients)
node _T_2 = eq(_T_1, UInt<1>(0h0))
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
node _T_5 = eq(_T_2, UInt<1>(0h0))
when _T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:105 assert (!meta.clients.orR)\n") : printf
assert(clock, _T_2, UInt<1>(0h1), "") : assert
node _T_6 = eq(meta.dirty, UInt<1>(0h0))
node _T_7 = asUInt(reset)
node _T_8 = eq(_T_7, UInt<1>(0h0))
when _T_8 :
node _T_9 = eq(_T_6, UInt<1>(0h0))
when _T_9 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:106 assert (!meta.dirty)\n") : printf_1
assert(clock, _T_6, UInt<1>(0h1), "") : assert_1
node _T_10 = eq(meta.state, UInt<2>(0h1))
when _T_10 :
node _T_11 = eq(meta.dirty, UInt<1>(0h0))
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:109 assert (!meta.dirty)\n") : printf_2
assert(clock, _T_11, UInt<1>(0h1), "") : assert_2
node _T_15 = eq(meta.state, UInt<2>(0h2))
when _T_15 :
node _T_16 = orr(meta.clients)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:112 assert (meta.clients.orR)\n") : printf_3
assert(clock, _T_16, UInt<1>(0h1), "") : assert_3
node _T_20 = sub(meta.clients, UInt<1>(0h1))
node _T_21 = tail(_T_20, 1)
node _T_22 = and(meta.clients, _T_21)
node _T_23 = eq(_T_22, UInt<1>(0h0))
node _T_24 = asUInt(reset)
node _T_25 = eq(_T_24, UInt<1>(0h0))
when _T_25 :
node _T_26 = eq(_T_23, UInt<1>(0h0))
when _T_26 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:113 assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one\n") : printf_4
assert(clock, _T_23, UInt<1>(0h1), "") : assert_4
node _T_27 = eq(meta.state, UInt<2>(0h3))
when _T_27 :
skip
regreset s_rprobe : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_rprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_rprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_release : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_releaseack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_pprobe : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_acquire : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_flush : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantlast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grant : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_probeack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_grantack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_execute : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_writeback : UInt<1>, clock, reset, UInt<1>(0h1)
reg sink : UInt<3>, clock
reg gotT : UInt<1>, clock
reg bad_grant : UInt<1>, clock
reg probes_done : UInt<1>, clock
reg probes_toN : UInt<1>, clock
reg probes_noT : UInt<1>, clock
node _T_28 = neq(meta.state, UInt<2>(0h0))
node _T_29 = and(meta_valid, _T_28)
node _T_30 = eq(io.nestedwb.set, request.set)
node _T_31 = and(_T_29, _T_30)
node _T_32 = eq(io.nestedwb.tag, meta.tag)
node _T_33 = and(_T_31, _T_32)
when _T_33 :
when io.nestedwb.b_clr_dirty :
connect meta.dirty, UInt<1>(0h0)
when io.nestedwb.c_set_dirty :
connect meta.dirty, UInt<1>(0h1)
when io.nestedwb.b_toB :
connect meta.state, UInt<2>(0h1)
when io.nestedwb.b_toN :
connect meta.hit, UInt<1>(0h0)
connect io.status.valid, request_valid
connect io.status.bits.set, request.set
connect io.status.bits.tag, request.tag
connect io.status.bits.way, meta.way
node _io_status_bits_blockB_T = eq(meta_valid, UInt<1>(0h0))
node _io_status_bits_blockB_T_1 = eq(w_releaseack, UInt<1>(0h0))
node _io_status_bits_blockB_T_2 = eq(w_rprobeacklast, UInt<1>(0h0))
node _io_status_bits_blockB_T_3 = or(_io_status_bits_blockB_T_1, _io_status_bits_blockB_T_2)
node _io_status_bits_blockB_T_4 = eq(w_pprobeacklast, UInt<1>(0h0))
node _io_status_bits_blockB_T_5 = or(_io_status_bits_blockB_T_3, _io_status_bits_blockB_T_4)
node _io_status_bits_blockB_T_6 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_blockB_T_7 = and(_io_status_bits_blockB_T_5, _io_status_bits_blockB_T_6)
node _io_status_bits_blockB_T_8 = or(_io_status_bits_blockB_T, _io_status_bits_blockB_T_7)
connect io.status.bits.blockB, _io_status_bits_blockB_T_8
node _io_status_bits_nestB_T = and(meta_valid, w_releaseack)
node _io_status_bits_nestB_T_1 = and(_io_status_bits_nestB_T, w_rprobeacklast)
node _io_status_bits_nestB_T_2 = and(_io_status_bits_nestB_T_1, w_pprobeacklast)
node _io_status_bits_nestB_T_3 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_nestB_T_4 = and(_io_status_bits_nestB_T_2, _io_status_bits_nestB_T_3)
connect io.status.bits.nestB, _io_status_bits_nestB_T_4
node _io_status_bits_blockC_T = eq(meta_valid, UInt<1>(0h0))
connect io.status.bits.blockC, _io_status_bits_blockC_T
node _io_status_bits_nestC_T = eq(w_rprobeackfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_1 = eq(w_pprobeackfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_2 = or(_io_status_bits_nestC_T, _io_status_bits_nestC_T_1)
node _io_status_bits_nestC_T_3 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_4 = or(_io_status_bits_nestC_T_2, _io_status_bits_nestC_T_3)
node _io_status_bits_nestC_T_5 = and(meta_valid, _io_status_bits_nestC_T_4)
connect io.status.bits.nestC, _io_status_bits_nestC_T_5
node _T_34 = eq(io.status.bits.nestB, UInt<1>(0h0))
node _T_35 = eq(io.status.bits.blockB, UInt<1>(0h0))
node _T_36 = or(_T_34, _T_35)
node _T_37 = asUInt(reset)
node _T_38 = eq(_T_37, UInt<1>(0h0))
when _T_38 :
node _T_39 = eq(_T_36, UInt<1>(0h0))
when _T_39 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:179 assert (!io.status.bits.nestB || !io.status.bits.blockB)\n") : printf_5
assert(clock, _T_36, UInt<1>(0h1), "") : assert_5
node _T_40 = eq(io.status.bits.nestC, UInt<1>(0h0))
node _T_41 = eq(io.status.bits.blockC, UInt<1>(0h0))
node _T_42 = or(_T_40, _T_41)
node _T_43 = asUInt(reset)
node _T_44 = eq(_T_43, UInt<1>(0h0))
when _T_44 :
node _T_45 = eq(_T_42, UInt<1>(0h0))
when _T_45 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:180 assert (!io.status.bits.nestC || !io.status.bits.blockC)\n") : printf_6
assert(clock, _T_42, UInt<1>(0h1), "") : assert_6
node _no_wait_T = and(w_rprobeacklast, w_releaseack)
node _no_wait_T_1 = and(_no_wait_T, w_grantlast)
node _no_wait_T_2 = and(_no_wait_T_1, w_pprobeacklast)
node no_wait = and(_no_wait_T_2, w_grantack)
node _io_schedule_bits_a_valid_T = eq(s_acquire, UInt<1>(0h0))
node _io_schedule_bits_a_valid_T_1 = and(_io_schedule_bits_a_valid_T, s_release)
node _io_schedule_bits_a_valid_T_2 = and(_io_schedule_bits_a_valid_T_1, s_pprobe)
connect io.schedule.bits.a.valid, _io_schedule_bits_a_valid_T_2
node _io_schedule_bits_b_valid_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_valid_T_1 = eq(s_pprobe, UInt<1>(0h0))
node _io_schedule_bits_b_valid_T_2 = or(_io_schedule_bits_b_valid_T, _io_schedule_bits_b_valid_T_1)
connect io.schedule.bits.b.valid, _io_schedule_bits_b_valid_T_2
node _io_schedule_bits_c_valid_T = eq(s_release, UInt<1>(0h0))
node _io_schedule_bits_c_valid_T_1 = and(_io_schedule_bits_c_valid_T, w_rprobeackfirst)
node _io_schedule_bits_c_valid_T_2 = eq(s_probeack, UInt<1>(0h0))
node _io_schedule_bits_c_valid_T_3 = and(_io_schedule_bits_c_valid_T_2, w_pprobeackfirst)
node _io_schedule_bits_c_valid_T_4 = or(_io_schedule_bits_c_valid_T_1, _io_schedule_bits_c_valid_T_3)
connect io.schedule.bits.c.valid, _io_schedule_bits_c_valid_T_4
node _io_schedule_bits_d_valid_T = eq(s_execute, UInt<1>(0h0))
node _io_schedule_bits_d_valid_T_1 = and(_io_schedule_bits_d_valid_T, w_pprobeack)
node _io_schedule_bits_d_valid_T_2 = and(_io_schedule_bits_d_valid_T_1, w_grant)
connect io.schedule.bits.d.valid, _io_schedule_bits_d_valid_T_2
node _io_schedule_bits_e_valid_T = eq(s_grantack, UInt<1>(0h0))
node _io_schedule_bits_e_valid_T_1 = and(_io_schedule_bits_e_valid_T, w_grantfirst)
connect io.schedule.bits.e.valid, _io_schedule_bits_e_valid_T_1
node _io_schedule_bits_x_valid_T = eq(s_flush, UInt<1>(0h0))
node _io_schedule_bits_x_valid_T_1 = and(_io_schedule_bits_x_valid_T, w_releaseack)
connect io.schedule.bits.x.valid, _io_schedule_bits_x_valid_T_1
node _io_schedule_bits_dir_valid_T = eq(s_release, UInt<1>(0h0))
node _io_schedule_bits_dir_valid_T_1 = and(_io_schedule_bits_dir_valid_T, w_rprobeackfirst)
node _io_schedule_bits_dir_valid_T_2 = eq(s_writeback, UInt<1>(0h0))
node _io_schedule_bits_dir_valid_T_3 = and(_io_schedule_bits_dir_valid_T_2, no_wait)
node _io_schedule_bits_dir_valid_T_4 = or(_io_schedule_bits_dir_valid_T_1, _io_schedule_bits_dir_valid_T_3)
connect io.schedule.bits.dir.valid, _io_schedule_bits_dir_valid_T_4
connect io.schedule.bits.reload, no_wait
node _io_schedule_valid_T = or(io.schedule.bits.a.valid, io.schedule.bits.b.valid)
node _io_schedule_valid_T_1 = or(_io_schedule_valid_T, io.schedule.bits.c.valid)
node _io_schedule_valid_T_2 = or(_io_schedule_valid_T_1, io.schedule.bits.d.valid)
node _io_schedule_valid_T_3 = or(_io_schedule_valid_T_2, io.schedule.bits.e.valid)
node _io_schedule_valid_T_4 = or(_io_schedule_valid_T_3, io.schedule.bits.x.valid)
node _io_schedule_valid_T_5 = or(_io_schedule_valid_T_4, io.schedule.bits.dir.valid)
connect io.schedule.valid, _io_schedule_valid_T_5
when io.schedule.ready :
connect s_rprobe, UInt<1>(0h1)
when w_rprobeackfirst :
connect s_release, UInt<1>(0h1)
connect s_pprobe, UInt<1>(0h1)
node _T_46 = and(s_release, s_pprobe)
when _T_46 :
connect s_acquire, UInt<1>(0h1)
when w_releaseack :
connect s_flush, UInt<1>(0h1)
when w_pprobeackfirst :
connect s_probeack, UInt<1>(0h1)
when w_grantfirst :
connect s_grantack, UInt<1>(0h1)
node _T_47 = and(w_pprobeack, w_grant)
when _T_47 :
connect s_execute, UInt<1>(0h1)
when no_wait :
connect s_writeback, UInt<1>(0h1)
when no_wait :
connect request_valid, UInt<1>(0h0)
connect meta_valid, UInt<1>(0h0)
wire final_meta_writeback : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}
connect final_meta_writeback, meta
node _req_clientBit_uncommonBits_T = or(request.source, UInt<3>(0h0))
node req_clientBit_uncommonBits = bits(_req_clientBit_uncommonBits_T, 2, 0)
node _req_clientBit_T = shr(request.source, 3)
node _req_clientBit_T_1 = eq(_req_clientBit_T, UInt<2>(0h2))
node _req_clientBit_T_2 = leq(UInt<1>(0h0), req_clientBit_uncommonBits)
node _req_clientBit_T_3 = and(_req_clientBit_T_1, _req_clientBit_T_2)
node _req_clientBit_T_4 = leq(req_clientBit_uncommonBits, UInt<3>(0h7))
node req_clientBit = and(_req_clientBit_T_3, _req_clientBit_T_4)
node _req_needT_T = bits(request.opcode, 2, 2)
node _req_needT_T_1 = eq(_req_needT_T, UInt<1>(0h0))
node _req_needT_T_2 = eq(request.opcode, UInt<3>(0h5))
node _req_needT_T_3 = eq(request.param, UInt<1>(0h1))
node _req_needT_T_4 = and(_req_needT_T_2, _req_needT_T_3)
node _req_needT_T_5 = or(_req_needT_T_1, _req_needT_T_4)
node _req_needT_T_6 = eq(request.opcode, UInt<3>(0h6))
node _req_needT_T_7 = eq(request.opcode, UInt<3>(0h7))
node _req_needT_T_8 = or(_req_needT_T_6, _req_needT_T_7)
node _req_needT_T_9 = neq(request.param, UInt<2>(0h0))
node _req_needT_T_10 = and(_req_needT_T_8, _req_needT_T_9)
node req_needT = or(_req_needT_T_5, _req_needT_T_10)
node _req_acquire_T = eq(request.opcode, UInt<3>(0h6))
node _req_acquire_T_1 = eq(request.opcode, UInt<3>(0h7))
node req_acquire = or(_req_acquire_T, _req_acquire_T_1)
node _meta_no_clients_T = orr(meta.clients)
node meta_no_clients = eq(_meta_no_clients_T, UInt<1>(0h0))
node _req_promoteT_T = eq(meta.state, UInt<2>(0h3))
node _req_promoteT_T_1 = and(meta_no_clients, _req_promoteT_T)
node _req_promoteT_T_2 = mux(meta.hit, _req_promoteT_T_1, gotT)
node req_promoteT = and(req_acquire, _req_promoteT_T_2)
node _T_48 = and(request.prio[2], UInt<1>(0h1))
when _T_48 :
node _final_meta_writeback_dirty_T = bits(request.opcode, 0, 0)
node _final_meta_writeback_dirty_T_1 = or(meta.dirty, _final_meta_writeback_dirty_T)
connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_1
node _final_meta_writeback_state_T = neq(request.param, UInt<3>(0h3))
node _final_meta_writeback_state_T_1 = eq(meta.state, UInt<2>(0h2))
node _final_meta_writeback_state_T_2 = and(_final_meta_writeback_state_T, _final_meta_writeback_state_T_1)
node _final_meta_writeback_state_T_3 = mux(_final_meta_writeback_state_T_2, UInt<2>(0h3), meta.state)
connect final_meta_writeback.state, _final_meta_writeback_state_T_3
node _final_meta_writeback_clients_T = eq(request.param, UInt<3>(0h1))
node _final_meta_writeback_clients_T_1 = eq(request.param, UInt<3>(0h2))
node _final_meta_writeback_clients_T_2 = or(_final_meta_writeback_clients_T, _final_meta_writeback_clients_T_1)
node _final_meta_writeback_clients_T_3 = eq(request.param, UInt<3>(0h5))
node _final_meta_writeback_clients_T_4 = or(_final_meta_writeback_clients_T_2, _final_meta_writeback_clients_T_3)
node _final_meta_writeback_clients_T_5 = mux(_final_meta_writeback_clients_T_4, req_clientBit, UInt<1>(0h0))
node _final_meta_writeback_clients_T_6 = not(_final_meta_writeback_clients_T_5)
node _final_meta_writeback_clients_T_7 = and(meta.clients, _final_meta_writeback_clients_T_6)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_7
connect final_meta_writeback.hit, UInt<1>(0h1)
else :
node _T_49 = and(request.control, UInt<1>(0h1))
when _T_49 :
when meta.hit :
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h0)
node _final_meta_writeback_clients_T_8 = not(probes_toN)
node _final_meta_writeback_clients_T_9 = and(meta.clients, _final_meta_writeback_clients_T_8)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_9
connect final_meta_writeback.hit, UInt<1>(0h0)
else :
node _final_meta_writeback_dirty_T_2 = and(meta.hit, meta.dirty)
node _final_meta_writeback_dirty_T_3 = bits(request.opcode, 2, 2)
node _final_meta_writeback_dirty_T_4 = eq(_final_meta_writeback_dirty_T_3, UInt<1>(0h0))
node _final_meta_writeback_dirty_T_5 = or(_final_meta_writeback_dirty_T_2, _final_meta_writeback_dirty_T_4)
connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_5
node _final_meta_writeback_state_T_4 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_5 = eq(meta.hit, UInt<1>(0h0))
node _final_meta_writeback_state_T_6 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_7 = mux(gotT, _final_meta_writeback_state_T_6, UInt<2>(0h1))
node _final_meta_writeback_state_T_8 = and(meta_no_clients, req_acquire)
node _final_meta_writeback_state_T_9 = mux(_final_meta_writeback_state_T_8, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_10 = eq(UInt<2>(0h1), meta.state)
node _final_meta_writeback_state_T_11 = mux(_final_meta_writeback_state_T_10, UInt<2>(0h1), UInt<2>(0h1))
node _final_meta_writeback_state_T_12 = eq(UInt<2>(0h2), meta.state)
node _final_meta_writeback_state_T_13 = mux(_final_meta_writeback_state_T_12, UInt<2>(0h3), _final_meta_writeback_state_T_11)
node _final_meta_writeback_state_T_14 = eq(UInt<2>(0h3), meta.state)
node _final_meta_writeback_state_T_15 = mux(_final_meta_writeback_state_T_14, _final_meta_writeback_state_T_9, _final_meta_writeback_state_T_13)
node _final_meta_writeback_state_T_16 = mux(_final_meta_writeback_state_T_5, _final_meta_writeback_state_T_7, _final_meta_writeback_state_T_15)
node _final_meta_writeback_state_T_17 = mux(req_needT, _final_meta_writeback_state_T_4, _final_meta_writeback_state_T_16)
connect final_meta_writeback.state, _final_meta_writeback_state_T_17
node _final_meta_writeback_clients_T_10 = not(probes_toN)
node _final_meta_writeback_clients_T_11 = and(meta.clients, _final_meta_writeback_clients_T_10)
node _final_meta_writeback_clients_T_12 = mux(meta.hit, _final_meta_writeback_clients_T_11, UInt<1>(0h0))
node _final_meta_writeback_clients_T_13 = mux(req_acquire, req_clientBit, UInt<1>(0h0))
node _final_meta_writeback_clients_T_14 = or(_final_meta_writeback_clients_T_12, _final_meta_writeback_clients_T_13)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_14
connect final_meta_writeback.tag, request.tag
connect final_meta_writeback.hit, UInt<1>(0h1)
when bad_grant :
when meta.hit :
node _T_50 = eq(meta_valid, UInt<1>(0h0))
node _T_51 = eq(meta.state, UInt<2>(0h1))
node _T_52 = or(_T_50, _T_51)
node _T_53 = asUInt(reset)
node _T_54 = eq(_T_53, UInt<1>(0h0))
when _T_54 :
node _T_55 = eq(_T_52, UInt<1>(0h0))
when _T_55 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:254 assert (!meta_valid || meta.state === BRANCH)\n") : printf_7
assert(clock, _T_52, UInt<1>(0h1), "") : assert_7
connect final_meta_writeback.hit, UInt<1>(0h1)
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h1)
node _final_meta_writeback_clients_T_15 = not(probes_toN)
node _final_meta_writeback_clients_T_16 = and(meta.clients, _final_meta_writeback_clients_T_15)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_16
else :
connect final_meta_writeback.hit, UInt<1>(0h0)
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h0)
connect final_meta_writeback.clients, UInt<1>(0h0)
wire invalid : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>}
connect invalid.dirty, UInt<1>(0h0)
connect invalid.state, UInt<2>(0h0)
connect invalid.clients, UInt<1>(0h0)
connect invalid.tag, UInt<1>(0h0)
node _honour_BtoT_T = and(meta.clients, req_clientBit)
node _honour_BtoT_T_1 = orr(_honour_BtoT_T)
node honour_BtoT = and(meta.hit, _honour_BtoT_T_1)
node _excluded_client_T = and(meta.hit, request.prio[0])
node _excluded_client_T_1 = eq(request.opcode, UInt<3>(0h6))
node _excluded_client_T_2 = eq(request.opcode, UInt<3>(0h7))
node _excluded_client_T_3 = or(_excluded_client_T_1, _excluded_client_T_2)
node _excluded_client_T_4 = eq(request.opcode, UInt<3>(0h4))
node _excluded_client_T_5 = or(_excluded_client_T_3, _excluded_client_T_4)
node _excluded_client_T_6 = eq(request.opcode, UInt<3>(0h5))
node _excluded_client_T_7 = and(_excluded_client_T_6, UInt<1>(0h0))
node _excluded_client_T_8 = or(_excluded_client_T_5, _excluded_client_T_7)
node _excluded_client_T_9 = and(_excluded_client_T, _excluded_client_T_8)
node excluded_client = mux(_excluded_client_T_9, req_clientBit, UInt<1>(0h0))
connect io.schedule.bits.a.bits.tag, request.tag
connect io.schedule.bits.a.bits.set, request.set
node _io_schedule_bits_a_bits_param_T = mux(meta.hit, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_a_bits_param_T_1 = mux(req_needT, _io_schedule_bits_a_bits_param_T, UInt<2>(0h0))
connect io.schedule.bits.a.bits.param, _io_schedule_bits_a_bits_param_T_1
node _io_schedule_bits_a_bits_block_T = neq(request.size, UInt<3>(0h6))
node _io_schedule_bits_a_bits_block_T_1 = eq(request.opcode, UInt<1>(0h0))
node _io_schedule_bits_a_bits_block_T_2 = eq(request.opcode, UInt<3>(0h7))
node _io_schedule_bits_a_bits_block_T_3 = or(_io_schedule_bits_a_bits_block_T_1, _io_schedule_bits_a_bits_block_T_2)
node _io_schedule_bits_a_bits_block_T_4 = eq(_io_schedule_bits_a_bits_block_T_3, UInt<1>(0h0))
node _io_schedule_bits_a_bits_block_T_5 = or(_io_schedule_bits_a_bits_block_T, _io_schedule_bits_a_bits_block_T_4)
connect io.schedule.bits.a.bits.block, _io_schedule_bits_a_bits_block_T_5
connect io.schedule.bits.a.bits.source, UInt<1>(0h0)
node _io_schedule_bits_b_bits_param_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_bits_param_T_1 = mux(req_needT, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_b_bits_param_T_2 = mux(request.prio[1], request.param, _io_schedule_bits_b_bits_param_T_1)
node _io_schedule_bits_b_bits_param_T_3 = mux(_io_schedule_bits_b_bits_param_T, UInt<2>(0h2), _io_schedule_bits_b_bits_param_T_2)
connect io.schedule.bits.b.bits.param, _io_schedule_bits_b_bits_param_T_3
node _io_schedule_bits_b_bits_tag_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_bits_tag_T_1 = mux(_io_schedule_bits_b_bits_tag_T, meta.tag, request.tag)
connect io.schedule.bits.b.bits.tag, _io_schedule_bits_b_bits_tag_T_1
connect io.schedule.bits.b.bits.set, request.set
node _io_schedule_bits_b_bits_clients_T = not(excluded_client)
node _io_schedule_bits_b_bits_clients_T_1 = and(meta.clients, _io_schedule_bits_b_bits_clients_T)
connect io.schedule.bits.b.bits.clients, _io_schedule_bits_b_bits_clients_T_1
node _io_schedule_bits_c_bits_opcode_T = mux(meta.dirty, UInt<3>(0h7), UInt<3>(0h6))
connect io.schedule.bits.c.bits.opcode, _io_schedule_bits_c_bits_opcode_T
node _io_schedule_bits_c_bits_param_T = eq(meta.state, UInt<2>(0h1))
node _io_schedule_bits_c_bits_param_T_1 = mux(_io_schedule_bits_c_bits_param_T, UInt<3>(0h2), UInt<3>(0h1))
connect io.schedule.bits.c.bits.param, _io_schedule_bits_c_bits_param_T_1
connect io.schedule.bits.c.bits.source, UInt<1>(0h0)
connect io.schedule.bits.c.bits.tag, meta.tag
connect io.schedule.bits.c.bits.set, request.set
connect io.schedule.bits.c.bits.way, meta.way
connect io.schedule.bits.c.bits.dirty, meta.dirty
connect io.schedule.bits.d.bits.set, request.set
connect io.schedule.bits.d.bits.put, request.put
connect io.schedule.bits.d.bits.offset, request.offset
connect io.schedule.bits.d.bits.tag, request.tag
connect io.schedule.bits.d.bits.source, request.source
connect io.schedule.bits.d.bits.size, request.size
connect io.schedule.bits.d.bits.param, request.param
connect io.schedule.bits.d.bits.opcode, request.opcode
connect io.schedule.bits.d.bits.control, request.control
connect io.schedule.bits.d.bits.prio, request.prio
node _io_schedule_bits_d_bits_param_T = eq(req_acquire, UInt<1>(0h0))
node _io_schedule_bits_d_bits_param_T_1 = mux(req_promoteT, UInt<2>(0h1), UInt<2>(0h0))
node _io_schedule_bits_d_bits_param_T_2 = mux(honour_BtoT, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_d_bits_param_T_3 = eq(UInt<2>(0h0), request.param)
node _io_schedule_bits_d_bits_param_T_4 = mux(_io_schedule_bits_d_bits_param_T_3, _io_schedule_bits_d_bits_param_T_1, request.param)
node _io_schedule_bits_d_bits_param_T_5 = eq(UInt<2>(0h2), request.param)
node _io_schedule_bits_d_bits_param_T_6 = mux(_io_schedule_bits_d_bits_param_T_5, _io_schedule_bits_d_bits_param_T_2, _io_schedule_bits_d_bits_param_T_4)
node _io_schedule_bits_d_bits_param_T_7 = eq(UInt<2>(0h1), request.param)
node _io_schedule_bits_d_bits_param_T_8 = mux(_io_schedule_bits_d_bits_param_T_7, UInt<2>(0h1), _io_schedule_bits_d_bits_param_T_6)
node _io_schedule_bits_d_bits_param_T_9 = mux(_io_schedule_bits_d_bits_param_T, request.param, _io_schedule_bits_d_bits_param_T_8)
connect io.schedule.bits.d.bits.param, _io_schedule_bits_d_bits_param_T_9
connect io.schedule.bits.d.bits.sink, UInt<1>(0h0)
connect io.schedule.bits.d.bits.way, meta.way
connect io.schedule.bits.d.bits.bad, bad_grant
connect io.schedule.bits.e.bits.sink, sink
connect io.schedule.bits.x.bits.fail, UInt<1>(0h0)
connect io.schedule.bits.dir.bits.set, request.set
connect io.schedule.bits.dir.bits.way, meta.way
node _io_schedule_bits_dir_bits_data_T = eq(s_release, UInt<1>(0h0))
wire _io_schedule_bits_dir_bits_data_WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>}
connect _io_schedule_bits_dir_bits_data_WIRE.tag, final_meta_writeback.tag
connect _io_schedule_bits_dir_bits_data_WIRE.clients, final_meta_writeback.clients
connect _io_schedule_bits_dir_bits_data_WIRE.state, final_meta_writeback.state
connect _io_schedule_bits_dir_bits_data_WIRE.dirty, final_meta_writeback.dirty
node _io_schedule_bits_dir_bits_data_T_1 = mux(_io_schedule_bits_dir_bits_data_T, invalid, _io_schedule_bits_dir_bits_data_WIRE)
connect io.schedule.bits.dir.bits.data, _io_schedule_bits_dir_bits_data_T_1
node _evict_T = eq(meta.hit, UInt<1>(0h0))
wire evict : UInt
connect evict, UInt<1>(0h0)
node evict_c = orr(meta.clients)
node _evict_T_1 = eq(UInt<2>(0h1), meta.state)
when _evict_T_1 :
node _evict_out_T = mux(evict_c, UInt<1>(0h0), UInt<1>(0h1))
connect evict, _evict_out_T
else :
node _evict_T_2 = eq(UInt<2>(0h2), meta.state)
when _evict_T_2 :
node _evict_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect evict, _evict_out_T_1
else :
node _evict_T_3 = eq(UInt<2>(0h3), meta.state)
when _evict_T_3 :
node _evict_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _evict_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _evict_out_T_4 = mux(evict_c, _evict_out_T_2, _evict_out_T_3)
connect evict, _evict_out_T_4
else :
node _evict_T_4 = eq(UInt<2>(0h0), meta.state)
when _evict_T_4 :
connect evict, UInt<4>(0h8)
node _evict_T_5 = eq(_evict_T, UInt<1>(0h0))
when _evict_T_5 :
connect evict, UInt<4>(0h8)
wire before : UInt
connect before, UInt<1>(0h0)
node before_c = orr(meta.clients)
node _before_T = eq(UInt<2>(0h1), meta.state)
when _before_T :
node _before_out_T = mux(before_c, UInt<1>(0h0), UInt<1>(0h1))
connect before, _before_out_T
else :
node _before_T_1 = eq(UInt<2>(0h2), meta.state)
when _before_T_1 :
node _before_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect before, _before_out_T_1
else :
node _before_T_2 = eq(UInt<2>(0h3), meta.state)
when _before_T_2 :
node _before_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _before_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _before_out_T_4 = mux(before_c, _before_out_T_2, _before_out_T_3)
connect before, _before_out_T_4
else :
node _before_T_3 = eq(UInt<2>(0h0), meta.state)
when _before_T_3 :
connect before, UInt<4>(0h8)
node _before_T_4 = eq(meta.hit, UInt<1>(0h0))
when _before_T_4 :
connect before, UInt<4>(0h8)
wire after : UInt
connect after, UInt<1>(0h0)
node after_c = orr(final_meta_writeback.clients)
node _after_T = eq(UInt<2>(0h1), final_meta_writeback.state)
when _after_T :
node _after_out_T = mux(after_c, UInt<1>(0h0), UInt<1>(0h1))
connect after, _after_out_T
else :
node _after_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state)
when _after_T_1 :
node _after_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect after, _after_out_T_1
else :
node _after_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state)
when _after_T_2 :
node _after_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _after_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _after_out_T_4 = mux(after_c, _after_out_T_2, _after_out_T_3)
connect after, _after_out_T_4
else :
node _after_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state)
when _after_T_3 :
connect after, UInt<4>(0h8)
node _after_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0))
when _after_T_4 :
connect after, UInt<4>(0h8)
node _T_56 = eq(s_release, UInt<1>(0h0))
node _T_57 = and(_T_56, w_rprobeackfirst)
node _T_58 = and(_T_57, io.schedule.ready)
when _T_58 :
node _T_59 = eq(evict, UInt<1>(0h1))
node _T_60 = eq(_T_59, UInt<1>(0h0))
node _T_61 = asUInt(reset)
node _T_62 = eq(_T_61, UInt<1>(0h0))
when _T_62 :
node _T_63 = eq(_T_60, UInt<1>(0h0))
when _T_63 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_8
assert(clock, _T_60, UInt<1>(0h1), "") : assert_8
node _T_64 = eq(before, UInt<1>(0h1))
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(_T_65, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_9
assert(clock, _T_65, UInt<1>(0h1), "") : assert_9
node _T_69 = eq(evict, UInt<1>(0h0))
node _T_70 = eq(_T_69, UInt<1>(0h0))
node _T_71 = asUInt(reset)
node _T_72 = eq(_T_71, UInt<1>(0h0))
when _T_72 :
node _T_73 = eq(_T_70, UInt<1>(0h0))
when _T_73 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_10
assert(clock, _T_70, UInt<1>(0h1), "") : assert_10
node _T_74 = eq(before, UInt<1>(0h0))
node _T_75 = eq(_T_74, UInt<1>(0h0))
node _T_76 = asUInt(reset)
node _T_77 = eq(_T_76, UInt<1>(0h0))
when _T_77 :
node _T_78 = eq(_T_75, UInt<1>(0h0))
when _T_78 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_11
assert(clock, _T_75, UInt<1>(0h1), "") : assert_11
node _T_79 = eq(evict, UInt<3>(0h7))
node _T_80 = eq(before, UInt<3>(0h7))
node _T_81 = eq(evict, UInt<3>(0h5))
node _T_82 = eq(before, UInt<3>(0h5))
node _T_83 = eq(evict, UInt<3>(0h4))
node _T_84 = eq(before, UInt<3>(0h4))
node _T_85 = eq(evict, UInt<3>(0h6))
node _T_86 = eq(before, UInt<3>(0h6))
node _T_87 = eq(evict, UInt<2>(0h3))
node _T_88 = eq(before, UInt<2>(0h3))
node _T_89 = eq(evict, UInt<2>(0h2))
node _T_90 = eq(before, UInt<2>(0h2))
node _T_91 = eq(s_writeback, UInt<1>(0h0))
node _T_92 = and(_T_91, no_wait)
node _T_93 = and(_T_92, io.schedule.ready)
when _T_93 :
node _T_94 = eq(before, UInt<4>(0h8))
node _T_95 = eq(after, UInt<1>(0h1))
node _T_96 = and(_T_94, _T_95)
node _T_97 = eq(_T_96, UInt<1>(0h0))
node _T_98 = asUInt(reset)
node _T_99 = eq(_T_98, UInt<1>(0h0))
when _T_99 :
node _T_100 = eq(_T_97, UInt<1>(0h0))
when _T_100 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_12
assert(clock, _T_97, UInt<1>(0h1), "") : assert_12
node _T_101 = eq(before, UInt<4>(0h8))
node _T_102 = eq(after, UInt<1>(0h0))
node _T_103 = and(_T_101, _T_102)
node _T_104 = eq(_T_103, UInt<1>(0h0))
node _T_105 = asUInt(reset)
node _T_106 = eq(_T_105, UInt<1>(0h0))
when _T_106 :
node _T_107 = eq(_T_104, UInt<1>(0h0))
when _T_107 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_13
assert(clock, _T_104, UInt<1>(0h1), "") : assert_13
node _T_108 = eq(before, UInt<4>(0h8))
node _T_109 = eq(after, UInt<3>(0h7))
node _T_110 = and(_T_108, _T_109)
node _T_111 = eq(before, UInt<4>(0h8))
node _T_112 = eq(after, UInt<3>(0h5))
node _T_113 = and(_T_111, _T_112)
node _T_114 = eq(_T_113, UInt<1>(0h0))
node _T_115 = asUInt(reset)
node _T_116 = eq(_T_115, UInt<1>(0h0))
when _T_116 :
node _T_117 = eq(_T_114, UInt<1>(0h0))
when _T_117 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_14
assert(clock, _T_114, UInt<1>(0h1), "") : assert_14
node _T_118 = eq(before, UInt<4>(0h8))
node _T_119 = eq(after, UInt<3>(0h4))
node _T_120 = and(_T_118, _T_119)
node _T_121 = eq(_T_120, UInt<1>(0h0))
node _T_122 = asUInt(reset)
node _T_123 = eq(_T_122, UInt<1>(0h0))
when _T_123 :
node _T_124 = eq(_T_121, UInt<1>(0h0))
when _T_124 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_15
assert(clock, _T_121, UInt<1>(0h1), "") : assert_15
node _T_125 = eq(before, UInt<4>(0h8))
node _T_126 = eq(after, UInt<3>(0h6))
node _T_127 = and(_T_125, _T_126)
node _T_128 = eq(before, UInt<4>(0h8))
node _T_129 = eq(after, UInt<2>(0h3))
node _T_130 = and(_T_128, _T_129)
node _T_131 = eq(before, UInt<4>(0h8))
node _T_132 = eq(after, UInt<2>(0h2))
node _T_133 = and(_T_131, _T_132)
node _T_134 = eq(_T_133, UInt<1>(0h0))
node _T_135 = asUInt(reset)
node _T_136 = eq(_T_135, UInt<1>(0h0))
when _T_136 :
node _T_137 = eq(_T_134, UInt<1>(0h0))
when _T_137 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_16
assert(clock, _T_134, UInt<1>(0h1), "") : assert_16
node _T_138 = eq(before, UInt<1>(0h1))
node _T_139 = eq(after, UInt<4>(0h8))
node _T_140 = and(_T_138, _T_139)
node _T_141 = eq(_T_140, UInt<1>(0h0))
node _T_142 = asUInt(reset)
node _T_143 = eq(_T_142, UInt<1>(0h0))
when _T_143 :
node _T_144 = eq(_T_141, UInt<1>(0h0))
when _T_144 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_17
assert(clock, _T_141, UInt<1>(0h1), "") : assert_17
node _T_145 = eq(before, UInt<1>(0h1))
node _T_146 = eq(after, UInt<1>(0h0))
node _T_147 = and(_T_145, _T_146)
node _T_148 = eq(_T_147, UInt<1>(0h0))
node _T_149 = asUInt(reset)
node _T_150 = eq(_T_149, UInt<1>(0h0))
when _T_150 :
node _T_151 = eq(_T_148, UInt<1>(0h0))
when _T_151 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_18
assert(clock, _T_148, UInt<1>(0h1), "") : assert_18
node _T_152 = eq(before, UInt<1>(0h1))
node _T_153 = eq(after, UInt<3>(0h7))
node _T_154 = and(_T_152, _T_153)
node _T_155 = eq(_T_154, UInt<1>(0h0))
node _T_156 = asUInt(reset)
node _T_157 = eq(_T_156, UInt<1>(0h0))
when _T_157 :
node _T_158 = eq(_T_155, UInt<1>(0h0))
when _T_158 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_19
assert(clock, _T_155, UInt<1>(0h1), "") : assert_19
node _T_159 = eq(before, UInt<1>(0h1))
node _T_160 = eq(after, UInt<3>(0h5))
node _T_161 = and(_T_159, _T_160)
node _T_162 = eq(_T_161, UInt<1>(0h0))
node _T_163 = asUInt(reset)
node _T_164 = eq(_T_163, UInt<1>(0h0))
when _T_164 :
node _T_165 = eq(_T_162, UInt<1>(0h0))
when _T_165 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_20
assert(clock, _T_162, UInt<1>(0h1), "") : assert_20
node _T_166 = eq(before, UInt<1>(0h1))
node _T_167 = eq(after, UInt<3>(0h4))
node _T_168 = and(_T_166, _T_167)
node _T_169 = eq(_T_168, UInt<1>(0h0))
node _T_170 = asUInt(reset)
node _T_171 = eq(_T_170, UInt<1>(0h0))
when _T_171 :
node _T_172 = eq(_T_169, UInt<1>(0h0))
when _T_172 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_21
assert(clock, _T_169, UInt<1>(0h1), "") : assert_21
node _T_173 = eq(before, UInt<1>(0h1))
node _T_174 = eq(after, UInt<3>(0h6))
node _T_175 = and(_T_173, _T_174)
node _T_176 = eq(_T_175, UInt<1>(0h0))
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(_T_176, UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_22
assert(clock, _T_176, UInt<1>(0h1), "") : assert_22
node _T_180 = eq(before, UInt<1>(0h1))
node _T_181 = eq(after, UInt<2>(0h3))
node _T_182 = and(_T_180, _T_181)
node _T_183 = eq(_T_182, UInt<1>(0h0))
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_23
assert(clock, _T_183, UInt<1>(0h1), "") : assert_23
node _T_187 = eq(before, UInt<1>(0h1))
node _T_188 = eq(after, UInt<2>(0h2))
node _T_189 = and(_T_187, _T_188)
node _T_190 = eq(_T_189, UInt<1>(0h0))
node _T_191 = asUInt(reset)
node _T_192 = eq(_T_191, UInt<1>(0h0))
when _T_192 :
node _T_193 = eq(_T_190, UInt<1>(0h0))
when _T_193 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_24
assert(clock, _T_190, UInt<1>(0h1), "") : assert_24
node _T_194 = eq(before, UInt<1>(0h0))
node _T_195 = eq(after, UInt<4>(0h8))
node _T_196 = and(_T_194, _T_195)
node _T_197 = eq(_T_196, UInt<1>(0h0))
node _T_198 = asUInt(reset)
node _T_199 = eq(_T_198, UInt<1>(0h0))
when _T_199 :
node _T_200 = eq(_T_197, UInt<1>(0h0))
when _T_200 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_25
assert(clock, _T_197, UInt<1>(0h1), "") : assert_25
node _T_201 = eq(before, UInt<1>(0h0))
node _T_202 = eq(after, UInt<1>(0h1))
node _T_203 = and(_T_201, _T_202)
node _T_204 = eq(_T_203, UInt<1>(0h0))
node _T_205 = asUInt(reset)
node _T_206 = eq(_T_205, UInt<1>(0h0))
when _T_206 :
node _T_207 = eq(_T_204, UInt<1>(0h0))
when _T_207 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_26
assert(clock, _T_204, UInt<1>(0h1), "") : assert_26
node _T_208 = eq(before, UInt<1>(0h0))
node _T_209 = eq(after, UInt<3>(0h7))
node _T_210 = and(_T_208, _T_209)
node _T_211 = eq(_T_210, UInt<1>(0h0))
node _T_212 = asUInt(reset)
node _T_213 = eq(_T_212, UInt<1>(0h0))
when _T_213 :
node _T_214 = eq(_T_211, UInt<1>(0h0))
when _T_214 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_27
assert(clock, _T_211, UInt<1>(0h1), "") : assert_27
node _T_215 = eq(before, UInt<1>(0h0))
node _T_216 = eq(after, UInt<3>(0h5))
node _T_217 = and(_T_215, _T_216)
node _T_218 = eq(_T_217, UInt<1>(0h0))
node _T_219 = asUInt(reset)
node _T_220 = eq(_T_219, UInt<1>(0h0))
when _T_220 :
node _T_221 = eq(_T_218, UInt<1>(0h0))
when _T_221 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_28
assert(clock, _T_218, UInt<1>(0h1), "") : assert_28
node _T_222 = eq(before, UInt<1>(0h0))
node _T_223 = eq(after, UInt<3>(0h6))
node _T_224 = and(_T_222, _T_223)
node _T_225 = eq(_T_224, UInt<1>(0h0))
node _T_226 = asUInt(reset)
node _T_227 = eq(_T_226, UInt<1>(0h0))
when _T_227 :
node _T_228 = eq(_T_225, UInt<1>(0h0))
when _T_228 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_29
assert(clock, _T_225, UInt<1>(0h1), "") : assert_29
node _T_229 = eq(before, UInt<1>(0h0))
node _T_230 = eq(after, UInt<3>(0h4))
node _T_231 = and(_T_229, _T_230)
node _T_232 = eq(_T_231, UInt<1>(0h0))
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_30
assert(clock, _T_232, UInt<1>(0h1), "") : assert_30
node _T_236 = eq(before, UInt<1>(0h0))
node _T_237 = eq(after, UInt<2>(0h3))
node _T_238 = and(_T_236, _T_237)
node _T_239 = eq(_T_238, UInt<1>(0h0))
node _T_240 = asUInt(reset)
node _T_241 = eq(_T_240, UInt<1>(0h0))
when _T_241 :
node _T_242 = eq(_T_239, UInt<1>(0h0))
when _T_242 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_31
assert(clock, _T_239, UInt<1>(0h1), "") : assert_31
node _T_243 = eq(before, UInt<1>(0h0))
node _T_244 = eq(after, UInt<2>(0h2))
node _T_245 = and(_T_243, _T_244)
node _T_246 = eq(_T_245, UInt<1>(0h0))
node _T_247 = asUInt(reset)
node _T_248 = eq(_T_247, UInt<1>(0h0))
when _T_248 :
node _T_249 = eq(_T_246, UInt<1>(0h0))
when _T_249 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_32
assert(clock, _T_246, UInt<1>(0h1), "") : assert_32
node _T_250 = eq(before, UInt<3>(0h7))
node _T_251 = eq(after, UInt<4>(0h8))
node _T_252 = and(_T_250, _T_251)
node _T_253 = eq(_T_252, UInt<1>(0h0))
node _T_254 = asUInt(reset)
node _T_255 = eq(_T_254, UInt<1>(0h0))
when _T_255 :
node _T_256 = eq(_T_253, UInt<1>(0h0))
when _T_256 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_33
assert(clock, _T_253, UInt<1>(0h1), "") : assert_33
node _T_257 = eq(before, UInt<3>(0h7))
node _T_258 = eq(after, UInt<1>(0h1))
node _T_259 = and(_T_257, _T_258)
node _T_260 = eq(_T_259, UInt<1>(0h0))
node _T_261 = asUInt(reset)
node _T_262 = eq(_T_261, UInt<1>(0h0))
when _T_262 :
node _T_263 = eq(_T_260, UInt<1>(0h0))
when _T_263 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_34
assert(clock, _T_260, UInt<1>(0h1), "") : assert_34
node _T_264 = eq(before, UInt<3>(0h7))
node _T_265 = eq(after, UInt<1>(0h0))
node _T_266 = and(_T_264, _T_265)
node _T_267 = eq(_T_266, UInt<1>(0h0))
node _T_268 = asUInt(reset)
node _T_269 = eq(_T_268, UInt<1>(0h0))
when _T_269 :
node _T_270 = eq(_T_267, UInt<1>(0h0))
when _T_270 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_35
assert(clock, _T_267, UInt<1>(0h1), "") : assert_35
node _T_271 = eq(before, UInt<3>(0h7))
node _T_272 = eq(after, UInt<3>(0h5))
node _T_273 = and(_T_271, _T_272)
node _T_274 = eq(_T_273, UInt<1>(0h0))
node _T_275 = asUInt(reset)
node _T_276 = eq(_T_275, UInt<1>(0h0))
when _T_276 :
node _T_277 = eq(_T_274, UInt<1>(0h0))
when _T_277 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_36
assert(clock, _T_274, UInt<1>(0h1), "") : assert_36
node _T_278 = eq(before, UInt<3>(0h7))
node _T_279 = eq(after, UInt<3>(0h6))
node _T_280 = and(_T_278, _T_279)
node _T_281 = eq(before, UInt<3>(0h7))
node _T_282 = eq(after, UInt<3>(0h4))
node _T_283 = and(_T_281, _T_282)
node _T_284 = eq(_T_283, UInt<1>(0h0))
node _T_285 = asUInt(reset)
node _T_286 = eq(_T_285, UInt<1>(0h0))
when _T_286 :
node _T_287 = eq(_T_284, UInt<1>(0h0))
when _T_287 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_37
assert(clock, _T_284, UInt<1>(0h1), "") : assert_37
node _T_288 = eq(before, UInt<3>(0h7))
node _T_289 = eq(after, UInt<2>(0h3))
node _T_290 = and(_T_288, _T_289)
node _T_291 = eq(before, UInt<3>(0h7))
node _T_292 = eq(after, UInt<2>(0h2))
node _T_293 = and(_T_291, _T_292)
node _T_294 = eq(_T_293, UInt<1>(0h0))
node _T_295 = asUInt(reset)
node _T_296 = eq(_T_295, UInt<1>(0h0))
when _T_296 :
node _T_297 = eq(_T_294, UInt<1>(0h0))
when _T_297 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_38
assert(clock, _T_294, UInt<1>(0h1), "") : assert_38
node _T_298 = eq(before, UInt<3>(0h5))
node _T_299 = eq(after, UInt<4>(0h8))
node _T_300 = and(_T_298, _T_299)
node _T_301 = eq(_T_300, UInt<1>(0h0))
node _T_302 = asUInt(reset)
node _T_303 = eq(_T_302, UInt<1>(0h0))
when _T_303 :
node _T_304 = eq(_T_301, UInt<1>(0h0))
when _T_304 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_39
assert(clock, _T_301, UInt<1>(0h1), "") : assert_39
node _T_305 = eq(before, UInt<3>(0h5))
node _T_306 = eq(after, UInt<1>(0h1))
node _T_307 = and(_T_305, _T_306)
node _T_308 = eq(_T_307, UInt<1>(0h0))
node _T_309 = asUInt(reset)
node _T_310 = eq(_T_309, UInt<1>(0h0))
when _T_310 :
node _T_311 = eq(_T_308, UInt<1>(0h0))
when _T_311 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_40
assert(clock, _T_308, UInt<1>(0h1), "") : assert_40
node _T_312 = eq(before, UInt<3>(0h5))
node _T_313 = eq(after, UInt<1>(0h0))
node _T_314 = and(_T_312, _T_313)
node _T_315 = eq(_T_314, UInt<1>(0h0))
node _T_316 = asUInt(reset)
node _T_317 = eq(_T_316, UInt<1>(0h0))
when _T_317 :
node _T_318 = eq(_T_315, UInt<1>(0h0))
when _T_318 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_41
assert(clock, _T_315, UInt<1>(0h1), "") : assert_41
node _T_319 = eq(before, UInt<3>(0h5))
node _T_320 = eq(after, UInt<3>(0h7))
node _T_321 = and(_T_319, _T_320)
node _T_322 = eq(before, UInt<3>(0h5))
node _T_323 = eq(after, UInt<3>(0h6))
node _T_324 = and(_T_322, _T_323)
node _T_325 = eq(before, UInt<3>(0h5))
node _T_326 = eq(after, UInt<3>(0h4))
node _T_327 = and(_T_325, _T_326)
node _T_328 = eq(_T_327, UInt<1>(0h0))
node _T_329 = asUInt(reset)
node _T_330 = eq(_T_329, UInt<1>(0h0))
when _T_330 :
node _T_331 = eq(_T_328, UInt<1>(0h0))
when _T_331 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_42
assert(clock, _T_328, UInt<1>(0h1), "") : assert_42
node _T_332 = eq(before, UInt<3>(0h5))
node _T_333 = eq(after, UInt<2>(0h3))
node _T_334 = and(_T_332, _T_333)
node _T_335 = eq(before, UInt<3>(0h5))
node _T_336 = eq(after, UInt<2>(0h2))
node _T_337 = and(_T_335, _T_336)
node _T_338 = eq(_T_337, UInt<1>(0h0))
node _T_339 = asUInt(reset)
node _T_340 = eq(_T_339, UInt<1>(0h0))
when _T_340 :
node _T_341 = eq(_T_338, UInt<1>(0h0))
when _T_341 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_43
assert(clock, _T_338, UInt<1>(0h1), "") : assert_43
node _T_342 = eq(before, UInt<3>(0h6))
node _T_343 = eq(after, UInt<4>(0h8))
node _T_344 = and(_T_342, _T_343)
node _T_345 = eq(_T_344, UInt<1>(0h0))
node _T_346 = asUInt(reset)
node _T_347 = eq(_T_346, UInt<1>(0h0))
when _T_347 :
node _T_348 = eq(_T_345, UInt<1>(0h0))
when _T_348 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_44
assert(clock, _T_345, UInt<1>(0h1), "") : assert_44
node _T_349 = eq(before, UInt<3>(0h6))
node _T_350 = eq(after, UInt<1>(0h1))
node _T_351 = and(_T_349, _T_350)
node _T_352 = eq(_T_351, UInt<1>(0h0))
node _T_353 = asUInt(reset)
node _T_354 = eq(_T_353, UInt<1>(0h0))
when _T_354 :
node _T_355 = eq(_T_352, UInt<1>(0h0))
when _T_355 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_45
assert(clock, _T_352, UInt<1>(0h1), "") : assert_45
node _T_356 = eq(before, UInt<3>(0h6))
node _T_357 = eq(after, UInt<1>(0h0))
node _T_358 = and(_T_356, _T_357)
node _T_359 = eq(_T_358, UInt<1>(0h0))
node _T_360 = asUInt(reset)
node _T_361 = eq(_T_360, UInt<1>(0h0))
when _T_361 :
node _T_362 = eq(_T_359, UInt<1>(0h0))
when _T_362 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_46
assert(clock, _T_359, UInt<1>(0h1), "") : assert_46
node _T_363 = eq(before, UInt<3>(0h6))
node _T_364 = eq(after, UInt<3>(0h7))
node _T_365 = and(_T_363, _T_364)
node _T_366 = eq(_T_365, UInt<1>(0h0))
node _T_367 = asUInt(reset)
node _T_368 = eq(_T_367, UInt<1>(0h0))
when _T_368 :
node _T_369 = eq(_T_366, UInt<1>(0h0))
when _T_369 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_47
assert(clock, _T_366, UInt<1>(0h1), "") : assert_47
node _T_370 = eq(before, UInt<3>(0h6))
node _T_371 = eq(after, UInt<3>(0h5))
node _T_372 = and(_T_370, _T_371)
node _T_373 = eq(_T_372, UInt<1>(0h0))
node _T_374 = asUInt(reset)
node _T_375 = eq(_T_374, UInt<1>(0h0))
when _T_375 :
node _T_376 = eq(_T_373, UInt<1>(0h0))
when _T_376 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_48
assert(clock, _T_373, UInt<1>(0h1), "") : assert_48
node _T_377 = eq(before, UInt<3>(0h6))
node _T_378 = eq(after, UInt<3>(0h4))
node _T_379 = and(_T_377, _T_378)
node _T_380 = eq(_T_379, UInt<1>(0h0))
node _T_381 = asUInt(reset)
node _T_382 = eq(_T_381, UInt<1>(0h0))
when _T_382 :
node _T_383 = eq(_T_380, UInt<1>(0h0))
when _T_383 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_49
assert(clock, _T_380, UInt<1>(0h1), "") : assert_49
node _T_384 = eq(before, UInt<3>(0h6))
node _T_385 = eq(after, UInt<2>(0h3))
node _T_386 = and(_T_384, _T_385)
node _T_387 = eq(_T_386, UInt<1>(0h0))
node _T_388 = asUInt(reset)
node _T_389 = eq(_T_388, UInt<1>(0h0))
when _T_389 :
node _T_390 = eq(_T_387, UInt<1>(0h0))
when _T_390 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_50
assert(clock, _T_387, UInt<1>(0h1), "") : assert_50
node _T_391 = eq(before, UInt<3>(0h6))
node _T_392 = eq(after, UInt<2>(0h2))
node _T_393 = and(_T_391, _T_392)
node _T_394 = eq(before, UInt<3>(0h4))
node _T_395 = eq(after, UInt<4>(0h8))
node _T_396 = and(_T_394, _T_395)
node _T_397 = eq(_T_396, UInt<1>(0h0))
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(_T_397, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_51
assert(clock, _T_397, UInt<1>(0h1), "") : assert_51
node _T_401 = eq(before, UInt<3>(0h4))
node _T_402 = eq(after, UInt<1>(0h1))
node _T_403 = and(_T_401, _T_402)
node _T_404 = eq(_T_403, UInt<1>(0h0))
node _T_405 = asUInt(reset)
node _T_406 = eq(_T_405, UInt<1>(0h0))
when _T_406 :
node _T_407 = eq(_T_404, UInt<1>(0h0))
when _T_407 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_52
assert(clock, _T_404, UInt<1>(0h1), "") : assert_52
node _T_408 = eq(before, UInt<3>(0h4))
node _T_409 = eq(after, UInt<1>(0h0))
node _T_410 = and(_T_408, _T_409)
node _T_411 = eq(_T_410, UInt<1>(0h0))
node _T_412 = asUInt(reset)
node _T_413 = eq(_T_412, UInt<1>(0h0))
when _T_413 :
node _T_414 = eq(_T_411, UInt<1>(0h0))
when _T_414 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_53
assert(clock, _T_411, UInt<1>(0h1), "") : assert_53
node _T_415 = eq(before, UInt<3>(0h4))
node _T_416 = eq(after, UInt<3>(0h7))
node _T_417 = and(_T_415, _T_416)
node _T_418 = eq(_T_417, UInt<1>(0h0))
node _T_419 = asUInt(reset)
node _T_420 = eq(_T_419, UInt<1>(0h0))
when _T_420 :
node _T_421 = eq(_T_418, UInt<1>(0h0))
when _T_421 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_54
assert(clock, _T_418, UInt<1>(0h1), "") : assert_54
node _T_422 = eq(before, UInt<3>(0h4))
node _T_423 = eq(after, UInt<3>(0h5))
node _T_424 = and(_T_422, _T_423)
node _T_425 = eq(_T_424, UInt<1>(0h0))
node _T_426 = asUInt(reset)
node _T_427 = eq(_T_426, UInt<1>(0h0))
when _T_427 :
node _T_428 = eq(_T_425, UInt<1>(0h0))
when _T_428 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_55
assert(clock, _T_425, UInt<1>(0h1), "") : assert_55
node _T_429 = eq(before, UInt<3>(0h4))
node _T_430 = eq(after, UInt<3>(0h6))
node _T_431 = and(_T_429, _T_430)
node _T_432 = eq(before, UInt<3>(0h4))
node _T_433 = eq(after, UInt<2>(0h3))
node _T_434 = and(_T_432, _T_433)
node _T_435 = eq(_T_434, UInt<1>(0h0))
node _T_436 = asUInt(reset)
node _T_437 = eq(_T_436, UInt<1>(0h0))
when _T_437 :
node _T_438 = eq(_T_435, UInt<1>(0h0))
when _T_438 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_56
assert(clock, _T_435, UInt<1>(0h1), "") : assert_56
node _T_439 = eq(before, UInt<3>(0h4))
node _T_440 = eq(after, UInt<2>(0h2))
node _T_441 = and(_T_439, _T_440)
node _T_442 = eq(before, UInt<2>(0h3))
node _T_443 = eq(after, UInt<4>(0h8))
node _T_444 = and(_T_442, _T_443)
node _T_445 = eq(_T_444, UInt<1>(0h0))
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_57
assert(clock, _T_445, UInt<1>(0h1), "") : assert_57
node _T_449 = eq(before, UInt<2>(0h3))
node _T_450 = eq(after, UInt<1>(0h1))
node _T_451 = and(_T_449, _T_450)
node _T_452 = eq(_T_451, UInt<1>(0h0))
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(_T_452, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_58
assert(clock, _T_452, UInt<1>(0h1), "") : assert_58
node _T_456 = eq(before, UInt<2>(0h3))
node _T_457 = eq(after, UInt<1>(0h0))
node _T_458 = and(_T_456, _T_457)
node _T_459 = eq(_T_458, UInt<1>(0h0))
node _T_460 = asUInt(reset)
node _T_461 = eq(_T_460, UInt<1>(0h0))
when _T_461 :
node _T_462 = eq(_T_459, UInt<1>(0h0))
when _T_462 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_59
assert(clock, _T_459, UInt<1>(0h1), "") : assert_59
node _T_463 = eq(before, UInt<2>(0h3))
node _T_464 = eq(after, UInt<3>(0h7))
node _T_465 = and(_T_463, _T_464)
node _T_466 = eq(before, UInt<2>(0h3))
node _T_467 = eq(after, UInt<3>(0h5))
node _T_468 = and(_T_466, _T_467)
node _T_469 = eq(before, UInt<2>(0h3))
node _T_470 = eq(after, UInt<3>(0h6))
node _T_471 = and(_T_469, _T_470)
node _T_472 = eq(before, UInt<2>(0h3))
node _T_473 = eq(after, UInt<3>(0h4))
node _T_474 = and(_T_472, _T_473)
node _T_475 = eq(before, UInt<2>(0h3))
node _T_476 = eq(after, UInt<2>(0h2))
node _T_477 = and(_T_475, _T_476)
node _T_478 = eq(before, UInt<2>(0h2))
node _T_479 = eq(after, UInt<4>(0h8))
node _T_480 = and(_T_478, _T_479)
node _T_481 = eq(_T_480, UInt<1>(0h0))
node _T_482 = asUInt(reset)
node _T_483 = eq(_T_482, UInt<1>(0h0))
when _T_483 :
node _T_484 = eq(_T_481, UInt<1>(0h0))
when _T_484 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_60
assert(clock, _T_481, UInt<1>(0h1), "") : assert_60
node _T_485 = eq(before, UInt<2>(0h2))
node _T_486 = eq(after, UInt<1>(0h1))
node _T_487 = and(_T_485, _T_486)
node _T_488 = eq(_T_487, UInt<1>(0h0))
node _T_489 = asUInt(reset)
node _T_490 = eq(_T_489, UInt<1>(0h0))
when _T_490 :
node _T_491 = eq(_T_488, UInt<1>(0h0))
when _T_491 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_61
assert(clock, _T_488, UInt<1>(0h1), "") : assert_61
node _T_492 = eq(before, UInt<2>(0h2))
node _T_493 = eq(after, UInt<1>(0h0))
node _T_494 = and(_T_492, _T_493)
node _T_495 = eq(_T_494, UInt<1>(0h0))
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(_T_495, UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_62
assert(clock, _T_495, UInt<1>(0h1), "") : assert_62
node _T_499 = eq(before, UInt<2>(0h2))
node _T_500 = eq(after, UInt<3>(0h7))
node _T_501 = and(_T_499, _T_500)
node _T_502 = eq(_T_501, UInt<1>(0h0))
node _T_503 = asUInt(reset)
node _T_504 = eq(_T_503, UInt<1>(0h0))
when _T_504 :
node _T_505 = eq(_T_502, UInt<1>(0h0))
when _T_505 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_63
assert(clock, _T_502, UInt<1>(0h1), "") : assert_63
node _T_506 = eq(before, UInt<2>(0h2))
node _T_507 = eq(after, UInt<3>(0h5))
node _T_508 = and(_T_506, _T_507)
node _T_509 = eq(_T_508, UInt<1>(0h0))
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_T_509, UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_64
assert(clock, _T_509, UInt<1>(0h1), "") : assert_64
node _T_513 = eq(before, UInt<2>(0h2))
node _T_514 = eq(after, UInt<3>(0h6))
node _T_515 = and(_T_513, _T_514)
node _T_516 = eq(before, UInt<2>(0h2))
node _T_517 = eq(after, UInt<3>(0h4))
node _T_518 = and(_T_516, _T_517)
node _T_519 = eq(before, UInt<2>(0h2))
node _T_520 = eq(after, UInt<2>(0h3))
node _T_521 = and(_T_519, _T_520)
node _T_522 = eq(_T_521, UInt<1>(0h0))
node _T_523 = asUInt(reset)
node _T_524 = eq(_T_523, UInt<1>(0h0))
when _T_524 :
node _T_525 = eq(_T_522, UInt<1>(0h0))
when _T_525 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_65
assert(clock, _T_522, UInt<1>(0h1), "") : assert_65
node _probe_bit_uncommonBits_T = or(io.sinkc.bits.source, UInt<3>(0h0))
node probe_bit_uncommonBits = bits(_probe_bit_uncommonBits_T, 2, 0)
node _probe_bit_T = shr(io.sinkc.bits.source, 3)
node _probe_bit_T_1 = eq(_probe_bit_T, UInt<2>(0h2))
node _probe_bit_T_2 = leq(UInt<1>(0h0), probe_bit_uncommonBits)
node _probe_bit_T_3 = and(_probe_bit_T_1, _probe_bit_T_2)
node _probe_bit_T_4 = leq(probe_bit_uncommonBits, UInt<3>(0h7))
node probe_bit = and(_probe_bit_T_3, _probe_bit_T_4)
node _last_probe_T = or(probes_done, probe_bit)
node _last_probe_T_1 = not(excluded_client)
node _last_probe_T_2 = and(meta.clients, _last_probe_T_1)
node last_probe = eq(_last_probe_T, _last_probe_T_2)
node _probe_toN_T = eq(io.sinkc.bits.param, UInt<3>(0h1))
node _probe_toN_T_1 = eq(io.sinkc.bits.param, UInt<3>(0h2))
node _probe_toN_T_2 = or(_probe_toN_T, _probe_toN_T_1)
node _probe_toN_T_3 = eq(io.sinkc.bits.param, UInt<3>(0h5))
node probe_toN = or(_probe_toN_T_2, _probe_toN_T_3)
when io.sinkc.valid :
node _T_526 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1))
node _T_527 = and(probe_toN, _T_526)
node _T_528 = eq(probe_toN, UInt<1>(0h0))
node _T_529 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1))
node _T_530 = and(_T_528, _T_529)
node _probes_done_T = or(probes_done, probe_bit)
connect probes_done, _probes_done_T
node _probes_toN_T = mux(probe_toN, probe_bit, UInt<1>(0h0))
node _probes_toN_T_1 = or(probes_toN, _probes_toN_T)
connect probes_toN, _probes_toN_T_1
node _probes_noT_T = neq(io.sinkc.bits.param, UInt<3>(0h3))
node _probes_noT_T_1 = or(probes_noT, _probes_noT_T)
connect probes_noT, _probes_noT_T_1
node _w_rprobeackfirst_T = or(w_rprobeackfirst, last_probe)
connect w_rprobeackfirst, _w_rprobeackfirst_T
node _w_rprobeacklast_T = and(last_probe, io.sinkc.bits.last)
node _w_rprobeacklast_T_1 = or(w_rprobeacklast, _w_rprobeacklast_T)
connect w_rprobeacklast, _w_rprobeacklast_T_1
node _w_pprobeackfirst_T = or(w_pprobeackfirst, last_probe)
connect w_pprobeackfirst, _w_pprobeackfirst_T
node _w_pprobeacklast_T = and(last_probe, io.sinkc.bits.last)
node _w_pprobeacklast_T_1 = or(w_pprobeacklast, _w_pprobeacklast_T)
connect w_pprobeacklast, _w_pprobeacklast_T_1
node _set_pprobeack_T = eq(request.offset, UInt<1>(0h0))
node _set_pprobeack_T_1 = or(io.sinkc.bits.last, _set_pprobeack_T)
node set_pprobeack = and(last_probe, _set_pprobeack_T_1)
node _w_pprobeack_T = or(w_pprobeack, set_pprobeack)
connect w_pprobeack, _w_pprobeack_T
node _T_531 = eq(set_pprobeack, UInt<1>(0h0))
node _T_532 = and(_T_531, w_rprobeackfirst)
node _T_533 = and(set_pprobeack, w_rprobeackfirst)
node _T_534 = neq(meta.state, UInt<2>(0h0))
node _T_535 = eq(io.sinkc.bits.tag, meta.tag)
node _T_536 = and(_T_534, _T_535)
node _T_537 = and(_T_536, io.sinkc.bits.data)
when _T_537 :
connect meta.dirty, UInt<1>(0h1)
when io.sinkd.valid :
node _T_538 = eq(io.sinkd.bits.opcode, UInt<3>(0h4))
node _T_539 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_540 = or(_T_538, _T_539)
when _T_540 :
connect sink, io.sinkd.bits.sink
connect w_grantfirst, UInt<1>(0h1)
connect w_grantlast, io.sinkd.bits.last
connect bad_grant, io.sinkd.bits.denied
node _w_grant_T = eq(request.offset, UInt<1>(0h0))
node _w_grant_T_1 = or(_w_grant_T, io.sinkd.bits.last)
connect w_grant, _w_grant_T_1
node _T_541 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_542 = eq(request.offset, UInt<1>(0h0))
node _T_543 = and(_T_541, _T_542)
node _T_544 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_545 = neq(request.offset, UInt<1>(0h0))
node _T_546 = and(_T_544, _T_545)
node _gotT_T = eq(io.sinkd.bits.param, UInt<2>(0h0))
connect gotT, _gotT_T
else :
node _T_547 = eq(io.sinkd.bits.opcode, UInt<3>(0h6))
when _T_547 :
connect w_releaseack, UInt<1>(0h1)
when io.sinke.valid :
connect w_grantack, UInt<1>(0h1)
wire allocate_as_full : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>}
connect allocate_as_full.set, io.allocate.bits.set
connect allocate_as_full.put, io.allocate.bits.put
connect allocate_as_full.offset, io.allocate.bits.offset
connect allocate_as_full.tag, io.allocate.bits.tag
connect allocate_as_full.source, io.allocate.bits.source
connect allocate_as_full.size, io.allocate.bits.size
connect allocate_as_full.param, io.allocate.bits.param
connect allocate_as_full.opcode, io.allocate.bits.opcode
connect allocate_as_full.control, io.allocate.bits.control
connect allocate_as_full.prio, io.allocate.bits.prio
node _new_meta_T = and(io.allocate.valid, io.allocate.bits.repeat)
node new_meta = mux(_new_meta_T, final_meta_writeback, io.directory.bits)
node new_request = mux(io.allocate.valid, allocate_as_full, request)
node _new_needT_T = bits(new_request.opcode, 2, 2)
node _new_needT_T_1 = eq(_new_needT_T, UInt<1>(0h0))
node _new_needT_T_2 = eq(new_request.opcode, UInt<3>(0h5))
node _new_needT_T_3 = eq(new_request.param, UInt<1>(0h1))
node _new_needT_T_4 = and(_new_needT_T_2, _new_needT_T_3)
node _new_needT_T_5 = or(_new_needT_T_1, _new_needT_T_4)
node _new_needT_T_6 = eq(new_request.opcode, UInt<3>(0h6))
node _new_needT_T_7 = eq(new_request.opcode, UInt<3>(0h7))
node _new_needT_T_8 = or(_new_needT_T_6, _new_needT_T_7)
node _new_needT_T_9 = neq(new_request.param, UInt<2>(0h0))
node _new_needT_T_10 = and(_new_needT_T_8, _new_needT_T_9)
node new_needT = or(_new_needT_T_5, _new_needT_T_10)
node _new_clientBit_uncommonBits_T = or(new_request.source, UInt<3>(0h0))
node new_clientBit_uncommonBits = bits(_new_clientBit_uncommonBits_T, 2, 0)
node _new_clientBit_T = shr(new_request.source, 3)
node _new_clientBit_T_1 = eq(_new_clientBit_T, UInt<2>(0h2))
node _new_clientBit_T_2 = leq(UInt<1>(0h0), new_clientBit_uncommonBits)
node _new_clientBit_T_3 = and(_new_clientBit_T_1, _new_clientBit_T_2)
node _new_clientBit_T_4 = leq(new_clientBit_uncommonBits, UInt<3>(0h7))
node new_clientBit = and(_new_clientBit_T_3, _new_clientBit_T_4)
node _new_skipProbe_T = eq(new_request.opcode, UInt<3>(0h6))
node _new_skipProbe_T_1 = eq(new_request.opcode, UInt<3>(0h7))
node _new_skipProbe_T_2 = or(_new_skipProbe_T, _new_skipProbe_T_1)
node _new_skipProbe_T_3 = eq(new_request.opcode, UInt<3>(0h4))
node _new_skipProbe_T_4 = or(_new_skipProbe_T_2, _new_skipProbe_T_3)
node _new_skipProbe_T_5 = eq(new_request.opcode, UInt<3>(0h5))
node _new_skipProbe_T_6 = and(_new_skipProbe_T_5, UInt<1>(0h0))
node _new_skipProbe_T_7 = or(_new_skipProbe_T_4, _new_skipProbe_T_6)
node new_skipProbe = mux(_new_skipProbe_T_7, new_clientBit, UInt<1>(0h0))
wire prior : UInt
connect prior, UInt<1>(0h0)
node prior_c = orr(final_meta_writeback.clients)
node _prior_T = eq(UInt<2>(0h1), final_meta_writeback.state)
when _prior_T :
node _prior_out_T = mux(prior_c, UInt<1>(0h0), UInt<1>(0h1))
connect prior, _prior_out_T
else :
node _prior_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state)
when _prior_T_1 :
node _prior_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect prior, _prior_out_T_1
else :
node _prior_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state)
when _prior_T_2 :
node _prior_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _prior_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _prior_out_T_4 = mux(prior_c, _prior_out_T_2, _prior_out_T_3)
connect prior, _prior_out_T_4
else :
node _prior_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state)
when _prior_T_3 :
connect prior, UInt<4>(0h8)
node _prior_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0))
when _prior_T_4 :
connect prior, UInt<4>(0h8)
node _T_548 = and(io.allocate.valid, io.allocate.bits.repeat)
when _T_548 :
node _T_549 = eq(prior, UInt<4>(0h8))
node _T_550 = eq(prior, UInt<1>(0h1))
node _T_551 = eq(_T_550, UInt<1>(0h0))
node _T_552 = asUInt(reset)
node _T_553 = eq(_T_552, UInt<1>(0h0))
when _T_553 :
node _T_554 = eq(_T_551, UInt<1>(0h0))
when _T_554 :
printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_66
assert(clock, _T_551, UInt<1>(0h1), "") : assert_66
node _T_555 = eq(prior, UInt<1>(0h0))
node _T_556 = eq(_T_555, UInt<1>(0h0))
node _T_557 = asUInt(reset)
node _T_558 = eq(_T_557, UInt<1>(0h0))
when _T_558 :
node _T_559 = eq(_T_556, UInt<1>(0h0))
when _T_559 :
printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_67
assert(clock, _T_556, UInt<1>(0h1), "") : assert_67
node _T_560 = eq(prior, UInt<3>(0h7))
node _T_561 = eq(prior, UInt<3>(0h5))
node _T_562 = eq(prior, UInt<3>(0h4))
node _T_563 = eq(prior, UInt<3>(0h6))
node _T_564 = eq(prior, UInt<2>(0h3))
node _T_565 = eq(prior, UInt<2>(0h2))
when io.allocate.valid :
node _T_566 = eq(request_valid, UInt<1>(0h0))
node _T_567 = and(io.schedule.ready, io.schedule.valid)
node _T_568 = and(no_wait, _T_567)
node _T_569 = or(_T_566, _T_568)
node _T_570 = asUInt(reset)
node _T_571 = eq(_T_570, UInt<1>(0h0))
when _T_571 :
node _T_572 = eq(_T_569, UInt<1>(0h0))
when _T_572 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:533 assert (!request_valid || (no_wait && io.schedule.fire))\n") : printf_68
assert(clock, _T_569, UInt<1>(0h1), "") : assert_68
connect request_valid, UInt<1>(0h1)
connect request.set, io.allocate.bits.set
connect request.put, io.allocate.bits.put
connect request.offset, io.allocate.bits.offset
connect request.tag, io.allocate.bits.tag
connect request.source, io.allocate.bits.source
connect request.size, io.allocate.bits.size
connect request.param, io.allocate.bits.param
connect request.opcode, io.allocate.bits.opcode
connect request.control, io.allocate.bits.control
connect request.prio, io.allocate.bits.prio
node _T_573 = and(io.allocate.valid, io.allocate.bits.repeat)
node _T_574 = or(io.directory.valid, _T_573)
when _T_574 :
connect meta_valid, UInt<1>(0h1)
connect meta, new_meta
connect probes_done, UInt<1>(0h0)
connect probes_toN, UInt<1>(0h0)
connect probes_noT, UInt<1>(0h0)
connect gotT, UInt<1>(0h0)
connect bad_grant, UInt<1>(0h0)
connect s_rprobe, UInt<1>(0h1)
connect w_rprobeackfirst, UInt<1>(0h1)
connect w_rprobeacklast, UInt<1>(0h1)
connect s_release, UInt<1>(0h1)
connect w_releaseack, UInt<1>(0h1)
connect s_pprobe, UInt<1>(0h1)
connect s_acquire, UInt<1>(0h1)
connect s_flush, UInt<1>(0h1)
connect w_grantfirst, UInt<1>(0h1)
connect w_grantlast, UInt<1>(0h1)
connect w_grant, UInt<1>(0h1)
connect w_pprobeackfirst, UInt<1>(0h1)
connect w_pprobeacklast, UInt<1>(0h1)
connect w_pprobeack, UInt<1>(0h1)
connect s_probeack, UInt<1>(0h1)
connect s_grantack, UInt<1>(0h1)
connect s_execute, UInt<1>(0h1)
connect w_grantack, UInt<1>(0h1)
connect s_writeback, UInt<1>(0h1)
node _T_575 = and(new_request.prio[2], UInt<1>(0h1))
when _T_575 :
connect s_execute, UInt<1>(0h0)
node _T_576 = bits(new_request.opcode, 0, 0)
node _T_577 = eq(new_meta.dirty, UInt<1>(0h0))
node _T_578 = and(_T_576, _T_577)
when _T_578 :
connect s_writeback, UInt<1>(0h0)
node _T_579 = eq(new_request.param, UInt<3>(0h0))
node _T_580 = eq(new_request.param, UInt<3>(0h4))
node _T_581 = or(_T_579, _T_580)
node _T_582 = eq(new_meta.state, UInt<2>(0h2))
node _T_583 = and(_T_581, _T_582)
when _T_583 :
connect s_writeback, UInt<1>(0h0)
node _T_584 = eq(new_request.param, UInt<3>(0h1))
node _T_585 = eq(new_request.param, UInt<3>(0h2))
node _T_586 = or(_T_584, _T_585)
node _T_587 = eq(new_request.param, UInt<3>(0h5))
node _T_588 = or(_T_586, _T_587)
node _T_589 = and(new_meta.clients, new_clientBit)
node _T_590 = neq(_T_589, UInt<1>(0h0))
node _T_591 = and(_T_588, _T_590)
when _T_591 :
connect s_writeback, UInt<1>(0h0)
node _T_592 = asUInt(reset)
node _T_593 = eq(_T_592, UInt<1>(0h0))
when _T_593 :
node _T_594 = eq(new_meta.hit, UInt<1>(0h0))
when _T_594 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:585 assert (new_meta.hit)\n") : printf_69
assert(clock, new_meta.hit, UInt<1>(0h1), "") : assert_69
else :
node _T_595 = and(new_request.control, UInt<1>(0h1))
when _T_595 :
connect s_flush, UInt<1>(0h0)
when new_meta.hit :
connect s_release, UInt<1>(0h0)
connect w_releaseack, UInt<1>(0h0)
node _T_596 = neq(new_meta.clients, UInt<1>(0h0))
node _T_597 = and(UInt<1>(0h1), _T_596)
when _T_597 :
connect s_rprobe, UInt<1>(0h0)
connect w_rprobeackfirst, UInt<1>(0h0)
connect w_rprobeacklast, UInt<1>(0h0)
else :
connect s_execute, UInt<1>(0h0)
node _T_598 = eq(new_meta.hit, UInt<1>(0h0))
node _T_599 = neq(new_meta.state, UInt<2>(0h0))
node _T_600 = and(_T_598, _T_599)
when _T_600 :
connect s_release, UInt<1>(0h0)
connect w_releaseack, UInt<1>(0h0)
node _T_601 = neq(new_meta.clients, UInt<1>(0h0))
node _T_602 = and(UInt<1>(0h1), _T_601)
when _T_602 :
connect s_rprobe, UInt<1>(0h0)
connect w_rprobeackfirst, UInt<1>(0h0)
connect w_rprobeacklast, UInt<1>(0h0)
node _T_603 = eq(new_meta.hit, UInt<1>(0h0))
node _T_604 = eq(new_meta.state, UInt<2>(0h1))
node _T_605 = and(_T_604, new_needT)
node _T_606 = or(_T_603, _T_605)
when _T_606 :
connect s_acquire, UInt<1>(0h0)
connect w_grantfirst, UInt<1>(0h0)
connect w_grantlast, UInt<1>(0h0)
connect w_grant, UInt<1>(0h0)
connect s_grantack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_607 = eq(new_meta.state, UInt<2>(0h2))
node _T_608 = or(new_needT, _T_607)
node _T_609 = and(new_meta.hit, _T_608)
node _T_610 = not(new_skipProbe)
node _T_611 = and(new_meta.clients, _T_610)
node _T_612 = neq(_T_611, UInt<1>(0h0))
node _T_613 = and(_T_609, _T_612)
node _T_614 = and(UInt<1>(0h1), _T_613)
when _T_614 :
connect s_pprobe, UInt<1>(0h0)
connect w_pprobeackfirst, UInt<1>(0h0)
connect w_pprobeacklast, UInt<1>(0h0)
connect w_pprobeack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_615 = eq(new_request.opcode, UInt<3>(0h6))
node _T_616 = eq(new_request.opcode, UInt<3>(0h7))
node _T_617 = or(_T_615, _T_616)
when _T_617 :
connect w_grantack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_618 = bits(new_request.opcode, 2, 2)
node _T_619 = eq(_T_618, UInt<1>(0h0))
node _T_620 = and(_T_619, new_meta.hit)
node _T_621 = eq(new_meta.dirty, UInt<1>(0h0))
node _T_622 = and(_T_620, _T_621)
when _T_622 :
connect s_writeback, UInt<1>(0h0) | module MSHR_6( // @[MSHR.scala:84:7]
input clock, // @[MSHR.scala:84:7]
input reset, // @[MSHR.scala:84:7]
input io_allocate_valid, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_2, // @[MSHR.scala:86:14]
input io_allocate_bits_control, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14]
input [12:0] io_allocate_bits_tag, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14]
input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14]
input io_allocate_bits_repeat, // @[MSHR.scala:86:14]
input io_directory_valid, // @[MSHR.scala:86:14]
input io_directory_bits_dirty, // @[MSHR.scala:86:14]
input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14]
input io_directory_bits_clients, // @[MSHR.scala:86:14]
input [12:0] io_directory_bits_tag, // @[MSHR.scala:86:14]
input io_directory_bits_hit, // @[MSHR.scala:86:14]
input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14]
output io_status_valid, // @[MSHR.scala:86:14]
output [9:0] io_status_bits_set, // @[MSHR.scala:86:14]
output [12:0] io_status_bits_tag, // @[MSHR.scala:86:14]
output [2:0] io_status_bits_way, // @[MSHR.scala:86:14]
output io_status_bits_blockB, // @[MSHR.scala:86:14]
output io_status_bits_nestB, // @[MSHR.scala:86:14]
output io_status_bits_blockC, // @[MSHR.scala:86:14]
output io_status_bits_nestC, // @[MSHR.scala:86:14]
input io_schedule_ready, // @[MSHR.scala:86:14]
output io_schedule_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_a_valid, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14]
output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14]
output io_schedule_bits_b_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14]
output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14]
output io_schedule_bits_c_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14]
output io_schedule_bits_d_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14]
output io_schedule_bits_e_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14]
output io_schedule_bits_x_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14]
output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14]
output io_schedule_bits_reload, // @[MSHR.scala:86:14]
input io_sinkc_valid, // @[MSHR.scala:86:14]
input io_sinkc_bits_last, // @[MSHR.scala:86:14]
input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14]
input [12:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14]
input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14]
input io_sinkc_bits_data, // @[MSHR.scala:86:14]
input io_sinkd_valid, // @[MSHR.scala:86:14]
input io_sinkd_bits_last, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14]
input io_sinkd_bits_denied, // @[MSHR.scala:86:14]
input io_sinke_valid, // @[MSHR.scala:86:14]
input [2:0] io_sinke_bits_sink, // @[MSHR.scala:86:14]
input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14]
input [12:0] io_nestedwb_tag, // @[MSHR.scala:86:14]
input io_nestedwb_b_toN, // @[MSHR.scala:86:14]
input io_nestedwb_b_toB, // @[MSHR.scala:86:14]
input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14]
input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14]
);
wire [12:0] final_meta_writeback_tag; // @[MSHR.scala:215:38]
wire final_meta_writeback_clients; // @[MSHR.scala:215:38]
wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38]
wire final_meta_writeback_dirty; // @[MSHR.scala:215:38]
wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7]
wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7]
wire [12:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7]
wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7]
wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7]
wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7]
wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7]
wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7]
wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7]
wire [12:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7]
wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7]
wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7]
wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7]
wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7]
wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7]
wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7]
wire [12:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7]
wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7]
wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7]
wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7]
wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7]
wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7]
wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7]
wire [2:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7]
wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7]
wire [12:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7]
wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7]
wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_0 = 1'h0; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_1 = 1'h0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_0 = 1'h0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_1 = 1'h0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7]
wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68]
wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80]
wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21]
wire invalid_clients = 1'h0; // @[MSHR.scala:268:21]
wire _excluded_client_T = 1'h0; // @[MSHR.scala:279:38]
wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137]
wire _excluded_client_T_9 = 1'h0; // @[MSHR.scala:279:57]
wire excluded_client = 1'h0; // @[MSHR.scala:279:28]
wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire allocate_as_full_prio_0 = 1'h0; // @[MSHR.scala:504:34]
wire allocate_as_full_prio_1 = 1'h0; // @[MSHR.scala:504:34]
wire new_request_prio_0 = 1'h0; // @[MSHR.scala:506:24]
wire new_request_prio_1 = 1'h0; // @[MSHR.scala:506:24]
wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137]
wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire _req_clientBit_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _req_clientBit_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire _io_schedule_bits_b_bits_clients_T = 1'h1; // @[MSHR.scala:289:53]
wire _probe_bit_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _probe_bit_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire _last_probe_T_1 = 1'h1; // @[MSHR.scala:459:66]
wire _new_clientBit_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _new_clientBit_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire [2:0] io_schedule_bits_a_bits_source = 3'h0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_source = 3'h0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_sink = 3'h0; // @[MSHR.scala:84:7]
wire [12:0] invalid_tag = 13'h0; // @[MSHR.scala:268:21]
wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21]
wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70]
wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34]
wire [12:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34]
wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34]
wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40]
wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93]
wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28]
wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39]
wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105]
wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55]
wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91]
wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41]
wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41]
wire [12:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41]
wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51]
wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64]
wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41]
wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41]
wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57]
wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41]
wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43]
wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40]
wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66]
wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41]
wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41]
wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41]
wire [12:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41]
wire no_wait; // @[MSHR.scala:183:83]
wire [5:0] _probe_bit_uncommonBits_T = io_sinkc_bits_source_0; // @[Parameters.scala:52:29]
wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7]
wire [12:0] io_status_bits_tag_0; // @[MSHR.scala:84:7]
wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockB_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestB_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockC_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestC_0; // @[MSHR.scala:84:7]
wire io_status_valid_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7]
wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7]
wire io_schedule_valid_0; // @[MSHR.scala:84:7]
reg request_valid; // @[MSHR.scala:97:30]
assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30]
reg request_prio_2; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20]
reg request_control; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_opcode; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_param; // @[MSHR.scala:98:20]
reg [2:0] request_size; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_source; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20]
wire [5:0] _req_clientBit_uncommonBits_T = request_source; // @[Parameters.scala:52:29]
reg [12:0] request_tag; // @[MSHR.scala:98:20]
assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_offset; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_put; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20]
reg [9:0] request_set; // @[MSHR.scala:98:20]
assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
reg meta_valid; // @[MSHR.scala:99:27]
reg meta_dirty; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17]
reg [1:0] meta_state; // @[MSHR.scala:100:17]
reg meta_clients; // @[MSHR.scala:100:17]
wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39]
assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients; // @[MSHR.scala:100:17, :289:51]
wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27]
wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27]
wire _last_probe_T_2 = meta_clients; // @[MSHR.scala:100:17, :459:64]
reg [12:0] meta_tag; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17]
reg meta_hit; // @[MSHR.scala:100:17]
reg [2:0] meta_way; // @[MSHR.scala:100:17]
assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38]
reg s_rprobe; // @[MSHR.scala:121:33]
reg w_rprobeackfirst; // @[MSHR.scala:122:33]
reg w_rprobeacklast; // @[MSHR.scala:123:33]
reg s_release; // @[MSHR.scala:124:33]
reg w_releaseack; // @[MSHR.scala:125:33]
reg s_pprobe; // @[MSHR.scala:126:33]
reg s_acquire; // @[MSHR.scala:127:33]
reg s_flush; // @[MSHR.scala:128:33]
reg w_grantfirst; // @[MSHR.scala:129:33]
reg w_grantlast; // @[MSHR.scala:130:33]
reg w_grant; // @[MSHR.scala:131:33]
reg w_pprobeackfirst; // @[MSHR.scala:132:33]
reg w_pprobeacklast; // @[MSHR.scala:133:33]
reg w_pprobeack; // @[MSHR.scala:134:33]
reg s_grantack; // @[MSHR.scala:136:33]
reg s_execute; // @[MSHR.scala:137:33]
reg w_grantack; // @[MSHR.scala:138:33]
reg s_writeback; // @[MSHR.scala:139:33]
reg [2:0] sink; // @[MSHR.scala:147:17]
assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17]
reg gotT; // @[MSHR.scala:148:17]
reg bad_grant; // @[MSHR.scala:149:22]
assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22]
reg probes_done; // @[MSHR.scala:150:24]
reg probes_toN; // @[MSHR.scala:151:23]
reg probes_noT; // @[MSHR.scala:152:23]
wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28]
wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45]
wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62]
wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}]
wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82]
wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}]
wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103]
wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}]
assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}]
assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40]
wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39]
wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}]
wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}]
wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96]
assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}]
assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93]
assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28]
assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28]
wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43]
wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64]
wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}]
wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85]
wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}]
assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}]
assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39]
wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33]
wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}]
wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}]
assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}]
assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83]
wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31]
wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}]
assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}]
assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55]
wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31]
wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44]
assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}]
assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41]
wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32]
wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}]
assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}]
assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64]
wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31]
wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}]
assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}]
assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57]
wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31]
assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}]
assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43]
wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31]
assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}]
assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40]
wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34]
wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}]
wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70]
wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}]
assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}]
assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66]
wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49]
wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}]
wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}]
wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49]
wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}]
assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}]
assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105]
wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71]
wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71]
wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71]
wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire [12:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71]
wire final_meta_writeback_hit; // @[MSHR.scala:215:38]
wire [2:0] req_clientBit_uncommonBits = _req_clientBit_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] _req_clientBit_T = request_source[5:3]; // @[Parameters.scala:54:10]
wire _req_clientBit_T_1 = _req_clientBit_T == 3'h2; // @[Parameters.scala:54:{10,32}]
wire _req_clientBit_T_3 = _req_clientBit_T_1; // @[Parameters.scala:54:{32,67}]
wire req_clientBit = _req_clientBit_T_3; // @[Parameters.scala:54:67, :56:48]
wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12]
wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12]
wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _req_needT_T_2; // @[Parameters.scala:270:13]
assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13]
wire _excluded_client_T_6; // @[Parameters.scala:279:117]
assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117]
wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42]
wire _req_needT_T_3; // @[Parameters.scala:270:42]
assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42]
wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11]
assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11]
wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42]
wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _req_needT_T_6; // @[Parameters.scala:271:14]
assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14]
wire _req_acquire_T; // @[MSHR.scala:219:36]
assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14]
wire _excluded_client_T_1; // @[Parameters.scala:279:12]
assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12]
wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52]
wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89]
wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52]
wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}]
wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}]
wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81]
wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}]
wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}]
wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}]
wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65]
wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}]
wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55]
wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78]
wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78]
assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78]
wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70]
wire _evict_T_2; // @[MSHR.scala:317:26]
assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _before_T_1; // @[MSHR.scala:317:26]
assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}]
wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}]
wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43]
assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43]
wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75]
wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}]
wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:56:48]
wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}]
wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}]
wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54]
wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}]
wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45]
wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}]
wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}]
wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40]
wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40]
assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40]
wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65]
assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65]
wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41]
wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}]
wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72]
wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}]
wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70]
wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70]
wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53]
assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53]
wire _evict_T_1; // @[MSHR.scala:317:26]
assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire _before_T; // @[MSHR.scala:317:26]
assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70]
wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70]
wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55]
wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70]
wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70]
wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66]
wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}]
wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}]
wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:56:48]
wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40]
assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30]
wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54]
wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}]
assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21]
assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21]
assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36]
assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36]
wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:56:48]
wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}]
wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}]
wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}]
wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}]
wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}]
wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56]
wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70]
assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}]
wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51]
wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55]
wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52]
wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}]
wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}]
assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38]
assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91]
wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42]
wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70]
wire [2:0] _io_schedule_bits_b_bits_param_T_2 = {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:286:{61,97}]
assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}]
assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41]
wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42]
assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}]
assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41]
assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51]
assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41]
assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41]
assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}]
assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41]
wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42]
wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53]
wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53]
wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89]
wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79]
assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41]
wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42]
assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 13'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}]
assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41]
wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32]
wire [3:0] evict; // @[MSHR.scala:314:26]
wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32]
wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32]
wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32]
assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32]
assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39]
wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39]
assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39]
assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76]
wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76]
assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76]
assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32]
assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] before_0; // @[MSHR.scala:314:26]
wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32]
wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11]
assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] after; // @[MSHR.scala:314:26]
wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26]
wire _after_T; // @[MSHR.scala:317:26]
assign _after_T = _GEN_9; // @[MSHR.scala:317:26]
wire _prior_T; // @[MSHR.scala:317:26]
assign _prior_T = _GEN_9; // @[MSHR.scala:317:26]
wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32]
wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26]
wire _after_T_1; // @[MSHR.scala:317:26]
assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire _prior_T_1; // @[MSHR.scala:317:26]
assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32]
wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32]
assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32]
assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39]
wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39]
assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39]
assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76]
wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76]
assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76]
assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26]
wire _after_T_3; // @[MSHR.scala:317:26]
assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26]
wire _prior_T_3; // @[MSHR.scala:317:26]
assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26]
assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire [2:0] probe_bit_uncommonBits = _probe_bit_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] _probe_bit_T = io_sinkc_bits_source_0[5:3]; // @[Parameters.scala:54:10]
wire _probe_bit_T_1 = _probe_bit_T == 3'h2; // @[Parameters.scala:54:{10,32}]
wire _probe_bit_T_3 = _probe_bit_T_1; // @[Parameters.scala:54:{32,67}]
wire probe_bit = _probe_bit_T_3; // @[Parameters.scala:54:67, :56:48]
wire _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:56:48]
wire _last_probe_T; // @[MSHR.scala:459:33]
assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33]
wire _probes_done_T; // @[MSHR.scala:467:32]
assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32]
wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}]
wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11]
wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43]
wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75]
wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}]
wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:56:48]
wire _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}]
wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53]
wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}]
wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42]
wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55]
wire _w_rprobeacklast_T; // @[MSHR.scala:471:55]
assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55]
wire _w_pprobeacklast_T; // @[MSHR.scala:473:55]
assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55]
wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}]
wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42]
wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}]
wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77]
wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}]
wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}]
wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32]
wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33]
wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}]
wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35]
wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40]
wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [12:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [12:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] _new_clientBit_uncommonBits_T = new_request_source; // @[Parameters.scala:52:29]
wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12]
wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _new_needT_T_2; // @[Parameters.scala:270:13]
assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13]
wire _new_skipProbe_T_5; // @[Parameters.scala:279:117]
assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117]
wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42]
wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _new_needT_T_6; // @[Parameters.scala:271:14]
assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14]
wire _new_skipProbe_T; // @[Parameters.scala:279:12]
assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12]
wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52]
wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89]
wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire [2:0] new_clientBit_uncommonBits = _new_clientBit_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] _new_clientBit_T = new_request_source[5:3]; // @[Parameters.scala:54:10]
wire _new_clientBit_T_1 = _new_clientBit_T == 3'h2; // @[Parameters.scala:54:{10,32}]
wire _new_clientBit_T_3 = _new_clientBit_T_1; // @[Parameters.scala:54:{32,67}]
wire new_clientBit = _new_clientBit_T_3; // @[Parameters.scala:54:67, :56:48]
wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}]
wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}]
wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}]
wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:56:48]
wire [3:0] prior; // @[MSHR.scala:314:26]
wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32]
wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire _T_574 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28] |
Generate the Verilog code corresponding to this FIRRTL code module MulRecFN_22 :
output io : { flip a : UInt<33>, flip b : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
inst mulRawFN of MulRawFN_22
node mulRawFN_io_a_exp = bits(io.a, 31, 23)
node _mulRawFN_io_a_isZero_T = bits(mulRawFN_io_a_exp, 8, 6)
node mulRawFN_io_a_isZero = eq(_mulRawFN_io_a_isZero_T, UInt<1>(0h0))
node _mulRawFN_io_a_isSpecial_T = bits(mulRawFN_io_a_exp, 8, 7)
node mulRawFN_io_a_isSpecial = eq(_mulRawFN_io_a_isSpecial_T, UInt<2>(0h3))
wire mulRawFN_io_a_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _mulRawFN_io_a_out_isNaN_T = bits(mulRawFN_io_a_exp, 6, 6)
node _mulRawFN_io_a_out_isNaN_T_1 = and(mulRawFN_io_a_isSpecial, _mulRawFN_io_a_out_isNaN_T)
connect mulRawFN_io_a_out.isNaN, _mulRawFN_io_a_out_isNaN_T_1
node _mulRawFN_io_a_out_isInf_T = bits(mulRawFN_io_a_exp, 6, 6)
node _mulRawFN_io_a_out_isInf_T_1 = eq(_mulRawFN_io_a_out_isInf_T, UInt<1>(0h0))
node _mulRawFN_io_a_out_isInf_T_2 = and(mulRawFN_io_a_isSpecial, _mulRawFN_io_a_out_isInf_T_1)
connect mulRawFN_io_a_out.isInf, _mulRawFN_io_a_out_isInf_T_2
connect mulRawFN_io_a_out.isZero, mulRawFN_io_a_isZero
node _mulRawFN_io_a_out_sign_T = bits(io.a, 32, 32)
connect mulRawFN_io_a_out.sign, _mulRawFN_io_a_out_sign_T
node _mulRawFN_io_a_out_sExp_T = cvt(mulRawFN_io_a_exp)
connect mulRawFN_io_a_out.sExp, _mulRawFN_io_a_out_sExp_T
node _mulRawFN_io_a_out_sig_T = eq(mulRawFN_io_a_isZero, UInt<1>(0h0))
node _mulRawFN_io_a_out_sig_T_1 = cat(UInt<1>(0h0), _mulRawFN_io_a_out_sig_T)
node _mulRawFN_io_a_out_sig_T_2 = bits(io.a, 22, 0)
node _mulRawFN_io_a_out_sig_T_3 = cat(_mulRawFN_io_a_out_sig_T_1, _mulRawFN_io_a_out_sig_T_2)
connect mulRawFN_io_a_out.sig, _mulRawFN_io_a_out_sig_T_3
connect mulRawFN.io.a.sig, mulRawFN_io_a_out.sig
connect mulRawFN.io.a.sExp, mulRawFN_io_a_out.sExp
connect mulRawFN.io.a.sign, mulRawFN_io_a_out.sign
connect mulRawFN.io.a.isZero, mulRawFN_io_a_out.isZero
connect mulRawFN.io.a.isInf, mulRawFN_io_a_out.isInf
connect mulRawFN.io.a.isNaN, mulRawFN_io_a_out.isNaN
node mulRawFN_io_b_exp = bits(io.b, 31, 23)
node _mulRawFN_io_b_isZero_T = bits(mulRawFN_io_b_exp, 8, 6)
node mulRawFN_io_b_isZero = eq(_mulRawFN_io_b_isZero_T, UInt<1>(0h0))
node _mulRawFN_io_b_isSpecial_T = bits(mulRawFN_io_b_exp, 8, 7)
node mulRawFN_io_b_isSpecial = eq(_mulRawFN_io_b_isSpecial_T, UInt<2>(0h3))
wire mulRawFN_io_b_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _mulRawFN_io_b_out_isNaN_T = bits(mulRawFN_io_b_exp, 6, 6)
node _mulRawFN_io_b_out_isNaN_T_1 = and(mulRawFN_io_b_isSpecial, _mulRawFN_io_b_out_isNaN_T)
connect mulRawFN_io_b_out.isNaN, _mulRawFN_io_b_out_isNaN_T_1
node _mulRawFN_io_b_out_isInf_T = bits(mulRawFN_io_b_exp, 6, 6)
node _mulRawFN_io_b_out_isInf_T_1 = eq(_mulRawFN_io_b_out_isInf_T, UInt<1>(0h0))
node _mulRawFN_io_b_out_isInf_T_2 = and(mulRawFN_io_b_isSpecial, _mulRawFN_io_b_out_isInf_T_1)
connect mulRawFN_io_b_out.isInf, _mulRawFN_io_b_out_isInf_T_2
connect mulRawFN_io_b_out.isZero, mulRawFN_io_b_isZero
node _mulRawFN_io_b_out_sign_T = bits(io.b, 32, 32)
connect mulRawFN_io_b_out.sign, _mulRawFN_io_b_out_sign_T
node _mulRawFN_io_b_out_sExp_T = cvt(mulRawFN_io_b_exp)
connect mulRawFN_io_b_out.sExp, _mulRawFN_io_b_out_sExp_T
node _mulRawFN_io_b_out_sig_T = eq(mulRawFN_io_b_isZero, UInt<1>(0h0))
node _mulRawFN_io_b_out_sig_T_1 = cat(UInt<1>(0h0), _mulRawFN_io_b_out_sig_T)
node _mulRawFN_io_b_out_sig_T_2 = bits(io.b, 22, 0)
node _mulRawFN_io_b_out_sig_T_3 = cat(_mulRawFN_io_b_out_sig_T_1, _mulRawFN_io_b_out_sig_T_2)
connect mulRawFN_io_b_out.sig, _mulRawFN_io_b_out_sig_T_3
connect mulRawFN.io.b.sig, mulRawFN_io_b_out.sig
connect mulRawFN.io.b.sExp, mulRawFN_io_b_out.sExp
connect mulRawFN.io.b.sign, mulRawFN_io_b_out.sign
connect mulRawFN.io.b.isZero, mulRawFN_io_b_out.isZero
connect mulRawFN.io.b.isInf, mulRawFN_io_b_out.isInf
connect mulRawFN.io.b.isNaN, mulRawFN_io_b_out.isNaN
inst roundRawFNToRecFN of RoundRawFNToRecFN_e8_s24_78
connect roundRawFNToRecFN.io.invalidExc, mulRawFN.io.invalidExc
connect roundRawFNToRecFN.io.infiniteExc, UInt<1>(0h0)
connect roundRawFNToRecFN.io.in.sig, mulRawFN.io.rawOut.sig
connect roundRawFNToRecFN.io.in.sExp, mulRawFN.io.rawOut.sExp
connect roundRawFNToRecFN.io.in.sign, mulRawFN.io.rawOut.sign
connect roundRawFNToRecFN.io.in.isZero, mulRawFN.io.rawOut.isZero
connect roundRawFNToRecFN.io.in.isInf, mulRawFN.io.rawOut.isInf
connect roundRawFNToRecFN.io.in.isNaN, mulRawFN.io.rawOut.isNaN
connect roundRawFNToRecFN.io.roundingMode, io.roundingMode
connect roundRawFNToRecFN.io.detectTininess, io.detectTininess
connect io.out, roundRawFNToRecFN.io.out
connect io.exceptionFlags, roundRawFNToRecFN.io.exceptionFlags | module MulRecFN_22( // @[MulRecFN.scala:100:7]
input [32:0] io_a, // @[MulRecFN.scala:102:16]
input [32:0] io_b, // @[MulRecFN.scala:102:16]
output [32:0] io_out // @[MulRecFN.scala:102:16]
);
wire _mulRawFN_io_invalidExc; // @[MulRecFN.scala:113:26]
wire _mulRawFN_io_rawOut_isNaN; // @[MulRecFN.scala:113:26]
wire _mulRawFN_io_rawOut_isInf; // @[MulRecFN.scala:113:26]
wire _mulRawFN_io_rawOut_isZero; // @[MulRecFN.scala:113:26]
wire _mulRawFN_io_rawOut_sign; // @[MulRecFN.scala:113:26]
wire [9:0] _mulRawFN_io_rawOut_sExp; // @[MulRecFN.scala:113:26]
wire [26:0] _mulRawFN_io_rawOut_sig; // @[MulRecFN.scala:113:26]
wire [32:0] io_a_0 = io_a; // @[MulRecFN.scala:100:7]
wire [32:0] io_b_0 = io_b; // @[MulRecFN.scala:100:7]
wire io_detectTininess = 1'h1; // @[MulRecFN.scala:100:7, :102:16, :121:15]
wire [2:0] io_roundingMode = 3'h0; // @[MulRecFN.scala:100:7, :102:16, :121:15]
wire [32:0] io_out_0; // @[MulRecFN.scala:100:7]
wire [4:0] io_exceptionFlags; // @[MulRecFN.scala:100:7]
wire [8:0] mulRawFN_io_a_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _mulRawFN_io_a_isZero_T = mulRawFN_io_a_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire mulRawFN_io_a_isZero = _mulRawFN_io_a_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire mulRawFN_io_a_out_isZero = mulRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _mulRawFN_io_a_isSpecial_T = mulRawFN_io_a_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire mulRawFN_io_a_isSpecial = &_mulRawFN_io_a_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _mulRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _mulRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _mulRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _mulRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _mulRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire mulRawFN_io_a_out_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire mulRawFN_io_a_out_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire mulRawFN_io_a_out_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] mulRawFN_io_a_out_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] mulRawFN_io_a_out_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _mulRawFN_io_a_out_isNaN_T = mulRawFN_io_a_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _mulRawFN_io_a_out_isInf_T = mulRawFN_io_a_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _mulRawFN_io_a_out_isNaN_T_1 = mulRawFN_io_a_isSpecial & _mulRawFN_io_a_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign mulRawFN_io_a_out_isNaN = _mulRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _mulRawFN_io_a_out_isInf_T_1 = ~_mulRawFN_io_a_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _mulRawFN_io_a_out_isInf_T_2 = mulRawFN_io_a_isSpecial & _mulRawFN_io_a_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign mulRawFN_io_a_out_isInf = _mulRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _mulRawFN_io_a_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign mulRawFN_io_a_out_sign = _mulRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _mulRawFN_io_a_out_sExp_T = {1'h0, mulRawFN_io_a_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign mulRawFN_io_a_out_sExp = _mulRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _mulRawFN_io_a_out_sig_T = ~mulRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _mulRawFN_io_a_out_sig_T_1 = {1'h0, _mulRawFN_io_a_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _mulRawFN_io_a_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _mulRawFN_io_a_out_sig_T_3 = {_mulRawFN_io_a_out_sig_T_1, _mulRawFN_io_a_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign mulRawFN_io_a_out_sig = _mulRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [8:0] mulRawFN_io_b_exp = io_b_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _mulRawFN_io_b_isZero_T = mulRawFN_io_b_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire mulRawFN_io_b_isZero = _mulRawFN_io_b_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire mulRawFN_io_b_out_isZero = mulRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _mulRawFN_io_b_isSpecial_T = mulRawFN_io_b_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire mulRawFN_io_b_isSpecial = &_mulRawFN_io_b_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _mulRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _mulRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _mulRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _mulRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _mulRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire mulRawFN_io_b_out_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire mulRawFN_io_b_out_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire mulRawFN_io_b_out_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] mulRawFN_io_b_out_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] mulRawFN_io_b_out_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _mulRawFN_io_b_out_isNaN_T = mulRawFN_io_b_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _mulRawFN_io_b_out_isInf_T = mulRawFN_io_b_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _mulRawFN_io_b_out_isNaN_T_1 = mulRawFN_io_b_isSpecial & _mulRawFN_io_b_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign mulRawFN_io_b_out_isNaN = _mulRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _mulRawFN_io_b_out_isInf_T_1 = ~_mulRawFN_io_b_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _mulRawFN_io_b_out_isInf_T_2 = mulRawFN_io_b_isSpecial & _mulRawFN_io_b_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign mulRawFN_io_b_out_isInf = _mulRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _mulRawFN_io_b_out_sign_T = io_b_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign mulRawFN_io_b_out_sign = _mulRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _mulRawFN_io_b_out_sExp_T = {1'h0, mulRawFN_io_b_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign mulRawFN_io_b_out_sExp = _mulRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _mulRawFN_io_b_out_sig_T = ~mulRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _mulRawFN_io_b_out_sig_T_1 = {1'h0, _mulRawFN_io_b_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _mulRawFN_io_b_out_sig_T_2 = io_b_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _mulRawFN_io_b_out_sig_T_3 = {_mulRawFN_io_b_out_sig_T_1, _mulRawFN_io_b_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign mulRawFN_io_b_out_sig = _mulRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
MulRawFN_22 mulRawFN ( // @[MulRecFN.scala:113:26]
.io_a_isNaN (mulRawFN_io_a_out_isNaN), // @[rawFloatFromRecFN.scala:55:23]
.io_a_isInf (mulRawFN_io_a_out_isInf), // @[rawFloatFromRecFN.scala:55:23]
.io_a_isZero (mulRawFN_io_a_out_isZero), // @[rawFloatFromRecFN.scala:55:23]
.io_a_sign (mulRawFN_io_a_out_sign), // @[rawFloatFromRecFN.scala:55:23]
.io_a_sExp (mulRawFN_io_a_out_sExp), // @[rawFloatFromRecFN.scala:55:23]
.io_a_sig (mulRawFN_io_a_out_sig), // @[rawFloatFromRecFN.scala:55:23]
.io_b_isNaN (mulRawFN_io_b_out_isNaN), // @[rawFloatFromRecFN.scala:55:23]
.io_b_isInf (mulRawFN_io_b_out_isInf), // @[rawFloatFromRecFN.scala:55:23]
.io_b_isZero (mulRawFN_io_b_out_isZero), // @[rawFloatFromRecFN.scala:55:23]
.io_b_sign (mulRawFN_io_b_out_sign), // @[rawFloatFromRecFN.scala:55:23]
.io_b_sExp (mulRawFN_io_b_out_sExp), // @[rawFloatFromRecFN.scala:55:23]
.io_b_sig (mulRawFN_io_b_out_sig), // @[rawFloatFromRecFN.scala:55:23]
.io_invalidExc (_mulRawFN_io_invalidExc),
.io_rawOut_isNaN (_mulRawFN_io_rawOut_isNaN),
.io_rawOut_isInf (_mulRawFN_io_rawOut_isInf),
.io_rawOut_isZero (_mulRawFN_io_rawOut_isZero),
.io_rawOut_sign (_mulRawFN_io_rawOut_sign),
.io_rawOut_sExp (_mulRawFN_io_rawOut_sExp),
.io_rawOut_sig (_mulRawFN_io_rawOut_sig)
); // @[MulRecFN.scala:113:26]
RoundRawFNToRecFN_e8_s24_78 roundRawFNToRecFN ( // @[MulRecFN.scala:121:15]
.io_invalidExc (_mulRawFN_io_invalidExc), // @[MulRecFN.scala:113:26]
.io_in_isNaN (_mulRawFN_io_rawOut_isNaN), // @[MulRecFN.scala:113:26]
.io_in_isInf (_mulRawFN_io_rawOut_isInf), // @[MulRecFN.scala:113:26]
.io_in_isZero (_mulRawFN_io_rawOut_isZero), // @[MulRecFN.scala:113:26]
.io_in_sign (_mulRawFN_io_rawOut_sign), // @[MulRecFN.scala:113:26]
.io_in_sExp (_mulRawFN_io_rawOut_sExp), // @[MulRecFN.scala:113:26]
.io_in_sig (_mulRawFN_io_rawOut_sig), // @[MulRecFN.scala:113:26]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags)
); // @[MulRecFN.scala:121:15]
assign io_out = io_out_0; // @[MulRecFN.scala:100:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_89 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_source_valid_1 of AsyncResetSynchronizerShiftReg_w1_d3_i0_106
connect io_out_source_valid_1.clock, clock
connect io_out_source_valid_1.reset, reset
connect io_out_source_valid_1.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_source_valid_1.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_89( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_106 io_out_source_valid_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_101 :
input clock : Clock
input reset : Reset
output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}}
connect io.y, io.x | module OptimizationBarrier_TLBEntryData_101( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae_ptw, // @[package.scala:268:18]
input io_x_ae_final, // @[package.scala:268:18]
input io_x_ae_stage2, // @[package.scala:268:18]
input io_x_pf, // @[package.scala:268:18]
input io_x_gf, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_hw, // @[package.scala:268:18]
input io_x_hx, // @[package.scala:268:18]
input io_x_hr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_ppp, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output [19:0] io_y_ppn, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_ae_ptw, // @[package.scala:268:18]
output io_y_ae_final, // @[package.scala:268:18]
output io_y_ae_stage2, // @[package.scala:268:18]
output io_y_pf, // @[package.scala:268:18]
output io_y_gf, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_hw, // @[package.scala:268:18]
output io_y_hx, // @[package.scala:268:18]
output io_y_hr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_ppp, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30]
wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30]
wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30]
wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30]
wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30]
wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30]
wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30]
wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30]
wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30]
wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30]
wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30]
wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30]
wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30]
assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30]
assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30]
assign io_y_pf = io_y_pf_0; // @[package.scala:267:30]
assign io_y_gf = io_y_gf_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_hw = io_y_hw_0; // @[package.scala:267:30]
assign io_y_hx = io_y_hx_0; // @[package.scala:267:30]
assign io_y_hr = io_y_hr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module BranchDecode_5 :
input clock : Clock
input reset : Reset
output io : { flip inst : UInt<32>, flip pc : UInt<40>, out : { is_ret : UInt<1>, is_call : UInt<1>, target : UInt<40>, cfi_type : UInt<3>, sfb_offset : { valid : UInt<1>, bits : UInt<6>}, shadowable : UInt<1>}}
wire bpd_csignals_decoded_plaInput : UInt<32>
node bpd_csignals_decoded_invInputs = not(bpd_csignals_decoded_plaInput)
wire bpd_csignals_decoded : UInt<5>
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0 = bits(bpd_csignals_decoded_plaInput, 0, 0)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1 = bits(bpd_csignals_decoded_plaInput, 1, 1)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2 = bits(bpd_csignals_decoded_invInputs, 2, 2)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3 = bits(bpd_csignals_decoded_invInputs, 3, 3)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4 = bits(bpd_csignals_decoded_plaInput, 4, 4)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5 = bits(bpd_csignals_decoded_invInputs, 5, 5)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6 = bits(bpd_csignals_decoded_invInputs, 6, 6)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7 = bits(bpd_csignals_decoded_invInputs, 12, 12)
node bpd_csignals_decoded_andMatrixOutputs_lo_lo = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7)
node bpd_csignals_decoded_andMatrixOutputs_lo_hi = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5)
node bpd_csignals_decoded_andMatrixOutputs_lo = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi, bpd_csignals_decoded_andMatrixOutputs_lo_lo)
node bpd_csignals_decoded_andMatrixOutputs_hi_lo = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3)
node bpd_csignals_decoded_andMatrixOutputs_hi_hi = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1)
node bpd_csignals_decoded_andMatrixOutputs_hi = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi, bpd_csignals_decoded_andMatrixOutputs_hi_lo)
node _bpd_csignals_decoded_andMatrixOutputs_T = cat(bpd_csignals_decoded_andMatrixOutputs_hi, bpd_csignals_decoded_andMatrixOutputs_lo)
node bpd_csignals_decoded_andMatrixOutputs_5_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_1 = bits(bpd_csignals_decoded_plaInput, 0, 0)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_1 = bits(bpd_csignals_decoded_plaInput, 1, 1)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_1 = bits(bpd_csignals_decoded_invInputs, 2, 2)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_1 = bits(bpd_csignals_decoded_plaInput, 4, 4)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_1 = bits(bpd_csignals_decoded_invInputs, 5, 5)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_1 = bits(bpd_csignals_decoded_invInputs, 6, 6)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_1 = bits(bpd_csignals_decoded_invInputs, 12, 12)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_1 = bits(bpd_csignals_decoded_invInputs, 13, 13)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8 = bits(bpd_csignals_decoded_invInputs, 14, 14)
node bpd_csignals_decoded_andMatrixOutputs_lo_lo_1 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8)
node bpd_csignals_decoded_andMatrixOutputs_lo_hi_1 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_1)
node bpd_csignals_decoded_andMatrixOutputs_lo_1 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_1, bpd_csignals_decoded_andMatrixOutputs_lo_lo_1)
node bpd_csignals_decoded_andMatrixOutputs_hi_lo_1 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_1)
node bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_1)
node bpd_csignals_decoded_andMatrixOutputs_hi_hi_1 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_1)
node bpd_csignals_decoded_andMatrixOutputs_hi_1 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_1, bpd_csignals_decoded_andMatrixOutputs_hi_lo_1)
node _bpd_csignals_decoded_andMatrixOutputs_T_1 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_1, bpd_csignals_decoded_andMatrixOutputs_lo_1)
node bpd_csignals_decoded_andMatrixOutputs_9_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_1)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_2 = bits(bpd_csignals_decoded_plaInput, 0, 0)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_2 = bits(bpd_csignals_decoded_plaInput, 1, 1)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_2 = bits(bpd_csignals_decoded_invInputs, 2, 2)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_2 = bits(bpd_csignals_decoded_plaInput, 4, 4)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_2 = bits(bpd_csignals_decoded_plaInput, 5, 5)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_2 = bits(bpd_csignals_decoded_invInputs, 6, 6)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_2 = bits(bpd_csignals_decoded_invInputs, 12, 12)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_2 = bits(bpd_csignals_decoded_invInputs, 13, 13)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_1 = bits(bpd_csignals_decoded_invInputs, 14, 14)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9 = bits(bpd_csignals_decoded_invInputs, 25, 25)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10 = bits(bpd_csignals_decoded_invInputs, 26, 26)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11 = bits(bpd_csignals_decoded_invInputs, 27, 27)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12 = bits(bpd_csignals_decoded_invInputs, 28, 28)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13 = bits(bpd_csignals_decoded_invInputs, 29, 29)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14 = bits(bpd_csignals_decoded_invInputs, 31, 31)
node bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13)
node bpd_csignals_decoded_andMatrixOutputs_lo_lo_2 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14)
node bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11)
node bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9)
node bpd_csignals_decoded_andMatrixOutputs_lo_hi_2 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo)
node bpd_csignals_decoded_andMatrixOutputs_lo_2 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_2, bpd_csignals_decoded_andMatrixOutputs_lo_lo_2)
node bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_2)
node bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_2)
node bpd_csignals_decoded_andMatrixOutputs_hi_lo_2 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo)
node bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_2)
node bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_1 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_2)
node bpd_csignals_decoded_andMatrixOutputs_hi_hi_2 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_1, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo)
node bpd_csignals_decoded_andMatrixOutputs_hi_2 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_2, bpd_csignals_decoded_andMatrixOutputs_hi_lo_2)
node _bpd_csignals_decoded_andMatrixOutputs_T_2 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_2, bpd_csignals_decoded_andMatrixOutputs_lo_2)
node bpd_csignals_decoded_andMatrixOutputs_14_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_2)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_3 = bits(bpd_csignals_decoded_plaInput, 0, 0)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_3 = bits(bpd_csignals_decoded_plaInput, 1, 1)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_3 = bits(bpd_csignals_decoded_invInputs, 2, 2)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_3 = bits(bpd_csignals_decoded_invInputs, 3, 3)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_3 = bits(bpd_csignals_decoded_plaInput, 4, 4)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_3 = bits(bpd_csignals_decoded_plaInput, 5, 5)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_3 = bits(bpd_csignals_decoded_invInputs, 6, 6)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_3 = bits(bpd_csignals_decoded_invInputs, 25, 25)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_2 = bits(bpd_csignals_decoded_invInputs, 26, 26)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_1 = bits(bpd_csignals_decoded_invInputs, 27, 27)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_1 = bits(bpd_csignals_decoded_invInputs, 28, 28)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_1 = bits(bpd_csignals_decoded_invInputs, 29, 29)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_1 = bits(bpd_csignals_decoded_invInputs, 30, 30)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_1 = bits(bpd_csignals_decoded_invInputs, 31, 31)
node bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_1 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_1)
node bpd_csignals_decoded_andMatrixOutputs_lo_lo_3 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_1)
node bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_1 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_1)
node bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_1 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_2)
node bpd_csignals_decoded_andMatrixOutputs_lo_hi_3 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_1, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_1)
node bpd_csignals_decoded_andMatrixOutputs_lo_3 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_3, bpd_csignals_decoded_andMatrixOutputs_lo_lo_3)
node bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_1 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_3)
node bpd_csignals_decoded_andMatrixOutputs_hi_lo_3 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_3)
node bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_1 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_3)
node bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_2 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_3)
node bpd_csignals_decoded_andMatrixOutputs_hi_hi_3 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_2, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_1)
node bpd_csignals_decoded_andMatrixOutputs_hi_3 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_3, bpd_csignals_decoded_andMatrixOutputs_hi_lo_3)
node _bpd_csignals_decoded_andMatrixOutputs_T_3 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_3, bpd_csignals_decoded_andMatrixOutputs_lo_3)
node bpd_csignals_decoded_andMatrixOutputs_0_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_3)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_4 = bits(bpd_csignals_decoded_plaInput, 0, 0)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_4 = bits(bpd_csignals_decoded_plaInput, 1, 1)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_4 = bits(bpd_csignals_decoded_invInputs, 2, 2)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_4 = bits(bpd_csignals_decoded_plaInput, 4, 4)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_4 = bits(bpd_csignals_decoded_plaInput, 5, 5)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_4 = bits(bpd_csignals_decoded_invInputs, 6, 6)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_4 = bits(bpd_csignals_decoded_invInputs, 13, 13)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_4 = bits(bpd_csignals_decoded_invInputs, 14, 14)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_3 = bits(bpd_csignals_decoded_invInputs, 25, 25)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_2 = bits(bpd_csignals_decoded_invInputs, 26, 26)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_2 = bits(bpd_csignals_decoded_invInputs, 27, 27)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_2 = bits(bpd_csignals_decoded_invInputs, 28, 28)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_2 = bits(bpd_csignals_decoded_invInputs, 29, 29)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_2 = bits(bpd_csignals_decoded_invInputs, 30, 30)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_1 = bits(bpd_csignals_decoded_invInputs, 31, 31)
node bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_2 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_2)
node bpd_csignals_decoded_andMatrixOutputs_lo_lo_4 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_1)
node bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_2 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_2)
node bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_2 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_2)
node bpd_csignals_decoded_andMatrixOutputs_lo_hi_4 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_2, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_2)
node bpd_csignals_decoded_andMatrixOutputs_lo_4 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_4, bpd_csignals_decoded_andMatrixOutputs_lo_lo_4)
node bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_1 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_4)
node bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_2 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_4)
node bpd_csignals_decoded_andMatrixOutputs_hi_lo_4 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_2, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_1)
node bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_2 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_4)
node bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_3 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_4)
node bpd_csignals_decoded_andMatrixOutputs_hi_hi_4 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_3, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_2)
node bpd_csignals_decoded_andMatrixOutputs_hi_4 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_4, bpd_csignals_decoded_andMatrixOutputs_hi_lo_4)
node _bpd_csignals_decoded_andMatrixOutputs_T_4 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_4, bpd_csignals_decoded_andMatrixOutputs_lo_4)
node bpd_csignals_decoded_andMatrixOutputs_2_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_4)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_5 = bits(bpd_csignals_decoded_plaInput, 0, 0)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_5 = bits(bpd_csignals_decoded_plaInput, 1, 1)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_5 = bits(bpd_csignals_decoded_plaInput, 2, 2)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_5 = bits(bpd_csignals_decoded_invInputs, 3, 3)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_5 = bits(bpd_csignals_decoded_plaInput, 4, 4)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_5 = bits(bpd_csignals_decoded_plaInput, 5, 5)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_5 = bits(bpd_csignals_decoded_invInputs, 6, 6)
node bpd_csignals_decoded_andMatrixOutputs_lo_hi_5 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_5)
node bpd_csignals_decoded_andMatrixOutputs_lo_5 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_5)
node bpd_csignals_decoded_andMatrixOutputs_hi_lo_5 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_5)
node bpd_csignals_decoded_andMatrixOutputs_hi_hi_5 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_5)
node bpd_csignals_decoded_andMatrixOutputs_hi_5 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_5, bpd_csignals_decoded_andMatrixOutputs_hi_lo_5)
node _bpd_csignals_decoded_andMatrixOutputs_T_5 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_5, bpd_csignals_decoded_andMatrixOutputs_lo_5)
node bpd_csignals_decoded_andMatrixOutputs_12_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_5)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_6 = bits(bpd_csignals_decoded_plaInput, 0, 0)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_6 = bits(bpd_csignals_decoded_plaInput, 1, 1)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_6 = bits(bpd_csignals_decoded_invInputs, 2, 2)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_6 = bits(bpd_csignals_decoded_invInputs, 3, 3)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_6 = bits(bpd_csignals_decoded_invInputs, 4, 4)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_6 = bits(bpd_csignals_decoded_plaInput, 5, 5)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_6 = bits(bpd_csignals_decoded_plaInput, 6, 6)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_5 = bits(bpd_csignals_decoded_invInputs, 13, 13)
node bpd_csignals_decoded_andMatrixOutputs_lo_lo_5 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_5)
node bpd_csignals_decoded_andMatrixOutputs_lo_hi_6 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_6)
node bpd_csignals_decoded_andMatrixOutputs_lo_6 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_6, bpd_csignals_decoded_andMatrixOutputs_lo_lo_5)
node bpd_csignals_decoded_andMatrixOutputs_hi_lo_6 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_6)
node bpd_csignals_decoded_andMatrixOutputs_hi_hi_6 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_6)
node bpd_csignals_decoded_andMatrixOutputs_hi_6 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_6, bpd_csignals_decoded_andMatrixOutputs_hi_lo_6)
node _bpd_csignals_decoded_andMatrixOutputs_T_6 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_6, bpd_csignals_decoded_andMatrixOutputs_lo_6)
node bpd_csignals_decoded_andMatrixOutputs_6_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_6)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_7 = bits(bpd_csignals_decoded_plaInput, 0, 0)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_7 = bits(bpd_csignals_decoded_plaInput, 1, 1)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_7 = bits(bpd_csignals_decoded_plaInput, 2, 2)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_7 = bits(bpd_csignals_decoded_invInputs, 3, 3)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_7 = bits(bpd_csignals_decoded_invInputs, 4, 4)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_7 = bits(bpd_csignals_decoded_plaInput, 5, 5)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_7 = bits(bpd_csignals_decoded_plaInput, 6, 6)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_6 = bits(bpd_csignals_decoded_invInputs, 12, 12)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_4 = bits(bpd_csignals_decoded_invInputs, 13, 13)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_3 = bits(bpd_csignals_decoded_invInputs, 14, 14)
node bpd_csignals_decoded_andMatrixOutputs_lo_lo_6 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_3)
node bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_3 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_7)
node bpd_csignals_decoded_andMatrixOutputs_lo_hi_7 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_6)
node bpd_csignals_decoded_andMatrixOutputs_lo_7 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_7, bpd_csignals_decoded_andMatrixOutputs_lo_lo_6)
node bpd_csignals_decoded_andMatrixOutputs_hi_lo_7 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_7)
node bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_4 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_7)
node bpd_csignals_decoded_andMatrixOutputs_hi_hi_7 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_7)
node bpd_csignals_decoded_andMatrixOutputs_hi_7 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_7, bpd_csignals_decoded_andMatrixOutputs_hi_lo_7)
node _bpd_csignals_decoded_andMatrixOutputs_T_7 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_7, bpd_csignals_decoded_andMatrixOutputs_lo_7)
node bpd_csignals_decoded_andMatrixOutputs_15_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_7)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_8 = bits(bpd_csignals_decoded_plaInput, 0, 0)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_8 = bits(bpd_csignals_decoded_plaInput, 1, 1)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_8 = bits(bpd_csignals_decoded_plaInput, 2, 2)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_8 = bits(bpd_csignals_decoded_plaInput, 3, 3)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_8 = bits(bpd_csignals_decoded_invInputs, 4, 4)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_8 = bits(bpd_csignals_decoded_plaInput, 5, 5)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_8 = bits(bpd_csignals_decoded_plaInput, 6, 6)
node bpd_csignals_decoded_andMatrixOutputs_lo_hi_8 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_8)
node bpd_csignals_decoded_andMatrixOutputs_lo_8 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_8)
node bpd_csignals_decoded_andMatrixOutputs_hi_lo_8 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_8)
node bpd_csignals_decoded_andMatrixOutputs_hi_hi_8 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_8)
node bpd_csignals_decoded_andMatrixOutputs_hi_8 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_8, bpd_csignals_decoded_andMatrixOutputs_hi_lo_8)
node _bpd_csignals_decoded_andMatrixOutputs_T_8 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_8, bpd_csignals_decoded_andMatrixOutputs_lo_8)
node bpd_csignals_decoded_andMatrixOutputs_11_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_8)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_9 = bits(bpd_csignals_decoded_plaInput, 0, 0)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_9 = bits(bpd_csignals_decoded_plaInput, 1, 1)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_9 = bits(bpd_csignals_decoded_invInputs, 2, 2)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_9 = bits(bpd_csignals_decoded_invInputs, 3, 3)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_9 = bits(bpd_csignals_decoded_plaInput, 4, 4)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_9 = bits(bpd_csignals_decoded_invInputs, 5, 5)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_9 = bits(bpd_csignals_decoded_invInputs, 6, 6)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_7 = bits(bpd_csignals_decoded_plaInput, 12, 12)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_5 = bits(bpd_csignals_decoded_invInputs, 13, 13)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_4 = bits(bpd_csignals_decoded_invInputs, 26, 26)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_3 = bits(bpd_csignals_decoded_invInputs, 27, 27)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_3 = bits(bpd_csignals_decoded_invInputs, 28, 28)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_3 = bits(bpd_csignals_decoded_invInputs, 29, 29)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_3 = bits(bpd_csignals_decoded_invInputs, 30, 30)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_2 = bits(bpd_csignals_decoded_invInputs, 31, 31)
node bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_3 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_3)
node bpd_csignals_decoded_andMatrixOutputs_lo_lo_7 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_2)
node bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_3 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_3)
node bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_4 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_4)
node bpd_csignals_decoded_andMatrixOutputs_lo_hi_9 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_4, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_3)
node bpd_csignals_decoded_andMatrixOutputs_lo_9 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_9, bpd_csignals_decoded_andMatrixOutputs_lo_lo_7)
node bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_2 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_7)
node bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_3 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_9)
node bpd_csignals_decoded_andMatrixOutputs_hi_lo_9 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_3, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_2)
node bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_3 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_9)
node bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_5 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_9)
node bpd_csignals_decoded_andMatrixOutputs_hi_hi_9 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_5, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_3)
node bpd_csignals_decoded_andMatrixOutputs_hi_9 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_9, bpd_csignals_decoded_andMatrixOutputs_hi_lo_9)
node _bpd_csignals_decoded_andMatrixOutputs_T_9 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_9, bpd_csignals_decoded_andMatrixOutputs_lo_9)
node bpd_csignals_decoded_andMatrixOutputs_3_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_9)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_10 = bits(bpd_csignals_decoded_plaInput, 0, 0)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_10 = bits(bpd_csignals_decoded_plaInput, 1, 1)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_10 = bits(bpd_csignals_decoded_invInputs, 2, 2)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_10 = bits(bpd_csignals_decoded_plaInput, 3, 3)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_10 = bits(bpd_csignals_decoded_plaInput, 4, 4)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_10 = bits(bpd_csignals_decoded_invInputs, 6, 6)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_10 = bits(bpd_csignals_decoded_plaInput, 12, 12)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_8 = bits(bpd_csignals_decoded_invInputs, 13, 13)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_6 = bits(bpd_csignals_decoded_invInputs, 25, 25)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_5 = bits(bpd_csignals_decoded_invInputs, 26, 26)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_4 = bits(bpd_csignals_decoded_invInputs, 27, 27)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_4 = bits(bpd_csignals_decoded_invInputs, 28, 28)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_4 = bits(bpd_csignals_decoded_invInputs, 29, 29)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_4 = bits(bpd_csignals_decoded_invInputs, 30, 30)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_3 = bits(bpd_csignals_decoded_invInputs, 31, 31)
node bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_4 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_4)
node bpd_csignals_decoded_andMatrixOutputs_lo_lo_8 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_3)
node bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_4 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_4)
node bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_5 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_5)
node bpd_csignals_decoded_andMatrixOutputs_lo_hi_10 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_5, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_4)
node bpd_csignals_decoded_andMatrixOutputs_lo_10 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_10, bpd_csignals_decoded_andMatrixOutputs_lo_lo_8)
node bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_3 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_8)
node bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_4 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_10)
node bpd_csignals_decoded_andMatrixOutputs_hi_lo_10 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_4, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_3)
node bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_4 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_10)
node bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_6 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_10)
node bpd_csignals_decoded_andMatrixOutputs_hi_hi_10 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_6, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_4)
node bpd_csignals_decoded_andMatrixOutputs_hi_10 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_10, bpd_csignals_decoded_andMatrixOutputs_hi_lo_10)
node _bpd_csignals_decoded_andMatrixOutputs_T_10 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_10, bpd_csignals_decoded_andMatrixOutputs_lo_10)
node bpd_csignals_decoded_andMatrixOutputs_7_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_10)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_11 = bits(bpd_csignals_decoded_plaInput, 0, 0)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_11 = bits(bpd_csignals_decoded_plaInput, 1, 1)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_11 = bits(bpd_csignals_decoded_invInputs, 2, 2)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_11 = bits(bpd_csignals_decoded_invInputs, 3, 3)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_11 = bits(bpd_csignals_decoded_plaInput, 4, 4)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_11 = bits(bpd_csignals_decoded_invInputs, 5, 5)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_11 = bits(bpd_csignals_decoded_invInputs, 6, 6)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_9 = bits(bpd_csignals_decoded_plaInput, 13, 13)
node bpd_csignals_decoded_andMatrixOutputs_lo_lo_9 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_11, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_9)
node bpd_csignals_decoded_andMatrixOutputs_lo_hi_11 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_11, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_11)
node bpd_csignals_decoded_andMatrixOutputs_lo_11 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_11, bpd_csignals_decoded_andMatrixOutputs_lo_lo_9)
node bpd_csignals_decoded_andMatrixOutputs_hi_lo_11 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_11, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_11)
node bpd_csignals_decoded_andMatrixOutputs_hi_hi_11 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_11, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_11)
node bpd_csignals_decoded_andMatrixOutputs_hi_11 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_11, bpd_csignals_decoded_andMatrixOutputs_hi_lo_11)
node _bpd_csignals_decoded_andMatrixOutputs_T_11 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_11, bpd_csignals_decoded_andMatrixOutputs_lo_11)
node bpd_csignals_decoded_andMatrixOutputs_1_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_11)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_12 = bits(bpd_csignals_decoded_plaInput, 0, 0)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_12 = bits(bpd_csignals_decoded_plaInput, 1, 1)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_12 = bits(bpd_csignals_decoded_invInputs, 2, 2)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_12 = bits(bpd_csignals_decoded_invInputs, 3, 3)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_12 = bits(bpd_csignals_decoded_invInputs, 4, 4)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_12 = bits(bpd_csignals_decoded_plaInput, 5, 5)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_12 = bits(bpd_csignals_decoded_plaInput, 6, 6)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_10 = bits(bpd_csignals_decoded_plaInput, 14, 14)
node bpd_csignals_decoded_andMatrixOutputs_lo_lo_10 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_10)
node bpd_csignals_decoded_andMatrixOutputs_lo_hi_12 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_12)
node bpd_csignals_decoded_andMatrixOutputs_lo_12 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_12, bpd_csignals_decoded_andMatrixOutputs_lo_lo_10)
node bpd_csignals_decoded_andMatrixOutputs_hi_lo_12 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_12)
node bpd_csignals_decoded_andMatrixOutputs_hi_hi_12 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_12)
node bpd_csignals_decoded_andMatrixOutputs_hi_12 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_12, bpd_csignals_decoded_andMatrixOutputs_hi_lo_12)
node _bpd_csignals_decoded_andMatrixOutputs_T_12 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_12, bpd_csignals_decoded_andMatrixOutputs_lo_12)
node bpd_csignals_decoded_andMatrixOutputs_13_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_12)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_13 = bits(bpd_csignals_decoded_plaInput, 0, 0)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_13 = bits(bpd_csignals_decoded_plaInput, 1, 1)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_13 = bits(bpd_csignals_decoded_invInputs, 2, 2)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_13 = bits(bpd_csignals_decoded_invInputs, 3, 3)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_13 = bits(bpd_csignals_decoded_plaInput, 4, 4)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_13 = bits(bpd_csignals_decoded_invInputs, 5, 5)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_13 = bits(bpd_csignals_decoded_invInputs, 6, 6)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_11 = bits(bpd_csignals_decoded_plaInput, 12, 12)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_7 = bits(bpd_csignals_decoded_invInputs, 13, 13)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_6 = bits(bpd_csignals_decoded_plaInput, 14, 14)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_5 = bits(bpd_csignals_decoded_invInputs, 26, 26)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_5 = bits(bpd_csignals_decoded_invInputs, 27, 27)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_5 = bits(bpd_csignals_decoded_invInputs, 28, 28)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_5 = bits(bpd_csignals_decoded_invInputs, 29, 29)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_4 = bits(bpd_csignals_decoded_invInputs, 31, 31)
node bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_5 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_5)
node bpd_csignals_decoded_andMatrixOutputs_lo_lo_11 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_4)
node bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_5 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_5)
node bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_6 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_6)
node bpd_csignals_decoded_andMatrixOutputs_lo_hi_13 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_6, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_5)
node bpd_csignals_decoded_andMatrixOutputs_lo_13 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_13, bpd_csignals_decoded_andMatrixOutputs_lo_lo_11)
node bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_4 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_13, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_11)
node bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_5 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_13, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_13)
node bpd_csignals_decoded_andMatrixOutputs_hi_lo_13 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_5, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_4)
node bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_5 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_13, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_13)
node bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_7 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_13, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_13)
node bpd_csignals_decoded_andMatrixOutputs_hi_hi_13 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_7, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_5)
node bpd_csignals_decoded_andMatrixOutputs_hi_13 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_13, bpd_csignals_decoded_andMatrixOutputs_hi_lo_13)
node _bpd_csignals_decoded_andMatrixOutputs_T_13 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_13, bpd_csignals_decoded_andMatrixOutputs_lo_13)
node bpd_csignals_decoded_andMatrixOutputs_4_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_13)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_14 = bits(bpd_csignals_decoded_plaInput, 0, 0)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_14 = bits(bpd_csignals_decoded_plaInput, 1, 1)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_14 = bits(bpd_csignals_decoded_invInputs, 2, 2)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_14 = bits(bpd_csignals_decoded_plaInput, 3, 3)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_14 = bits(bpd_csignals_decoded_plaInput, 4, 4)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_14 = bits(bpd_csignals_decoded_invInputs, 6, 6)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_14 = bits(bpd_csignals_decoded_plaInput, 12, 12)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_12 = bits(bpd_csignals_decoded_invInputs, 13, 13)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_8 = bits(bpd_csignals_decoded_plaInput, 14, 14)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_7 = bits(bpd_csignals_decoded_invInputs, 25, 25)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_6 = bits(bpd_csignals_decoded_invInputs, 26, 26)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_6 = bits(bpd_csignals_decoded_invInputs, 27, 27)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_6 = bits(bpd_csignals_decoded_invInputs, 28, 28)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_6 = bits(bpd_csignals_decoded_invInputs, 29, 29)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_5 = bits(bpd_csignals_decoded_invInputs, 31, 31)
node bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_6 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_6)
node bpd_csignals_decoded_andMatrixOutputs_lo_lo_12 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_5)
node bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_6 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_6)
node bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_7 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_7)
node bpd_csignals_decoded_andMatrixOutputs_lo_hi_14 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_7, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_6)
node bpd_csignals_decoded_andMatrixOutputs_lo_14 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_14, bpd_csignals_decoded_andMatrixOutputs_lo_lo_12)
node bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_5 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_14, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_12)
node bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_6 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_14, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_14)
node bpd_csignals_decoded_andMatrixOutputs_hi_lo_14 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_6, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_5)
node bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_6 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_14, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_14)
node bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_8 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_14, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_14)
node bpd_csignals_decoded_andMatrixOutputs_hi_hi_14 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_8, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_6)
node bpd_csignals_decoded_andMatrixOutputs_hi_14 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_14, bpd_csignals_decoded_andMatrixOutputs_hi_lo_14)
node _bpd_csignals_decoded_andMatrixOutputs_T_14 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_14, bpd_csignals_decoded_andMatrixOutputs_lo_14)
node bpd_csignals_decoded_andMatrixOutputs_8_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_14)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_15 = bits(bpd_csignals_decoded_plaInput, 0, 0)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_15 = bits(bpd_csignals_decoded_plaInput, 1, 1)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_15 = bits(bpd_csignals_decoded_invInputs, 2, 2)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_15 = bits(bpd_csignals_decoded_plaInput, 4, 4)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_15 = bits(bpd_csignals_decoded_plaInput, 5, 5)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_15 = bits(bpd_csignals_decoded_invInputs, 6, 6)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_15 = bits(bpd_csignals_decoded_plaInput, 12, 12)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_13 = bits(bpd_csignals_decoded_invInputs, 13, 13)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_9 = bits(bpd_csignals_decoded_plaInput, 14, 14)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_8 = bits(bpd_csignals_decoded_invInputs, 25, 25)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_7 = bits(bpd_csignals_decoded_invInputs, 26, 26)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_7 = bits(bpd_csignals_decoded_invInputs, 27, 27)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_7 = bits(bpd_csignals_decoded_invInputs, 28, 28)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_7 = bits(bpd_csignals_decoded_invInputs, 29, 29)
node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_6 = bits(bpd_csignals_decoded_invInputs, 31, 31)
node bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_7 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_7)
node bpd_csignals_decoded_andMatrixOutputs_lo_lo_13 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_6)
node bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_7 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_7)
node bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_8 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_8)
node bpd_csignals_decoded_andMatrixOutputs_lo_hi_15 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_8, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_7)
node bpd_csignals_decoded_andMatrixOutputs_lo_15 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_15, bpd_csignals_decoded_andMatrixOutputs_lo_lo_13)
node bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_6 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_15, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_13)
node bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_7 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_15, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_15)
node bpd_csignals_decoded_andMatrixOutputs_hi_lo_15 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_7, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_6)
node bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_7 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_15, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_15)
node bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_9 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_15, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_15)
node bpd_csignals_decoded_andMatrixOutputs_hi_hi_15 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_9, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_7)
node bpd_csignals_decoded_andMatrixOutputs_hi_15 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_15, bpd_csignals_decoded_andMatrixOutputs_hi_lo_15)
node _bpd_csignals_decoded_andMatrixOutputs_T_15 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_15, bpd_csignals_decoded_andMatrixOutputs_lo_15)
node bpd_csignals_decoded_andMatrixOutputs_10_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_15)
node bpd_csignals_decoded_orMatrixOutputs_lo = cat(bpd_csignals_decoded_andMatrixOutputs_2_2, bpd_csignals_decoded_andMatrixOutputs_10_2)
node bpd_csignals_decoded_orMatrixOutputs_hi = cat(bpd_csignals_decoded_andMatrixOutputs_14_2, bpd_csignals_decoded_andMatrixOutputs_0_2)
node _bpd_csignals_decoded_orMatrixOutputs_T = cat(bpd_csignals_decoded_orMatrixOutputs_hi, bpd_csignals_decoded_orMatrixOutputs_lo)
node _bpd_csignals_decoded_orMatrixOutputs_T_1 = orr(_bpd_csignals_decoded_orMatrixOutputs_T)
node bpd_csignals_decoded_orMatrixOutputs_lo_lo = cat(bpd_csignals_decoded_andMatrixOutputs_8_2, bpd_csignals_decoded_andMatrixOutputs_10_2)
node bpd_csignals_decoded_orMatrixOutputs_lo_hi_hi = cat(bpd_csignals_decoded_andMatrixOutputs_7_2, bpd_csignals_decoded_andMatrixOutputs_1_2)
node bpd_csignals_decoded_orMatrixOutputs_lo_hi = cat(bpd_csignals_decoded_orMatrixOutputs_lo_hi_hi, bpd_csignals_decoded_andMatrixOutputs_4_2)
node bpd_csignals_decoded_orMatrixOutputs_lo_1 = cat(bpd_csignals_decoded_orMatrixOutputs_lo_hi, bpd_csignals_decoded_orMatrixOutputs_lo_lo)
node bpd_csignals_decoded_orMatrixOutputs_hi_lo_hi = cat(bpd_csignals_decoded_andMatrixOutputs_0_2, bpd_csignals_decoded_andMatrixOutputs_12_2)
node bpd_csignals_decoded_orMatrixOutputs_hi_lo = cat(bpd_csignals_decoded_orMatrixOutputs_hi_lo_hi, bpd_csignals_decoded_andMatrixOutputs_3_2)
node bpd_csignals_decoded_orMatrixOutputs_hi_hi_hi = cat(bpd_csignals_decoded_andMatrixOutputs_5_2, bpd_csignals_decoded_andMatrixOutputs_9_2)
node bpd_csignals_decoded_orMatrixOutputs_hi_hi = cat(bpd_csignals_decoded_orMatrixOutputs_hi_hi_hi, bpd_csignals_decoded_andMatrixOutputs_14_2)
node bpd_csignals_decoded_orMatrixOutputs_hi_1 = cat(bpd_csignals_decoded_orMatrixOutputs_hi_hi, bpd_csignals_decoded_orMatrixOutputs_hi_lo)
node _bpd_csignals_decoded_orMatrixOutputs_T_2 = cat(bpd_csignals_decoded_orMatrixOutputs_hi_1, bpd_csignals_decoded_orMatrixOutputs_lo_1)
node _bpd_csignals_decoded_orMatrixOutputs_T_3 = orr(_bpd_csignals_decoded_orMatrixOutputs_T_2)
node _bpd_csignals_decoded_orMatrixOutputs_T_4 = orr(bpd_csignals_decoded_andMatrixOutputs_15_2)
node _bpd_csignals_decoded_orMatrixOutputs_T_5 = orr(bpd_csignals_decoded_andMatrixOutputs_11_2)
node _bpd_csignals_decoded_orMatrixOutputs_T_6 = cat(bpd_csignals_decoded_andMatrixOutputs_6_2, bpd_csignals_decoded_andMatrixOutputs_13_2)
node _bpd_csignals_decoded_orMatrixOutputs_T_7 = orr(_bpd_csignals_decoded_orMatrixOutputs_T_6)
node bpd_csignals_decoded_orMatrixOutputs_lo_2 = cat(_bpd_csignals_decoded_orMatrixOutputs_T_3, _bpd_csignals_decoded_orMatrixOutputs_T_1)
node bpd_csignals_decoded_orMatrixOutputs_hi_hi_1 = cat(_bpd_csignals_decoded_orMatrixOutputs_T_7, _bpd_csignals_decoded_orMatrixOutputs_T_5)
node bpd_csignals_decoded_orMatrixOutputs_hi_2 = cat(bpd_csignals_decoded_orMatrixOutputs_hi_hi_1, _bpd_csignals_decoded_orMatrixOutputs_T_4)
node bpd_csignals_decoded_orMatrixOutputs = cat(bpd_csignals_decoded_orMatrixOutputs_hi_2, bpd_csignals_decoded_orMatrixOutputs_lo_2)
node _bpd_csignals_decoded_invMatrixOutputs_T = bits(bpd_csignals_decoded_orMatrixOutputs, 0, 0)
node _bpd_csignals_decoded_invMatrixOutputs_T_1 = bits(bpd_csignals_decoded_orMatrixOutputs, 1, 1)
node _bpd_csignals_decoded_invMatrixOutputs_T_2 = bits(bpd_csignals_decoded_orMatrixOutputs, 2, 2)
node _bpd_csignals_decoded_invMatrixOutputs_T_3 = bits(bpd_csignals_decoded_orMatrixOutputs, 3, 3)
node _bpd_csignals_decoded_invMatrixOutputs_T_4 = bits(bpd_csignals_decoded_orMatrixOutputs, 4, 4)
node bpd_csignals_decoded_invMatrixOutputs_lo = cat(_bpd_csignals_decoded_invMatrixOutputs_T_1, _bpd_csignals_decoded_invMatrixOutputs_T)
node bpd_csignals_decoded_invMatrixOutputs_hi_hi = cat(_bpd_csignals_decoded_invMatrixOutputs_T_4, _bpd_csignals_decoded_invMatrixOutputs_T_3)
node bpd_csignals_decoded_invMatrixOutputs_hi = cat(bpd_csignals_decoded_invMatrixOutputs_hi_hi, _bpd_csignals_decoded_invMatrixOutputs_T_2)
node bpd_csignals_decoded_invMatrixOutputs = cat(bpd_csignals_decoded_invMatrixOutputs_hi, bpd_csignals_decoded_invMatrixOutputs_lo)
connect bpd_csignals_decoded, bpd_csignals_decoded_invMatrixOutputs
connect bpd_csignals_decoded_plaInput, io.inst
node bpd_csignals_0 = bits(bpd_csignals_decoded, 4, 4)
node bpd_csignals_1 = bits(bpd_csignals_decoded, 3, 3)
node bpd_csignals_2 = bits(bpd_csignals_decoded, 2, 2)
node bpd_csignals_3 = bits(bpd_csignals_decoded, 1, 1)
node bpd_csignals_4 = bits(bpd_csignals_decoded, 0, 0)
node cs_is_br = bits(bpd_csignals_0, 0, 0)
node cs_is_jal = bits(bpd_csignals_1, 0, 0)
node cs_is_jalr = bits(bpd_csignals_2, 0, 0)
node cs_is_shadowable = bits(bpd_csignals_3, 0, 0)
node cs_has_rs2 = bits(bpd_csignals_4, 0, 0)
node _io_out_is_call_T = or(cs_is_jal, cs_is_jalr)
node _io_out_is_call_T_1 = bits(io.inst, 11, 7)
node _io_out_is_call_T_2 = eq(_io_out_is_call_T_1, UInt<1>(0h1))
node _io_out_is_call_T_3 = and(_io_out_is_call_T, _io_out_is_call_T_2)
connect io.out.is_call, _io_out_is_call_T_3
node _io_out_is_ret_T = bits(io.inst, 19, 15)
node _io_out_is_ret_T_1 = and(_io_out_is_ret_T, UInt<5>(0h1b))
node _io_out_is_ret_T_2 = eq(UInt<1>(0h1), _io_out_is_ret_T_1)
node _io_out_is_ret_T_3 = and(cs_is_jalr, _io_out_is_ret_T_2)
node _io_out_is_ret_T_4 = bits(io.inst, 11, 7)
node _io_out_is_ret_T_5 = eq(_io_out_is_ret_T_4, UInt<1>(0h0))
node _io_out_is_ret_T_6 = and(_io_out_is_ret_T_3, _io_out_is_ret_T_5)
connect io.out.is_ret, _io_out_is_ret_T_6
node _io_out_target_b_imm32_T = bits(io.inst, 31, 31)
node _io_out_target_b_imm32_T_1 = mux(_io_out_target_b_imm32_T, UInt<20>(0hfffff), UInt<20>(0h0))
node _io_out_target_b_imm32_T_2 = bits(io.inst, 7, 7)
node _io_out_target_b_imm32_T_3 = bits(io.inst, 30, 25)
node _io_out_target_b_imm32_T_4 = bits(io.inst, 11, 8)
node io_out_target_b_imm32_lo = cat(_io_out_target_b_imm32_T_4, UInt<1>(0h0))
node io_out_target_b_imm32_hi_hi = cat(_io_out_target_b_imm32_T_1, _io_out_target_b_imm32_T_2)
node io_out_target_b_imm32_hi = cat(io_out_target_b_imm32_hi_hi, _io_out_target_b_imm32_T_3)
node io_out_target_b_imm32 = cat(io_out_target_b_imm32_hi, io_out_target_b_imm32_lo)
node _io_out_target_T = asSInt(io.pc)
node _io_out_target_T_1 = asSInt(io_out_target_b_imm32)
node _io_out_target_T_2 = add(_io_out_target_T, _io_out_target_T_1)
node _io_out_target_T_3 = tail(_io_out_target_T_2, 1)
node _io_out_target_T_4 = asSInt(_io_out_target_T_3)
node _io_out_target_T_5 = and(_io_out_target_T_4, asSInt(UInt<2>(0h2)))
node _io_out_target_T_6 = asSInt(_io_out_target_T_5)
node _io_out_target_T_7 = asUInt(_io_out_target_T_6)
node _io_out_target_j_imm32_T = bits(io.inst, 31, 31)
node _io_out_target_j_imm32_T_1 = mux(_io_out_target_j_imm32_T, UInt<12>(0hfff), UInt<12>(0h0))
node _io_out_target_j_imm32_T_2 = bits(io.inst, 19, 12)
node _io_out_target_j_imm32_T_3 = bits(io.inst, 20, 20)
node _io_out_target_j_imm32_T_4 = bits(io.inst, 30, 25)
node _io_out_target_j_imm32_T_5 = bits(io.inst, 24, 21)
node io_out_target_j_imm32_lo_hi = cat(_io_out_target_j_imm32_T_4, _io_out_target_j_imm32_T_5)
node io_out_target_j_imm32_lo = cat(io_out_target_j_imm32_lo_hi, UInt<1>(0h0))
node io_out_target_j_imm32_hi_hi = cat(_io_out_target_j_imm32_T_1, _io_out_target_j_imm32_T_2)
node io_out_target_j_imm32_hi = cat(io_out_target_j_imm32_hi_hi, _io_out_target_j_imm32_T_3)
node io_out_target_j_imm32 = cat(io_out_target_j_imm32_hi, io_out_target_j_imm32_lo)
node _io_out_target_T_8 = asSInt(io.pc)
node _io_out_target_T_9 = asSInt(io_out_target_j_imm32)
node _io_out_target_T_10 = add(_io_out_target_T_8, _io_out_target_T_9)
node _io_out_target_T_11 = tail(_io_out_target_T_10, 1)
node _io_out_target_T_12 = asSInt(_io_out_target_T_11)
node _io_out_target_T_13 = and(_io_out_target_T_12, asSInt(UInt<2>(0h2)))
node _io_out_target_T_14 = asSInt(_io_out_target_T_13)
node _io_out_target_T_15 = asUInt(_io_out_target_T_14)
node _io_out_target_T_16 = mux(cs_is_br, _io_out_target_T_7, _io_out_target_T_15)
connect io.out.target, _io_out_target_T_16
node _io_out_cfi_type_T = mux(cs_is_br, UInt<3>(0h1), UInt<3>(0h0))
node _io_out_cfi_type_T_1 = mux(cs_is_jal, UInt<3>(0h2), _io_out_cfi_type_T)
node _io_out_cfi_type_T_2 = mux(cs_is_jalr, UInt<3>(0h3), _io_out_cfi_type_T_1)
connect io.out.cfi_type, _io_out_cfi_type_T_2
node _br_offset_T = bits(io.inst, 7, 7)
node _br_offset_T_1 = bits(io.inst, 30, 25)
node _br_offset_T_2 = bits(io.inst, 11, 8)
node br_offset_lo = cat(_br_offset_T_2, UInt<1>(0h0))
node br_offset_hi = cat(_br_offset_T, _br_offset_T_1)
node br_offset = cat(br_offset_hi, br_offset_lo)
node _io_out_sfb_offset_valid_T = bits(io.inst, 31, 31)
node _io_out_sfb_offset_valid_T_1 = eq(_io_out_sfb_offset_valid_T, UInt<1>(0h0))
node _io_out_sfb_offset_valid_T_2 = and(cs_is_br, _io_out_sfb_offset_valid_T_1)
node _io_out_sfb_offset_valid_T_3 = neq(br_offset, UInt<1>(0h0))
node _io_out_sfb_offset_valid_T_4 = and(_io_out_sfb_offset_valid_T_2, _io_out_sfb_offset_valid_T_3)
node _io_out_sfb_offset_valid_T_5 = shr(br_offset, 6)
node _io_out_sfb_offset_valid_T_6 = eq(_io_out_sfb_offset_valid_T_5, UInt<1>(0h0))
node _io_out_sfb_offset_valid_T_7 = and(_io_out_sfb_offset_valid_T_4, _io_out_sfb_offset_valid_T_6)
connect io.out.sfb_offset.valid, _io_out_sfb_offset_valid_T_7
connect io.out.sfb_offset.bits, br_offset
node _io_out_shadowable_T = eq(cs_has_rs2, UInt<1>(0h0))
node _io_out_shadowable_T_1 = bits(io.inst, 19, 15)
node _io_out_shadowable_T_2 = bits(io.inst, 11, 7)
node _io_out_shadowable_T_3 = eq(_io_out_shadowable_T_1, _io_out_shadowable_T_2)
node _io_out_shadowable_T_4 = or(_io_out_shadowable_T, _io_out_shadowable_T_3)
node _io_out_shadowable_T_5 = and(io.inst, UInt<32>(0hfe00707f))
node _io_out_shadowable_T_6 = eq(UInt<6>(0h33), _io_out_shadowable_T_5)
node _io_out_shadowable_T_7 = bits(io.inst, 19, 15)
node _io_out_shadowable_T_8 = eq(_io_out_shadowable_T_7, UInt<1>(0h0))
node _io_out_shadowable_T_9 = and(_io_out_shadowable_T_6, _io_out_shadowable_T_8)
node _io_out_shadowable_T_10 = or(_io_out_shadowable_T_4, _io_out_shadowable_T_9)
node _io_out_shadowable_T_11 = and(cs_is_shadowable, _io_out_shadowable_T_10)
connect io.out.shadowable, _io_out_shadowable_T_11 | module BranchDecode_5( // @[decode.scala:623:7]
input clock, // @[decode.scala:623:7]
input reset, // @[decode.scala:623:7]
input [31:0] io_inst, // @[decode.scala:625:14]
input [39:0] io_pc, // @[decode.scala:625:14]
output io_out_is_ret, // @[decode.scala:625:14]
output io_out_is_call, // @[decode.scala:625:14]
output [39:0] io_out_target, // @[decode.scala:625:14]
output [2:0] io_out_cfi_type, // @[decode.scala:625:14]
output io_out_sfb_offset_valid, // @[decode.scala:625:14]
output [5:0] io_out_sfb_offset_bits, // @[decode.scala:625:14]
output io_out_shadowable // @[decode.scala:625:14]
);
wire [31:0] io_inst_0 = io_inst; // @[decode.scala:623:7]
wire [39:0] io_pc_0 = io_pc; // @[decode.scala:623:7]
wire [31:0] bpd_csignals_decoded_plaInput = io_inst_0; // @[pla.scala:77:22]
wire _io_out_is_ret_T_6; // @[decode.scala:695:72]
wire [39:0] _io_out_target_T = io_pc_0; // @[decode.scala:623:7]
wire [39:0] _io_out_target_T_8 = io_pc_0; // @[decode.scala:623:7]
wire _io_out_is_call_T_3; // @[decode.scala:694:47]
wire [39:0] _io_out_target_T_16; // @[decode.scala:697:23]
wire [2:0] _io_out_cfi_type_T_2; // @[decode.scala:700:8]
wire _io_out_sfb_offset_valid_T_7; // @[decode.scala:710:76]
wire _io_out_shadowable_T_11; // @[decode.scala:712:41]
wire io_out_sfb_offset_valid_0; // @[decode.scala:623:7]
wire [5:0] io_out_sfb_offset_bits_0; // @[decode.scala:623:7]
wire io_out_is_ret_0; // @[decode.scala:623:7]
wire io_out_is_call_0; // @[decode.scala:623:7]
wire [39:0] io_out_target_0; // @[decode.scala:623:7]
wire [2:0] io_out_cfi_type_0; // @[decode.scala:623:7]
wire io_out_shadowable_0; // @[decode.scala:623:7]
wire [31:0] bpd_csignals_decoded_invInputs = ~bpd_csignals_decoded_plaInput; // @[pla.scala:77:22, :78:21]
wire [4:0] bpd_csignals_decoded_invMatrixOutputs; // @[pla.scala:120:37]
wire [4:0] bpd_csignals_decoded; // @[pla.scala:81:23]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_1 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_2 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_3 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_4 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_5 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_6 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_7 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_8 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_9 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_10 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_11 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_12 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_13 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_14 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_15 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_1 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_2 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_3 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_4 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_5 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_6 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_7 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_8 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_9 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_10 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_11 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_12 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_13 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_14 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_15 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_1 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_2 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_3 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_4 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_6 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_9 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_10 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_11 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_12 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_13 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_14 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_15 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_3 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_5 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_6 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_7 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_9 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_11 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_12 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_13 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_1 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_2 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_3 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_4 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_5 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_9 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_10 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_11 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_13 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_14 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_15 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5 = bpd_csignals_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_1 = bpd_csignals_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_9 = bpd_csignals_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_11 = bpd_csignals_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_13 = bpd_csignals_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_1 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_2 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_3 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_4 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_5 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_9 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_10 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_11 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_13 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_14 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_15 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7 = bpd_csignals_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_1 = bpd_csignals_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_2 = bpd_csignals_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_6 = bpd_csignals_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo = {bpd_csignals_decoded_andMatrixOutputs_lo_hi, bpd_csignals_decoded_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:90:45, :98:53]
wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi = {bpd_csignals_decoded_andMatrixOutputs_hi_hi, bpd_csignals_decoded_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53]
wire [7:0] _bpd_csignals_decoded_andMatrixOutputs_T = {bpd_csignals_decoded_andMatrixOutputs_hi, bpd_csignals_decoded_andMatrixOutputs_lo}; // @[pla.scala:98:53]
wire bpd_csignals_decoded_andMatrixOutputs_5_2 = &_bpd_csignals_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_1 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_2 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_4 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_5 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_4 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_5 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_8 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_7 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_12 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_13 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8 = bpd_csignals_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_1 = bpd_csignals_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_4 = bpd_csignals_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_3 = bpd_csignals_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8}; // @[pla.scala:91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_1}; // @[pla.scala:91:29, :98:53]
wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_1 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_1, bpd_csignals_decoded_andMatrixOutputs_lo_lo_1}; // @[pla.scala:98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_1}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:90:45, :98:53]
wire [2:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_1 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_1}; // @[pla.scala:91:29, :98:53]
wire [4:0] bpd_csignals_decoded_andMatrixOutputs_hi_1 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_1, bpd_csignals_decoded_andMatrixOutputs_hi_lo_1}; // @[pla.scala:98:53]
wire [8:0] _bpd_csignals_decoded_andMatrixOutputs_T_1 = {bpd_csignals_decoded_andMatrixOutputs_hi_1, bpd_csignals_decoded_andMatrixOutputs_lo_1}; // @[pla.scala:98:53]
wire bpd_csignals_decoded_andMatrixOutputs_9_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_2 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_3 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_4 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_5 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_6 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_7 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_8 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_12 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_15 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9 = bpd_csignals_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_3 = bpd_csignals_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_3 = bpd_csignals_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_6 = bpd_csignals_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_7 = bpd_csignals_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_8 = bpd_csignals_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_2 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_2 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_4 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_5 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_5 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_6 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_7 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_1 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_2 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_3 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_4 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_5 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_6 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_7 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_1 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_2 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_3 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_4 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_5 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_6 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_7 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_1 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_2 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_3 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_4 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_5 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_6 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_7 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_1 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_1 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_2 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_3 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_4 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_5 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_6 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13}; // @[pla.scala:91:29, :98:53]
wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_2 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14}; // @[pla.scala:91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11}; // @[pla.scala:91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9}; // @[pla.scala:91:29, :98:53]
wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_2 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo}; // @[pla.scala:98:53]
wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_2 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_2, bpd_csignals_decoded_andMatrixOutputs_lo_lo_2}; // @[pla.scala:98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_2}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_2 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo}; // @[pla.scala:98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_2}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :98:53]
wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_2 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_1, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo}; // @[pla.scala:98:53]
wire [7:0] bpd_csignals_decoded_andMatrixOutputs_hi_2 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_2, bpd_csignals_decoded_andMatrixOutputs_hi_lo_2}; // @[pla.scala:98:53]
wire [14:0] _bpd_csignals_decoded_andMatrixOutputs_T_2 = {bpd_csignals_decoded_andMatrixOutputs_hi_2, bpd_csignals_decoded_andMatrixOutputs_lo_2}; // @[pla.scala:98:53]
wire bpd_csignals_decoded_andMatrixOutputs_14_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_1 = bpd_csignals_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_2 = bpd_csignals_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_3 = bpd_csignals_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_4 = bpd_csignals_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_1}; // @[pla.scala:91:29, :98:53]
wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_3 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_2}; // @[pla.scala:91:29, :98:53]
wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_3 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_1, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_1}; // @[pla.scala:98:53]
wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_3 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_3, bpd_csignals_decoded_andMatrixOutputs_lo_lo_3}; // @[pla.scala:98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_3}; // @[pla.scala:90:45, :98:53]
wire [2:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_3 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_2 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_3}; // @[pla.scala:90:45, :98:53]
wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_3 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_2, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_1}; // @[pla.scala:98:53]
wire [6:0] bpd_csignals_decoded_andMatrixOutputs_hi_3 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_3, bpd_csignals_decoded_andMatrixOutputs_hi_lo_3}; // @[pla.scala:98:53]
wire [13:0] _bpd_csignals_decoded_andMatrixOutputs_T_3 = {bpd_csignals_decoded_andMatrixOutputs_hi_3, bpd_csignals_decoded_andMatrixOutputs_lo_3}; // @[pla.scala:98:53]
wire bpd_csignals_decoded_andMatrixOutputs_0_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_3; // @[pla.scala:98:{53,70}]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_2 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_2}; // @[pla.scala:91:29, :98:53]
wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_4 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_2 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_2 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_2}; // @[pla.scala:91:29, :98:53]
wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_4 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_2, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_2}; // @[pla.scala:98:53]
wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_4 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_4, bpd_csignals_decoded_andMatrixOutputs_lo_lo_4}; // @[pla.scala:98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_4}; // @[pla.scala:91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_2 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_4}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_4 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_2, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_1}; // @[pla.scala:98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_2 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_4}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_3 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_4}; // @[pla.scala:90:45, :98:53]
wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_4 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_3, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_2}; // @[pla.scala:98:53]
wire [7:0] bpd_csignals_decoded_andMatrixOutputs_hi_4 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_4, bpd_csignals_decoded_andMatrixOutputs_hi_lo_4}; // @[pla.scala:98:53]
wire [14:0] _bpd_csignals_decoded_andMatrixOutputs_T_4 = {bpd_csignals_decoded_andMatrixOutputs_hi_4, bpd_csignals_decoded_andMatrixOutputs_lo_4}; // @[pla.scala:98:53]
wire bpd_csignals_decoded_andMatrixOutputs_2_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_4; // @[pla.scala:98:{53,70}]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_5 = bpd_csignals_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_7 = bpd_csignals_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_8 = bpd_csignals_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_5}; // @[pla.scala:90:45, :98:53]
wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_5 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_5}; // @[pla.scala:91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_5}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_5}; // @[pla.scala:90:45, :98:53]
wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_5 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_5, bpd_csignals_decoded_andMatrixOutputs_hi_lo_5}; // @[pla.scala:98:53]
wire [6:0] _bpd_csignals_decoded_andMatrixOutputs_T_5 = {bpd_csignals_decoded_andMatrixOutputs_hi_5, bpd_csignals_decoded_andMatrixOutputs_lo_5}; // @[pla.scala:98:53]
wire bpd_csignals_decoded_andMatrixOutputs_12_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_5; // @[pla.scala:98:{53,70}]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_6 = bpd_csignals_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_7 = bpd_csignals_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_8 = bpd_csignals_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_12 = bpd_csignals_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_6 = bpd_csignals_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_7 = bpd_csignals_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_8 = bpd_csignals_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_12 = bpd_csignals_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_5}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_6}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_6 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_6, bpd_csignals_decoded_andMatrixOutputs_lo_lo_5}; // @[pla.scala:98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_6}; // @[pla.scala:91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_6}; // @[pla.scala:90:45, :98:53]
wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_6 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_6, bpd_csignals_decoded_andMatrixOutputs_hi_lo_6}; // @[pla.scala:98:53]
wire [7:0] _bpd_csignals_decoded_andMatrixOutputs_T_6 = {bpd_csignals_decoded_andMatrixOutputs_hi_6, bpd_csignals_decoded_andMatrixOutputs_lo_6}; // @[pla.scala:98:53]
wire bpd_csignals_decoded_andMatrixOutputs_6_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_6; // @[pla.scala:98:{53,70}]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_3 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_7}; // @[pla.scala:90:45, :98:53]
wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_7 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_6}; // @[pla.scala:91:29, :98:53]
wire [4:0] bpd_csignals_decoded_andMatrixOutputs_lo_7 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_7, bpd_csignals_decoded_andMatrixOutputs_lo_lo_6}; // @[pla.scala:98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_7 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_7}; // @[pla.scala:91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_4 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_7}; // @[pla.scala:90:45, :98:53]
wire [2:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_7 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_7}; // @[pla.scala:90:45, :98:53]
wire [4:0] bpd_csignals_decoded_andMatrixOutputs_hi_7 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_7, bpd_csignals_decoded_andMatrixOutputs_hi_lo_7}; // @[pla.scala:98:53]
wire [9:0] _bpd_csignals_decoded_andMatrixOutputs_T_7 = {bpd_csignals_decoded_andMatrixOutputs_hi_7, bpd_csignals_decoded_andMatrixOutputs_lo_7}; // @[pla.scala:98:53]
wire bpd_csignals_decoded_andMatrixOutputs_15_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_7; // @[pla.scala:98:{53,70}]
wire _bpd_csignals_decoded_orMatrixOutputs_T_4 = bpd_csignals_decoded_andMatrixOutputs_15_2; // @[pla.scala:98:70, :114:36]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_8 = bpd_csignals_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_10 = bpd_csignals_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_14 = bpd_csignals_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_8 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_8}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_8 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_8}; // @[pla.scala:90:45, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_8 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_8}; // @[pla.scala:90:45, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_8 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_8}; // @[pla.scala:90:45, :98:53]
wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_8 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_8, bpd_csignals_decoded_andMatrixOutputs_hi_lo_8}; // @[pla.scala:98:53]
wire [6:0] _bpd_csignals_decoded_andMatrixOutputs_T_8 = {bpd_csignals_decoded_andMatrixOutputs_hi_8, bpd_csignals_decoded_andMatrixOutputs_lo_8}; // @[pla.scala:98:53]
wire bpd_csignals_decoded_andMatrixOutputs_11_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_8; // @[pla.scala:98:{53,70}]
wire _bpd_csignals_decoded_orMatrixOutputs_T_5 = bpd_csignals_decoded_andMatrixOutputs_11_2; // @[pla.scala:98:70, :114:36]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_7 = bpd_csignals_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_10 = bpd_csignals_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_11 = bpd_csignals_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_14 = bpd_csignals_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_15 = bpd_csignals_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_3 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_3}; // @[pla.scala:91:29, :98:53]
wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_7 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_3 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_4 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_4}; // @[pla.scala:91:29, :98:53]
wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_9 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_4, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_3}; // @[pla.scala:98:53]
wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_9 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_9, bpd_csignals_decoded_andMatrixOutputs_lo_lo_7}; // @[pla.scala:98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_2 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_7}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_3 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_9}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_9 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_3, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_2}; // @[pla.scala:98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_3 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_9}; // @[pla.scala:91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_9}; // @[pla.scala:90:45, :98:53]
wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_9 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_5, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_3}; // @[pla.scala:98:53]
wire [7:0] bpd_csignals_decoded_andMatrixOutputs_hi_9 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_9, bpd_csignals_decoded_andMatrixOutputs_hi_lo_9}; // @[pla.scala:98:53]
wire [14:0] _bpd_csignals_decoded_andMatrixOutputs_T_9 = {bpd_csignals_decoded_andMatrixOutputs_hi_9, bpd_csignals_decoded_andMatrixOutputs_lo_9}; // @[pla.scala:98:53]
wire bpd_csignals_decoded_andMatrixOutputs_3_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_9; // @[pla.scala:98:{53,70}]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_4 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_4}; // @[pla.scala:91:29, :98:53]
wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_8 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_4 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_4}; // @[pla.scala:91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_5}; // @[pla.scala:91:29, :98:53]
wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_10 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_5, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_4}; // @[pla.scala:98:53]
wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_10 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_10, bpd_csignals_decoded_andMatrixOutputs_lo_lo_8}; // @[pla.scala:98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_3 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_8}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_4 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_10}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_10 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_4, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_3}; // @[pla.scala:98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_4 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_10}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_10}; // @[pla.scala:90:45, :98:53]
wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_10 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_6, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_4}; // @[pla.scala:98:53]
wire [7:0] bpd_csignals_decoded_andMatrixOutputs_hi_10 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_10, bpd_csignals_decoded_andMatrixOutputs_hi_lo_10}; // @[pla.scala:98:53]
wire [14:0] _bpd_csignals_decoded_andMatrixOutputs_T_10 = {bpd_csignals_decoded_andMatrixOutputs_hi_10, bpd_csignals_decoded_andMatrixOutputs_lo_10}; // @[pla.scala:98:53]
wire bpd_csignals_decoded_andMatrixOutputs_7_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_10; // @[pla.scala:98:{53,70}]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_9 = bpd_csignals_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_9 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_11, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_9}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_11 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_11, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_11}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_11 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_11, bpd_csignals_decoded_andMatrixOutputs_lo_lo_9}; // @[pla.scala:98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_11 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_11, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_11}; // @[pla.scala:91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_11 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_11, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_11}; // @[pla.scala:90:45, :98:53]
wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_11 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_11, bpd_csignals_decoded_andMatrixOutputs_hi_lo_11}; // @[pla.scala:98:53]
wire [7:0] _bpd_csignals_decoded_andMatrixOutputs_T_11 = {bpd_csignals_decoded_andMatrixOutputs_hi_11, bpd_csignals_decoded_andMatrixOutputs_lo_11}; // @[pla.scala:98:53]
wire bpd_csignals_decoded_andMatrixOutputs_1_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_11; // @[pla.scala:98:{53,70}]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_10 = bpd_csignals_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_6 = bpd_csignals_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_8 = bpd_csignals_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_9 = bpd_csignals_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_10 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_10}; // @[pla.scala:90:45, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_12 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_12}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_12 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_12, bpd_csignals_decoded_andMatrixOutputs_lo_lo_10}; // @[pla.scala:98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_12 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_12}; // @[pla.scala:91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_12 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_12}; // @[pla.scala:90:45, :98:53]
wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_12 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_12, bpd_csignals_decoded_andMatrixOutputs_hi_lo_12}; // @[pla.scala:98:53]
wire [7:0] _bpd_csignals_decoded_andMatrixOutputs_T_12 = {bpd_csignals_decoded_andMatrixOutputs_hi_12, bpd_csignals_decoded_andMatrixOutputs_lo_12}; // @[pla.scala:98:53]
wire bpd_csignals_decoded_andMatrixOutputs_13_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_12; // @[pla.scala:98:{53,70}]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_5}; // @[pla.scala:91:29, :98:53]
wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_11 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_4}; // @[pla.scala:91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_5}; // @[pla.scala:91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_6}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_13 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_6, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_5}; // @[pla.scala:98:53]
wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_13 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_13, bpd_csignals_decoded_andMatrixOutputs_lo_lo_11}; // @[pla.scala:98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_4 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_13, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_11}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_13, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_13}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_13 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_5, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_4}; // @[pla.scala:98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_13, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_13}; // @[pla.scala:91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_7 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_13, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_13}; // @[pla.scala:90:45, :98:53]
wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_13 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_7, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_5}; // @[pla.scala:98:53]
wire [7:0] bpd_csignals_decoded_andMatrixOutputs_hi_13 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_13, bpd_csignals_decoded_andMatrixOutputs_hi_lo_13}; // @[pla.scala:98:53]
wire [14:0] _bpd_csignals_decoded_andMatrixOutputs_T_13 = {bpd_csignals_decoded_andMatrixOutputs_hi_13, bpd_csignals_decoded_andMatrixOutputs_lo_13}; // @[pla.scala:98:53]
wire bpd_csignals_decoded_andMatrixOutputs_4_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_13; // @[pla.scala:98:{53,70}]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_6}; // @[pla.scala:91:29, :98:53]
wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_12 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_5}; // @[pla.scala:91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_6}; // @[pla.scala:91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_7 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_7}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_14 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_7, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_6}; // @[pla.scala:98:53]
wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_14 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_14, bpd_csignals_decoded_andMatrixOutputs_lo_lo_12}; // @[pla.scala:98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_14, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_12}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_14, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_14}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_14 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_6, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_5}; // @[pla.scala:98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_14, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_14}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_8 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_14, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_14}; // @[pla.scala:90:45, :98:53]
wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_14 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_8, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_6}; // @[pla.scala:98:53]
wire [7:0] bpd_csignals_decoded_andMatrixOutputs_hi_14 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_14, bpd_csignals_decoded_andMatrixOutputs_hi_lo_14}; // @[pla.scala:98:53]
wire [14:0] _bpd_csignals_decoded_andMatrixOutputs_T_14 = {bpd_csignals_decoded_andMatrixOutputs_hi_14, bpd_csignals_decoded_andMatrixOutputs_lo_14}; // @[pla.scala:98:53]
wire bpd_csignals_decoded_andMatrixOutputs_8_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_14; // @[pla.scala:98:{53,70}]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_7 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_7}; // @[pla.scala:91:29, :98:53]
wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_13 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_6}; // @[pla.scala:91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_7 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_7}; // @[pla.scala:91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_8 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_8}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_15 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_8, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_7}; // @[pla.scala:98:53]
wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_15 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_15, bpd_csignals_decoded_andMatrixOutputs_lo_lo_13}; // @[pla.scala:98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_15, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_13}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_7 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_15, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_15}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_15 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_7, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_6}; // @[pla.scala:98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_7 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_15, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_15}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_9 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_15, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_15}; // @[pla.scala:90:45, :98:53]
wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_15 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_9, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_7}; // @[pla.scala:98:53]
wire [7:0] bpd_csignals_decoded_andMatrixOutputs_hi_15 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_15, bpd_csignals_decoded_andMatrixOutputs_hi_lo_15}; // @[pla.scala:98:53]
wire [14:0] _bpd_csignals_decoded_andMatrixOutputs_T_15 = {bpd_csignals_decoded_andMatrixOutputs_hi_15, bpd_csignals_decoded_andMatrixOutputs_lo_15}; // @[pla.scala:98:53]
wire bpd_csignals_decoded_andMatrixOutputs_10_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_15; // @[pla.scala:98:{53,70}]
wire [1:0] bpd_csignals_decoded_orMatrixOutputs_lo = {bpd_csignals_decoded_andMatrixOutputs_2_2, bpd_csignals_decoded_andMatrixOutputs_10_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] bpd_csignals_decoded_orMatrixOutputs_hi = {bpd_csignals_decoded_andMatrixOutputs_14_2, bpd_csignals_decoded_andMatrixOutputs_0_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] _bpd_csignals_decoded_orMatrixOutputs_T = {bpd_csignals_decoded_orMatrixOutputs_hi, bpd_csignals_decoded_orMatrixOutputs_lo}; // @[pla.scala:114:19]
wire _bpd_csignals_decoded_orMatrixOutputs_T_1 = |_bpd_csignals_decoded_orMatrixOutputs_T; // @[pla.scala:114:{19,36}]
wire [1:0] bpd_csignals_decoded_orMatrixOutputs_lo_lo = {bpd_csignals_decoded_andMatrixOutputs_8_2, bpd_csignals_decoded_andMatrixOutputs_10_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] bpd_csignals_decoded_orMatrixOutputs_lo_hi_hi = {bpd_csignals_decoded_andMatrixOutputs_7_2, bpd_csignals_decoded_andMatrixOutputs_1_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] bpd_csignals_decoded_orMatrixOutputs_lo_hi = {bpd_csignals_decoded_orMatrixOutputs_lo_hi_hi, bpd_csignals_decoded_andMatrixOutputs_4_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] bpd_csignals_decoded_orMatrixOutputs_lo_1 = {bpd_csignals_decoded_orMatrixOutputs_lo_hi, bpd_csignals_decoded_orMatrixOutputs_lo_lo}; // @[pla.scala:114:19]
wire [1:0] bpd_csignals_decoded_orMatrixOutputs_hi_lo_hi = {bpd_csignals_decoded_andMatrixOutputs_0_2, bpd_csignals_decoded_andMatrixOutputs_12_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] bpd_csignals_decoded_orMatrixOutputs_hi_lo = {bpd_csignals_decoded_orMatrixOutputs_hi_lo_hi, bpd_csignals_decoded_andMatrixOutputs_3_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] bpd_csignals_decoded_orMatrixOutputs_hi_hi_hi = {bpd_csignals_decoded_andMatrixOutputs_5_2, bpd_csignals_decoded_andMatrixOutputs_9_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] bpd_csignals_decoded_orMatrixOutputs_hi_hi = {bpd_csignals_decoded_orMatrixOutputs_hi_hi_hi, bpd_csignals_decoded_andMatrixOutputs_14_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] bpd_csignals_decoded_orMatrixOutputs_hi_1 = {bpd_csignals_decoded_orMatrixOutputs_hi_hi, bpd_csignals_decoded_orMatrixOutputs_hi_lo}; // @[pla.scala:114:19]
wire [10:0] _bpd_csignals_decoded_orMatrixOutputs_T_2 = {bpd_csignals_decoded_orMatrixOutputs_hi_1, bpd_csignals_decoded_orMatrixOutputs_lo_1}; // @[pla.scala:114:19]
wire _bpd_csignals_decoded_orMatrixOutputs_T_3 = |_bpd_csignals_decoded_orMatrixOutputs_T_2; // @[pla.scala:114:{19,36}]
wire [1:0] _bpd_csignals_decoded_orMatrixOutputs_T_6 = {bpd_csignals_decoded_andMatrixOutputs_6_2, bpd_csignals_decoded_andMatrixOutputs_13_2}; // @[pla.scala:98:70, :114:19]
wire _bpd_csignals_decoded_orMatrixOutputs_T_7 = |_bpd_csignals_decoded_orMatrixOutputs_T_6; // @[pla.scala:114:{19,36}]
wire [1:0] bpd_csignals_decoded_orMatrixOutputs_lo_2 = {_bpd_csignals_decoded_orMatrixOutputs_T_3, _bpd_csignals_decoded_orMatrixOutputs_T_1}; // @[pla.scala:102:36, :114:36]
wire [1:0] bpd_csignals_decoded_orMatrixOutputs_hi_hi_1 = {_bpd_csignals_decoded_orMatrixOutputs_T_7, _bpd_csignals_decoded_orMatrixOutputs_T_5}; // @[pla.scala:102:36, :114:36]
wire [2:0] bpd_csignals_decoded_orMatrixOutputs_hi_2 = {bpd_csignals_decoded_orMatrixOutputs_hi_hi_1, _bpd_csignals_decoded_orMatrixOutputs_T_4}; // @[pla.scala:102:36, :114:36]
wire [4:0] bpd_csignals_decoded_orMatrixOutputs = {bpd_csignals_decoded_orMatrixOutputs_hi_2, bpd_csignals_decoded_orMatrixOutputs_lo_2}; // @[pla.scala:102:36]
wire _bpd_csignals_decoded_invMatrixOutputs_T = bpd_csignals_decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31]
wire _bpd_csignals_decoded_invMatrixOutputs_T_1 = bpd_csignals_decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31]
wire _bpd_csignals_decoded_invMatrixOutputs_T_2 = bpd_csignals_decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31]
wire _bpd_csignals_decoded_invMatrixOutputs_T_3 = bpd_csignals_decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31]
wire _bpd_csignals_decoded_invMatrixOutputs_T_4 = bpd_csignals_decoded_orMatrixOutputs[4]; // @[pla.scala:102:36, :124:31]
wire [1:0] bpd_csignals_decoded_invMatrixOutputs_lo = {_bpd_csignals_decoded_invMatrixOutputs_T_1, _bpd_csignals_decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31]
wire [1:0] bpd_csignals_decoded_invMatrixOutputs_hi_hi = {_bpd_csignals_decoded_invMatrixOutputs_T_4, _bpd_csignals_decoded_invMatrixOutputs_T_3}; // @[pla.scala:120:37, :124:31]
wire [2:0] bpd_csignals_decoded_invMatrixOutputs_hi = {bpd_csignals_decoded_invMatrixOutputs_hi_hi, _bpd_csignals_decoded_invMatrixOutputs_T_2}; // @[pla.scala:120:37, :124:31]
assign bpd_csignals_decoded_invMatrixOutputs = {bpd_csignals_decoded_invMatrixOutputs_hi, bpd_csignals_decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37]
assign bpd_csignals_decoded = bpd_csignals_decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37]
wire bpd_csignals_0 = bpd_csignals_decoded[4]; // @[pla.scala:81:23]
wire cs_is_br = bpd_csignals_0; // @[Decode.scala:50:77]
wire bpd_csignals_1 = bpd_csignals_decoded[3]; // @[pla.scala:81:23]
wire cs_is_jal = bpd_csignals_1; // @[Decode.scala:50:77]
wire bpd_csignals_2 = bpd_csignals_decoded[2]; // @[pla.scala:81:23]
wire cs_is_jalr = bpd_csignals_2; // @[Decode.scala:50:77]
wire bpd_csignals_3 = bpd_csignals_decoded[1]; // @[pla.scala:81:23]
wire cs_is_shadowable = bpd_csignals_3; // @[Decode.scala:50:77]
wire bpd_csignals_4 = bpd_csignals_decoded[0]; // @[pla.scala:81:23]
wire cs_has_rs2 = bpd_csignals_4; // @[Decode.scala:50:77]
wire _io_out_is_call_T = cs_is_jal | cs_is_jalr; // @[decode.scala:689:34, :690:35, :694:32]
wire [4:0] _io_out_is_call_T_1 = io_inst_0[11:7]; // @[decode.scala:623:7]
wire [4:0] _io_out_is_ret_T_4 = io_inst_0[11:7]; // @[decode.scala:623:7]
wire [4:0] _io_out_shadowable_T_2 = io_inst_0[11:7]; // @[decode.scala:623:7]
wire _io_out_is_call_T_2 = _io_out_is_call_T_1 == 5'h1; // @[decode.scala:694:65]
assign _io_out_is_call_T_3 = _io_out_is_call_T & _io_out_is_call_T_2; // @[decode.scala:694:{32,47,65}]
assign io_out_is_call_0 = _io_out_is_call_T_3; // @[decode.scala:623:7, :694:47]
wire [4:0] _io_out_is_ret_T = io_inst_0[19:15]; // @[decode.scala:623:7]
wire [4:0] _io_out_shadowable_T_1 = io_inst_0[19:15]; // @[decode.scala:623:7]
wire [4:0] _io_out_shadowable_T_7 = io_inst_0[19:15]; // @[decode.scala:623:7]
wire [4:0] _io_out_is_ret_T_1 = _io_out_is_ret_T & 5'h1B; // @[decode.scala:695:51]
wire _io_out_is_ret_T_2 = _io_out_is_ret_T_1 == 5'h1; // @[decode.scala:695:51]
wire _io_out_is_ret_T_3 = cs_is_jalr & _io_out_is_ret_T_2; // @[decode.scala:690:35, :695:{32,51}]
wire _io_out_is_ret_T_5 = _io_out_is_ret_T_4 == 5'h0; // @[decode.scala:695:90]
assign _io_out_is_ret_T_6 = _io_out_is_ret_T_3 & _io_out_is_ret_T_5; // @[decode.scala:695:{32,72,90}]
assign io_out_is_ret_0 = _io_out_is_ret_T_6; // @[decode.scala:623:7, :695:72]
wire _io_out_target_b_imm32_T = io_inst_0[31]; // @[decode.scala:623:7]
wire _io_out_target_j_imm32_T = io_inst_0[31]; // @[decode.scala:623:7]
wire _io_out_sfb_offset_valid_T = io_inst_0[31]; // @[decode.scala:623:7, :710:50]
wire [19:0] _io_out_target_b_imm32_T_1 = {20{_io_out_target_b_imm32_T}}; // @[consts.scala:337:{27,35}]
wire _io_out_target_b_imm32_T_2 = io_inst_0[7]; // @[decode.scala:623:7]
wire _br_offset_T = io_inst_0[7]; // @[decode.scala:623:7, :708:30]
wire [5:0] _io_out_target_b_imm32_T_3 = io_inst_0[30:25]; // @[decode.scala:623:7]
wire [5:0] _io_out_target_j_imm32_T_4 = io_inst_0[30:25]; // @[decode.scala:623:7]
wire [5:0] _br_offset_T_1 = io_inst_0[30:25]; // @[decode.scala:623:7, :708:42]
wire [3:0] _io_out_target_b_imm32_T_4 = io_inst_0[11:8]; // @[decode.scala:623:7]
wire [3:0] _br_offset_T_2 = io_inst_0[11:8]; // @[decode.scala:623:7, :708:58]
wire [4:0] io_out_target_b_imm32_lo = {_io_out_target_b_imm32_T_4, 1'h0}; // @[consts.scala:337:{22,68}]
wire [20:0] io_out_target_b_imm32_hi_hi = {_io_out_target_b_imm32_T_1, _io_out_target_b_imm32_T_2}; // @[consts.scala:337:{22,27,46}]
wire [26:0] io_out_target_b_imm32_hi = {io_out_target_b_imm32_hi_hi, _io_out_target_b_imm32_T_3}; // @[consts.scala:337:{22,55}]
wire [31:0] io_out_target_b_imm32 = {io_out_target_b_imm32_hi, io_out_target_b_imm32_lo}; // @[consts.scala:337:22]
wire [31:0] _io_out_target_T_1 = io_out_target_b_imm32; // @[consts.scala:337:22, :338:27]
wire [40:0] _io_out_target_T_2 = {_io_out_target_T[39], _io_out_target_T} + {{9{_io_out_target_T_1[31]}}, _io_out_target_T_1}; // @[consts.scala:338:{10,17,27}]
wire [39:0] _io_out_target_T_3 = _io_out_target_T_2[39:0]; // @[consts.scala:338:17]
wire [39:0] _io_out_target_T_4 = _io_out_target_T_3; // @[consts.scala:338:17]
wire [39:0] _io_out_target_T_5 = _io_out_target_T_4 & 40'hFFFFFFFFFE; // @[consts.scala:338:{17,42}]
wire [39:0] _io_out_target_T_6 = _io_out_target_T_5; // @[consts.scala:338:42]
wire [39:0] _io_out_target_T_7 = _io_out_target_T_6; // @[consts.scala:338:{42,52}]
wire [11:0] _io_out_target_j_imm32_T_1 = {12{_io_out_target_j_imm32_T}}; // @[consts.scala:343:{27,35}]
wire [7:0] _io_out_target_j_imm32_T_2 = io_inst_0[19:12]; // @[decode.scala:623:7]
wire _io_out_target_j_imm32_T_3 = io_inst_0[20]; // @[decode.scala:623:7]
wire [3:0] _io_out_target_j_imm32_T_5 = io_inst_0[24:21]; // @[decode.scala:623:7]
wire [9:0] io_out_target_j_imm32_lo_hi = {_io_out_target_j_imm32_T_4, _io_out_target_j_imm32_T_5}; // @[consts.scala:343:{22,69,82}]
wire [10:0] io_out_target_j_imm32_lo = {io_out_target_j_imm32_lo_hi, 1'h0}; // @[consts.scala:343:22]
wire [19:0] io_out_target_j_imm32_hi_hi = {_io_out_target_j_imm32_T_1, _io_out_target_j_imm32_T_2}; // @[consts.scala:343:{22,27,46}]
wire [20:0] io_out_target_j_imm32_hi = {io_out_target_j_imm32_hi_hi, _io_out_target_j_imm32_T_3}; // @[consts.scala:343:{22,59}]
wire [31:0] io_out_target_j_imm32 = {io_out_target_j_imm32_hi, io_out_target_j_imm32_lo}; // @[consts.scala:343:22]
wire [31:0] _io_out_target_T_9 = io_out_target_j_imm32; // @[consts.scala:343:22, :344:27]
wire [40:0] _io_out_target_T_10 = {_io_out_target_T_8[39], _io_out_target_T_8} + {{9{_io_out_target_T_9[31]}}, _io_out_target_T_9}; // @[consts.scala:344:{10,17,27}]
wire [39:0] _io_out_target_T_11 = _io_out_target_T_10[39:0]; // @[consts.scala:344:17]
wire [39:0] _io_out_target_T_12 = _io_out_target_T_11; // @[consts.scala:344:17]
wire [39:0] _io_out_target_T_13 = _io_out_target_T_12 & 40'hFFFFFFFFFE; // @[consts.scala:344:{17,42}]
wire [39:0] _io_out_target_T_14 = _io_out_target_T_13; // @[consts.scala:344:42]
wire [39:0] _io_out_target_T_15 = _io_out_target_T_14; // @[consts.scala:344:{42,52}]
assign _io_out_target_T_16 = cs_is_br ? _io_out_target_T_7 : _io_out_target_T_15; // @[decode.scala:688:33, :697:23]
assign io_out_target_0 = _io_out_target_T_16; // @[decode.scala:623:7, :697:23]
wire [2:0] _io_out_cfi_type_T = {2'h0, cs_is_br}; // @[decode.scala:688:33, :704:8]
wire [2:0] _io_out_cfi_type_T_1 = cs_is_jal ? 3'h2 : _io_out_cfi_type_T; // @[decode.scala:689:34, :702:8, :704:8]
assign _io_out_cfi_type_T_2 = cs_is_jalr ? 3'h3 : _io_out_cfi_type_T_1; // @[decode.scala:690:35, :700:8, :702:8]
assign io_out_cfi_type_0 = _io_out_cfi_type_T_2; // @[decode.scala:623:7, :700:8]
wire [4:0] br_offset_lo = {_br_offset_T_2, 1'h0}; // @[decode.scala:708:{22,58}]
wire [6:0] br_offset_hi = {_br_offset_T, _br_offset_T_1}; // @[decode.scala:708:{22,30,42}]
wire [11:0] br_offset = {br_offset_hi, br_offset_lo}; // @[decode.scala:708:22]
wire _io_out_sfb_offset_valid_T_1 = ~_io_out_sfb_offset_valid_T; // @[decode.scala:710:{42,50}]
wire _io_out_sfb_offset_valid_T_2 = cs_is_br & _io_out_sfb_offset_valid_T_1; // @[decode.scala:688:33, :710:{39,42}]
wire _io_out_sfb_offset_valid_T_3 = |br_offset; // @[decode.scala:708:22, :710:68]
wire _io_out_sfb_offset_valid_T_4 = _io_out_sfb_offset_valid_T_2 & _io_out_sfb_offset_valid_T_3; // @[decode.scala:710:{39,55,68}]
wire [5:0] _io_out_sfb_offset_valid_T_5 = br_offset[11:6]; // @[decode.scala:708:22, :710:90]
wire _io_out_sfb_offset_valid_T_6 = _io_out_sfb_offset_valid_T_5 == 6'h0; // @[decode.scala:710:{90,117}]
assign _io_out_sfb_offset_valid_T_7 = _io_out_sfb_offset_valid_T_4 & _io_out_sfb_offset_valid_T_6; // @[decode.scala:710:{55,76,117}]
assign io_out_sfb_offset_valid_0 = _io_out_sfb_offset_valid_T_7; // @[decode.scala:623:7, :710:76]
assign io_out_sfb_offset_bits_0 = br_offset[5:0]; // @[decode.scala:623:7, :708:22, :711:27]
wire _io_out_shadowable_T = ~cs_has_rs2; // @[decode.scala:692:35, :713:5]
wire _io_out_shadowable_T_3 = _io_out_shadowable_T_1 == _io_out_shadowable_T_2; // @[decode.scala:714:22]
wire _io_out_shadowable_T_4 = _io_out_shadowable_T | _io_out_shadowable_T_3; // @[decode.scala:713:{5,17}, :714:22]
wire [31:0] _io_out_shadowable_T_5 = io_inst_0 & 32'hFE00707F; // @[decode.scala:623:7, :715:14]
wire _io_out_shadowable_T_6 = _io_out_shadowable_T_5 == 32'h33; // @[decode.scala:715:14]
wire _io_out_shadowable_T_8 = _io_out_shadowable_T_7 == 5'h0; // @[decode.scala:695:90, :715:41]
wire _io_out_shadowable_T_9 = _io_out_shadowable_T_6 & _io_out_shadowable_T_8; // @[decode.scala:715:{14,22,41}]
wire _io_out_shadowable_T_10 = _io_out_shadowable_T_4 | _io_out_shadowable_T_9; // @[decode.scala:713:17, :714:42, :715:22]
assign _io_out_shadowable_T_11 = cs_is_shadowable & _io_out_shadowable_T_10; // @[decode.scala:691:41, :712:41, :714:42]
assign io_out_shadowable_0 = _io_out_shadowable_T_11; // @[decode.scala:623:7, :712:41]
assign io_out_is_ret = io_out_is_ret_0; // @[decode.scala:623:7]
assign io_out_is_call = io_out_is_call_0; // @[decode.scala:623:7]
assign io_out_target = io_out_target_0; // @[decode.scala:623:7]
assign io_out_cfi_type = io_out_cfi_type_0; // @[decode.scala:623:7]
assign io_out_sfb_offset_valid = io_out_sfb_offset_valid_0; // @[decode.scala:623:7]
assign io_out_sfb_offset_bits = io_out_sfb_offset_bits_0; // @[decode.scala:623:7]
assign io_out_shadowable = io_out_shadowable_0; // @[decode.scala:623:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_46 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_sink_extend of AsyncResetSynchronizerShiftReg_w1_d3_i0_46
connect io_out_sink_extend.clock, clock
connect io_out_sink_extend.reset, reset
connect io_out_sink_extend.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_sink_extend.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_46( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_46 io_out_sink_extend ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module Tile_76 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>}
inst tile_0_0 of PE_332
connect tile_0_0.clock, clock
connect tile_0_0.reset, reset
connect tile_0_0.io.in_a, io.in_a[0]
connect tile_0_0.io.in_b, io.in_b[0]
connect tile_0_0.io.in_d, io.in_d[0]
connect tile_0_0.io.in_control.shift, io.in_control[0].shift
connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate
connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow
connect tile_0_0.io.in_valid, io.in_valid[0]
connect tile_0_0.io.in_id, io.in_id[0]
connect tile_0_0.io.in_last, io.in_last[0]
connect io.out_c[0], tile_0_0.io.out_c
connect io.out_control[0], tile_0_0.io.out_control
connect io.out_id[0], tile_0_0.io.out_id
connect io.out_last[0], tile_0_0.io.out_last
connect io.out_valid[0], tile_0_0.io.out_valid
connect io.out_b[0], tile_0_0.io.out_b
connect io.bad_dataflow, tile_0_0.io.bad_dataflow
connect io.out_a[0], tile_0_0.io.out_a | module Tile_76( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [7:0] io_in_a_0, // @[Tile.scala:17:14]
input [19:0] io_in_b_0, // @[Tile.scala:17:14]
input [19:0] io_in_d_0, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [2:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [7:0] io_out_a_0, // @[Tile.scala:17:14]
output [19:0] io_out_c_0, // @[Tile.scala:17:14]
output [19:0] io_out_b_0, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [2:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0 // @[Tile.scala:17:14]
);
wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7]
wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7]
wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44]
wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
PE_332 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0_0), // @[Tile.scala:16:7]
.io_in_b (io_in_b_0_0), // @[Tile.scala:16:7]
.io_in_d (io_in_d_0_0), // @[Tile.scala:16:7]
.io_out_a (io_out_a_0_0),
.io_out_b (io_out_b_0_0),
.io_out_c (io_out_c_0_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0)
); // @[Tile.scala:42:44]
assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7]
assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7]
assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module Tile_206 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>}
inst tile_0_0 of PE_462
connect tile_0_0.clock, clock
connect tile_0_0.reset, reset
connect tile_0_0.io.in_a, io.in_a[0]
connect tile_0_0.io.in_b, io.in_b[0]
connect tile_0_0.io.in_d, io.in_d[0]
connect tile_0_0.io.in_control.shift, io.in_control[0].shift
connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate
connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow
connect tile_0_0.io.in_valid, io.in_valid[0]
connect tile_0_0.io.in_id, io.in_id[0]
connect tile_0_0.io.in_last, io.in_last[0]
connect io.out_c[0], tile_0_0.io.out_c
connect io.out_control[0], tile_0_0.io.out_control
connect io.out_id[0], tile_0_0.io.out_id
connect io.out_last[0], tile_0_0.io.out_last
connect io.out_valid[0], tile_0_0.io.out_valid
connect io.out_b[0], tile_0_0.io.out_b
connect io.bad_dataflow, tile_0_0.io.bad_dataflow
connect io.out_a[0], tile_0_0.io.out_a | module Tile_206( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [7:0] io_in_a_0, // @[Tile.scala:17:14]
input [19:0] io_in_b_0, // @[Tile.scala:17:14]
input [19:0] io_in_d_0, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [2:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [7:0] io_out_a_0, // @[Tile.scala:17:14]
output [19:0] io_out_c_0, // @[Tile.scala:17:14]
output [19:0] io_out_b_0, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [2:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0 // @[Tile.scala:17:14]
);
wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7]
wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7]
wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44]
wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
PE_462 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0_0), // @[Tile.scala:16:7]
.io_in_b (io_in_b_0_0), // @[Tile.scala:16:7]
.io_in_d (io_in_d_0_0), // @[Tile.scala:16:7]
.io_out_a (io_out_a_0_0),
.io_out_b (io_out_b_0_0),
.io_out_c (io_out_c_0_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0)
); // @[Tile.scala:42:44]
assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7]
assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7]
assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_90 :
output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node rawIn_exp = bits(io.in, 31, 23)
node _rawIn_isZero_T = bits(rawIn_exp, 8, 6)
node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0))
node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7)
node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3))
wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T)
connect rawIn.isNaN, _rawIn_out_isNaN_T_1
node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0))
node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1)
connect rawIn.isInf, _rawIn_out_isInf_T_2
connect rawIn.isZero, rawIn_isZero
node _rawIn_out_sign_T = bits(io.in, 32, 32)
connect rawIn.sign, _rawIn_out_sign_T
node _rawIn_out_sExp_T = cvt(rawIn_exp)
connect rawIn.sExp, _rawIn_out_sExp_T
node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0))
node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T)
node _rawIn_out_sig_T_2 = bits(io.in, 22, 0)
node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2)
connect rawIn.sig, _rawIn_out_sig_T_3
node _io_out_T = shl(io.in, 0)
connect io.out, _io_out_T
node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22)
node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0))
node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0))
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RecFNToRecFN_90( // @[RecFNToRecFN.scala:44:5]
input [32:0] io_in, // @[RecFNToRecFN.scala:48:16]
output [32:0] io_out // @[RecFNToRecFN.scala:48:16]
);
wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5]
wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35]
wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54]
wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5]
wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5]
wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35]
wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}]
wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46]
assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54]
assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module BankBinder :
input clock : Clock
input reset : Reset
output auto : { flip in_3 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip in_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip in_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip in_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out_3 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeIn.d.bits.corrupt
invalidate nodeIn.d.bits.data
invalidate nodeIn.d.bits.denied
invalidate nodeIn.d.bits.sink
invalidate nodeIn.d.bits.source
invalidate nodeIn.d.bits.size
invalidate nodeIn.d.bits.param
invalidate nodeIn.d.bits.opcode
invalidate nodeIn.d.valid
invalidate nodeIn.d.ready
invalidate nodeIn.a.bits.corrupt
invalidate nodeIn.a.bits.data
invalidate nodeIn.a.bits.mask
invalidate nodeIn.a.bits.address
invalidate nodeIn.a.bits.source
invalidate nodeIn.a.bits.size
invalidate nodeIn.a.bits.param
invalidate nodeIn.a.bits.opcode
invalidate nodeIn.a.valid
invalidate nodeIn.a.ready
wire nodeIn_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeIn_1.d.bits.corrupt
invalidate nodeIn_1.d.bits.data
invalidate nodeIn_1.d.bits.denied
invalidate nodeIn_1.d.bits.sink
invalidate nodeIn_1.d.bits.source
invalidate nodeIn_1.d.bits.size
invalidate nodeIn_1.d.bits.param
invalidate nodeIn_1.d.bits.opcode
invalidate nodeIn_1.d.valid
invalidate nodeIn_1.d.ready
invalidate nodeIn_1.a.bits.corrupt
invalidate nodeIn_1.a.bits.data
invalidate nodeIn_1.a.bits.mask
invalidate nodeIn_1.a.bits.address
invalidate nodeIn_1.a.bits.source
invalidate nodeIn_1.a.bits.size
invalidate nodeIn_1.a.bits.param
invalidate nodeIn_1.a.bits.opcode
invalidate nodeIn_1.a.valid
invalidate nodeIn_1.a.ready
wire nodeIn_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeIn_2.d.bits.corrupt
invalidate nodeIn_2.d.bits.data
invalidate nodeIn_2.d.bits.denied
invalidate nodeIn_2.d.bits.sink
invalidate nodeIn_2.d.bits.source
invalidate nodeIn_2.d.bits.size
invalidate nodeIn_2.d.bits.param
invalidate nodeIn_2.d.bits.opcode
invalidate nodeIn_2.d.valid
invalidate nodeIn_2.d.ready
invalidate nodeIn_2.a.bits.corrupt
invalidate nodeIn_2.a.bits.data
invalidate nodeIn_2.a.bits.mask
invalidate nodeIn_2.a.bits.address
invalidate nodeIn_2.a.bits.source
invalidate nodeIn_2.a.bits.size
invalidate nodeIn_2.a.bits.param
invalidate nodeIn_2.a.bits.opcode
invalidate nodeIn_2.a.valid
invalidate nodeIn_2.a.ready
wire nodeIn_3 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeIn_3.d.bits.corrupt
invalidate nodeIn_3.d.bits.data
invalidate nodeIn_3.d.bits.denied
invalidate nodeIn_3.d.bits.sink
invalidate nodeIn_3.d.bits.source
invalidate nodeIn_3.d.bits.size
invalidate nodeIn_3.d.bits.param
invalidate nodeIn_3.d.bits.opcode
invalidate nodeIn_3.d.valid
invalidate nodeIn_3.d.ready
invalidate nodeIn_3.a.bits.corrupt
invalidate nodeIn_3.a.bits.data
invalidate nodeIn_3.a.bits.mask
invalidate nodeIn_3.a.bits.address
invalidate nodeIn_3.a.bits.source
invalidate nodeIn_3.a.bits.size
invalidate nodeIn_3.a.bits.param
invalidate nodeIn_3.a.bits.opcode
invalidate nodeIn_3.a.valid
invalidate nodeIn_3.a.ready
inst monitor of TLMonitor_56
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, nodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, nodeIn.d.bits.source
connect monitor.io.in.d.bits.size, nodeIn.d.bits.size
connect monitor.io.in.d.bits.param, nodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode
connect monitor.io.in.d.valid, nodeIn.d.valid
connect monitor.io.in.d.ready, nodeIn.d.ready
connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, nodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, nodeIn.a.bits.address
connect monitor.io.in.a.bits.source, nodeIn.a.bits.source
connect monitor.io.in.a.bits.size, nodeIn.a.bits.size
connect monitor.io.in.a.bits.param, nodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode
connect monitor.io.in.a.valid, nodeIn.a.valid
connect monitor.io.in.a.ready, nodeIn.a.ready
inst monitor_1 of TLMonitor_57
connect monitor_1.clock, clock
connect monitor_1.reset, reset
connect monitor_1.io.in.d.bits.corrupt, nodeIn_1.d.bits.corrupt
connect monitor_1.io.in.d.bits.data, nodeIn_1.d.bits.data
connect monitor_1.io.in.d.bits.denied, nodeIn_1.d.bits.denied
connect monitor_1.io.in.d.bits.sink, nodeIn_1.d.bits.sink
connect monitor_1.io.in.d.bits.source, nodeIn_1.d.bits.source
connect monitor_1.io.in.d.bits.size, nodeIn_1.d.bits.size
connect monitor_1.io.in.d.bits.param, nodeIn_1.d.bits.param
connect monitor_1.io.in.d.bits.opcode, nodeIn_1.d.bits.opcode
connect monitor_1.io.in.d.valid, nodeIn_1.d.valid
connect monitor_1.io.in.d.ready, nodeIn_1.d.ready
connect monitor_1.io.in.a.bits.corrupt, nodeIn_1.a.bits.corrupt
connect monitor_1.io.in.a.bits.data, nodeIn_1.a.bits.data
connect monitor_1.io.in.a.bits.mask, nodeIn_1.a.bits.mask
connect monitor_1.io.in.a.bits.address, nodeIn_1.a.bits.address
connect monitor_1.io.in.a.bits.source, nodeIn_1.a.bits.source
connect monitor_1.io.in.a.bits.size, nodeIn_1.a.bits.size
connect monitor_1.io.in.a.bits.param, nodeIn_1.a.bits.param
connect monitor_1.io.in.a.bits.opcode, nodeIn_1.a.bits.opcode
connect monitor_1.io.in.a.valid, nodeIn_1.a.valid
connect monitor_1.io.in.a.ready, nodeIn_1.a.ready
inst monitor_2 of TLMonitor_58
connect monitor_2.clock, clock
connect monitor_2.reset, reset
connect monitor_2.io.in.d.bits.corrupt, nodeIn_2.d.bits.corrupt
connect monitor_2.io.in.d.bits.data, nodeIn_2.d.bits.data
connect monitor_2.io.in.d.bits.denied, nodeIn_2.d.bits.denied
connect monitor_2.io.in.d.bits.sink, nodeIn_2.d.bits.sink
connect monitor_2.io.in.d.bits.source, nodeIn_2.d.bits.source
connect monitor_2.io.in.d.bits.size, nodeIn_2.d.bits.size
connect monitor_2.io.in.d.bits.param, nodeIn_2.d.bits.param
connect monitor_2.io.in.d.bits.opcode, nodeIn_2.d.bits.opcode
connect monitor_2.io.in.d.valid, nodeIn_2.d.valid
connect monitor_2.io.in.d.ready, nodeIn_2.d.ready
connect monitor_2.io.in.a.bits.corrupt, nodeIn_2.a.bits.corrupt
connect monitor_2.io.in.a.bits.data, nodeIn_2.a.bits.data
connect monitor_2.io.in.a.bits.mask, nodeIn_2.a.bits.mask
connect monitor_2.io.in.a.bits.address, nodeIn_2.a.bits.address
connect monitor_2.io.in.a.bits.source, nodeIn_2.a.bits.source
connect monitor_2.io.in.a.bits.size, nodeIn_2.a.bits.size
connect monitor_2.io.in.a.bits.param, nodeIn_2.a.bits.param
connect monitor_2.io.in.a.bits.opcode, nodeIn_2.a.bits.opcode
connect monitor_2.io.in.a.valid, nodeIn_2.a.valid
connect monitor_2.io.in.a.ready, nodeIn_2.a.ready
inst monitor_3 of TLMonitor_59
connect monitor_3.clock, clock
connect monitor_3.reset, reset
connect monitor_3.io.in.d.bits.corrupt, nodeIn_3.d.bits.corrupt
connect monitor_3.io.in.d.bits.data, nodeIn_3.d.bits.data
connect monitor_3.io.in.d.bits.denied, nodeIn_3.d.bits.denied
connect monitor_3.io.in.d.bits.sink, nodeIn_3.d.bits.sink
connect monitor_3.io.in.d.bits.source, nodeIn_3.d.bits.source
connect monitor_3.io.in.d.bits.size, nodeIn_3.d.bits.size
connect monitor_3.io.in.d.bits.param, nodeIn_3.d.bits.param
connect monitor_3.io.in.d.bits.opcode, nodeIn_3.d.bits.opcode
connect monitor_3.io.in.d.valid, nodeIn_3.d.valid
connect monitor_3.io.in.d.ready, nodeIn_3.d.ready
connect monitor_3.io.in.a.bits.corrupt, nodeIn_3.a.bits.corrupt
connect monitor_3.io.in.a.bits.data, nodeIn_3.a.bits.data
connect monitor_3.io.in.a.bits.mask, nodeIn_3.a.bits.mask
connect monitor_3.io.in.a.bits.address, nodeIn_3.a.bits.address
connect monitor_3.io.in.a.bits.source, nodeIn_3.a.bits.source
connect monitor_3.io.in.a.bits.size, nodeIn_3.a.bits.size
connect monitor_3.io.in.a.bits.param, nodeIn_3.a.bits.param
connect monitor_3.io.in.a.bits.opcode, nodeIn_3.a.bits.opcode
connect monitor_3.io.in.a.valid, nodeIn_3.a.valid
connect monitor_3.io.in.a.ready, nodeIn_3.a.ready
wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeOut.d.bits.corrupt
invalidate nodeOut.d.bits.data
invalidate nodeOut.d.bits.denied
invalidate nodeOut.d.bits.sink
invalidate nodeOut.d.bits.source
invalidate nodeOut.d.bits.size
invalidate nodeOut.d.bits.param
invalidate nodeOut.d.bits.opcode
invalidate nodeOut.d.valid
invalidate nodeOut.d.ready
invalidate nodeOut.a.bits.corrupt
invalidate nodeOut.a.bits.data
invalidate nodeOut.a.bits.mask
invalidate nodeOut.a.bits.address
invalidate nodeOut.a.bits.source
invalidate nodeOut.a.bits.size
invalidate nodeOut.a.bits.param
invalidate nodeOut.a.bits.opcode
invalidate nodeOut.a.valid
invalidate nodeOut.a.ready
wire x1_nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate x1_nodeOut.d.bits.corrupt
invalidate x1_nodeOut.d.bits.data
invalidate x1_nodeOut.d.bits.denied
invalidate x1_nodeOut.d.bits.sink
invalidate x1_nodeOut.d.bits.source
invalidate x1_nodeOut.d.bits.size
invalidate x1_nodeOut.d.bits.param
invalidate x1_nodeOut.d.bits.opcode
invalidate x1_nodeOut.d.valid
invalidate x1_nodeOut.d.ready
invalidate x1_nodeOut.a.bits.corrupt
invalidate x1_nodeOut.a.bits.data
invalidate x1_nodeOut.a.bits.mask
invalidate x1_nodeOut.a.bits.address
invalidate x1_nodeOut.a.bits.source
invalidate x1_nodeOut.a.bits.size
invalidate x1_nodeOut.a.bits.param
invalidate x1_nodeOut.a.bits.opcode
invalidate x1_nodeOut.a.valid
invalidate x1_nodeOut.a.ready
wire x1_nodeOut_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate x1_nodeOut_1.d.bits.corrupt
invalidate x1_nodeOut_1.d.bits.data
invalidate x1_nodeOut_1.d.bits.denied
invalidate x1_nodeOut_1.d.bits.sink
invalidate x1_nodeOut_1.d.bits.source
invalidate x1_nodeOut_1.d.bits.size
invalidate x1_nodeOut_1.d.bits.param
invalidate x1_nodeOut_1.d.bits.opcode
invalidate x1_nodeOut_1.d.valid
invalidate x1_nodeOut_1.d.ready
invalidate x1_nodeOut_1.a.bits.corrupt
invalidate x1_nodeOut_1.a.bits.data
invalidate x1_nodeOut_1.a.bits.mask
invalidate x1_nodeOut_1.a.bits.address
invalidate x1_nodeOut_1.a.bits.source
invalidate x1_nodeOut_1.a.bits.size
invalidate x1_nodeOut_1.a.bits.param
invalidate x1_nodeOut_1.a.bits.opcode
invalidate x1_nodeOut_1.a.valid
invalidate x1_nodeOut_1.a.ready
wire x1_nodeOut_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate x1_nodeOut_2.d.bits.corrupt
invalidate x1_nodeOut_2.d.bits.data
invalidate x1_nodeOut_2.d.bits.denied
invalidate x1_nodeOut_2.d.bits.sink
invalidate x1_nodeOut_2.d.bits.source
invalidate x1_nodeOut_2.d.bits.size
invalidate x1_nodeOut_2.d.bits.param
invalidate x1_nodeOut_2.d.bits.opcode
invalidate x1_nodeOut_2.d.valid
invalidate x1_nodeOut_2.d.ready
invalidate x1_nodeOut_2.a.bits.corrupt
invalidate x1_nodeOut_2.a.bits.data
invalidate x1_nodeOut_2.a.bits.mask
invalidate x1_nodeOut_2.a.bits.address
invalidate x1_nodeOut_2.a.bits.source
invalidate x1_nodeOut_2.a.bits.size
invalidate x1_nodeOut_2.a.bits.param
invalidate x1_nodeOut_2.a.bits.opcode
invalidate x1_nodeOut_2.a.valid
invalidate x1_nodeOut_2.a.ready
connect auto.out_0, nodeOut
connect auto.out_1, x1_nodeOut
connect auto.out_2, x1_nodeOut_1
connect auto.out_3, x1_nodeOut_2
connect nodeIn, auto.in_0
connect nodeIn_1, auto.in_1
connect nodeIn_2, auto.in_2
connect nodeIn_3, auto.in_3
connect nodeOut, nodeIn
connect x1_nodeOut, nodeIn_1
connect x1_nodeOut_1, nodeIn_2
connect x1_nodeOut_2, nodeIn_3 | module BankBinder( // @[BankBinder.scala:61:9]
input clock, // @[BankBinder.scala:61:9]
input reset, // @[BankBinder.scala:61:9]
output auto_in_3_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_3_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_3_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_3_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_3_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_3_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_3_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_3_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_3_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_3_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_3_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_3_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_3_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_3_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_3_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_3_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_in_3_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_3_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_3_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_2_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_2_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_2_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_2_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_2_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_2_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_2_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_2_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_2_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_2_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_2_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_2_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_2_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_2_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_2_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_2_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_in_2_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_2_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_2_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_1_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_1_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_1_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_1_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_1_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_1_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_1_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_1_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_1_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_0_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_0_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_0_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_0_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_0_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_0_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_0_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_0_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_3_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_3_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_3_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_3_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_3_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_3_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_3_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_3_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_3_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_3_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_3_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_3_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_3_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_3_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_3_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_3_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_out_3_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_3_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_3_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_3_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_2_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_2_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_2_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_2_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_2_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_2_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_2_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_2_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_2_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_2_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_2_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_2_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_2_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_2_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_2_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_2_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_out_2_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_2_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_2_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_2_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_1_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_1_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_1_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_1_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_0_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_0_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_0_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_0_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_0_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_out_0_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_0_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_0_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
TLMonitor_56 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (auto_out_0_a_ready),
.io_in_a_valid (auto_in_0_a_valid),
.io_in_a_bits_opcode (auto_in_0_a_bits_opcode),
.io_in_a_bits_param (auto_in_0_a_bits_param),
.io_in_a_bits_size (auto_in_0_a_bits_size),
.io_in_a_bits_source (auto_in_0_a_bits_source),
.io_in_a_bits_address (auto_in_0_a_bits_address),
.io_in_a_bits_mask (auto_in_0_a_bits_mask),
.io_in_a_bits_corrupt (auto_in_0_a_bits_corrupt),
.io_in_d_ready (auto_in_0_d_ready),
.io_in_d_valid (auto_out_0_d_valid),
.io_in_d_bits_opcode (auto_out_0_d_bits_opcode),
.io_in_d_bits_param (auto_out_0_d_bits_param),
.io_in_d_bits_size (auto_out_0_d_bits_size),
.io_in_d_bits_source (auto_out_0_d_bits_source),
.io_in_d_bits_sink (auto_out_0_d_bits_sink),
.io_in_d_bits_denied (auto_out_0_d_bits_denied),
.io_in_d_bits_corrupt (auto_out_0_d_bits_corrupt)
); // @[Nodes.scala:27:25]
TLMonitor_57 monitor_1 ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (auto_out_1_a_ready),
.io_in_a_valid (auto_in_1_a_valid),
.io_in_a_bits_opcode (auto_in_1_a_bits_opcode),
.io_in_a_bits_param (auto_in_1_a_bits_param),
.io_in_a_bits_size (auto_in_1_a_bits_size),
.io_in_a_bits_source (auto_in_1_a_bits_source),
.io_in_a_bits_address (auto_in_1_a_bits_address),
.io_in_a_bits_mask (auto_in_1_a_bits_mask),
.io_in_a_bits_corrupt (auto_in_1_a_bits_corrupt),
.io_in_d_ready (auto_in_1_d_ready),
.io_in_d_valid (auto_out_1_d_valid),
.io_in_d_bits_opcode (auto_out_1_d_bits_opcode),
.io_in_d_bits_param (auto_out_1_d_bits_param),
.io_in_d_bits_size (auto_out_1_d_bits_size),
.io_in_d_bits_source (auto_out_1_d_bits_source),
.io_in_d_bits_sink (auto_out_1_d_bits_sink),
.io_in_d_bits_denied (auto_out_1_d_bits_denied),
.io_in_d_bits_corrupt (auto_out_1_d_bits_corrupt)
); // @[Nodes.scala:27:25]
TLMonitor_58 monitor_2 ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (auto_out_2_a_ready),
.io_in_a_valid (auto_in_2_a_valid),
.io_in_a_bits_opcode (auto_in_2_a_bits_opcode),
.io_in_a_bits_param (auto_in_2_a_bits_param),
.io_in_a_bits_size (auto_in_2_a_bits_size),
.io_in_a_bits_source (auto_in_2_a_bits_source),
.io_in_a_bits_address (auto_in_2_a_bits_address),
.io_in_a_bits_mask (auto_in_2_a_bits_mask),
.io_in_a_bits_corrupt (auto_in_2_a_bits_corrupt),
.io_in_d_ready (auto_in_2_d_ready),
.io_in_d_valid (auto_out_2_d_valid),
.io_in_d_bits_opcode (auto_out_2_d_bits_opcode),
.io_in_d_bits_param (auto_out_2_d_bits_param),
.io_in_d_bits_size (auto_out_2_d_bits_size),
.io_in_d_bits_source (auto_out_2_d_bits_source),
.io_in_d_bits_sink (auto_out_2_d_bits_sink),
.io_in_d_bits_denied (auto_out_2_d_bits_denied),
.io_in_d_bits_corrupt (auto_out_2_d_bits_corrupt)
); // @[Nodes.scala:27:25]
TLMonitor_59 monitor_3 ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (auto_out_3_a_ready),
.io_in_a_valid (auto_in_3_a_valid),
.io_in_a_bits_opcode (auto_in_3_a_bits_opcode),
.io_in_a_bits_param (auto_in_3_a_bits_param),
.io_in_a_bits_size (auto_in_3_a_bits_size),
.io_in_a_bits_source (auto_in_3_a_bits_source),
.io_in_a_bits_address (auto_in_3_a_bits_address),
.io_in_a_bits_mask (auto_in_3_a_bits_mask),
.io_in_a_bits_corrupt (auto_in_3_a_bits_corrupt),
.io_in_d_ready (auto_in_3_d_ready),
.io_in_d_valid (auto_out_3_d_valid),
.io_in_d_bits_opcode (auto_out_3_d_bits_opcode),
.io_in_d_bits_param (auto_out_3_d_bits_param),
.io_in_d_bits_size (auto_out_3_d_bits_size),
.io_in_d_bits_source (auto_out_3_d_bits_source),
.io_in_d_bits_sink (auto_out_3_d_bits_sink),
.io_in_d_bits_denied (auto_out_3_d_bits_denied),
.io_in_d_bits_corrupt (auto_out_3_d_bits_corrupt)
); // @[Nodes.scala:27:25]
assign auto_in_3_a_ready = auto_out_3_a_ready; // @[BankBinder.scala:61:9]
assign auto_in_3_d_valid = auto_out_3_d_valid; // @[BankBinder.scala:61:9]
assign auto_in_3_d_bits_opcode = auto_out_3_d_bits_opcode; // @[BankBinder.scala:61:9]
assign auto_in_3_d_bits_param = auto_out_3_d_bits_param; // @[BankBinder.scala:61:9]
assign auto_in_3_d_bits_size = auto_out_3_d_bits_size; // @[BankBinder.scala:61:9]
assign auto_in_3_d_bits_source = auto_out_3_d_bits_source; // @[BankBinder.scala:61:9]
assign auto_in_3_d_bits_denied = auto_out_3_d_bits_denied; // @[BankBinder.scala:61:9]
assign auto_in_3_d_bits_data = auto_out_3_d_bits_data; // @[BankBinder.scala:61:9]
assign auto_in_3_d_bits_corrupt = auto_out_3_d_bits_corrupt; // @[BankBinder.scala:61:9]
assign auto_in_2_a_ready = auto_out_2_a_ready; // @[BankBinder.scala:61:9]
assign auto_in_2_d_valid = auto_out_2_d_valid; // @[BankBinder.scala:61:9]
assign auto_in_2_d_bits_opcode = auto_out_2_d_bits_opcode; // @[BankBinder.scala:61:9]
assign auto_in_2_d_bits_param = auto_out_2_d_bits_param; // @[BankBinder.scala:61:9]
assign auto_in_2_d_bits_size = auto_out_2_d_bits_size; // @[BankBinder.scala:61:9]
assign auto_in_2_d_bits_source = auto_out_2_d_bits_source; // @[BankBinder.scala:61:9]
assign auto_in_2_d_bits_denied = auto_out_2_d_bits_denied; // @[BankBinder.scala:61:9]
assign auto_in_2_d_bits_data = auto_out_2_d_bits_data; // @[BankBinder.scala:61:9]
assign auto_in_2_d_bits_corrupt = auto_out_2_d_bits_corrupt; // @[BankBinder.scala:61:9]
assign auto_in_1_a_ready = auto_out_1_a_ready; // @[BankBinder.scala:61:9]
assign auto_in_1_d_valid = auto_out_1_d_valid; // @[BankBinder.scala:61:9]
assign auto_in_1_d_bits_opcode = auto_out_1_d_bits_opcode; // @[BankBinder.scala:61:9]
assign auto_in_1_d_bits_param = auto_out_1_d_bits_param; // @[BankBinder.scala:61:9]
assign auto_in_1_d_bits_size = auto_out_1_d_bits_size; // @[BankBinder.scala:61:9]
assign auto_in_1_d_bits_source = auto_out_1_d_bits_source; // @[BankBinder.scala:61:9]
assign auto_in_1_d_bits_denied = auto_out_1_d_bits_denied; // @[BankBinder.scala:61:9]
assign auto_in_1_d_bits_data = auto_out_1_d_bits_data; // @[BankBinder.scala:61:9]
assign auto_in_1_d_bits_corrupt = auto_out_1_d_bits_corrupt; // @[BankBinder.scala:61:9]
assign auto_in_0_a_ready = auto_out_0_a_ready; // @[BankBinder.scala:61:9]
assign auto_in_0_d_valid = auto_out_0_d_valid; // @[BankBinder.scala:61:9]
assign auto_in_0_d_bits_opcode = auto_out_0_d_bits_opcode; // @[BankBinder.scala:61:9]
assign auto_in_0_d_bits_param = auto_out_0_d_bits_param; // @[BankBinder.scala:61:9]
assign auto_in_0_d_bits_size = auto_out_0_d_bits_size; // @[BankBinder.scala:61:9]
assign auto_in_0_d_bits_source = auto_out_0_d_bits_source; // @[BankBinder.scala:61:9]
assign auto_in_0_d_bits_denied = auto_out_0_d_bits_denied; // @[BankBinder.scala:61:9]
assign auto_in_0_d_bits_data = auto_out_0_d_bits_data; // @[BankBinder.scala:61:9]
assign auto_in_0_d_bits_corrupt = auto_out_0_d_bits_corrupt; // @[BankBinder.scala:61:9]
assign auto_out_3_a_valid = auto_in_3_a_valid; // @[BankBinder.scala:61:9]
assign auto_out_3_a_bits_opcode = auto_in_3_a_bits_opcode; // @[BankBinder.scala:61:9]
assign auto_out_3_a_bits_param = auto_in_3_a_bits_param; // @[BankBinder.scala:61:9]
assign auto_out_3_a_bits_size = auto_in_3_a_bits_size; // @[BankBinder.scala:61:9]
assign auto_out_3_a_bits_source = auto_in_3_a_bits_source; // @[BankBinder.scala:61:9]
assign auto_out_3_a_bits_address = auto_in_3_a_bits_address; // @[BankBinder.scala:61:9]
assign auto_out_3_a_bits_mask = auto_in_3_a_bits_mask; // @[BankBinder.scala:61:9]
assign auto_out_3_a_bits_data = auto_in_3_a_bits_data; // @[BankBinder.scala:61:9]
assign auto_out_3_a_bits_corrupt = auto_in_3_a_bits_corrupt; // @[BankBinder.scala:61:9]
assign auto_out_3_d_ready = auto_in_3_d_ready; // @[BankBinder.scala:61:9]
assign auto_out_2_a_valid = auto_in_2_a_valid; // @[BankBinder.scala:61:9]
assign auto_out_2_a_bits_opcode = auto_in_2_a_bits_opcode; // @[BankBinder.scala:61:9]
assign auto_out_2_a_bits_param = auto_in_2_a_bits_param; // @[BankBinder.scala:61:9]
assign auto_out_2_a_bits_size = auto_in_2_a_bits_size; // @[BankBinder.scala:61:9]
assign auto_out_2_a_bits_source = auto_in_2_a_bits_source; // @[BankBinder.scala:61:9]
assign auto_out_2_a_bits_address = auto_in_2_a_bits_address; // @[BankBinder.scala:61:9]
assign auto_out_2_a_bits_mask = auto_in_2_a_bits_mask; // @[BankBinder.scala:61:9]
assign auto_out_2_a_bits_data = auto_in_2_a_bits_data; // @[BankBinder.scala:61:9]
assign auto_out_2_a_bits_corrupt = auto_in_2_a_bits_corrupt; // @[BankBinder.scala:61:9]
assign auto_out_2_d_ready = auto_in_2_d_ready; // @[BankBinder.scala:61:9]
assign auto_out_1_a_valid = auto_in_1_a_valid; // @[BankBinder.scala:61:9]
assign auto_out_1_a_bits_opcode = auto_in_1_a_bits_opcode; // @[BankBinder.scala:61:9]
assign auto_out_1_a_bits_param = auto_in_1_a_bits_param; // @[BankBinder.scala:61:9]
assign auto_out_1_a_bits_size = auto_in_1_a_bits_size; // @[BankBinder.scala:61:9]
assign auto_out_1_a_bits_source = auto_in_1_a_bits_source; // @[BankBinder.scala:61:9]
assign auto_out_1_a_bits_address = auto_in_1_a_bits_address; // @[BankBinder.scala:61:9]
assign auto_out_1_a_bits_mask = auto_in_1_a_bits_mask; // @[BankBinder.scala:61:9]
assign auto_out_1_a_bits_data = auto_in_1_a_bits_data; // @[BankBinder.scala:61:9]
assign auto_out_1_a_bits_corrupt = auto_in_1_a_bits_corrupt; // @[BankBinder.scala:61:9]
assign auto_out_1_d_ready = auto_in_1_d_ready; // @[BankBinder.scala:61:9]
assign auto_out_0_a_valid = auto_in_0_a_valid; // @[BankBinder.scala:61:9]
assign auto_out_0_a_bits_opcode = auto_in_0_a_bits_opcode; // @[BankBinder.scala:61:9]
assign auto_out_0_a_bits_param = auto_in_0_a_bits_param; // @[BankBinder.scala:61:9]
assign auto_out_0_a_bits_size = auto_in_0_a_bits_size; // @[BankBinder.scala:61:9]
assign auto_out_0_a_bits_source = auto_in_0_a_bits_source; // @[BankBinder.scala:61:9]
assign auto_out_0_a_bits_address = auto_in_0_a_bits_address; // @[BankBinder.scala:61:9]
assign auto_out_0_a_bits_mask = auto_in_0_a_bits_mask; // @[BankBinder.scala:61:9]
assign auto_out_0_a_bits_data = auto_in_0_a_bits_data; // @[BankBinder.scala:61:9]
assign auto_out_0_a_bits_corrupt = auto_in_0_a_bits_corrupt; // @[BankBinder.scala:61:9]
assign auto_out_0_d_ready = auto_in_0_d_ready; // @[BankBinder.scala:61:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module DTLB_2 :
input clock : Clock
input reset : Reset
output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vaddr : UInt<40>, passthrough : UInt<1>, size : UInt<2>, cmd : UInt<5>, prv : UInt<2>, v : UInt<1>}}, resp : { miss : UInt<1>, paddr : UInt<32>, gpa : UInt<40>, gpa_is_pte : UInt<1>, pf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ma : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, cacheable : UInt<1>, must_alloc : UInt<1>, prefetchable : UInt<1>, size : UInt<2>, cmd : UInt<5>}, flip sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}, ptw : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { addr : UInt<27>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}}}, flip resp : { valid : UInt<1>, bits : { ae_ptw : UInt<1>, ae_final : UInt<1>, pf : UInt<1>, gf : UInt<1>, hr : UInt<1>, hw : UInt<1>, hx : UInt<1>, pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>, fragmented_superpage : UInt<1>, homogeneous : UInt<1>, gpa : { valid : UInt<1>, bits : UInt<39>}, gpa_is_pte : UInt<1>}}, flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[0], flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[0]}}, flip kill : UInt<1>}
node vpn = bits(io.req.bits.vaddr, 38, 12)
reg sectored_entries : { level : UInt<2>, tag_vpn : UInt<27>, tag_v : UInt<1>, data : UInt<42>[4], valid : UInt<1>[4]}[8][1], clock
reg superpage_entries : { level : UInt<2>, tag_vpn : UInt<27>, tag_v : UInt<1>, data : UInt<42>[1], valid : UInt<1>[1]}[4], clock
reg special_entry : { level : UInt<2>, tag_vpn : UInt<27>, tag_v : UInt<1>, data : UInt<42>[1], valid : UInt<1>[1]}, clock
regreset state : UInt<2>, clock, reset, UInt<2>(0h0)
reg r_refill_tag : UInt<27>, clock
reg r_superpage_repl_addr : UInt<2>, clock
reg r_sectored_repl_addr : UInt<3>, clock
reg r_sectored_hit : { valid : UInt<1>, bits : UInt<3>}, clock
reg r_superpage_hit : { valid : UInt<1>, bits : UInt<2>}, clock
reg r_vstage1_en : UInt<1>, clock
reg r_stage2_en : UInt<1>, clock
reg r_need_gpa : UInt<1>, clock
reg r_gpa_valid : UInt<1>, clock
reg r_gpa : UInt<39>, clock
reg r_gpa_vpn : UInt<27>, clock
reg r_gpa_is_pte : UInt<1>, clock
node priv_v = and(UInt<1>(0h0), io.req.bits.v)
node priv_s = bits(io.req.bits.prv, 0, 0)
node priv_uses_vm = leq(io.req.bits.prv, UInt<1>(0h1))
node satp = mux(priv_v, io.ptw.vsatp, io.ptw.ptbr)
node _stage1_en_T = bits(satp.mode, 3, 3)
node stage1_en = and(UInt<1>(0h1), _stage1_en_T)
node _vstage1_en_T = and(UInt<1>(0h0), priv_v)
node _vstage1_en_T_1 = bits(io.ptw.vsatp.mode, 3, 3)
node vstage1_en = and(_vstage1_en_T, _vstage1_en_T_1)
node _stage2_en_T = and(UInt<1>(0h0), priv_v)
node _stage2_en_T_1 = bits(io.ptw.hgatp.mode, 3, 3)
node stage2_en = and(_stage2_en_T, _stage2_en_T_1)
node _vm_enabled_T = or(stage1_en, stage2_en)
node _vm_enabled_T_1 = and(_vm_enabled_T, priv_uses_vm)
node _vm_enabled_T_2 = eq(io.req.bits.passthrough, UInt<1>(0h0))
node vm_enabled = and(_vm_enabled_T_1, _vm_enabled_T_2)
regreset v_entries_use_stage1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _vsatp_mode_mismatch_T = neq(vstage1_en, v_entries_use_stage1)
node _vsatp_mode_mismatch_T_1 = and(priv_v, _vsatp_mode_mismatch_T)
node _vsatp_mode_mismatch_T_2 = eq(io.req.bits.passthrough, UInt<1>(0h0))
node vsatp_mode_mismatch = and(_vsatp_mode_mismatch_T_1, _vsatp_mode_mismatch_T_2)
node refill_ppn = bits(io.ptw.resp.bits.pte.ppn, 19, 0)
node do_refill = and(UInt<1>(0h1), io.ptw.resp.valid)
node _invalidate_refill_T = eq(state, UInt<2>(0h1))
node _invalidate_refill_T_1 = eq(state, UInt<2>(0h3))
node _invalidate_refill_T_2 = or(_invalidate_refill_T, _invalidate_refill_T_1)
node invalidate_refill = or(_invalidate_refill_T_2, io.sfence.valid)
node _mpu_ppn_T = and(vm_enabled, UInt<1>(0h1))
wire _mpu_ppn_WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _mpu_ppn_WIRE_1 : UInt<42>
connect _mpu_ppn_WIRE_1, special_entry.data[0]
node _mpu_ppn_T_1 = bits(_mpu_ppn_WIRE_1, 0, 0)
connect _mpu_ppn_WIRE.fragmented_superpage, _mpu_ppn_T_1
node _mpu_ppn_T_2 = bits(_mpu_ppn_WIRE_1, 1, 1)
connect _mpu_ppn_WIRE.c, _mpu_ppn_T_2
node _mpu_ppn_T_3 = bits(_mpu_ppn_WIRE_1, 2, 2)
connect _mpu_ppn_WIRE.eff, _mpu_ppn_T_3
node _mpu_ppn_T_4 = bits(_mpu_ppn_WIRE_1, 3, 3)
connect _mpu_ppn_WIRE.paa, _mpu_ppn_T_4
node _mpu_ppn_T_5 = bits(_mpu_ppn_WIRE_1, 4, 4)
connect _mpu_ppn_WIRE.pal, _mpu_ppn_T_5
node _mpu_ppn_T_6 = bits(_mpu_ppn_WIRE_1, 5, 5)
connect _mpu_ppn_WIRE.ppp, _mpu_ppn_T_6
node _mpu_ppn_T_7 = bits(_mpu_ppn_WIRE_1, 6, 6)
connect _mpu_ppn_WIRE.pr, _mpu_ppn_T_7
node _mpu_ppn_T_8 = bits(_mpu_ppn_WIRE_1, 7, 7)
connect _mpu_ppn_WIRE.px, _mpu_ppn_T_8
node _mpu_ppn_T_9 = bits(_mpu_ppn_WIRE_1, 8, 8)
connect _mpu_ppn_WIRE.pw, _mpu_ppn_T_9
node _mpu_ppn_T_10 = bits(_mpu_ppn_WIRE_1, 9, 9)
connect _mpu_ppn_WIRE.hr, _mpu_ppn_T_10
node _mpu_ppn_T_11 = bits(_mpu_ppn_WIRE_1, 10, 10)
connect _mpu_ppn_WIRE.hx, _mpu_ppn_T_11
node _mpu_ppn_T_12 = bits(_mpu_ppn_WIRE_1, 11, 11)
connect _mpu_ppn_WIRE.hw, _mpu_ppn_T_12
node _mpu_ppn_T_13 = bits(_mpu_ppn_WIRE_1, 12, 12)
connect _mpu_ppn_WIRE.sr, _mpu_ppn_T_13
node _mpu_ppn_T_14 = bits(_mpu_ppn_WIRE_1, 13, 13)
connect _mpu_ppn_WIRE.sx, _mpu_ppn_T_14
node _mpu_ppn_T_15 = bits(_mpu_ppn_WIRE_1, 14, 14)
connect _mpu_ppn_WIRE.sw, _mpu_ppn_T_15
node _mpu_ppn_T_16 = bits(_mpu_ppn_WIRE_1, 15, 15)
connect _mpu_ppn_WIRE.gf, _mpu_ppn_T_16
node _mpu_ppn_T_17 = bits(_mpu_ppn_WIRE_1, 16, 16)
connect _mpu_ppn_WIRE.pf, _mpu_ppn_T_17
node _mpu_ppn_T_18 = bits(_mpu_ppn_WIRE_1, 17, 17)
connect _mpu_ppn_WIRE.ae_stage2, _mpu_ppn_T_18
node _mpu_ppn_T_19 = bits(_mpu_ppn_WIRE_1, 18, 18)
connect _mpu_ppn_WIRE.ae_final, _mpu_ppn_T_19
node _mpu_ppn_T_20 = bits(_mpu_ppn_WIRE_1, 19, 19)
connect _mpu_ppn_WIRE.ae_ptw, _mpu_ppn_T_20
node _mpu_ppn_T_21 = bits(_mpu_ppn_WIRE_1, 20, 20)
connect _mpu_ppn_WIRE.g, _mpu_ppn_T_21
node _mpu_ppn_T_22 = bits(_mpu_ppn_WIRE_1, 21, 21)
connect _mpu_ppn_WIRE.u, _mpu_ppn_T_22
node _mpu_ppn_T_23 = bits(_mpu_ppn_WIRE_1, 41, 22)
connect _mpu_ppn_WIRE.ppn, _mpu_ppn_T_23
inst mpu_ppn_barrier of OptimizationBarrier_TLBEntryData_42
connect mpu_ppn_barrier.clock, clock
connect mpu_ppn_barrier.reset, reset
connect mpu_ppn_barrier.io.x.fragmented_superpage, _mpu_ppn_WIRE.fragmented_superpage
connect mpu_ppn_barrier.io.x.c, _mpu_ppn_WIRE.c
connect mpu_ppn_barrier.io.x.eff, _mpu_ppn_WIRE.eff
connect mpu_ppn_barrier.io.x.paa, _mpu_ppn_WIRE.paa
connect mpu_ppn_barrier.io.x.pal, _mpu_ppn_WIRE.pal
connect mpu_ppn_barrier.io.x.ppp, _mpu_ppn_WIRE.ppp
connect mpu_ppn_barrier.io.x.pr, _mpu_ppn_WIRE.pr
connect mpu_ppn_barrier.io.x.px, _mpu_ppn_WIRE.px
connect mpu_ppn_barrier.io.x.pw, _mpu_ppn_WIRE.pw
connect mpu_ppn_barrier.io.x.hr, _mpu_ppn_WIRE.hr
connect mpu_ppn_barrier.io.x.hx, _mpu_ppn_WIRE.hx
connect mpu_ppn_barrier.io.x.hw, _mpu_ppn_WIRE.hw
connect mpu_ppn_barrier.io.x.sr, _mpu_ppn_WIRE.sr
connect mpu_ppn_barrier.io.x.sx, _mpu_ppn_WIRE.sx
connect mpu_ppn_barrier.io.x.sw, _mpu_ppn_WIRE.sw
connect mpu_ppn_barrier.io.x.gf, _mpu_ppn_WIRE.gf
connect mpu_ppn_barrier.io.x.pf, _mpu_ppn_WIRE.pf
connect mpu_ppn_barrier.io.x.ae_stage2, _mpu_ppn_WIRE.ae_stage2
connect mpu_ppn_barrier.io.x.ae_final, _mpu_ppn_WIRE.ae_final
connect mpu_ppn_barrier.io.x.ae_ptw, _mpu_ppn_WIRE.ae_ptw
connect mpu_ppn_barrier.io.x.g, _mpu_ppn_WIRE.g
connect mpu_ppn_barrier.io.x.u, _mpu_ppn_WIRE.u
connect mpu_ppn_barrier.io.x.ppn, _mpu_ppn_WIRE.ppn
node mpu_ppn_res = shr(mpu_ppn_barrier.io.y.ppn, 18)
node _mpu_ppn_ignore_T = lt(special_entry.level, UInt<1>(0h1))
node mpu_ppn_ignore = or(_mpu_ppn_ignore_T, UInt<1>(0h0))
node _mpu_ppn_T_24 = mux(mpu_ppn_ignore, vpn, UInt<1>(0h0))
node _mpu_ppn_T_25 = or(_mpu_ppn_T_24, mpu_ppn_barrier.io.y.ppn)
node _mpu_ppn_T_26 = bits(_mpu_ppn_T_25, 17, 9)
node _mpu_ppn_T_27 = cat(mpu_ppn_res, _mpu_ppn_T_26)
node _mpu_ppn_ignore_T_1 = lt(special_entry.level, UInt<2>(0h2))
node mpu_ppn_ignore_1 = or(_mpu_ppn_ignore_T_1, UInt<1>(0h0))
node _mpu_ppn_T_28 = mux(mpu_ppn_ignore_1, vpn, UInt<1>(0h0))
node _mpu_ppn_T_29 = or(_mpu_ppn_T_28, mpu_ppn_barrier.io.y.ppn)
node _mpu_ppn_T_30 = bits(_mpu_ppn_T_29, 8, 0)
node _mpu_ppn_T_31 = cat(_mpu_ppn_T_27, _mpu_ppn_T_30)
node _mpu_ppn_T_32 = shr(io.req.bits.vaddr, 12)
node _mpu_ppn_T_33 = mux(_mpu_ppn_T, _mpu_ppn_T_31, _mpu_ppn_T_32)
node mpu_ppn = mux(do_refill, refill_ppn, _mpu_ppn_T_33)
node _mpu_physaddr_T = bits(io.req.bits.vaddr, 11, 0)
node mpu_physaddr = cat(mpu_ppn, _mpu_physaddr_T)
node _mpu_priv_T = or(do_refill, io.req.bits.passthrough)
node _mpu_priv_T_1 = and(UInt<1>(0h1), _mpu_priv_T)
node _mpu_priv_T_2 = cat(io.ptw.status.debug, io.req.bits.prv)
node mpu_priv = mux(_mpu_priv_T_1, UInt<1>(0h1), _mpu_priv_T_2)
inst pmp of PMPChecker_s3_2
connect pmp.clock, clock
connect pmp.reset, reset
connect pmp.io.addr, mpu_physaddr
connect pmp.io.size, io.req.bits.size
connect pmp.io.prv, mpu_priv
inst pma of PMAChecker_3
connect pma.clock, clock
connect pma.reset, reset
connect pma.io.paddr, mpu_physaddr
node cacheable = and(pma.io.resp.cacheable, UInt<1>(0h1))
node _homogeneous_T = xor(mpu_physaddr, UInt<1>(0h0))
node _homogeneous_T_1 = cvt(_homogeneous_T)
node _homogeneous_T_2 = and(_homogeneous_T_1, asSInt(UInt<14>(0h2000)))
node _homogeneous_T_3 = asSInt(_homogeneous_T_2)
node _homogeneous_T_4 = eq(_homogeneous_T_3, asSInt(UInt<1>(0h0)))
node _homogeneous_T_5 = xor(mpu_physaddr, UInt<14>(0h3000))
node _homogeneous_T_6 = cvt(_homogeneous_T_5)
node _homogeneous_T_7 = and(_homogeneous_T_6, asSInt(UInt<13>(0h1000)))
node _homogeneous_T_8 = asSInt(_homogeneous_T_7)
node _homogeneous_T_9 = eq(_homogeneous_T_8, asSInt(UInt<1>(0h0)))
node _homogeneous_T_10 = xor(mpu_physaddr, UInt<17>(0h10000))
node _homogeneous_T_11 = cvt(_homogeneous_T_10)
node _homogeneous_T_12 = and(_homogeneous_T_11, asSInt(UInt<17>(0h10000)))
node _homogeneous_T_13 = asSInt(_homogeneous_T_12)
node _homogeneous_T_14 = eq(_homogeneous_T_13, asSInt(UInt<1>(0h0)))
node _homogeneous_T_15 = xor(mpu_physaddr, UInt<18>(0h20000))
node _homogeneous_T_16 = cvt(_homogeneous_T_15)
node _homogeneous_T_17 = and(_homogeneous_T_16, asSInt(UInt<15>(0h4000)))
node _homogeneous_T_18 = asSInt(_homogeneous_T_17)
node _homogeneous_T_19 = eq(_homogeneous_T_18, asSInt(UInt<1>(0h0)))
node _homogeneous_T_20 = xor(mpu_physaddr, UInt<18>(0h24000))
node _homogeneous_T_21 = cvt(_homogeneous_T_20)
node _homogeneous_T_22 = and(_homogeneous_T_21, asSInt(UInt<13>(0h1000)))
node _homogeneous_T_23 = asSInt(_homogeneous_T_22)
node _homogeneous_T_24 = eq(_homogeneous_T_23, asSInt(UInt<1>(0h0)))
node _homogeneous_T_25 = xor(mpu_physaddr, UInt<21>(0h100000))
node _homogeneous_T_26 = cvt(_homogeneous_T_25)
node _homogeneous_T_27 = and(_homogeneous_T_26, asSInt(UInt<18>(0h2f000)))
node _homogeneous_T_28 = asSInt(_homogeneous_T_27)
node _homogeneous_T_29 = eq(_homogeneous_T_28, asSInt(UInt<1>(0h0)))
node _homogeneous_T_30 = xor(mpu_physaddr, UInt<26>(0h2000000))
node _homogeneous_T_31 = cvt(_homogeneous_T_30)
node _homogeneous_T_32 = and(_homogeneous_T_31, asSInt(UInt<17>(0h10000)))
node _homogeneous_T_33 = asSInt(_homogeneous_T_32)
node _homogeneous_T_34 = eq(_homogeneous_T_33, asSInt(UInt<1>(0h0)))
node _homogeneous_T_35 = xor(mpu_physaddr, UInt<26>(0h2010000))
node _homogeneous_T_36 = cvt(_homogeneous_T_35)
node _homogeneous_T_37 = and(_homogeneous_T_36, asSInt(UInt<13>(0h1000)))
node _homogeneous_T_38 = asSInt(_homogeneous_T_37)
node _homogeneous_T_39 = eq(_homogeneous_T_38, asSInt(UInt<1>(0h0)))
node _homogeneous_T_40 = xor(mpu_physaddr, UInt<28>(0h8000000))
node _homogeneous_T_41 = cvt(_homogeneous_T_40)
node _homogeneous_T_42 = and(_homogeneous_T_41, asSInt(UInt<17>(0h10000)))
node _homogeneous_T_43 = asSInt(_homogeneous_T_42)
node _homogeneous_T_44 = eq(_homogeneous_T_43, asSInt(UInt<1>(0h0)))
node _homogeneous_T_45 = xor(mpu_physaddr, UInt<28>(0hc000000))
node _homogeneous_T_46 = cvt(_homogeneous_T_45)
node _homogeneous_T_47 = and(_homogeneous_T_46, asSInt(UInt<27>(0h4000000)))
node _homogeneous_T_48 = asSInt(_homogeneous_T_47)
node _homogeneous_T_49 = eq(_homogeneous_T_48, asSInt(UInt<1>(0h0)))
node _homogeneous_T_50 = xor(mpu_physaddr, UInt<29>(0h10020000))
node _homogeneous_T_51 = cvt(_homogeneous_T_50)
node _homogeneous_T_52 = and(_homogeneous_T_51, asSInt(UInt<13>(0h1000)))
node _homogeneous_T_53 = asSInt(_homogeneous_T_52)
node _homogeneous_T_54 = eq(_homogeneous_T_53, asSInt(UInt<1>(0h0)))
node _homogeneous_T_55 = xor(mpu_physaddr, UInt<32>(0h80000000))
node _homogeneous_T_56 = cvt(_homogeneous_T_55)
node _homogeneous_T_57 = and(_homogeneous_T_56, asSInt(UInt<29>(0h10000000)))
node _homogeneous_T_58 = asSInt(_homogeneous_T_57)
node _homogeneous_T_59 = eq(_homogeneous_T_58, asSInt(UInt<1>(0h0)))
node _homogeneous_T_60 = or(UInt<1>(0h0), _homogeneous_T_4)
node _homogeneous_T_61 = or(_homogeneous_T_60, _homogeneous_T_9)
node _homogeneous_T_62 = or(_homogeneous_T_61, _homogeneous_T_14)
node _homogeneous_T_63 = or(_homogeneous_T_62, _homogeneous_T_19)
node _homogeneous_T_64 = or(_homogeneous_T_63, _homogeneous_T_24)
node _homogeneous_T_65 = or(_homogeneous_T_64, _homogeneous_T_29)
node _homogeneous_T_66 = or(_homogeneous_T_65, _homogeneous_T_34)
node _homogeneous_T_67 = or(_homogeneous_T_66, _homogeneous_T_39)
node _homogeneous_T_68 = or(_homogeneous_T_67, _homogeneous_T_44)
node _homogeneous_T_69 = or(_homogeneous_T_68, _homogeneous_T_49)
node _homogeneous_T_70 = or(_homogeneous_T_69, _homogeneous_T_54)
node homogeneous = or(_homogeneous_T_70, _homogeneous_T_59)
node _homogeneous_T_71 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _homogeneous_T_72 = xor(mpu_physaddr, UInt<17>(0h10000))
node _homogeneous_T_73 = cvt(_homogeneous_T_72)
node _homogeneous_T_74 = and(_homogeneous_T_73, asSInt(UInt<33>(0h8a130000)))
node _homogeneous_T_75 = asSInt(_homogeneous_T_74)
node _homogeneous_T_76 = eq(_homogeneous_T_75, asSInt(UInt<1>(0h0)))
node _homogeneous_T_77 = or(UInt<1>(0h0), _homogeneous_T_76)
node _homogeneous_T_78 = eq(_homogeneous_T_77, UInt<1>(0h0))
node _homogeneous_T_79 = xor(mpu_physaddr, UInt<1>(0h0))
node _homogeneous_T_80 = cvt(_homogeneous_T_79)
node _homogeneous_T_81 = and(_homogeneous_T_80, asSInt(UInt<33>(0hffff3000)))
node _homogeneous_T_82 = asSInt(_homogeneous_T_81)
node _homogeneous_T_83 = eq(_homogeneous_T_82, asSInt(UInt<1>(0h0)))
node _homogeneous_T_84 = xor(mpu_physaddr, UInt<14>(0h3000))
node _homogeneous_T_85 = cvt(_homogeneous_T_84)
node _homogeneous_T_86 = and(_homogeneous_T_85, asSInt(UInt<33>(0hffff3000)))
node _homogeneous_T_87 = asSInt(_homogeneous_T_86)
node _homogeneous_T_88 = eq(_homogeneous_T_87, asSInt(UInt<1>(0h0)))
node _homogeneous_T_89 = xor(mpu_physaddr, UInt<17>(0h10000))
node _homogeneous_T_90 = cvt(_homogeneous_T_89)
node _homogeneous_T_91 = and(_homogeneous_T_90, asSInt(UInt<33>(0hffff0000)))
node _homogeneous_T_92 = asSInt(_homogeneous_T_91)
node _homogeneous_T_93 = eq(_homogeneous_T_92, asSInt(UInt<1>(0h0)))
node _homogeneous_T_94 = xor(mpu_physaddr, UInt<28>(0h8000000))
node _homogeneous_T_95 = cvt(_homogeneous_T_94)
node _homogeneous_T_96 = and(_homogeneous_T_95, asSInt(UInt<33>(0hffff0000)))
node _homogeneous_T_97 = asSInt(_homogeneous_T_96)
node _homogeneous_T_98 = eq(_homogeneous_T_97, asSInt(UInt<1>(0h0)))
node _homogeneous_T_99 = xor(mpu_physaddr, UInt<32>(0h80000000))
node _homogeneous_T_100 = cvt(_homogeneous_T_99)
node _homogeneous_T_101 = and(_homogeneous_T_100, asSInt(UInt<33>(0hf0000000)))
node _homogeneous_T_102 = asSInt(_homogeneous_T_101)
node _homogeneous_T_103 = eq(_homogeneous_T_102, asSInt(UInt<1>(0h0)))
node _homogeneous_T_104 = or(UInt<1>(0h0), _homogeneous_T_83)
node _homogeneous_T_105 = or(_homogeneous_T_104, _homogeneous_T_88)
node _homogeneous_T_106 = or(_homogeneous_T_105, _homogeneous_T_93)
node _homogeneous_T_107 = or(_homogeneous_T_106, _homogeneous_T_98)
node _homogeneous_T_108 = or(_homogeneous_T_107, _homogeneous_T_103)
node _homogeneous_T_109 = xor(mpu_physaddr, UInt<28>(0h8000000))
node _homogeneous_T_110 = cvt(_homogeneous_T_109)
node _homogeneous_T_111 = and(_homogeneous_T_110, asSInt(UInt<33>(0h8e020000)))
node _homogeneous_T_112 = asSInt(_homogeneous_T_111)
node _homogeneous_T_113 = eq(_homogeneous_T_112, asSInt(UInt<1>(0h0)))
node _homogeneous_T_114 = xor(mpu_physaddr, UInt<32>(0h80000000))
node _homogeneous_T_115 = cvt(_homogeneous_T_114)
node _homogeneous_T_116 = and(_homogeneous_T_115, asSInt(UInt<33>(0h80000000)))
node _homogeneous_T_117 = asSInt(_homogeneous_T_116)
node _homogeneous_T_118 = eq(_homogeneous_T_117, asSInt(UInt<1>(0h0)))
node _homogeneous_T_119 = or(UInt<1>(0h0), _homogeneous_T_113)
node _homogeneous_T_120 = or(_homogeneous_T_119, _homogeneous_T_118)
node _homogeneous_T_121 = xor(mpu_physaddr, UInt<17>(0h10000))
node _homogeneous_T_122 = cvt(_homogeneous_T_121)
node _homogeneous_T_123 = and(_homogeneous_T_122, asSInt(UInt<33>(0h8a130000)))
node _homogeneous_T_124 = asSInt(_homogeneous_T_123)
node _homogeneous_T_125 = eq(_homogeneous_T_124, asSInt(UInt<1>(0h0)))
node _homogeneous_T_126 = or(UInt<1>(0h0), _homogeneous_T_125)
node _homogeneous_T_127 = eq(_homogeneous_T_126, UInt<1>(0h0))
node _homogeneous_T_128 = xor(mpu_physaddr, UInt<17>(0h10000))
node _homogeneous_T_129 = cvt(_homogeneous_T_128)
node _homogeneous_T_130 = and(_homogeneous_T_129, asSInt(UInt<33>(0h8a130000)))
node _homogeneous_T_131 = asSInt(_homogeneous_T_130)
node _homogeneous_T_132 = eq(_homogeneous_T_131, asSInt(UInt<1>(0h0)))
node _homogeneous_T_133 = or(UInt<1>(0h0), _homogeneous_T_132)
node _homogeneous_T_134 = eq(_homogeneous_T_133, UInt<1>(0h0))
node _deny_access_to_debug_T = leq(mpu_priv, UInt<2>(0h3))
node _deny_access_to_debug_T_1 = xor(mpu_physaddr, UInt<1>(0h0))
node _deny_access_to_debug_T_2 = cvt(_deny_access_to_debug_T_1)
node _deny_access_to_debug_T_3 = and(_deny_access_to_debug_T_2, asSInt(UInt<13>(0h1000)))
node _deny_access_to_debug_T_4 = asSInt(_deny_access_to_debug_T_3)
node _deny_access_to_debug_T_5 = eq(_deny_access_to_debug_T_4, asSInt(UInt<1>(0h0)))
node deny_access_to_debug = and(_deny_access_to_debug_T, _deny_access_to_debug_T_5)
node _prot_r_T = eq(deny_access_to_debug, UInt<1>(0h0))
node _prot_r_T_1 = and(pma.io.resp.r, _prot_r_T)
node prot_r = and(_prot_r_T_1, pmp.io.r)
node _prot_w_T = eq(deny_access_to_debug, UInt<1>(0h0))
node _prot_w_T_1 = and(pma.io.resp.w, _prot_w_T)
node prot_w = and(_prot_w_T_1, pmp.io.w)
node _prot_x_T = eq(deny_access_to_debug, UInt<1>(0h0))
node _prot_x_T_1 = and(pma.io.resp.x, _prot_x_T)
node prot_x = and(_prot_x_T_1, pmp.io.x)
node _sector_hits_T = or(sectored_entries[0][0].valid[0], sectored_entries[0][0].valid[1])
node _sector_hits_T_1 = or(_sector_hits_T, sectored_entries[0][0].valid[2])
node _sector_hits_T_2 = or(_sector_hits_T_1, sectored_entries[0][0].valid[3])
node _sector_hits_T_3 = xor(sectored_entries[0][0].tag_vpn, vpn)
node _sector_hits_T_4 = shr(_sector_hits_T_3, 2)
node _sector_hits_T_5 = eq(_sector_hits_T_4, UInt<1>(0h0))
node _sector_hits_T_6 = eq(sectored_entries[0][0].tag_v, priv_v)
node _sector_hits_T_7 = and(_sector_hits_T_5, _sector_hits_T_6)
node sector_hits_0 = and(_sector_hits_T_2, _sector_hits_T_7)
node _sector_hits_T_8 = or(sectored_entries[0][1].valid[0], sectored_entries[0][1].valid[1])
node _sector_hits_T_9 = or(_sector_hits_T_8, sectored_entries[0][1].valid[2])
node _sector_hits_T_10 = or(_sector_hits_T_9, sectored_entries[0][1].valid[3])
node _sector_hits_T_11 = xor(sectored_entries[0][1].tag_vpn, vpn)
node _sector_hits_T_12 = shr(_sector_hits_T_11, 2)
node _sector_hits_T_13 = eq(_sector_hits_T_12, UInt<1>(0h0))
node _sector_hits_T_14 = eq(sectored_entries[0][1].tag_v, priv_v)
node _sector_hits_T_15 = and(_sector_hits_T_13, _sector_hits_T_14)
node sector_hits_1 = and(_sector_hits_T_10, _sector_hits_T_15)
node _sector_hits_T_16 = or(sectored_entries[0][2].valid[0], sectored_entries[0][2].valid[1])
node _sector_hits_T_17 = or(_sector_hits_T_16, sectored_entries[0][2].valid[2])
node _sector_hits_T_18 = or(_sector_hits_T_17, sectored_entries[0][2].valid[3])
node _sector_hits_T_19 = xor(sectored_entries[0][2].tag_vpn, vpn)
node _sector_hits_T_20 = shr(_sector_hits_T_19, 2)
node _sector_hits_T_21 = eq(_sector_hits_T_20, UInt<1>(0h0))
node _sector_hits_T_22 = eq(sectored_entries[0][2].tag_v, priv_v)
node _sector_hits_T_23 = and(_sector_hits_T_21, _sector_hits_T_22)
node sector_hits_2 = and(_sector_hits_T_18, _sector_hits_T_23)
node _sector_hits_T_24 = or(sectored_entries[0][3].valid[0], sectored_entries[0][3].valid[1])
node _sector_hits_T_25 = or(_sector_hits_T_24, sectored_entries[0][3].valid[2])
node _sector_hits_T_26 = or(_sector_hits_T_25, sectored_entries[0][3].valid[3])
node _sector_hits_T_27 = xor(sectored_entries[0][3].tag_vpn, vpn)
node _sector_hits_T_28 = shr(_sector_hits_T_27, 2)
node _sector_hits_T_29 = eq(_sector_hits_T_28, UInt<1>(0h0))
node _sector_hits_T_30 = eq(sectored_entries[0][3].tag_v, priv_v)
node _sector_hits_T_31 = and(_sector_hits_T_29, _sector_hits_T_30)
node sector_hits_3 = and(_sector_hits_T_26, _sector_hits_T_31)
node _sector_hits_T_32 = or(sectored_entries[0][4].valid[0], sectored_entries[0][4].valid[1])
node _sector_hits_T_33 = or(_sector_hits_T_32, sectored_entries[0][4].valid[2])
node _sector_hits_T_34 = or(_sector_hits_T_33, sectored_entries[0][4].valid[3])
node _sector_hits_T_35 = xor(sectored_entries[0][4].tag_vpn, vpn)
node _sector_hits_T_36 = shr(_sector_hits_T_35, 2)
node _sector_hits_T_37 = eq(_sector_hits_T_36, UInt<1>(0h0))
node _sector_hits_T_38 = eq(sectored_entries[0][4].tag_v, priv_v)
node _sector_hits_T_39 = and(_sector_hits_T_37, _sector_hits_T_38)
node sector_hits_4 = and(_sector_hits_T_34, _sector_hits_T_39)
node _sector_hits_T_40 = or(sectored_entries[0][5].valid[0], sectored_entries[0][5].valid[1])
node _sector_hits_T_41 = or(_sector_hits_T_40, sectored_entries[0][5].valid[2])
node _sector_hits_T_42 = or(_sector_hits_T_41, sectored_entries[0][5].valid[3])
node _sector_hits_T_43 = xor(sectored_entries[0][5].tag_vpn, vpn)
node _sector_hits_T_44 = shr(_sector_hits_T_43, 2)
node _sector_hits_T_45 = eq(_sector_hits_T_44, UInt<1>(0h0))
node _sector_hits_T_46 = eq(sectored_entries[0][5].tag_v, priv_v)
node _sector_hits_T_47 = and(_sector_hits_T_45, _sector_hits_T_46)
node sector_hits_5 = and(_sector_hits_T_42, _sector_hits_T_47)
node _sector_hits_T_48 = or(sectored_entries[0][6].valid[0], sectored_entries[0][6].valid[1])
node _sector_hits_T_49 = or(_sector_hits_T_48, sectored_entries[0][6].valid[2])
node _sector_hits_T_50 = or(_sector_hits_T_49, sectored_entries[0][6].valid[3])
node _sector_hits_T_51 = xor(sectored_entries[0][6].tag_vpn, vpn)
node _sector_hits_T_52 = shr(_sector_hits_T_51, 2)
node _sector_hits_T_53 = eq(_sector_hits_T_52, UInt<1>(0h0))
node _sector_hits_T_54 = eq(sectored_entries[0][6].tag_v, priv_v)
node _sector_hits_T_55 = and(_sector_hits_T_53, _sector_hits_T_54)
node sector_hits_6 = and(_sector_hits_T_50, _sector_hits_T_55)
node _sector_hits_T_56 = or(sectored_entries[0][7].valid[0], sectored_entries[0][7].valid[1])
node _sector_hits_T_57 = or(_sector_hits_T_56, sectored_entries[0][7].valid[2])
node _sector_hits_T_58 = or(_sector_hits_T_57, sectored_entries[0][7].valid[3])
node _sector_hits_T_59 = xor(sectored_entries[0][7].tag_vpn, vpn)
node _sector_hits_T_60 = shr(_sector_hits_T_59, 2)
node _sector_hits_T_61 = eq(_sector_hits_T_60, UInt<1>(0h0))
node _sector_hits_T_62 = eq(sectored_entries[0][7].tag_v, priv_v)
node _sector_hits_T_63 = and(_sector_hits_T_61, _sector_hits_T_62)
node sector_hits_7 = and(_sector_hits_T_58, _sector_hits_T_63)
node _superpage_hits_tagMatch_T = eq(superpage_entries[0].tag_v, priv_v)
node superpage_hits_tagMatch = and(superpage_entries[0].valid[0], _superpage_hits_tagMatch_T)
node _superpage_hits_ignore_T = lt(superpage_entries[0].level, UInt<1>(0h0))
node superpage_hits_ignore = or(_superpage_hits_ignore_T, UInt<1>(0h0))
node _superpage_hits_T = xor(superpage_entries[0].tag_vpn, vpn)
node _superpage_hits_T_1 = bits(_superpage_hits_T, 26, 18)
node _superpage_hits_T_2 = eq(_superpage_hits_T_1, UInt<1>(0h0))
node _superpage_hits_T_3 = or(superpage_hits_ignore, _superpage_hits_T_2)
node _superpage_hits_T_4 = and(superpage_hits_tagMatch, _superpage_hits_T_3)
node _superpage_hits_ignore_T_1 = lt(superpage_entries[0].level, UInt<1>(0h1))
node superpage_hits_ignore_1 = or(_superpage_hits_ignore_T_1, UInt<1>(0h0))
node _superpage_hits_T_5 = xor(superpage_entries[0].tag_vpn, vpn)
node _superpage_hits_T_6 = bits(_superpage_hits_T_5, 17, 9)
node _superpage_hits_T_7 = eq(_superpage_hits_T_6, UInt<1>(0h0))
node _superpage_hits_T_8 = or(superpage_hits_ignore_1, _superpage_hits_T_7)
node _superpage_hits_T_9 = and(_superpage_hits_T_4, _superpage_hits_T_8)
node _superpage_hits_ignore_T_2 = lt(superpage_entries[0].level, UInt<2>(0h2))
node superpage_hits_ignore_2 = or(_superpage_hits_ignore_T_2, UInt<1>(0h1))
node _superpage_hits_T_10 = xor(superpage_entries[0].tag_vpn, vpn)
node _superpage_hits_T_11 = bits(_superpage_hits_T_10, 8, 0)
node _superpage_hits_T_12 = eq(_superpage_hits_T_11, UInt<1>(0h0))
node _superpage_hits_T_13 = or(superpage_hits_ignore_2, _superpage_hits_T_12)
node superpage_hits_0 = and(_superpage_hits_T_9, _superpage_hits_T_13)
node _superpage_hits_tagMatch_T_1 = eq(superpage_entries[1].tag_v, priv_v)
node superpage_hits_tagMatch_1 = and(superpage_entries[1].valid[0], _superpage_hits_tagMatch_T_1)
node _superpage_hits_ignore_T_3 = lt(superpage_entries[1].level, UInt<1>(0h0))
node superpage_hits_ignore_3 = or(_superpage_hits_ignore_T_3, UInt<1>(0h0))
node _superpage_hits_T_14 = xor(superpage_entries[1].tag_vpn, vpn)
node _superpage_hits_T_15 = bits(_superpage_hits_T_14, 26, 18)
node _superpage_hits_T_16 = eq(_superpage_hits_T_15, UInt<1>(0h0))
node _superpage_hits_T_17 = or(superpage_hits_ignore_3, _superpage_hits_T_16)
node _superpage_hits_T_18 = and(superpage_hits_tagMatch_1, _superpage_hits_T_17)
node _superpage_hits_ignore_T_4 = lt(superpage_entries[1].level, UInt<1>(0h1))
node superpage_hits_ignore_4 = or(_superpage_hits_ignore_T_4, UInt<1>(0h0))
node _superpage_hits_T_19 = xor(superpage_entries[1].tag_vpn, vpn)
node _superpage_hits_T_20 = bits(_superpage_hits_T_19, 17, 9)
node _superpage_hits_T_21 = eq(_superpage_hits_T_20, UInt<1>(0h0))
node _superpage_hits_T_22 = or(superpage_hits_ignore_4, _superpage_hits_T_21)
node _superpage_hits_T_23 = and(_superpage_hits_T_18, _superpage_hits_T_22)
node _superpage_hits_ignore_T_5 = lt(superpage_entries[1].level, UInt<2>(0h2))
node superpage_hits_ignore_5 = or(_superpage_hits_ignore_T_5, UInt<1>(0h1))
node _superpage_hits_T_24 = xor(superpage_entries[1].tag_vpn, vpn)
node _superpage_hits_T_25 = bits(_superpage_hits_T_24, 8, 0)
node _superpage_hits_T_26 = eq(_superpage_hits_T_25, UInt<1>(0h0))
node _superpage_hits_T_27 = or(superpage_hits_ignore_5, _superpage_hits_T_26)
node superpage_hits_1 = and(_superpage_hits_T_23, _superpage_hits_T_27)
node _superpage_hits_tagMatch_T_2 = eq(superpage_entries[2].tag_v, priv_v)
node superpage_hits_tagMatch_2 = and(superpage_entries[2].valid[0], _superpage_hits_tagMatch_T_2)
node _superpage_hits_ignore_T_6 = lt(superpage_entries[2].level, UInt<1>(0h0))
node superpage_hits_ignore_6 = or(_superpage_hits_ignore_T_6, UInt<1>(0h0))
node _superpage_hits_T_28 = xor(superpage_entries[2].tag_vpn, vpn)
node _superpage_hits_T_29 = bits(_superpage_hits_T_28, 26, 18)
node _superpage_hits_T_30 = eq(_superpage_hits_T_29, UInt<1>(0h0))
node _superpage_hits_T_31 = or(superpage_hits_ignore_6, _superpage_hits_T_30)
node _superpage_hits_T_32 = and(superpage_hits_tagMatch_2, _superpage_hits_T_31)
node _superpage_hits_ignore_T_7 = lt(superpage_entries[2].level, UInt<1>(0h1))
node superpage_hits_ignore_7 = or(_superpage_hits_ignore_T_7, UInt<1>(0h0))
node _superpage_hits_T_33 = xor(superpage_entries[2].tag_vpn, vpn)
node _superpage_hits_T_34 = bits(_superpage_hits_T_33, 17, 9)
node _superpage_hits_T_35 = eq(_superpage_hits_T_34, UInt<1>(0h0))
node _superpage_hits_T_36 = or(superpage_hits_ignore_7, _superpage_hits_T_35)
node _superpage_hits_T_37 = and(_superpage_hits_T_32, _superpage_hits_T_36)
node _superpage_hits_ignore_T_8 = lt(superpage_entries[2].level, UInt<2>(0h2))
node superpage_hits_ignore_8 = or(_superpage_hits_ignore_T_8, UInt<1>(0h1))
node _superpage_hits_T_38 = xor(superpage_entries[2].tag_vpn, vpn)
node _superpage_hits_T_39 = bits(_superpage_hits_T_38, 8, 0)
node _superpage_hits_T_40 = eq(_superpage_hits_T_39, UInt<1>(0h0))
node _superpage_hits_T_41 = or(superpage_hits_ignore_8, _superpage_hits_T_40)
node superpage_hits_2 = and(_superpage_hits_T_37, _superpage_hits_T_41)
node _superpage_hits_tagMatch_T_3 = eq(superpage_entries[3].tag_v, priv_v)
node superpage_hits_tagMatch_3 = and(superpage_entries[3].valid[0], _superpage_hits_tagMatch_T_3)
node _superpage_hits_ignore_T_9 = lt(superpage_entries[3].level, UInt<1>(0h0))
node superpage_hits_ignore_9 = or(_superpage_hits_ignore_T_9, UInt<1>(0h0))
node _superpage_hits_T_42 = xor(superpage_entries[3].tag_vpn, vpn)
node _superpage_hits_T_43 = bits(_superpage_hits_T_42, 26, 18)
node _superpage_hits_T_44 = eq(_superpage_hits_T_43, UInt<1>(0h0))
node _superpage_hits_T_45 = or(superpage_hits_ignore_9, _superpage_hits_T_44)
node _superpage_hits_T_46 = and(superpage_hits_tagMatch_3, _superpage_hits_T_45)
node _superpage_hits_ignore_T_10 = lt(superpage_entries[3].level, UInt<1>(0h1))
node superpage_hits_ignore_10 = or(_superpage_hits_ignore_T_10, UInt<1>(0h0))
node _superpage_hits_T_47 = xor(superpage_entries[3].tag_vpn, vpn)
node _superpage_hits_T_48 = bits(_superpage_hits_T_47, 17, 9)
node _superpage_hits_T_49 = eq(_superpage_hits_T_48, UInt<1>(0h0))
node _superpage_hits_T_50 = or(superpage_hits_ignore_10, _superpage_hits_T_49)
node _superpage_hits_T_51 = and(_superpage_hits_T_46, _superpage_hits_T_50)
node _superpage_hits_ignore_T_11 = lt(superpage_entries[3].level, UInt<2>(0h2))
node superpage_hits_ignore_11 = or(_superpage_hits_ignore_T_11, UInt<1>(0h1))
node _superpage_hits_T_52 = xor(superpage_entries[3].tag_vpn, vpn)
node _superpage_hits_T_53 = bits(_superpage_hits_T_52, 8, 0)
node _superpage_hits_T_54 = eq(_superpage_hits_T_53, UInt<1>(0h0))
node _superpage_hits_T_55 = or(superpage_hits_ignore_11, _superpage_hits_T_54)
node superpage_hits_3 = and(_superpage_hits_T_51, _superpage_hits_T_55)
node hitsVec_idx = bits(vpn, 1, 0)
node _hitsVec_T = xor(sectored_entries[0][0].tag_vpn, vpn)
node _hitsVec_T_1 = shr(_hitsVec_T, 2)
node _hitsVec_T_2 = eq(_hitsVec_T_1, UInt<1>(0h0))
node _hitsVec_T_3 = eq(sectored_entries[0][0].tag_v, priv_v)
node _hitsVec_T_4 = and(_hitsVec_T_2, _hitsVec_T_3)
node _hitsVec_T_5 = and(sectored_entries[0][0].valid[hitsVec_idx], _hitsVec_T_4)
node hitsVec_0 = and(vm_enabled, _hitsVec_T_5)
node hitsVec_idx_1 = bits(vpn, 1, 0)
node _hitsVec_T_6 = xor(sectored_entries[0][1].tag_vpn, vpn)
node _hitsVec_T_7 = shr(_hitsVec_T_6, 2)
node _hitsVec_T_8 = eq(_hitsVec_T_7, UInt<1>(0h0))
node _hitsVec_T_9 = eq(sectored_entries[0][1].tag_v, priv_v)
node _hitsVec_T_10 = and(_hitsVec_T_8, _hitsVec_T_9)
node _hitsVec_T_11 = and(sectored_entries[0][1].valid[hitsVec_idx_1], _hitsVec_T_10)
node hitsVec_1 = and(vm_enabled, _hitsVec_T_11)
node hitsVec_idx_2 = bits(vpn, 1, 0)
node _hitsVec_T_12 = xor(sectored_entries[0][2].tag_vpn, vpn)
node _hitsVec_T_13 = shr(_hitsVec_T_12, 2)
node _hitsVec_T_14 = eq(_hitsVec_T_13, UInt<1>(0h0))
node _hitsVec_T_15 = eq(sectored_entries[0][2].tag_v, priv_v)
node _hitsVec_T_16 = and(_hitsVec_T_14, _hitsVec_T_15)
node _hitsVec_T_17 = and(sectored_entries[0][2].valid[hitsVec_idx_2], _hitsVec_T_16)
node hitsVec_2 = and(vm_enabled, _hitsVec_T_17)
node hitsVec_idx_3 = bits(vpn, 1, 0)
node _hitsVec_T_18 = xor(sectored_entries[0][3].tag_vpn, vpn)
node _hitsVec_T_19 = shr(_hitsVec_T_18, 2)
node _hitsVec_T_20 = eq(_hitsVec_T_19, UInt<1>(0h0))
node _hitsVec_T_21 = eq(sectored_entries[0][3].tag_v, priv_v)
node _hitsVec_T_22 = and(_hitsVec_T_20, _hitsVec_T_21)
node _hitsVec_T_23 = and(sectored_entries[0][3].valid[hitsVec_idx_3], _hitsVec_T_22)
node hitsVec_3 = and(vm_enabled, _hitsVec_T_23)
node hitsVec_idx_4 = bits(vpn, 1, 0)
node _hitsVec_T_24 = xor(sectored_entries[0][4].tag_vpn, vpn)
node _hitsVec_T_25 = shr(_hitsVec_T_24, 2)
node _hitsVec_T_26 = eq(_hitsVec_T_25, UInt<1>(0h0))
node _hitsVec_T_27 = eq(sectored_entries[0][4].tag_v, priv_v)
node _hitsVec_T_28 = and(_hitsVec_T_26, _hitsVec_T_27)
node _hitsVec_T_29 = and(sectored_entries[0][4].valid[hitsVec_idx_4], _hitsVec_T_28)
node hitsVec_4 = and(vm_enabled, _hitsVec_T_29)
node hitsVec_idx_5 = bits(vpn, 1, 0)
node _hitsVec_T_30 = xor(sectored_entries[0][5].tag_vpn, vpn)
node _hitsVec_T_31 = shr(_hitsVec_T_30, 2)
node _hitsVec_T_32 = eq(_hitsVec_T_31, UInt<1>(0h0))
node _hitsVec_T_33 = eq(sectored_entries[0][5].tag_v, priv_v)
node _hitsVec_T_34 = and(_hitsVec_T_32, _hitsVec_T_33)
node _hitsVec_T_35 = and(sectored_entries[0][5].valid[hitsVec_idx_5], _hitsVec_T_34)
node hitsVec_5 = and(vm_enabled, _hitsVec_T_35)
node hitsVec_idx_6 = bits(vpn, 1, 0)
node _hitsVec_T_36 = xor(sectored_entries[0][6].tag_vpn, vpn)
node _hitsVec_T_37 = shr(_hitsVec_T_36, 2)
node _hitsVec_T_38 = eq(_hitsVec_T_37, UInt<1>(0h0))
node _hitsVec_T_39 = eq(sectored_entries[0][6].tag_v, priv_v)
node _hitsVec_T_40 = and(_hitsVec_T_38, _hitsVec_T_39)
node _hitsVec_T_41 = and(sectored_entries[0][6].valid[hitsVec_idx_6], _hitsVec_T_40)
node hitsVec_6 = and(vm_enabled, _hitsVec_T_41)
node hitsVec_idx_7 = bits(vpn, 1, 0)
node _hitsVec_T_42 = xor(sectored_entries[0][7].tag_vpn, vpn)
node _hitsVec_T_43 = shr(_hitsVec_T_42, 2)
node _hitsVec_T_44 = eq(_hitsVec_T_43, UInt<1>(0h0))
node _hitsVec_T_45 = eq(sectored_entries[0][7].tag_v, priv_v)
node _hitsVec_T_46 = and(_hitsVec_T_44, _hitsVec_T_45)
node _hitsVec_T_47 = and(sectored_entries[0][7].valid[hitsVec_idx_7], _hitsVec_T_46)
node hitsVec_7 = and(vm_enabled, _hitsVec_T_47)
node _hitsVec_tagMatch_T = eq(superpage_entries[0].tag_v, priv_v)
node hitsVec_tagMatch = and(superpage_entries[0].valid[0], _hitsVec_tagMatch_T)
node _hitsVec_ignore_T = lt(superpage_entries[0].level, UInt<1>(0h0))
node hitsVec_ignore = or(_hitsVec_ignore_T, UInt<1>(0h0))
node _hitsVec_T_48 = xor(superpage_entries[0].tag_vpn, vpn)
node _hitsVec_T_49 = bits(_hitsVec_T_48, 26, 18)
node _hitsVec_T_50 = eq(_hitsVec_T_49, UInt<1>(0h0))
node _hitsVec_T_51 = or(hitsVec_ignore, _hitsVec_T_50)
node _hitsVec_T_52 = and(hitsVec_tagMatch, _hitsVec_T_51)
node _hitsVec_ignore_T_1 = lt(superpage_entries[0].level, UInt<1>(0h1))
node hitsVec_ignore_1 = or(_hitsVec_ignore_T_1, UInt<1>(0h0))
node _hitsVec_T_53 = xor(superpage_entries[0].tag_vpn, vpn)
node _hitsVec_T_54 = bits(_hitsVec_T_53, 17, 9)
node _hitsVec_T_55 = eq(_hitsVec_T_54, UInt<1>(0h0))
node _hitsVec_T_56 = or(hitsVec_ignore_1, _hitsVec_T_55)
node _hitsVec_T_57 = and(_hitsVec_T_52, _hitsVec_T_56)
node _hitsVec_ignore_T_2 = lt(superpage_entries[0].level, UInt<2>(0h2))
node hitsVec_ignore_2 = or(_hitsVec_ignore_T_2, UInt<1>(0h1))
node _hitsVec_T_58 = xor(superpage_entries[0].tag_vpn, vpn)
node _hitsVec_T_59 = bits(_hitsVec_T_58, 8, 0)
node _hitsVec_T_60 = eq(_hitsVec_T_59, UInt<1>(0h0))
node _hitsVec_T_61 = or(hitsVec_ignore_2, _hitsVec_T_60)
node _hitsVec_T_62 = and(_hitsVec_T_57, _hitsVec_T_61)
node hitsVec_8 = and(vm_enabled, _hitsVec_T_62)
node _hitsVec_tagMatch_T_1 = eq(superpage_entries[1].tag_v, priv_v)
node hitsVec_tagMatch_1 = and(superpage_entries[1].valid[0], _hitsVec_tagMatch_T_1)
node _hitsVec_ignore_T_3 = lt(superpage_entries[1].level, UInt<1>(0h0))
node hitsVec_ignore_3 = or(_hitsVec_ignore_T_3, UInt<1>(0h0))
node _hitsVec_T_63 = xor(superpage_entries[1].tag_vpn, vpn)
node _hitsVec_T_64 = bits(_hitsVec_T_63, 26, 18)
node _hitsVec_T_65 = eq(_hitsVec_T_64, UInt<1>(0h0))
node _hitsVec_T_66 = or(hitsVec_ignore_3, _hitsVec_T_65)
node _hitsVec_T_67 = and(hitsVec_tagMatch_1, _hitsVec_T_66)
node _hitsVec_ignore_T_4 = lt(superpage_entries[1].level, UInt<1>(0h1))
node hitsVec_ignore_4 = or(_hitsVec_ignore_T_4, UInt<1>(0h0))
node _hitsVec_T_68 = xor(superpage_entries[1].tag_vpn, vpn)
node _hitsVec_T_69 = bits(_hitsVec_T_68, 17, 9)
node _hitsVec_T_70 = eq(_hitsVec_T_69, UInt<1>(0h0))
node _hitsVec_T_71 = or(hitsVec_ignore_4, _hitsVec_T_70)
node _hitsVec_T_72 = and(_hitsVec_T_67, _hitsVec_T_71)
node _hitsVec_ignore_T_5 = lt(superpage_entries[1].level, UInt<2>(0h2))
node hitsVec_ignore_5 = or(_hitsVec_ignore_T_5, UInt<1>(0h1))
node _hitsVec_T_73 = xor(superpage_entries[1].tag_vpn, vpn)
node _hitsVec_T_74 = bits(_hitsVec_T_73, 8, 0)
node _hitsVec_T_75 = eq(_hitsVec_T_74, UInt<1>(0h0))
node _hitsVec_T_76 = or(hitsVec_ignore_5, _hitsVec_T_75)
node _hitsVec_T_77 = and(_hitsVec_T_72, _hitsVec_T_76)
node hitsVec_9 = and(vm_enabled, _hitsVec_T_77)
node _hitsVec_tagMatch_T_2 = eq(superpage_entries[2].tag_v, priv_v)
node hitsVec_tagMatch_2 = and(superpage_entries[2].valid[0], _hitsVec_tagMatch_T_2)
node _hitsVec_ignore_T_6 = lt(superpage_entries[2].level, UInt<1>(0h0))
node hitsVec_ignore_6 = or(_hitsVec_ignore_T_6, UInt<1>(0h0))
node _hitsVec_T_78 = xor(superpage_entries[2].tag_vpn, vpn)
node _hitsVec_T_79 = bits(_hitsVec_T_78, 26, 18)
node _hitsVec_T_80 = eq(_hitsVec_T_79, UInt<1>(0h0))
node _hitsVec_T_81 = or(hitsVec_ignore_6, _hitsVec_T_80)
node _hitsVec_T_82 = and(hitsVec_tagMatch_2, _hitsVec_T_81)
node _hitsVec_ignore_T_7 = lt(superpage_entries[2].level, UInt<1>(0h1))
node hitsVec_ignore_7 = or(_hitsVec_ignore_T_7, UInt<1>(0h0))
node _hitsVec_T_83 = xor(superpage_entries[2].tag_vpn, vpn)
node _hitsVec_T_84 = bits(_hitsVec_T_83, 17, 9)
node _hitsVec_T_85 = eq(_hitsVec_T_84, UInt<1>(0h0))
node _hitsVec_T_86 = or(hitsVec_ignore_7, _hitsVec_T_85)
node _hitsVec_T_87 = and(_hitsVec_T_82, _hitsVec_T_86)
node _hitsVec_ignore_T_8 = lt(superpage_entries[2].level, UInt<2>(0h2))
node hitsVec_ignore_8 = or(_hitsVec_ignore_T_8, UInt<1>(0h1))
node _hitsVec_T_88 = xor(superpage_entries[2].tag_vpn, vpn)
node _hitsVec_T_89 = bits(_hitsVec_T_88, 8, 0)
node _hitsVec_T_90 = eq(_hitsVec_T_89, UInt<1>(0h0))
node _hitsVec_T_91 = or(hitsVec_ignore_8, _hitsVec_T_90)
node _hitsVec_T_92 = and(_hitsVec_T_87, _hitsVec_T_91)
node hitsVec_10 = and(vm_enabled, _hitsVec_T_92)
node _hitsVec_tagMatch_T_3 = eq(superpage_entries[3].tag_v, priv_v)
node hitsVec_tagMatch_3 = and(superpage_entries[3].valid[0], _hitsVec_tagMatch_T_3)
node _hitsVec_ignore_T_9 = lt(superpage_entries[3].level, UInt<1>(0h0))
node hitsVec_ignore_9 = or(_hitsVec_ignore_T_9, UInt<1>(0h0))
node _hitsVec_T_93 = xor(superpage_entries[3].tag_vpn, vpn)
node _hitsVec_T_94 = bits(_hitsVec_T_93, 26, 18)
node _hitsVec_T_95 = eq(_hitsVec_T_94, UInt<1>(0h0))
node _hitsVec_T_96 = or(hitsVec_ignore_9, _hitsVec_T_95)
node _hitsVec_T_97 = and(hitsVec_tagMatch_3, _hitsVec_T_96)
node _hitsVec_ignore_T_10 = lt(superpage_entries[3].level, UInt<1>(0h1))
node hitsVec_ignore_10 = or(_hitsVec_ignore_T_10, UInt<1>(0h0))
node _hitsVec_T_98 = xor(superpage_entries[3].tag_vpn, vpn)
node _hitsVec_T_99 = bits(_hitsVec_T_98, 17, 9)
node _hitsVec_T_100 = eq(_hitsVec_T_99, UInt<1>(0h0))
node _hitsVec_T_101 = or(hitsVec_ignore_10, _hitsVec_T_100)
node _hitsVec_T_102 = and(_hitsVec_T_97, _hitsVec_T_101)
node _hitsVec_ignore_T_11 = lt(superpage_entries[3].level, UInt<2>(0h2))
node hitsVec_ignore_11 = or(_hitsVec_ignore_T_11, UInt<1>(0h1))
node _hitsVec_T_103 = xor(superpage_entries[3].tag_vpn, vpn)
node _hitsVec_T_104 = bits(_hitsVec_T_103, 8, 0)
node _hitsVec_T_105 = eq(_hitsVec_T_104, UInt<1>(0h0))
node _hitsVec_T_106 = or(hitsVec_ignore_11, _hitsVec_T_105)
node _hitsVec_T_107 = and(_hitsVec_T_102, _hitsVec_T_106)
node hitsVec_11 = and(vm_enabled, _hitsVec_T_107)
node _hitsVec_tagMatch_T_4 = eq(special_entry.tag_v, priv_v)
node hitsVec_tagMatch_4 = and(special_entry.valid[0], _hitsVec_tagMatch_T_4)
node _hitsVec_ignore_T_12 = lt(special_entry.level, UInt<1>(0h0))
node hitsVec_ignore_12 = or(_hitsVec_ignore_T_12, UInt<1>(0h0))
node _hitsVec_T_108 = xor(special_entry.tag_vpn, vpn)
node _hitsVec_T_109 = bits(_hitsVec_T_108, 26, 18)
node _hitsVec_T_110 = eq(_hitsVec_T_109, UInt<1>(0h0))
node _hitsVec_T_111 = or(hitsVec_ignore_12, _hitsVec_T_110)
node _hitsVec_T_112 = and(hitsVec_tagMatch_4, _hitsVec_T_111)
node _hitsVec_ignore_T_13 = lt(special_entry.level, UInt<1>(0h1))
node hitsVec_ignore_13 = or(_hitsVec_ignore_T_13, UInt<1>(0h0))
node _hitsVec_T_113 = xor(special_entry.tag_vpn, vpn)
node _hitsVec_T_114 = bits(_hitsVec_T_113, 17, 9)
node _hitsVec_T_115 = eq(_hitsVec_T_114, UInt<1>(0h0))
node _hitsVec_T_116 = or(hitsVec_ignore_13, _hitsVec_T_115)
node _hitsVec_T_117 = and(_hitsVec_T_112, _hitsVec_T_116)
node _hitsVec_ignore_T_14 = lt(special_entry.level, UInt<2>(0h2))
node hitsVec_ignore_14 = or(_hitsVec_ignore_T_14, UInt<1>(0h0))
node _hitsVec_T_118 = xor(special_entry.tag_vpn, vpn)
node _hitsVec_T_119 = bits(_hitsVec_T_118, 8, 0)
node _hitsVec_T_120 = eq(_hitsVec_T_119, UInt<1>(0h0))
node _hitsVec_T_121 = or(hitsVec_ignore_14, _hitsVec_T_120)
node _hitsVec_T_122 = and(_hitsVec_T_117, _hitsVec_T_121)
node hitsVec_12 = and(vm_enabled, _hitsVec_T_122)
node real_hits_lo_lo_hi = cat(hitsVec_2, hitsVec_1)
node real_hits_lo_lo = cat(real_hits_lo_lo_hi, hitsVec_0)
node real_hits_lo_hi_hi = cat(hitsVec_5, hitsVec_4)
node real_hits_lo_hi = cat(real_hits_lo_hi_hi, hitsVec_3)
node real_hits_lo = cat(real_hits_lo_hi, real_hits_lo_lo)
node real_hits_hi_lo_hi = cat(hitsVec_8, hitsVec_7)
node real_hits_hi_lo = cat(real_hits_hi_lo_hi, hitsVec_6)
node real_hits_hi_hi_lo = cat(hitsVec_10, hitsVec_9)
node real_hits_hi_hi_hi = cat(hitsVec_12, hitsVec_11)
node real_hits_hi_hi = cat(real_hits_hi_hi_hi, real_hits_hi_hi_lo)
node real_hits_hi = cat(real_hits_hi_hi, real_hits_hi_lo)
node real_hits = cat(real_hits_hi, real_hits_lo)
node _hits_T = eq(vm_enabled, UInt<1>(0h0))
node hits = cat(_hits_T, real_hits)
when do_refill :
node refill_v = or(r_vstage1_en, r_stage2_en)
wire newEntry : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
connect newEntry.ppn, io.ptw.resp.bits.pte.ppn
connect newEntry.c, cacheable
connect newEntry.u, io.ptw.resp.bits.pte.u
node _newEntry_g_T = and(io.ptw.resp.bits.pte.g, io.ptw.resp.bits.pte.v)
connect newEntry.g, _newEntry_g_T
connect newEntry.ae_ptw, io.ptw.resp.bits.ae_ptw
connect newEntry.ae_final, io.ptw.resp.bits.ae_final
node _newEntry_ae_stage2_T = and(io.ptw.resp.bits.ae_final, io.ptw.resp.bits.gpa_is_pte)
node _newEntry_ae_stage2_T_1 = and(_newEntry_ae_stage2_T, r_stage2_en)
connect newEntry.ae_stage2, _newEntry_ae_stage2_T_1
connect newEntry.pf, io.ptw.resp.bits.pf
connect newEntry.gf, io.ptw.resp.bits.gf
connect newEntry.hr, io.ptw.resp.bits.hr
connect newEntry.hw, io.ptw.resp.bits.hw
connect newEntry.hx, io.ptw.resp.bits.hx
node _newEntry_sr_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0))
node _newEntry_sr_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sr_T)
node _newEntry_sr_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sr_T_1)
node _newEntry_sr_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sr_T_2)
node _newEntry_sr_T_4 = and(_newEntry_sr_T_3, io.ptw.resp.bits.pte.a)
node _newEntry_sr_T_5 = and(_newEntry_sr_T_4, io.ptw.resp.bits.pte.r)
connect newEntry.sr, _newEntry_sr_T_5
node _newEntry_sw_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0))
node _newEntry_sw_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sw_T)
node _newEntry_sw_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sw_T_1)
node _newEntry_sw_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sw_T_2)
node _newEntry_sw_T_4 = and(_newEntry_sw_T_3, io.ptw.resp.bits.pte.a)
node _newEntry_sw_T_5 = and(_newEntry_sw_T_4, io.ptw.resp.bits.pte.w)
node _newEntry_sw_T_6 = and(_newEntry_sw_T_5, io.ptw.resp.bits.pte.d)
connect newEntry.sw, _newEntry_sw_T_6
node _newEntry_sx_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0))
node _newEntry_sx_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sx_T)
node _newEntry_sx_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sx_T_1)
node _newEntry_sx_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sx_T_2)
node _newEntry_sx_T_4 = and(_newEntry_sx_T_3, io.ptw.resp.bits.pte.a)
node _newEntry_sx_T_5 = and(_newEntry_sx_T_4, io.ptw.resp.bits.pte.x)
connect newEntry.sx, _newEntry_sx_T_5
connect newEntry.pr, prot_r
connect newEntry.pw, prot_w
connect newEntry.px, prot_x
connect newEntry.ppp, pma.io.resp.pp
connect newEntry.pal, pma.io.resp.al
connect newEntry.paa, pma.io.resp.aa
connect newEntry.eff, pma.io.resp.eff
connect newEntry.fragmented_superpage, io.ptw.resp.bits.fragmented_superpage
node _T = eq(io.ptw.resp.bits.homogeneous, UInt<1>(0h0))
node _T_1 = and(UInt<1>(0h1), _T)
when _T_1 :
connect special_entry.tag_vpn, r_refill_tag
connect special_entry.tag_v, refill_v
node _special_entry_level_T = bits(io.ptw.resp.bits.level, 1, 0)
connect special_entry.level, _special_entry_level_T
connect special_entry.valid[0], UInt<1>(0h1)
node special_entry_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node special_entry_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node special_entry_data_0_lo_lo_hi = cat(special_entry_data_0_lo_lo_hi_hi, newEntry.eff)
node special_entry_data_0_lo_lo = cat(special_entry_data_0_lo_lo_hi, special_entry_data_0_lo_lo_lo)
node special_entry_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node special_entry_data_0_lo_hi_lo = cat(special_entry_data_0_lo_hi_lo_hi, newEntry.ppp)
node special_entry_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node special_entry_data_0_lo_hi_hi = cat(special_entry_data_0_lo_hi_hi_hi, newEntry.pw)
node special_entry_data_0_lo_hi = cat(special_entry_data_0_lo_hi_hi, special_entry_data_0_lo_hi_lo)
node special_entry_data_0_lo = cat(special_entry_data_0_lo_hi, special_entry_data_0_lo_lo)
node special_entry_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node special_entry_data_0_hi_lo_lo = cat(special_entry_data_0_hi_lo_lo_hi, newEntry.hw)
node special_entry_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node special_entry_data_0_hi_lo_hi = cat(special_entry_data_0_hi_lo_hi_hi, newEntry.sw)
node special_entry_data_0_hi_lo = cat(special_entry_data_0_hi_lo_hi, special_entry_data_0_hi_lo_lo)
node special_entry_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node special_entry_data_0_hi_hi_lo = cat(special_entry_data_0_hi_hi_lo_hi, newEntry.ae_stage2)
node special_entry_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node special_entry_data_0_hi_hi_hi = cat(special_entry_data_0_hi_hi_hi_hi, newEntry.g)
node special_entry_data_0_hi_hi = cat(special_entry_data_0_hi_hi_hi, special_entry_data_0_hi_hi_lo)
node special_entry_data_0_hi = cat(special_entry_data_0_hi_hi, special_entry_data_0_hi_lo)
node _special_entry_data_0_T = cat(special_entry_data_0_hi, special_entry_data_0_lo)
connect special_entry.data[0], _special_entry_data_0_T
else :
node _T_2 = lt(io.ptw.resp.bits.level, UInt<2>(0h2))
when _T_2 :
node _waddr_T = and(r_superpage_hit.valid, UInt<1>(0h0))
node waddr = mux(_waddr_T, r_superpage_hit.bits, r_superpage_repl_addr)
node _T_3 = eq(r_superpage_repl_addr, UInt<1>(0h0))
when _T_3 :
connect superpage_entries[0].tag_vpn, r_refill_tag
connect superpage_entries[0].tag_v, refill_v
node _superpage_entries_0_level_T = bits(io.ptw.resp.bits.level, 0, 0)
connect superpage_entries[0].level, _superpage_entries_0_level_T
connect superpage_entries[0].valid[0], UInt<1>(0h1)
node superpage_entries_0_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node superpage_entries_0_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node superpage_entries_0_data_0_lo_lo_hi = cat(superpage_entries_0_data_0_lo_lo_hi_hi, newEntry.eff)
node superpage_entries_0_data_0_lo_lo = cat(superpage_entries_0_data_0_lo_lo_hi, superpage_entries_0_data_0_lo_lo_lo)
node superpage_entries_0_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node superpage_entries_0_data_0_lo_hi_lo = cat(superpage_entries_0_data_0_lo_hi_lo_hi, newEntry.ppp)
node superpage_entries_0_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node superpage_entries_0_data_0_lo_hi_hi = cat(superpage_entries_0_data_0_lo_hi_hi_hi, newEntry.pw)
node superpage_entries_0_data_0_lo_hi = cat(superpage_entries_0_data_0_lo_hi_hi, superpage_entries_0_data_0_lo_hi_lo)
node superpage_entries_0_data_0_lo = cat(superpage_entries_0_data_0_lo_hi, superpage_entries_0_data_0_lo_lo)
node superpage_entries_0_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node superpage_entries_0_data_0_hi_lo_lo = cat(superpage_entries_0_data_0_hi_lo_lo_hi, newEntry.hw)
node superpage_entries_0_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node superpage_entries_0_data_0_hi_lo_hi = cat(superpage_entries_0_data_0_hi_lo_hi_hi, newEntry.sw)
node superpage_entries_0_data_0_hi_lo = cat(superpage_entries_0_data_0_hi_lo_hi, superpage_entries_0_data_0_hi_lo_lo)
node superpage_entries_0_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node superpage_entries_0_data_0_hi_hi_lo = cat(superpage_entries_0_data_0_hi_hi_lo_hi, newEntry.ae_stage2)
node superpage_entries_0_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node superpage_entries_0_data_0_hi_hi_hi = cat(superpage_entries_0_data_0_hi_hi_hi_hi, newEntry.g)
node superpage_entries_0_data_0_hi_hi = cat(superpage_entries_0_data_0_hi_hi_hi, superpage_entries_0_data_0_hi_hi_lo)
node superpage_entries_0_data_0_hi = cat(superpage_entries_0_data_0_hi_hi, superpage_entries_0_data_0_hi_lo)
node _superpage_entries_0_data_0_T = cat(superpage_entries_0_data_0_hi, superpage_entries_0_data_0_lo)
connect superpage_entries[0].data[0], _superpage_entries_0_data_0_T
when invalidate_refill :
connect superpage_entries[0].valid[0], UInt<1>(0h0)
node _T_4 = eq(r_superpage_repl_addr, UInt<1>(0h1))
when _T_4 :
connect superpage_entries[1].tag_vpn, r_refill_tag
connect superpage_entries[1].tag_v, refill_v
node _superpage_entries_1_level_T = bits(io.ptw.resp.bits.level, 0, 0)
connect superpage_entries[1].level, _superpage_entries_1_level_T
connect superpage_entries[1].valid[0], UInt<1>(0h1)
node superpage_entries_1_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node superpage_entries_1_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node superpage_entries_1_data_0_lo_lo_hi = cat(superpage_entries_1_data_0_lo_lo_hi_hi, newEntry.eff)
node superpage_entries_1_data_0_lo_lo = cat(superpage_entries_1_data_0_lo_lo_hi, superpage_entries_1_data_0_lo_lo_lo)
node superpage_entries_1_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node superpage_entries_1_data_0_lo_hi_lo = cat(superpage_entries_1_data_0_lo_hi_lo_hi, newEntry.ppp)
node superpage_entries_1_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node superpage_entries_1_data_0_lo_hi_hi = cat(superpage_entries_1_data_0_lo_hi_hi_hi, newEntry.pw)
node superpage_entries_1_data_0_lo_hi = cat(superpage_entries_1_data_0_lo_hi_hi, superpage_entries_1_data_0_lo_hi_lo)
node superpage_entries_1_data_0_lo = cat(superpage_entries_1_data_0_lo_hi, superpage_entries_1_data_0_lo_lo)
node superpage_entries_1_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node superpage_entries_1_data_0_hi_lo_lo = cat(superpage_entries_1_data_0_hi_lo_lo_hi, newEntry.hw)
node superpage_entries_1_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node superpage_entries_1_data_0_hi_lo_hi = cat(superpage_entries_1_data_0_hi_lo_hi_hi, newEntry.sw)
node superpage_entries_1_data_0_hi_lo = cat(superpage_entries_1_data_0_hi_lo_hi, superpage_entries_1_data_0_hi_lo_lo)
node superpage_entries_1_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node superpage_entries_1_data_0_hi_hi_lo = cat(superpage_entries_1_data_0_hi_hi_lo_hi, newEntry.ae_stage2)
node superpage_entries_1_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node superpage_entries_1_data_0_hi_hi_hi = cat(superpage_entries_1_data_0_hi_hi_hi_hi, newEntry.g)
node superpage_entries_1_data_0_hi_hi = cat(superpage_entries_1_data_0_hi_hi_hi, superpage_entries_1_data_0_hi_hi_lo)
node superpage_entries_1_data_0_hi = cat(superpage_entries_1_data_0_hi_hi, superpage_entries_1_data_0_hi_lo)
node _superpage_entries_1_data_0_T = cat(superpage_entries_1_data_0_hi, superpage_entries_1_data_0_lo)
connect superpage_entries[1].data[0], _superpage_entries_1_data_0_T
when invalidate_refill :
connect superpage_entries[1].valid[0], UInt<1>(0h0)
node _T_5 = eq(r_superpage_repl_addr, UInt<2>(0h2))
when _T_5 :
connect superpage_entries[2].tag_vpn, r_refill_tag
connect superpage_entries[2].tag_v, refill_v
node _superpage_entries_2_level_T = bits(io.ptw.resp.bits.level, 0, 0)
connect superpage_entries[2].level, _superpage_entries_2_level_T
connect superpage_entries[2].valid[0], UInt<1>(0h1)
node superpage_entries_2_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node superpage_entries_2_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node superpage_entries_2_data_0_lo_lo_hi = cat(superpage_entries_2_data_0_lo_lo_hi_hi, newEntry.eff)
node superpage_entries_2_data_0_lo_lo = cat(superpage_entries_2_data_0_lo_lo_hi, superpage_entries_2_data_0_lo_lo_lo)
node superpage_entries_2_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node superpage_entries_2_data_0_lo_hi_lo = cat(superpage_entries_2_data_0_lo_hi_lo_hi, newEntry.ppp)
node superpage_entries_2_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node superpage_entries_2_data_0_lo_hi_hi = cat(superpage_entries_2_data_0_lo_hi_hi_hi, newEntry.pw)
node superpage_entries_2_data_0_lo_hi = cat(superpage_entries_2_data_0_lo_hi_hi, superpage_entries_2_data_0_lo_hi_lo)
node superpage_entries_2_data_0_lo = cat(superpage_entries_2_data_0_lo_hi, superpage_entries_2_data_0_lo_lo)
node superpage_entries_2_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node superpage_entries_2_data_0_hi_lo_lo = cat(superpage_entries_2_data_0_hi_lo_lo_hi, newEntry.hw)
node superpage_entries_2_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node superpage_entries_2_data_0_hi_lo_hi = cat(superpage_entries_2_data_0_hi_lo_hi_hi, newEntry.sw)
node superpage_entries_2_data_0_hi_lo = cat(superpage_entries_2_data_0_hi_lo_hi, superpage_entries_2_data_0_hi_lo_lo)
node superpage_entries_2_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node superpage_entries_2_data_0_hi_hi_lo = cat(superpage_entries_2_data_0_hi_hi_lo_hi, newEntry.ae_stage2)
node superpage_entries_2_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node superpage_entries_2_data_0_hi_hi_hi = cat(superpage_entries_2_data_0_hi_hi_hi_hi, newEntry.g)
node superpage_entries_2_data_0_hi_hi = cat(superpage_entries_2_data_0_hi_hi_hi, superpage_entries_2_data_0_hi_hi_lo)
node superpage_entries_2_data_0_hi = cat(superpage_entries_2_data_0_hi_hi, superpage_entries_2_data_0_hi_lo)
node _superpage_entries_2_data_0_T = cat(superpage_entries_2_data_0_hi, superpage_entries_2_data_0_lo)
connect superpage_entries[2].data[0], _superpage_entries_2_data_0_T
when invalidate_refill :
connect superpage_entries[2].valid[0], UInt<1>(0h0)
node _T_6 = eq(r_superpage_repl_addr, UInt<2>(0h3))
when _T_6 :
connect superpage_entries[3].tag_vpn, r_refill_tag
connect superpage_entries[3].tag_v, refill_v
node _superpage_entries_3_level_T = bits(io.ptw.resp.bits.level, 0, 0)
connect superpage_entries[3].level, _superpage_entries_3_level_T
connect superpage_entries[3].valid[0], UInt<1>(0h1)
node superpage_entries_3_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node superpage_entries_3_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node superpage_entries_3_data_0_lo_lo_hi = cat(superpage_entries_3_data_0_lo_lo_hi_hi, newEntry.eff)
node superpage_entries_3_data_0_lo_lo = cat(superpage_entries_3_data_0_lo_lo_hi, superpage_entries_3_data_0_lo_lo_lo)
node superpage_entries_3_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node superpage_entries_3_data_0_lo_hi_lo = cat(superpage_entries_3_data_0_lo_hi_lo_hi, newEntry.ppp)
node superpage_entries_3_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node superpage_entries_3_data_0_lo_hi_hi = cat(superpage_entries_3_data_0_lo_hi_hi_hi, newEntry.pw)
node superpage_entries_3_data_0_lo_hi = cat(superpage_entries_3_data_0_lo_hi_hi, superpage_entries_3_data_0_lo_hi_lo)
node superpage_entries_3_data_0_lo = cat(superpage_entries_3_data_0_lo_hi, superpage_entries_3_data_0_lo_lo)
node superpage_entries_3_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node superpage_entries_3_data_0_hi_lo_lo = cat(superpage_entries_3_data_0_hi_lo_lo_hi, newEntry.hw)
node superpage_entries_3_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node superpage_entries_3_data_0_hi_lo_hi = cat(superpage_entries_3_data_0_hi_lo_hi_hi, newEntry.sw)
node superpage_entries_3_data_0_hi_lo = cat(superpage_entries_3_data_0_hi_lo_hi, superpage_entries_3_data_0_hi_lo_lo)
node superpage_entries_3_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node superpage_entries_3_data_0_hi_hi_lo = cat(superpage_entries_3_data_0_hi_hi_lo_hi, newEntry.ae_stage2)
node superpage_entries_3_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node superpage_entries_3_data_0_hi_hi_hi = cat(superpage_entries_3_data_0_hi_hi_hi_hi, newEntry.g)
node superpage_entries_3_data_0_hi_hi = cat(superpage_entries_3_data_0_hi_hi_hi, superpage_entries_3_data_0_hi_hi_lo)
node superpage_entries_3_data_0_hi = cat(superpage_entries_3_data_0_hi_hi, superpage_entries_3_data_0_hi_lo)
node _superpage_entries_3_data_0_T = cat(superpage_entries_3_data_0_hi, superpage_entries_3_data_0_lo)
connect superpage_entries[3].data[0], _superpage_entries_3_data_0_T
when invalidate_refill :
connect superpage_entries[3].valid[0], UInt<1>(0h0)
else :
node waddr_1 = mux(r_sectored_hit.valid, r_sectored_hit.bits, r_sectored_repl_addr)
node _T_7 = eq(waddr_1, UInt<1>(0h0))
when _T_7 :
node _T_8 = eq(r_sectored_hit.valid, UInt<1>(0h0))
when _T_8 :
connect sectored_entries[0][0].valid[0], UInt<1>(0h0)
connect sectored_entries[0][0].valid[1], UInt<1>(0h0)
connect sectored_entries[0][0].valid[2], UInt<1>(0h0)
connect sectored_entries[0][0].valid[3], UInt<1>(0h0)
connect sectored_entries[0][0].tag_vpn, r_refill_tag
connect sectored_entries[0][0].tag_v, refill_v
connect sectored_entries[0][0].level, UInt<2>(0h0)
node idx = bits(r_refill_tag, 1, 0)
connect sectored_entries[0][0].valid[idx], UInt<1>(0h1)
node sectored_entries_0_0_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node sectored_entries_0_0_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node sectored_entries_0_0_data_lo_lo_hi = cat(sectored_entries_0_0_data_lo_lo_hi_hi, newEntry.eff)
node sectored_entries_0_0_data_lo_lo = cat(sectored_entries_0_0_data_lo_lo_hi, sectored_entries_0_0_data_lo_lo_lo)
node sectored_entries_0_0_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node sectored_entries_0_0_data_lo_hi_lo = cat(sectored_entries_0_0_data_lo_hi_lo_hi, newEntry.ppp)
node sectored_entries_0_0_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node sectored_entries_0_0_data_lo_hi_hi = cat(sectored_entries_0_0_data_lo_hi_hi_hi, newEntry.pw)
node sectored_entries_0_0_data_lo_hi = cat(sectored_entries_0_0_data_lo_hi_hi, sectored_entries_0_0_data_lo_hi_lo)
node sectored_entries_0_0_data_lo = cat(sectored_entries_0_0_data_lo_hi, sectored_entries_0_0_data_lo_lo)
node sectored_entries_0_0_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node sectored_entries_0_0_data_hi_lo_lo = cat(sectored_entries_0_0_data_hi_lo_lo_hi, newEntry.hw)
node sectored_entries_0_0_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node sectored_entries_0_0_data_hi_lo_hi = cat(sectored_entries_0_0_data_hi_lo_hi_hi, newEntry.sw)
node sectored_entries_0_0_data_hi_lo = cat(sectored_entries_0_0_data_hi_lo_hi, sectored_entries_0_0_data_hi_lo_lo)
node sectored_entries_0_0_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node sectored_entries_0_0_data_hi_hi_lo = cat(sectored_entries_0_0_data_hi_hi_lo_hi, newEntry.ae_stage2)
node sectored_entries_0_0_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node sectored_entries_0_0_data_hi_hi_hi = cat(sectored_entries_0_0_data_hi_hi_hi_hi, newEntry.g)
node sectored_entries_0_0_data_hi_hi = cat(sectored_entries_0_0_data_hi_hi_hi, sectored_entries_0_0_data_hi_hi_lo)
node sectored_entries_0_0_data_hi = cat(sectored_entries_0_0_data_hi_hi, sectored_entries_0_0_data_hi_lo)
node _sectored_entries_0_0_data_T = cat(sectored_entries_0_0_data_hi, sectored_entries_0_0_data_lo)
connect sectored_entries[0][0].data[idx], _sectored_entries_0_0_data_T
when invalidate_refill :
connect sectored_entries[0][0].valid[0], UInt<1>(0h0)
connect sectored_entries[0][0].valid[1], UInt<1>(0h0)
connect sectored_entries[0][0].valid[2], UInt<1>(0h0)
connect sectored_entries[0][0].valid[3], UInt<1>(0h0)
node _T_9 = eq(waddr_1, UInt<1>(0h1))
when _T_9 :
node _T_10 = eq(r_sectored_hit.valid, UInt<1>(0h0))
when _T_10 :
connect sectored_entries[0][1].valid[0], UInt<1>(0h0)
connect sectored_entries[0][1].valid[1], UInt<1>(0h0)
connect sectored_entries[0][1].valid[2], UInt<1>(0h0)
connect sectored_entries[0][1].valid[3], UInt<1>(0h0)
connect sectored_entries[0][1].tag_vpn, r_refill_tag
connect sectored_entries[0][1].tag_v, refill_v
connect sectored_entries[0][1].level, UInt<2>(0h0)
node idx_1 = bits(r_refill_tag, 1, 0)
connect sectored_entries[0][1].valid[idx_1], UInt<1>(0h1)
node sectored_entries_0_1_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node sectored_entries_0_1_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node sectored_entries_0_1_data_lo_lo_hi = cat(sectored_entries_0_1_data_lo_lo_hi_hi, newEntry.eff)
node sectored_entries_0_1_data_lo_lo = cat(sectored_entries_0_1_data_lo_lo_hi, sectored_entries_0_1_data_lo_lo_lo)
node sectored_entries_0_1_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node sectored_entries_0_1_data_lo_hi_lo = cat(sectored_entries_0_1_data_lo_hi_lo_hi, newEntry.ppp)
node sectored_entries_0_1_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node sectored_entries_0_1_data_lo_hi_hi = cat(sectored_entries_0_1_data_lo_hi_hi_hi, newEntry.pw)
node sectored_entries_0_1_data_lo_hi = cat(sectored_entries_0_1_data_lo_hi_hi, sectored_entries_0_1_data_lo_hi_lo)
node sectored_entries_0_1_data_lo = cat(sectored_entries_0_1_data_lo_hi, sectored_entries_0_1_data_lo_lo)
node sectored_entries_0_1_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node sectored_entries_0_1_data_hi_lo_lo = cat(sectored_entries_0_1_data_hi_lo_lo_hi, newEntry.hw)
node sectored_entries_0_1_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node sectored_entries_0_1_data_hi_lo_hi = cat(sectored_entries_0_1_data_hi_lo_hi_hi, newEntry.sw)
node sectored_entries_0_1_data_hi_lo = cat(sectored_entries_0_1_data_hi_lo_hi, sectored_entries_0_1_data_hi_lo_lo)
node sectored_entries_0_1_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node sectored_entries_0_1_data_hi_hi_lo = cat(sectored_entries_0_1_data_hi_hi_lo_hi, newEntry.ae_stage2)
node sectored_entries_0_1_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node sectored_entries_0_1_data_hi_hi_hi = cat(sectored_entries_0_1_data_hi_hi_hi_hi, newEntry.g)
node sectored_entries_0_1_data_hi_hi = cat(sectored_entries_0_1_data_hi_hi_hi, sectored_entries_0_1_data_hi_hi_lo)
node sectored_entries_0_1_data_hi = cat(sectored_entries_0_1_data_hi_hi, sectored_entries_0_1_data_hi_lo)
node _sectored_entries_0_1_data_T = cat(sectored_entries_0_1_data_hi, sectored_entries_0_1_data_lo)
connect sectored_entries[0][1].data[idx_1], _sectored_entries_0_1_data_T
when invalidate_refill :
connect sectored_entries[0][1].valid[0], UInt<1>(0h0)
connect sectored_entries[0][1].valid[1], UInt<1>(0h0)
connect sectored_entries[0][1].valid[2], UInt<1>(0h0)
connect sectored_entries[0][1].valid[3], UInt<1>(0h0)
node _T_11 = eq(waddr_1, UInt<2>(0h2))
when _T_11 :
node _T_12 = eq(r_sectored_hit.valid, UInt<1>(0h0))
when _T_12 :
connect sectored_entries[0][2].valid[0], UInt<1>(0h0)
connect sectored_entries[0][2].valid[1], UInt<1>(0h0)
connect sectored_entries[0][2].valid[2], UInt<1>(0h0)
connect sectored_entries[0][2].valid[3], UInt<1>(0h0)
connect sectored_entries[0][2].tag_vpn, r_refill_tag
connect sectored_entries[0][2].tag_v, refill_v
connect sectored_entries[0][2].level, UInt<2>(0h0)
node idx_2 = bits(r_refill_tag, 1, 0)
connect sectored_entries[0][2].valid[idx_2], UInt<1>(0h1)
node sectored_entries_0_2_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node sectored_entries_0_2_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node sectored_entries_0_2_data_lo_lo_hi = cat(sectored_entries_0_2_data_lo_lo_hi_hi, newEntry.eff)
node sectored_entries_0_2_data_lo_lo = cat(sectored_entries_0_2_data_lo_lo_hi, sectored_entries_0_2_data_lo_lo_lo)
node sectored_entries_0_2_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node sectored_entries_0_2_data_lo_hi_lo = cat(sectored_entries_0_2_data_lo_hi_lo_hi, newEntry.ppp)
node sectored_entries_0_2_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node sectored_entries_0_2_data_lo_hi_hi = cat(sectored_entries_0_2_data_lo_hi_hi_hi, newEntry.pw)
node sectored_entries_0_2_data_lo_hi = cat(sectored_entries_0_2_data_lo_hi_hi, sectored_entries_0_2_data_lo_hi_lo)
node sectored_entries_0_2_data_lo = cat(sectored_entries_0_2_data_lo_hi, sectored_entries_0_2_data_lo_lo)
node sectored_entries_0_2_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node sectored_entries_0_2_data_hi_lo_lo = cat(sectored_entries_0_2_data_hi_lo_lo_hi, newEntry.hw)
node sectored_entries_0_2_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node sectored_entries_0_2_data_hi_lo_hi = cat(sectored_entries_0_2_data_hi_lo_hi_hi, newEntry.sw)
node sectored_entries_0_2_data_hi_lo = cat(sectored_entries_0_2_data_hi_lo_hi, sectored_entries_0_2_data_hi_lo_lo)
node sectored_entries_0_2_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node sectored_entries_0_2_data_hi_hi_lo = cat(sectored_entries_0_2_data_hi_hi_lo_hi, newEntry.ae_stage2)
node sectored_entries_0_2_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node sectored_entries_0_2_data_hi_hi_hi = cat(sectored_entries_0_2_data_hi_hi_hi_hi, newEntry.g)
node sectored_entries_0_2_data_hi_hi = cat(sectored_entries_0_2_data_hi_hi_hi, sectored_entries_0_2_data_hi_hi_lo)
node sectored_entries_0_2_data_hi = cat(sectored_entries_0_2_data_hi_hi, sectored_entries_0_2_data_hi_lo)
node _sectored_entries_0_2_data_T = cat(sectored_entries_0_2_data_hi, sectored_entries_0_2_data_lo)
connect sectored_entries[0][2].data[idx_2], _sectored_entries_0_2_data_T
when invalidate_refill :
connect sectored_entries[0][2].valid[0], UInt<1>(0h0)
connect sectored_entries[0][2].valid[1], UInt<1>(0h0)
connect sectored_entries[0][2].valid[2], UInt<1>(0h0)
connect sectored_entries[0][2].valid[3], UInt<1>(0h0)
node _T_13 = eq(waddr_1, UInt<2>(0h3))
when _T_13 :
node _T_14 = eq(r_sectored_hit.valid, UInt<1>(0h0))
when _T_14 :
connect sectored_entries[0][3].valid[0], UInt<1>(0h0)
connect sectored_entries[0][3].valid[1], UInt<1>(0h0)
connect sectored_entries[0][3].valid[2], UInt<1>(0h0)
connect sectored_entries[0][3].valid[3], UInt<1>(0h0)
connect sectored_entries[0][3].tag_vpn, r_refill_tag
connect sectored_entries[0][3].tag_v, refill_v
connect sectored_entries[0][3].level, UInt<2>(0h0)
node idx_3 = bits(r_refill_tag, 1, 0)
connect sectored_entries[0][3].valid[idx_3], UInt<1>(0h1)
node sectored_entries_0_3_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node sectored_entries_0_3_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node sectored_entries_0_3_data_lo_lo_hi = cat(sectored_entries_0_3_data_lo_lo_hi_hi, newEntry.eff)
node sectored_entries_0_3_data_lo_lo = cat(sectored_entries_0_3_data_lo_lo_hi, sectored_entries_0_3_data_lo_lo_lo)
node sectored_entries_0_3_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node sectored_entries_0_3_data_lo_hi_lo = cat(sectored_entries_0_3_data_lo_hi_lo_hi, newEntry.ppp)
node sectored_entries_0_3_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node sectored_entries_0_3_data_lo_hi_hi = cat(sectored_entries_0_3_data_lo_hi_hi_hi, newEntry.pw)
node sectored_entries_0_3_data_lo_hi = cat(sectored_entries_0_3_data_lo_hi_hi, sectored_entries_0_3_data_lo_hi_lo)
node sectored_entries_0_3_data_lo = cat(sectored_entries_0_3_data_lo_hi, sectored_entries_0_3_data_lo_lo)
node sectored_entries_0_3_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node sectored_entries_0_3_data_hi_lo_lo = cat(sectored_entries_0_3_data_hi_lo_lo_hi, newEntry.hw)
node sectored_entries_0_3_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node sectored_entries_0_3_data_hi_lo_hi = cat(sectored_entries_0_3_data_hi_lo_hi_hi, newEntry.sw)
node sectored_entries_0_3_data_hi_lo = cat(sectored_entries_0_3_data_hi_lo_hi, sectored_entries_0_3_data_hi_lo_lo)
node sectored_entries_0_3_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node sectored_entries_0_3_data_hi_hi_lo = cat(sectored_entries_0_3_data_hi_hi_lo_hi, newEntry.ae_stage2)
node sectored_entries_0_3_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node sectored_entries_0_3_data_hi_hi_hi = cat(sectored_entries_0_3_data_hi_hi_hi_hi, newEntry.g)
node sectored_entries_0_3_data_hi_hi = cat(sectored_entries_0_3_data_hi_hi_hi, sectored_entries_0_3_data_hi_hi_lo)
node sectored_entries_0_3_data_hi = cat(sectored_entries_0_3_data_hi_hi, sectored_entries_0_3_data_hi_lo)
node _sectored_entries_0_3_data_T = cat(sectored_entries_0_3_data_hi, sectored_entries_0_3_data_lo)
connect sectored_entries[0][3].data[idx_3], _sectored_entries_0_3_data_T
when invalidate_refill :
connect sectored_entries[0][3].valid[0], UInt<1>(0h0)
connect sectored_entries[0][3].valid[1], UInt<1>(0h0)
connect sectored_entries[0][3].valid[2], UInt<1>(0h0)
connect sectored_entries[0][3].valid[3], UInt<1>(0h0)
node _T_15 = eq(waddr_1, UInt<3>(0h4))
when _T_15 :
node _T_16 = eq(r_sectored_hit.valid, UInt<1>(0h0))
when _T_16 :
connect sectored_entries[0][4].valid[0], UInt<1>(0h0)
connect sectored_entries[0][4].valid[1], UInt<1>(0h0)
connect sectored_entries[0][4].valid[2], UInt<1>(0h0)
connect sectored_entries[0][4].valid[3], UInt<1>(0h0)
connect sectored_entries[0][4].tag_vpn, r_refill_tag
connect sectored_entries[0][4].tag_v, refill_v
connect sectored_entries[0][4].level, UInt<2>(0h0)
node idx_4 = bits(r_refill_tag, 1, 0)
connect sectored_entries[0][4].valid[idx_4], UInt<1>(0h1)
node sectored_entries_0_4_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node sectored_entries_0_4_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node sectored_entries_0_4_data_lo_lo_hi = cat(sectored_entries_0_4_data_lo_lo_hi_hi, newEntry.eff)
node sectored_entries_0_4_data_lo_lo = cat(sectored_entries_0_4_data_lo_lo_hi, sectored_entries_0_4_data_lo_lo_lo)
node sectored_entries_0_4_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node sectored_entries_0_4_data_lo_hi_lo = cat(sectored_entries_0_4_data_lo_hi_lo_hi, newEntry.ppp)
node sectored_entries_0_4_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node sectored_entries_0_4_data_lo_hi_hi = cat(sectored_entries_0_4_data_lo_hi_hi_hi, newEntry.pw)
node sectored_entries_0_4_data_lo_hi = cat(sectored_entries_0_4_data_lo_hi_hi, sectored_entries_0_4_data_lo_hi_lo)
node sectored_entries_0_4_data_lo = cat(sectored_entries_0_4_data_lo_hi, sectored_entries_0_4_data_lo_lo)
node sectored_entries_0_4_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node sectored_entries_0_4_data_hi_lo_lo = cat(sectored_entries_0_4_data_hi_lo_lo_hi, newEntry.hw)
node sectored_entries_0_4_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node sectored_entries_0_4_data_hi_lo_hi = cat(sectored_entries_0_4_data_hi_lo_hi_hi, newEntry.sw)
node sectored_entries_0_4_data_hi_lo = cat(sectored_entries_0_4_data_hi_lo_hi, sectored_entries_0_4_data_hi_lo_lo)
node sectored_entries_0_4_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node sectored_entries_0_4_data_hi_hi_lo = cat(sectored_entries_0_4_data_hi_hi_lo_hi, newEntry.ae_stage2)
node sectored_entries_0_4_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node sectored_entries_0_4_data_hi_hi_hi = cat(sectored_entries_0_4_data_hi_hi_hi_hi, newEntry.g)
node sectored_entries_0_4_data_hi_hi = cat(sectored_entries_0_4_data_hi_hi_hi, sectored_entries_0_4_data_hi_hi_lo)
node sectored_entries_0_4_data_hi = cat(sectored_entries_0_4_data_hi_hi, sectored_entries_0_4_data_hi_lo)
node _sectored_entries_0_4_data_T = cat(sectored_entries_0_4_data_hi, sectored_entries_0_4_data_lo)
connect sectored_entries[0][4].data[idx_4], _sectored_entries_0_4_data_T
when invalidate_refill :
connect sectored_entries[0][4].valid[0], UInt<1>(0h0)
connect sectored_entries[0][4].valid[1], UInt<1>(0h0)
connect sectored_entries[0][4].valid[2], UInt<1>(0h0)
connect sectored_entries[0][4].valid[3], UInt<1>(0h0)
node _T_17 = eq(waddr_1, UInt<3>(0h5))
when _T_17 :
node _T_18 = eq(r_sectored_hit.valid, UInt<1>(0h0))
when _T_18 :
connect sectored_entries[0][5].valid[0], UInt<1>(0h0)
connect sectored_entries[0][5].valid[1], UInt<1>(0h0)
connect sectored_entries[0][5].valid[2], UInt<1>(0h0)
connect sectored_entries[0][5].valid[3], UInt<1>(0h0)
connect sectored_entries[0][5].tag_vpn, r_refill_tag
connect sectored_entries[0][5].tag_v, refill_v
connect sectored_entries[0][5].level, UInt<2>(0h0)
node idx_5 = bits(r_refill_tag, 1, 0)
connect sectored_entries[0][5].valid[idx_5], UInt<1>(0h1)
node sectored_entries_0_5_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node sectored_entries_0_5_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node sectored_entries_0_5_data_lo_lo_hi = cat(sectored_entries_0_5_data_lo_lo_hi_hi, newEntry.eff)
node sectored_entries_0_5_data_lo_lo = cat(sectored_entries_0_5_data_lo_lo_hi, sectored_entries_0_5_data_lo_lo_lo)
node sectored_entries_0_5_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node sectored_entries_0_5_data_lo_hi_lo = cat(sectored_entries_0_5_data_lo_hi_lo_hi, newEntry.ppp)
node sectored_entries_0_5_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node sectored_entries_0_5_data_lo_hi_hi = cat(sectored_entries_0_5_data_lo_hi_hi_hi, newEntry.pw)
node sectored_entries_0_5_data_lo_hi = cat(sectored_entries_0_5_data_lo_hi_hi, sectored_entries_0_5_data_lo_hi_lo)
node sectored_entries_0_5_data_lo = cat(sectored_entries_0_5_data_lo_hi, sectored_entries_0_5_data_lo_lo)
node sectored_entries_0_5_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node sectored_entries_0_5_data_hi_lo_lo = cat(sectored_entries_0_5_data_hi_lo_lo_hi, newEntry.hw)
node sectored_entries_0_5_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node sectored_entries_0_5_data_hi_lo_hi = cat(sectored_entries_0_5_data_hi_lo_hi_hi, newEntry.sw)
node sectored_entries_0_5_data_hi_lo = cat(sectored_entries_0_5_data_hi_lo_hi, sectored_entries_0_5_data_hi_lo_lo)
node sectored_entries_0_5_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node sectored_entries_0_5_data_hi_hi_lo = cat(sectored_entries_0_5_data_hi_hi_lo_hi, newEntry.ae_stage2)
node sectored_entries_0_5_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node sectored_entries_0_5_data_hi_hi_hi = cat(sectored_entries_0_5_data_hi_hi_hi_hi, newEntry.g)
node sectored_entries_0_5_data_hi_hi = cat(sectored_entries_0_5_data_hi_hi_hi, sectored_entries_0_5_data_hi_hi_lo)
node sectored_entries_0_5_data_hi = cat(sectored_entries_0_5_data_hi_hi, sectored_entries_0_5_data_hi_lo)
node _sectored_entries_0_5_data_T = cat(sectored_entries_0_5_data_hi, sectored_entries_0_5_data_lo)
connect sectored_entries[0][5].data[idx_5], _sectored_entries_0_5_data_T
when invalidate_refill :
connect sectored_entries[0][5].valid[0], UInt<1>(0h0)
connect sectored_entries[0][5].valid[1], UInt<1>(0h0)
connect sectored_entries[0][5].valid[2], UInt<1>(0h0)
connect sectored_entries[0][5].valid[3], UInt<1>(0h0)
node _T_19 = eq(waddr_1, UInt<3>(0h6))
when _T_19 :
node _T_20 = eq(r_sectored_hit.valid, UInt<1>(0h0))
when _T_20 :
connect sectored_entries[0][6].valid[0], UInt<1>(0h0)
connect sectored_entries[0][6].valid[1], UInt<1>(0h0)
connect sectored_entries[0][6].valid[2], UInt<1>(0h0)
connect sectored_entries[0][6].valid[3], UInt<1>(0h0)
connect sectored_entries[0][6].tag_vpn, r_refill_tag
connect sectored_entries[0][6].tag_v, refill_v
connect sectored_entries[0][6].level, UInt<2>(0h0)
node idx_6 = bits(r_refill_tag, 1, 0)
connect sectored_entries[0][6].valid[idx_6], UInt<1>(0h1)
node sectored_entries_0_6_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node sectored_entries_0_6_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node sectored_entries_0_6_data_lo_lo_hi = cat(sectored_entries_0_6_data_lo_lo_hi_hi, newEntry.eff)
node sectored_entries_0_6_data_lo_lo = cat(sectored_entries_0_6_data_lo_lo_hi, sectored_entries_0_6_data_lo_lo_lo)
node sectored_entries_0_6_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node sectored_entries_0_6_data_lo_hi_lo = cat(sectored_entries_0_6_data_lo_hi_lo_hi, newEntry.ppp)
node sectored_entries_0_6_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node sectored_entries_0_6_data_lo_hi_hi = cat(sectored_entries_0_6_data_lo_hi_hi_hi, newEntry.pw)
node sectored_entries_0_6_data_lo_hi = cat(sectored_entries_0_6_data_lo_hi_hi, sectored_entries_0_6_data_lo_hi_lo)
node sectored_entries_0_6_data_lo = cat(sectored_entries_0_6_data_lo_hi, sectored_entries_0_6_data_lo_lo)
node sectored_entries_0_6_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node sectored_entries_0_6_data_hi_lo_lo = cat(sectored_entries_0_6_data_hi_lo_lo_hi, newEntry.hw)
node sectored_entries_0_6_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node sectored_entries_0_6_data_hi_lo_hi = cat(sectored_entries_0_6_data_hi_lo_hi_hi, newEntry.sw)
node sectored_entries_0_6_data_hi_lo = cat(sectored_entries_0_6_data_hi_lo_hi, sectored_entries_0_6_data_hi_lo_lo)
node sectored_entries_0_6_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node sectored_entries_0_6_data_hi_hi_lo = cat(sectored_entries_0_6_data_hi_hi_lo_hi, newEntry.ae_stage2)
node sectored_entries_0_6_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node sectored_entries_0_6_data_hi_hi_hi = cat(sectored_entries_0_6_data_hi_hi_hi_hi, newEntry.g)
node sectored_entries_0_6_data_hi_hi = cat(sectored_entries_0_6_data_hi_hi_hi, sectored_entries_0_6_data_hi_hi_lo)
node sectored_entries_0_6_data_hi = cat(sectored_entries_0_6_data_hi_hi, sectored_entries_0_6_data_hi_lo)
node _sectored_entries_0_6_data_T = cat(sectored_entries_0_6_data_hi, sectored_entries_0_6_data_lo)
connect sectored_entries[0][6].data[idx_6], _sectored_entries_0_6_data_T
when invalidate_refill :
connect sectored_entries[0][6].valid[0], UInt<1>(0h0)
connect sectored_entries[0][6].valid[1], UInt<1>(0h0)
connect sectored_entries[0][6].valid[2], UInt<1>(0h0)
connect sectored_entries[0][6].valid[3], UInt<1>(0h0)
node _T_21 = eq(waddr_1, UInt<3>(0h7))
when _T_21 :
node _T_22 = eq(r_sectored_hit.valid, UInt<1>(0h0))
when _T_22 :
connect sectored_entries[0][7].valid[0], UInt<1>(0h0)
connect sectored_entries[0][7].valid[1], UInt<1>(0h0)
connect sectored_entries[0][7].valid[2], UInt<1>(0h0)
connect sectored_entries[0][7].valid[3], UInt<1>(0h0)
connect sectored_entries[0][7].tag_vpn, r_refill_tag
connect sectored_entries[0][7].tag_v, refill_v
connect sectored_entries[0][7].level, UInt<2>(0h0)
node idx_7 = bits(r_refill_tag, 1, 0)
connect sectored_entries[0][7].valid[idx_7], UInt<1>(0h1)
node sectored_entries_0_7_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node sectored_entries_0_7_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node sectored_entries_0_7_data_lo_lo_hi = cat(sectored_entries_0_7_data_lo_lo_hi_hi, newEntry.eff)
node sectored_entries_0_7_data_lo_lo = cat(sectored_entries_0_7_data_lo_lo_hi, sectored_entries_0_7_data_lo_lo_lo)
node sectored_entries_0_7_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node sectored_entries_0_7_data_lo_hi_lo = cat(sectored_entries_0_7_data_lo_hi_lo_hi, newEntry.ppp)
node sectored_entries_0_7_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node sectored_entries_0_7_data_lo_hi_hi = cat(sectored_entries_0_7_data_lo_hi_hi_hi, newEntry.pw)
node sectored_entries_0_7_data_lo_hi = cat(sectored_entries_0_7_data_lo_hi_hi, sectored_entries_0_7_data_lo_hi_lo)
node sectored_entries_0_7_data_lo = cat(sectored_entries_0_7_data_lo_hi, sectored_entries_0_7_data_lo_lo)
node sectored_entries_0_7_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node sectored_entries_0_7_data_hi_lo_lo = cat(sectored_entries_0_7_data_hi_lo_lo_hi, newEntry.hw)
node sectored_entries_0_7_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node sectored_entries_0_7_data_hi_lo_hi = cat(sectored_entries_0_7_data_hi_lo_hi_hi, newEntry.sw)
node sectored_entries_0_7_data_hi_lo = cat(sectored_entries_0_7_data_hi_lo_hi, sectored_entries_0_7_data_hi_lo_lo)
node sectored_entries_0_7_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node sectored_entries_0_7_data_hi_hi_lo = cat(sectored_entries_0_7_data_hi_hi_lo_hi, newEntry.ae_stage2)
node sectored_entries_0_7_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node sectored_entries_0_7_data_hi_hi_hi = cat(sectored_entries_0_7_data_hi_hi_hi_hi, newEntry.g)
node sectored_entries_0_7_data_hi_hi = cat(sectored_entries_0_7_data_hi_hi_hi, sectored_entries_0_7_data_hi_hi_lo)
node sectored_entries_0_7_data_hi = cat(sectored_entries_0_7_data_hi_hi, sectored_entries_0_7_data_hi_lo)
node _sectored_entries_0_7_data_T = cat(sectored_entries_0_7_data_hi, sectored_entries_0_7_data_lo)
connect sectored_entries[0][7].data[idx_7], _sectored_entries_0_7_data_T
when invalidate_refill :
connect sectored_entries[0][7].valid[0], UInt<1>(0h0)
connect sectored_entries[0][7].valid[1], UInt<1>(0h0)
connect sectored_entries[0][7].valid[2], UInt<1>(0h0)
connect sectored_entries[0][7].valid[3], UInt<1>(0h0)
connect r_gpa_valid, io.ptw.resp.bits.gpa.valid
connect r_gpa, io.ptw.resp.bits.gpa.bits
connect r_gpa_is_pte, io.ptw.resp.bits.gpa_is_pte
node _entries_T = bits(vpn, 1, 0)
wire _entries_WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_1 : UInt<42>
connect _entries_WIRE_1, sectored_entries[0][0].data[_entries_T]
node _entries_T_1 = bits(_entries_WIRE_1, 0, 0)
connect _entries_WIRE.fragmented_superpage, _entries_T_1
node _entries_T_2 = bits(_entries_WIRE_1, 1, 1)
connect _entries_WIRE.c, _entries_T_2
node _entries_T_3 = bits(_entries_WIRE_1, 2, 2)
connect _entries_WIRE.eff, _entries_T_3
node _entries_T_4 = bits(_entries_WIRE_1, 3, 3)
connect _entries_WIRE.paa, _entries_T_4
node _entries_T_5 = bits(_entries_WIRE_1, 4, 4)
connect _entries_WIRE.pal, _entries_T_5
node _entries_T_6 = bits(_entries_WIRE_1, 5, 5)
connect _entries_WIRE.ppp, _entries_T_6
node _entries_T_7 = bits(_entries_WIRE_1, 6, 6)
connect _entries_WIRE.pr, _entries_T_7
node _entries_T_8 = bits(_entries_WIRE_1, 7, 7)
connect _entries_WIRE.px, _entries_T_8
node _entries_T_9 = bits(_entries_WIRE_1, 8, 8)
connect _entries_WIRE.pw, _entries_T_9
node _entries_T_10 = bits(_entries_WIRE_1, 9, 9)
connect _entries_WIRE.hr, _entries_T_10
node _entries_T_11 = bits(_entries_WIRE_1, 10, 10)
connect _entries_WIRE.hx, _entries_T_11
node _entries_T_12 = bits(_entries_WIRE_1, 11, 11)
connect _entries_WIRE.hw, _entries_T_12
node _entries_T_13 = bits(_entries_WIRE_1, 12, 12)
connect _entries_WIRE.sr, _entries_T_13
node _entries_T_14 = bits(_entries_WIRE_1, 13, 13)
connect _entries_WIRE.sx, _entries_T_14
node _entries_T_15 = bits(_entries_WIRE_1, 14, 14)
connect _entries_WIRE.sw, _entries_T_15
node _entries_T_16 = bits(_entries_WIRE_1, 15, 15)
connect _entries_WIRE.gf, _entries_T_16
node _entries_T_17 = bits(_entries_WIRE_1, 16, 16)
connect _entries_WIRE.pf, _entries_T_17
node _entries_T_18 = bits(_entries_WIRE_1, 17, 17)
connect _entries_WIRE.ae_stage2, _entries_T_18
node _entries_T_19 = bits(_entries_WIRE_1, 18, 18)
connect _entries_WIRE.ae_final, _entries_T_19
node _entries_T_20 = bits(_entries_WIRE_1, 19, 19)
connect _entries_WIRE.ae_ptw, _entries_T_20
node _entries_T_21 = bits(_entries_WIRE_1, 20, 20)
connect _entries_WIRE.g, _entries_T_21
node _entries_T_22 = bits(_entries_WIRE_1, 21, 21)
connect _entries_WIRE.u, _entries_T_22
node _entries_T_23 = bits(_entries_WIRE_1, 41, 22)
connect _entries_WIRE.ppn, _entries_T_23
inst entries_barrier of OptimizationBarrier_TLBEntryData_43
connect entries_barrier.clock, clock
connect entries_barrier.reset, reset
connect entries_barrier.io.x.fragmented_superpage, _entries_WIRE.fragmented_superpage
connect entries_barrier.io.x.c, _entries_WIRE.c
connect entries_barrier.io.x.eff, _entries_WIRE.eff
connect entries_barrier.io.x.paa, _entries_WIRE.paa
connect entries_barrier.io.x.pal, _entries_WIRE.pal
connect entries_barrier.io.x.ppp, _entries_WIRE.ppp
connect entries_barrier.io.x.pr, _entries_WIRE.pr
connect entries_barrier.io.x.px, _entries_WIRE.px
connect entries_barrier.io.x.pw, _entries_WIRE.pw
connect entries_barrier.io.x.hr, _entries_WIRE.hr
connect entries_barrier.io.x.hx, _entries_WIRE.hx
connect entries_barrier.io.x.hw, _entries_WIRE.hw
connect entries_barrier.io.x.sr, _entries_WIRE.sr
connect entries_barrier.io.x.sx, _entries_WIRE.sx
connect entries_barrier.io.x.sw, _entries_WIRE.sw
connect entries_barrier.io.x.gf, _entries_WIRE.gf
connect entries_barrier.io.x.pf, _entries_WIRE.pf
connect entries_barrier.io.x.ae_stage2, _entries_WIRE.ae_stage2
connect entries_barrier.io.x.ae_final, _entries_WIRE.ae_final
connect entries_barrier.io.x.ae_ptw, _entries_WIRE.ae_ptw
connect entries_barrier.io.x.g, _entries_WIRE.g
connect entries_barrier.io.x.u, _entries_WIRE.u
connect entries_barrier.io.x.ppn, _entries_WIRE.ppn
node _entries_T_24 = bits(vpn, 1, 0)
wire _entries_WIRE_2 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_3 : UInt<42>
connect _entries_WIRE_3, sectored_entries[0][1].data[_entries_T_24]
node _entries_T_25 = bits(_entries_WIRE_3, 0, 0)
connect _entries_WIRE_2.fragmented_superpage, _entries_T_25
node _entries_T_26 = bits(_entries_WIRE_3, 1, 1)
connect _entries_WIRE_2.c, _entries_T_26
node _entries_T_27 = bits(_entries_WIRE_3, 2, 2)
connect _entries_WIRE_2.eff, _entries_T_27
node _entries_T_28 = bits(_entries_WIRE_3, 3, 3)
connect _entries_WIRE_2.paa, _entries_T_28
node _entries_T_29 = bits(_entries_WIRE_3, 4, 4)
connect _entries_WIRE_2.pal, _entries_T_29
node _entries_T_30 = bits(_entries_WIRE_3, 5, 5)
connect _entries_WIRE_2.ppp, _entries_T_30
node _entries_T_31 = bits(_entries_WIRE_3, 6, 6)
connect _entries_WIRE_2.pr, _entries_T_31
node _entries_T_32 = bits(_entries_WIRE_3, 7, 7)
connect _entries_WIRE_2.px, _entries_T_32
node _entries_T_33 = bits(_entries_WIRE_3, 8, 8)
connect _entries_WIRE_2.pw, _entries_T_33
node _entries_T_34 = bits(_entries_WIRE_3, 9, 9)
connect _entries_WIRE_2.hr, _entries_T_34
node _entries_T_35 = bits(_entries_WIRE_3, 10, 10)
connect _entries_WIRE_2.hx, _entries_T_35
node _entries_T_36 = bits(_entries_WIRE_3, 11, 11)
connect _entries_WIRE_2.hw, _entries_T_36
node _entries_T_37 = bits(_entries_WIRE_3, 12, 12)
connect _entries_WIRE_2.sr, _entries_T_37
node _entries_T_38 = bits(_entries_WIRE_3, 13, 13)
connect _entries_WIRE_2.sx, _entries_T_38
node _entries_T_39 = bits(_entries_WIRE_3, 14, 14)
connect _entries_WIRE_2.sw, _entries_T_39
node _entries_T_40 = bits(_entries_WIRE_3, 15, 15)
connect _entries_WIRE_2.gf, _entries_T_40
node _entries_T_41 = bits(_entries_WIRE_3, 16, 16)
connect _entries_WIRE_2.pf, _entries_T_41
node _entries_T_42 = bits(_entries_WIRE_3, 17, 17)
connect _entries_WIRE_2.ae_stage2, _entries_T_42
node _entries_T_43 = bits(_entries_WIRE_3, 18, 18)
connect _entries_WIRE_2.ae_final, _entries_T_43
node _entries_T_44 = bits(_entries_WIRE_3, 19, 19)
connect _entries_WIRE_2.ae_ptw, _entries_T_44
node _entries_T_45 = bits(_entries_WIRE_3, 20, 20)
connect _entries_WIRE_2.g, _entries_T_45
node _entries_T_46 = bits(_entries_WIRE_3, 21, 21)
connect _entries_WIRE_2.u, _entries_T_46
node _entries_T_47 = bits(_entries_WIRE_3, 41, 22)
connect _entries_WIRE_2.ppn, _entries_T_47
inst entries_barrier_1 of OptimizationBarrier_TLBEntryData_44
connect entries_barrier_1.clock, clock
connect entries_barrier_1.reset, reset
connect entries_barrier_1.io.x.fragmented_superpage, _entries_WIRE_2.fragmented_superpage
connect entries_barrier_1.io.x.c, _entries_WIRE_2.c
connect entries_barrier_1.io.x.eff, _entries_WIRE_2.eff
connect entries_barrier_1.io.x.paa, _entries_WIRE_2.paa
connect entries_barrier_1.io.x.pal, _entries_WIRE_2.pal
connect entries_barrier_1.io.x.ppp, _entries_WIRE_2.ppp
connect entries_barrier_1.io.x.pr, _entries_WIRE_2.pr
connect entries_barrier_1.io.x.px, _entries_WIRE_2.px
connect entries_barrier_1.io.x.pw, _entries_WIRE_2.pw
connect entries_barrier_1.io.x.hr, _entries_WIRE_2.hr
connect entries_barrier_1.io.x.hx, _entries_WIRE_2.hx
connect entries_barrier_1.io.x.hw, _entries_WIRE_2.hw
connect entries_barrier_1.io.x.sr, _entries_WIRE_2.sr
connect entries_barrier_1.io.x.sx, _entries_WIRE_2.sx
connect entries_barrier_1.io.x.sw, _entries_WIRE_2.sw
connect entries_barrier_1.io.x.gf, _entries_WIRE_2.gf
connect entries_barrier_1.io.x.pf, _entries_WIRE_2.pf
connect entries_barrier_1.io.x.ae_stage2, _entries_WIRE_2.ae_stage2
connect entries_barrier_1.io.x.ae_final, _entries_WIRE_2.ae_final
connect entries_barrier_1.io.x.ae_ptw, _entries_WIRE_2.ae_ptw
connect entries_barrier_1.io.x.g, _entries_WIRE_2.g
connect entries_barrier_1.io.x.u, _entries_WIRE_2.u
connect entries_barrier_1.io.x.ppn, _entries_WIRE_2.ppn
node _entries_T_48 = bits(vpn, 1, 0)
wire _entries_WIRE_4 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_5 : UInt<42>
connect _entries_WIRE_5, sectored_entries[0][2].data[_entries_T_48]
node _entries_T_49 = bits(_entries_WIRE_5, 0, 0)
connect _entries_WIRE_4.fragmented_superpage, _entries_T_49
node _entries_T_50 = bits(_entries_WIRE_5, 1, 1)
connect _entries_WIRE_4.c, _entries_T_50
node _entries_T_51 = bits(_entries_WIRE_5, 2, 2)
connect _entries_WIRE_4.eff, _entries_T_51
node _entries_T_52 = bits(_entries_WIRE_5, 3, 3)
connect _entries_WIRE_4.paa, _entries_T_52
node _entries_T_53 = bits(_entries_WIRE_5, 4, 4)
connect _entries_WIRE_4.pal, _entries_T_53
node _entries_T_54 = bits(_entries_WIRE_5, 5, 5)
connect _entries_WIRE_4.ppp, _entries_T_54
node _entries_T_55 = bits(_entries_WIRE_5, 6, 6)
connect _entries_WIRE_4.pr, _entries_T_55
node _entries_T_56 = bits(_entries_WIRE_5, 7, 7)
connect _entries_WIRE_4.px, _entries_T_56
node _entries_T_57 = bits(_entries_WIRE_5, 8, 8)
connect _entries_WIRE_4.pw, _entries_T_57
node _entries_T_58 = bits(_entries_WIRE_5, 9, 9)
connect _entries_WIRE_4.hr, _entries_T_58
node _entries_T_59 = bits(_entries_WIRE_5, 10, 10)
connect _entries_WIRE_4.hx, _entries_T_59
node _entries_T_60 = bits(_entries_WIRE_5, 11, 11)
connect _entries_WIRE_4.hw, _entries_T_60
node _entries_T_61 = bits(_entries_WIRE_5, 12, 12)
connect _entries_WIRE_4.sr, _entries_T_61
node _entries_T_62 = bits(_entries_WIRE_5, 13, 13)
connect _entries_WIRE_4.sx, _entries_T_62
node _entries_T_63 = bits(_entries_WIRE_5, 14, 14)
connect _entries_WIRE_4.sw, _entries_T_63
node _entries_T_64 = bits(_entries_WIRE_5, 15, 15)
connect _entries_WIRE_4.gf, _entries_T_64
node _entries_T_65 = bits(_entries_WIRE_5, 16, 16)
connect _entries_WIRE_4.pf, _entries_T_65
node _entries_T_66 = bits(_entries_WIRE_5, 17, 17)
connect _entries_WIRE_4.ae_stage2, _entries_T_66
node _entries_T_67 = bits(_entries_WIRE_5, 18, 18)
connect _entries_WIRE_4.ae_final, _entries_T_67
node _entries_T_68 = bits(_entries_WIRE_5, 19, 19)
connect _entries_WIRE_4.ae_ptw, _entries_T_68
node _entries_T_69 = bits(_entries_WIRE_5, 20, 20)
connect _entries_WIRE_4.g, _entries_T_69
node _entries_T_70 = bits(_entries_WIRE_5, 21, 21)
connect _entries_WIRE_4.u, _entries_T_70
node _entries_T_71 = bits(_entries_WIRE_5, 41, 22)
connect _entries_WIRE_4.ppn, _entries_T_71
inst entries_barrier_2 of OptimizationBarrier_TLBEntryData_45
connect entries_barrier_2.clock, clock
connect entries_barrier_2.reset, reset
connect entries_barrier_2.io.x.fragmented_superpage, _entries_WIRE_4.fragmented_superpage
connect entries_barrier_2.io.x.c, _entries_WIRE_4.c
connect entries_barrier_2.io.x.eff, _entries_WIRE_4.eff
connect entries_barrier_2.io.x.paa, _entries_WIRE_4.paa
connect entries_barrier_2.io.x.pal, _entries_WIRE_4.pal
connect entries_barrier_2.io.x.ppp, _entries_WIRE_4.ppp
connect entries_barrier_2.io.x.pr, _entries_WIRE_4.pr
connect entries_barrier_2.io.x.px, _entries_WIRE_4.px
connect entries_barrier_2.io.x.pw, _entries_WIRE_4.pw
connect entries_barrier_2.io.x.hr, _entries_WIRE_4.hr
connect entries_barrier_2.io.x.hx, _entries_WIRE_4.hx
connect entries_barrier_2.io.x.hw, _entries_WIRE_4.hw
connect entries_barrier_2.io.x.sr, _entries_WIRE_4.sr
connect entries_barrier_2.io.x.sx, _entries_WIRE_4.sx
connect entries_barrier_2.io.x.sw, _entries_WIRE_4.sw
connect entries_barrier_2.io.x.gf, _entries_WIRE_4.gf
connect entries_barrier_2.io.x.pf, _entries_WIRE_4.pf
connect entries_barrier_2.io.x.ae_stage2, _entries_WIRE_4.ae_stage2
connect entries_barrier_2.io.x.ae_final, _entries_WIRE_4.ae_final
connect entries_barrier_2.io.x.ae_ptw, _entries_WIRE_4.ae_ptw
connect entries_barrier_2.io.x.g, _entries_WIRE_4.g
connect entries_barrier_2.io.x.u, _entries_WIRE_4.u
connect entries_barrier_2.io.x.ppn, _entries_WIRE_4.ppn
node _entries_T_72 = bits(vpn, 1, 0)
wire _entries_WIRE_6 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_7 : UInt<42>
connect _entries_WIRE_7, sectored_entries[0][3].data[_entries_T_72]
node _entries_T_73 = bits(_entries_WIRE_7, 0, 0)
connect _entries_WIRE_6.fragmented_superpage, _entries_T_73
node _entries_T_74 = bits(_entries_WIRE_7, 1, 1)
connect _entries_WIRE_6.c, _entries_T_74
node _entries_T_75 = bits(_entries_WIRE_7, 2, 2)
connect _entries_WIRE_6.eff, _entries_T_75
node _entries_T_76 = bits(_entries_WIRE_7, 3, 3)
connect _entries_WIRE_6.paa, _entries_T_76
node _entries_T_77 = bits(_entries_WIRE_7, 4, 4)
connect _entries_WIRE_6.pal, _entries_T_77
node _entries_T_78 = bits(_entries_WIRE_7, 5, 5)
connect _entries_WIRE_6.ppp, _entries_T_78
node _entries_T_79 = bits(_entries_WIRE_7, 6, 6)
connect _entries_WIRE_6.pr, _entries_T_79
node _entries_T_80 = bits(_entries_WIRE_7, 7, 7)
connect _entries_WIRE_6.px, _entries_T_80
node _entries_T_81 = bits(_entries_WIRE_7, 8, 8)
connect _entries_WIRE_6.pw, _entries_T_81
node _entries_T_82 = bits(_entries_WIRE_7, 9, 9)
connect _entries_WIRE_6.hr, _entries_T_82
node _entries_T_83 = bits(_entries_WIRE_7, 10, 10)
connect _entries_WIRE_6.hx, _entries_T_83
node _entries_T_84 = bits(_entries_WIRE_7, 11, 11)
connect _entries_WIRE_6.hw, _entries_T_84
node _entries_T_85 = bits(_entries_WIRE_7, 12, 12)
connect _entries_WIRE_6.sr, _entries_T_85
node _entries_T_86 = bits(_entries_WIRE_7, 13, 13)
connect _entries_WIRE_6.sx, _entries_T_86
node _entries_T_87 = bits(_entries_WIRE_7, 14, 14)
connect _entries_WIRE_6.sw, _entries_T_87
node _entries_T_88 = bits(_entries_WIRE_7, 15, 15)
connect _entries_WIRE_6.gf, _entries_T_88
node _entries_T_89 = bits(_entries_WIRE_7, 16, 16)
connect _entries_WIRE_6.pf, _entries_T_89
node _entries_T_90 = bits(_entries_WIRE_7, 17, 17)
connect _entries_WIRE_6.ae_stage2, _entries_T_90
node _entries_T_91 = bits(_entries_WIRE_7, 18, 18)
connect _entries_WIRE_6.ae_final, _entries_T_91
node _entries_T_92 = bits(_entries_WIRE_7, 19, 19)
connect _entries_WIRE_6.ae_ptw, _entries_T_92
node _entries_T_93 = bits(_entries_WIRE_7, 20, 20)
connect _entries_WIRE_6.g, _entries_T_93
node _entries_T_94 = bits(_entries_WIRE_7, 21, 21)
connect _entries_WIRE_6.u, _entries_T_94
node _entries_T_95 = bits(_entries_WIRE_7, 41, 22)
connect _entries_WIRE_6.ppn, _entries_T_95
inst entries_barrier_3 of OptimizationBarrier_TLBEntryData_46
connect entries_barrier_3.clock, clock
connect entries_barrier_3.reset, reset
connect entries_barrier_3.io.x.fragmented_superpage, _entries_WIRE_6.fragmented_superpage
connect entries_barrier_3.io.x.c, _entries_WIRE_6.c
connect entries_barrier_3.io.x.eff, _entries_WIRE_6.eff
connect entries_barrier_3.io.x.paa, _entries_WIRE_6.paa
connect entries_barrier_3.io.x.pal, _entries_WIRE_6.pal
connect entries_barrier_3.io.x.ppp, _entries_WIRE_6.ppp
connect entries_barrier_3.io.x.pr, _entries_WIRE_6.pr
connect entries_barrier_3.io.x.px, _entries_WIRE_6.px
connect entries_barrier_3.io.x.pw, _entries_WIRE_6.pw
connect entries_barrier_3.io.x.hr, _entries_WIRE_6.hr
connect entries_barrier_3.io.x.hx, _entries_WIRE_6.hx
connect entries_barrier_3.io.x.hw, _entries_WIRE_6.hw
connect entries_barrier_3.io.x.sr, _entries_WIRE_6.sr
connect entries_barrier_3.io.x.sx, _entries_WIRE_6.sx
connect entries_barrier_3.io.x.sw, _entries_WIRE_6.sw
connect entries_barrier_3.io.x.gf, _entries_WIRE_6.gf
connect entries_barrier_3.io.x.pf, _entries_WIRE_6.pf
connect entries_barrier_3.io.x.ae_stage2, _entries_WIRE_6.ae_stage2
connect entries_barrier_3.io.x.ae_final, _entries_WIRE_6.ae_final
connect entries_barrier_3.io.x.ae_ptw, _entries_WIRE_6.ae_ptw
connect entries_barrier_3.io.x.g, _entries_WIRE_6.g
connect entries_barrier_3.io.x.u, _entries_WIRE_6.u
connect entries_barrier_3.io.x.ppn, _entries_WIRE_6.ppn
node _entries_T_96 = bits(vpn, 1, 0)
wire _entries_WIRE_8 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_9 : UInt<42>
connect _entries_WIRE_9, sectored_entries[0][4].data[_entries_T_96]
node _entries_T_97 = bits(_entries_WIRE_9, 0, 0)
connect _entries_WIRE_8.fragmented_superpage, _entries_T_97
node _entries_T_98 = bits(_entries_WIRE_9, 1, 1)
connect _entries_WIRE_8.c, _entries_T_98
node _entries_T_99 = bits(_entries_WIRE_9, 2, 2)
connect _entries_WIRE_8.eff, _entries_T_99
node _entries_T_100 = bits(_entries_WIRE_9, 3, 3)
connect _entries_WIRE_8.paa, _entries_T_100
node _entries_T_101 = bits(_entries_WIRE_9, 4, 4)
connect _entries_WIRE_8.pal, _entries_T_101
node _entries_T_102 = bits(_entries_WIRE_9, 5, 5)
connect _entries_WIRE_8.ppp, _entries_T_102
node _entries_T_103 = bits(_entries_WIRE_9, 6, 6)
connect _entries_WIRE_8.pr, _entries_T_103
node _entries_T_104 = bits(_entries_WIRE_9, 7, 7)
connect _entries_WIRE_8.px, _entries_T_104
node _entries_T_105 = bits(_entries_WIRE_9, 8, 8)
connect _entries_WIRE_8.pw, _entries_T_105
node _entries_T_106 = bits(_entries_WIRE_9, 9, 9)
connect _entries_WIRE_8.hr, _entries_T_106
node _entries_T_107 = bits(_entries_WIRE_9, 10, 10)
connect _entries_WIRE_8.hx, _entries_T_107
node _entries_T_108 = bits(_entries_WIRE_9, 11, 11)
connect _entries_WIRE_8.hw, _entries_T_108
node _entries_T_109 = bits(_entries_WIRE_9, 12, 12)
connect _entries_WIRE_8.sr, _entries_T_109
node _entries_T_110 = bits(_entries_WIRE_9, 13, 13)
connect _entries_WIRE_8.sx, _entries_T_110
node _entries_T_111 = bits(_entries_WIRE_9, 14, 14)
connect _entries_WIRE_8.sw, _entries_T_111
node _entries_T_112 = bits(_entries_WIRE_9, 15, 15)
connect _entries_WIRE_8.gf, _entries_T_112
node _entries_T_113 = bits(_entries_WIRE_9, 16, 16)
connect _entries_WIRE_8.pf, _entries_T_113
node _entries_T_114 = bits(_entries_WIRE_9, 17, 17)
connect _entries_WIRE_8.ae_stage2, _entries_T_114
node _entries_T_115 = bits(_entries_WIRE_9, 18, 18)
connect _entries_WIRE_8.ae_final, _entries_T_115
node _entries_T_116 = bits(_entries_WIRE_9, 19, 19)
connect _entries_WIRE_8.ae_ptw, _entries_T_116
node _entries_T_117 = bits(_entries_WIRE_9, 20, 20)
connect _entries_WIRE_8.g, _entries_T_117
node _entries_T_118 = bits(_entries_WIRE_9, 21, 21)
connect _entries_WIRE_8.u, _entries_T_118
node _entries_T_119 = bits(_entries_WIRE_9, 41, 22)
connect _entries_WIRE_8.ppn, _entries_T_119
inst entries_barrier_4 of OptimizationBarrier_TLBEntryData_47
connect entries_barrier_4.clock, clock
connect entries_barrier_4.reset, reset
connect entries_barrier_4.io.x.fragmented_superpage, _entries_WIRE_8.fragmented_superpage
connect entries_barrier_4.io.x.c, _entries_WIRE_8.c
connect entries_barrier_4.io.x.eff, _entries_WIRE_8.eff
connect entries_barrier_4.io.x.paa, _entries_WIRE_8.paa
connect entries_barrier_4.io.x.pal, _entries_WIRE_8.pal
connect entries_barrier_4.io.x.ppp, _entries_WIRE_8.ppp
connect entries_barrier_4.io.x.pr, _entries_WIRE_8.pr
connect entries_barrier_4.io.x.px, _entries_WIRE_8.px
connect entries_barrier_4.io.x.pw, _entries_WIRE_8.pw
connect entries_barrier_4.io.x.hr, _entries_WIRE_8.hr
connect entries_barrier_4.io.x.hx, _entries_WIRE_8.hx
connect entries_barrier_4.io.x.hw, _entries_WIRE_8.hw
connect entries_barrier_4.io.x.sr, _entries_WIRE_8.sr
connect entries_barrier_4.io.x.sx, _entries_WIRE_8.sx
connect entries_barrier_4.io.x.sw, _entries_WIRE_8.sw
connect entries_barrier_4.io.x.gf, _entries_WIRE_8.gf
connect entries_barrier_4.io.x.pf, _entries_WIRE_8.pf
connect entries_barrier_4.io.x.ae_stage2, _entries_WIRE_8.ae_stage2
connect entries_barrier_4.io.x.ae_final, _entries_WIRE_8.ae_final
connect entries_barrier_4.io.x.ae_ptw, _entries_WIRE_8.ae_ptw
connect entries_barrier_4.io.x.g, _entries_WIRE_8.g
connect entries_barrier_4.io.x.u, _entries_WIRE_8.u
connect entries_barrier_4.io.x.ppn, _entries_WIRE_8.ppn
node _entries_T_120 = bits(vpn, 1, 0)
wire _entries_WIRE_10 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_11 : UInt<42>
connect _entries_WIRE_11, sectored_entries[0][5].data[_entries_T_120]
node _entries_T_121 = bits(_entries_WIRE_11, 0, 0)
connect _entries_WIRE_10.fragmented_superpage, _entries_T_121
node _entries_T_122 = bits(_entries_WIRE_11, 1, 1)
connect _entries_WIRE_10.c, _entries_T_122
node _entries_T_123 = bits(_entries_WIRE_11, 2, 2)
connect _entries_WIRE_10.eff, _entries_T_123
node _entries_T_124 = bits(_entries_WIRE_11, 3, 3)
connect _entries_WIRE_10.paa, _entries_T_124
node _entries_T_125 = bits(_entries_WIRE_11, 4, 4)
connect _entries_WIRE_10.pal, _entries_T_125
node _entries_T_126 = bits(_entries_WIRE_11, 5, 5)
connect _entries_WIRE_10.ppp, _entries_T_126
node _entries_T_127 = bits(_entries_WIRE_11, 6, 6)
connect _entries_WIRE_10.pr, _entries_T_127
node _entries_T_128 = bits(_entries_WIRE_11, 7, 7)
connect _entries_WIRE_10.px, _entries_T_128
node _entries_T_129 = bits(_entries_WIRE_11, 8, 8)
connect _entries_WIRE_10.pw, _entries_T_129
node _entries_T_130 = bits(_entries_WIRE_11, 9, 9)
connect _entries_WIRE_10.hr, _entries_T_130
node _entries_T_131 = bits(_entries_WIRE_11, 10, 10)
connect _entries_WIRE_10.hx, _entries_T_131
node _entries_T_132 = bits(_entries_WIRE_11, 11, 11)
connect _entries_WIRE_10.hw, _entries_T_132
node _entries_T_133 = bits(_entries_WIRE_11, 12, 12)
connect _entries_WIRE_10.sr, _entries_T_133
node _entries_T_134 = bits(_entries_WIRE_11, 13, 13)
connect _entries_WIRE_10.sx, _entries_T_134
node _entries_T_135 = bits(_entries_WIRE_11, 14, 14)
connect _entries_WIRE_10.sw, _entries_T_135
node _entries_T_136 = bits(_entries_WIRE_11, 15, 15)
connect _entries_WIRE_10.gf, _entries_T_136
node _entries_T_137 = bits(_entries_WIRE_11, 16, 16)
connect _entries_WIRE_10.pf, _entries_T_137
node _entries_T_138 = bits(_entries_WIRE_11, 17, 17)
connect _entries_WIRE_10.ae_stage2, _entries_T_138
node _entries_T_139 = bits(_entries_WIRE_11, 18, 18)
connect _entries_WIRE_10.ae_final, _entries_T_139
node _entries_T_140 = bits(_entries_WIRE_11, 19, 19)
connect _entries_WIRE_10.ae_ptw, _entries_T_140
node _entries_T_141 = bits(_entries_WIRE_11, 20, 20)
connect _entries_WIRE_10.g, _entries_T_141
node _entries_T_142 = bits(_entries_WIRE_11, 21, 21)
connect _entries_WIRE_10.u, _entries_T_142
node _entries_T_143 = bits(_entries_WIRE_11, 41, 22)
connect _entries_WIRE_10.ppn, _entries_T_143
inst entries_barrier_5 of OptimizationBarrier_TLBEntryData_48
connect entries_barrier_5.clock, clock
connect entries_barrier_5.reset, reset
connect entries_barrier_5.io.x.fragmented_superpage, _entries_WIRE_10.fragmented_superpage
connect entries_barrier_5.io.x.c, _entries_WIRE_10.c
connect entries_barrier_5.io.x.eff, _entries_WIRE_10.eff
connect entries_barrier_5.io.x.paa, _entries_WIRE_10.paa
connect entries_barrier_5.io.x.pal, _entries_WIRE_10.pal
connect entries_barrier_5.io.x.ppp, _entries_WIRE_10.ppp
connect entries_barrier_5.io.x.pr, _entries_WIRE_10.pr
connect entries_barrier_5.io.x.px, _entries_WIRE_10.px
connect entries_barrier_5.io.x.pw, _entries_WIRE_10.pw
connect entries_barrier_5.io.x.hr, _entries_WIRE_10.hr
connect entries_barrier_5.io.x.hx, _entries_WIRE_10.hx
connect entries_barrier_5.io.x.hw, _entries_WIRE_10.hw
connect entries_barrier_5.io.x.sr, _entries_WIRE_10.sr
connect entries_barrier_5.io.x.sx, _entries_WIRE_10.sx
connect entries_barrier_5.io.x.sw, _entries_WIRE_10.sw
connect entries_barrier_5.io.x.gf, _entries_WIRE_10.gf
connect entries_barrier_5.io.x.pf, _entries_WIRE_10.pf
connect entries_barrier_5.io.x.ae_stage2, _entries_WIRE_10.ae_stage2
connect entries_barrier_5.io.x.ae_final, _entries_WIRE_10.ae_final
connect entries_barrier_5.io.x.ae_ptw, _entries_WIRE_10.ae_ptw
connect entries_barrier_5.io.x.g, _entries_WIRE_10.g
connect entries_barrier_5.io.x.u, _entries_WIRE_10.u
connect entries_barrier_5.io.x.ppn, _entries_WIRE_10.ppn
node _entries_T_144 = bits(vpn, 1, 0)
wire _entries_WIRE_12 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_13 : UInt<42>
connect _entries_WIRE_13, sectored_entries[0][6].data[_entries_T_144]
node _entries_T_145 = bits(_entries_WIRE_13, 0, 0)
connect _entries_WIRE_12.fragmented_superpage, _entries_T_145
node _entries_T_146 = bits(_entries_WIRE_13, 1, 1)
connect _entries_WIRE_12.c, _entries_T_146
node _entries_T_147 = bits(_entries_WIRE_13, 2, 2)
connect _entries_WIRE_12.eff, _entries_T_147
node _entries_T_148 = bits(_entries_WIRE_13, 3, 3)
connect _entries_WIRE_12.paa, _entries_T_148
node _entries_T_149 = bits(_entries_WIRE_13, 4, 4)
connect _entries_WIRE_12.pal, _entries_T_149
node _entries_T_150 = bits(_entries_WIRE_13, 5, 5)
connect _entries_WIRE_12.ppp, _entries_T_150
node _entries_T_151 = bits(_entries_WIRE_13, 6, 6)
connect _entries_WIRE_12.pr, _entries_T_151
node _entries_T_152 = bits(_entries_WIRE_13, 7, 7)
connect _entries_WIRE_12.px, _entries_T_152
node _entries_T_153 = bits(_entries_WIRE_13, 8, 8)
connect _entries_WIRE_12.pw, _entries_T_153
node _entries_T_154 = bits(_entries_WIRE_13, 9, 9)
connect _entries_WIRE_12.hr, _entries_T_154
node _entries_T_155 = bits(_entries_WIRE_13, 10, 10)
connect _entries_WIRE_12.hx, _entries_T_155
node _entries_T_156 = bits(_entries_WIRE_13, 11, 11)
connect _entries_WIRE_12.hw, _entries_T_156
node _entries_T_157 = bits(_entries_WIRE_13, 12, 12)
connect _entries_WIRE_12.sr, _entries_T_157
node _entries_T_158 = bits(_entries_WIRE_13, 13, 13)
connect _entries_WIRE_12.sx, _entries_T_158
node _entries_T_159 = bits(_entries_WIRE_13, 14, 14)
connect _entries_WIRE_12.sw, _entries_T_159
node _entries_T_160 = bits(_entries_WIRE_13, 15, 15)
connect _entries_WIRE_12.gf, _entries_T_160
node _entries_T_161 = bits(_entries_WIRE_13, 16, 16)
connect _entries_WIRE_12.pf, _entries_T_161
node _entries_T_162 = bits(_entries_WIRE_13, 17, 17)
connect _entries_WIRE_12.ae_stage2, _entries_T_162
node _entries_T_163 = bits(_entries_WIRE_13, 18, 18)
connect _entries_WIRE_12.ae_final, _entries_T_163
node _entries_T_164 = bits(_entries_WIRE_13, 19, 19)
connect _entries_WIRE_12.ae_ptw, _entries_T_164
node _entries_T_165 = bits(_entries_WIRE_13, 20, 20)
connect _entries_WIRE_12.g, _entries_T_165
node _entries_T_166 = bits(_entries_WIRE_13, 21, 21)
connect _entries_WIRE_12.u, _entries_T_166
node _entries_T_167 = bits(_entries_WIRE_13, 41, 22)
connect _entries_WIRE_12.ppn, _entries_T_167
inst entries_barrier_6 of OptimizationBarrier_TLBEntryData_49
connect entries_barrier_6.clock, clock
connect entries_barrier_6.reset, reset
connect entries_barrier_6.io.x.fragmented_superpage, _entries_WIRE_12.fragmented_superpage
connect entries_barrier_6.io.x.c, _entries_WIRE_12.c
connect entries_barrier_6.io.x.eff, _entries_WIRE_12.eff
connect entries_barrier_6.io.x.paa, _entries_WIRE_12.paa
connect entries_barrier_6.io.x.pal, _entries_WIRE_12.pal
connect entries_barrier_6.io.x.ppp, _entries_WIRE_12.ppp
connect entries_barrier_6.io.x.pr, _entries_WIRE_12.pr
connect entries_barrier_6.io.x.px, _entries_WIRE_12.px
connect entries_barrier_6.io.x.pw, _entries_WIRE_12.pw
connect entries_barrier_6.io.x.hr, _entries_WIRE_12.hr
connect entries_barrier_6.io.x.hx, _entries_WIRE_12.hx
connect entries_barrier_6.io.x.hw, _entries_WIRE_12.hw
connect entries_barrier_6.io.x.sr, _entries_WIRE_12.sr
connect entries_barrier_6.io.x.sx, _entries_WIRE_12.sx
connect entries_barrier_6.io.x.sw, _entries_WIRE_12.sw
connect entries_barrier_6.io.x.gf, _entries_WIRE_12.gf
connect entries_barrier_6.io.x.pf, _entries_WIRE_12.pf
connect entries_barrier_6.io.x.ae_stage2, _entries_WIRE_12.ae_stage2
connect entries_barrier_6.io.x.ae_final, _entries_WIRE_12.ae_final
connect entries_barrier_6.io.x.ae_ptw, _entries_WIRE_12.ae_ptw
connect entries_barrier_6.io.x.g, _entries_WIRE_12.g
connect entries_barrier_6.io.x.u, _entries_WIRE_12.u
connect entries_barrier_6.io.x.ppn, _entries_WIRE_12.ppn
node _entries_T_168 = bits(vpn, 1, 0)
wire _entries_WIRE_14 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_15 : UInt<42>
connect _entries_WIRE_15, sectored_entries[0][7].data[_entries_T_168]
node _entries_T_169 = bits(_entries_WIRE_15, 0, 0)
connect _entries_WIRE_14.fragmented_superpage, _entries_T_169
node _entries_T_170 = bits(_entries_WIRE_15, 1, 1)
connect _entries_WIRE_14.c, _entries_T_170
node _entries_T_171 = bits(_entries_WIRE_15, 2, 2)
connect _entries_WIRE_14.eff, _entries_T_171
node _entries_T_172 = bits(_entries_WIRE_15, 3, 3)
connect _entries_WIRE_14.paa, _entries_T_172
node _entries_T_173 = bits(_entries_WIRE_15, 4, 4)
connect _entries_WIRE_14.pal, _entries_T_173
node _entries_T_174 = bits(_entries_WIRE_15, 5, 5)
connect _entries_WIRE_14.ppp, _entries_T_174
node _entries_T_175 = bits(_entries_WIRE_15, 6, 6)
connect _entries_WIRE_14.pr, _entries_T_175
node _entries_T_176 = bits(_entries_WIRE_15, 7, 7)
connect _entries_WIRE_14.px, _entries_T_176
node _entries_T_177 = bits(_entries_WIRE_15, 8, 8)
connect _entries_WIRE_14.pw, _entries_T_177
node _entries_T_178 = bits(_entries_WIRE_15, 9, 9)
connect _entries_WIRE_14.hr, _entries_T_178
node _entries_T_179 = bits(_entries_WIRE_15, 10, 10)
connect _entries_WIRE_14.hx, _entries_T_179
node _entries_T_180 = bits(_entries_WIRE_15, 11, 11)
connect _entries_WIRE_14.hw, _entries_T_180
node _entries_T_181 = bits(_entries_WIRE_15, 12, 12)
connect _entries_WIRE_14.sr, _entries_T_181
node _entries_T_182 = bits(_entries_WIRE_15, 13, 13)
connect _entries_WIRE_14.sx, _entries_T_182
node _entries_T_183 = bits(_entries_WIRE_15, 14, 14)
connect _entries_WIRE_14.sw, _entries_T_183
node _entries_T_184 = bits(_entries_WIRE_15, 15, 15)
connect _entries_WIRE_14.gf, _entries_T_184
node _entries_T_185 = bits(_entries_WIRE_15, 16, 16)
connect _entries_WIRE_14.pf, _entries_T_185
node _entries_T_186 = bits(_entries_WIRE_15, 17, 17)
connect _entries_WIRE_14.ae_stage2, _entries_T_186
node _entries_T_187 = bits(_entries_WIRE_15, 18, 18)
connect _entries_WIRE_14.ae_final, _entries_T_187
node _entries_T_188 = bits(_entries_WIRE_15, 19, 19)
connect _entries_WIRE_14.ae_ptw, _entries_T_188
node _entries_T_189 = bits(_entries_WIRE_15, 20, 20)
connect _entries_WIRE_14.g, _entries_T_189
node _entries_T_190 = bits(_entries_WIRE_15, 21, 21)
connect _entries_WIRE_14.u, _entries_T_190
node _entries_T_191 = bits(_entries_WIRE_15, 41, 22)
connect _entries_WIRE_14.ppn, _entries_T_191
inst entries_barrier_7 of OptimizationBarrier_TLBEntryData_50
connect entries_barrier_7.clock, clock
connect entries_barrier_7.reset, reset
connect entries_barrier_7.io.x.fragmented_superpage, _entries_WIRE_14.fragmented_superpage
connect entries_barrier_7.io.x.c, _entries_WIRE_14.c
connect entries_barrier_7.io.x.eff, _entries_WIRE_14.eff
connect entries_barrier_7.io.x.paa, _entries_WIRE_14.paa
connect entries_barrier_7.io.x.pal, _entries_WIRE_14.pal
connect entries_barrier_7.io.x.ppp, _entries_WIRE_14.ppp
connect entries_barrier_7.io.x.pr, _entries_WIRE_14.pr
connect entries_barrier_7.io.x.px, _entries_WIRE_14.px
connect entries_barrier_7.io.x.pw, _entries_WIRE_14.pw
connect entries_barrier_7.io.x.hr, _entries_WIRE_14.hr
connect entries_barrier_7.io.x.hx, _entries_WIRE_14.hx
connect entries_barrier_7.io.x.hw, _entries_WIRE_14.hw
connect entries_barrier_7.io.x.sr, _entries_WIRE_14.sr
connect entries_barrier_7.io.x.sx, _entries_WIRE_14.sx
connect entries_barrier_7.io.x.sw, _entries_WIRE_14.sw
connect entries_barrier_7.io.x.gf, _entries_WIRE_14.gf
connect entries_barrier_7.io.x.pf, _entries_WIRE_14.pf
connect entries_barrier_7.io.x.ae_stage2, _entries_WIRE_14.ae_stage2
connect entries_barrier_7.io.x.ae_final, _entries_WIRE_14.ae_final
connect entries_barrier_7.io.x.ae_ptw, _entries_WIRE_14.ae_ptw
connect entries_barrier_7.io.x.g, _entries_WIRE_14.g
connect entries_barrier_7.io.x.u, _entries_WIRE_14.u
connect entries_barrier_7.io.x.ppn, _entries_WIRE_14.ppn
wire _entries_WIRE_16 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_17 : UInt<42>
connect _entries_WIRE_17, superpage_entries[0].data[0]
node _entries_T_192 = bits(_entries_WIRE_17, 0, 0)
connect _entries_WIRE_16.fragmented_superpage, _entries_T_192
node _entries_T_193 = bits(_entries_WIRE_17, 1, 1)
connect _entries_WIRE_16.c, _entries_T_193
node _entries_T_194 = bits(_entries_WIRE_17, 2, 2)
connect _entries_WIRE_16.eff, _entries_T_194
node _entries_T_195 = bits(_entries_WIRE_17, 3, 3)
connect _entries_WIRE_16.paa, _entries_T_195
node _entries_T_196 = bits(_entries_WIRE_17, 4, 4)
connect _entries_WIRE_16.pal, _entries_T_196
node _entries_T_197 = bits(_entries_WIRE_17, 5, 5)
connect _entries_WIRE_16.ppp, _entries_T_197
node _entries_T_198 = bits(_entries_WIRE_17, 6, 6)
connect _entries_WIRE_16.pr, _entries_T_198
node _entries_T_199 = bits(_entries_WIRE_17, 7, 7)
connect _entries_WIRE_16.px, _entries_T_199
node _entries_T_200 = bits(_entries_WIRE_17, 8, 8)
connect _entries_WIRE_16.pw, _entries_T_200
node _entries_T_201 = bits(_entries_WIRE_17, 9, 9)
connect _entries_WIRE_16.hr, _entries_T_201
node _entries_T_202 = bits(_entries_WIRE_17, 10, 10)
connect _entries_WIRE_16.hx, _entries_T_202
node _entries_T_203 = bits(_entries_WIRE_17, 11, 11)
connect _entries_WIRE_16.hw, _entries_T_203
node _entries_T_204 = bits(_entries_WIRE_17, 12, 12)
connect _entries_WIRE_16.sr, _entries_T_204
node _entries_T_205 = bits(_entries_WIRE_17, 13, 13)
connect _entries_WIRE_16.sx, _entries_T_205
node _entries_T_206 = bits(_entries_WIRE_17, 14, 14)
connect _entries_WIRE_16.sw, _entries_T_206
node _entries_T_207 = bits(_entries_WIRE_17, 15, 15)
connect _entries_WIRE_16.gf, _entries_T_207
node _entries_T_208 = bits(_entries_WIRE_17, 16, 16)
connect _entries_WIRE_16.pf, _entries_T_208
node _entries_T_209 = bits(_entries_WIRE_17, 17, 17)
connect _entries_WIRE_16.ae_stage2, _entries_T_209
node _entries_T_210 = bits(_entries_WIRE_17, 18, 18)
connect _entries_WIRE_16.ae_final, _entries_T_210
node _entries_T_211 = bits(_entries_WIRE_17, 19, 19)
connect _entries_WIRE_16.ae_ptw, _entries_T_211
node _entries_T_212 = bits(_entries_WIRE_17, 20, 20)
connect _entries_WIRE_16.g, _entries_T_212
node _entries_T_213 = bits(_entries_WIRE_17, 21, 21)
connect _entries_WIRE_16.u, _entries_T_213
node _entries_T_214 = bits(_entries_WIRE_17, 41, 22)
connect _entries_WIRE_16.ppn, _entries_T_214
inst entries_barrier_8 of OptimizationBarrier_TLBEntryData_51
connect entries_barrier_8.clock, clock
connect entries_barrier_8.reset, reset
connect entries_barrier_8.io.x.fragmented_superpage, _entries_WIRE_16.fragmented_superpage
connect entries_barrier_8.io.x.c, _entries_WIRE_16.c
connect entries_barrier_8.io.x.eff, _entries_WIRE_16.eff
connect entries_barrier_8.io.x.paa, _entries_WIRE_16.paa
connect entries_barrier_8.io.x.pal, _entries_WIRE_16.pal
connect entries_barrier_8.io.x.ppp, _entries_WIRE_16.ppp
connect entries_barrier_8.io.x.pr, _entries_WIRE_16.pr
connect entries_barrier_8.io.x.px, _entries_WIRE_16.px
connect entries_barrier_8.io.x.pw, _entries_WIRE_16.pw
connect entries_barrier_8.io.x.hr, _entries_WIRE_16.hr
connect entries_barrier_8.io.x.hx, _entries_WIRE_16.hx
connect entries_barrier_8.io.x.hw, _entries_WIRE_16.hw
connect entries_barrier_8.io.x.sr, _entries_WIRE_16.sr
connect entries_barrier_8.io.x.sx, _entries_WIRE_16.sx
connect entries_barrier_8.io.x.sw, _entries_WIRE_16.sw
connect entries_barrier_8.io.x.gf, _entries_WIRE_16.gf
connect entries_barrier_8.io.x.pf, _entries_WIRE_16.pf
connect entries_barrier_8.io.x.ae_stage2, _entries_WIRE_16.ae_stage2
connect entries_barrier_8.io.x.ae_final, _entries_WIRE_16.ae_final
connect entries_barrier_8.io.x.ae_ptw, _entries_WIRE_16.ae_ptw
connect entries_barrier_8.io.x.g, _entries_WIRE_16.g
connect entries_barrier_8.io.x.u, _entries_WIRE_16.u
connect entries_barrier_8.io.x.ppn, _entries_WIRE_16.ppn
wire _entries_WIRE_18 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_19 : UInt<42>
connect _entries_WIRE_19, superpage_entries[1].data[0]
node _entries_T_215 = bits(_entries_WIRE_19, 0, 0)
connect _entries_WIRE_18.fragmented_superpage, _entries_T_215
node _entries_T_216 = bits(_entries_WIRE_19, 1, 1)
connect _entries_WIRE_18.c, _entries_T_216
node _entries_T_217 = bits(_entries_WIRE_19, 2, 2)
connect _entries_WIRE_18.eff, _entries_T_217
node _entries_T_218 = bits(_entries_WIRE_19, 3, 3)
connect _entries_WIRE_18.paa, _entries_T_218
node _entries_T_219 = bits(_entries_WIRE_19, 4, 4)
connect _entries_WIRE_18.pal, _entries_T_219
node _entries_T_220 = bits(_entries_WIRE_19, 5, 5)
connect _entries_WIRE_18.ppp, _entries_T_220
node _entries_T_221 = bits(_entries_WIRE_19, 6, 6)
connect _entries_WIRE_18.pr, _entries_T_221
node _entries_T_222 = bits(_entries_WIRE_19, 7, 7)
connect _entries_WIRE_18.px, _entries_T_222
node _entries_T_223 = bits(_entries_WIRE_19, 8, 8)
connect _entries_WIRE_18.pw, _entries_T_223
node _entries_T_224 = bits(_entries_WIRE_19, 9, 9)
connect _entries_WIRE_18.hr, _entries_T_224
node _entries_T_225 = bits(_entries_WIRE_19, 10, 10)
connect _entries_WIRE_18.hx, _entries_T_225
node _entries_T_226 = bits(_entries_WIRE_19, 11, 11)
connect _entries_WIRE_18.hw, _entries_T_226
node _entries_T_227 = bits(_entries_WIRE_19, 12, 12)
connect _entries_WIRE_18.sr, _entries_T_227
node _entries_T_228 = bits(_entries_WIRE_19, 13, 13)
connect _entries_WIRE_18.sx, _entries_T_228
node _entries_T_229 = bits(_entries_WIRE_19, 14, 14)
connect _entries_WIRE_18.sw, _entries_T_229
node _entries_T_230 = bits(_entries_WIRE_19, 15, 15)
connect _entries_WIRE_18.gf, _entries_T_230
node _entries_T_231 = bits(_entries_WIRE_19, 16, 16)
connect _entries_WIRE_18.pf, _entries_T_231
node _entries_T_232 = bits(_entries_WIRE_19, 17, 17)
connect _entries_WIRE_18.ae_stage2, _entries_T_232
node _entries_T_233 = bits(_entries_WIRE_19, 18, 18)
connect _entries_WIRE_18.ae_final, _entries_T_233
node _entries_T_234 = bits(_entries_WIRE_19, 19, 19)
connect _entries_WIRE_18.ae_ptw, _entries_T_234
node _entries_T_235 = bits(_entries_WIRE_19, 20, 20)
connect _entries_WIRE_18.g, _entries_T_235
node _entries_T_236 = bits(_entries_WIRE_19, 21, 21)
connect _entries_WIRE_18.u, _entries_T_236
node _entries_T_237 = bits(_entries_WIRE_19, 41, 22)
connect _entries_WIRE_18.ppn, _entries_T_237
inst entries_barrier_9 of OptimizationBarrier_TLBEntryData_52
connect entries_barrier_9.clock, clock
connect entries_barrier_9.reset, reset
connect entries_barrier_9.io.x.fragmented_superpage, _entries_WIRE_18.fragmented_superpage
connect entries_barrier_9.io.x.c, _entries_WIRE_18.c
connect entries_barrier_9.io.x.eff, _entries_WIRE_18.eff
connect entries_barrier_9.io.x.paa, _entries_WIRE_18.paa
connect entries_barrier_9.io.x.pal, _entries_WIRE_18.pal
connect entries_barrier_9.io.x.ppp, _entries_WIRE_18.ppp
connect entries_barrier_9.io.x.pr, _entries_WIRE_18.pr
connect entries_barrier_9.io.x.px, _entries_WIRE_18.px
connect entries_barrier_9.io.x.pw, _entries_WIRE_18.pw
connect entries_barrier_9.io.x.hr, _entries_WIRE_18.hr
connect entries_barrier_9.io.x.hx, _entries_WIRE_18.hx
connect entries_barrier_9.io.x.hw, _entries_WIRE_18.hw
connect entries_barrier_9.io.x.sr, _entries_WIRE_18.sr
connect entries_barrier_9.io.x.sx, _entries_WIRE_18.sx
connect entries_barrier_9.io.x.sw, _entries_WIRE_18.sw
connect entries_barrier_9.io.x.gf, _entries_WIRE_18.gf
connect entries_barrier_9.io.x.pf, _entries_WIRE_18.pf
connect entries_barrier_9.io.x.ae_stage2, _entries_WIRE_18.ae_stage2
connect entries_barrier_9.io.x.ae_final, _entries_WIRE_18.ae_final
connect entries_barrier_9.io.x.ae_ptw, _entries_WIRE_18.ae_ptw
connect entries_barrier_9.io.x.g, _entries_WIRE_18.g
connect entries_barrier_9.io.x.u, _entries_WIRE_18.u
connect entries_barrier_9.io.x.ppn, _entries_WIRE_18.ppn
wire _entries_WIRE_20 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_21 : UInt<42>
connect _entries_WIRE_21, superpage_entries[2].data[0]
node _entries_T_238 = bits(_entries_WIRE_21, 0, 0)
connect _entries_WIRE_20.fragmented_superpage, _entries_T_238
node _entries_T_239 = bits(_entries_WIRE_21, 1, 1)
connect _entries_WIRE_20.c, _entries_T_239
node _entries_T_240 = bits(_entries_WIRE_21, 2, 2)
connect _entries_WIRE_20.eff, _entries_T_240
node _entries_T_241 = bits(_entries_WIRE_21, 3, 3)
connect _entries_WIRE_20.paa, _entries_T_241
node _entries_T_242 = bits(_entries_WIRE_21, 4, 4)
connect _entries_WIRE_20.pal, _entries_T_242
node _entries_T_243 = bits(_entries_WIRE_21, 5, 5)
connect _entries_WIRE_20.ppp, _entries_T_243
node _entries_T_244 = bits(_entries_WIRE_21, 6, 6)
connect _entries_WIRE_20.pr, _entries_T_244
node _entries_T_245 = bits(_entries_WIRE_21, 7, 7)
connect _entries_WIRE_20.px, _entries_T_245
node _entries_T_246 = bits(_entries_WIRE_21, 8, 8)
connect _entries_WIRE_20.pw, _entries_T_246
node _entries_T_247 = bits(_entries_WIRE_21, 9, 9)
connect _entries_WIRE_20.hr, _entries_T_247
node _entries_T_248 = bits(_entries_WIRE_21, 10, 10)
connect _entries_WIRE_20.hx, _entries_T_248
node _entries_T_249 = bits(_entries_WIRE_21, 11, 11)
connect _entries_WIRE_20.hw, _entries_T_249
node _entries_T_250 = bits(_entries_WIRE_21, 12, 12)
connect _entries_WIRE_20.sr, _entries_T_250
node _entries_T_251 = bits(_entries_WIRE_21, 13, 13)
connect _entries_WIRE_20.sx, _entries_T_251
node _entries_T_252 = bits(_entries_WIRE_21, 14, 14)
connect _entries_WIRE_20.sw, _entries_T_252
node _entries_T_253 = bits(_entries_WIRE_21, 15, 15)
connect _entries_WIRE_20.gf, _entries_T_253
node _entries_T_254 = bits(_entries_WIRE_21, 16, 16)
connect _entries_WIRE_20.pf, _entries_T_254
node _entries_T_255 = bits(_entries_WIRE_21, 17, 17)
connect _entries_WIRE_20.ae_stage2, _entries_T_255
node _entries_T_256 = bits(_entries_WIRE_21, 18, 18)
connect _entries_WIRE_20.ae_final, _entries_T_256
node _entries_T_257 = bits(_entries_WIRE_21, 19, 19)
connect _entries_WIRE_20.ae_ptw, _entries_T_257
node _entries_T_258 = bits(_entries_WIRE_21, 20, 20)
connect _entries_WIRE_20.g, _entries_T_258
node _entries_T_259 = bits(_entries_WIRE_21, 21, 21)
connect _entries_WIRE_20.u, _entries_T_259
node _entries_T_260 = bits(_entries_WIRE_21, 41, 22)
connect _entries_WIRE_20.ppn, _entries_T_260
inst entries_barrier_10 of OptimizationBarrier_TLBEntryData_53
connect entries_barrier_10.clock, clock
connect entries_barrier_10.reset, reset
connect entries_barrier_10.io.x.fragmented_superpage, _entries_WIRE_20.fragmented_superpage
connect entries_barrier_10.io.x.c, _entries_WIRE_20.c
connect entries_barrier_10.io.x.eff, _entries_WIRE_20.eff
connect entries_barrier_10.io.x.paa, _entries_WIRE_20.paa
connect entries_barrier_10.io.x.pal, _entries_WIRE_20.pal
connect entries_barrier_10.io.x.ppp, _entries_WIRE_20.ppp
connect entries_barrier_10.io.x.pr, _entries_WIRE_20.pr
connect entries_barrier_10.io.x.px, _entries_WIRE_20.px
connect entries_barrier_10.io.x.pw, _entries_WIRE_20.pw
connect entries_barrier_10.io.x.hr, _entries_WIRE_20.hr
connect entries_barrier_10.io.x.hx, _entries_WIRE_20.hx
connect entries_barrier_10.io.x.hw, _entries_WIRE_20.hw
connect entries_barrier_10.io.x.sr, _entries_WIRE_20.sr
connect entries_barrier_10.io.x.sx, _entries_WIRE_20.sx
connect entries_barrier_10.io.x.sw, _entries_WIRE_20.sw
connect entries_barrier_10.io.x.gf, _entries_WIRE_20.gf
connect entries_barrier_10.io.x.pf, _entries_WIRE_20.pf
connect entries_barrier_10.io.x.ae_stage2, _entries_WIRE_20.ae_stage2
connect entries_barrier_10.io.x.ae_final, _entries_WIRE_20.ae_final
connect entries_barrier_10.io.x.ae_ptw, _entries_WIRE_20.ae_ptw
connect entries_barrier_10.io.x.g, _entries_WIRE_20.g
connect entries_barrier_10.io.x.u, _entries_WIRE_20.u
connect entries_barrier_10.io.x.ppn, _entries_WIRE_20.ppn
wire _entries_WIRE_22 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_23 : UInt<42>
connect _entries_WIRE_23, superpage_entries[3].data[0]
node _entries_T_261 = bits(_entries_WIRE_23, 0, 0)
connect _entries_WIRE_22.fragmented_superpage, _entries_T_261
node _entries_T_262 = bits(_entries_WIRE_23, 1, 1)
connect _entries_WIRE_22.c, _entries_T_262
node _entries_T_263 = bits(_entries_WIRE_23, 2, 2)
connect _entries_WIRE_22.eff, _entries_T_263
node _entries_T_264 = bits(_entries_WIRE_23, 3, 3)
connect _entries_WIRE_22.paa, _entries_T_264
node _entries_T_265 = bits(_entries_WIRE_23, 4, 4)
connect _entries_WIRE_22.pal, _entries_T_265
node _entries_T_266 = bits(_entries_WIRE_23, 5, 5)
connect _entries_WIRE_22.ppp, _entries_T_266
node _entries_T_267 = bits(_entries_WIRE_23, 6, 6)
connect _entries_WIRE_22.pr, _entries_T_267
node _entries_T_268 = bits(_entries_WIRE_23, 7, 7)
connect _entries_WIRE_22.px, _entries_T_268
node _entries_T_269 = bits(_entries_WIRE_23, 8, 8)
connect _entries_WIRE_22.pw, _entries_T_269
node _entries_T_270 = bits(_entries_WIRE_23, 9, 9)
connect _entries_WIRE_22.hr, _entries_T_270
node _entries_T_271 = bits(_entries_WIRE_23, 10, 10)
connect _entries_WIRE_22.hx, _entries_T_271
node _entries_T_272 = bits(_entries_WIRE_23, 11, 11)
connect _entries_WIRE_22.hw, _entries_T_272
node _entries_T_273 = bits(_entries_WIRE_23, 12, 12)
connect _entries_WIRE_22.sr, _entries_T_273
node _entries_T_274 = bits(_entries_WIRE_23, 13, 13)
connect _entries_WIRE_22.sx, _entries_T_274
node _entries_T_275 = bits(_entries_WIRE_23, 14, 14)
connect _entries_WIRE_22.sw, _entries_T_275
node _entries_T_276 = bits(_entries_WIRE_23, 15, 15)
connect _entries_WIRE_22.gf, _entries_T_276
node _entries_T_277 = bits(_entries_WIRE_23, 16, 16)
connect _entries_WIRE_22.pf, _entries_T_277
node _entries_T_278 = bits(_entries_WIRE_23, 17, 17)
connect _entries_WIRE_22.ae_stage2, _entries_T_278
node _entries_T_279 = bits(_entries_WIRE_23, 18, 18)
connect _entries_WIRE_22.ae_final, _entries_T_279
node _entries_T_280 = bits(_entries_WIRE_23, 19, 19)
connect _entries_WIRE_22.ae_ptw, _entries_T_280
node _entries_T_281 = bits(_entries_WIRE_23, 20, 20)
connect _entries_WIRE_22.g, _entries_T_281
node _entries_T_282 = bits(_entries_WIRE_23, 21, 21)
connect _entries_WIRE_22.u, _entries_T_282
node _entries_T_283 = bits(_entries_WIRE_23, 41, 22)
connect _entries_WIRE_22.ppn, _entries_T_283
inst entries_barrier_11 of OptimizationBarrier_TLBEntryData_54
connect entries_barrier_11.clock, clock
connect entries_barrier_11.reset, reset
connect entries_barrier_11.io.x.fragmented_superpage, _entries_WIRE_22.fragmented_superpage
connect entries_barrier_11.io.x.c, _entries_WIRE_22.c
connect entries_barrier_11.io.x.eff, _entries_WIRE_22.eff
connect entries_barrier_11.io.x.paa, _entries_WIRE_22.paa
connect entries_barrier_11.io.x.pal, _entries_WIRE_22.pal
connect entries_barrier_11.io.x.ppp, _entries_WIRE_22.ppp
connect entries_barrier_11.io.x.pr, _entries_WIRE_22.pr
connect entries_barrier_11.io.x.px, _entries_WIRE_22.px
connect entries_barrier_11.io.x.pw, _entries_WIRE_22.pw
connect entries_barrier_11.io.x.hr, _entries_WIRE_22.hr
connect entries_barrier_11.io.x.hx, _entries_WIRE_22.hx
connect entries_barrier_11.io.x.hw, _entries_WIRE_22.hw
connect entries_barrier_11.io.x.sr, _entries_WIRE_22.sr
connect entries_barrier_11.io.x.sx, _entries_WIRE_22.sx
connect entries_barrier_11.io.x.sw, _entries_WIRE_22.sw
connect entries_barrier_11.io.x.gf, _entries_WIRE_22.gf
connect entries_barrier_11.io.x.pf, _entries_WIRE_22.pf
connect entries_barrier_11.io.x.ae_stage2, _entries_WIRE_22.ae_stage2
connect entries_barrier_11.io.x.ae_final, _entries_WIRE_22.ae_final
connect entries_barrier_11.io.x.ae_ptw, _entries_WIRE_22.ae_ptw
connect entries_barrier_11.io.x.g, _entries_WIRE_22.g
connect entries_barrier_11.io.x.u, _entries_WIRE_22.u
connect entries_barrier_11.io.x.ppn, _entries_WIRE_22.ppn
wire _entries_WIRE_24 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_25 : UInt<42>
connect _entries_WIRE_25, special_entry.data[0]
node _entries_T_284 = bits(_entries_WIRE_25, 0, 0)
connect _entries_WIRE_24.fragmented_superpage, _entries_T_284
node _entries_T_285 = bits(_entries_WIRE_25, 1, 1)
connect _entries_WIRE_24.c, _entries_T_285
node _entries_T_286 = bits(_entries_WIRE_25, 2, 2)
connect _entries_WIRE_24.eff, _entries_T_286
node _entries_T_287 = bits(_entries_WIRE_25, 3, 3)
connect _entries_WIRE_24.paa, _entries_T_287
node _entries_T_288 = bits(_entries_WIRE_25, 4, 4)
connect _entries_WIRE_24.pal, _entries_T_288
node _entries_T_289 = bits(_entries_WIRE_25, 5, 5)
connect _entries_WIRE_24.ppp, _entries_T_289
node _entries_T_290 = bits(_entries_WIRE_25, 6, 6)
connect _entries_WIRE_24.pr, _entries_T_290
node _entries_T_291 = bits(_entries_WIRE_25, 7, 7)
connect _entries_WIRE_24.px, _entries_T_291
node _entries_T_292 = bits(_entries_WIRE_25, 8, 8)
connect _entries_WIRE_24.pw, _entries_T_292
node _entries_T_293 = bits(_entries_WIRE_25, 9, 9)
connect _entries_WIRE_24.hr, _entries_T_293
node _entries_T_294 = bits(_entries_WIRE_25, 10, 10)
connect _entries_WIRE_24.hx, _entries_T_294
node _entries_T_295 = bits(_entries_WIRE_25, 11, 11)
connect _entries_WIRE_24.hw, _entries_T_295
node _entries_T_296 = bits(_entries_WIRE_25, 12, 12)
connect _entries_WIRE_24.sr, _entries_T_296
node _entries_T_297 = bits(_entries_WIRE_25, 13, 13)
connect _entries_WIRE_24.sx, _entries_T_297
node _entries_T_298 = bits(_entries_WIRE_25, 14, 14)
connect _entries_WIRE_24.sw, _entries_T_298
node _entries_T_299 = bits(_entries_WIRE_25, 15, 15)
connect _entries_WIRE_24.gf, _entries_T_299
node _entries_T_300 = bits(_entries_WIRE_25, 16, 16)
connect _entries_WIRE_24.pf, _entries_T_300
node _entries_T_301 = bits(_entries_WIRE_25, 17, 17)
connect _entries_WIRE_24.ae_stage2, _entries_T_301
node _entries_T_302 = bits(_entries_WIRE_25, 18, 18)
connect _entries_WIRE_24.ae_final, _entries_T_302
node _entries_T_303 = bits(_entries_WIRE_25, 19, 19)
connect _entries_WIRE_24.ae_ptw, _entries_T_303
node _entries_T_304 = bits(_entries_WIRE_25, 20, 20)
connect _entries_WIRE_24.g, _entries_T_304
node _entries_T_305 = bits(_entries_WIRE_25, 21, 21)
connect _entries_WIRE_24.u, _entries_T_305
node _entries_T_306 = bits(_entries_WIRE_25, 41, 22)
connect _entries_WIRE_24.ppn, _entries_T_306
inst entries_barrier_12 of OptimizationBarrier_TLBEntryData_55
connect entries_barrier_12.clock, clock
connect entries_barrier_12.reset, reset
connect entries_barrier_12.io.x.fragmented_superpage, _entries_WIRE_24.fragmented_superpage
connect entries_barrier_12.io.x.c, _entries_WIRE_24.c
connect entries_barrier_12.io.x.eff, _entries_WIRE_24.eff
connect entries_barrier_12.io.x.paa, _entries_WIRE_24.paa
connect entries_barrier_12.io.x.pal, _entries_WIRE_24.pal
connect entries_barrier_12.io.x.ppp, _entries_WIRE_24.ppp
connect entries_barrier_12.io.x.pr, _entries_WIRE_24.pr
connect entries_barrier_12.io.x.px, _entries_WIRE_24.px
connect entries_barrier_12.io.x.pw, _entries_WIRE_24.pw
connect entries_barrier_12.io.x.hr, _entries_WIRE_24.hr
connect entries_barrier_12.io.x.hx, _entries_WIRE_24.hx
connect entries_barrier_12.io.x.hw, _entries_WIRE_24.hw
connect entries_barrier_12.io.x.sr, _entries_WIRE_24.sr
connect entries_barrier_12.io.x.sx, _entries_WIRE_24.sx
connect entries_barrier_12.io.x.sw, _entries_WIRE_24.sw
connect entries_barrier_12.io.x.gf, _entries_WIRE_24.gf
connect entries_barrier_12.io.x.pf, _entries_WIRE_24.pf
connect entries_barrier_12.io.x.ae_stage2, _entries_WIRE_24.ae_stage2
connect entries_barrier_12.io.x.ae_final, _entries_WIRE_24.ae_final
connect entries_barrier_12.io.x.ae_ptw, _entries_WIRE_24.ae_ptw
connect entries_barrier_12.io.x.g, _entries_WIRE_24.g
connect entries_barrier_12.io.x.u, _entries_WIRE_24.u
connect entries_barrier_12.io.x.ppn, _entries_WIRE_24.ppn
node _ppn_T = eq(vm_enabled, UInt<1>(0h0))
node ppn_res = shr(entries_barrier_8.io.y.ppn, 18)
node _ppn_ignore_T = lt(superpage_entries[0].level, UInt<1>(0h1))
node ppn_ignore = or(_ppn_ignore_T, UInt<1>(0h0))
node _ppn_T_1 = mux(ppn_ignore, vpn, UInt<1>(0h0))
node _ppn_T_2 = or(_ppn_T_1, entries_barrier_8.io.y.ppn)
node _ppn_T_3 = bits(_ppn_T_2, 17, 9)
node _ppn_T_4 = cat(ppn_res, _ppn_T_3)
node _ppn_ignore_T_1 = lt(superpage_entries[0].level, UInt<2>(0h2))
node ppn_ignore_1 = or(_ppn_ignore_T_1, UInt<1>(0h1))
node _ppn_T_5 = mux(ppn_ignore_1, vpn, UInt<1>(0h0))
node _ppn_T_6 = or(_ppn_T_5, entries_barrier_8.io.y.ppn)
node _ppn_T_7 = bits(_ppn_T_6, 8, 0)
node _ppn_T_8 = cat(_ppn_T_4, _ppn_T_7)
node ppn_res_1 = shr(entries_barrier_9.io.y.ppn, 18)
node _ppn_ignore_T_2 = lt(superpage_entries[1].level, UInt<1>(0h1))
node ppn_ignore_2 = or(_ppn_ignore_T_2, UInt<1>(0h0))
node _ppn_T_9 = mux(ppn_ignore_2, vpn, UInt<1>(0h0))
node _ppn_T_10 = or(_ppn_T_9, entries_barrier_9.io.y.ppn)
node _ppn_T_11 = bits(_ppn_T_10, 17, 9)
node _ppn_T_12 = cat(ppn_res_1, _ppn_T_11)
node _ppn_ignore_T_3 = lt(superpage_entries[1].level, UInt<2>(0h2))
node ppn_ignore_3 = or(_ppn_ignore_T_3, UInt<1>(0h1))
node _ppn_T_13 = mux(ppn_ignore_3, vpn, UInt<1>(0h0))
node _ppn_T_14 = or(_ppn_T_13, entries_barrier_9.io.y.ppn)
node _ppn_T_15 = bits(_ppn_T_14, 8, 0)
node _ppn_T_16 = cat(_ppn_T_12, _ppn_T_15)
node ppn_res_2 = shr(entries_barrier_10.io.y.ppn, 18)
node _ppn_ignore_T_4 = lt(superpage_entries[2].level, UInt<1>(0h1))
node ppn_ignore_4 = or(_ppn_ignore_T_4, UInt<1>(0h0))
node _ppn_T_17 = mux(ppn_ignore_4, vpn, UInt<1>(0h0))
node _ppn_T_18 = or(_ppn_T_17, entries_barrier_10.io.y.ppn)
node _ppn_T_19 = bits(_ppn_T_18, 17, 9)
node _ppn_T_20 = cat(ppn_res_2, _ppn_T_19)
node _ppn_ignore_T_5 = lt(superpage_entries[2].level, UInt<2>(0h2))
node ppn_ignore_5 = or(_ppn_ignore_T_5, UInt<1>(0h1))
node _ppn_T_21 = mux(ppn_ignore_5, vpn, UInt<1>(0h0))
node _ppn_T_22 = or(_ppn_T_21, entries_barrier_10.io.y.ppn)
node _ppn_T_23 = bits(_ppn_T_22, 8, 0)
node _ppn_T_24 = cat(_ppn_T_20, _ppn_T_23)
node ppn_res_3 = shr(entries_barrier_11.io.y.ppn, 18)
node _ppn_ignore_T_6 = lt(superpage_entries[3].level, UInt<1>(0h1))
node ppn_ignore_6 = or(_ppn_ignore_T_6, UInt<1>(0h0))
node _ppn_T_25 = mux(ppn_ignore_6, vpn, UInt<1>(0h0))
node _ppn_T_26 = or(_ppn_T_25, entries_barrier_11.io.y.ppn)
node _ppn_T_27 = bits(_ppn_T_26, 17, 9)
node _ppn_T_28 = cat(ppn_res_3, _ppn_T_27)
node _ppn_ignore_T_7 = lt(superpage_entries[3].level, UInt<2>(0h2))
node ppn_ignore_7 = or(_ppn_ignore_T_7, UInt<1>(0h1))
node _ppn_T_29 = mux(ppn_ignore_7, vpn, UInt<1>(0h0))
node _ppn_T_30 = or(_ppn_T_29, entries_barrier_11.io.y.ppn)
node _ppn_T_31 = bits(_ppn_T_30, 8, 0)
node _ppn_T_32 = cat(_ppn_T_28, _ppn_T_31)
node ppn_res_4 = shr(entries_barrier_12.io.y.ppn, 18)
node _ppn_ignore_T_8 = lt(special_entry.level, UInt<1>(0h1))
node ppn_ignore_8 = or(_ppn_ignore_T_8, UInt<1>(0h0))
node _ppn_T_33 = mux(ppn_ignore_8, vpn, UInt<1>(0h0))
node _ppn_T_34 = or(_ppn_T_33, entries_barrier_12.io.y.ppn)
node _ppn_T_35 = bits(_ppn_T_34, 17, 9)
node _ppn_T_36 = cat(ppn_res_4, _ppn_T_35)
node _ppn_ignore_T_9 = lt(special_entry.level, UInt<2>(0h2))
node ppn_ignore_9 = or(_ppn_ignore_T_9, UInt<1>(0h0))
node _ppn_T_37 = mux(ppn_ignore_9, vpn, UInt<1>(0h0))
node _ppn_T_38 = or(_ppn_T_37, entries_barrier_12.io.y.ppn)
node _ppn_T_39 = bits(_ppn_T_38, 8, 0)
node _ppn_T_40 = cat(_ppn_T_36, _ppn_T_39)
node _ppn_T_41 = bits(vpn, 19, 0)
node _ppn_T_42 = mux(hitsVec_0, entries_barrier.io.y.ppn, UInt<1>(0h0))
node _ppn_T_43 = mux(hitsVec_1, entries_barrier_1.io.y.ppn, UInt<1>(0h0))
node _ppn_T_44 = mux(hitsVec_2, entries_barrier_2.io.y.ppn, UInt<1>(0h0))
node _ppn_T_45 = mux(hitsVec_3, entries_barrier_3.io.y.ppn, UInt<1>(0h0))
node _ppn_T_46 = mux(hitsVec_4, entries_barrier_4.io.y.ppn, UInt<1>(0h0))
node _ppn_T_47 = mux(hitsVec_5, entries_barrier_5.io.y.ppn, UInt<1>(0h0))
node _ppn_T_48 = mux(hitsVec_6, entries_barrier_6.io.y.ppn, UInt<1>(0h0))
node _ppn_T_49 = mux(hitsVec_7, entries_barrier_7.io.y.ppn, UInt<1>(0h0))
node _ppn_T_50 = mux(hitsVec_8, _ppn_T_8, UInt<1>(0h0))
node _ppn_T_51 = mux(hitsVec_9, _ppn_T_16, UInt<1>(0h0))
node _ppn_T_52 = mux(hitsVec_10, _ppn_T_24, UInt<1>(0h0))
node _ppn_T_53 = mux(hitsVec_11, _ppn_T_32, UInt<1>(0h0))
node _ppn_T_54 = mux(hitsVec_12, _ppn_T_40, UInt<1>(0h0))
node _ppn_T_55 = mux(_ppn_T, _ppn_T_41, UInt<1>(0h0))
node _ppn_T_56 = or(_ppn_T_42, _ppn_T_43)
node _ppn_T_57 = or(_ppn_T_56, _ppn_T_44)
node _ppn_T_58 = or(_ppn_T_57, _ppn_T_45)
node _ppn_T_59 = or(_ppn_T_58, _ppn_T_46)
node _ppn_T_60 = or(_ppn_T_59, _ppn_T_47)
node _ppn_T_61 = or(_ppn_T_60, _ppn_T_48)
node _ppn_T_62 = or(_ppn_T_61, _ppn_T_49)
node _ppn_T_63 = or(_ppn_T_62, _ppn_T_50)
node _ppn_T_64 = or(_ppn_T_63, _ppn_T_51)
node _ppn_T_65 = or(_ppn_T_64, _ppn_T_52)
node _ppn_T_66 = or(_ppn_T_65, _ppn_T_53)
node _ppn_T_67 = or(_ppn_T_66, _ppn_T_54)
node _ppn_T_68 = or(_ppn_T_67, _ppn_T_55)
wire ppn : UInt<20>
connect ppn, _ppn_T_68
node ptw_ae_array_lo_lo_hi = cat(entries_barrier_2.io.y.ae_ptw, entries_barrier_1.io.y.ae_ptw)
node ptw_ae_array_lo_lo = cat(ptw_ae_array_lo_lo_hi, entries_barrier.io.y.ae_ptw)
node ptw_ae_array_lo_hi_hi = cat(entries_barrier_5.io.y.ae_ptw, entries_barrier_4.io.y.ae_ptw)
node ptw_ae_array_lo_hi = cat(ptw_ae_array_lo_hi_hi, entries_barrier_3.io.y.ae_ptw)
node ptw_ae_array_lo = cat(ptw_ae_array_lo_hi, ptw_ae_array_lo_lo)
node ptw_ae_array_hi_lo_hi = cat(entries_barrier_8.io.y.ae_ptw, entries_barrier_7.io.y.ae_ptw)
node ptw_ae_array_hi_lo = cat(ptw_ae_array_hi_lo_hi, entries_barrier_6.io.y.ae_ptw)
node ptw_ae_array_hi_hi_lo = cat(entries_barrier_10.io.y.ae_ptw, entries_barrier_9.io.y.ae_ptw)
node ptw_ae_array_hi_hi_hi = cat(entries_barrier_12.io.y.ae_ptw, entries_barrier_11.io.y.ae_ptw)
node ptw_ae_array_hi_hi = cat(ptw_ae_array_hi_hi_hi, ptw_ae_array_hi_hi_lo)
node ptw_ae_array_hi = cat(ptw_ae_array_hi_hi, ptw_ae_array_hi_lo)
node _ptw_ae_array_T = cat(ptw_ae_array_hi, ptw_ae_array_lo)
node ptw_ae_array = cat(UInt<1>(0h0), _ptw_ae_array_T)
node final_ae_array_lo_lo_hi = cat(entries_barrier_2.io.y.ae_final, entries_barrier_1.io.y.ae_final)
node final_ae_array_lo_lo = cat(final_ae_array_lo_lo_hi, entries_barrier.io.y.ae_final)
node final_ae_array_lo_hi_hi = cat(entries_barrier_5.io.y.ae_final, entries_barrier_4.io.y.ae_final)
node final_ae_array_lo_hi = cat(final_ae_array_lo_hi_hi, entries_barrier_3.io.y.ae_final)
node final_ae_array_lo = cat(final_ae_array_lo_hi, final_ae_array_lo_lo)
node final_ae_array_hi_lo_hi = cat(entries_barrier_8.io.y.ae_final, entries_barrier_7.io.y.ae_final)
node final_ae_array_hi_lo = cat(final_ae_array_hi_lo_hi, entries_barrier_6.io.y.ae_final)
node final_ae_array_hi_hi_lo = cat(entries_barrier_10.io.y.ae_final, entries_barrier_9.io.y.ae_final)
node final_ae_array_hi_hi_hi = cat(entries_barrier_12.io.y.ae_final, entries_barrier_11.io.y.ae_final)
node final_ae_array_hi_hi = cat(final_ae_array_hi_hi_hi, final_ae_array_hi_hi_lo)
node final_ae_array_hi = cat(final_ae_array_hi_hi, final_ae_array_hi_lo)
node _final_ae_array_T = cat(final_ae_array_hi, final_ae_array_lo)
node final_ae_array = cat(UInt<1>(0h0), _final_ae_array_T)
node ptw_pf_array_lo_lo_hi = cat(entries_barrier_2.io.y.pf, entries_barrier_1.io.y.pf)
node ptw_pf_array_lo_lo = cat(ptw_pf_array_lo_lo_hi, entries_barrier.io.y.pf)
node ptw_pf_array_lo_hi_hi = cat(entries_barrier_5.io.y.pf, entries_barrier_4.io.y.pf)
node ptw_pf_array_lo_hi = cat(ptw_pf_array_lo_hi_hi, entries_barrier_3.io.y.pf)
node ptw_pf_array_lo = cat(ptw_pf_array_lo_hi, ptw_pf_array_lo_lo)
node ptw_pf_array_hi_lo_hi = cat(entries_barrier_8.io.y.pf, entries_barrier_7.io.y.pf)
node ptw_pf_array_hi_lo = cat(ptw_pf_array_hi_lo_hi, entries_barrier_6.io.y.pf)
node ptw_pf_array_hi_hi_lo = cat(entries_barrier_10.io.y.pf, entries_barrier_9.io.y.pf)
node ptw_pf_array_hi_hi_hi = cat(entries_barrier_12.io.y.pf, entries_barrier_11.io.y.pf)
node ptw_pf_array_hi_hi = cat(ptw_pf_array_hi_hi_hi, ptw_pf_array_hi_hi_lo)
node ptw_pf_array_hi = cat(ptw_pf_array_hi_hi, ptw_pf_array_hi_lo)
node _ptw_pf_array_T = cat(ptw_pf_array_hi, ptw_pf_array_lo)
node ptw_pf_array = cat(UInt<1>(0h0), _ptw_pf_array_T)
node ptw_gf_array_lo_lo_hi = cat(entries_barrier_2.io.y.gf, entries_barrier_1.io.y.gf)
node ptw_gf_array_lo_lo = cat(ptw_gf_array_lo_lo_hi, entries_barrier.io.y.gf)
node ptw_gf_array_lo_hi_hi = cat(entries_barrier_5.io.y.gf, entries_barrier_4.io.y.gf)
node ptw_gf_array_lo_hi = cat(ptw_gf_array_lo_hi_hi, entries_barrier_3.io.y.gf)
node ptw_gf_array_lo = cat(ptw_gf_array_lo_hi, ptw_gf_array_lo_lo)
node ptw_gf_array_hi_lo_hi = cat(entries_barrier_8.io.y.gf, entries_barrier_7.io.y.gf)
node ptw_gf_array_hi_lo = cat(ptw_gf_array_hi_lo_hi, entries_barrier_6.io.y.gf)
node ptw_gf_array_hi_hi_lo = cat(entries_barrier_10.io.y.gf, entries_barrier_9.io.y.gf)
node ptw_gf_array_hi_hi_hi = cat(entries_barrier_12.io.y.gf, entries_barrier_11.io.y.gf)
node ptw_gf_array_hi_hi = cat(ptw_gf_array_hi_hi_hi, ptw_gf_array_hi_hi_lo)
node ptw_gf_array_hi = cat(ptw_gf_array_hi_hi, ptw_gf_array_hi_lo)
node _ptw_gf_array_T = cat(ptw_gf_array_hi, ptw_gf_array_lo)
node ptw_gf_array = cat(UInt<1>(0h0), _ptw_gf_array_T)
node sum = mux(priv_v, io.ptw.gstatus.sum, io.ptw.status.sum)
node _priv_rw_ok_T = eq(priv_s, UInt<1>(0h0))
node _priv_rw_ok_T_1 = or(_priv_rw_ok_T, sum)
node priv_rw_ok_lo_lo_hi = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u)
node priv_rw_ok_lo_lo = cat(priv_rw_ok_lo_lo_hi, entries_barrier.io.y.u)
node priv_rw_ok_lo_hi_hi = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u)
node priv_rw_ok_lo_hi = cat(priv_rw_ok_lo_hi_hi, entries_barrier_3.io.y.u)
node priv_rw_ok_lo = cat(priv_rw_ok_lo_hi, priv_rw_ok_lo_lo)
node priv_rw_ok_hi_lo_hi = cat(entries_barrier_8.io.y.u, entries_barrier_7.io.y.u)
node priv_rw_ok_hi_lo = cat(priv_rw_ok_hi_lo_hi, entries_barrier_6.io.y.u)
node priv_rw_ok_hi_hi_lo = cat(entries_barrier_10.io.y.u, entries_barrier_9.io.y.u)
node priv_rw_ok_hi_hi_hi = cat(entries_barrier_12.io.y.u, entries_barrier_11.io.y.u)
node priv_rw_ok_hi_hi = cat(priv_rw_ok_hi_hi_hi, priv_rw_ok_hi_hi_lo)
node priv_rw_ok_hi = cat(priv_rw_ok_hi_hi, priv_rw_ok_hi_lo)
node _priv_rw_ok_T_2 = cat(priv_rw_ok_hi, priv_rw_ok_lo)
node _priv_rw_ok_T_3 = mux(_priv_rw_ok_T_1, _priv_rw_ok_T_2, UInt<1>(0h0))
node priv_rw_ok_lo_lo_hi_1 = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u)
node priv_rw_ok_lo_lo_1 = cat(priv_rw_ok_lo_lo_hi_1, entries_barrier.io.y.u)
node priv_rw_ok_lo_hi_hi_1 = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u)
node priv_rw_ok_lo_hi_1 = cat(priv_rw_ok_lo_hi_hi_1, entries_barrier_3.io.y.u)
node priv_rw_ok_lo_1 = cat(priv_rw_ok_lo_hi_1, priv_rw_ok_lo_lo_1)
node priv_rw_ok_hi_lo_hi_1 = cat(entries_barrier_8.io.y.u, entries_barrier_7.io.y.u)
node priv_rw_ok_hi_lo_1 = cat(priv_rw_ok_hi_lo_hi_1, entries_barrier_6.io.y.u)
node priv_rw_ok_hi_hi_lo_1 = cat(entries_barrier_10.io.y.u, entries_barrier_9.io.y.u)
node priv_rw_ok_hi_hi_hi_1 = cat(entries_barrier_12.io.y.u, entries_barrier_11.io.y.u)
node priv_rw_ok_hi_hi_1 = cat(priv_rw_ok_hi_hi_hi_1, priv_rw_ok_hi_hi_lo_1)
node priv_rw_ok_hi_1 = cat(priv_rw_ok_hi_hi_1, priv_rw_ok_hi_lo_1)
node _priv_rw_ok_T_4 = cat(priv_rw_ok_hi_1, priv_rw_ok_lo_1)
node _priv_rw_ok_T_5 = not(_priv_rw_ok_T_4)
node _priv_rw_ok_T_6 = mux(priv_s, _priv_rw_ok_T_5, UInt<1>(0h0))
node priv_rw_ok = or(_priv_rw_ok_T_3, _priv_rw_ok_T_6)
node priv_x_ok_lo_lo_hi = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u)
node priv_x_ok_lo_lo = cat(priv_x_ok_lo_lo_hi, entries_barrier.io.y.u)
node priv_x_ok_lo_hi_hi = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u)
node priv_x_ok_lo_hi = cat(priv_x_ok_lo_hi_hi, entries_barrier_3.io.y.u)
node priv_x_ok_lo = cat(priv_x_ok_lo_hi, priv_x_ok_lo_lo)
node priv_x_ok_hi_lo_hi = cat(entries_barrier_8.io.y.u, entries_barrier_7.io.y.u)
node priv_x_ok_hi_lo = cat(priv_x_ok_hi_lo_hi, entries_barrier_6.io.y.u)
node priv_x_ok_hi_hi_lo = cat(entries_barrier_10.io.y.u, entries_barrier_9.io.y.u)
node priv_x_ok_hi_hi_hi = cat(entries_barrier_12.io.y.u, entries_barrier_11.io.y.u)
node priv_x_ok_hi_hi = cat(priv_x_ok_hi_hi_hi, priv_x_ok_hi_hi_lo)
node priv_x_ok_hi = cat(priv_x_ok_hi_hi, priv_x_ok_hi_lo)
node _priv_x_ok_T = cat(priv_x_ok_hi, priv_x_ok_lo)
node _priv_x_ok_T_1 = not(_priv_x_ok_T)
node priv_x_ok_lo_lo_hi_1 = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u)
node priv_x_ok_lo_lo_1 = cat(priv_x_ok_lo_lo_hi_1, entries_barrier.io.y.u)
node priv_x_ok_lo_hi_hi_1 = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u)
node priv_x_ok_lo_hi_1 = cat(priv_x_ok_lo_hi_hi_1, entries_barrier_3.io.y.u)
node priv_x_ok_lo_1 = cat(priv_x_ok_lo_hi_1, priv_x_ok_lo_lo_1)
node priv_x_ok_hi_lo_hi_1 = cat(entries_barrier_8.io.y.u, entries_barrier_7.io.y.u)
node priv_x_ok_hi_lo_1 = cat(priv_x_ok_hi_lo_hi_1, entries_barrier_6.io.y.u)
node priv_x_ok_hi_hi_lo_1 = cat(entries_barrier_10.io.y.u, entries_barrier_9.io.y.u)
node priv_x_ok_hi_hi_hi_1 = cat(entries_barrier_12.io.y.u, entries_barrier_11.io.y.u)
node priv_x_ok_hi_hi_1 = cat(priv_x_ok_hi_hi_hi_1, priv_x_ok_hi_hi_lo_1)
node priv_x_ok_hi_1 = cat(priv_x_ok_hi_hi_1, priv_x_ok_hi_lo_1)
node _priv_x_ok_T_2 = cat(priv_x_ok_hi_1, priv_x_ok_lo_1)
node priv_x_ok = mux(priv_s, _priv_x_ok_T_1, _priv_x_ok_T_2)
node _stage1_bypass_T = mux(UInt<1>(0h0), UInt<13>(0h1fff), UInt<13>(0h0))
node _stage1_bypass_T_1 = eq(stage1_en, UInt<1>(0h0))
node _stage1_bypass_T_2 = mux(_stage1_bypass_T_1, UInt<13>(0h1fff), UInt<13>(0h0))
node stage1_bypass_lo_lo_hi = cat(entries_barrier_2.io.y.ae_stage2, entries_barrier_1.io.y.ae_stage2)
node stage1_bypass_lo_lo = cat(stage1_bypass_lo_lo_hi, entries_barrier.io.y.ae_stage2)
node stage1_bypass_lo_hi_hi = cat(entries_barrier_5.io.y.ae_stage2, entries_barrier_4.io.y.ae_stage2)
node stage1_bypass_lo_hi = cat(stage1_bypass_lo_hi_hi, entries_barrier_3.io.y.ae_stage2)
node stage1_bypass_lo = cat(stage1_bypass_lo_hi, stage1_bypass_lo_lo)
node stage1_bypass_hi_lo_hi = cat(entries_barrier_8.io.y.ae_stage2, entries_barrier_7.io.y.ae_stage2)
node stage1_bypass_hi_lo = cat(stage1_bypass_hi_lo_hi, entries_barrier_6.io.y.ae_stage2)
node stage1_bypass_hi_hi_lo = cat(entries_barrier_10.io.y.ae_stage2, entries_barrier_9.io.y.ae_stage2)
node stage1_bypass_hi_hi_hi = cat(entries_barrier_12.io.y.ae_stage2, entries_barrier_11.io.y.ae_stage2)
node stage1_bypass_hi_hi = cat(stage1_bypass_hi_hi_hi, stage1_bypass_hi_hi_lo)
node stage1_bypass_hi = cat(stage1_bypass_hi_hi, stage1_bypass_hi_lo)
node _stage1_bypass_T_3 = cat(stage1_bypass_hi, stage1_bypass_lo)
node _stage1_bypass_T_4 = or(_stage1_bypass_T_2, _stage1_bypass_T_3)
node stage1_bypass = and(_stage1_bypass_T, _stage1_bypass_T_4)
node _mxr_T = mux(priv_v, io.ptw.gstatus.mxr, UInt<1>(0h0))
node mxr = or(io.ptw.status.mxr, _mxr_T)
node r_array_lo_lo_hi = cat(entries_barrier_2.io.y.sr, entries_barrier_1.io.y.sr)
node r_array_lo_lo = cat(r_array_lo_lo_hi, entries_barrier.io.y.sr)
node r_array_lo_hi_hi = cat(entries_barrier_5.io.y.sr, entries_barrier_4.io.y.sr)
node r_array_lo_hi = cat(r_array_lo_hi_hi, entries_barrier_3.io.y.sr)
node r_array_lo = cat(r_array_lo_hi, r_array_lo_lo)
node r_array_hi_lo_hi = cat(entries_barrier_8.io.y.sr, entries_barrier_7.io.y.sr)
node r_array_hi_lo = cat(r_array_hi_lo_hi, entries_barrier_6.io.y.sr)
node r_array_hi_hi_lo = cat(entries_barrier_10.io.y.sr, entries_barrier_9.io.y.sr)
node r_array_hi_hi_hi = cat(entries_barrier_12.io.y.sr, entries_barrier_11.io.y.sr)
node r_array_hi_hi = cat(r_array_hi_hi_hi, r_array_hi_hi_lo)
node r_array_hi = cat(r_array_hi_hi, r_array_hi_lo)
node _r_array_T = cat(r_array_hi, r_array_lo)
node r_array_lo_lo_hi_1 = cat(entries_barrier_2.io.y.sx, entries_barrier_1.io.y.sx)
node r_array_lo_lo_1 = cat(r_array_lo_lo_hi_1, entries_barrier.io.y.sx)
node r_array_lo_hi_hi_1 = cat(entries_barrier_5.io.y.sx, entries_barrier_4.io.y.sx)
node r_array_lo_hi_1 = cat(r_array_lo_hi_hi_1, entries_barrier_3.io.y.sx)
node r_array_lo_1 = cat(r_array_lo_hi_1, r_array_lo_lo_1)
node r_array_hi_lo_hi_1 = cat(entries_barrier_8.io.y.sx, entries_barrier_7.io.y.sx)
node r_array_hi_lo_1 = cat(r_array_hi_lo_hi_1, entries_barrier_6.io.y.sx)
node r_array_hi_hi_lo_1 = cat(entries_barrier_10.io.y.sx, entries_barrier_9.io.y.sx)
node r_array_hi_hi_hi_1 = cat(entries_barrier_12.io.y.sx, entries_barrier_11.io.y.sx)
node r_array_hi_hi_1 = cat(r_array_hi_hi_hi_1, r_array_hi_hi_lo_1)
node r_array_hi_1 = cat(r_array_hi_hi_1, r_array_hi_lo_1)
node _r_array_T_1 = cat(r_array_hi_1, r_array_lo_1)
node _r_array_T_2 = mux(mxr, _r_array_T_1, UInt<1>(0h0))
node _r_array_T_3 = or(_r_array_T, _r_array_T_2)
node _r_array_T_4 = and(priv_rw_ok, _r_array_T_3)
node _r_array_T_5 = or(_r_array_T_4, stage1_bypass)
node r_array = cat(UInt<1>(0h1), _r_array_T_5)
node w_array_lo_lo_hi = cat(entries_barrier_2.io.y.sw, entries_barrier_1.io.y.sw)
node w_array_lo_lo = cat(w_array_lo_lo_hi, entries_barrier.io.y.sw)
node w_array_lo_hi_hi = cat(entries_barrier_5.io.y.sw, entries_barrier_4.io.y.sw)
node w_array_lo_hi = cat(w_array_lo_hi_hi, entries_barrier_3.io.y.sw)
node w_array_lo = cat(w_array_lo_hi, w_array_lo_lo)
node w_array_hi_lo_hi = cat(entries_barrier_8.io.y.sw, entries_barrier_7.io.y.sw)
node w_array_hi_lo = cat(w_array_hi_lo_hi, entries_barrier_6.io.y.sw)
node w_array_hi_hi_lo = cat(entries_barrier_10.io.y.sw, entries_barrier_9.io.y.sw)
node w_array_hi_hi_hi = cat(entries_barrier_12.io.y.sw, entries_barrier_11.io.y.sw)
node w_array_hi_hi = cat(w_array_hi_hi_hi, w_array_hi_hi_lo)
node w_array_hi = cat(w_array_hi_hi, w_array_hi_lo)
node _w_array_T = cat(w_array_hi, w_array_lo)
node _w_array_T_1 = and(priv_rw_ok, _w_array_T)
node _w_array_T_2 = or(_w_array_T_1, stage1_bypass)
node w_array = cat(UInt<1>(0h1), _w_array_T_2)
node x_array_lo_lo_hi = cat(entries_barrier_2.io.y.sx, entries_barrier_1.io.y.sx)
node x_array_lo_lo = cat(x_array_lo_lo_hi, entries_barrier.io.y.sx)
node x_array_lo_hi_hi = cat(entries_barrier_5.io.y.sx, entries_barrier_4.io.y.sx)
node x_array_lo_hi = cat(x_array_lo_hi_hi, entries_barrier_3.io.y.sx)
node x_array_lo = cat(x_array_lo_hi, x_array_lo_lo)
node x_array_hi_lo_hi = cat(entries_barrier_8.io.y.sx, entries_barrier_7.io.y.sx)
node x_array_hi_lo = cat(x_array_hi_lo_hi, entries_barrier_6.io.y.sx)
node x_array_hi_hi_lo = cat(entries_barrier_10.io.y.sx, entries_barrier_9.io.y.sx)
node x_array_hi_hi_hi = cat(entries_barrier_12.io.y.sx, entries_barrier_11.io.y.sx)
node x_array_hi_hi = cat(x_array_hi_hi_hi, x_array_hi_hi_lo)
node x_array_hi = cat(x_array_hi_hi, x_array_hi_lo)
node _x_array_T = cat(x_array_hi, x_array_lo)
node _x_array_T_1 = and(priv_x_ok, _x_array_T)
node _x_array_T_2 = or(_x_array_T_1, stage1_bypass)
node x_array = cat(UInt<1>(0h1), _x_array_T_2)
node _stage2_bypass_T = eq(stage2_en, UInt<1>(0h0))
node stage2_bypass = mux(_stage2_bypass_T, UInt<13>(0h1fff), UInt<13>(0h0))
node hr_array_lo_lo_hi = cat(entries_barrier_2.io.y.hr, entries_barrier_1.io.y.hr)
node hr_array_lo_lo = cat(hr_array_lo_lo_hi, entries_barrier.io.y.hr)
node hr_array_lo_hi_hi = cat(entries_barrier_5.io.y.hr, entries_barrier_4.io.y.hr)
node hr_array_lo_hi = cat(hr_array_lo_hi_hi, entries_barrier_3.io.y.hr)
node hr_array_lo = cat(hr_array_lo_hi, hr_array_lo_lo)
node hr_array_hi_lo_hi = cat(entries_barrier_8.io.y.hr, entries_barrier_7.io.y.hr)
node hr_array_hi_lo = cat(hr_array_hi_lo_hi, entries_barrier_6.io.y.hr)
node hr_array_hi_hi_lo = cat(entries_barrier_10.io.y.hr, entries_barrier_9.io.y.hr)
node hr_array_hi_hi_hi = cat(entries_barrier_12.io.y.hr, entries_barrier_11.io.y.hr)
node hr_array_hi_hi = cat(hr_array_hi_hi_hi, hr_array_hi_hi_lo)
node hr_array_hi = cat(hr_array_hi_hi, hr_array_hi_lo)
node _hr_array_T = cat(hr_array_hi, hr_array_lo)
node hr_array_lo_lo_hi_1 = cat(entries_barrier_2.io.y.hx, entries_barrier_1.io.y.hx)
node hr_array_lo_lo_1 = cat(hr_array_lo_lo_hi_1, entries_barrier.io.y.hx)
node hr_array_lo_hi_hi_1 = cat(entries_barrier_5.io.y.hx, entries_barrier_4.io.y.hx)
node hr_array_lo_hi_1 = cat(hr_array_lo_hi_hi_1, entries_barrier_3.io.y.hx)
node hr_array_lo_1 = cat(hr_array_lo_hi_1, hr_array_lo_lo_1)
node hr_array_hi_lo_hi_1 = cat(entries_barrier_8.io.y.hx, entries_barrier_7.io.y.hx)
node hr_array_hi_lo_1 = cat(hr_array_hi_lo_hi_1, entries_barrier_6.io.y.hx)
node hr_array_hi_hi_lo_1 = cat(entries_barrier_10.io.y.hx, entries_barrier_9.io.y.hx)
node hr_array_hi_hi_hi_1 = cat(entries_barrier_12.io.y.hx, entries_barrier_11.io.y.hx)
node hr_array_hi_hi_1 = cat(hr_array_hi_hi_hi_1, hr_array_hi_hi_lo_1)
node hr_array_hi_1 = cat(hr_array_hi_hi_1, hr_array_hi_lo_1)
node _hr_array_T_1 = cat(hr_array_hi_1, hr_array_lo_1)
node _hr_array_T_2 = mux(io.ptw.status.mxr, _hr_array_T_1, UInt<1>(0h0))
node _hr_array_T_3 = or(_hr_array_T, _hr_array_T_2)
node _hr_array_T_4 = or(_hr_array_T_3, stage2_bypass)
node hr_array = cat(UInt<1>(0h1), _hr_array_T_4)
node hw_array_lo_lo_hi = cat(entries_barrier_2.io.y.hw, entries_barrier_1.io.y.hw)
node hw_array_lo_lo = cat(hw_array_lo_lo_hi, entries_barrier.io.y.hw)
node hw_array_lo_hi_hi = cat(entries_barrier_5.io.y.hw, entries_barrier_4.io.y.hw)
node hw_array_lo_hi = cat(hw_array_lo_hi_hi, entries_barrier_3.io.y.hw)
node hw_array_lo = cat(hw_array_lo_hi, hw_array_lo_lo)
node hw_array_hi_lo_hi = cat(entries_barrier_8.io.y.hw, entries_barrier_7.io.y.hw)
node hw_array_hi_lo = cat(hw_array_hi_lo_hi, entries_barrier_6.io.y.hw)
node hw_array_hi_hi_lo = cat(entries_barrier_10.io.y.hw, entries_barrier_9.io.y.hw)
node hw_array_hi_hi_hi = cat(entries_barrier_12.io.y.hw, entries_barrier_11.io.y.hw)
node hw_array_hi_hi = cat(hw_array_hi_hi_hi, hw_array_hi_hi_lo)
node hw_array_hi = cat(hw_array_hi_hi, hw_array_hi_lo)
node _hw_array_T = cat(hw_array_hi, hw_array_lo)
node _hw_array_T_1 = or(_hw_array_T, stage2_bypass)
node hw_array = cat(UInt<1>(0h1), _hw_array_T_1)
node hx_array_lo_lo_hi = cat(entries_barrier_2.io.y.hx, entries_barrier_1.io.y.hx)
node hx_array_lo_lo = cat(hx_array_lo_lo_hi, entries_barrier.io.y.hx)
node hx_array_lo_hi_hi = cat(entries_barrier_5.io.y.hx, entries_barrier_4.io.y.hx)
node hx_array_lo_hi = cat(hx_array_lo_hi_hi, entries_barrier_3.io.y.hx)
node hx_array_lo = cat(hx_array_lo_hi, hx_array_lo_lo)
node hx_array_hi_lo_hi = cat(entries_barrier_8.io.y.hx, entries_barrier_7.io.y.hx)
node hx_array_hi_lo = cat(hx_array_hi_lo_hi, entries_barrier_6.io.y.hx)
node hx_array_hi_hi_lo = cat(entries_barrier_10.io.y.hx, entries_barrier_9.io.y.hx)
node hx_array_hi_hi_hi = cat(entries_barrier_12.io.y.hx, entries_barrier_11.io.y.hx)
node hx_array_hi_hi = cat(hx_array_hi_hi_hi, hx_array_hi_hi_lo)
node hx_array_hi = cat(hx_array_hi_hi, hx_array_hi_lo)
node _hx_array_T = cat(hx_array_hi, hx_array_lo)
node _hx_array_T_1 = or(_hx_array_T, stage2_bypass)
node hx_array = cat(UInt<1>(0h1), _hx_array_T_1)
node _pr_array_T = mux(prot_r, UInt<2>(0h3), UInt<2>(0h0))
node pr_array_lo_lo_hi = cat(entries_barrier_2.io.y.pr, entries_barrier_1.io.y.pr)
node pr_array_lo_lo = cat(pr_array_lo_lo_hi, entries_barrier.io.y.pr)
node pr_array_lo_hi_hi = cat(entries_barrier_5.io.y.pr, entries_barrier_4.io.y.pr)
node pr_array_lo_hi = cat(pr_array_lo_hi_hi, entries_barrier_3.io.y.pr)
node pr_array_lo = cat(pr_array_lo_hi, pr_array_lo_lo)
node pr_array_hi_lo_hi = cat(entries_barrier_8.io.y.pr, entries_barrier_7.io.y.pr)
node pr_array_hi_lo = cat(pr_array_hi_lo_hi, entries_barrier_6.io.y.pr)
node pr_array_hi_hi_hi = cat(entries_barrier_11.io.y.pr, entries_barrier_10.io.y.pr)
node pr_array_hi_hi = cat(pr_array_hi_hi_hi, entries_barrier_9.io.y.pr)
node pr_array_hi = cat(pr_array_hi_hi, pr_array_hi_lo)
node _pr_array_T_1 = cat(pr_array_hi, pr_array_lo)
node _pr_array_T_2 = cat(_pr_array_T, _pr_array_T_1)
node _pr_array_T_3 = or(ptw_ae_array, final_ae_array)
node _pr_array_T_4 = not(_pr_array_T_3)
node pr_array = and(_pr_array_T_2, _pr_array_T_4)
node _pw_array_T = mux(prot_w, UInt<2>(0h3), UInt<2>(0h0))
node pw_array_lo_lo_hi = cat(entries_barrier_2.io.y.pw, entries_barrier_1.io.y.pw)
node pw_array_lo_lo = cat(pw_array_lo_lo_hi, entries_barrier.io.y.pw)
node pw_array_lo_hi_hi = cat(entries_barrier_5.io.y.pw, entries_barrier_4.io.y.pw)
node pw_array_lo_hi = cat(pw_array_lo_hi_hi, entries_barrier_3.io.y.pw)
node pw_array_lo = cat(pw_array_lo_hi, pw_array_lo_lo)
node pw_array_hi_lo_hi = cat(entries_barrier_8.io.y.pw, entries_barrier_7.io.y.pw)
node pw_array_hi_lo = cat(pw_array_hi_lo_hi, entries_barrier_6.io.y.pw)
node pw_array_hi_hi_hi = cat(entries_barrier_11.io.y.pw, entries_barrier_10.io.y.pw)
node pw_array_hi_hi = cat(pw_array_hi_hi_hi, entries_barrier_9.io.y.pw)
node pw_array_hi = cat(pw_array_hi_hi, pw_array_hi_lo)
node _pw_array_T_1 = cat(pw_array_hi, pw_array_lo)
node _pw_array_T_2 = cat(_pw_array_T, _pw_array_T_1)
node _pw_array_T_3 = or(ptw_ae_array, final_ae_array)
node _pw_array_T_4 = not(_pw_array_T_3)
node pw_array = and(_pw_array_T_2, _pw_array_T_4)
node _px_array_T = mux(prot_x, UInt<2>(0h3), UInt<2>(0h0))
node px_array_lo_lo_hi = cat(entries_barrier_2.io.y.px, entries_barrier_1.io.y.px)
node px_array_lo_lo = cat(px_array_lo_lo_hi, entries_barrier.io.y.px)
node px_array_lo_hi_hi = cat(entries_barrier_5.io.y.px, entries_barrier_4.io.y.px)
node px_array_lo_hi = cat(px_array_lo_hi_hi, entries_barrier_3.io.y.px)
node px_array_lo = cat(px_array_lo_hi, px_array_lo_lo)
node px_array_hi_lo_hi = cat(entries_barrier_8.io.y.px, entries_barrier_7.io.y.px)
node px_array_hi_lo = cat(px_array_hi_lo_hi, entries_barrier_6.io.y.px)
node px_array_hi_hi_hi = cat(entries_barrier_11.io.y.px, entries_barrier_10.io.y.px)
node px_array_hi_hi = cat(px_array_hi_hi_hi, entries_barrier_9.io.y.px)
node px_array_hi = cat(px_array_hi_hi, px_array_hi_lo)
node _px_array_T_1 = cat(px_array_hi, px_array_lo)
node _px_array_T_2 = cat(_px_array_T, _px_array_T_1)
node _px_array_T_3 = or(ptw_ae_array, final_ae_array)
node _px_array_T_4 = not(_px_array_T_3)
node px_array = and(_px_array_T_2, _px_array_T_4)
node _eff_array_T = mux(pma.io.resp.eff, UInt<2>(0h3), UInt<2>(0h0))
node eff_array_lo_lo_hi = cat(entries_barrier_2.io.y.eff, entries_barrier_1.io.y.eff)
node eff_array_lo_lo = cat(eff_array_lo_lo_hi, entries_barrier.io.y.eff)
node eff_array_lo_hi_hi = cat(entries_barrier_5.io.y.eff, entries_barrier_4.io.y.eff)
node eff_array_lo_hi = cat(eff_array_lo_hi_hi, entries_barrier_3.io.y.eff)
node eff_array_lo = cat(eff_array_lo_hi, eff_array_lo_lo)
node eff_array_hi_lo_hi = cat(entries_barrier_8.io.y.eff, entries_barrier_7.io.y.eff)
node eff_array_hi_lo = cat(eff_array_hi_lo_hi, entries_barrier_6.io.y.eff)
node eff_array_hi_hi_hi = cat(entries_barrier_11.io.y.eff, entries_barrier_10.io.y.eff)
node eff_array_hi_hi = cat(eff_array_hi_hi_hi, entries_barrier_9.io.y.eff)
node eff_array_hi = cat(eff_array_hi_hi, eff_array_hi_lo)
node _eff_array_T_1 = cat(eff_array_hi, eff_array_lo)
node eff_array = cat(_eff_array_T, _eff_array_T_1)
node _c_array_T = mux(cacheable, UInt<2>(0h3), UInt<2>(0h0))
node c_array_lo_lo_hi = cat(entries_barrier_2.io.y.c, entries_barrier_1.io.y.c)
node c_array_lo_lo = cat(c_array_lo_lo_hi, entries_barrier.io.y.c)
node c_array_lo_hi_hi = cat(entries_barrier_5.io.y.c, entries_barrier_4.io.y.c)
node c_array_lo_hi = cat(c_array_lo_hi_hi, entries_barrier_3.io.y.c)
node c_array_lo = cat(c_array_lo_hi, c_array_lo_lo)
node c_array_hi_lo_hi = cat(entries_barrier_8.io.y.c, entries_barrier_7.io.y.c)
node c_array_hi_lo = cat(c_array_hi_lo_hi, entries_barrier_6.io.y.c)
node c_array_hi_hi_hi = cat(entries_barrier_11.io.y.c, entries_barrier_10.io.y.c)
node c_array_hi_hi = cat(c_array_hi_hi_hi, entries_barrier_9.io.y.c)
node c_array_hi = cat(c_array_hi_hi, c_array_hi_lo)
node _c_array_T_1 = cat(c_array_hi, c_array_lo)
node c_array = cat(_c_array_T, _c_array_T_1)
node _ppp_array_T = mux(pma.io.resp.pp, UInt<2>(0h3), UInt<2>(0h0))
node ppp_array_lo_lo_hi = cat(entries_barrier_2.io.y.ppp, entries_barrier_1.io.y.ppp)
node ppp_array_lo_lo = cat(ppp_array_lo_lo_hi, entries_barrier.io.y.ppp)
node ppp_array_lo_hi_hi = cat(entries_barrier_5.io.y.ppp, entries_barrier_4.io.y.ppp)
node ppp_array_lo_hi = cat(ppp_array_lo_hi_hi, entries_barrier_3.io.y.ppp)
node ppp_array_lo = cat(ppp_array_lo_hi, ppp_array_lo_lo)
node ppp_array_hi_lo_hi = cat(entries_barrier_8.io.y.ppp, entries_barrier_7.io.y.ppp)
node ppp_array_hi_lo = cat(ppp_array_hi_lo_hi, entries_barrier_6.io.y.ppp)
node ppp_array_hi_hi_hi = cat(entries_barrier_11.io.y.ppp, entries_barrier_10.io.y.ppp)
node ppp_array_hi_hi = cat(ppp_array_hi_hi_hi, entries_barrier_9.io.y.ppp)
node ppp_array_hi = cat(ppp_array_hi_hi, ppp_array_hi_lo)
node _ppp_array_T_1 = cat(ppp_array_hi, ppp_array_lo)
node ppp_array = cat(_ppp_array_T, _ppp_array_T_1)
node _paa_array_T = mux(pma.io.resp.aa, UInt<2>(0h3), UInt<2>(0h0))
node paa_array_lo_lo_hi = cat(entries_barrier_2.io.y.paa, entries_barrier_1.io.y.paa)
node paa_array_lo_lo = cat(paa_array_lo_lo_hi, entries_barrier.io.y.paa)
node paa_array_lo_hi_hi = cat(entries_barrier_5.io.y.paa, entries_barrier_4.io.y.paa)
node paa_array_lo_hi = cat(paa_array_lo_hi_hi, entries_barrier_3.io.y.paa)
node paa_array_lo = cat(paa_array_lo_hi, paa_array_lo_lo)
node paa_array_hi_lo_hi = cat(entries_barrier_8.io.y.paa, entries_barrier_7.io.y.paa)
node paa_array_hi_lo = cat(paa_array_hi_lo_hi, entries_barrier_6.io.y.paa)
node paa_array_hi_hi_hi = cat(entries_barrier_11.io.y.paa, entries_barrier_10.io.y.paa)
node paa_array_hi_hi = cat(paa_array_hi_hi_hi, entries_barrier_9.io.y.paa)
node paa_array_hi = cat(paa_array_hi_hi, paa_array_hi_lo)
node _paa_array_T_1 = cat(paa_array_hi, paa_array_lo)
node paa_array = cat(_paa_array_T, _paa_array_T_1)
node _pal_array_T = mux(pma.io.resp.al, UInt<2>(0h3), UInt<2>(0h0))
node pal_array_lo_lo_hi = cat(entries_barrier_2.io.y.pal, entries_barrier_1.io.y.pal)
node pal_array_lo_lo = cat(pal_array_lo_lo_hi, entries_barrier.io.y.pal)
node pal_array_lo_hi_hi = cat(entries_barrier_5.io.y.pal, entries_barrier_4.io.y.pal)
node pal_array_lo_hi = cat(pal_array_lo_hi_hi, entries_barrier_3.io.y.pal)
node pal_array_lo = cat(pal_array_lo_hi, pal_array_lo_lo)
node pal_array_hi_lo_hi = cat(entries_barrier_8.io.y.pal, entries_barrier_7.io.y.pal)
node pal_array_hi_lo = cat(pal_array_hi_lo_hi, entries_barrier_6.io.y.pal)
node pal_array_hi_hi_hi = cat(entries_barrier_11.io.y.pal, entries_barrier_10.io.y.pal)
node pal_array_hi_hi = cat(pal_array_hi_hi_hi, entries_barrier_9.io.y.pal)
node pal_array_hi = cat(pal_array_hi_hi, pal_array_hi_lo)
node _pal_array_T_1 = cat(pal_array_hi, pal_array_lo)
node pal_array = cat(_pal_array_T, _pal_array_T_1)
node ppp_array_if_cached = or(ppp_array, c_array)
node paa_array_if_cached = or(paa_array, UInt<1>(0h0))
node pal_array_if_cached = or(pal_array, UInt<1>(0h0))
node _prefetchable_array_T = and(cacheable, homogeneous)
node _prefetchable_array_T_1 = shl(_prefetchable_array_T, 1)
node prefetchable_array_lo_lo_hi = cat(entries_barrier_2.io.y.c, entries_barrier_1.io.y.c)
node prefetchable_array_lo_lo = cat(prefetchable_array_lo_lo_hi, entries_barrier.io.y.c)
node prefetchable_array_lo_hi_hi = cat(entries_barrier_5.io.y.c, entries_barrier_4.io.y.c)
node prefetchable_array_lo_hi = cat(prefetchable_array_lo_hi_hi, entries_barrier_3.io.y.c)
node prefetchable_array_lo = cat(prefetchable_array_lo_hi, prefetchable_array_lo_lo)
node prefetchable_array_hi_lo_hi = cat(entries_barrier_8.io.y.c, entries_barrier_7.io.y.c)
node prefetchable_array_hi_lo = cat(prefetchable_array_hi_lo_hi, entries_barrier_6.io.y.c)
node prefetchable_array_hi_hi_hi = cat(entries_barrier_11.io.y.c, entries_barrier_10.io.y.c)
node prefetchable_array_hi_hi = cat(prefetchable_array_hi_hi_hi, entries_barrier_9.io.y.c)
node prefetchable_array_hi = cat(prefetchable_array_hi_hi, prefetchable_array_hi_lo)
node _prefetchable_array_T_2 = cat(prefetchable_array_hi, prefetchable_array_lo)
node prefetchable_array = cat(_prefetchable_array_T_1, _prefetchable_array_T_2)
node _misaligned_T = dshl(UInt<1>(0h1), io.req.bits.size)
node _misaligned_T_1 = sub(_misaligned_T, UInt<1>(0h1))
node _misaligned_T_2 = tail(_misaligned_T_1, 1)
node _misaligned_T_3 = and(io.req.bits.vaddr, _misaligned_T_2)
node misaligned = orr(_misaligned_T_3)
node _bad_va_T = and(vm_enabled, stage1_en)
node bad_va_maskedVAddr = and(io.req.bits.vaddr, UInt<40>(0hc000000000))
node _bad_va_T_1 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _bad_va_T_2 = eq(bad_va_maskedVAddr, UInt<1>(0h0))
node _bad_va_T_3 = eq(bad_va_maskedVAddr, UInt<40>(0hc000000000))
node _bad_va_T_4 = and(UInt<1>(0h1), _bad_va_T_3)
node _bad_va_T_5 = or(_bad_va_T_2, _bad_va_T_4)
node _bad_va_T_6 = eq(_bad_va_T_5, UInt<1>(0h0))
node _bad_va_T_7 = and(_bad_va_T_1, _bad_va_T_6)
node bad_va = and(_bad_va_T, _bad_va_T_7)
node _cmd_lrsc_T = eq(io.req.bits.cmd, UInt<3>(0h6))
node _cmd_lrsc_T_1 = eq(io.req.bits.cmd, UInt<3>(0h7))
node _cmd_lrsc_T_2 = or(_cmd_lrsc_T, _cmd_lrsc_T_1)
node cmd_lrsc = and(UInt<1>(0h0), _cmd_lrsc_T_2)
node _cmd_amo_logical_T = eq(io.req.bits.cmd, UInt<3>(0h4))
node _cmd_amo_logical_T_1 = eq(io.req.bits.cmd, UInt<4>(0h9))
node _cmd_amo_logical_T_2 = eq(io.req.bits.cmd, UInt<4>(0ha))
node _cmd_amo_logical_T_3 = eq(io.req.bits.cmd, UInt<4>(0hb))
node _cmd_amo_logical_T_4 = or(_cmd_amo_logical_T, _cmd_amo_logical_T_1)
node _cmd_amo_logical_T_5 = or(_cmd_amo_logical_T_4, _cmd_amo_logical_T_2)
node _cmd_amo_logical_T_6 = or(_cmd_amo_logical_T_5, _cmd_amo_logical_T_3)
node cmd_amo_logical = and(UInt<1>(0h0), _cmd_amo_logical_T_6)
node _cmd_amo_arithmetic_T = eq(io.req.bits.cmd, UInt<4>(0h8))
node _cmd_amo_arithmetic_T_1 = eq(io.req.bits.cmd, UInt<4>(0hc))
node _cmd_amo_arithmetic_T_2 = eq(io.req.bits.cmd, UInt<4>(0hd))
node _cmd_amo_arithmetic_T_3 = eq(io.req.bits.cmd, UInt<4>(0he))
node _cmd_amo_arithmetic_T_4 = eq(io.req.bits.cmd, UInt<4>(0hf))
node _cmd_amo_arithmetic_T_5 = or(_cmd_amo_arithmetic_T, _cmd_amo_arithmetic_T_1)
node _cmd_amo_arithmetic_T_6 = or(_cmd_amo_arithmetic_T_5, _cmd_amo_arithmetic_T_2)
node _cmd_amo_arithmetic_T_7 = or(_cmd_amo_arithmetic_T_6, _cmd_amo_arithmetic_T_3)
node _cmd_amo_arithmetic_T_8 = or(_cmd_amo_arithmetic_T_7, _cmd_amo_arithmetic_T_4)
node cmd_amo_arithmetic = and(UInt<1>(0h0), _cmd_amo_arithmetic_T_8)
node cmd_put_partial = eq(io.req.bits.cmd, UInt<5>(0h11))
node _cmd_read_T = eq(io.req.bits.cmd, UInt<1>(0h0))
node _cmd_read_T_1 = eq(io.req.bits.cmd, UInt<5>(0h10))
node _cmd_read_T_2 = eq(io.req.bits.cmd, UInt<3>(0h6))
node _cmd_read_T_3 = eq(io.req.bits.cmd, UInt<3>(0h7))
node _cmd_read_T_4 = or(_cmd_read_T, _cmd_read_T_1)
node _cmd_read_T_5 = or(_cmd_read_T_4, _cmd_read_T_2)
node _cmd_read_T_6 = or(_cmd_read_T_5, _cmd_read_T_3)
node _cmd_read_T_7 = eq(io.req.bits.cmd, UInt<3>(0h4))
node _cmd_read_T_8 = eq(io.req.bits.cmd, UInt<4>(0h9))
node _cmd_read_T_9 = eq(io.req.bits.cmd, UInt<4>(0ha))
node _cmd_read_T_10 = eq(io.req.bits.cmd, UInt<4>(0hb))
node _cmd_read_T_11 = or(_cmd_read_T_7, _cmd_read_T_8)
node _cmd_read_T_12 = or(_cmd_read_T_11, _cmd_read_T_9)
node _cmd_read_T_13 = or(_cmd_read_T_12, _cmd_read_T_10)
node _cmd_read_T_14 = eq(io.req.bits.cmd, UInt<4>(0h8))
node _cmd_read_T_15 = eq(io.req.bits.cmd, UInt<4>(0hc))
node _cmd_read_T_16 = eq(io.req.bits.cmd, UInt<4>(0hd))
node _cmd_read_T_17 = eq(io.req.bits.cmd, UInt<4>(0he))
node _cmd_read_T_18 = eq(io.req.bits.cmd, UInt<4>(0hf))
node _cmd_read_T_19 = or(_cmd_read_T_14, _cmd_read_T_15)
node _cmd_read_T_20 = or(_cmd_read_T_19, _cmd_read_T_16)
node _cmd_read_T_21 = or(_cmd_read_T_20, _cmd_read_T_17)
node _cmd_read_T_22 = or(_cmd_read_T_21, _cmd_read_T_18)
node _cmd_read_T_23 = or(_cmd_read_T_13, _cmd_read_T_22)
node cmd_read = or(_cmd_read_T_6, _cmd_read_T_23)
node _cmd_readx_T = eq(io.req.bits.cmd, UInt<5>(0h10))
node cmd_readx = and(UInt<1>(0h0), _cmd_readx_T)
node _cmd_write_T = eq(io.req.bits.cmd, UInt<1>(0h1))
node _cmd_write_T_1 = eq(io.req.bits.cmd, UInt<5>(0h11))
node _cmd_write_T_2 = or(_cmd_write_T, _cmd_write_T_1)
node _cmd_write_T_3 = eq(io.req.bits.cmd, UInt<3>(0h7))
node _cmd_write_T_4 = or(_cmd_write_T_2, _cmd_write_T_3)
node _cmd_write_T_5 = eq(io.req.bits.cmd, UInt<3>(0h4))
node _cmd_write_T_6 = eq(io.req.bits.cmd, UInt<4>(0h9))
node _cmd_write_T_7 = eq(io.req.bits.cmd, UInt<4>(0ha))
node _cmd_write_T_8 = eq(io.req.bits.cmd, UInt<4>(0hb))
node _cmd_write_T_9 = or(_cmd_write_T_5, _cmd_write_T_6)
node _cmd_write_T_10 = or(_cmd_write_T_9, _cmd_write_T_7)
node _cmd_write_T_11 = or(_cmd_write_T_10, _cmd_write_T_8)
node _cmd_write_T_12 = eq(io.req.bits.cmd, UInt<4>(0h8))
node _cmd_write_T_13 = eq(io.req.bits.cmd, UInt<4>(0hc))
node _cmd_write_T_14 = eq(io.req.bits.cmd, UInt<4>(0hd))
node _cmd_write_T_15 = eq(io.req.bits.cmd, UInt<4>(0he))
node _cmd_write_T_16 = eq(io.req.bits.cmd, UInt<4>(0hf))
node _cmd_write_T_17 = or(_cmd_write_T_12, _cmd_write_T_13)
node _cmd_write_T_18 = or(_cmd_write_T_17, _cmd_write_T_14)
node _cmd_write_T_19 = or(_cmd_write_T_18, _cmd_write_T_15)
node _cmd_write_T_20 = or(_cmd_write_T_19, _cmd_write_T_16)
node _cmd_write_T_21 = or(_cmd_write_T_11, _cmd_write_T_20)
node cmd_write = or(_cmd_write_T_4, _cmd_write_T_21)
node _cmd_write_perms_T = eq(io.req.bits.cmd, UInt<3>(0h5))
node _cmd_write_perms_T_1 = eq(io.req.bits.cmd, UInt<5>(0h17))
node _cmd_write_perms_T_2 = or(_cmd_write_perms_T, _cmd_write_perms_T_1)
node cmd_write_perms = or(cmd_write, _cmd_write_perms_T_2)
node lrscAllowed = mux(UInt<1>(0h0), UInt<1>(0h0), c_array)
node _ae_array_T = mux(misaligned, eff_array, UInt<1>(0h0))
node _ae_array_T_1 = not(lrscAllowed)
node _ae_array_T_2 = mux(cmd_lrsc, _ae_array_T_1, UInt<1>(0h0))
node ae_array = or(_ae_array_T, _ae_array_T_2)
node _ae_ld_array_T = not(pr_array)
node _ae_ld_array_T_1 = or(ae_array, _ae_ld_array_T)
node ae_ld_array = mux(cmd_read, _ae_ld_array_T_1, UInt<1>(0h0))
node _ae_st_array_T = not(pw_array)
node _ae_st_array_T_1 = or(ae_array, _ae_st_array_T)
node _ae_st_array_T_2 = mux(cmd_write_perms, _ae_st_array_T_1, UInt<1>(0h0))
node _ae_st_array_T_3 = not(ppp_array_if_cached)
node _ae_st_array_T_4 = mux(cmd_put_partial, _ae_st_array_T_3, UInt<1>(0h0))
node _ae_st_array_T_5 = or(_ae_st_array_T_2, _ae_st_array_T_4)
node _ae_st_array_T_6 = not(pal_array_if_cached)
node _ae_st_array_T_7 = mux(cmd_amo_logical, _ae_st_array_T_6, UInt<1>(0h0))
node _ae_st_array_T_8 = or(_ae_st_array_T_5, _ae_st_array_T_7)
node _ae_st_array_T_9 = not(paa_array_if_cached)
node _ae_st_array_T_10 = mux(cmd_amo_arithmetic, _ae_st_array_T_9, UInt<1>(0h0))
node ae_st_array = or(_ae_st_array_T_8, _ae_st_array_T_10)
node _must_alloc_array_T = not(ppp_array)
node _must_alloc_array_T_1 = mux(cmd_put_partial, _must_alloc_array_T, UInt<1>(0h0))
node _must_alloc_array_T_2 = not(pal_array)
node _must_alloc_array_T_3 = mux(cmd_amo_logical, _must_alloc_array_T_2, UInt<1>(0h0))
node _must_alloc_array_T_4 = or(_must_alloc_array_T_1, _must_alloc_array_T_3)
node _must_alloc_array_T_5 = not(paa_array)
node _must_alloc_array_T_6 = mux(cmd_amo_arithmetic, _must_alloc_array_T_5, UInt<1>(0h0))
node _must_alloc_array_T_7 = or(_must_alloc_array_T_4, _must_alloc_array_T_6)
node _must_alloc_array_T_8 = not(UInt<14>(0h0))
node _must_alloc_array_T_9 = mux(cmd_lrsc, _must_alloc_array_T_8, UInt<1>(0h0))
node must_alloc_array = or(_must_alloc_array_T_7, _must_alloc_array_T_9)
node _pf_ld_array_T = mux(cmd_readx, x_array, r_array)
node _pf_ld_array_T_1 = not(_pf_ld_array_T)
node _pf_ld_array_T_2 = not(ptw_ae_array)
node _pf_ld_array_T_3 = and(_pf_ld_array_T_1, _pf_ld_array_T_2)
node _pf_ld_array_T_4 = or(_pf_ld_array_T_3, ptw_pf_array)
node _pf_ld_array_T_5 = not(ptw_gf_array)
node _pf_ld_array_T_6 = and(_pf_ld_array_T_4, _pf_ld_array_T_5)
node pf_ld_array = mux(cmd_read, _pf_ld_array_T_6, UInt<1>(0h0))
node _pf_st_array_T = not(w_array)
node _pf_st_array_T_1 = not(ptw_ae_array)
node _pf_st_array_T_2 = and(_pf_st_array_T, _pf_st_array_T_1)
node _pf_st_array_T_3 = or(_pf_st_array_T_2, ptw_pf_array)
node _pf_st_array_T_4 = not(ptw_gf_array)
node _pf_st_array_T_5 = and(_pf_st_array_T_3, _pf_st_array_T_4)
node pf_st_array = mux(cmd_write_perms, _pf_st_array_T_5, UInt<1>(0h0))
node _pf_inst_array_T = not(x_array)
node _pf_inst_array_T_1 = not(ptw_ae_array)
node _pf_inst_array_T_2 = and(_pf_inst_array_T, _pf_inst_array_T_1)
node _pf_inst_array_T_3 = or(_pf_inst_array_T_2, ptw_pf_array)
node _pf_inst_array_T_4 = not(ptw_gf_array)
node pf_inst_array = and(_pf_inst_array_T_3, _pf_inst_array_T_4)
node _gf_ld_array_T = and(priv_v, cmd_read)
node _gf_ld_array_T_1 = mux(cmd_readx, hx_array, hr_array)
node _gf_ld_array_T_2 = not(_gf_ld_array_T_1)
node _gf_ld_array_T_3 = or(_gf_ld_array_T_2, ptw_gf_array)
node _gf_ld_array_T_4 = not(ptw_ae_array)
node _gf_ld_array_T_5 = and(_gf_ld_array_T_3, _gf_ld_array_T_4)
node gf_ld_array = mux(_gf_ld_array_T, _gf_ld_array_T_5, UInt<1>(0h0))
node _gf_st_array_T = and(priv_v, cmd_write_perms)
node _gf_st_array_T_1 = not(hw_array)
node _gf_st_array_T_2 = or(_gf_st_array_T_1, ptw_gf_array)
node _gf_st_array_T_3 = not(ptw_ae_array)
node _gf_st_array_T_4 = and(_gf_st_array_T_2, _gf_st_array_T_3)
node gf_st_array = mux(_gf_st_array_T, _gf_st_array_T_4, UInt<1>(0h0))
node _gf_inst_array_T = not(hx_array)
node _gf_inst_array_T_1 = or(_gf_inst_array_T, ptw_gf_array)
node _gf_inst_array_T_2 = not(ptw_ae_array)
node _gf_inst_array_T_3 = and(_gf_inst_array_T_1, _gf_inst_array_T_2)
node gf_inst_array = mux(priv_v, _gf_inst_array_T_3, UInt<1>(0h0))
node gpa_hits_need_gpa_mask = or(gf_ld_array, gf_st_array)
node _gpa_hits_hit_mask_T = eq(r_gpa_vpn, vpn)
node _gpa_hits_hit_mask_T_1 = and(r_gpa_valid, _gpa_hits_hit_mask_T)
node _gpa_hits_hit_mask_T_2 = mux(_gpa_hits_hit_mask_T_1, UInt<12>(0hfff), UInt<12>(0h0))
node _gpa_hits_hit_mask_T_3 = eq(vstage1_en, UInt<1>(0h0))
node _gpa_hits_hit_mask_T_4 = mux(_gpa_hits_hit_mask_T_3, UInt<13>(0h1fff), UInt<13>(0h0))
node gpa_hits_hit_mask = or(_gpa_hits_hit_mask_T_2, _gpa_hits_hit_mask_T_4)
node _gpa_hits_T = bits(gpa_hits_need_gpa_mask, 12, 0)
node _gpa_hits_T_1 = not(_gpa_hits_T)
node gpa_hits = or(gpa_hits_hit_mask, _gpa_hits_T_1)
node tlb_hit_if_not_gpa_miss = orr(real_hits)
node _tlb_hit_T = and(real_hits, gpa_hits)
node tlb_hit = orr(_tlb_hit_T)
node _tlb_miss_T = eq(vsatp_mode_mismatch, UInt<1>(0h0))
node _tlb_miss_T_1 = and(vm_enabled, _tlb_miss_T)
node _tlb_miss_T_2 = eq(bad_va, UInt<1>(0h0))
node _tlb_miss_T_3 = and(_tlb_miss_T_1, _tlb_miss_T_2)
node _tlb_miss_T_4 = eq(tlb_hit, UInt<1>(0h0))
node tlb_miss = and(_tlb_miss_T_3, _tlb_miss_T_4)
regreset state_reg : UInt<7>, clock, reset, UInt<7>(0h0)
wire _state_vec_WIRE : UInt<7>[1]
connect _state_vec_WIRE[0], UInt<7>(0h0)
regreset state_vec : UInt<7>[1], clock, reset, _state_vec_WIRE
regreset state_reg_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _T_23 = and(io.req.valid, vm_enabled)
when _T_23 :
node _T_24 = or(sector_hits_0, sector_hits_1)
node _T_25 = or(_T_24, sector_hits_2)
node _T_26 = or(_T_25, sector_hits_3)
node _T_27 = or(_T_26, sector_hits_4)
node _T_28 = or(_T_27, sector_hits_5)
node _T_29 = or(_T_28, sector_hits_6)
node _T_30 = or(_T_29, sector_hits_7)
when _T_30 :
node lo_lo = cat(sector_hits_1, sector_hits_0)
node lo_hi = cat(sector_hits_3, sector_hits_2)
node lo = cat(lo_hi, lo_lo)
node hi_lo = cat(sector_hits_5, sector_hits_4)
node hi_hi = cat(sector_hits_7, sector_hits_6)
node hi = cat(hi_hi, hi_lo)
node _T_31 = cat(hi, lo)
node hi_1 = bits(_T_31, 7, 4)
node lo_1 = bits(_T_31, 3, 0)
node _T_32 = orr(hi_1)
node _T_33 = or(hi_1, lo_1)
node hi_2 = bits(_T_33, 3, 2)
node lo_2 = bits(_T_33, 1, 0)
node _T_34 = orr(hi_2)
node _T_35 = or(hi_2, lo_2)
node _T_36 = bits(_T_35, 1, 1)
node _T_37 = cat(_T_34, _T_36)
node _T_38 = cat(_T_32, _T_37)
node state_vec_0_touch_way_sized = bits(_T_38, 2, 0)
node _state_vec_0_set_left_older_T = bits(state_vec_0_touch_way_sized, 2, 2)
node state_vec_0_set_left_older = eq(_state_vec_0_set_left_older_T, UInt<1>(0h0))
node state_vec_0_left_subtree_state = bits(state_vec[0], 5, 3)
node state_vec_0_right_subtree_state = bits(state_vec[0], 2, 0)
node _state_vec_0_T = bits(state_vec_0_touch_way_sized, 1, 0)
node _state_vec_0_set_left_older_T_1 = bits(_state_vec_0_T, 1, 1)
node state_vec_0_set_left_older_1 = eq(_state_vec_0_set_left_older_T_1, UInt<1>(0h0))
node state_vec_0_left_subtree_state_1 = bits(state_vec_0_left_subtree_state, 1, 1)
node state_vec_0_right_subtree_state_1 = bits(state_vec_0_left_subtree_state, 0, 0)
node _state_vec_0_T_1 = bits(_state_vec_0_T, 0, 0)
node _state_vec_0_T_2 = bits(_state_vec_0_T_1, 0, 0)
node _state_vec_0_T_3 = eq(_state_vec_0_T_2, UInt<1>(0h0))
node _state_vec_0_T_4 = mux(state_vec_0_set_left_older_1, state_vec_0_left_subtree_state_1, _state_vec_0_T_3)
node _state_vec_0_T_5 = bits(_state_vec_0_T, 0, 0)
node _state_vec_0_T_6 = bits(_state_vec_0_T_5, 0, 0)
node _state_vec_0_T_7 = eq(_state_vec_0_T_6, UInt<1>(0h0))
node _state_vec_0_T_8 = mux(state_vec_0_set_left_older_1, _state_vec_0_T_7, state_vec_0_right_subtree_state_1)
node state_vec_0_hi = cat(state_vec_0_set_left_older_1, _state_vec_0_T_4)
node _state_vec_0_T_9 = cat(state_vec_0_hi, _state_vec_0_T_8)
node _state_vec_0_T_10 = mux(state_vec_0_set_left_older, state_vec_0_left_subtree_state, _state_vec_0_T_9)
node _state_vec_0_T_11 = bits(state_vec_0_touch_way_sized, 1, 0)
node _state_vec_0_set_left_older_T_2 = bits(_state_vec_0_T_11, 1, 1)
node state_vec_0_set_left_older_2 = eq(_state_vec_0_set_left_older_T_2, UInt<1>(0h0))
node state_vec_0_left_subtree_state_2 = bits(state_vec_0_right_subtree_state, 1, 1)
node state_vec_0_right_subtree_state_2 = bits(state_vec_0_right_subtree_state, 0, 0)
node _state_vec_0_T_12 = bits(_state_vec_0_T_11, 0, 0)
node _state_vec_0_T_13 = bits(_state_vec_0_T_12, 0, 0)
node _state_vec_0_T_14 = eq(_state_vec_0_T_13, UInt<1>(0h0))
node _state_vec_0_T_15 = mux(state_vec_0_set_left_older_2, state_vec_0_left_subtree_state_2, _state_vec_0_T_14)
node _state_vec_0_T_16 = bits(_state_vec_0_T_11, 0, 0)
node _state_vec_0_T_17 = bits(_state_vec_0_T_16, 0, 0)
node _state_vec_0_T_18 = eq(_state_vec_0_T_17, UInt<1>(0h0))
node _state_vec_0_T_19 = mux(state_vec_0_set_left_older_2, _state_vec_0_T_18, state_vec_0_right_subtree_state_2)
node state_vec_0_hi_1 = cat(state_vec_0_set_left_older_2, _state_vec_0_T_15)
node _state_vec_0_T_20 = cat(state_vec_0_hi_1, _state_vec_0_T_19)
node _state_vec_0_T_21 = mux(state_vec_0_set_left_older, _state_vec_0_T_20, state_vec_0_right_subtree_state)
node state_vec_0_hi_2 = cat(state_vec_0_set_left_older, _state_vec_0_T_10)
node _state_vec_0_T_22 = cat(state_vec_0_hi_2, _state_vec_0_T_21)
connect state_vec[0], _state_vec_0_T_22
node _T_39 = or(superpage_hits_0, superpage_hits_1)
node _T_40 = or(_T_39, superpage_hits_2)
node _T_41 = or(_T_40, superpage_hits_3)
when _T_41 :
node lo_3 = cat(superpage_hits_1, superpage_hits_0)
node hi_3 = cat(superpage_hits_3, superpage_hits_2)
node _T_42 = cat(hi_3, lo_3)
node hi_4 = bits(_T_42, 3, 2)
node lo_4 = bits(_T_42, 1, 0)
node _T_43 = orr(hi_4)
node _T_44 = or(hi_4, lo_4)
node _T_45 = bits(_T_44, 1, 1)
node _T_46 = cat(_T_43, _T_45)
node state_reg_touch_way_sized = bits(_T_46, 1, 0)
node _state_reg_set_left_older_T = bits(state_reg_touch_way_sized, 1, 1)
node state_reg_set_left_older = eq(_state_reg_set_left_older_T, UInt<1>(0h0))
node state_reg_left_subtree_state = bits(state_reg_1, 1, 1)
node state_reg_right_subtree_state = bits(state_reg_1, 0, 0)
node _state_reg_T = bits(state_reg_touch_way_sized, 0, 0)
node _state_reg_T_1 = bits(_state_reg_T, 0, 0)
node _state_reg_T_2 = eq(_state_reg_T_1, UInt<1>(0h0))
node _state_reg_T_3 = mux(state_reg_set_left_older, state_reg_left_subtree_state, _state_reg_T_2)
node _state_reg_T_4 = bits(state_reg_touch_way_sized, 0, 0)
node _state_reg_T_5 = bits(_state_reg_T_4, 0, 0)
node _state_reg_T_6 = eq(_state_reg_T_5, UInt<1>(0h0))
node _state_reg_T_7 = mux(state_reg_set_left_older, _state_reg_T_6, state_reg_right_subtree_state)
node state_reg_hi = cat(state_reg_set_left_older, _state_reg_T_3)
node _state_reg_T_8 = cat(state_reg_hi, _state_reg_T_7)
connect state_reg_1, _state_reg_T_8
node _multipleHits_T = bits(real_hits, 5, 0)
node _multipleHits_T_1 = bits(_multipleHits_T, 2, 0)
node _multipleHits_T_2 = bits(_multipleHits_T_1, 0, 0)
node multipleHits_leftOne = bits(_multipleHits_T_2, 0, 0)
node _multipleHits_T_3 = bits(_multipleHits_T_1, 2, 1)
node _multipleHits_T_4 = bits(_multipleHits_T_3, 0, 0)
node multipleHits_leftOne_1 = bits(_multipleHits_T_4, 0, 0)
node _multipleHits_T_5 = bits(_multipleHits_T_3, 1, 1)
node multipleHits_rightOne = bits(_multipleHits_T_5, 0, 0)
node multipleHits_rightOne_1 = or(multipleHits_leftOne_1, multipleHits_rightOne)
node _multipleHits_T_6 = or(UInt<1>(0h0), UInt<1>(0h0))
node _multipleHits_T_7 = and(multipleHits_leftOne_1, multipleHits_rightOne)
node multipleHits_rightTwo = or(_multipleHits_T_6, _multipleHits_T_7)
node multipleHits_leftOne_2 = or(multipleHits_leftOne, multipleHits_rightOne_1)
node _multipleHits_T_8 = or(UInt<1>(0h0), multipleHits_rightTwo)
node _multipleHits_T_9 = and(multipleHits_leftOne, multipleHits_rightOne_1)
node multipleHits_leftTwo = or(_multipleHits_T_8, _multipleHits_T_9)
node _multipleHits_T_10 = bits(_multipleHits_T, 5, 3)
node _multipleHits_T_11 = bits(_multipleHits_T_10, 0, 0)
node multipleHits_leftOne_3 = bits(_multipleHits_T_11, 0, 0)
node _multipleHits_T_12 = bits(_multipleHits_T_10, 2, 1)
node _multipleHits_T_13 = bits(_multipleHits_T_12, 0, 0)
node multipleHits_leftOne_4 = bits(_multipleHits_T_13, 0, 0)
node _multipleHits_T_14 = bits(_multipleHits_T_12, 1, 1)
node multipleHits_rightOne_2 = bits(_multipleHits_T_14, 0, 0)
node multipleHits_rightOne_3 = or(multipleHits_leftOne_4, multipleHits_rightOne_2)
node _multipleHits_T_15 = or(UInt<1>(0h0), UInt<1>(0h0))
node _multipleHits_T_16 = and(multipleHits_leftOne_4, multipleHits_rightOne_2)
node multipleHits_rightTwo_1 = or(_multipleHits_T_15, _multipleHits_T_16)
node multipleHits_rightOne_4 = or(multipleHits_leftOne_3, multipleHits_rightOne_3)
node _multipleHits_T_17 = or(UInt<1>(0h0), multipleHits_rightTwo_1)
node _multipleHits_T_18 = and(multipleHits_leftOne_3, multipleHits_rightOne_3)
node multipleHits_rightTwo_2 = or(_multipleHits_T_17, _multipleHits_T_18)
node multipleHits_leftOne_5 = or(multipleHits_leftOne_2, multipleHits_rightOne_4)
node _multipleHits_T_19 = or(multipleHits_leftTwo, multipleHits_rightTwo_2)
node _multipleHits_T_20 = and(multipleHits_leftOne_2, multipleHits_rightOne_4)
node multipleHits_leftTwo_1 = or(_multipleHits_T_19, _multipleHits_T_20)
node _multipleHits_T_21 = bits(real_hits, 12, 6)
node _multipleHits_T_22 = bits(_multipleHits_T_21, 2, 0)
node _multipleHits_T_23 = bits(_multipleHits_T_22, 0, 0)
node multipleHits_leftOne_6 = bits(_multipleHits_T_23, 0, 0)
node _multipleHits_T_24 = bits(_multipleHits_T_22, 2, 1)
node _multipleHits_T_25 = bits(_multipleHits_T_24, 0, 0)
node multipleHits_leftOne_7 = bits(_multipleHits_T_25, 0, 0)
node _multipleHits_T_26 = bits(_multipleHits_T_24, 1, 1)
node multipleHits_rightOne_5 = bits(_multipleHits_T_26, 0, 0)
node multipleHits_rightOne_6 = or(multipleHits_leftOne_7, multipleHits_rightOne_5)
node _multipleHits_T_27 = or(UInt<1>(0h0), UInt<1>(0h0))
node _multipleHits_T_28 = and(multipleHits_leftOne_7, multipleHits_rightOne_5)
node multipleHits_rightTwo_3 = or(_multipleHits_T_27, _multipleHits_T_28)
node multipleHits_leftOne_8 = or(multipleHits_leftOne_6, multipleHits_rightOne_6)
node _multipleHits_T_29 = or(UInt<1>(0h0), multipleHits_rightTwo_3)
node _multipleHits_T_30 = and(multipleHits_leftOne_6, multipleHits_rightOne_6)
node multipleHits_leftTwo_2 = or(_multipleHits_T_29, _multipleHits_T_30)
node _multipleHits_T_31 = bits(_multipleHits_T_21, 6, 3)
node _multipleHits_T_32 = bits(_multipleHits_T_31, 1, 0)
node _multipleHits_T_33 = bits(_multipleHits_T_32, 0, 0)
node multipleHits_leftOne_9 = bits(_multipleHits_T_33, 0, 0)
node _multipleHits_T_34 = bits(_multipleHits_T_32, 1, 1)
node multipleHits_rightOne_7 = bits(_multipleHits_T_34, 0, 0)
node multipleHits_leftOne_10 = or(multipleHits_leftOne_9, multipleHits_rightOne_7)
node _multipleHits_T_35 = or(UInt<1>(0h0), UInt<1>(0h0))
node _multipleHits_T_36 = and(multipleHits_leftOne_9, multipleHits_rightOne_7)
node multipleHits_leftTwo_3 = or(_multipleHits_T_35, _multipleHits_T_36)
node _multipleHits_T_37 = bits(_multipleHits_T_31, 3, 2)
node _multipleHits_T_38 = bits(_multipleHits_T_37, 0, 0)
node multipleHits_leftOne_11 = bits(_multipleHits_T_38, 0, 0)
node _multipleHits_T_39 = bits(_multipleHits_T_37, 1, 1)
node multipleHits_rightOne_8 = bits(_multipleHits_T_39, 0, 0)
node multipleHits_rightOne_9 = or(multipleHits_leftOne_11, multipleHits_rightOne_8)
node _multipleHits_T_40 = or(UInt<1>(0h0), UInt<1>(0h0))
node _multipleHits_T_41 = and(multipleHits_leftOne_11, multipleHits_rightOne_8)
node multipleHits_rightTwo_4 = or(_multipleHits_T_40, _multipleHits_T_41)
node multipleHits_rightOne_10 = or(multipleHits_leftOne_10, multipleHits_rightOne_9)
node _multipleHits_T_42 = or(multipleHits_leftTwo_3, multipleHits_rightTwo_4)
node _multipleHits_T_43 = and(multipleHits_leftOne_10, multipleHits_rightOne_9)
node multipleHits_rightTwo_5 = or(_multipleHits_T_42, _multipleHits_T_43)
node multipleHits_rightOne_11 = or(multipleHits_leftOne_8, multipleHits_rightOne_10)
node _multipleHits_T_44 = or(multipleHits_leftTwo_2, multipleHits_rightTwo_5)
node _multipleHits_T_45 = and(multipleHits_leftOne_8, multipleHits_rightOne_10)
node multipleHits_rightTwo_6 = or(_multipleHits_T_44, _multipleHits_T_45)
node _multipleHits_T_46 = or(multipleHits_leftOne_5, multipleHits_rightOne_11)
node _multipleHits_T_47 = or(multipleHits_leftTwo_1, multipleHits_rightTwo_6)
node _multipleHits_T_48 = and(multipleHits_leftOne_5, multipleHits_rightOne_11)
node multipleHits = or(_multipleHits_T_47, _multipleHits_T_48)
node _io_req_ready_T = eq(state, UInt<2>(0h0))
connect io.req.ready, _io_req_ready_T
node _io_resp_pf_ld_T = and(bad_va, cmd_read)
node _io_resp_pf_ld_T_1 = and(pf_ld_array, hits)
node _io_resp_pf_ld_T_2 = orr(_io_resp_pf_ld_T_1)
node _io_resp_pf_ld_T_3 = or(_io_resp_pf_ld_T, _io_resp_pf_ld_T_2)
connect io.resp.pf.ld, _io_resp_pf_ld_T_3
node _io_resp_pf_st_T = and(bad_va, cmd_write_perms)
node _io_resp_pf_st_T_1 = and(pf_st_array, hits)
node _io_resp_pf_st_T_2 = orr(_io_resp_pf_st_T_1)
node _io_resp_pf_st_T_3 = or(_io_resp_pf_st_T, _io_resp_pf_st_T_2)
connect io.resp.pf.st, _io_resp_pf_st_T_3
node _io_resp_pf_inst_T = and(pf_inst_array, hits)
node _io_resp_pf_inst_T_1 = orr(_io_resp_pf_inst_T)
node _io_resp_pf_inst_T_2 = or(bad_va, _io_resp_pf_inst_T_1)
connect io.resp.pf.inst, _io_resp_pf_inst_T_2
node _io_resp_gf_ld_T = and(UInt<1>(0h0), cmd_read)
node _io_resp_gf_ld_T_1 = and(gf_ld_array, hits)
node _io_resp_gf_ld_T_2 = orr(_io_resp_gf_ld_T_1)
node _io_resp_gf_ld_T_3 = or(_io_resp_gf_ld_T, _io_resp_gf_ld_T_2)
connect io.resp.gf.ld, _io_resp_gf_ld_T_3
node _io_resp_gf_st_T = and(UInt<1>(0h0), cmd_write_perms)
node _io_resp_gf_st_T_1 = and(gf_st_array, hits)
node _io_resp_gf_st_T_2 = orr(_io_resp_gf_st_T_1)
node _io_resp_gf_st_T_3 = or(_io_resp_gf_st_T, _io_resp_gf_st_T_2)
connect io.resp.gf.st, _io_resp_gf_st_T_3
node _io_resp_gf_inst_T = and(gf_inst_array, hits)
node _io_resp_gf_inst_T_1 = orr(_io_resp_gf_inst_T)
node _io_resp_gf_inst_T_2 = or(UInt<1>(0h0), _io_resp_gf_inst_T_1)
connect io.resp.gf.inst, _io_resp_gf_inst_T_2
node _io_resp_ae_ld_T = and(ae_ld_array, hits)
node _io_resp_ae_ld_T_1 = orr(_io_resp_ae_ld_T)
connect io.resp.ae.ld, _io_resp_ae_ld_T_1
node _io_resp_ae_st_T = and(ae_st_array, hits)
node _io_resp_ae_st_T_1 = orr(_io_resp_ae_st_T)
connect io.resp.ae.st, _io_resp_ae_st_T_1
node _io_resp_ae_inst_T = not(px_array)
node _io_resp_ae_inst_T_1 = and(_io_resp_ae_inst_T, hits)
node _io_resp_ae_inst_T_2 = orr(_io_resp_ae_inst_T_1)
connect io.resp.ae.inst, _io_resp_ae_inst_T_2
node _io_resp_ma_ld_T = and(misaligned, cmd_read)
connect io.resp.ma.ld, _io_resp_ma_ld_T
node _io_resp_ma_st_T = and(misaligned, cmd_write)
connect io.resp.ma.st, _io_resp_ma_st_T
connect io.resp.ma.inst, UInt<1>(0h0)
node _io_resp_cacheable_T = and(c_array, hits)
node _io_resp_cacheable_T_1 = orr(_io_resp_cacheable_T)
connect io.resp.cacheable, _io_resp_cacheable_T_1
node _io_resp_must_alloc_T = and(must_alloc_array, hits)
node _io_resp_must_alloc_T_1 = orr(_io_resp_must_alloc_T)
connect io.resp.must_alloc, _io_resp_must_alloc_T_1
node _io_resp_prefetchable_T = and(prefetchable_array, hits)
node _io_resp_prefetchable_T_1 = orr(_io_resp_prefetchable_T)
node _io_resp_prefetchable_T_2 = and(_io_resp_prefetchable_T_1, UInt<1>(0h1))
connect io.resp.prefetchable, _io_resp_prefetchable_T_2
node _io_resp_miss_T = or(do_refill, vsatp_mode_mismatch)
node _io_resp_miss_T_1 = or(_io_resp_miss_T, tlb_miss)
node _io_resp_miss_T_2 = or(_io_resp_miss_T_1, multipleHits)
connect io.resp.miss, _io_resp_miss_T_2
node _io_resp_paddr_T = bits(io.req.bits.vaddr, 11, 0)
node _io_resp_paddr_T_1 = cat(ppn, _io_resp_paddr_T)
connect io.resp.paddr, _io_resp_paddr_T_1
connect io.resp.size, io.req.bits.size
connect io.resp.cmd, io.req.bits.cmd
node _io_resp_gpa_is_pte_T = and(vstage1_en, r_gpa_is_pte)
connect io.resp.gpa_is_pte, _io_resp_gpa_is_pte_T
node _io_resp_gpa_page_T = eq(vstage1_en, UInt<1>(0h0))
node _io_resp_gpa_page_T_1 = cat(UInt<1>(0h0), vpn)
node _io_resp_gpa_page_T_2 = shr(r_gpa, 12)
node io_resp_gpa_page = mux(_io_resp_gpa_page_T, _io_resp_gpa_page_T_1, _io_resp_gpa_page_T_2)
node _io_resp_gpa_offset_T = bits(r_gpa, 11, 0)
node _io_resp_gpa_offset_T_1 = bits(io.req.bits.vaddr, 11, 0)
node io_resp_gpa_offset = mux(io.resp.gpa_is_pte, _io_resp_gpa_offset_T, _io_resp_gpa_offset_T_1)
node _io_resp_gpa_T = cat(io_resp_gpa_page, io_resp_gpa_offset)
connect io.resp.gpa, _io_resp_gpa_T
node _io_ptw_req_valid_T = eq(state, UInt<2>(0h1))
connect io.ptw.req.valid, _io_ptw_req_valid_T
node _io_ptw_req_bits_valid_T = eq(io.kill, UInt<1>(0h0))
connect io.ptw.req.bits.valid, _io_ptw_req_bits_valid_T
connect io.ptw.req.bits.bits.addr, r_refill_tag
connect io.ptw.req.bits.bits.vstage1, r_vstage1_en
connect io.ptw.req.bits.bits.stage2, r_stage2_en
connect io.ptw.req.bits.bits.need_gpa, r_need_gpa
node _T_47 = and(io.ptw.req.ready, io.ptw.req.valid)
node _T_48 = and(_T_47, io.ptw.req.bits.valid)
when _T_48 :
connect r_gpa_valid, UInt<1>(0h0)
connect r_gpa_vpn, r_refill_tag
node _T_49 = and(io.req.ready, io.req.valid)
node _T_50 = and(_T_49, tlb_miss)
when _T_50 :
connect state, UInt<2>(0h1)
connect r_refill_tag, vpn
connect r_need_gpa, tlb_hit_if_not_gpa_miss
connect r_vstage1_en, vstage1_en
connect r_stage2_en, stage2_en
node r_superpage_repl_addr_left_subtree_older = bits(state_reg_1, 2, 2)
node r_superpage_repl_addr_left_subtree_state = bits(state_reg_1, 1, 1)
node r_superpage_repl_addr_right_subtree_state = bits(state_reg_1, 0, 0)
node _r_superpage_repl_addr_T = bits(r_superpage_repl_addr_left_subtree_state, 0, 0)
node _r_superpage_repl_addr_T_1 = bits(r_superpage_repl_addr_right_subtree_state, 0, 0)
node _r_superpage_repl_addr_T_2 = mux(r_superpage_repl_addr_left_subtree_older, _r_superpage_repl_addr_T, _r_superpage_repl_addr_T_1)
node _r_superpage_repl_addr_T_3 = cat(r_superpage_repl_addr_left_subtree_older, _r_superpage_repl_addr_T_2)
node r_superpage_repl_addr_valids_lo = cat(superpage_entries[1].valid[0], superpage_entries[0].valid[0])
node r_superpage_repl_addr_valids_hi = cat(superpage_entries[3].valid[0], superpage_entries[2].valid[0])
node r_superpage_repl_addr_valids = cat(r_superpage_repl_addr_valids_hi, r_superpage_repl_addr_valids_lo)
node _r_superpage_repl_addr_T_4 = andr(r_superpage_repl_addr_valids)
node _r_superpage_repl_addr_T_5 = not(r_superpage_repl_addr_valids)
node _r_superpage_repl_addr_T_6 = bits(_r_superpage_repl_addr_T_5, 0, 0)
node _r_superpage_repl_addr_T_7 = bits(_r_superpage_repl_addr_T_5, 1, 1)
node _r_superpage_repl_addr_T_8 = bits(_r_superpage_repl_addr_T_5, 2, 2)
node _r_superpage_repl_addr_T_9 = bits(_r_superpage_repl_addr_T_5, 3, 3)
node _r_superpage_repl_addr_T_10 = mux(_r_superpage_repl_addr_T_8, UInt<2>(0h2), UInt<2>(0h3))
node _r_superpage_repl_addr_T_11 = mux(_r_superpage_repl_addr_T_7, UInt<1>(0h1), _r_superpage_repl_addr_T_10)
node _r_superpage_repl_addr_T_12 = mux(_r_superpage_repl_addr_T_6, UInt<1>(0h0), _r_superpage_repl_addr_T_11)
node _r_superpage_repl_addr_T_13 = mux(_r_superpage_repl_addr_T_4, _r_superpage_repl_addr_T_3, _r_superpage_repl_addr_T_12)
connect r_superpage_repl_addr, _r_superpage_repl_addr_T_13
node r_sectored_repl_addr_left_subtree_older = bits(state_vec[0], 6, 6)
node r_sectored_repl_addr_left_subtree_state = bits(state_vec[0], 5, 3)
node r_sectored_repl_addr_right_subtree_state = bits(state_vec[0], 2, 0)
node r_sectored_repl_addr_left_subtree_older_1 = bits(r_sectored_repl_addr_left_subtree_state, 2, 2)
node r_sectored_repl_addr_left_subtree_state_1 = bits(r_sectored_repl_addr_left_subtree_state, 1, 1)
node r_sectored_repl_addr_right_subtree_state_1 = bits(r_sectored_repl_addr_left_subtree_state, 0, 0)
node _r_sectored_repl_addr_T = bits(r_sectored_repl_addr_left_subtree_state_1, 0, 0)
node _r_sectored_repl_addr_T_1 = bits(r_sectored_repl_addr_right_subtree_state_1, 0, 0)
node _r_sectored_repl_addr_T_2 = mux(r_sectored_repl_addr_left_subtree_older_1, _r_sectored_repl_addr_T, _r_sectored_repl_addr_T_1)
node _r_sectored_repl_addr_T_3 = cat(r_sectored_repl_addr_left_subtree_older_1, _r_sectored_repl_addr_T_2)
node r_sectored_repl_addr_left_subtree_older_2 = bits(r_sectored_repl_addr_right_subtree_state, 2, 2)
node r_sectored_repl_addr_left_subtree_state_2 = bits(r_sectored_repl_addr_right_subtree_state, 1, 1)
node r_sectored_repl_addr_right_subtree_state_2 = bits(r_sectored_repl_addr_right_subtree_state, 0, 0)
node _r_sectored_repl_addr_T_4 = bits(r_sectored_repl_addr_left_subtree_state_2, 0, 0)
node _r_sectored_repl_addr_T_5 = bits(r_sectored_repl_addr_right_subtree_state_2, 0, 0)
node _r_sectored_repl_addr_T_6 = mux(r_sectored_repl_addr_left_subtree_older_2, _r_sectored_repl_addr_T_4, _r_sectored_repl_addr_T_5)
node _r_sectored_repl_addr_T_7 = cat(r_sectored_repl_addr_left_subtree_older_2, _r_sectored_repl_addr_T_6)
node _r_sectored_repl_addr_T_8 = mux(r_sectored_repl_addr_left_subtree_older, _r_sectored_repl_addr_T_3, _r_sectored_repl_addr_T_7)
node _r_sectored_repl_addr_T_9 = cat(r_sectored_repl_addr_left_subtree_older, _r_sectored_repl_addr_T_8)
node _r_sectored_repl_addr_valids_T = or(sectored_entries[0][0].valid[0], sectored_entries[0][0].valid[1])
node _r_sectored_repl_addr_valids_T_1 = or(_r_sectored_repl_addr_valids_T, sectored_entries[0][0].valid[2])
node _r_sectored_repl_addr_valids_T_2 = or(_r_sectored_repl_addr_valids_T_1, sectored_entries[0][0].valid[3])
node _r_sectored_repl_addr_valids_T_3 = or(sectored_entries[0][1].valid[0], sectored_entries[0][1].valid[1])
node _r_sectored_repl_addr_valids_T_4 = or(_r_sectored_repl_addr_valids_T_3, sectored_entries[0][1].valid[2])
node _r_sectored_repl_addr_valids_T_5 = or(_r_sectored_repl_addr_valids_T_4, sectored_entries[0][1].valid[3])
node _r_sectored_repl_addr_valids_T_6 = or(sectored_entries[0][2].valid[0], sectored_entries[0][2].valid[1])
node _r_sectored_repl_addr_valids_T_7 = or(_r_sectored_repl_addr_valids_T_6, sectored_entries[0][2].valid[2])
node _r_sectored_repl_addr_valids_T_8 = or(_r_sectored_repl_addr_valids_T_7, sectored_entries[0][2].valid[3])
node _r_sectored_repl_addr_valids_T_9 = or(sectored_entries[0][3].valid[0], sectored_entries[0][3].valid[1])
node _r_sectored_repl_addr_valids_T_10 = or(_r_sectored_repl_addr_valids_T_9, sectored_entries[0][3].valid[2])
node _r_sectored_repl_addr_valids_T_11 = or(_r_sectored_repl_addr_valids_T_10, sectored_entries[0][3].valid[3])
node _r_sectored_repl_addr_valids_T_12 = or(sectored_entries[0][4].valid[0], sectored_entries[0][4].valid[1])
node _r_sectored_repl_addr_valids_T_13 = or(_r_sectored_repl_addr_valids_T_12, sectored_entries[0][4].valid[2])
node _r_sectored_repl_addr_valids_T_14 = or(_r_sectored_repl_addr_valids_T_13, sectored_entries[0][4].valid[3])
node _r_sectored_repl_addr_valids_T_15 = or(sectored_entries[0][5].valid[0], sectored_entries[0][5].valid[1])
node _r_sectored_repl_addr_valids_T_16 = or(_r_sectored_repl_addr_valids_T_15, sectored_entries[0][5].valid[2])
node _r_sectored_repl_addr_valids_T_17 = or(_r_sectored_repl_addr_valids_T_16, sectored_entries[0][5].valid[3])
node _r_sectored_repl_addr_valids_T_18 = or(sectored_entries[0][6].valid[0], sectored_entries[0][6].valid[1])
node _r_sectored_repl_addr_valids_T_19 = or(_r_sectored_repl_addr_valids_T_18, sectored_entries[0][6].valid[2])
node _r_sectored_repl_addr_valids_T_20 = or(_r_sectored_repl_addr_valids_T_19, sectored_entries[0][6].valid[3])
node _r_sectored_repl_addr_valids_T_21 = or(sectored_entries[0][7].valid[0], sectored_entries[0][7].valid[1])
node _r_sectored_repl_addr_valids_T_22 = or(_r_sectored_repl_addr_valids_T_21, sectored_entries[0][7].valid[2])
node _r_sectored_repl_addr_valids_T_23 = or(_r_sectored_repl_addr_valids_T_22, sectored_entries[0][7].valid[3])
node r_sectored_repl_addr_valids_lo_lo = cat(_r_sectored_repl_addr_valids_T_5, _r_sectored_repl_addr_valids_T_2)
node r_sectored_repl_addr_valids_lo_hi = cat(_r_sectored_repl_addr_valids_T_11, _r_sectored_repl_addr_valids_T_8)
node r_sectored_repl_addr_valids_lo = cat(r_sectored_repl_addr_valids_lo_hi, r_sectored_repl_addr_valids_lo_lo)
node r_sectored_repl_addr_valids_hi_lo = cat(_r_sectored_repl_addr_valids_T_17, _r_sectored_repl_addr_valids_T_14)
node r_sectored_repl_addr_valids_hi_hi = cat(_r_sectored_repl_addr_valids_T_23, _r_sectored_repl_addr_valids_T_20)
node r_sectored_repl_addr_valids_hi = cat(r_sectored_repl_addr_valids_hi_hi, r_sectored_repl_addr_valids_hi_lo)
node r_sectored_repl_addr_valids = cat(r_sectored_repl_addr_valids_hi, r_sectored_repl_addr_valids_lo)
node _r_sectored_repl_addr_T_10 = andr(r_sectored_repl_addr_valids)
node _r_sectored_repl_addr_T_11 = not(r_sectored_repl_addr_valids)
node _r_sectored_repl_addr_T_12 = bits(_r_sectored_repl_addr_T_11, 0, 0)
node _r_sectored_repl_addr_T_13 = bits(_r_sectored_repl_addr_T_11, 1, 1)
node _r_sectored_repl_addr_T_14 = bits(_r_sectored_repl_addr_T_11, 2, 2)
node _r_sectored_repl_addr_T_15 = bits(_r_sectored_repl_addr_T_11, 3, 3)
node _r_sectored_repl_addr_T_16 = bits(_r_sectored_repl_addr_T_11, 4, 4)
node _r_sectored_repl_addr_T_17 = bits(_r_sectored_repl_addr_T_11, 5, 5)
node _r_sectored_repl_addr_T_18 = bits(_r_sectored_repl_addr_T_11, 6, 6)
node _r_sectored_repl_addr_T_19 = bits(_r_sectored_repl_addr_T_11, 7, 7)
node _r_sectored_repl_addr_T_20 = mux(_r_sectored_repl_addr_T_18, UInt<3>(0h6), UInt<3>(0h7))
node _r_sectored_repl_addr_T_21 = mux(_r_sectored_repl_addr_T_17, UInt<3>(0h5), _r_sectored_repl_addr_T_20)
node _r_sectored_repl_addr_T_22 = mux(_r_sectored_repl_addr_T_16, UInt<3>(0h4), _r_sectored_repl_addr_T_21)
node _r_sectored_repl_addr_T_23 = mux(_r_sectored_repl_addr_T_15, UInt<2>(0h3), _r_sectored_repl_addr_T_22)
node _r_sectored_repl_addr_T_24 = mux(_r_sectored_repl_addr_T_14, UInt<2>(0h2), _r_sectored_repl_addr_T_23)
node _r_sectored_repl_addr_T_25 = mux(_r_sectored_repl_addr_T_13, UInt<1>(0h1), _r_sectored_repl_addr_T_24)
node _r_sectored_repl_addr_T_26 = mux(_r_sectored_repl_addr_T_12, UInt<1>(0h0), _r_sectored_repl_addr_T_25)
node _r_sectored_repl_addr_T_27 = mux(_r_sectored_repl_addr_T_10, _r_sectored_repl_addr_T_9, _r_sectored_repl_addr_T_26)
connect r_sectored_repl_addr, _r_sectored_repl_addr_T_27
node _r_sectored_hit_valid_T = or(sector_hits_0, sector_hits_1)
node _r_sectored_hit_valid_T_1 = or(_r_sectored_hit_valid_T, sector_hits_2)
node _r_sectored_hit_valid_T_2 = or(_r_sectored_hit_valid_T_1, sector_hits_3)
node _r_sectored_hit_valid_T_3 = or(_r_sectored_hit_valid_T_2, sector_hits_4)
node _r_sectored_hit_valid_T_4 = or(_r_sectored_hit_valid_T_3, sector_hits_5)
node _r_sectored_hit_valid_T_5 = or(_r_sectored_hit_valid_T_4, sector_hits_6)
node _r_sectored_hit_valid_T_6 = or(_r_sectored_hit_valid_T_5, sector_hits_7)
connect r_sectored_hit.valid, _r_sectored_hit_valid_T_6
node r_sectored_hit_bits_lo_lo = cat(sector_hits_1, sector_hits_0)
node r_sectored_hit_bits_lo_hi = cat(sector_hits_3, sector_hits_2)
node r_sectored_hit_bits_lo = cat(r_sectored_hit_bits_lo_hi, r_sectored_hit_bits_lo_lo)
node r_sectored_hit_bits_hi_lo = cat(sector_hits_5, sector_hits_4)
node r_sectored_hit_bits_hi_hi = cat(sector_hits_7, sector_hits_6)
node r_sectored_hit_bits_hi = cat(r_sectored_hit_bits_hi_hi, r_sectored_hit_bits_hi_lo)
node _r_sectored_hit_bits_T = cat(r_sectored_hit_bits_hi, r_sectored_hit_bits_lo)
node r_sectored_hit_bits_hi_1 = bits(_r_sectored_hit_bits_T, 7, 4)
node r_sectored_hit_bits_lo_1 = bits(_r_sectored_hit_bits_T, 3, 0)
node _r_sectored_hit_bits_T_1 = orr(r_sectored_hit_bits_hi_1)
node _r_sectored_hit_bits_T_2 = or(r_sectored_hit_bits_hi_1, r_sectored_hit_bits_lo_1)
node r_sectored_hit_bits_hi_2 = bits(_r_sectored_hit_bits_T_2, 3, 2)
node r_sectored_hit_bits_lo_2 = bits(_r_sectored_hit_bits_T_2, 1, 0)
node _r_sectored_hit_bits_T_3 = orr(r_sectored_hit_bits_hi_2)
node _r_sectored_hit_bits_T_4 = or(r_sectored_hit_bits_hi_2, r_sectored_hit_bits_lo_2)
node _r_sectored_hit_bits_T_5 = bits(_r_sectored_hit_bits_T_4, 1, 1)
node _r_sectored_hit_bits_T_6 = cat(_r_sectored_hit_bits_T_3, _r_sectored_hit_bits_T_5)
node _r_sectored_hit_bits_T_7 = cat(_r_sectored_hit_bits_T_1, _r_sectored_hit_bits_T_6)
connect r_sectored_hit.bits, _r_sectored_hit_bits_T_7
node _r_superpage_hit_valid_T = or(superpage_hits_0, superpage_hits_1)
node _r_superpage_hit_valid_T_1 = or(_r_superpage_hit_valid_T, superpage_hits_2)
node _r_superpage_hit_valid_T_2 = or(_r_superpage_hit_valid_T_1, superpage_hits_3)
connect r_superpage_hit.valid, _r_superpage_hit_valid_T_2
node r_superpage_hit_bits_lo = cat(superpage_hits_1, superpage_hits_0)
node r_superpage_hit_bits_hi = cat(superpage_hits_3, superpage_hits_2)
node _r_superpage_hit_bits_T = cat(r_superpage_hit_bits_hi, r_superpage_hit_bits_lo)
node r_superpage_hit_bits_hi_1 = bits(_r_superpage_hit_bits_T, 3, 2)
node r_superpage_hit_bits_lo_1 = bits(_r_superpage_hit_bits_T, 1, 0)
node _r_superpage_hit_bits_T_1 = orr(r_superpage_hit_bits_hi_1)
node _r_superpage_hit_bits_T_2 = or(r_superpage_hit_bits_hi_1, r_superpage_hit_bits_lo_1)
node _r_superpage_hit_bits_T_3 = bits(_r_superpage_hit_bits_T_2, 1, 1)
node _r_superpage_hit_bits_T_4 = cat(_r_superpage_hit_bits_T_1, _r_superpage_hit_bits_T_3)
connect r_superpage_hit.bits, _r_superpage_hit_bits_T_4
node _T_51 = eq(state, UInt<2>(0h1))
when _T_51 :
when io.sfence.valid :
connect state, UInt<2>(0h0)
when io.ptw.req.ready :
node _state_T = mux(io.sfence.valid, UInt<2>(0h3), UInt<2>(0h2))
connect state, _state_T
when io.kill :
connect state, UInt<2>(0h0)
node _T_52 = eq(state, UInt<2>(0h2))
node _T_53 = and(_T_52, io.sfence.valid)
when _T_53 :
connect state, UInt<2>(0h3)
when io.ptw.resp.valid :
connect state, UInt<2>(0h0)
when io.sfence.valid :
node _T_54 = eq(io.sfence.bits.rs1, UInt<1>(0h0))
node _T_55 = shr(io.sfence.bits.addr, 12)
node _T_56 = eq(_T_55, vpn)
node _T_57 = or(_T_54, _T_56)
node _T_58 = asUInt(reset)
node _T_59 = eq(_T_58, UInt<1>(0h0))
when _T_59 :
node _T_60 = eq(_T_57, UInt<1>(0h0))
when _T_60 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at TLB.scala:719 assert(!io.sfence.bits.rs1 || (io.sfence.bits.addr >> pgIdxBits) === vpn)\n") : printf
assert(clock, _T_57, UInt<1>(0h1), "") : assert
node hv = and(UInt<1>(0h0), io.sfence.bits.hv)
node hg = and(UInt<1>(0h0), io.sfence.bits.hg)
node _T_61 = eq(hg, UInt<1>(0h0))
node _T_62 = and(_T_61, io.sfence.bits.rs1)
when _T_62 :
node _T_63 = xor(sectored_entries[0][0].tag_vpn, vpn)
node _T_64 = shr(_T_63, 2)
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = eq(sectored_entries[0][0].tag_v, hv)
node _T_67 = and(_T_65, _T_66)
when _T_67 :
wire _WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_1 : UInt<42>
connect _WIRE_1, sectored_entries[0][0].data[0]
node _T_68 = bits(_WIRE_1, 0, 0)
connect _WIRE.fragmented_superpage, _T_68
node _T_69 = bits(_WIRE_1, 1, 1)
connect _WIRE.c, _T_69
node _T_70 = bits(_WIRE_1, 2, 2)
connect _WIRE.eff, _T_70
node _T_71 = bits(_WIRE_1, 3, 3)
connect _WIRE.paa, _T_71
node _T_72 = bits(_WIRE_1, 4, 4)
connect _WIRE.pal, _T_72
node _T_73 = bits(_WIRE_1, 5, 5)
connect _WIRE.ppp, _T_73
node _T_74 = bits(_WIRE_1, 6, 6)
connect _WIRE.pr, _T_74
node _T_75 = bits(_WIRE_1, 7, 7)
connect _WIRE.px, _T_75
node _T_76 = bits(_WIRE_1, 8, 8)
connect _WIRE.pw, _T_76
node _T_77 = bits(_WIRE_1, 9, 9)
connect _WIRE.hr, _T_77
node _T_78 = bits(_WIRE_1, 10, 10)
connect _WIRE.hx, _T_78
node _T_79 = bits(_WIRE_1, 11, 11)
connect _WIRE.hw, _T_79
node _T_80 = bits(_WIRE_1, 12, 12)
connect _WIRE.sr, _T_80
node _T_81 = bits(_WIRE_1, 13, 13)
connect _WIRE.sx, _T_81
node _T_82 = bits(_WIRE_1, 14, 14)
connect _WIRE.sw, _T_82
node _T_83 = bits(_WIRE_1, 15, 15)
connect _WIRE.gf, _T_83
node _T_84 = bits(_WIRE_1, 16, 16)
connect _WIRE.pf, _T_84
node _T_85 = bits(_WIRE_1, 17, 17)
connect _WIRE.ae_stage2, _T_85
node _T_86 = bits(_WIRE_1, 18, 18)
connect _WIRE.ae_final, _T_86
node _T_87 = bits(_WIRE_1, 19, 19)
connect _WIRE.ae_ptw, _T_87
node _T_88 = bits(_WIRE_1, 20, 20)
connect _WIRE.g, _T_88
node _T_89 = bits(_WIRE_1, 21, 21)
connect _WIRE.u, _T_89
node _T_90 = bits(_WIRE_1, 41, 22)
connect _WIRE.ppn, _T_90
wire _WIRE_2 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_3 : UInt<42>
connect _WIRE_3, sectored_entries[0][0].data[1]
node _T_91 = bits(_WIRE_3, 0, 0)
connect _WIRE_2.fragmented_superpage, _T_91
node _T_92 = bits(_WIRE_3, 1, 1)
connect _WIRE_2.c, _T_92
node _T_93 = bits(_WIRE_3, 2, 2)
connect _WIRE_2.eff, _T_93
node _T_94 = bits(_WIRE_3, 3, 3)
connect _WIRE_2.paa, _T_94
node _T_95 = bits(_WIRE_3, 4, 4)
connect _WIRE_2.pal, _T_95
node _T_96 = bits(_WIRE_3, 5, 5)
connect _WIRE_2.ppp, _T_96
node _T_97 = bits(_WIRE_3, 6, 6)
connect _WIRE_2.pr, _T_97
node _T_98 = bits(_WIRE_3, 7, 7)
connect _WIRE_2.px, _T_98
node _T_99 = bits(_WIRE_3, 8, 8)
connect _WIRE_2.pw, _T_99
node _T_100 = bits(_WIRE_3, 9, 9)
connect _WIRE_2.hr, _T_100
node _T_101 = bits(_WIRE_3, 10, 10)
connect _WIRE_2.hx, _T_101
node _T_102 = bits(_WIRE_3, 11, 11)
connect _WIRE_2.hw, _T_102
node _T_103 = bits(_WIRE_3, 12, 12)
connect _WIRE_2.sr, _T_103
node _T_104 = bits(_WIRE_3, 13, 13)
connect _WIRE_2.sx, _T_104
node _T_105 = bits(_WIRE_3, 14, 14)
connect _WIRE_2.sw, _T_105
node _T_106 = bits(_WIRE_3, 15, 15)
connect _WIRE_2.gf, _T_106
node _T_107 = bits(_WIRE_3, 16, 16)
connect _WIRE_2.pf, _T_107
node _T_108 = bits(_WIRE_3, 17, 17)
connect _WIRE_2.ae_stage2, _T_108
node _T_109 = bits(_WIRE_3, 18, 18)
connect _WIRE_2.ae_final, _T_109
node _T_110 = bits(_WIRE_3, 19, 19)
connect _WIRE_2.ae_ptw, _T_110
node _T_111 = bits(_WIRE_3, 20, 20)
connect _WIRE_2.g, _T_111
node _T_112 = bits(_WIRE_3, 21, 21)
connect _WIRE_2.u, _T_112
node _T_113 = bits(_WIRE_3, 41, 22)
connect _WIRE_2.ppn, _T_113
wire _WIRE_4 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_5 : UInt<42>
connect _WIRE_5, sectored_entries[0][0].data[2]
node _T_114 = bits(_WIRE_5, 0, 0)
connect _WIRE_4.fragmented_superpage, _T_114
node _T_115 = bits(_WIRE_5, 1, 1)
connect _WIRE_4.c, _T_115
node _T_116 = bits(_WIRE_5, 2, 2)
connect _WIRE_4.eff, _T_116
node _T_117 = bits(_WIRE_5, 3, 3)
connect _WIRE_4.paa, _T_117
node _T_118 = bits(_WIRE_5, 4, 4)
connect _WIRE_4.pal, _T_118
node _T_119 = bits(_WIRE_5, 5, 5)
connect _WIRE_4.ppp, _T_119
node _T_120 = bits(_WIRE_5, 6, 6)
connect _WIRE_4.pr, _T_120
node _T_121 = bits(_WIRE_5, 7, 7)
connect _WIRE_4.px, _T_121
node _T_122 = bits(_WIRE_5, 8, 8)
connect _WIRE_4.pw, _T_122
node _T_123 = bits(_WIRE_5, 9, 9)
connect _WIRE_4.hr, _T_123
node _T_124 = bits(_WIRE_5, 10, 10)
connect _WIRE_4.hx, _T_124
node _T_125 = bits(_WIRE_5, 11, 11)
connect _WIRE_4.hw, _T_125
node _T_126 = bits(_WIRE_5, 12, 12)
connect _WIRE_4.sr, _T_126
node _T_127 = bits(_WIRE_5, 13, 13)
connect _WIRE_4.sx, _T_127
node _T_128 = bits(_WIRE_5, 14, 14)
connect _WIRE_4.sw, _T_128
node _T_129 = bits(_WIRE_5, 15, 15)
connect _WIRE_4.gf, _T_129
node _T_130 = bits(_WIRE_5, 16, 16)
connect _WIRE_4.pf, _T_130
node _T_131 = bits(_WIRE_5, 17, 17)
connect _WIRE_4.ae_stage2, _T_131
node _T_132 = bits(_WIRE_5, 18, 18)
connect _WIRE_4.ae_final, _T_132
node _T_133 = bits(_WIRE_5, 19, 19)
connect _WIRE_4.ae_ptw, _T_133
node _T_134 = bits(_WIRE_5, 20, 20)
connect _WIRE_4.g, _T_134
node _T_135 = bits(_WIRE_5, 21, 21)
connect _WIRE_4.u, _T_135
node _T_136 = bits(_WIRE_5, 41, 22)
connect _WIRE_4.ppn, _T_136
wire _WIRE_6 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_7 : UInt<42>
connect _WIRE_7, sectored_entries[0][0].data[3]
node _T_137 = bits(_WIRE_7, 0, 0)
connect _WIRE_6.fragmented_superpage, _T_137
node _T_138 = bits(_WIRE_7, 1, 1)
connect _WIRE_6.c, _T_138
node _T_139 = bits(_WIRE_7, 2, 2)
connect _WIRE_6.eff, _T_139
node _T_140 = bits(_WIRE_7, 3, 3)
connect _WIRE_6.paa, _T_140
node _T_141 = bits(_WIRE_7, 4, 4)
connect _WIRE_6.pal, _T_141
node _T_142 = bits(_WIRE_7, 5, 5)
connect _WIRE_6.ppp, _T_142
node _T_143 = bits(_WIRE_7, 6, 6)
connect _WIRE_6.pr, _T_143
node _T_144 = bits(_WIRE_7, 7, 7)
connect _WIRE_6.px, _T_144
node _T_145 = bits(_WIRE_7, 8, 8)
connect _WIRE_6.pw, _T_145
node _T_146 = bits(_WIRE_7, 9, 9)
connect _WIRE_6.hr, _T_146
node _T_147 = bits(_WIRE_7, 10, 10)
connect _WIRE_6.hx, _T_147
node _T_148 = bits(_WIRE_7, 11, 11)
connect _WIRE_6.hw, _T_148
node _T_149 = bits(_WIRE_7, 12, 12)
connect _WIRE_6.sr, _T_149
node _T_150 = bits(_WIRE_7, 13, 13)
connect _WIRE_6.sx, _T_150
node _T_151 = bits(_WIRE_7, 14, 14)
connect _WIRE_6.sw, _T_151
node _T_152 = bits(_WIRE_7, 15, 15)
connect _WIRE_6.gf, _T_152
node _T_153 = bits(_WIRE_7, 16, 16)
connect _WIRE_6.pf, _T_153
node _T_154 = bits(_WIRE_7, 17, 17)
connect _WIRE_6.ae_stage2, _T_154
node _T_155 = bits(_WIRE_7, 18, 18)
connect _WIRE_6.ae_final, _T_155
node _T_156 = bits(_WIRE_7, 19, 19)
connect _WIRE_6.ae_ptw, _T_156
node _T_157 = bits(_WIRE_7, 20, 20)
connect _WIRE_6.g, _T_157
node _T_158 = bits(_WIRE_7, 21, 21)
connect _WIRE_6.u, _T_158
node _T_159 = bits(_WIRE_7, 41, 22)
connect _WIRE_6.ppn, _T_159
node _T_160 = eq(sectored_entries[0][0].tag_v, hv)
node _T_161 = bits(vpn, 1, 0)
node _T_162 = eq(UInt<1>(0h0), _T_161)
node _T_163 = and(_T_160, _T_162)
when _T_163 :
connect sectored_entries[0][0].valid[0], UInt<1>(0h0)
node _T_164 = eq(sectored_entries[0][0].tag_v, hv)
node _T_165 = bits(vpn, 1, 0)
node _T_166 = eq(UInt<1>(0h1), _T_165)
node _T_167 = and(_T_164, _T_166)
when _T_167 :
connect sectored_entries[0][0].valid[1], UInt<1>(0h0)
node _T_168 = eq(sectored_entries[0][0].tag_v, hv)
node _T_169 = bits(vpn, 1, 0)
node _T_170 = eq(UInt<2>(0h2), _T_169)
node _T_171 = and(_T_168, _T_170)
when _T_171 :
connect sectored_entries[0][0].valid[2], UInt<1>(0h0)
node _T_172 = eq(sectored_entries[0][0].tag_v, hv)
node _T_173 = bits(vpn, 1, 0)
node _T_174 = eq(UInt<2>(0h3), _T_173)
node _T_175 = and(_T_172, _T_174)
when _T_175 :
connect sectored_entries[0][0].valid[3], UInt<1>(0h0)
node _T_176 = xor(sectored_entries[0][0].tag_vpn, vpn)
node _T_177 = shr(_T_176, 18)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
wire _WIRE_8 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_9 : UInt<42>
connect _WIRE_9, sectored_entries[0][0].data[0]
node _T_179 = bits(_WIRE_9, 0, 0)
connect _WIRE_8.fragmented_superpage, _T_179
node _T_180 = bits(_WIRE_9, 1, 1)
connect _WIRE_8.c, _T_180
node _T_181 = bits(_WIRE_9, 2, 2)
connect _WIRE_8.eff, _T_181
node _T_182 = bits(_WIRE_9, 3, 3)
connect _WIRE_8.paa, _T_182
node _T_183 = bits(_WIRE_9, 4, 4)
connect _WIRE_8.pal, _T_183
node _T_184 = bits(_WIRE_9, 5, 5)
connect _WIRE_8.ppp, _T_184
node _T_185 = bits(_WIRE_9, 6, 6)
connect _WIRE_8.pr, _T_185
node _T_186 = bits(_WIRE_9, 7, 7)
connect _WIRE_8.px, _T_186
node _T_187 = bits(_WIRE_9, 8, 8)
connect _WIRE_8.pw, _T_187
node _T_188 = bits(_WIRE_9, 9, 9)
connect _WIRE_8.hr, _T_188
node _T_189 = bits(_WIRE_9, 10, 10)
connect _WIRE_8.hx, _T_189
node _T_190 = bits(_WIRE_9, 11, 11)
connect _WIRE_8.hw, _T_190
node _T_191 = bits(_WIRE_9, 12, 12)
connect _WIRE_8.sr, _T_191
node _T_192 = bits(_WIRE_9, 13, 13)
connect _WIRE_8.sx, _T_192
node _T_193 = bits(_WIRE_9, 14, 14)
connect _WIRE_8.sw, _T_193
node _T_194 = bits(_WIRE_9, 15, 15)
connect _WIRE_8.gf, _T_194
node _T_195 = bits(_WIRE_9, 16, 16)
connect _WIRE_8.pf, _T_195
node _T_196 = bits(_WIRE_9, 17, 17)
connect _WIRE_8.ae_stage2, _T_196
node _T_197 = bits(_WIRE_9, 18, 18)
connect _WIRE_8.ae_final, _T_197
node _T_198 = bits(_WIRE_9, 19, 19)
connect _WIRE_8.ae_ptw, _T_198
node _T_199 = bits(_WIRE_9, 20, 20)
connect _WIRE_8.g, _T_199
node _T_200 = bits(_WIRE_9, 21, 21)
connect _WIRE_8.u, _T_200
node _T_201 = bits(_WIRE_9, 41, 22)
connect _WIRE_8.ppn, _T_201
wire _WIRE_10 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_11 : UInt<42>
connect _WIRE_11, sectored_entries[0][0].data[1]
node _T_202 = bits(_WIRE_11, 0, 0)
connect _WIRE_10.fragmented_superpage, _T_202
node _T_203 = bits(_WIRE_11, 1, 1)
connect _WIRE_10.c, _T_203
node _T_204 = bits(_WIRE_11, 2, 2)
connect _WIRE_10.eff, _T_204
node _T_205 = bits(_WIRE_11, 3, 3)
connect _WIRE_10.paa, _T_205
node _T_206 = bits(_WIRE_11, 4, 4)
connect _WIRE_10.pal, _T_206
node _T_207 = bits(_WIRE_11, 5, 5)
connect _WIRE_10.ppp, _T_207
node _T_208 = bits(_WIRE_11, 6, 6)
connect _WIRE_10.pr, _T_208
node _T_209 = bits(_WIRE_11, 7, 7)
connect _WIRE_10.px, _T_209
node _T_210 = bits(_WIRE_11, 8, 8)
connect _WIRE_10.pw, _T_210
node _T_211 = bits(_WIRE_11, 9, 9)
connect _WIRE_10.hr, _T_211
node _T_212 = bits(_WIRE_11, 10, 10)
connect _WIRE_10.hx, _T_212
node _T_213 = bits(_WIRE_11, 11, 11)
connect _WIRE_10.hw, _T_213
node _T_214 = bits(_WIRE_11, 12, 12)
connect _WIRE_10.sr, _T_214
node _T_215 = bits(_WIRE_11, 13, 13)
connect _WIRE_10.sx, _T_215
node _T_216 = bits(_WIRE_11, 14, 14)
connect _WIRE_10.sw, _T_216
node _T_217 = bits(_WIRE_11, 15, 15)
connect _WIRE_10.gf, _T_217
node _T_218 = bits(_WIRE_11, 16, 16)
connect _WIRE_10.pf, _T_218
node _T_219 = bits(_WIRE_11, 17, 17)
connect _WIRE_10.ae_stage2, _T_219
node _T_220 = bits(_WIRE_11, 18, 18)
connect _WIRE_10.ae_final, _T_220
node _T_221 = bits(_WIRE_11, 19, 19)
connect _WIRE_10.ae_ptw, _T_221
node _T_222 = bits(_WIRE_11, 20, 20)
connect _WIRE_10.g, _T_222
node _T_223 = bits(_WIRE_11, 21, 21)
connect _WIRE_10.u, _T_223
node _T_224 = bits(_WIRE_11, 41, 22)
connect _WIRE_10.ppn, _T_224
wire _WIRE_12 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_13 : UInt<42>
connect _WIRE_13, sectored_entries[0][0].data[2]
node _T_225 = bits(_WIRE_13, 0, 0)
connect _WIRE_12.fragmented_superpage, _T_225
node _T_226 = bits(_WIRE_13, 1, 1)
connect _WIRE_12.c, _T_226
node _T_227 = bits(_WIRE_13, 2, 2)
connect _WIRE_12.eff, _T_227
node _T_228 = bits(_WIRE_13, 3, 3)
connect _WIRE_12.paa, _T_228
node _T_229 = bits(_WIRE_13, 4, 4)
connect _WIRE_12.pal, _T_229
node _T_230 = bits(_WIRE_13, 5, 5)
connect _WIRE_12.ppp, _T_230
node _T_231 = bits(_WIRE_13, 6, 6)
connect _WIRE_12.pr, _T_231
node _T_232 = bits(_WIRE_13, 7, 7)
connect _WIRE_12.px, _T_232
node _T_233 = bits(_WIRE_13, 8, 8)
connect _WIRE_12.pw, _T_233
node _T_234 = bits(_WIRE_13, 9, 9)
connect _WIRE_12.hr, _T_234
node _T_235 = bits(_WIRE_13, 10, 10)
connect _WIRE_12.hx, _T_235
node _T_236 = bits(_WIRE_13, 11, 11)
connect _WIRE_12.hw, _T_236
node _T_237 = bits(_WIRE_13, 12, 12)
connect _WIRE_12.sr, _T_237
node _T_238 = bits(_WIRE_13, 13, 13)
connect _WIRE_12.sx, _T_238
node _T_239 = bits(_WIRE_13, 14, 14)
connect _WIRE_12.sw, _T_239
node _T_240 = bits(_WIRE_13, 15, 15)
connect _WIRE_12.gf, _T_240
node _T_241 = bits(_WIRE_13, 16, 16)
connect _WIRE_12.pf, _T_241
node _T_242 = bits(_WIRE_13, 17, 17)
connect _WIRE_12.ae_stage2, _T_242
node _T_243 = bits(_WIRE_13, 18, 18)
connect _WIRE_12.ae_final, _T_243
node _T_244 = bits(_WIRE_13, 19, 19)
connect _WIRE_12.ae_ptw, _T_244
node _T_245 = bits(_WIRE_13, 20, 20)
connect _WIRE_12.g, _T_245
node _T_246 = bits(_WIRE_13, 21, 21)
connect _WIRE_12.u, _T_246
node _T_247 = bits(_WIRE_13, 41, 22)
connect _WIRE_12.ppn, _T_247
wire _WIRE_14 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_15 : UInt<42>
connect _WIRE_15, sectored_entries[0][0].data[3]
node _T_248 = bits(_WIRE_15, 0, 0)
connect _WIRE_14.fragmented_superpage, _T_248
node _T_249 = bits(_WIRE_15, 1, 1)
connect _WIRE_14.c, _T_249
node _T_250 = bits(_WIRE_15, 2, 2)
connect _WIRE_14.eff, _T_250
node _T_251 = bits(_WIRE_15, 3, 3)
connect _WIRE_14.paa, _T_251
node _T_252 = bits(_WIRE_15, 4, 4)
connect _WIRE_14.pal, _T_252
node _T_253 = bits(_WIRE_15, 5, 5)
connect _WIRE_14.ppp, _T_253
node _T_254 = bits(_WIRE_15, 6, 6)
connect _WIRE_14.pr, _T_254
node _T_255 = bits(_WIRE_15, 7, 7)
connect _WIRE_14.px, _T_255
node _T_256 = bits(_WIRE_15, 8, 8)
connect _WIRE_14.pw, _T_256
node _T_257 = bits(_WIRE_15, 9, 9)
connect _WIRE_14.hr, _T_257
node _T_258 = bits(_WIRE_15, 10, 10)
connect _WIRE_14.hx, _T_258
node _T_259 = bits(_WIRE_15, 11, 11)
connect _WIRE_14.hw, _T_259
node _T_260 = bits(_WIRE_15, 12, 12)
connect _WIRE_14.sr, _T_260
node _T_261 = bits(_WIRE_15, 13, 13)
connect _WIRE_14.sx, _T_261
node _T_262 = bits(_WIRE_15, 14, 14)
connect _WIRE_14.sw, _T_262
node _T_263 = bits(_WIRE_15, 15, 15)
connect _WIRE_14.gf, _T_263
node _T_264 = bits(_WIRE_15, 16, 16)
connect _WIRE_14.pf, _T_264
node _T_265 = bits(_WIRE_15, 17, 17)
connect _WIRE_14.ae_stage2, _T_265
node _T_266 = bits(_WIRE_15, 18, 18)
connect _WIRE_14.ae_final, _T_266
node _T_267 = bits(_WIRE_15, 19, 19)
connect _WIRE_14.ae_ptw, _T_267
node _T_268 = bits(_WIRE_15, 20, 20)
connect _WIRE_14.g, _T_268
node _T_269 = bits(_WIRE_15, 21, 21)
connect _WIRE_14.u, _T_269
node _T_270 = bits(_WIRE_15, 41, 22)
connect _WIRE_14.ppn, _T_270
node _T_271 = eq(sectored_entries[0][0].tag_v, hv)
node _T_272 = and(_T_271, _WIRE_8.fragmented_superpage)
when _T_272 :
connect sectored_entries[0][0].valid[0], UInt<1>(0h0)
node _T_273 = eq(sectored_entries[0][0].tag_v, hv)
node _T_274 = and(_T_273, _WIRE_10.fragmented_superpage)
when _T_274 :
connect sectored_entries[0][0].valid[1], UInt<1>(0h0)
node _T_275 = eq(sectored_entries[0][0].tag_v, hv)
node _T_276 = and(_T_275, _WIRE_12.fragmented_superpage)
when _T_276 :
connect sectored_entries[0][0].valid[2], UInt<1>(0h0)
node _T_277 = eq(sectored_entries[0][0].tag_v, hv)
node _T_278 = and(_T_277, _WIRE_14.fragmented_superpage)
when _T_278 :
connect sectored_entries[0][0].valid[3], UInt<1>(0h0)
else :
node _T_279 = eq(hg, UInt<1>(0h0))
node _T_280 = and(_T_279, io.sfence.bits.rs2)
when _T_280 :
wire _WIRE_16 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_17 : UInt<42>
connect _WIRE_17, sectored_entries[0][0].data[0]
node _T_281 = bits(_WIRE_17, 0, 0)
connect _WIRE_16.fragmented_superpage, _T_281
node _T_282 = bits(_WIRE_17, 1, 1)
connect _WIRE_16.c, _T_282
node _T_283 = bits(_WIRE_17, 2, 2)
connect _WIRE_16.eff, _T_283
node _T_284 = bits(_WIRE_17, 3, 3)
connect _WIRE_16.paa, _T_284
node _T_285 = bits(_WIRE_17, 4, 4)
connect _WIRE_16.pal, _T_285
node _T_286 = bits(_WIRE_17, 5, 5)
connect _WIRE_16.ppp, _T_286
node _T_287 = bits(_WIRE_17, 6, 6)
connect _WIRE_16.pr, _T_287
node _T_288 = bits(_WIRE_17, 7, 7)
connect _WIRE_16.px, _T_288
node _T_289 = bits(_WIRE_17, 8, 8)
connect _WIRE_16.pw, _T_289
node _T_290 = bits(_WIRE_17, 9, 9)
connect _WIRE_16.hr, _T_290
node _T_291 = bits(_WIRE_17, 10, 10)
connect _WIRE_16.hx, _T_291
node _T_292 = bits(_WIRE_17, 11, 11)
connect _WIRE_16.hw, _T_292
node _T_293 = bits(_WIRE_17, 12, 12)
connect _WIRE_16.sr, _T_293
node _T_294 = bits(_WIRE_17, 13, 13)
connect _WIRE_16.sx, _T_294
node _T_295 = bits(_WIRE_17, 14, 14)
connect _WIRE_16.sw, _T_295
node _T_296 = bits(_WIRE_17, 15, 15)
connect _WIRE_16.gf, _T_296
node _T_297 = bits(_WIRE_17, 16, 16)
connect _WIRE_16.pf, _T_297
node _T_298 = bits(_WIRE_17, 17, 17)
connect _WIRE_16.ae_stage2, _T_298
node _T_299 = bits(_WIRE_17, 18, 18)
connect _WIRE_16.ae_final, _T_299
node _T_300 = bits(_WIRE_17, 19, 19)
connect _WIRE_16.ae_ptw, _T_300
node _T_301 = bits(_WIRE_17, 20, 20)
connect _WIRE_16.g, _T_301
node _T_302 = bits(_WIRE_17, 21, 21)
connect _WIRE_16.u, _T_302
node _T_303 = bits(_WIRE_17, 41, 22)
connect _WIRE_16.ppn, _T_303
wire _WIRE_18 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_19 : UInt<42>
connect _WIRE_19, sectored_entries[0][0].data[1]
node _T_304 = bits(_WIRE_19, 0, 0)
connect _WIRE_18.fragmented_superpage, _T_304
node _T_305 = bits(_WIRE_19, 1, 1)
connect _WIRE_18.c, _T_305
node _T_306 = bits(_WIRE_19, 2, 2)
connect _WIRE_18.eff, _T_306
node _T_307 = bits(_WIRE_19, 3, 3)
connect _WIRE_18.paa, _T_307
node _T_308 = bits(_WIRE_19, 4, 4)
connect _WIRE_18.pal, _T_308
node _T_309 = bits(_WIRE_19, 5, 5)
connect _WIRE_18.ppp, _T_309
node _T_310 = bits(_WIRE_19, 6, 6)
connect _WIRE_18.pr, _T_310
node _T_311 = bits(_WIRE_19, 7, 7)
connect _WIRE_18.px, _T_311
node _T_312 = bits(_WIRE_19, 8, 8)
connect _WIRE_18.pw, _T_312
node _T_313 = bits(_WIRE_19, 9, 9)
connect _WIRE_18.hr, _T_313
node _T_314 = bits(_WIRE_19, 10, 10)
connect _WIRE_18.hx, _T_314
node _T_315 = bits(_WIRE_19, 11, 11)
connect _WIRE_18.hw, _T_315
node _T_316 = bits(_WIRE_19, 12, 12)
connect _WIRE_18.sr, _T_316
node _T_317 = bits(_WIRE_19, 13, 13)
connect _WIRE_18.sx, _T_317
node _T_318 = bits(_WIRE_19, 14, 14)
connect _WIRE_18.sw, _T_318
node _T_319 = bits(_WIRE_19, 15, 15)
connect _WIRE_18.gf, _T_319
node _T_320 = bits(_WIRE_19, 16, 16)
connect _WIRE_18.pf, _T_320
node _T_321 = bits(_WIRE_19, 17, 17)
connect _WIRE_18.ae_stage2, _T_321
node _T_322 = bits(_WIRE_19, 18, 18)
connect _WIRE_18.ae_final, _T_322
node _T_323 = bits(_WIRE_19, 19, 19)
connect _WIRE_18.ae_ptw, _T_323
node _T_324 = bits(_WIRE_19, 20, 20)
connect _WIRE_18.g, _T_324
node _T_325 = bits(_WIRE_19, 21, 21)
connect _WIRE_18.u, _T_325
node _T_326 = bits(_WIRE_19, 41, 22)
connect _WIRE_18.ppn, _T_326
wire _WIRE_20 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_21 : UInt<42>
connect _WIRE_21, sectored_entries[0][0].data[2]
node _T_327 = bits(_WIRE_21, 0, 0)
connect _WIRE_20.fragmented_superpage, _T_327
node _T_328 = bits(_WIRE_21, 1, 1)
connect _WIRE_20.c, _T_328
node _T_329 = bits(_WIRE_21, 2, 2)
connect _WIRE_20.eff, _T_329
node _T_330 = bits(_WIRE_21, 3, 3)
connect _WIRE_20.paa, _T_330
node _T_331 = bits(_WIRE_21, 4, 4)
connect _WIRE_20.pal, _T_331
node _T_332 = bits(_WIRE_21, 5, 5)
connect _WIRE_20.ppp, _T_332
node _T_333 = bits(_WIRE_21, 6, 6)
connect _WIRE_20.pr, _T_333
node _T_334 = bits(_WIRE_21, 7, 7)
connect _WIRE_20.px, _T_334
node _T_335 = bits(_WIRE_21, 8, 8)
connect _WIRE_20.pw, _T_335
node _T_336 = bits(_WIRE_21, 9, 9)
connect _WIRE_20.hr, _T_336
node _T_337 = bits(_WIRE_21, 10, 10)
connect _WIRE_20.hx, _T_337
node _T_338 = bits(_WIRE_21, 11, 11)
connect _WIRE_20.hw, _T_338
node _T_339 = bits(_WIRE_21, 12, 12)
connect _WIRE_20.sr, _T_339
node _T_340 = bits(_WIRE_21, 13, 13)
connect _WIRE_20.sx, _T_340
node _T_341 = bits(_WIRE_21, 14, 14)
connect _WIRE_20.sw, _T_341
node _T_342 = bits(_WIRE_21, 15, 15)
connect _WIRE_20.gf, _T_342
node _T_343 = bits(_WIRE_21, 16, 16)
connect _WIRE_20.pf, _T_343
node _T_344 = bits(_WIRE_21, 17, 17)
connect _WIRE_20.ae_stage2, _T_344
node _T_345 = bits(_WIRE_21, 18, 18)
connect _WIRE_20.ae_final, _T_345
node _T_346 = bits(_WIRE_21, 19, 19)
connect _WIRE_20.ae_ptw, _T_346
node _T_347 = bits(_WIRE_21, 20, 20)
connect _WIRE_20.g, _T_347
node _T_348 = bits(_WIRE_21, 21, 21)
connect _WIRE_20.u, _T_348
node _T_349 = bits(_WIRE_21, 41, 22)
connect _WIRE_20.ppn, _T_349
wire _WIRE_22 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_23 : UInt<42>
connect _WIRE_23, sectored_entries[0][0].data[3]
node _T_350 = bits(_WIRE_23, 0, 0)
connect _WIRE_22.fragmented_superpage, _T_350
node _T_351 = bits(_WIRE_23, 1, 1)
connect _WIRE_22.c, _T_351
node _T_352 = bits(_WIRE_23, 2, 2)
connect _WIRE_22.eff, _T_352
node _T_353 = bits(_WIRE_23, 3, 3)
connect _WIRE_22.paa, _T_353
node _T_354 = bits(_WIRE_23, 4, 4)
connect _WIRE_22.pal, _T_354
node _T_355 = bits(_WIRE_23, 5, 5)
connect _WIRE_22.ppp, _T_355
node _T_356 = bits(_WIRE_23, 6, 6)
connect _WIRE_22.pr, _T_356
node _T_357 = bits(_WIRE_23, 7, 7)
connect _WIRE_22.px, _T_357
node _T_358 = bits(_WIRE_23, 8, 8)
connect _WIRE_22.pw, _T_358
node _T_359 = bits(_WIRE_23, 9, 9)
connect _WIRE_22.hr, _T_359
node _T_360 = bits(_WIRE_23, 10, 10)
connect _WIRE_22.hx, _T_360
node _T_361 = bits(_WIRE_23, 11, 11)
connect _WIRE_22.hw, _T_361
node _T_362 = bits(_WIRE_23, 12, 12)
connect _WIRE_22.sr, _T_362
node _T_363 = bits(_WIRE_23, 13, 13)
connect _WIRE_22.sx, _T_363
node _T_364 = bits(_WIRE_23, 14, 14)
connect _WIRE_22.sw, _T_364
node _T_365 = bits(_WIRE_23, 15, 15)
connect _WIRE_22.gf, _T_365
node _T_366 = bits(_WIRE_23, 16, 16)
connect _WIRE_22.pf, _T_366
node _T_367 = bits(_WIRE_23, 17, 17)
connect _WIRE_22.ae_stage2, _T_367
node _T_368 = bits(_WIRE_23, 18, 18)
connect _WIRE_22.ae_final, _T_368
node _T_369 = bits(_WIRE_23, 19, 19)
connect _WIRE_22.ae_ptw, _T_369
node _T_370 = bits(_WIRE_23, 20, 20)
connect _WIRE_22.g, _T_370
node _T_371 = bits(_WIRE_23, 21, 21)
connect _WIRE_22.u, _T_371
node _T_372 = bits(_WIRE_23, 41, 22)
connect _WIRE_22.ppn, _T_372
node _T_373 = eq(sectored_entries[0][0].tag_v, hv)
node _T_374 = eq(_WIRE_16.g, UInt<1>(0h0))
node _T_375 = and(_T_373, _T_374)
when _T_375 :
connect sectored_entries[0][0].valid[0], UInt<1>(0h0)
node _T_376 = eq(sectored_entries[0][0].tag_v, hv)
node _T_377 = eq(_WIRE_18.g, UInt<1>(0h0))
node _T_378 = and(_T_376, _T_377)
when _T_378 :
connect sectored_entries[0][0].valid[1], UInt<1>(0h0)
node _T_379 = eq(sectored_entries[0][0].tag_v, hv)
node _T_380 = eq(_WIRE_20.g, UInt<1>(0h0))
node _T_381 = and(_T_379, _T_380)
when _T_381 :
connect sectored_entries[0][0].valid[2], UInt<1>(0h0)
node _T_382 = eq(sectored_entries[0][0].tag_v, hv)
node _T_383 = eq(_WIRE_22.g, UInt<1>(0h0))
node _T_384 = and(_T_382, _T_383)
when _T_384 :
connect sectored_entries[0][0].valid[3], UInt<1>(0h0)
else :
node _T_385 = or(hv, hg)
wire _WIRE_24 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_25 : UInt<42>
connect _WIRE_25, sectored_entries[0][0].data[0]
node _T_386 = bits(_WIRE_25, 0, 0)
connect _WIRE_24.fragmented_superpage, _T_386
node _T_387 = bits(_WIRE_25, 1, 1)
connect _WIRE_24.c, _T_387
node _T_388 = bits(_WIRE_25, 2, 2)
connect _WIRE_24.eff, _T_388
node _T_389 = bits(_WIRE_25, 3, 3)
connect _WIRE_24.paa, _T_389
node _T_390 = bits(_WIRE_25, 4, 4)
connect _WIRE_24.pal, _T_390
node _T_391 = bits(_WIRE_25, 5, 5)
connect _WIRE_24.ppp, _T_391
node _T_392 = bits(_WIRE_25, 6, 6)
connect _WIRE_24.pr, _T_392
node _T_393 = bits(_WIRE_25, 7, 7)
connect _WIRE_24.px, _T_393
node _T_394 = bits(_WIRE_25, 8, 8)
connect _WIRE_24.pw, _T_394
node _T_395 = bits(_WIRE_25, 9, 9)
connect _WIRE_24.hr, _T_395
node _T_396 = bits(_WIRE_25, 10, 10)
connect _WIRE_24.hx, _T_396
node _T_397 = bits(_WIRE_25, 11, 11)
connect _WIRE_24.hw, _T_397
node _T_398 = bits(_WIRE_25, 12, 12)
connect _WIRE_24.sr, _T_398
node _T_399 = bits(_WIRE_25, 13, 13)
connect _WIRE_24.sx, _T_399
node _T_400 = bits(_WIRE_25, 14, 14)
connect _WIRE_24.sw, _T_400
node _T_401 = bits(_WIRE_25, 15, 15)
connect _WIRE_24.gf, _T_401
node _T_402 = bits(_WIRE_25, 16, 16)
connect _WIRE_24.pf, _T_402
node _T_403 = bits(_WIRE_25, 17, 17)
connect _WIRE_24.ae_stage2, _T_403
node _T_404 = bits(_WIRE_25, 18, 18)
connect _WIRE_24.ae_final, _T_404
node _T_405 = bits(_WIRE_25, 19, 19)
connect _WIRE_24.ae_ptw, _T_405
node _T_406 = bits(_WIRE_25, 20, 20)
connect _WIRE_24.g, _T_406
node _T_407 = bits(_WIRE_25, 21, 21)
connect _WIRE_24.u, _T_407
node _T_408 = bits(_WIRE_25, 41, 22)
connect _WIRE_24.ppn, _T_408
wire _WIRE_26 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_27 : UInt<42>
connect _WIRE_27, sectored_entries[0][0].data[1]
node _T_409 = bits(_WIRE_27, 0, 0)
connect _WIRE_26.fragmented_superpage, _T_409
node _T_410 = bits(_WIRE_27, 1, 1)
connect _WIRE_26.c, _T_410
node _T_411 = bits(_WIRE_27, 2, 2)
connect _WIRE_26.eff, _T_411
node _T_412 = bits(_WIRE_27, 3, 3)
connect _WIRE_26.paa, _T_412
node _T_413 = bits(_WIRE_27, 4, 4)
connect _WIRE_26.pal, _T_413
node _T_414 = bits(_WIRE_27, 5, 5)
connect _WIRE_26.ppp, _T_414
node _T_415 = bits(_WIRE_27, 6, 6)
connect _WIRE_26.pr, _T_415
node _T_416 = bits(_WIRE_27, 7, 7)
connect _WIRE_26.px, _T_416
node _T_417 = bits(_WIRE_27, 8, 8)
connect _WIRE_26.pw, _T_417
node _T_418 = bits(_WIRE_27, 9, 9)
connect _WIRE_26.hr, _T_418
node _T_419 = bits(_WIRE_27, 10, 10)
connect _WIRE_26.hx, _T_419
node _T_420 = bits(_WIRE_27, 11, 11)
connect _WIRE_26.hw, _T_420
node _T_421 = bits(_WIRE_27, 12, 12)
connect _WIRE_26.sr, _T_421
node _T_422 = bits(_WIRE_27, 13, 13)
connect _WIRE_26.sx, _T_422
node _T_423 = bits(_WIRE_27, 14, 14)
connect _WIRE_26.sw, _T_423
node _T_424 = bits(_WIRE_27, 15, 15)
connect _WIRE_26.gf, _T_424
node _T_425 = bits(_WIRE_27, 16, 16)
connect _WIRE_26.pf, _T_425
node _T_426 = bits(_WIRE_27, 17, 17)
connect _WIRE_26.ae_stage2, _T_426
node _T_427 = bits(_WIRE_27, 18, 18)
connect _WIRE_26.ae_final, _T_427
node _T_428 = bits(_WIRE_27, 19, 19)
connect _WIRE_26.ae_ptw, _T_428
node _T_429 = bits(_WIRE_27, 20, 20)
connect _WIRE_26.g, _T_429
node _T_430 = bits(_WIRE_27, 21, 21)
connect _WIRE_26.u, _T_430
node _T_431 = bits(_WIRE_27, 41, 22)
connect _WIRE_26.ppn, _T_431
wire _WIRE_28 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_29 : UInt<42>
connect _WIRE_29, sectored_entries[0][0].data[2]
node _T_432 = bits(_WIRE_29, 0, 0)
connect _WIRE_28.fragmented_superpage, _T_432
node _T_433 = bits(_WIRE_29, 1, 1)
connect _WIRE_28.c, _T_433
node _T_434 = bits(_WIRE_29, 2, 2)
connect _WIRE_28.eff, _T_434
node _T_435 = bits(_WIRE_29, 3, 3)
connect _WIRE_28.paa, _T_435
node _T_436 = bits(_WIRE_29, 4, 4)
connect _WIRE_28.pal, _T_436
node _T_437 = bits(_WIRE_29, 5, 5)
connect _WIRE_28.ppp, _T_437
node _T_438 = bits(_WIRE_29, 6, 6)
connect _WIRE_28.pr, _T_438
node _T_439 = bits(_WIRE_29, 7, 7)
connect _WIRE_28.px, _T_439
node _T_440 = bits(_WIRE_29, 8, 8)
connect _WIRE_28.pw, _T_440
node _T_441 = bits(_WIRE_29, 9, 9)
connect _WIRE_28.hr, _T_441
node _T_442 = bits(_WIRE_29, 10, 10)
connect _WIRE_28.hx, _T_442
node _T_443 = bits(_WIRE_29, 11, 11)
connect _WIRE_28.hw, _T_443
node _T_444 = bits(_WIRE_29, 12, 12)
connect _WIRE_28.sr, _T_444
node _T_445 = bits(_WIRE_29, 13, 13)
connect _WIRE_28.sx, _T_445
node _T_446 = bits(_WIRE_29, 14, 14)
connect _WIRE_28.sw, _T_446
node _T_447 = bits(_WIRE_29, 15, 15)
connect _WIRE_28.gf, _T_447
node _T_448 = bits(_WIRE_29, 16, 16)
connect _WIRE_28.pf, _T_448
node _T_449 = bits(_WIRE_29, 17, 17)
connect _WIRE_28.ae_stage2, _T_449
node _T_450 = bits(_WIRE_29, 18, 18)
connect _WIRE_28.ae_final, _T_450
node _T_451 = bits(_WIRE_29, 19, 19)
connect _WIRE_28.ae_ptw, _T_451
node _T_452 = bits(_WIRE_29, 20, 20)
connect _WIRE_28.g, _T_452
node _T_453 = bits(_WIRE_29, 21, 21)
connect _WIRE_28.u, _T_453
node _T_454 = bits(_WIRE_29, 41, 22)
connect _WIRE_28.ppn, _T_454
wire _WIRE_30 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_31 : UInt<42>
connect _WIRE_31, sectored_entries[0][0].data[3]
node _T_455 = bits(_WIRE_31, 0, 0)
connect _WIRE_30.fragmented_superpage, _T_455
node _T_456 = bits(_WIRE_31, 1, 1)
connect _WIRE_30.c, _T_456
node _T_457 = bits(_WIRE_31, 2, 2)
connect _WIRE_30.eff, _T_457
node _T_458 = bits(_WIRE_31, 3, 3)
connect _WIRE_30.paa, _T_458
node _T_459 = bits(_WIRE_31, 4, 4)
connect _WIRE_30.pal, _T_459
node _T_460 = bits(_WIRE_31, 5, 5)
connect _WIRE_30.ppp, _T_460
node _T_461 = bits(_WIRE_31, 6, 6)
connect _WIRE_30.pr, _T_461
node _T_462 = bits(_WIRE_31, 7, 7)
connect _WIRE_30.px, _T_462
node _T_463 = bits(_WIRE_31, 8, 8)
connect _WIRE_30.pw, _T_463
node _T_464 = bits(_WIRE_31, 9, 9)
connect _WIRE_30.hr, _T_464
node _T_465 = bits(_WIRE_31, 10, 10)
connect _WIRE_30.hx, _T_465
node _T_466 = bits(_WIRE_31, 11, 11)
connect _WIRE_30.hw, _T_466
node _T_467 = bits(_WIRE_31, 12, 12)
connect _WIRE_30.sr, _T_467
node _T_468 = bits(_WIRE_31, 13, 13)
connect _WIRE_30.sx, _T_468
node _T_469 = bits(_WIRE_31, 14, 14)
connect _WIRE_30.sw, _T_469
node _T_470 = bits(_WIRE_31, 15, 15)
connect _WIRE_30.gf, _T_470
node _T_471 = bits(_WIRE_31, 16, 16)
connect _WIRE_30.pf, _T_471
node _T_472 = bits(_WIRE_31, 17, 17)
connect _WIRE_30.ae_stage2, _T_472
node _T_473 = bits(_WIRE_31, 18, 18)
connect _WIRE_30.ae_final, _T_473
node _T_474 = bits(_WIRE_31, 19, 19)
connect _WIRE_30.ae_ptw, _T_474
node _T_475 = bits(_WIRE_31, 20, 20)
connect _WIRE_30.g, _T_475
node _T_476 = bits(_WIRE_31, 21, 21)
connect _WIRE_30.u, _T_476
node _T_477 = bits(_WIRE_31, 41, 22)
connect _WIRE_30.ppn, _T_477
node _T_478 = eq(sectored_entries[0][0].tag_v, _T_385)
when _T_478 :
connect sectored_entries[0][0].valid[0], UInt<1>(0h0)
node _T_479 = eq(sectored_entries[0][0].tag_v, _T_385)
when _T_479 :
connect sectored_entries[0][0].valid[1], UInt<1>(0h0)
node _T_480 = eq(sectored_entries[0][0].tag_v, _T_385)
when _T_480 :
connect sectored_entries[0][0].valid[2], UInt<1>(0h0)
node _T_481 = eq(sectored_entries[0][0].tag_v, _T_385)
when _T_481 :
connect sectored_entries[0][0].valid[3], UInt<1>(0h0)
node hv_1 = and(UInt<1>(0h0), io.sfence.bits.hv)
node hg_1 = and(UInt<1>(0h0), io.sfence.bits.hg)
node _T_482 = eq(hg_1, UInt<1>(0h0))
node _T_483 = and(_T_482, io.sfence.bits.rs1)
when _T_483 :
node _T_484 = xor(sectored_entries[0][1].tag_vpn, vpn)
node _T_485 = shr(_T_484, 2)
node _T_486 = eq(_T_485, UInt<1>(0h0))
node _T_487 = eq(sectored_entries[0][1].tag_v, hv_1)
node _T_488 = and(_T_486, _T_487)
when _T_488 :
wire _WIRE_32 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_33 : UInt<42>
connect _WIRE_33, sectored_entries[0][1].data[0]
node _T_489 = bits(_WIRE_33, 0, 0)
connect _WIRE_32.fragmented_superpage, _T_489
node _T_490 = bits(_WIRE_33, 1, 1)
connect _WIRE_32.c, _T_490
node _T_491 = bits(_WIRE_33, 2, 2)
connect _WIRE_32.eff, _T_491
node _T_492 = bits(_WIRE_33, 3, 3)
connect _WIRE_32.paa, _T_492
node _T_493 = bits(_WIRE_33, 4, 4)
connect _WIRE_32.pal, _T_493
node _T_494 = bits(_WIRE_33, 5, 5)
connect _WIRE_32.ppp, _T_494
node _T_495 = bits(_WIRE_33, 6, 6)
connect _WIRE_32.pr, _T_495
node _T_496 = bits(_WIRE_33, 7, 7)
connect _WIRE_32.px, _T_496
node _T_497 = bits(_WIRE_33, 8, 8)
connect _WIRE_32.pw, _T_497
node _T_498 = bits(_WIRE_33, 9, 9)
connect _WIRE_32.hr, _T_498
node _T_499 = bits(_WIRE_33, 10, 10)
connect _WIRE_32.hx, _T_499
node _T_500 = bits(_WIRE_33, 11, 11)
connect _WIRE_32.hw, _T_500
node _T_501 = bits(_WIRE_33, 12, 12)
connect _WIRE_32.sr, _T_501
node _T_502 = bits(_WIRE_33, 13, 13)
connect _WIRE_32.sx, _T_502
node _T_503 = bits(_WIRE_33, 14, 14)
connect _WIRE_32.sw, _T_503
node _T_504 = bits(_WIRE_33, 15, 15)
connect _WIRE_32.gf, _T_504
node _T_505 = bits(_WIRE_33, 16, 16)
connect _WIRE_32.pf, _T_505
node _T_506 = bits(_WIRE_33, 17, 17)
connect _WIRE_32.ae_stage2, _T_506
node _T_507 = bits(_WIRE_33, 18, 18)
connect _WIRE_32.ae_final, _T_507
node _T_508 = bits(_WIRE_33, 19, 19)
connect _WIRE_32.ae_ptw, _T_508
node _T_509 = bits(_WIRE_33, 20, 20)
connect _WIRE_32.g, _T_509
node _T_510 = bits(_WIRE_33, 21, 21)
connect _WIRE_32.u, _T_510
node _T_511 = bits(_WIRE_33, 41, 22)
connect _WIRE_32.ppn, _T_511
wire _WIRE_34 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_35 : UInt<42>
connect _WIRE_35, sectored_entries[0][1].data[1]
node _T_512 = bits(_WIRE_35, 0, 0)
connect _WIRE_34.fragmented_superpage, _T_512
node _T_513 = bits(_WIRE_35, 1, 1)
connect _WIRE_34.c, _T_513
node _T_514 = bits(_WIRE_35, 2, 2)
connect _WIRE_34.eff, _T_514
node _T_515 = bits(_WIRE_35, 3, 3)
connect _WIRE_34.paa, _T_515
node _T_516 = bits(_WIRE_35, 4, 4)
connect _WIRE_34.pal, _T_516
node _T_517 = bits(_WIRE_35, 5, 5)
connect _WIRE_34.ppp, _T_517
node _T_518 = bits(_WIRE_35, 6, 6)
connect _WIRE_34.pr, _T_518
node _T_519 = bits(_WIRE_35, 7, 7)
connect _WIRE_34.px, _T_519
node _T_520 = bits(_WIRE_35, 8, 8)
connect _WIRE_34.pw, _T_520
node _T_521 = bits(_WIRE_35, 9, 9)
connect _WIRE_34.hr, _T_521
node _T_522 = bits(_WIRE_35, 10, 10)
connect _WIRE_34.hx, _T_522
node _T_523 = bits(_WIRE_35, 11, 11)
connect _WIRE_34.hw, _T_523
node _T_524 = bits(_WIRE_35, 12, 12)
connect _WIRE_34.sr, _T_524
node _T_525 = bits(_WIRE_35, 13, 13)
connect _WIRE_34.sx, _T_525
node _T_526 = bits(_WIRE_35, 14, 14)
connect _WIRE_34.sw, _T_526
node _T_527 = bits(_WIRE_35, 15, 15)
connect _WIRE_34.gf, _T_527
node _T_528 = bits(_WIRE_35, 16, 16)
connect _WIRE_34.pf, _T_528
node _T_529 = bits(_WIRE_35, 17, 17)
connect _WIRE_34.ae_stage2, _T_529
node _T_530 = bits(_WIRE_35, 18, 18)
connect _WIRE_34.ae_final, _T_530
node _T_531 = bits(_WIRE_35, 19, 19)
connect _WIRE_34.ae_ptw, _T_531
node _T_532 = bits(_WIRE_35, 20, 20)
connect _WIRE_34.g, _T_532
node _T_533 = bits(_WIRE_35, 21, 21)
connect _WIRE_34.u, _T_533
node _T_534 = bits(_WIRE_35, 41, 22)
connect _WIRE_34.ppn, _T_534
wire _WIRE_36 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_37 : UInt<42>
connect _WIRE_37, sectored_entries[0][1].data[2]
node _T_535 = bits(_WIRE_37, 0, 0)
connect _WIRE_36.fragmented_superpage, _T_535
node _T_536 = bits(_WIRE_37, 1, 1)
connect _WIRE_36.c, _T_536
node _T_537 = bits(_WIRE_37, 2, 2)
connect _WIRE_36.eff, _T_537
node _T_538 = bits(_WIRE_37, 3, 3)
connect _WIRE_36.paa, _T_538
node _T_539 = bits(_WIRE_37, 4, 4)
connect _WIRE_36.pal, _T_539
node _T_540 = bits(_WIRE_37, 5, 5)
connect _WIRE_36.ppp, _T_540
node _T_541 = bits(_WIRE_37, 6, 6)
connect _WIRE_36.pr, _T_541
node _T_542 = bits(_WIRE_37, 7, 7)
connect _WIRE_36.px, _T_542
node _T_543 = bits(_WIRE_37, 8, 8)
connect _WIRE_36.pw, _T_543
node _T_544 = bits(_WIRE_37, 9, 9)
connect _WIRE_36.hr, _T_544
node _T_545 = bits(_WIRE_37, 10, 10)
connect _WIRE_36.hx, _T_545
node _T_546 = bits(_WIRE_37, 11, 11)
connect _WIRE_36.hw, _T_546
node _T_547 = bits(_WIRE_37, 12, 12)
connect _WIRE_36.sr, _T_547
node _T_548 = bits(_WIRE_37, 13, 13)
connect _WIRE_36.sx, _T_548
node _T_549 = bits(_WIRE_37, 14, 14)
connect _WIRE_36.sw, _T_549
node _T_550 = bits(_WIRE_37, 15, 15)
connect _WIRE_36.gf, _T_550
node _T_551 = bits(_WIRE_37, 16, 16)
connect _WIRE_36.pf, _T_551
node _T_552 = bits(_WIRE_37, 17, 17)
connect _WIRE_36.ae_stage2, _T_552
node _T_553 = bits(_WIRE_37, 18, 18)
connect _WIRE_36.ae_final, _T_553
node _T_554 = bits(_WIRE_37, 19, 19)
connect _WIRE_36.ae_ptw, _T_554
node _T_555 = bits(_WIRE_37, 20, 20)
connect _WIRE_36.g, _T_555
node _T_556 = bits(_WIRE_37, 21, 21)
connect _WIRE_36.u, _T_556
node _T_557 = bits(_WIRE_37, 41, 22)
connect _WIRE_36.ppn, _T_557
wire _WIRE_38 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_39 : UInt<42>
connect _WIRE_39, sectored_entries[0][1].data[3]
node _T_558 = bits(_WIRE_39, 0, 0)
connect _WIRE_38.fragmented_superpage, _T_558
node _T_559 = bits(_WIRE_39, 1, 1)
connect _WIRE_38.c, _T_559
node _T_560 = bits(_WIRE_39, 2, 2)
connect _WIRE_38.eff, _T_560
node _T_561 = bits(_WIRE_39, 3, 3)
connect _WIRE_38.paa, _T_561
node _T_562 = bits(_WIRE_39, 4, 4)
connect _WIRE_38.pal, _T_562
node _T_563 = bits(_WIRE_39, 5, 5)
connect _WIRE_38.ppp, _T_563
node _T_564 = bits(_WIRE_39, 6, 6)
connect _WIRE_38.pr, _T_564
node _T_565 = bits(_WIRE_39, 7, 7)
connect _WIRE_38.px, _T_565
node _T_566 = bits(_WIRE_39, 8, 8)
connect _WIRE_38.pw, _T_566
node _T_567 = bits(_WIRE_39, 9, 9)
connect _WIRE_38.hr, _T_567
node _T_568 = bits(_WIRE_39, 10, 10)
connect _WIRE_38.hx, _T_568
node _T_569 = bits(_WIRE_39, 11, 11)
connect _WIRE_38.hw, _T_569
node _T_570 = bits(_WIRE_39, 12, 12)
connect _WIRE_38.sr, _T_570
node _T_571 = bits(_WIRE_39, 13, 13)
connect _WIRE_38.sx, _T_571
node _T_572 = bits(_WIRE_39, 14, 14)
connect _WIRE_38.sw, _T_572
node _T_573 = bits(_WIRE_39, 15, 15)
connect _WIRE_38.gf, _T_573
node _T_574 = bits(_WIRE_39, 16, 16)
connect _WIRE_38.pf, _T_574
node _T_575 = bits(_WIRE_39, 17, 17)
connect _WIRE_38.ae_stage2, _T_575
node _T_576 = bits(_WIRE_39, 18, 18)
connect _WIRE_38.ae_final, _T_576
node _T_577 = bits(_WIRE_39, 19, 19)
connect _WIRE_38.ae_ptw, _T_577
node _T_578 = bits(_WIRE_39, 20, 20)
connect _WIRE_38.g, _T_578
node _T_579 = bits(_WIRE_39, 21, 21)
connect _WIRE_38.u, _T_579
node _T_580 = bits(_WIRE_39, 41, 22)
connect _WIRE_38.ppn, _T_580
node _T_581 = eq(sectored_entries[0][1].tag_v, hv_1)
node _T_582 = bits(vpn, 1, 0)
node _T_583 = eq(UInt<1>(0h0), _T_582)
node _T_584 = and(_T_581, _T_583)
when _T_584 :
connect sectored_entries[0][1].valid[0], UInt<1>(0h0)
node _T_585 = eq(sectored_entries[0][1].tag_v, hv_1)
node _T_586 = bits(vpn, 1, 0)
node _T_587 = eq(UInt<1>(0h1), _T_586)
node _T_588 = and(_T_585, _T_587)
when _T_588 :
connect sectored_entries[0][1].valid[1], UInt<1>(0h0)
node _T_589 = eq(sectored_entries[0][1].tag_v, hv_1)
node _T_590 = bits(vpn, 1, 0)
node _T_591 = eq(UInt<2>(0h2), _T_590)
node _T_592 = and(_T_589, _T_591)
when _T_592 :
connect sectored_entries[0][1].valid[2], UInt<1>(0h0)
node _T_593 = eq(sectored_entries[0][1].tag_v, hv_1)
node _T_594 = bits(vpn, 1, 0)
node _T_595 = eq(UInt<2>(0h3), _T_594)
node _T_596 = and(_T_593, _T_595)
when _T_596 :
connect sectored_entries[0][1].valid[3], UInt<1>(0h0)
node _T_597 = xor(sectored_entries[0][1].tag_vpn, vpn)
node _T_598 = shr(_T_597, 18)
node _T_599 = eq(_T_598, UInt<1>(0h0))
when _T_599 :
wire _WIRE_40 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_41 : UInt<42>
connect _WIRE_41, sectored_entries[0][1].data[0]
node _T_600 = bits(_WIRE_41, 0, 0)
connect _WIRE_40.fragmented_superpage, _T_600
node _T_601 = bits(_WIRE_41, 1, 1)
connect _WIRE_40.c, _T_601
node _T_602 = bits(_WIRE_41, 2, 2)
connect _WIRE_40.eff, _T_602
node _T_603 = bits(_WIRE_41, 3, 3)
connect _WIRE_40.paa, _T_603
node _T_604 = bits(_WIRE_41, 4, 4)
connect _WIRE_40.pal, _T_604
node _T_605 = bits(_WIRE_41, 5, 5)
connect _WIRE_40.ppp, _T_605
node _T_606 = bits(_WIRE_41, 6, 6)
connect _WIRE_40.pr, _T_606
node _T_607 = bits(_WIRE_41, 7, 7)
connect _WIRE_40.px, _T_607
node _T_608 = bits(_WIRE_41, 8, 8)
connect _WIRE_40.pw, _T_608
node _T_609 = bits(_WIRE_41, 9, 9)
connect _WIRE_40.hr, _T_609
node _T_610 = bits(_WIRE_41, 10, 10)
connect _WIRE_40.hx, _T_610
node _T_611 = bits(_WIRE_41, 11, 11)
connect _WIRE_40.hw, _T_611
node _T_612 = bits(_WIRE_41, 12, 12)
connect _WIRE_40.sr, _T_612
node _T_613 = bits(_WIRE_41, 13, 13)
connect _WIRE_40.sx, _T_613
node _T_614 = bits(_WIRE_41, 14, 14)
connect _WIRE_40.sw, _T_614
node _T_615 = bits(_WIRE_41, 15, 15)
connect _WIRE_40.gf, _T_615
node _T_616 = bits(_WIRE_41, 16, 16)
connect _WIRE_40.pf, _T_616
node _T_617 = bits(_WIRE_41, 17, 17)
connect _WIRE_40.ae_stage2, _T_617
node _T_618 = bits(_WIRE_41, 18, 18)
connect _WIRE_40.ae_final, _T_618
node _T_619 = bits(_WIRE_41, 19, 19)
connect _WIRE_40.ae_ptw, _T_619
node _T_620 = bits(_WIRE_41, 20, 20)
connect _WIRE_40.g, _T_620
node _T_621 = bits(_WIRE_41, 21, 21)
connect _WIRE_40.u, _T_621
node _T_622 = bits(_WIRE_41, 41, 22)
connect _WIRE_40.ppn, _T_622
wire _WIRE_42 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_43 : UInt<42>
connect _WIRE_43, sectored_entries[0][1].data[1]
node _T_623 = bits(_WIRE_43, 0, 0)
connect _WIRE_42.fragmented_superpage, _T_623
node _T_624 = bits(_WIRE_43, 1, 1)
connect _WIRE_42.c, _T_624
node _T_625 = bits(_WIRE_43, 2, 2)
connect _WIRE_42.eff, _T_625
node _T_626 = bits(_WIRE_43, 3, 3)
connect _WIRE_42.paa, _T_626
node _T_627 = bits(_WIRE_43, 4, 4)
connect _WIRE_42.pal, _T_627
node _T_628 = bits(_WIRE_43, 5, 5)
connect _WIRE_42.ppp, _T_628
node _T_629 = bits(_WIRE_43, 6, 6)
connect _WIRE_42.pr, _T_629
node _T_630 = bits(_WIRE_43, 7, 7)
connect _WIRE_42.px, _T_630
node _T_631 = bits(_WIRE_43, 8, 8)
connect _WIRE_42.pw, _T_631
node _T_632 = bits(_WIRE_43, 9, 9)
connect _WIRE_42.hr, _T_632
node _T_633 = bits(_WIRE_43, 10, 10)
connect _WIRE_42.hx, _T_633
node _T_634 = bits(_WIRE_43, 11, 11)
connect _WIRE_42.hw, _T_634
node _T_635 = bits(_WIRE_43, 12, 12)
connect _WIRE_42.sr, _T_635
node _T_636 = bits(_WIRE_43, 13, 13)
connect _WIRE_42.sx, _T_636
node _T_637 = bits(_WIRE_43, 14, 14)
connect _WIRE_42.sw, _T_637
node _T_638 = bits(_WIRE_43, 15, 15)
connect _WIRE_42.gf, _T_638
node _T_639 = bits(_WIRE_43, 16, 16)
connect _WIRE_42.pf, _T_639
node _T_640 = bits(_WIRE_43, 17, 17)
connect _WIRE_42.ae_stage2, _T_640
node _T_641 = bits(_WIRE_43, 18, 18)
connect _WIRE_42.ae_final, _T_641
node _T_642 = bits(_WIRE_43, 19, 19)
connect _WIRE_42.ae_ptw, _T_642
node _T_643 = bits(_WIRE_43, 20, 20)
connect _WIRE_42.g, _T_643
node _T_644 = bits(_WIRE_43, 21, 21)
connect _WIRE_42.u, _T_644
node _T_645 = bits(_WIRE_43, 41, 22)
connect _WIRE_42.ppn, _T_645
wire _WIRE_44 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_45 : UInt<42>
connect _WIRE_45, sectored_entries[0][1].data[2]
node _T_646 = bits(_WIRE_45, 0, 0)
connect _WIRE_44.fragmented_superpage, _T_646
node _T_647 = bits(_WIRE_45, 1, 1)
connect _WIRE_44.c, _T_647
node _T_648 = bits(_WIRE_45, 2, 2)
connect _WIRE_44.eff, _T_648
node _T_649 = bits(_WIRE_45, 3, 3)
connect _WIRE_44.paa, _T_649
node _T_650 = bits(_WIRE_45, 4, 4)
connect _WIRE_44.pal, _T_650
node _T_651 = bits(_WIRE_45, 5, 5)
connect _WIRE_44.ppp, _T_651
node _T_652 = bits(_WIRE_45, 6, 6)
connect _WIRE_44.pr, _T_652
node _T_653 = bits(_WIRE_45, 7, 7)
connect _WIRE_44.px, _T_653
node _T_654 = bits(_WIRE_45, 8, 8)
connect _WIRE_44.pw, _T_654
node _T_655 = bits(_WIRE_45, 9, 9)
connect _WIRE_44.hr, _T_655
node _T_656 = bits(_WIRE_45, 10, 10)
connect _WIRE_44.hx, _T_656
node _T_657 = bits(_WIRE_45, 11, 11)
connect _WIRE_44.hw, _T_657
node _T_658 = bits(_WIRE_45, 12, 12)
connect _WIRE_44.sr, _T_658
node _T_659 = bits(_WIRE_45, 13, 13)
connect _WIRE_44.sx, _T_659
node _T_660 = bits(_WIRE_45, 14, 14)
connect _WIRE_44.sw, _T_660
node _T_661 = bits(_WIRE_45, 15, 15)
connect _WIRE_44.gf, _T_661
node _T_662 = bits(_WIRE_45, 16, 16)
connect _WIRE_44.pf, _T_662
node _T_663 = bits(_WIRE_45, 17, 17)
connect _WIRE_44.ae_stage2, _T_663
node _T_664 = bits(_WIRE_45, 18, 18)
connect _WIRE_44.ae_final, _T_664
node _T_665 = bits(_WIRE_45, 19, 19)
connect _WIRE_44.ae_ptw, _T_665
node _T_666 = bits(_WIRE_45, 20, 20)
connect _WIRE_44.g, _T_666
node _T_667 = bits(_WIRE_45, 21, 21)
connect _WIRE_44.u, _T_667
node _T_668 = bits(_WIRE_45, 41, 22)
connect _WIRE_44.ppn, _T_668
wire _WIRE_46 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_47 : UInt<42>
connect _WIRE_47, sectored_entries[0][1].data[3]
node _T_669 = bits(_WIRE_47, 0, 0)
connect _WIRE_46.fragmented_superpage, _T_669
node _T_670 = bits(_WIRE_47, 1, 1)
connect _WIRE_46.c, _T_670
node _T_671 = bits(_WIRE_47, 2, 2)
connect _WIRE_46.eff, _T_671
node _T_672 = bits(_WIRE_47, 3, 3)
connect _WIRE_46.paa, _T_672
node _T_673 = bits(_WIRE_47, 4, 4)
connect _WIRE_46.pal, _T_673
node _T_674 = bits(_WIRE_47, 5, 5)
connect _WIRE_46.ppp, _T_674
node _T_675 = bits(_WIRE_47, 6, 6)
connect _WIRE_46.pr, _T_675
node _T_676 = bits(_WIRE_47, 7, 7)
connect _WIRE_46.px, _T_676
node _T_677 = bits(_WIRE_47, 8, 8)
connect _WIRE_46.pw, _T_677
node _T_678 = bits(_WIRE_47, 9, 9)
connect _WIRE_46.hr, _T_678
node _T_679 = bits(_WIRE_47, 10, 10)
connect _WIRE_46.hx, _T_679
node _T_680 = bits(_WIRE_47, 11, 11)
connect _WIRE_46.hw, _T_680
node _T_681 = bits(_WIRE_47, 12, 12)
connect _WIRE_46.sr, _T_681
node _T_682 = bits(_WIRE_47, 13, 13)
connect _WIRE_46.sx, _T_682
node _T_683 = bits(_WIRE_47, 14, 14)
connect _WIRE_46.sw, _T_683
node _T_684 = bits(_WIRE_47, 15, 15)
connect _WIRE_46.gf, _T_684
node _T_685 = bits(_WIRE_47, 16, 16)
connect _WIRE_46.pf, _T_685
node _T_686 = bits(_WIRE_47, 17, 17)
connect _WIRE_46.ae_stage2, _T_686
node _T_687 = bits(_WIRE_47, 18, 18)
connect _WIRE_46.ae_final, _T_687
node _T_688 = bits(_WIRE_47, 19, 19)
connect _WIRE_46.ae_ptw, _T_688
node _T_689 = bits(_WIRE_47, 20, 20)
connect _WIRE_46.g, _T_689
node _T_690 = bits(_WIRE_47, 21, 21)
connect _WIRE_46.u, _T_690
node _T_691 = bits(_WIRE_47, 41, 22)
connect _WIRE_46.ppn, _T_691
node _T_692 = eq(sectored_entries[0][1].tag_v, hv_1)
node _T_693 = and(_T_692, _WIRE_40.fragmented_superpage)
when _T_693 :
connect sectored_entries[0][1].valid[0], UInt<1>(0h0)
node _T_694 = eq(sectored_entries[0][1].tag_v, hv_1)
node _T_695 = and(_T_694, _WIRE_42.fragmented_superpage)
when _T_695 :
connect sectored_entries[0][1].valid[1], UInt<1>(0h0)
node _T_696 = eq(sectored_entries[0][1].tag_v, hv_1)
node _T_697 = and(_T_696, _WIRE_44.fragmented_superpage)
when _T_697 :
connect sectored_entries[0][1].valid[2], UInt<1>(0h0)
node _T_698 = eq(sectored_entries[0][1].tag_v, hv_1)
node _T_699 = and(_T_698, _WIRE_46.fragmented_superpage)
when _T_699 :
connect sectored_entries[0][1].valid[3], UInt<1>(0h0)
else :
node _T_700 = eq(hg_1, UInt<1>(0h0))
node _T_701 = and(_T_700, io.sfence.bits.rs2)
when _T_701 :
wire _WIRE_48 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_49 : UInt<42>
connect _WIRE_49, sectored_entries[0][1].data[0]
node _T_702 = bits(_WIRE_49, 0, 0)
connect _WIRE_48.fragmented_superpage, _T_702
node _T_703 = bits(_WIRE_49, 1, 1)
connect _WIRE_48.c, _T_703
node _T_704 = bits(_WIRE_49, 2, 2)
connect _WIRE_48.eff, _T_704
node _T_705 = bits(_WIRE_49, 3, 3)
connect _WIRE_48.paa, _T_705
node _T_706 = bits(_WIRE_49, 4, 4)
connect _WIRE_48.pal, _T_706
node _T_707 = bits(_WIRE_49, 5, 5)
connect _WIRE_48.ppp, _T_707
node _T_708 = bits(_WIRE_49, 6, 6)
connect _WIRE_48.pr, _T_708
node _T_709 = bits(_WIRE_49, 7, 7)
connect _WIRE_48.px, _T_709
node _T_710 = bits(_WIRE_49, 8, 8)
connect _WIRE_48.pw, _T_710
node _T_711 = bits(_WIRE_49, 9, 9)
connect _WIRE_48.hr, _T_711
node _T_712 = bits(_WIRE_49, 10, 10)
connect _WIRE_48.hx, _T_712
node _T_713 = bits(_WIRE_49, 11, 11)
connect _WIRE_48.hw, _T_713
node _T_714 = bits(_WIRE_49, 12, 12)
connect _WIRE_48.sr, _T_714
node _T_715 = bits(_WIRE_49, 13, 13)
connect _WIRE_48.sx, _T_715
node _T_716 = bits(_WIRE_49, 14, 14)
connect _WIRE_48.sw, _T_716
node _T_717 = bits(_WIRE_49, 15, 15)
connect _WIRE_48.gf, _T_717
node _T_718 = bits(_WIRE_49, 16, 16)
connect _WIRE_48.pf, _T_718
node _T_719 = bits(_WIRE_49, 17, 17)
connect _WIRE_48.ae_stage2, _T_719
node _T_720 = bits(_WIRE_49, 18, 18)
connect _WIRE_48.ae_final, _T_720
node _T_721 = bits(_WIRE_49, 19, 19)
connect _WIRE_48.ae_ptw, _T_721
node _T_722 = bits(_WIRE_49, 20, 20)
connect _WIRE_48.g, _T_722
node _T_723 = bits(_WIRE_49, 21, 21)
connect _WIRE_48.u, _T_723
node _T_724 = bits(_WIRE_49, 41, 22)
connect _WIRE_48.ppn, _T_724
wire _WIRE_50 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_51 : UInt<42>
connect _WIRE_51, sectored_entries[0][1].data[1]
node _T_725 = bits(_WIRE_51, 0, 0)
connect _WIRE_50.fragmented_superpage, _T_725
node _T_726 = bits(_WIRE_51, 1, 1)
connect _WIRE_50.c, _T_726
node _T_727 = bits(_WIRE_51, 2, 2)
connect _WIRE_50.eff, _T_727
node _T_728 = bits(_WIRE_51, 3, 3)
connect _WIRE_50.paa, _T_728
node _T_729 = bits(_WIRE_51, 4, 4)
connect _WIRE_50.pal, _T_729
node _T_730 = bits(_WIRE_51, 5, 5)
connect _WIRE_50.ppp, _T_730
node _T_731 = bits(_WIRE_51, 6, 6)
connect _WIRE_50.pr, _T_731
node _T_732 = bits(_WIRE_51, 7, 7)
connect _WIRE_50.px, _T_732
node _T_733 = bits(_WIRE_51, 8, 8)
connect _WIRE_50.pw, _T_733
node _T_734 = bits(_WIRE_51, 9, 9)
connect _WIRE_50.hr, _T_734
node _T_735 = bits(_WIRE_51, 10, 10)
connect _WIRE_50.hx, _T_735
node _T_736 = bits(_WIRE_51, 11, 11)
connect _WIRE_50.hw, _T_736
node _T_737 = bits(_WIRE_51, 12, 12)
connect _WIRE_50.sr, _T_737
node _T_738 = bits(_WIRE_51, 13, 13)
connect _WIRE_50.sx, _T_738
node _T_739 = bits(_WIRE_51, 14, 14)
connect _WIRE_50.sw, _T_739
node _T_740 = bits(_WIRE_51, 15, 15)
connect _WIRE_50.gf, _T_740
node _T_741 = bits(_WIRE_51, 16, 16)
connect _WIRE_50.pf, _T_741
node _T_742 = bits(_WIRE_51, 17, 17)
connect _WIRE_50.ae_stage2, _T_742
node _T_743 = bits(_WIRE_51, 18, 18)
connect _WIRE_50.ae_final, _T_743
node _T_744 = bits(_WIRE_51, 19, 19)
connect _WIRE_50.ae_ptw, _T_744
node _T_745 = bits(_WIRE_51, 20, 20)
connect _WIRE_50.g, _T_745
node _T_746 = bits(_WIRE_51, 21, 21)
connect _WIRE_50.u, _T_746
node _T_747 = bits(_WIRE_51, 41, 22)
connect _WIRE_50.ppn, _T_747
wire _WIRE_52 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_53 : UInt<42>
connect _WIRE_53, sectored_entries[0][1].data[2]
node _T_748 = bits(_WIRE_53, 0, 0)
connect _WIRE_52.fragmented_superpage, _T_748
node _T_749 = bits(_WIRE_53, 1, 1)
connect _WIRE_52.c, _T_749
node _T_750 = bits(_WIRE_53, 2, 2)
connect _WIRE_52.eff, _T_750
node _T_751 = bits(_WIRE_53, 3, 3)
connect _WIRE_52.paa, _T_751
node _T_752 = bits(_WIRE_53, 4, 4)
connect _WIRE_52.pal, _T_752
node _T_753 = bits(_WIRE_53, 5, 5)
connect _WIRE_52.ppp, _T_753
node _T_754 = bits(_WIRE_53, 6, 6)
connect _WIRE_52.pr, _T_754
node _T_755 = bits(_WIRE_53, 7, 7)
connect _WIRE_52.px, _T_755
node _T_756 = bits(_WIRE_53, 8, 8)
connect _WIRE_52.pw, _T_756
node _T_757 = bits(_WIRE_53, 9, 9)
connect _WIRE_52.hr, _T_757
node _T_758 = bits(_WIRE_53, 10, 10)
connect _WIRE_52.hx, _T_758
node _T_759 = bits(_WIRE_53, 11, 11)
connect _WIRE_52.hw, _T_759
node _T_760 = bits(_WIRE_53, 12, 12)
connect _WIRE_52.sr, _T_760
node _T_761 = bits(_WIRE_53, 13, 13)
connect _WIRE_52.sx, _T_761
node _T_762 = bits(_WIRE_53, 14, 14)
connect _WIRE_52.sw, _T_762
node _T_763 = bits(_WIRE_53, 15, 15)
connect _WIRE_52.gf, _T_763
node _T_764 = bits(_WIRE_53, 16, 16)
connect _WIRE_52.pf, _T_764
node _T_765 = bits(_WIRE_53, 17, 17)
connect _WIRE_52.ae_stage2, _T_765
node _T_766 = bits(_WIRE_53, 18, 18)
connect _WIRE_52.ae_final, _T_766
node _T_767 = bits(_WIRE_53, 19, 19)
connect _WIRE_52.ae_ptw, _T_767
node _T_768 = bits(_WIRE_53, 20, 20)
connect _WIRE_52.g, _T_768
node _T_769 = bits(_WIRE_53, 21, 21)
connect _WIRE_52.u, _T_769
node _T_770 = bits(_WIRE_53, 41, 22)
connect _WIRE_52.ppn, _T_770
wire _WIRE_54 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_55 : UInt<42>
connect _WIRE_55, sectored_entries[0][1].data[3]
node _T_771 = bits(_WIRE_55, 0, 0)
connect _WIRE_54.fragmented_superpage, _T_771
node _T_772 = bits(_WIRE_55, 1, 1)
connect _WIRE_54.c, _T_772
node _T_773 = bits(_WIRE_55, 2, 2)
connect _WIRE_54.eff, _T_773
node _T_774 = bits(_WIRE_55, 3, 3)
connect _WIRE_54.paa, _T_774
node _T_775 = bits(_WIRE_55, 4, 4)
connect _WIRE_54.pal, _T_775
node _T_776 = bits(_WIRE_55, 5, 5)
connect _WIRE_54.ppp, _T_776
node _T_777 = bits(_WIRE_55, 6, 6)
connect _WIRE_54.pr, _T_777
node _T_778 = bits(_WIRE_55, 7, 7)
connect _WIRE_54.px, _T_778
node _T_779 = bits(_WIRE_55, 8, 8)
connect _WIRE_54.pw, _T_779
node _T_780 = bits(_WIRE_55, 9, 9)
connect _WIRE_54.hr, _T_780
node _T_781 = bits(_WIRE_55, 10, 10)
connect _WIRE_54.hx, _T_781
node _T_782 = bits(_WIRE_55, 11, 11)
connect _WIRE_54.hw, _T_782
node _T_783 = bits(_WIRE_55, 12, 12)
connect _WIRE_54.sr, _T_783
node _T_784 = bits(_WIRE_55, 13, 13)
connect _WIRE_54.sx, _T_784
node _T_785 = bits(_WIRE_55, 14, 14)
connect _WIRE_54.sw, _T_785
node _T_786 = bits(_WIRE_55, 15, 15)
connect _WIRE_54.gf, _T_786
node _T_787 = bits(_WIRE_55, 16, 16)
connect _WIRE_54.pf, _T_787
node _T_788 = bits(_WIRE_55, 17, 17)
connect _WIRE_54.ae_stage2, _T_788
node _T_789 = bits(_WIRE_55, 18, 18)
connect _WIRE_54.ae_final, _T_789
node _T_790 = bits(_WIRE_55, 19, 19)
connect _WIRE_54.ae_ptw, _T_790
node _T_791 = bits(_WIRE_55, 20, 20)
connect _WIRE_54.g, _T_791
node _T_792 = bits(_WIRE_55, 21, 21)
connect _WIRE_54.u, _T_792
node _T_793 = bits(_WIRE_55, 41, 22)
connect _WIRE_54.ppn, _T_793
node _T_794 = eq(sectored_entries[0][1].tag_v, hv_1)
node _T_795 = eq(_WIRE_48.g, UInt<1>(0h0))
node _T_796 = and(_T_794, _T_795)
when _T_796 :
connect sectored_entries[0][1].valid[0], UInt<1>(0h0)
node _T_797 = eq(sectored_entries[0][1].tag_v, hv_1)
node _T_798 = eq(_WIRE_50.g, UInt<1>(0h0))
node _T_799 = and(_T_797, _T_798)
when _T_799 :
connect sectored_entries[0][1].valid[1], UInt<1>(0h0)
node _T_800 = eq(sectored_entries[0][1].tag_v, hv_1)
node _T_801 = eq(_WIRE_52.g, UInt<1>(0h0))
node _T_802 = and(_T_800, _T_801)
when _T_802 :
connect sectored_entries[0][1].valid[2], UInt<1>(0h0)
node _T_803 = eq(sectored_entries[0][1].tag_v, hv_1)
node _T_804 = eq(_WIRE_54.g, UInt<1>(0h0))
node _T_805 = and(_T_803, _T_804)
when _T_805 :
connect sectored_entries[0][1].valid[3], UInt<1>(0h0)
else :
node _T_806 = or(hv_1, hg_1)
wire _WIRE_56 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_57 : UInt<42>
connect _WIRE_57, sectored_entries[0][1].data[0]
node _T_807 = bits(_WIRE_57, 0, 0)
connect _WIRE_56.fragmented_superpage, _T_807
node _T_808 = bits(_WIRE_57, 1, 1)
connect _WIRE_56.c, _T_808
node _T_809 = bits(_WIRE_57, 2, 2)
connect _WIRE_56.eff, _T_809
node _T_810 = bits(_WIRE_57, 3, 3)
connect _WIRE_56.paa, _T_810
node _T_811 = bits(_WIRE_57, 4, 4)
connect _WIRE_56.pal, _T_811
node _T_812 = bits(_WIRE_57, 5, 5)
connect _WIRE_56.ppp, _T_812
node _T_813 = bits(_WIRE_57, 6, 6)
connect _WIRE_56.pr, _T_813
node _T_814 = bits(_WIRE_57, 7, 7)
connect _WIRE_56.px, _T_814
node _T_815 = bits(_WIRE_57, 8, 8)
connect _WIRE_56.pw, _T_815
node _T_816 = bits(_WIRE_57, 9, 9)
connect _WIRE_56.hr, _T_816
node _T_817 = bits(_WIRE_57, 10, 10)
connect _WIRE_56.hx, _T_817
node _T_818 = bits(_WIRE_57, 11, 11)
connect _WIRE_56.hw, _T_818
node _T_819 = bits(_WIRE_57, 12, 12)
connect _WIRE_56.sr, _T_819
node _T_820 = bits(_WIRE_57, 13, 13)
connect _WIRE_56.sx, _T_820
node _T_821 = bits(_WIRE_57, 14, 14)
connect _WIRE_56.sw, _T_821
node _T_822 = bits(_WIRE_57, 15, 15)
connect _WIRE_56.gf, _T_822
node _T_823 = bits(_WIRE_57, 16, 16)
connect _WIRE_56.pf, _T_823
node _T_824 = bits(_WIRE_57, 17, 17)
connect _WIRE_56.ae_stage2, _T_824
node _T_825 = bits(_WIRE_57, 18, 18)
connect _WIRE_56.ae_final, _T_825
node _T_826 = bits(_WIRE_57, 19, 19)
connect _WIRE_56.ae_ptw, _T_826
node _T_827 = bits(_WIRE_57, 20, 20)
connect _WIRE_56.g, _T_827
node _T_828 = bits(_WIRE_57, 21, 21)
connect _WIRE_56.u, _T_828
node _T_829 = bits(_WIRE_57, 41, 22)
connect _WIRE_56.ppn, _T_829
wire _WIRE_58 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_59 : UInt<42>
connect _WIRE_59, sectored_entries[0][1].data[1]
node _T_830 = bits(_WIRE_59, 0, 0)
connect _WIRE_58.fragmented_superpage, _T_830
node _T_831 = bits(_WIRE_59, 1, 1)
connect _WIRE_58.c, _T_831
node _T_832 = bits(_WIRE_59, 2, 2)
connect _WIRE_58.eff, _T_832
node _T_833 = bits(_WIRE_59, 3, 3)
connect _WIRE_58.paa, _T_833
node _T_834 = bits(_WIRE_59, 4, 4)
connect _WIRE_58.pal, _T_834
node _T_835 = bits(_WIRE_59, 5, 5)
connect _WIRE_58.ppp, _T_835
node _T_836 = bits(_WIRE_59, 6, 6)
connect _WIRE_58.pr, _T_836
node _T_837 = bits(_WIRE_59, 7, 7)
connect _WIRE_58.px, _T_837
node _T_838 = bits(_WIRE_59, 8, 8)
connect _WIRE_58.pw, _T_838
node _T_839 = bits(_WIRE_59, 9, 9)
connect _WIRE_58.hr, _T_839
node _T_840 = bits(_WIRE_59, 10, 10)
connect _WIRE_58.hx, _T_840
node _T_841 = bits(_WIRE_59, 11, 11)
connect _WIRE_58.hw, _T_841
node _T_842 = bits(_WIRE_59, 12, 12)
connect _WIRE_58.sr, _T_842
node _T_843 = bits(_WIRE_59, 13, 13)
connect _WIRE_58.sx, _T_843
node _T_844 = bits(_WIRE_59, 14, 14)
connect _WIRE_58.sw, _T_844
node _T_845 = bits(_WIRE_59, 15, 15)
connect _WIRE_58.gf, _T_845
node _T_846 = bits(_WIRE_59, 16, 16)
connect _WIRE_58.pf, _T_846
node _T_847 = bits(_WIRE_59, 17, 17)
connect _WIRE_58.ae_stage2, _T_847
node _T_848 = bits(_WIRE_59, 18, 18)
connect _WIRE_58.ae_final, _T_848
node _T_849 = bits(_WIRE_59, 19, 19)
connect _WIRE_58.ae_ptw, _T_849
node _T_850 = bits(_WIRE_59, 20, 20)
connect _WIRE_58.g, _T_850
node _T_851 = bits(_WIRE_59, 21, 21)
connect _WIRE_58.u, _T_851
node _T_852 = bits(_WIRE_59, 41, 22)
connect _WIRE_58.ppn, _T_852
wire _WIRE_60 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_61 : UInt<42>
connect _WIRE_61, sectored_entries[0][1].data[2]
node _T_853 = bits(_WIRE_61, 0, 0)
connect _WIRE_60.fragmented_superpage, _T_853
node _T_854 = bits(_WIRE_61, 1, 1)
connect _WIRE_60.c, _T_854
node _T_855 = bits(_WIRE_61, 2, 2)
connect _WIRE_60.eff, _T_855
node _T_856 = bits(_WIRE_61, 3, 3)
connect _WIRE_60.paa, _T_856
node _T_857 = bits(_WIRE_61, 4, 4)
connect _WIRE_60.pal, _T_857
node _T_858 = bits(_WIRE_61, 5, 5)
connect _WIRE_60.ppp, _T_858
node _T_859 = bits(_WIRE_61, 6, 6)
connect _WIRE_60.pr, _T_859
node _T_860 = bits(_WIRE_61, 7, 7)
connect _WIRE_60.px, _T_860
node _T_861 = bits(_WIRE_61, 8, 8)
connect _WIRE_60.pw, _T_861
node _T_862 = bits(_WIRE_61, 9, 9)
connect _WIRE_60.hr, _T_862
node _T_863 = bits(_WIRE_61, 10, 10)
connect _WIRE_60.hx, _T_863
node _T_864 = bits(_WIRE_61, 11, 11)
connect _WIRE_60.hw, _T_864
node _T_865 = bits(_WIRE_61, 12, 12)
connect _WIRE_60.sr, _T_865
node _T_866 = bits(_WIRE_61, 13, 13)
connect _WIRE_60.sx, _T_866
node _T_867 = bits(_WIRE_61, 14, 14)
connect _WIRE_60.sw, _T_867
node _T_868 = bits(_WIRE_61, 15, 15)
connect _WIRE_60.gf, _T_868
node _T_869 = bits(_WIRE_61, 16, 16)
connect _WIRE_60.pf, _T_869
node _T_870 = bits(_WIRE_61, 17, 17)
connect _WIRE_60.ae_stage2, _T_870
node _T_871 = bits(_WIRE_61, 18, 18)
connect _WIRE_60.ae_final, _T_871
node _T_872 = bits(_WIRE_61, 19, 19)
connect _WIRE_60.ae_ptw, _T_872
node _T_873 = bits(_WIRE_61, 20, 20)
connect _WIRE_60.g, _T_873
node _T_874 = bits(_WIRE_61, 21, 21)
connect _WIRE_60.u, _T_874
node _T_875 = bits(_WIRE_61, 41, 22)
connect _WIRE_60.ppn, _T_875
wire _WIRE_62 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_63 : UInt<42>
connect _WIRE_63, sectored_entries[0][1].data[3]
node _T_876 = bits(_WIRE_63, 0, 0)
connect _WIRE_62.fragmented_superpage, _T_876
node _T_877 = bits(_WIRE_63, 1, 1)
connect _WIRE_62.c, _T_877
node _T_878 = bits(_WIRE_63, 2, 2)
connect _WIRE_62.eff, _T_878
node _T_879 = bits(_WIRE_63, 3, 3)
connect _WIRE_62.paa, _T_879
node _T_880 = bits(_WIRE_63, 4, 4)
connect _WIRE_62.pal, _T_880
node _T_881 = bits(_WIRE_63, 5, 5)
connect _WIRE_62.ppp, _T_881
node _T_882 = bits(_WIRE_63, 6, 6)
connect _WIRE_62.pr, _T_882
node _T_883 = bits(_WIRE_63, 7, 7)
connect _WIRE_62.px, _T_883
node _T_884 = bits(_WIRE_63, 8, 8)
connect _WIRE_62.pw, _T_884
node _T_885 = bits(_WIRE_63, 9, 9)
connect _WIRE_62.hr, _T_885
node _T_886 = bits(_WIRE_63, 10, 10)
connect _WIRE_62.hx, _T_886
node _T_887 = bits(_WIRE_63, 11, 11)
connect _WIRE_62.hw, _T_887
node _T_888 = bits(_WIRE_63, 12, 12)
connect _WIRE_62.sr, _T_888
node _T_889 = bits(_WIRE_63, 13, 13)
connect _WIRE_62.sx, _T_889
node _T_890 = bits(_WIRE_63, 14, 14)
connect _WIRE_62.sw, _T_890
node _T_891 = bits(_WIRE_63, 15, 15)
connect _WIRE_62.gf, _T_891
node _T_892 = bits(_WIRE_63, 16, 16)
connect _WIRE_62.pf, _T_892
node _T_893 = bits(_WIRE_63, 17, 17)
connect _WIRE_62.ae_stage2, _T_893
node _T_894 = bits(_WIRE_63, 18, 18)
connect _WIRE_62.ae_final, _T_894
node _T_895 = bits(_WIRE_63, 19, 19)
connect _WIRE_62.ae_ptw, _T_895
node _T_896 = bits(_WIRE_63, 20, 20)
connect _WIRE_62.g, _T_896
node _T_897 = bits(_WIRE_63, 21, 21)
connect _WIRE_62.u, _T_897
node _T_898 = bits(_WIRE_63, 41, 22)
connect _WIRE_62.ppn, _T_898
node _T_899 = eq(sectored_entries[0][1].tag_v, _T_806)
when _T_899 :
connect sectored_entries[0][1].valid[0], UInt<1>(0h0)
node _T_900 = eq(sectored_entries[0][1].tag_v, _T_806)
when _T_900 :
connect sectored_entries[0][1].valid[1], UInt<1>(0h0)
node _T_901 = eq(sectored_entries[0][1].tag_v, _T_806)
when _T_901 :
connect sectored_entries[0][1].valid[2], UInt<1>(0h0)
node _T_902 = eq(sectored_entries[0][1].tag_v, _T_806)
when _T_902 :
connect sectored_entries[0][1].valid[3], UInt<1>(0h0)
node hv_2 = and(UInt<1>(0h0), io.sfence.bits.hv)
node hg_2 = and(UInt<1>(0h0), io.sfence.bits.hg)
node _T_903 = eq(hg_2, UInt<1>(0h0))
node _T_904 = and(_T_903, io.sfence.bits.rs1)
when _T_904 :
node _T_905 = xor(sectored_entries[0][2].tag_vpn, vpn)
node _T_906 = shr(_T_905, 2)
node _T_907 = eq(_T_906, UInt<1>(0h0))
node _T_908 = eq(sectored_entries[0][2].tag_v, hv_2)
node _T_909 = and(_T_907, _T_908)
when _T_909 :
wire _WIRE_64 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_65 : UInt<42>
connect _WIRE_65, sectored_entries[0][2].data[0]
node _T_910 = bits(_WIRE_65, 0, 0)
connect _WIRE_64.fragmented_superpage, _T_910
node _T_911 = bits(_WIRE_65, 1, 1)
connect _WIRE_64.c, _T_911
node _T_912 = bits(_WIRE_65, 2, 2)
connect _WIRE_64.eff, _T_912
node _T_913 = bits(_WIRE_65, 3, 3)
connect _WIRE_64.paa, _T_913
node _T_914 = bits(_WIRE_65, 4, 4)
connect _WIRE_64.pal, _T_914
node _T_915 = bits(_WIRE_65, 5, 5)
connect _WIRE_64.ppp, _T_915
node _T_916 = bits(_WIRE_65, 6, 6)
connect _WIRE_64.pr, _T_916
node _T_917 = bits(_WIRE_65, 7, 7)
connect _WIRE_64.px, _T_917
node _T_918 = bits(_WIRE_65, 8, 8)
connect _WIRE_64.pw, _T_918
node _T_919 = bits(_WIRE_65, 9, 9)
connect _WIRE_64.hr, _T_919
node _T_920 = bits(_WIRE_65, 10, 10)
connect _WIRE_64.hx, _T_920
node _T_921 = bits(_WIRE_65, 11, 11)
connect _WIRE_64.hw, _T_921
node _T_922 = bits(_WIRE_65, 12, 12)
connect _WIRE_64.sr, _T_922
node _T_923 = bits(_WIRE_65, 13, 13)
connect _WIRE_64.sx, _T_923
node _T_924 = bits(_WIRE_65, 14, 14)
connect _WIRE_64.sw, _T_924
node _T_925 = bits(_WIRE_65, 15, 15)
connect _WIRE_64.gf, _T_925
node _T_926 = bits(_WIRE_65, 16, 16)
connect _WIRE_64.pf, _T_926
node _T_927 = bits(_WIRE_65, 17, 17)
connect _WIRE_64.ae_stage2, _T_927
node _T_928 = bits(_WIRE_65, 18, 18)
connect _WIRE_64.ae_final, _T_928
node _T_929 = bits(_WIRE_65, 19, 19)
connect _WIRE_64.ae_ptw, _T_929
node _T_930 = bits(_WIRE_65, 20, 20)
connect _WIRE_64.g, _T_930
node _T_931 = bits(_WIRE_65, 21, 21)
connect _WIRE_64.u, _T_931
node _T_932 = bits(_WIRE_65, 41, 22)
connect _WIRE_64.ppn, _T_932
wire _WIRE_66 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_67 : UInt<42>
connect _WIRE_67, sectored_entries[0][2].data[1]
node _T_933 = bits(_WIRE_67, 0, 0)
connect _WIRE_66.fragmented_superpage, _T_933
node _T_934 = bits(_WIRE_67, 1, 1)
connect _WIRE_66.c, _T_934
node _T_935 = bits(_WIRE_67, 2, 2)
connect _WIRE_66.eff, _T_935
node _T_936 = bits(_WIRE_67, 3, 3)
connect _WIRE_66.paa, _T_936
node _T_937 = bits(_WIRE_67, 4, 4)
connect _WIRE_66.pal, _T_937
node _T_938 = bits(_WIRE_67, 5, 5)
connect _WIRE_66.ppp, _T_938
node _T_939 = bits(_WIRE_67, 6, 6)
connect _WIRE_66.pr, _T_939
node _T_940 = bits(_WIRE_67, 7, 7)
connect _WIRE_66.px, _T_940
node _T_941 = bits(_WIRE_67, 8, 8)
connect _WIRE_66.pw, _T_941
node _T_942 = bits(_WIRE_67, 9, 9)
connect _WIRE_66.hr, _T_942
node _T_943 = bits(_WIRE_67, 10, 10)
connect _WIRE_66.hx, _T_943
node _T_944 = bits(_WIRE_67, 11, 11)
connect _WIRE_66.hw, _T_944
node _T_945 = bits(_WIRE_67, 12, 12)
connect _WIRE_66.sr, _T_945
node _T_946 = bits(_WIRE_67, 13, 13)
connect _WIRE_66.sx, _T_946
node _T_947 = bits(_WIRE_67, 14, 14)
connect _WIRE_66.sw, _T_947
node _T_948 = bits(_WIRE_67, 15, 15)
connect _WIRE_66.gf, _T_948
node _T_949 = bits(_WIRE_67, 16, 16)
connect _WIRE_66.pf, _T_949
node _T_950 = bits(_WIRE_67, 17, 17)
connect _WIRE_66.ae_stage2, _T_950
node _T_951 = bits(_WIRE_67, 18, 18)
connect _WIRE_66.ae_final, _T_951
node _T_952 = bits(_WIRE_67, 19, 19)
connect _WIRE_66.ae_ptw, _T_952
node _T_953 = bits(_WIRE_67, 20, 20)
connect _WIRE_66.g, _T_953
node _T_954 = bits(_WIRE_67, 21, 21)
connect _WIRE_66.u, _T_954
node _T_955 = bits(_WIRE_67, 41, 22)
connect _WIRE_66.ppn, _T_955
wire _WIRE_68 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_69 : UInt<42>
connect _WIRE_69, sectored_entries[0][2].data[2]
node _T_956 = bits(_WIRE_69, 0, 0)
connect _WIRE_68.fragmented_superpage, _T_956
node _T_957 = bits(_WIRE_69, 1, 1)
connect _WIRE_68.c, _T_957
node _T_958 = bits(_WIRE_69, 2, 2)
connect _WIRE_68.eff, _T_958
node _T_959 = bits(_WIRE_69, 3, 3)
connect _WIRE_68.paa, _T_959
node _T_960 = bits(_WIRE_69, 4, 4)
connect _WIRE_68.pal, _T_960
node _T_961 = bits(_WIRE_69, 5, 5)
connect _WIRE_68.ppp, _T_961
node _T_962 = bits(_WIRE_69, 6, 6)
connect _WIRE_68.pr, _T_962
node _T_963 = bits(_WIRE_69, 7, 7)
connect _WIRE_68.px, _T_963
node _T_964 = bits(_WIRE_69, 8, 8)
connect _WIRE_68.pw, _T_964
node _T_965 = bits(_WIRE_69, 9, 9)
connect _WIRE_68.hr, _T_965
node _T_966 = bits(_WIRE_69, 10, 10)
connect _WIRE_68.hx, _T_966
node _T_967 = bits(_WIRE_69, 11, 11)
connect _WIRE_68.hw, _T_967
node _T_968 = bits(_WIRE_69, 12, 12)
connect _WIRE_68.sr, _T_968
node _T_969 = bits(_WIRE_69, 13, 13)
connect _WIRE_68.sx, _T_969
node _T_970 = bits(_WIRE_69, 14, 14)
connect _WIRE_68.sw, _T_970
node _T_971 = bits(_WIRE_69, 15, 15)
connect _WIRE_68.gf, _T_971
node _T_972 = bits(_WIRE_69, 16, 16)
connect _WIRE_68.pf, _T_972
node _T_973 = bits(_WIRE_69, 17, 17)
connect _WIRE_68.ae_stage2, _T_973
node _T_974 = bits(_WIRE_69, 18, 18)
connect _WIRE_68.ae_final, _T_974
node _T_975 = bits(_WIRE_69, 19, 19)
connect _WIRE_68.ae_ptw, _T_975
node _T_976 = bits(_WIRE_69, 20, 20)
connect _WIRE_68.g, _T_976
node _T_977 = bits(_WIRE_69, 21, 21)
connect _WIRE_68.u, _T_977
node _T_978 = bits(_WIRE_69, 41, 22)
connect _WIRE_68.ppn, _T_978
wire _WIRE_70 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_71 : UInt<42>
connect _WIRE_71, sectored_entries[0][2].data[3]
node _T_979 = bits(_WIRE_71, 0, 0)
connect _WIRE_70.fragmented_superpage, _T_979
node _T_980 = bits(_WIRE_71, 1, 1)
connect _WIRE_70.c, _T_980
node _T_981 = bits(_WIRE_71, 2, 2)
connect _WIRE_70.eff, _T_981
node _T_982 = bits(_WIRE_71, 3, 3)
connect _WIRE_70.paa, _T_982
node _T_983 = bits(_WIRE_71, 4, 4)
connect _WIRE_70.pal, _T_983
node _T_984 = bits(_WIRE_71, 5, 5)
connect _WIRE_70.ppp, _T_984
node _T_985 = bits(_WIRE_71, 6, 6)
connect _WIRE_70.pr, _T_985
node _T_986 = bits(_WIRE_71, 7, 7)
connect _WIRE_70.px, _T_986
node _T_987 = bits(_WIRE_71, 8, 8)
connect _WIRE_70.pw, _T_987
node _T_988 = bits(_WIRE_71, 9, 9)
connect _WIRE_70.hr, _T_988
node _T_989 = bits(_WIRE_71, 10, 10)
connect _WIRE_70.hx, _T_989
node _T_990 = bits(_WIRE_71, 11, 11)
connect _WIRE_70.hw, _T_990
node _T_991 = bits(_WIRE_71, 12, 12)
connect _WIRE_70.sr, _T_991
node _T_992 = bits(_WIRE_71, 13, 13)
connect _WIRE_70.sx, _T_992
node _T_993 = bits(_WIRE_71, 14, 14)
connect _WIRE_70.sw, _T_993
node _T_994 = bits(_WIRE_71, 15, 15)
connect _WIRE_70.gf, _T_994
node _T_995 = bits(_WIRE_71, 16, 16)
connect _WIRE_70.pf, _T_995
node _T_996 = bits(_WIRE_71, 17, 17)
connect _WIRE_70.ae_stage2, _T_996
node _T_997 = bits(_WIRE_71, 18, 18)
connect _WIRE_70.ae_final, _T_997
node _T_998 = bits(_WIRE_71, 19, 19)
connect _WIRE_70.ae_ptw, _T_998
node _T_999 = bits(_WIRE_71, 20, 20)
connect _WIRE_70.g, _T_999
node _T_1000 = bits(_WIRE_71, 21, 21)
connect _WIRE_70.u, _T_1000
node _T_1001 = bits(_WIRE_71, 41, 22)
connect _WIRE_70.ppn, _T_1001
node _T_1002 = eq(sectored_entries[0][2].tag_v, hv_2)
node _T_1003 = bits(vpn, 1, 0)
node _T_1004 = eq(UInt<1>(0h0), _T_1003)
node _T_1005 = and(_T_1002, _T_1004)
when _T_1005 :
connect sectored_entries[0][2].valid[0], UInt<1>(0h0)
node _T_1006 = eq(sectored_entries[0][2].tag_v, hv_2)
node _T_1007 = bits(vpn, 1, 0)
node _T_1008 = eq(UInt<1>(0h1), _T_1007)
node _T_1009 = and(_T_1006, _T_1008)
when _T_1009 :
connect sectored_entries[0][2].valid[1], UInt<1>(0h0)
node _T_1010 = eq(sectored_entries[0][2].tag_v, hv_2)
node _T_1011 = bits(vpn, 1, 0)
node _T_1012 = eq(UInt<2>(0h2), _T_1011)
node _T_1013 = and(_T_1010, _T_1012)
when _T_1013 :
connect sectored_entries[0][2].valid[2], UInt<1>(0h0)
node _T_1014 = eq(sectored_entries[0][2].tag_v, hv_2)
node _T_1015 = bits(vpn, 1, 0)
node _T_1016 = eq(UInt<2>(0h3), _T_1015)
node _T_1017 = and(_T_1014, _T_1016)
when _T_1017 :
connect sectored_entries[0][2].valid[3], UInt<1>(0h0)
node _T_1018 = xor(sectored_entries[0][2].tag_vpn, vpn)
node _T_1019 = shr(_T_1018, 18)
node _T_1020 = eq(_T_1019, UInt<1>(0h0))
when _T_1020 :
wire _WIRE_72 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_73 : UInt<42>
connect _WIRE_73, sectored_entries[0][2].data[0]
node _T_1021 = bits(_WIRE_73, 0, 0)
connect _WIRE_72.fragmented_superpage, _T_1021
node _T_1022 = bits(_WIRE_73, 1, 1)
connect _WIRE_72.c, _T_1022
node _T_1023 = bits(_WIRE_73, 2, 2)
connect _WIRE_72.eff, _T_1023
node _T_1024 = bits(_WIRE_73, 3, 3)
connect _WIRE_72.paa, _T_1024
node _T_1025 = bits(_WIRE_73, 4, 4)
connect _WIRE_72.pal, _T_1025
node _T_1026 = bits(_WIRE_73, 5, 5)
connect _WIRE_72.ppp, _T_1026
node _T_1027 = bits(_WIRE_73, 6, 6)
connect _WIRE_72.pr, _T_1027
node _T_1028 = bits(_WIRE_73, 7, 7)
connect _WIRE_72.px, _T_1028
node _T_1029 = bits(_WIRE_73, 8, 8)
connect _WIRE_72.pw, _T_1029
node _T_1030 = bits(_WIRE_73, 9, 9)
connect _WIRE_72.hr, _T_1030
node _T_1031 = bits(_WIRE_73, 10, 10)
connect _WIRE_72.hx, _T_1031
node _T_1032 = bits(_WIRE_73, 11, 11)
connect _WIRE_72.hw, _T_1032
node _T_1033 = bits(_WIRE_73, 12, 12)
connect _WIRE_72.sr, _T_1033
node _T_1034 = bits(_WIRE_73, 13, 13)
connect _WIRE_72.sx, _T_1034
node _T_1035 = bits(_WIRE_73, 14, 14)
connect _WIRE_72.sw, _T_1035
node _T_1036 = bits(_WIRE_73, 15, 15)
connect _WIRE_72.gf, _T_1036
node _T_1037 = bits(_WIRE_73, 16, 16)
connect _WIRE_72.pf, _T_1037
node _T_1038 = bits(_WIRE_73, 17, 17)
connect _WIRE_72.ae_stage2, _T_1038
node _T_1039 = bits(_WIRE_73, 18, 18)
connect _WIRE_72.ae_final, _T_1039
node _T_1040 = bits(_WIRE_73, 19, 19)
connect _WIRE_72.ae_ptw, _T_1040
node _T_1041 = bits(_WIRE_73, 20, 20)
connect _WIRE_72.g, _T_1041
node _T_1042 = bits(_WIRE_73, 21, 21)
connect _WIRE_72.u, _T_1042
node _T_1043 = bits(_WIRE_73, 41, 22)
connect _WIRE_72.ppn, _T_1043
wire _WIRE_74 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_75 : UInt<42>
connect _WIRE_75, sectored_entries[0][2].data[1]
node _T_1044 = bits(_WIRE_75, 0, 0)
connect _WIRE_74.fragmented_superpage, _T_1044
node _T_1045 = bits(_WIRE_75, 1, 1)
connect _WIRE_74.c, _T_1045
node _T_1046 = bits(_WIRE_75, 2, 2)
connect _WIRE_74.eff, _T_1046
node _T_1047 = bits(_WIRE_75, 3, 3)
connect _WIRE_74.paa, _T_1047
node _T_1048 = bits(_WIRE_75, 4, 4)
connect _WIRE_74.pal, _T_1048
node _T_1049 = bits(_WIRE_75, 5, 5)
connect _WIRE_74.ppp, _T_1049
node _T_1050 = bits(_WIRE_75, 6, 6)
connect _WIRE_74.pr, _T_1050
node _T_1051 = bits(_WIRE_75, 7, 7)
connect _WIRE_74.px, _T_1051
node _T_1052 = bits(_WIRE_75, 8, 8)
connect _WIRE_74.pw, _T_1052
node _T_1053 = bits(_WIRE_75, 9, 9)
connect _WIRE_74.hr, _T_1053
node _T_1054 = bits(_WIRE_75, 10, 10)
connect _WIRE_74.hx, _T_1054
node _T_1055 = bits(_WIRE_75, 11, 11)
connect _WIRE_74.hw, _T_1055
node _T_1056 = bits(_WIRE_75, 12, 12)
connect _WIRE_74.sr, _T_1056
node _T_1057 = bits(_WIRE_75, 13, 13)
connect _WIRE_74.sx, _T_1057
node _T_1058 = bits(_WIRE_75, 14, 14)
connect _WIRE_74.sw, _T_1058
node _T_1059 = bits(_WIRE_75, 15, 15)
connect _WIRE_74.gf, _T_1059
node _T_1060 = bits(_WIRE_75, 16, 16)
connect _WIRE_74.pf, _T_1060
node _T_1061 = bits(_WIRE_75, 17, 17)
connect _WIRE_74.ae_stage2, _T_1061
node _T_1062 = bits(_WIRE_75, 18, 18)
connect _WIRE_74.ae_final, _T_1062
node _T_1063 = bits(_WIRE_75, 19, 19)
connect _WIRE_74.ae_ptw, _T_1063
node _T_1064 = bits(_WIRE_75, 20, 20)
connect _WIRE_74.g, _T_1064
node _T_1065 = bits(_WIRE_75, 21, 21)
connect _WIRE_74.u, _T_1065
node _T_1066 = bits(_WIRE_75, 41, 22)
connect _WIRE_74.ppn, _T_1066
wire _WIRE_76 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_77 : UInt<42>
connect _WIRE_77, sectored_entries[0][2].data[2]
node _T_1067 = bits(_WIRE_77, 0, 0)
connect _WIRE_76.fragmented_superpage, _T_1067
node _T_1068 = bits(_WIRE_77, 1, 1)
connect _WIRE_76.c, _T_1068
node _T_1069 = bits(_WIRE_77, 2, 2)
connect _WIRE_76.eff, _T_1069
node _T_1070 = bits(_WIRE_77, 3, 3)
connect _WIRE_76.paa, _T_1070
node _T_1071 = bits(_WIRE_77, 4, 4)
connect _WIRE_76.pal, _T_1071
node _T_1072 = bits(_WIRE_77, 5, 5)
connect _WIRE_76.ppp, _T_1072
node _T_1073 = bits(_WIRE_77, 6, 6)
connect _WIRE_76.pr, _T_1073
node _T_1074 = bits(_WIRE_77, 7, 7)
connect _WIRE_76.px, _T_1074
node _T_1075 = bits(_WIRE_77, 8, 8)
connect _WIRE_76.pw, _T_1075
node _T_1076 = bits(_WIRE_77, 9, 9)
connect _WIRE_76.hr, _T_1076
node _T_1077 = bits(_WIRE_77, 10, 10)
connect _WIRE_76.hx, _T_1077
node _T_1078 = bits(_WIRE_77, 11, 11)
connect _WIRE_76.hw, _T_1078
node _T_1079 = bits(_WIRE_77, 12, 12)
connect _WIRE_76.sr, _T_1079
node _T_1080 = bits(_WIRE_77, 13, 13)
connect _WIRE_76.sx, _T_1080
node _T_1081 = bits(_WIRE_77, 14, 14)
connect _WIRE_76.sw, _T_1081
node _T_1082 = bits(_WIRE_77, 15, 15)
connect _WIRE_76.gf, _T_1082
node _T_1083 = bits(_WIRE_77, 16, 16)
connect _WIRE_76.pf, _T_1083
node _T_1084 = bits(_WIRE_77, 17, 17)
connect _WIRE_76.ae_stage2, _T_1084
node _T_1085 = bits(_WIRE_77, 18, 18)
connect _WIRE_76.ae_final, _T_1085
node _T_1086 = bits(_WIRE_77, 19, 19)
connect _WIRE_76.ae_ptw, _T_1086
node _T_1087 = bits(_WIRE_77, 20, 20)
connect _WIRE_76.g, _T_1087
node _T_1088 = bits(_WIRE_77, 21, 21)
connect _WIRE_76.u, _T_1088
node _T_1089 = bits(_WIRE_77, 41, 22)
connect _WIRE_76.ppn, _T_1089
wire _WIRE_78 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_79 : UInt<42>
connect _WIRE_79, sectored_entries[0][2].data[3]
node _T_1090 = bits(_WIRE_79, 0, 0)
connect _WIRE_78.fragmented_superpage, _T_1090
node _T_1091 = bits(_WIRE_79, 1, 1)
connect _WIRE_78.c, _T_1091
node _T_1092 = bits(_WIRE_79, 2, 2)
connect _WIRE_78.eff, _T_1092
node _T_1093 = bits(_WIRE_79, 3, 3)
connect _WIRE_78.paa, _T_1093
node _T_1094 = bits(_WIRE_79, 4, 4)
connect _WIRE_78.pal, _T_1094
node _T_1095 = bits(_WIRE_79, 5, 5)
connect _WIRE_78.ppp, _T_1095
node _T_1096 = bits(_WIRE_79, 6, 6)
connect _WIRE_78.pr, _T_1096
node _T_1097 = bits(_WIRE_79, 7, 7)
connect _WIRE_78.px, _T_1097
node _T_1098 = bits(_WIRE_79, 8, 8)
connect _WIRE_78.pw, _T_1098
node _T_1099 = bits(_WIRE_79, 9, 9)
connect _WIRE_78.hr, _T_1099
node _T_1100 = bits(_WIRE_79, 10, 10)
connect _WIRE_78.hx, _T_1100
node _T_1101 = bits(_WIRE_79, 11, 11)
connect _WIRE_78.hw, _T_1101
node _T_1102 = bits(_WIRE_79, 12, 12)
connect _WIRE_78.sr, _T_1102
node _T_1103 = bits(_WIRE_79, 13, 13)
connect _WIRE_78.sx, _T_1103
node _T_1104 = bits(_WIRE_79, 14, 14)
connect _WIRE_78.sw, _T_1104
node _T_1105 = bits(_WIRE_79, 15, 15)
connect _WIRE_78.gf, _T_1105
node _T_1106 = bits(_WIRE_79, 16, 16)
connect _WIRE_78.pf, _T_1106
node _T_1107 = bits(_WIRE_79, 17, 17)
connect _WIRE_78.ae_stage2, _T_1107
node _T_1108 = bits(_WIRE_79, 18, 18)
connect _WIRE_78.ae_final, _T_1108
node _T_1109 = bits(_WIRE_79, 19, 19)
connect _WIRE_78.ae_ptw, _T_1109
node _T_1110 = bits(_WIRE_79, 20, 20)
connect _WIRE_78.g, _T_1110
node _T_1111 = bits(_WIRE_79, 21, 21)
connect _WIRE_78.u, _T_1111
node _T_1112 = bits(_WIRE_79, 41, 22)
connect _WIRE_78.ppn, _T_1112
node _T_1113 = eq(sectored_entries[0][2].tag_v, hv_2)
node _T_1114 = and(_T_1113, _WIRE_72.fragmented_superpage)
when _T_1114 :
connect sectored_entries[0][2].valid[0], UInt<1>(0h0)
node _T_1115 = eq(sectored_entries[0][2].tag_v, hv_2)
node _T_1116 = and(_T_1115, _WIRE_74.fragmented_superpage)
when _T_1116 :
connect sectored_entries[0][2].valid[1], UInt<1>(0h0)
node _T_1117 = eq(sectored_entries[0][2].tag_v, hv_2)
node _T_1118 = and(_T_1117, _WIRE_76.fragmented_superpage)
when _T_1118 :
connect sectored_entries[0][2].valid[2], UInt<1>(0h0)
node _T_1119 = eq(sectored_entries[0][2].tag_v, hv_2)
node _T_1120 = and(_T_1119, _WIRE_78.fragmented_superpage)
when _T_1120 :
connect sectored_entries[0][2].valid[3], UInt<1>(0h0)
else :
node _T_1121 = eq(hg_2, UInt<1>(0h0))
node _T_1122 = and(_T_1121, io.sfence.bits.rs2)
when _T_1122 :
wire _WIRE_80 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_81 : UInt<42>
connect _WIRE_81, sectored_entries[0][2].data[0]
node _T_1123 = bits(_WIRE_81, 0, 0)
connect _WIRE_80.fragmented_superpage, _T_1123
node _T_1124 = bits(_WIRE_81, 1, 1)
connect _WIRE_80.c, _T_1124
node _T_1125 = bits(_WIRE_81, 2, 2)
connect _WIRE_80.eff, _T_1125
node _T_1126 = bits(_WIRE_81, 3, 3)
connect _WIRE_80.paa, _T_1126
node _T_1127 = bits(_WIRE_81, 4, 4)
connect _WIRE_80.pal, _T_1127
node _T_1128 = bits(_WIRE_81, 5, 5)
connect _WIRE_80.ppp, _T_1128
node _T_1129 = bits(_WIRE_81, 6, 6)
connect _WIRE_80.pr, _T_1129
node _T_1130 = bits(_WIRE_81, 7, 7)
connect _WIRE_80.px, _T_1130
node _T_1131 = bits(_WIRE_81, 8, 8)
connect _WIRE_80.pw, _T_1131
node _T_1132 = bits(_WIRE_81, 9, 9)
connect _WIRE_80.hr, _T_1132
node _T_1133 = bits(_WIRE_81, 10, 10)
connect _WIRE_80.hx, _T_1133
node _T_1134 = bits(_WIRE_81, 11, 11)
connect _WIRE_80.hw, _T_1134
node _T_1135 = bits(_WIRE_81, 12, 12)
connect _WIRE_80.sr, _T_1135
node _T_1136 = bits(_WIRE_81, 13, 13)
connect _WIRE_80.sx, _T_1136
node _T_1137 = bits(_WIRE_81, 14, 14)
connect _WIRE_80.sw, _T_1137
node _T_1138 = bits(_WIRE_81, 15, 15)
connect _WIRE_80.gf, _T_1138
node _T_1139 = bits(_WIRE_81, 16, 16)
connect _WIRE_80.pf, _T_1139
node _T_1140 = bits(_WIRE_81, 17, 17)
connect _WIRE_80.ae_stage2, _T_1140
node _T_1141 = bits(_WIRE_81, 18, 18)
connect _WIRE_80.ae_final, _T_1141
node _T_1142 = bits(_WIRE_81, 19, 19)
connect _WIRE_80.ae_ptw, _T_1142
node _T_1143 = bits(_WIRE_81, 20, 20)
connect _WIRE_80.g, _T_1143
node _T_1144 = bits(_WIRE_81, 21, 21)
connect _WIRE_80.u, _T_1144
node _T_1145 = bits(_WIRE_81, 41, 22)
connect _WIRE_80.ppn, _T_1145
wire _WIRE_82 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_83 : UInt<42>
connect _WIRE_83, sectored_entries[0][2].data[1]
node _T_1146 = bits(_WIRE_83, 0, 0)
connect _WIRE_82.fragmented_superpage, _T_1146
node _T_1147 = bits(_WIRE_83, 1, 1)
connect _WIRE_82.c, _T_1147
node _T_1148 = bits(_WIRE_83, 2, 2)
connect _WIRE_82.eff, _T_1148
node _T_1149 = bits(_WIRE_83, 3, 3)
connect _WIRE_82.paa, _T_1149
node _T_1150 = bits(_WIRE_83, 4, 4)
connect _WIRE_82.pal, _T_1150
node _T_1151 = bits(_WIRE_83, 5, 5)
connect _WIRE_82.ppp, _T_1151
node _T_1152 = bits(_WIRE_83, 6, 6)
connect _WIRE_82.pr, _T_1152
node _T_1153 = bits(_WIRE_83, 7, 7)
connect _WIRE_82.px, _T_1153
node _T_1154 = bits(_WIRE_83, 8, 8)
connect _WIRE_82.pw, _T_1154
node _T_1155 = bits(_WIRE_83, 9, 9)
connect _WIRE_82.hr, _T_1155
node _T_1156 = bits(_WIRE_83, 10, 10)
connect _WIRE_82.hx, _T_1156
node _T_1157 = bits(_WIRE_83, 11, 11)
connect _WIRE_82.hw, _T_1157
node _T_1158 = bits(_WIRE_83, 12, 12)
connect _WIRE_82.sr, _T_1158
node _T_1159 = bits(_WIRE_83, 13, 13)
connect _WIRE_82.sx, _T_1159
node _T_1160 = bits(_WIRE_83, 14, 14)
connect _WIRE_82.sw, _T_1160
node _T_1161 = bits(_WIRE_83, 15, 15)
connect _WIRE_82.gf, _T_1161
node _T_1162 = bits(_WIRE_83, 16, 16)
connect _WIRE_82.pf, _T_1162
node _T_1163 = bits(_WIRE_83, 17, 17)
connect _WIRE_82.ae_stage2, _T_1163
node _T_1164 = bits(_WIRE_83, 18, 18)
connect _WIRE_82.ae_final, _T_1164
node _T_1165 = bits(_WIRE_83, 19, 19)
connect _WIRE_82.ae_ptw, _T_1165
node _T_1166 = bits(_WIRE_83, 20, 20)
connect _WIRE_82.g, _T_1166
node _T_1167 = bits(_WIRE_83, 21, 21)
connect _WIRE_82.u, _T_1167
node _T_1168 = bits(_WIRE_83, 41, 22)
connect _WIRE_82.ppn, _T_1168
wire _WIRE_84 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_85 : UInt<42>
connect _WIRE_85, sectored_entries[0][2].data[2]
node _T_1169 = bits(_WIRE_85, 0, 0)
connect _WIRE_84.fragmented_superpage, _T_1169
node _T_1170 = bits(_WIRE_85, 1, 1)
connect _WIRE_84.c, _T_1170
node _T_1171 = bits(_WIRE_85, 2, 2)
connect _WIRE_84.eff, _T_1171
node _T_1172 = bits(_WIRE_85, 3, 3)
connect _WIRE_84.paa, _T_1172
node _T_1173 = bits(_WIRE_85, 4, 4)
connect _WIRE_84.pal, _T_1173
node _T_1174 = bits(_WIRE_85, 5, 5)
connect _WIRE_84.ppp, _T_1174
node _T_1175 = bits(_WIRE_85, 6, 6)
connect _WIRE_84.pr, _T_1175
node _T_1176 = bits(_WIRE_85, 7, 7)
connect _WIRE_84.px, _T_1176
node _T_1177 = bits(_WIRE_85, 8, 8)
connect _WIRE_84.pw, _T_1177
node _T_1178 = bits(_WIRE_85, 9, 9)
connect _WIRE_84.hr, _T_1178
node _T_1179 = bits(_WIRE_85, 10, 10)
connect _WIRE_84.hx, _T_1179
node _T_1180 = bits(_WIRE_85, 11, 11)
connect _WIRE_84.hw, _T_1180
node _T_1181 = bits(_WIRE_85, 12, 12)
connect _WIRE_84.sr, _T_1181
node _T_1182 = bits(_WIRE_85, 13, 13)
connect _WIRE_84.sx, _T_1182
node _T_1183 = bits(_WIRE_85, 14, 14)
connect _WIRE_84.sw, _T_1183
node _T_1184 = bits(_WIRE_85, 15, 15)
connect _WIRE_84.gf, _T_1184
node _T_1185 = bits(_WIRE_85, 16, 16)
connect _WIRE_84.pf, _T_1185
node _T_1186 = bits(_WIRE_85, 17, 17)
connect _WIRE_84.ae_stage2, _T_1186
node _T_1187 = bits(_WIRE_85, 18, 18)
connect _WIRE_84.ae_final, _T_1187
node _T_1188 = bits(_WIRE_85, 19, 19)
connect _WIRE_84.ae_ptw, _T_1188
node _T_1189 = bits(_WIRE_85, 20, 20)
connect _WIRE_84.g, _T_1189
node _T_1190 = bits(_WIRE_85, 21, 21)
connect _WIRE_84.u, _T_1190
node _T_1191 = bits(_WIRE_85, 41, 22)
connect _WIRE_84.ppn, _T_1191
wire _WIRE_86 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_87 : UInt<42>
connect _WIRE_87, sectored_entries[0][2].data[3]
node _T_1192 = bits(_WIRE_87, 0, 0)
connect _WIRE_86.fragmented_superpage, _T_1192
node _T_1193 = bits(_WIRE_87, 1, 1)
connect _WIRE_86.c, _T_1193
node _T_1194 = bits(_WIRE_87, 2, 2)
connect _WIRE_86.eff, _T_1194
node _T_1195 = bits(_WIRE_87, 3, 3)
connect _WIRE_86.paa, _T_1195
node _T_1196 = bits(_WIRE_87, 4, 4)
connect _WIRE_86.pal, _T_1196
node _T_1197 = bits(_WIRE_87, 5, 5)
connect _WIRE_86.ppp, _T_1197
node _T_1198 = bits(_WIRE_87, 6, 6)
connect _WIRE_86.pr, _T_1198
node _T_1199 = bits(_WIRE_87, 7, 7)
connect _WIRE_86.px, _T_1199
node _T_1200 = bits(_WIRE_87, 8, 8)
connect _WIRE_86.pw, _T_1200
node _T_1201 = bits(_WIRE_87, 9, 9)
connect _WIRE_86.hr, _T_1201
node _T_1202 = bits(_WIRE_87, 10, 10)
connect _WIRE_86.hx, _T_1202
node _T_1203 = bits(_WIRE_87, 11, 11)
connect _WIRE_86.hw, _T_1203
node _T_1204 = bits(_WIRE_87, 12, 12)
connect _WIRE_86.sr, _T_1204
node _T_1205 = bits(_WIRE_87, 13, 13)
connect _WIRE_86.sx, _T_1205
node _T_1206 = bits(_WIRE_87, 14, 14)
connect _WIRE_86.sw, _T_1206
node _T_1207 = bits(_WIRE_87, 15, 15)
connect _WIRE_86.gf, _T_1207
node _T_1208 = bits(_WIRE_87, 16, 16)
connect _WIRE_86.pf, _T_1208
node _T_1209 = bits(_WIRE_87, 17, 17)
connect _WIRE_86.ae_stage2, _T_1209
node _T_1210 = bits(_WIRE_87, 18, 18)
connect _WIRE_86.ae_final, _T_1210
node _T_1211 = bits(_WIRE_87, 19, 19)
connect _WIRE_86.ae_ptw, _T_1211
node _T_1212 = bits(_WIRE_87, 20, 20)
connect _WIRE_86.g, _T_1212
node _T_1213 = bits(_WIRE_87, 21, 21)
connect _WIRE_86.u, _T_1213
node _T_1214 = bits(_WIRE_87, 41, 22)
connect _WIRE_86.ppn, _T_1214
node _T_1215 = eq(sectored_entries[0][2].tag_v, hv_2)
node _T_1216 = eq(_WIRE_80.g, UInt<1>(0h0))
node _T_1217 = and(_T_1215, _T_1216)
when _T_1217 :
connect sectored_entries[0][2].valid[0], UInt<1>(0h0)
node _T_1218 = eq(sectored_entries[0][2].tag_v, hv_2)
node _T_1219 = eq(_WIRE_82.g, UInt<1>(0h0))
node _T_1220 = and(_T_1218, _T_1219)
when _T_1220 :
connect sectored_entries[0][2].valid[1], UInt<1>(0h0)
node _T_1221 = eq(sectored_entries[0][2].tag_v, hv_2)
node _T_1222 = eq(_WIRE_84.g, UInt<1>(0h0))
node _T_1223 = and(_T_1221, _T_1222)
when _T_1223 :
connect sectored_entries[0][2].valid[2], UInt<1>(0h0)
node _T_1224 = eq(sectored_entries[0][2].tag_v, hv_2)
node _T_1225 = eq(_WIRE_86.g, UInt<1>(0h0))
node _T_1226 = and(_T_1224, _T_1225)
when _T_1226 :
connect sectored_entries[0][2].valid[3], UInt<1>(0h0)
else :
node _T_1227 = or(hv_2, hg_2)
wire _WIRE_88 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_89 : UInt<42>
connect _WIRE_89, sectored_entries[0][2].data[0]
node _T_1228 = bits(_WIRE_89, 0, 0)
connect _WIRE_88.fragmented_superpage, _T_1228
node _T_1229 = bits(_WIRE_89, 1, 1)
connect _WIRE_88.c, _T_1229
node _T_1230 = bits(_WIRE_89, 2, 2)
connect _WIRE_88.eff, _T_1230
node _T_1231 = bits(_WIRE_89, 3, 3)
connect _WIRE_88.paa, _T_1231
node _T_1232 = bits(_WIRE_89, 4, 4)
connect _WIRE_88.pal, _T_1232
node _T_1233 = bits(_WIRE_89, 5, 5)
connect _WIRE_88.ppp, _T_1233
node _T_1234 = bits(_WIRE_89, 6, 6)
connect _WIRE_88.pr, _T_1234
node _T_1235 = bits(_WIRE_89, 7, 7)
connect _WIRE_88.px, _T_1235
node _T_1236 = bits(_WIRE_89, 8, 8)
connect _WIRE_88.pw, _T_1236
node _T_1237 = bits(_WIRE_89, 9, 9)
connect _WIRE_88.hr, _T_1237
node _T_1238 = bits(_WIRE_89, 10, 10)
connect _WIRE_88.hx, _T_1238
node _T_1239 = bits(_WIRE_89, 11, 11)
connect _WIRE_88.hw, _T_1239
node _T_1240 = bits(_WIRE_89, 12, 12)
connect _WIRE_88.sr, _T_1240
node _T_1241 = bits(_WIRE_89, 13, 13)
connect _WIRE_88.sx, _T_1241
node _T_1242 = bits(_WIRE_89, 14, 14)
connect _WIRE_88.sw, _T_1242
node _T_1243 = bits(_WIRE_89, 15, 15)
connect _WIRE_88.gf, _T_1243
node _T_1244 = bits(_WIRE_89, 16, 16)
connect _WIRE_88.pf, _T_1244
node _T_1245 = bits(_WIRE_89, 17, 17)
connect _WIRE_88.ae_stage2, _T_1245
node _T_1246 = bits(_WIRE_89, 18, 18)
connect _WIRE_88.ae_final, _T_1246
node _T_1247 = bits(_WIRE_89, 19, 19)
connect _WIRE_88.ae_ptw, _T_1247
node _T_1248 = bits(_WIRE_89, 20, 20)
connect _WIRE_88.g, _T_1248
node _T_1249 = bits(_WIRE_89, 21, 21)
connect _WIRE_88.u, _T_1249
node _T_1250 = bits(_WIRE_89, 41, 22)
connect _WIRE_88.ppn, _T_1250
wire _WIRE_90 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_91 : UInt<42>
connect _WIRE_91, sectored_entries[0][2].data[1]
node _T_1251 = bits(_WIRE_91, 0, 0)
connect _WIRE_90.fragmented_superpage, _T_1251
node _T_1252 = bits(_WIRE_91, 1, 1)
connect _WIRE_90.c, _T_1252
node _T_1253 = bits(_WIRE_91, 2, 2)
connect _WIRE_90.eff, _T_1253
node _T_1254 = bits(_WIRE_91, 3, 3)
connect _WIRE_90.paa, _T_1254
node _T_1255 = bits(_WIRE_91, 4, 4)
connect _WIRE_90.pal, _T_1255
node _T_1256 = bits(_WIRE_91, 5, 5)
connect _WIRE_90.ppp, _T_1256
node _T_1257 = bits(_WIRE_91, 6, 6)
connect _WIRE_90.pr, _T_1257
node _T_1258 = bits(_WIRE_91, 7, 7)
connect _WIRE_90.px, _T_1258
node _T_1259 = bits(_WIRE_91, 8, 8)
connect _WIRE_90.pw, _T_1259
node _T_1260 = bits(_WIRE_91, 9, 9)
connect _WIRE_90.hr, _T_1260
node _T_1261 = bits(_WIRE_91, 10, 10)
connect _WIRE_90.hx, _T_1261
node _T_1262 = bits(_WIRE_91, 11, 11)
connect _WIRE_90.hw, _T_1262
node _T_1263 = bits(_WIRE_91, 12, 12)
connect _WIRE_90.sr, _T_1263
node _T_1264 = bits(_WIRE_91, 13, 13)
connect _WIRE_90.sx, _T_1264
node _T_1265 = bits(_WIRE_91, 14, 14)
connect _WIRE_90.sw, _T_1265
node _T_1266 = bits(_WIRE_91, 15, 15)
connect _WIRE_90.gf, _T_1266
node _T_1267 = bits(_WIRE_91, 16, 16)
connect _WIRE_90.pf, _T_1267
node _T_1268 = bits(_WIRE_91, 17, 17)
connect _WIRE_90.ae_stage2, _T_1268
node _T_1269 = bits(_WIRE_91, 18, 18)
connect _WIRE_90.ae_final, _T_1269
node _T_1270 = bits(_WIRE_91, 19, 19)
connect _WIRE_90.ae_ptw, _T_1270
node _T_1271 = bits(_WIRE_91, 20, 20)
connect _WIRE_90.g, _T_1271
node _T_1272 = bits(_WIRE_91, 21, 21)
connect _WIRE_90.u, _T_1272
node _T_1273 = bits(_WIRE_91, 41, 22)
connect _WIRE_90.ppn, _T_1273
wire _WIRE_92 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_93 : UInt<42>
connect _WIRE_93, sectored_entries[0][2].data[2]
node _T_1274 = bits(_WIRE_93, 0, 0)
connect _WIRE_92.fragmented_superpage, _T_1274
node _T_1275 = bits(_WIRE_93, 1, 1)
connect _WIRE_92.c, _T_1275
node _T_1276 = bits(_WIRE_93, 2, 2)
connect _WIRE_92.eff, _T_1276
node _T_1277 = bits(_WIRE_93, 3, 3)
connect _WIRE_92.paa, _T_1277
node _T_1278 = bits(_WIRE_93, 4, 4)
connect _WIRE_92.pal, _T_1278
node _T_1279 = bits(_WIRE_93, 5, 5)
connect _WIRE_92.ppp, _T_1279
node _T_1280 = bits(_WIRE_93, 6, 6)
connect _WIRE_92.pr, _T_1280
node _T_1281 = bits(_WIRE_93, 7, 7)
connect _WIRE_92.px, _T_1281
node _T_1282 = bits(_WIRE_93, 8, 8)
connect _WIRE_92.pw, _T_1282
node _T_1283 = bits(_WIRE_93, 9, 9)
connect _WIRE_92.hr, _T_1283
node _T_1284 = bits(_WIRE_93, 10, 10)
connect _WIRE_92.hx, _T_1284
node _T_1285 = bits(_WIRE_93, 11, 11)
connect _WIRE_92.hw, _T_1285
node _T_1286 = bits(_WIRE_93, 12, 12)
connect _WIRE_92.sr, _T_1286
node _T_1287 = bits(_WIRE_93, 13, 13)
connect _WIRE_92.sx, _T_1287
node _T_1288 = bits(_WIRE_93, 14, 14)
connect _WIRE_92.sw, _T_1288
node _T_1289 = bits(_WIRE_93, 15, 15)
connect _WIRE_92.gf, _T_1289
node _T_1290 = bits(_WIRE_93, 16, 16)
connect _WIRE_92.pf, _T_1290
node _T_1291 = bits(_WIRE_93, 17, 17)
connect _WIRE_92.ae_stage2, _T_1291
node _T_1292 = bits(_WIRE_93, 18, 18)
connect _WIRE_92.ae_final, _T_1292
node _T_1293 = bits(_WIRE_93, 19, 19)
connect _WIRE_92.ae_ptw, _T_1293
node _T_1294 = bits(_WIRE_93, 20, 20)
connect _WIRE_92.g, _T_1294
node _T_1295 = bits(_WIRE_93, 21, 21)
connect _WIRE_92.u, _T_1295
node _T_1296 = bits(_WIRE_93, 41, 22)
connect _WIRE_92.ppn, _T_1296
wire _WIRE_94 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_95 : UInt<42>
connect _WIRE_95, sectored_entries[0][2].data[3]
node _T_1297 = bits(_WIRE_95, 0, 0)
connect _WIRE_94.fragmented_superpage, _T_1297
node _T_1298 = bits(_WIRE_95, 1, 1)
connect _WIRE_94.c, _T_1298
node _T_1299 = bits(_WIRE_95, 2, 2)
connect _WIRE_94.eff, _T_1299
node _T_1300 = bits(_WIRE_95, 3, 3)
connect _WIRE_94.paa, _T_1300
node _T_1301 = bits(_WIRE_95, 4, 4)
connect _WIRE_94.pal, _T_1301
node _T_1302 = bits(_WIRE_95, 5, 5)
connect _WIRE_94.ppp, _T_1302
node _T_1303 = bits(_WIRE_95, 6, 6)
connect _WIRE_94.pr, _T_1303
node _T_1304 = bits(_WIRE_95, 7, 7)
connect _WIRE_94.px, _T_1304
node _T_1305 = bits(_WIRE_95, 8, 8)
connect _WIRE_94.pw, _T_1305
node _T_1306 = bits(_WIRE_95, 9, 9)
connect _WIRE_94.hr, _T_1306
node _T_1307 = bits(_WIRE_95, 10, 10)
connect _WIRE_94.hx, _T_1307
node _T_1308 = bits(_WIRE_95, 11, 11)
connect _WIRE_94.hw, _T_1308
node _T_1309 = bits(_WIRE_95, 12, 12)
connect _WIRE_94.sr, _T_1309
node _T_1310 = bits(_WIRE_95, 13, 13)
connect _WIRE_94.sx, _T_1310
node _T_1311 = bits(_WIRE_95, 14, 14)
connect _WIRE_94.sw, _T_1311
node _T_1312 = bits(_WIRE_95, 15, 15)
connect _WIRE_94.gf, _T_1312
node _T_1313 = bits(_WIRE_95, 16, 16)
connect _WIRE_94.pf, _T_1313
node _T_1314 = bits(_WIRE_95, 17, 17)
connect _WIRE_94.ae_stage2, _T_1314
node _T_1315 = bits(_WIRE_95, 18, 18)
connect _WIRE_94.ae_final, _T_1315
node _T_1316 = bits(_WIRE_95, 19, 19)
connect _WIRE_94.ae_ptw, _T_1316
node _T_1317 = bits(_WIRE_95, 20, 20)
connect _WIRE_94.g, _T_1317
node _T_1318 = bits(_WIRE_95, 21, 21)
connect _WIRE_94.u, _T_1318
node _T_1319 = bits(_WIRE_95, 41, 22)
connect _WIRE_94.ppn, _T_1319
node _T_1320 = eq(sectored_entries[0][2].tag_v, _T_1227)
when _T_1320 :
connect sectored_entries[0][2].valid[0], UInt<1>(0h0)
node _T_1321 = eq(sectored_entries[0][2].tag_v, _T_1227)
when _T_1321 :
connect sectored_entries[0][2].valid[1], UInt<1>(0h0)
node _T_1322 = eq(sectored_entries[0][2].tag_v, _T_1227)
when _T_1322 :
connect sectored_entries[0][2].valid[2], UInt<1>(0h0)
node _T_1323 = eq(sectored_entries[0][2].tag_v, _T_1227)
when _T_1323 :
connect sectored_entries[0][2].valid[3], UInt<1>(0h0)
node hv_3 = and(UInt<1>(0h0), io.sfence.bits.hv)
node hg_3 = and(UInt<1>(0h0), io.sfence.bits.hg)
node _T_1324 = eq(hg_3, UInt<1>(0h0))
node _T_1325 = and(_T_1324, io.sfence.bits.rs1)
when _T_1325 :
node _T_1326 = xor(sectored_entries[0][3].tag_vpn, vpn)
node _T_1327 = shr(_T_1326, 2)
node _T_1328 = eq(_T_1327, UInt<1>(0h0))
node _T_1329 = eq(sectored_entries[0][3].tag_v, hv_3)
node _T_1330 = and(_T_1328, _T_1329)
when _T_1330 :
wire _WIRE_96 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_97 : UInt<42>
connect _WIRE_97, sectored_entries[0][3].data[0]
node _T_1331 = bits(_WIRE_97, 0, 0)
connect _WIRE_96.fragmented_superpage, _T_1331
node _T_1332 = bits(_WIRE_97, 1, 1)
connect _WIRE_96.c, _T_1332
node _T_1333 = bits(_WIRE_97, 2, 2)
connect _WIRE_96.eff, _T_1333
node _T_1334 = bits(_WIRE_97, 3, 3)
connect _WIRE_96.paa, _T_1334
node _T_1335 = bits(_WIRE_97, 4, 4)
connect _WIRE_96.pal, _T_1335
node _T_1336 = bits(_WIRE_97, 5, 5)
connect _WIRE_96.ppp, _T_1336
node _T_1337 = bits(_WIRE_97, 6, 6)
connect _WIRE_96.pr, _T_1337
node _T_1338 = bits(_WIRE_97, 7, 7)
connect _WIRE_96.px, _T_1338
node _T_1339 = bits(_WIRE_97, 8, 8)
connect _WIRE_96.pw, _T_1339
node _T_1340 = bits(_WIRE_97, 9, 9)
connect _WIRE_96.hr, _T_1340
node _T_1341 = bits(_WIRE_97, 10, 10)
connect _WIRE_96.hx, _T_1341
node _T_1342 = bits(_WIRE_97, 11, 11)
connect _WIRE_96.hw, _T_1342
node _T_1343 = bits(_WIRE_97, 12, 12)
connect _WIRE_96.sr, _T_1343
node _T_1344 = bits(_WIRE_97, 13, 13)
connect _WIRE_96.sx, _T_1344
node _T_1345 = bits(_WIRE_97, 14, 14)
connect _WIRE_96.sw, _T_1345
node _T_1346 = bits(_WIRE_97, 15, 15)
connect _WIRE_96.gf, _T_1346
node _T_1347 = bits(_WIRE_97, 16, 16)
connect _WIRE_96.pf, _T_1347
node _T_1348 = bits(_WIRE_97, 17, 17)
connect _WIRE_96.ae_stage2, _T_1348
node _T_1349 = bits(_WIRE_97, 18, 18)
connect _WIRE_96.ae_final, _T_1349
node _T_1350 = bits(_WIRE_97, 19, 19)
connect _WIRE_96.ae_ptw, _T_1350
node _T_1351 = bits(_WIRE_97, 20, 20)
connect _WIRE_96.g, _T_1351
node _T_1352 = bits(_WIRE_97, 21, 21)
connect _WIRE_96.u, _T_1352
node _T_1353 = bits(_WIRE_97, 41, 22)
connect _WIRE_96.ppn, _T_1353
wire _WIRE_98 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_99 : UInt<42>
connect _WIRE_99, sectored_entries[0][3].data[1]
node _T_1354 = bits(_WIRE_99, 0, 0)
connect _WIRE_98.fragmented_superpage, _T_1354
node _T_1355 = bits(_WIRE_99, 1, 1)
connect _WIRE_98.c, _T_1355
node _T_1356 = bits(_WIRE_99, 2, 2)
connect _WIRE_98.eff, _T_1356
node _T_1357 = bits(_WIRE_99, 3, 3)
connect _WIRE_98.paa, _T_1357
node _T_1358 = bits(_WIRE_99, 4, 4)
connect _WIRE_98.pal, _T_1358
node _T_1359 = bits(_WIRE_99, 5, 5)
connect _WIRE_98.ppp, _T_1359
node _T_1360 = bits(_WIRE_99, 6, 6)
connect _WIRE_98.pr, _T_1360
node _T_1361 = bits(_WIRE_99, 7, 7)
connect _WIRE_98.px, _T_1361
node _T_1362 = bits(_WIRE_99, 8, 8)
connect _WIRE_98.pw, _T_1362
node _T_1363 = bits(_WIRE_99, 9, 9)
connect _WIRE_98.hr, _T_1363
node _T_1364 = bits(_WIRE_99, 10, 10)
connect _WIRE_98.hx, _T_1364
node _T_1365 = bits(_WIRE_99, 11, 11)
connect _WIRE_98.hw, _T_1365
node _T_1366 = bits(_WIRE_99, 12, 12)
connect _WIRE_98.sr, _T_1366
node _T_1367 = bits(_WIRE_99, 13, 13)
connect _WIRE_98.sx, _T_1367
node _T_1368 = bits(_WIRE_99, 14, 14)
connect _WIRE_98.sw, _T_1368
node _T_1369 = bits(_WIRE_99, 15, 15)
connect _WIRE_98.gf, _T_1369
node _T_1370 = bits(_WIRE_99, 16, 16)
connect _WIRE_98.pf, _T_1370
node _T_1371 = bits(_WIRE_99, 17, 17)
connect _WIRE_98.ae_stage2, _T_1371
node _T_1372 = bits(_WIRE_99, 18, 18)
connect _WIRE_98.ae_final, _T_1372
node _T_1373 = bits(_WIRE_99, 19, 19)
connect _WIRE_98.ae_ptw, _T_1373
node _T_1374 = bits(_WIRE_99, 20, 20)
connect _WIRE_98.g, _T_1374
node _T_1375 = bits(_WIRE_99, 21, 21)
connect _WIRE_98.u, _T_1375
node _T_1376 = bits(_WIRE_99, 41, 22)
connect _WIRE_98.ppn, _T_1376
wire _WIRE_100 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_101 : UInt<42>
connect _WIRE_101, sectored_entries[0][3].data[2]
node _T_1377 = bits(_WIRE_101, 0, 0)
connect _WIRE_100.fragmented_superpage, _T_1377
node _T_1378 = bits(_WIRE_101, 1, 1)
connect _WIRE_100.c, _T_1378
node _T_1379 = bits(_WIRE_101, 2, 2)
connect _WIRE_100.eff, _T_1379
node _T_1380 = bits(_WIRE_101, 3, 3)
connect _WIRE_100.paa, _T_1380
node _T_1381 = bits(_WIRE_101, 4, 4)
connect _WIRE_100.pal, _T_1381
node _T_1382 = bits(_WIRE_101, 5, 5)
connect _WIRE_100.ppp, _T_1382
node _T_1383 = bits(_WIRE_101, 6, 6)
connect _WIRE_100.pr, _T_1383
node _T_1384 = bits(_WIRE_101, 7, 7)
connect _WIRE_100.px, _T_1384
node _T_1385 = bits(_WIRE_101, 8, 8)
connect _WIRE_100.pw, _T_1385
node _T_1386 = bits(_WIRE_101, 9, 9)
connect _WIRE_100.hr, _T_1386
node _T_1387 = bits(_WIRE_101, 10, 10)
connect _WIRE_100.hx, _T_1387
node _T_1388 = bits(_WIRE_101, 11, 11)
connect _WIRE_100.hw, _T_1388
node _T_1389 = bits(_WIRE_101, 12, 12)
connect _WIRE_100.sr, _T_1389
node _T_1390 = bits(_WIRE_101, 13, 13)
connect _WIRE_100.sx, _T_1390
node _T_1391 = bits(_WIRE_101, 14, 14)
connect _WIRE_100.sw, _T_1391
node _T_1392 = bits(_WIRE_101, 15, 15)
connect _WIRE_100.gf, _T_1392
node _T_1393 = bits(_WIRE_101, 16, 16)
connect _WIRE_100.pf, _T_1393
node _T_1394 = bits(_WIRE_101, 17, 17)
connect _WIRE_100.ae_stage2, _T_1394
node _T_1395 = bits(_WIRE_101, 18, 18)
connect _WIRE_100.ae_final, _T_1395
node _T_1396 = bits(_WIRE_101, 19, 19)
connect _WIRE_100.ae_ptw, _T_1396
node _T_1397 = bits(_WIRE_101, 20, 20)
connect _WIRE_100.g, _T_1397
node _T_1398 = bits(_WIRE_101, 21, 21)
connect _WIRE_100.u, _T_1398
node _T_1399 = bits(_WIRE_101, 41, 22)
connect _WIRE_100.ppn, _T_1399
wire _WIRE_102 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_103 : UInt<42>
connect _WIRE_103, sectored_entries[0][3].data[3]
node _T_1400 = bits(_WIRE_103, 0, 0)
connect _WIRE_102.fragmented_superpage, _T_1400
node _T_1401 = bits(_WIRE_103, 1, 1)
connect _WIRE_102.c, _T_1401
node _T_1402 = bits(_WIRE_103, 2, 2)
connect _WIRE_102.eff, _T_1402
node _T_1403 = bits(_WIRE_103, 3, 3)
connect _WIRE_102.paa, _T_1403
node _T_1404 = bits(_WIRE_103, 4, 4)
connect _WIRE_102.pal, _T_1404
node _T_1405 = bits(_WIRE_103, 5, 5)
connect _WIRE_102.ppp, _T_1405
node _T_1406 = bits(_WIRE_103, 6, 6)
connect _WIRE_102.pr, _T_1406
node _T_1407 = bits(_WIRE_103, 7, 7)
connect _WIRE_102.px, _T_1407
node _T_1408 = bits(_WIRE_103, 8, 8)
connect _WIRE_102.pw, _T_1408
node _T_1409 = bits(_WIRE_103, 9, 9)
connect _WIRE_102.hr, _T_1409
node _T_1410 = bits(_WIRE_103, 10, 10)
connect _WIRE_102.hx, _T_1410
node _T_1411 = bits(_WIRE_103, 11, 11)
connect _WIRE_102.hw, _T_1411
node _T_1412 = bits(_WIRE_103, 12, 12)
connect _WIRE_102.sr, _T_1412
node _T_1413 = bits(_WIRE_103, 13, 13)
connect _WIRE_102.sx, _T_1413
node _T_1414 = bits(_WIRE_103, 14, 14)
connect _WIRE_102.sw, _T_1414
node _T_1415 = bits(_WIRE_103, 15, 15)
connect _WIRE_102.gf, _T_1415
node _T_1416 = bits(_WIRE_103, 16, 16)
connect _WIRE_102.pf, _T_1416
node _T_1417 = bits(_WIRE_103, 17, 17)
connect _WIRE_102.ae_stage2, _T_1417
node _T_1418 = bits(_WIRE_103, 18, 18)
connect _WIRE_102.ae_final, _T_1418
node _T_1419 = bits(_WIRE_103, 19, 19)
connect _WIRE_102.ae_ptw, _T_1419
node _T_1420 = bits(_WIRE_103, 20, 20)
connect _WIRE_102.g, _T_1420
node _T_1421 = bits(_WIRE_103, 21, 21)
connect _WIRE_102.u, _T_1421
node _T_1422 = bits(_WIRE_103, 41, 22)
connect _WIRE_102.ppn, _T_1422
node _T_1423 = eq(sectored_entries[0][3].tag_v, hv_3)
node _T_1424 = bits(vpn, 1, 0)
node _T_1425 = eq(UInt<1>(0h0), _T_1424)
node _T_1426 = and(_T_1423, _T_1425)
when _T_1426 :
connect sectored_entries[0][3].valid[0], UInt<1>(0h0)
node _T_1427 = eq(sectored_entries[0][3].tag_v, hv_3)
node _T_1428 = bits(vpn, 1, 0)
node _T_1429 = eq(UInt<1>(0h1), _T_1428)
node _T_1430 = and(_T_1427, _T_1429)
when _T_1430 :
connect sectored_entries[0][3].valid[1], UInt<1>(0h0)
node _T_1431 = eq(sectored_entries[0][3].tag_v, hv_3)
node _T_1432 = bits(vpn, 1, 0)
node _T_1433 = eq(UInt<2>(0h2), _T_1432)
node _T_1434 = and(_T_1431, _T_1433)
when _T_1434 :
connect sectored_entries[0][3].valid[2], UInt<1>(0h0)
node _T_1435 = eq(sectored_entries[0][3].tag_v, hv_3)
node _T_1436 = bits(vpn, 1, 0)
node _T_1437 = eq(UInt<2>(0h3), _T_1436)
node _T_1438 = and(_T_1435, _T_1437)
when _T_1438 :
connect sectored_entries[0][3].valid[3], UInt<1>(0h0)
node _T_1439 = xor(sectored_entries[0][3].tag_vpn, vpn)
node _T_1440 = shr(_T_1439, 18)
node _T_1441 = eq(_T_1440, UInt<1>(0h0))
when _T_1441 :
wire _WIRE_104 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_105 : UInt<42>
connect _WIRE_105, sectored_entries[0][3].data[0]
node _T_1442 = bits(_WIRE_105, 0, 0)
connect _WIRE_104.fragmented_superpage, _T_1442
node _T_1443 = bits(_WIRE_105, 1, 1)
connect _WIRE_104.c, _T_1443
node _T_1444 = bits(_WIRE_105, 2, 2)
connect _WIRE_104.eff, _T_1444
node _T_1445 = bits(_WIRE_105, 3, 3)
connect _WIRE_104.paa, _T_1445
node _T_1446 = bits(_WIRE_105, 4, 4)
connect _WIRE_104.pal, _T_1446
node _T_1447 = bits(_WIRE_105, 5, 5)
connect _WIRE_104.ppp, _T_1447
node _T_1448 = bits(_WIRE_105, 6, 6)
connect _WIRE_104.pr, _T_1448
node _T_1449 = bits(_WIRE_105, 7, 7)
connect _WIRE_104.px, _T_1449
node _T_1450 = bits(_WIRE_105, 8, 8)
connect _WIRE_104.pw, _T_1450
node _T_1451 = bits(_WIRE_105, 9, 9)
connect _WIRE_104.hr, _T_1451
node _T_1452 = bits(_WIRE_105, 10, 10)
connect _WIRE_104.hx, _T_1452
node _T_1453 = bits(_WIRE_105, 11, 11)
connect _WIRE_104.hw, _T_1453
node _T_1454 = bits(_WIRE_105, 12, 12)
connect _WIRE_104.sr, _T_1454
node _T_1455 = bits(_WIRE_105, 13, 13)
connect _WIRE_104.sx, _T_1455
node _T_1456 = bits(_WIRE_105, 14, 14)
connect _WIRE_104.sw, _T_1456
node _T_1457 = bits(_WIRE_105, 15, 15)
connect _WIRE_104.gf, _T_1457
node _T_1458 = bits(_WIRE_105, 16, 16)
connect _WIRE_104.pf, _T_1458
node _T_1459 = bits(_WIRE_105, 17, 17)
connect _WIRE_104.ae_stage2, _T_1459
node _T_1460 = bits(_WIRE_105, 18, 18)
connect _WIRE_104.ae_final, _T_1460
node _T_1461 = bits(_WIRE_105, 19, 19)
connect _WIRE_104.ae_ptw, _T_1461
node _T_1462 = bits(_WIRE_105, 20, 20)
connect _WIRE_104.g, _T_1462
node _T_1463 = bits(_WIRE_105, 21, 21)
connect _WIRE_104.u, _T_1463
node _T_1464 = bits(_WIRE_105, 41, 22)
connect _WIRE_104.ppn, _T_1464
wire _WIRE_106 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_107 : UInt<42>
connect _WIRE_107, sectored_entries[0][3].data[1]
node _T_1465 = bits(_WIRE_107, 0, 0)
connect _WIRE_106.fragmented_superpage, _T_1465
node _T_1466 = bits(_WIRE_107, 1, 1)
connect _WIRE_106.c, _T_1466
node _T_1467 = bits(_WIRE_107, 2, 2)
connect _WIRE_106.eff, _T_1467
node _T_1468 = bits(_WIRE_107, 3, 3)
connect _WIRE_106.paa, _T_1468
node _T_1469 = bits(_WIRE_107, 4, 4)
connect _WIRE_106.pal, _T_1469
node _T_1470 = bits(_WIRE_107, 5, 5)
connect _WIRE_106.ppp, _T_1470
node _T_1471 = bits(_WIRE_107, 6, 6)
connect _WIRE_106.pr, _T_1471
node _T_1472 = bits(_WIRE_107, 7, 7)
connect _WIRE_106.px, _T_1472
node _T_1473 = bits(_WIRE_107, 8, 8)
connect _WIRE_106.pw, _T_1473
node _T_1474 = bits(_WIRE_107, 9, 9)
connect _WIRE_106.hr, _T_1474
node _T_1475 = bits(_WIRE_107, 10, 10)
connect _WIRE_106.hx, _T_1475
node _T_1476 = bits(_WIRE_107, 11, 11)
connect _WIRE_106.hw, _T_1476
node _T_1477 = bits(_WIRE_107, 12, 12)
connect _WIRE_106.sr, _T_1477
node _T_1478 = bits(_WIRE_107, 13, 13)
connect _WIRE_106.sx, _T_1478
node _T_1479 = bits(_WIRE_107, 14, 14)
connect _WIRE_106.sw, _T_1479
node _T_1480 = bits(_WIRE_107, 15, 15)
connect _WIRE_106.gf, _T_1480
node _T_1481 = bits(_WIRE_107, 16, 16)
connect _WIRE_106.pf, _T_1481
node _T_1482 = bits(_WIRE_107, 17, 17)
connect _WIRE_106.ae_stage2, _T_1482
node _T_1483 = bits(_WIRE_107, 18, 18)
connect _WIRE_106.ae_final, _T_1483
node _T_1484 = bits(_WIRE_107, 19, 19)
connect _WIRE_106.ae_ptw, _T_1484
node _T_1485 = bits(_WIRE_107, 20, 20)
connect _WIRE_106.g, _T_1485
node _T_1486 = bits(_WIRE_107, 21, 21)
connect _WIRE_106.u, _T_1486
node _T_1487 = bits(_WIRE_107, 41, 22)
connect _WIRE_106.ppn, _T_1487
wire _WIRE_108 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_109 : UInt<42>
connect _WIRE_109, sectored_entries[0][3].data[2]
node _T_1488 = bits(_WIRE_109, 0, 0)
connect _WIRE_108.fragmented_superpage, _T_1488
node _T_1489 = bits(_WIRE_109, 1, 1)
connect _WIRE_108.c, _T_1489
node _T_1490 = bits(_WIRE_109, 2, 2)
connect _WIRE_108.eff, _T_1490
node _T_1491 = bits(_WIRE_109, 3, 3)
connect _WIRE_108.paa, _T_1491
node _T_1492 = bits(_WIRE_109, 4, 4)
connect _WIRE_108.pal, _T_1492
node _T_1493 = bits(_WIRE_109, 5, 5)
connect _WIRE_108.ppp, _T_1493
node _T_1494 = bits(_WIRE_109, 6, 6)
connect _WIRE_108.pr, _T_1494
node _T_1495 = bits(_WIRE_109, 7, 7)
connect _WIRE_108.px, _T_1495
node _T_1496 = bits(_WIRE_109, 8, 8)
connect _WIRE_108.pw, _T_1496
node _T_1497 = bits(_WIRE_109, 9, 9)
connect _WIRE_108.hr, _T_1497
node _T_1498 = bits(_WIRE_109, 10, 10)
connect _WIRE_108.hx, _T_1498
node _T_1499 = bits(_WIRE_109, 11, 11)
connect _WIRE_108.hw, _T_1499
node _T_1500 = bits(_WIRE_109, 12, 12)
connect _WIRE_108.sr, _T_1500
node _T_1501 = bits(_WIRE_109, 13, 13)
connect _WIRE_108.sx, _T_1501
node _T_1502 = bits(_WIRE_109, 14, 14)
connect _WIRE_108.sw, _T_1502
node _T_1503 = bits(_WIRE_109, 15, 15)
connect _WIRE_108.gf, _T_1503
node _T_1504 = bits(_WIRE_109, 16, 16)
connect _WIRE_108.pf, _T_1504
node _T_1505 = bits(_WIRE_109, 17, 17)
connect _WIRE_108.ae_stage2, _T_1505
node _T_1506 = bits(_WIRE_109, 18, 18)
connect _WIRE_108.ae_final, _T_1506
node _T_1507 = bits(_WIRE_109, 19, 19)
connect _WIRE_108.ae_ptw, _T_1507
node _T_1508 = bits(_WIRE_109, 20, 20)
connect _WIRE_108.g, _T_1508
node _T_1509 = bits(_WIRE_109, 21, 21)
connect _WIRE_108.u, _T_1509
node _T_1510 = bits(_WIRE_109, 41, 22)
connect _WIRE_108.ppn, _T_1510
wire _WIRE_110 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_111 : UInt<42>
connect _WIRE_111, sectored_entries[0][3].data[3]
node _T_1511 = bits(_WIRE_111, 0, 0)
connect _WIRE_110.fragmented_superpage, _T_1511
node _T_1512 = bits(_WIRE_111, 1, 1)
connect _WIRE_110.c, _T_1512
node _T_1513 = bits(_WIRE_111, 2, 2)
connect _WIRE_110.eff, _T_1513
node _T_1514 = bits(_WIRE_111, 3, 3)
connect _WIRE_110.paa, _T_1514
node _T_1515 = bits(_WIRE_111, 4, 4)
connect _WIRE_110.pal, _T_1515
node _T_1516 = bits(_WIRE_111, 5, 5)
connect _WIRE_110.ppp, _T_1516
node _T_1517 = bits(_WIRE_111, 6, 6)
connect _WIRE_110.pr, _T_1517
node _T_1518 = bits(_WIRE_111, 7, 7)
connect _WIRE_110.px, _T_1518
node _T_1519 = bits(_WIRE_111, 8, 8)
connect _WIRE_110.pw, _T_1519
node _T_1520 = bits(_WIRE_111, 9, 9)
connect _WIRE_110.hr, _T_1520
node _T_1521 = bits(_WIRE_111, 10, 10)
connect _WIRE_110.hx, _T_1521
node _T_1522 = bits(_WIRE_111, 11, 11)
connect _WIRE_110.hw, _T_1522
node _T_1523 = bits(_WIRE_111, 12, 12)
connect _WIRE_110.sr, _T_1523
node _T_1524 = bits(_WIRE_111, 13, 13)
connect _WIRE_110.sx, _T_1524
node _T_1525 = bits(_WIRE_111, 14, 14)
connect _WIRE_110.sw, _T_1525
node _T_1526 = bits(_WIRE_111, 15, 15)
connect _WIRE_110.gf, _T_1526
node _T_1527 = bits(_WIRE_111, 16, 16)
connect _WIRE_110.pf, _T_1527
node _T_1528 = bits(_WIRE_111, 17, 17)
connect _WIRE_110.ae_stage2, _T_1528
node _T_1529 = bits(_WIRE_111, 18, 18)
connect _WIRE_110.ae_final, _T_1529
node _T_1530 = bits(_WIRE_111, 19, 19)
connect _WIRE_110.ae_ptw, _T_1530
node _T_1531 = bits(_WIRE_111, 20, 20)
connect _WIRE_110.g, _T_1531
node _T_1532 = bits(_WIRE_111, 21, 21)
connect _WIRE_110.u, _T_1532
node _T_1533 = bits(_WIRE_111, 41, 22)
connect _WIRE_110.ppn, _T_1533
node _T_1534 = eq(sectored_entries[0][3].tag_v, hv_3)
node _T_1535 = and(_T_1534, _WIRE_104.fragmented_superpage)
when _T_1535 :
connect sectored_entries[0][3].valid[0], UInt<1>(0h0)
node _T_1536 = eq(sectored_entries[0][3].tag_v, hv_3)
node _T_1537 = and(_T_1536, _WIRE_106.fragmented_superpage)
when _T_1537 :
connect sectored_entries[0][3].valid[1], UInt<1>(0h0)
node _T_1538 = eq(sectored_entries[0][3].tag_v, hv_3)
node _T_1539 = and(_T_1538, _WIRE_108.fragmented_superpage)
when _T_1539 :
connect sectored_entries[0][3].valid[2], UInt<1>(0h0)
node _T_1540 = eq(sectored_entries[0][3].tag_v, hv_3)
node _T_1541 = and(_T_1540, _WIRE_110.fragmented_superpage)
when _T_1541 :
connect sectored_entries[0][3].valid[3], UInt<1>(0h0)
else :
node _T_1542 = eq(hg_3, UInt<1>(0h0))
node _T_1543 = and(_T_1542, io.sfence.bits.rs2)
when _T_1543 :
wire _WIRE_112 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_113 : UInt<42>
connect _WIRE_113, sectored_entries[0][3].data[0]
node _T_1544 = bits(_WIRE_113, 0, 0)
connect _WIRE_112.fragmented_superpage, _T_1544
node _T_1545 = bits(_WIRE_113, 1, 1)
connect _WIRE_112.c, _T_1545
node _T_1546 = bits(_WIRE_113, 2, 2)
connect _WIRE_112.eff, _T_1546
node _T_1547 = bits(_WIRE_113, 3, 3)
connect _WIRE_112.paa, _T_1547
node _T_1548 = bits(_WIRE_113, 4, 4)
connect _WIRE_112.pal, _T_1548
node _T_1549 = bits(_WIRE_113, 5, 5)
connect _WIRE_112.ppp, _T_1549
node _T_1550 = bits(_WIRE_113, 6, 6)
connect _WIRE_112.pr, _T_1550
node _T_1551 = bits(_WIRE_113, 7, 7)
connect _WIRE_112.px, _T_1551
node _T_1552 = bits(_WIRE_113, 8, 8)
connect _WIRE_112.pw, _T_1552
node _T_1553 = bits(_WIRE_113, 9, 9)
connect _WIRE_112.hr, _T_1553
node _T_1554 = bits(_WIRE_113, 10, 10)
connect _WIRE_112.hx, _T_1554
node _T_1555 = bits(_WIRE_113, 11, 11)
connect _WIRE_112.hw, _T_1555
node _T_1556 = bits(_WIRE_113, 12, 12)
connect _WIRE_112.sr, _T_1556
node _T_1557 = bits(_WIRE_113, 13, 13)
connect _WIRE_112.sx, _T_1557
node _T_1558 = bits(_WIRE_113, 14, 14)
connect _WIRE_112.sw, _T_1558
node _T_1559 = bits(_WIRE_113, 15, 15)
connect _WIRE_112.gf, _T_1559
node _T_1560 = bits(_WIRE_113, 16, 16)
connect _WIRE_112.pf, _T_1560
node _T_1561 = bits(_WIRE_113, 17, 17)
connect _WIRE_112.ae_stage2, _T_1561
node _T_1562 = bits(_WIRE_113, 18, 18)
connect _WIRE_112.ae_final, _T_1562
node _T_1563 = bits(_WIRE_113, 19, 19)
connect _WIRE_112.ae_ptw, _T_1563
node _T_1564 = bits(_WIRE_113, 20, 20)
connect _WIRE_112.g, _T_1564
node _T_1565 = bits(_WIRE_113, 21, 21)
connect _WIRE_112.u, _T_1565
node _T_1566 = bits(_WIRE_113, 41, 22)
connect _WIRE_112.ppn, _T_1566
wire _WIRE_114 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_115 : UInt<42>
connect _WIRE_115, sectored_entries[0][3].data[1]
node _T_1567 = bits(_WIRE_115, 0, 0)
connect _WIRE_114.fragmented_superpage, _T_1567
node _T_1568 = bits(_WIRE_115, 1, 1)
connect _WIRE_114.c, _T_1568
node _T_1569 = bits(_WIRE_115, 2, 2)
connect _WIRE_114.eff, _T_1569
node _T_1570 = bits(_WIRE_115, 3, 3)
connect _WIRE_114.paa, _T_1570
node _T_1571 = bits(_WIRE_115, 4, 4)
connect _WIRE_114.pal, _T_1571
node _T_1572 = bits(_WIRE_115, 5, 5)
connect _WIRE_114.ppp, _T_1572
node _T_1573 = bits(_WIRE_115, 6, 6)
connect _WIRE_114.pr, _T_1573
node _T_1574 = bits(_WIRE_115, 7, 7)
connect _WIRE_114.px, _T_1574
node _T_1575 = bits(_WIRE_115, 8, 8)
connect _WIRE_114.pw, _T_1575
node _T_1576 = bits(_WIRE_115, 9, 9)
connect _WIRE_114.hr, _T_1576
node _T_1577 = bits(_WIRE_115, 10, 10)
connect _WIRE_114.hx, _T_1577
node _T_1578 = bits(_WIRE_115, 11, 11)
connect _WIRE_114.hw, _T_1578
node _T_1579 = bits(_WIRE_115, 12, 12)
connect _WIRE_114.sr, _T_1579
node _T_1580 = bits(_WIRE_115, 13, 13)
connect _WIRE_114.sx, _T_1580
node _T_1581 = bits(_WIRE_115, 14, 14)
connect _WIRE_114.sw, _T_1581
node _T_1582 = bits(_WIRE_115, 15, 15)
connect _WIRE_114.gf, _T_1582
node _T_1583 = bits(_WIRE_115, 16, 16)
connect _WIRE_114.pf, _T_1583
node _T_1584 = bits(_WIRE_115, 17, 17)
connect _WIRE_114.ae_stage2, _T_1584
node _T_1585 = bits(_WIRE_115, 18, 18)
connect _WIRE_114.ae_final, _T_1585
node _T_1586 = bits(_WIRE_115, 19, 19)
connect _WIRE_114.ae_ptw, _T_1586
node _T_1587 = bits(_WIRE_115, 20, 20)
connect _WIRE_114.g, _T_1587
node _T_1588 = bits(_WIRE_115, 21, 21)
connect _WIRE_114.u, _T_1588
node _T_1589 = bits(_WIRE_115, 41, 22)
connect _WIRE_114.ppn, _T_1589
wire _WIRE_116 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_117 : UInt<42>
connect _WIRE_117, sectored_entries[0][3].data[2]
node _T_1590 = bits(_WIRE_117, 0, 0)
connect _WIRE_116.fragmented_superpage, _T_1590
node _T_1591 = bits(_WIRE_117, 1, 1)
connect _WIRE_116.c, _T_1591
node _T_1592 = bits(_WIRE_117, 2, 2)
connect _WIRE_116.eff, _T_1592
node _T_1593 = bits(_WIRE_117, 3, 3)
connect _WIRE_116.paa, _T_1593
node _T_1594 = bits(_WIRE_117, 4, 4)
connect _WIRE_116.pal, _T_1594
node _T_1595 = bits(_WIRE_117, 5, 5)
connect _WIRE_116.ppp, _T_1595
node _T_1596 = bits(_WIRE_117, 6, 6)
connect _WIRE_116.pr, _T_1596
node _T_1597 = bits(_WIRE_117, 7, 7)
connect _WIRE_116.px, _T_1597
node _T_1598 = bits(_WIRE_117, 8, 8)
connect _WIRE_116.pw, _T_1598
node _T_1599 = bits(_WIRE_117, 9, 9)
connect _WIRE_116.hr, _T_1599
node _T_1600 = bits(_WIRE_117, 10, 10)
connect _WIRE_116.hx, _T_1600
node _T_1601 = bits(_WIRE_117, 11, 11)
connect _WIRE_116.hw, _T_1601
node _T_1602 = bits(_WIRE_117, 12, 12)
connect _WIRE_116.sr, _T_1602
node _T_1603 = bits(_WIRE_117, 13, 13)
connect _WIRE_116.sx, _T_1603
node _T_1604 = bits(_WIRE_117, 14, 14)
connect _WIRE_116.sw, _T_1604
node _T_1605 = bits(_WIRE_117, 15, 15)
connect _WIRE_116.gf, _T_1605
node _T_1606 = bits(_WIRE_117, 16, 16)
connect _WIRE_116.pf, _T_1606
node _T_1607 = bits(_WIRE_117, 17, 17)
connect _WIRE_116.ae_stage2, _T_1607
node _T_1608 = bits(_WIRE_117, 18, 18)
connect _WIRE_116.ae_final, _T_1608
node _T_1609 = bits(_WIRE_117, 19, 19)
connect _WIRE_116.ae_ptw, _T_1609
node _T_1610 = bits(_WIRE_117, 20, 20)
connect _WIRE_116.g, _T_1610
node _T_1611 = bits(_WIRE_117, 21, 21)
connect _WIRE_116.u, _T_1611
node _T_1612 = bits(_WIRE_117, 41, 22)
connect _WIRE_116.ppn, _T_1612
wire _WIRE_118 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_119 : UInt<42>
connect _WIRE_119, sectored_entries[0][3].data[3]
node _T_1613 = bits(_WIRE_119, 0, 0)
connect _WIRE_118.fragmented_superpage, _T_1613
node _T_1614 = bits(_WIRE_119, 1, 1)
connect _WIRE_118.c, _T_1614
node _T_1615 = bits(_WIRE_119, 2, 2)
connect _WIRE_118.eff, _T_1615
node _T_1616 = bits(_WIRE_119, 3, 3)
connect _WIRE_118.paa, _T_1616
node _T_1617 = bits(_WIRE_119, 4, 4)
connect _WIRE_118.pal, _T_1617
node _T_1618 = bits(_WIRE_119, 5, 5)
connect _WIRE_118.ppp, _T_1618
node _T_1619 = bits(_WIRE_119, 6, 6)
connect _WIRE_118.pr, _T_1619
node _T_1620 = bits(_WIRE_119, 7, 7)
connect _WIRE_118.px, _T_1620
node _T_1621 = bits(_WIRE_119, 8, 8)
connect _WIRE_118.pw, _T_1621
node _T_1622 = bits(_WIRE_119, 9, 9)
connect _WIRE_118.hr, _T_1622
node _T_1623 = bits(_WIRE_119, 10, 10)
connect _WIRE_118.hx, _T_1623
node _T_1624 = bits(_WIRE_119, 11, 11)
connect _WIRE_118.hw, _T_1624
node _T_1625 = bits(_WIRE_119, 12, 12)
connect _WIRE_118.sr, _T_1625
node _T_1626 = bits(_WIRE_119, 13, 13)
connect _WIRE_118.sx, _T_1626
node _T_1627 = bits(_WIRE_119, 14, 14)
connect _WIRE_118.sw, _T_1627
node _T_1628 = bits(_WIRE_119, 15, 15)
connect _WIRE_118.gf, _T_1628
node _T_1629 = bits(_WIRE_119, 16, 16)
connect _WIRE_118.pf, _T_1629
node _T_1630 = bits(_WIRE_119, 17, 17)
connect _WIRE_118.ae_stage2, _T_1630
node _T_1631 = bits(_WIRE_119, 18, 18)
connect _WIRE_118.ae_final, _T_1631
node _T_1632 = bits(_WIRE_119, 19, 19)
connect _WIRE_118.ae_ptw, _T_1632
node _T_1633 = bits(_WIRE_119, 20, 20)
connect _WIRE_118.g, _T_1633
node _T_1634 = bits(_WIRE_119, 21, 21)
connect _WIRE_118.u, _T_1634
node _T_1635 = bits(_WIRE_119, 41, 22)
connect _WIRE_118.ppn, _T_1635
node _T_1636 = eq(sectored_entries[0][3].tag_v, hv_3)
node _T_1637 = eq(_WIRE_112.g, UInt<1>(0h0))
node _T_1638 = and(_T_1636, _T_1637)
when _T_1638 :
connect sectored_entries[0][3].valid[0], UInt<1>(0h0)
node _T_1639 = eq(sectored_entries[0][3].tag_v, hv_3)
node _T_1640 = eq(_WIRE_114.g, UInt<1>(0h0))
node _T_1641 = and(_T_1639, _T_1640)
when _T_1641 :
connect sectored_entries[0][3].valid[1], UInt<1>(0h0)
node _T_1642 = eq(sectored_entries[0][3].tag_v, hv_3)
node _T_1643 = eq(_WIRE_116.g, UInt<1>(0h0))
node _T_1644 = and(_T_1642, _T_1643)
when _T_1644 :
connect sectored_entries[0][3].valid[2], UInt<1>(0h0)
node _T_1645 = eq(sectored_entries[0][3].tag_v, hv_3)
node _T_1646 = eq(_WIRE_118.g, UInt<1>(0h0))
node _T_1647 = and(_T_1645, _T_1646)
when _T_1647 :
connect sectored_entries[0][3].valid[3], UInt<1>(0h0)
else :
node _T_1648 = or(hv_3, hg_3)
wire _WIRE_120 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_121 : UInt<42>
connect _WIRE_121, sectored_entries[0][3].data[0]
node _T_1649 = bits(_WIRE_121, 0, 0)
connect _WIRE_120.fragmented_superpage, _T_1649
node _T_1650 = bits(_WIRE_121, 1, 1)
connect _WIRE_120.c, _T_1650
node _T_1651 = bits(_WIRE_121, 2, 2)
connect _WIRE_120.eff, _T_1651
node _T_1652 = bits(_WIRE_121, 3, 3)
connect _WIRE_120.paa, _T_1652
node _T_1653 = bits(_WIRE_121, 4, 4)
connect _WIRE_120.pal, _T_1653
node _T_1654 = bits(_WIRE_121, 5, 5)
connect _WIRE_120.ppp, _T_1654
node _T_1655 = bits(_WIRE_121, 6, 6)
connect _WIRE_120.pr, _T_1655
node _T_1656 = bits(_WIRE_121, 7, 7)
connect _WIRE_120.px, _T_1656
node _T_1657 = bits(_WIRE_121, 8, 8)
connect _WIRE_120.pw, _T_1657
node _T_1658 = bits(_WIRE_121, 9, 9)
connect _WIRE_120.hr, _T_1658
node _T_1659 = bits(_WIRE_121, 10, 10)
connect _WIRE_120.hx, _T_1659
node _T_1660 = bits(_WIRE_121, 11, 11)
connect _WIRE_120.hw, _T_1660
node _T_1661 = bits(_WIRE_121, 12, 12)
connect _WIRE_120.sr, _T_1661
node _T_1662 = bits(_WIRE_121, 13, 13)
connect _WIRE_120.sx, _T_1662
node _T_1663 = bits(_WIRE_121, 14, 14)
connect _WIRE_120.sw, _T_1663
node _T_1664 = bits(_WIRE_121, 15, 15)
connect _WIRE_120.gf, _T_1664
node _T_1665 = bits(_WIRE_121, 16, 16)
connect _WIRE_120.pf, _T_1665
node _T_1666 = bits(_WIRE_121, 17, 17)
connect _WIRE_120.ae_stage2, _T_1666
node _T_1667 = bits(_WIRE_121, 18, 18)
connect _WIRE_120.ae_final, _T_1667
node _T_1668 = bits(_WIRE_121, 19, 19)
connect _WIRE_120.ae_ptw, _T_1668
node _T_1669 = bits(_WIRE_121, 20, 20)
connect _WIRE_120.g, _T_1669
node _T_1670 = bits(_WIRE_121, 21, 21)
connect _WIRE_120.u, _T_1670
node _T_1671 = bits(_WIRE_121, 41, 22)
connect _WIRE_120.ppn, _T_1671
wire _WIRE_122 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_123 : UInt<42>
connect _WIRE_123, sectored_entries[0][3].data[1]
node _T_1672 = bits(_WIRE_123, 0, 0)
connect _WIRE_122.fragmented_superpage, _T_1672
node _T_1673 = bits(_WIRE_123, 1, 1)
connect _WIRE_122.c, _T_1673
node _T_1674 = bits(_WIRE_123, 2, 2)
connect _WIRE_122.eff, _T_1674
node _T_1675 = bits(_WIRE_123, 3, 3)
connect _WIRE_122.paa, _T_1675
node _T_1676 = bits(_WIRE_123, 4, 4)
connect _WIRE_122.pal, _T_1676
node _T_1677 = bits(_WIRE_123, 5, 5)
connect _WIRE_122.ppp, _T_1677
node _T_1678 = bits(_WIRE_123, 6, 6)
connect _WIRE_122.pr, _T_1678
node _T_1679 = bits(_WIRE_123, 7, 7)
connect _WIRE_122.px, _T_1679
node _T_1680 = bits(_WIRE_123, 8, 8)
connect _WIRE_122.pw, _T_1680
node _T_1681 = bits(_WIRE_123, 9, 9)
connect _WIRE_122.hr, _T_1681
node _T_1682 = bits(_WIRE_123, 10, 10)
connect _WIRE_122.hx, _T_1682
node _T_1683 = bits(_WIRE_123, 11, 11)
connect _WIRE_122.hw, _T_1683
node _T_1684 = bits(_WIRE_123, 12, 12)
connect _WIRE_122.sr, _T_1684
node _T_1685 = bits(_WIRE_123, 13, 13)
connect _WIRE_122.sx, _T_1685
node _T_1686 = bits(_WIRE_123, 14, 14)
connect _WIRE_122.sw, _T_1686
node _T_1687 = bits(_WIRE_123, 15, 15)
connect _WIRE_122.gf, _T_1687
node _T_1688 = bits(_WIRE_123, 16, 16)
connect _WIRE_122.pf, _T_1688
node _T_1689 = bits(_WIRE_123, 17, 17)
connect _WIRE_122.ae_stage2, _T_1689
node _T_1690 = bits(_WIRE_123, 18, 18)
connect _WIRE_122.ae_final, _T_1690
node _T_1691 = bits(_WIRE_123, 19, 19)
connect _WIRE_122.ae_ptw, _T_1691
node _T_1692 = bits(_WIRE_123, 20, 20)
connect _WIRE_122.g, _T_1692
node _T_1693 = bits(_WIRE_123, 21, 21)
connect _WIRE_122.u, _T_1693
node _T_1694 = bits(_WIRE_123, 41, 22)
connect _WIRE_122.ppn, _T_1694
wire _WIRE_124 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_125 : UInt<42>
connect _WIRE_125, sectored_entries[0][3].data[2]
node _T_1695 = bits(_WIRE_125, 0, 0)
connect _WIRE_124.fragmented_superpage, _T_1695
node _T_1696 = bits(_WIRE_125, 1, 1)
connect _WIRE_124.c, _T_1696
node _T_1697 = bits(_WIRE_125, 2, 2)
connect _WIRE_124.eff, _T_1697
node _T_1698 = bits(_WIRE_125, 3, 3)
connect _WIRE_124.paa, _T_1698
node _T_1699 = bits(_WIRE_125, 4, 4)
connect _WIRE_124.pal, _T_1699
node _T_1700 = bits(_WIRE_125, 5, 5)
connect _WIRE_124.ppp, _T_1700
node _T_1701 = bits(_WIRE_125, 6, 6)
connect _WIRE_124.pr, _T_1701
node _T_1702 = bits(_WIRE_125, 7, 7)
connect _WIRE_124.px, _T_1702
node _T_1703 = bits(_WIRE_125, 8, 8)
connect _WIRE_124.pw, _T_1703
node _T_1704 = bits(_WIRE_125, 9, 9)
connect _WIRE_124.hr, _T_1704
node _T_1705 = bits(_WIRE_125, 10, 10)
connect _WIRE_124.hx, _T_1705
node _T_1706 = bits(_WIRE_125, 11, 11)
connect _WIRE_124.hw, _T_1706
node _T_1707 = bits(_WIRE_125, 12, 12)
connect _WIRE_124.sr, _T_1707
node _T_1708 = bits(_WIRE_125, 13, 13)
connect _WIRE_124.sx, _T_1708
node _T_1709 = bits(_WIRE_125, 14, 14)
connect _WIRE_124.sw, _T_1709
node _T_1710 = bits(_WIRE_125, 15, 15)
connect _WIRE_124.gf, _T_1710
node _T_1711 = bits(_WIRE_125, 16, 16)
connect _WIRE_124.pf, _T_1711
node _T_1712 = bits(_WIRE_125, 17, 17)
connect _WIRE_124.ae_stage2, _T_1712
node _T_1713 = bits(_WIRE_125, 18, 18)
connect _WIRE_124.ae_final, _T_1713
node _T_1714 = bits(_WIRE_125, 19, 19)
connect _WIRE_124.ae_ptw, _T_1714
node _T_1715 = bits(_WIRE_125, 20, 20)
connect _WIRE_124.g, _T_1715
node _T_1716 = bits(_WIRE_125, 21, 21)
connect _WIRE_124.u, _T_1716
node _T_1717 = bits(_WIRE_125, 41, 22)
connect _WIRE_124.ppn, _T_1717
wire _WIRE_126 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_127 : UInt<42>
connect _WIRE_127, sectored_entries[0][3].data[3]
node _T_1718 = bits(_WIRE_127, 0, 0)
connect _WIRE_126.fragmented_superpage, _T_1718
node _T_1719 = bits(_WIRE_127, 1, 1)
connect _WIRE_126.c, _T_1719
node _T_1720 = bits(_WIRE_127, 2, 2)
connect _WIRE_126.eff, _T_1720
node _T_1721 = bits(_WIRE_127, 3, 3)
connect _WIRE_126.paa, _T_1721
node _T_1722 = bits(_WIRE_127, 4, 4)
connect _WIRE_126.pal, _T_1722
node _T_1723 = bits(_WIRE_127, 5, 5)
connect _WIRE_126.ppp, _T_1723
node _T_1724 = bits(_WIRE_127, 6, 6)
connect _WIRE_126.pr, _T_1724
node _T_1725 = bits(_WIRE_127, 7, 7)
connect _WIRE_126.px, _T_1725
node _T_1726 = bits(_WIRE_127, 8, 8)
connect _WIRE_126.pw, _T_1726
node _T_1727 = bits(_WIRE_127, 9, 9)
connect _WIRE_126.hr, _T_1727
node _T_1728 = bits(_WIRE_127, 10, 10)
connect _WIRE_126.hx, _T_1728
node _T_1729 = bits(_WIRE_127, 11, 11)
connect _WIRE_126.hw, _T_1729
node _T_1730 = bits(_WIRE_127, 12, 12)
connect _WIRE_126.sr, _T_1730
node _T_1731 = bits(_WIRE_127, 13, 13)
connect _WIRE_126.sx, _T_1731
node _T_1732 = bits(_WIRE_127, 14, 14)
connect _WIRE_126.sw, _T_1732
node _T_1733 = bits(_WIRE_127, 15, 15)
connect _WIRE_126.gf, _T_1733
node _T_1734 = bits(_WIRE_127, 16, 16)
connect _WIRE_126.pf, _T_1734
node _T_1735 = bits(_WIRE_127, 17, 17)
connect _WIRE_126.ae_stage2, _T_1735
node _T_1736 = bits(_WIRE_127, 18, 18)
connect _WIRE_126.ae_final, _T_1736
node _T_1737 = bits(_WIRE_127, 19, 19)
connect _WIRE_126.ae_ptw, _T_1737
node _T_1738 = bits(_WIRE_127, 20, 20)
connect _WIRE_126.g, _T_1738
node _T_1739 = bits(_WIRE_127, 21, 21)
connect _WIRE_126.u, _T_1739
node _T_1740 = bits(_WIRE_127, 41, 22)
connect _WIRE_126.ppn, _T_1740
node _T_1741 = eq(sectored_entries[0][3].tag_v, _T_1648)
when _T_1741 :
connect sectored_entries[0][3].valid[0], UInt<1>(0h0)
node _T_1742 = eq(sectored_entries[0][3].tag_v, _T_1648)
when _T_1742 :
connect sectored_entries[0][3].valid[1], UInt<1>(0h0)
node _T_1743 = eq(sectored_entries[0][3].tag_v, _T_1648)
when _T_1743 :
connect sectored_entries[0][3].valid[2], UInt<1>(0h0)
node _T_1744 = eq(sectored_entries[0][3].tag_v, _T_1648)
when _T_1744 :
connect sectored_entries[0][3].valid[3], UInt<1>(0h0)
node hv_4 = and(UInt<1>(0h0), io.sfence.bits.hv)
node hg_4 = and(UInt<1>(0h0), io.sfence.bits.hg)
node _T_1745 = eq(hg_4, UInt<1>(0h0))
node _T_1746 = and(_T_1745, io.sfence.bits.rs1)
when _T_1746 :
node _T_1747 = xor(sectored_entries[0][4].tag_vpn, vpn)
node _T_1748 = shr(_T_1747, 2)
node _T_1749 = eq(_T_1748, UInt<1>(0h0))
node _T_1750 = eq(sectored_entries[0][4].tag_v, hv_4)
node _T_1751 = and(_T_1749, _T_1750)
when _T_1751 :
wire _WIRE_128 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_129 : UInt<42>
connect _WIRE_129, sectored_entries[0][4].data[0]
node _T_1752 = bits(_WIRE_129, 0, 0)
connect _WIRE_128.fragmented_superpage, _T_1752
node _T_1753 = bits(_WIRE_129, 1, 1)
connect _WIRE_128.c, _T_1753
node _T_1754 = bits(_WIRE_129, 2, 2)
connect _WIRE_128.eff, _T_1754
node _T_1755 = bits(_WIRE_129, 3, 3)
connect _WIRE_128.paa, _T_1755
node _T_1756 = bits(_WIRE_129, 4, 4)
connect _WIRE_128.pal, _T_1756
node _T_1757 = bits(_WIRE_129, 5, 5)
connect _WIRE_128.ppp, _T_1757
node _T_1758 = bits(_WIRE_129, 6, 6)
connect _WIRE_128.pr, _T_1758
node _T_1759 = bits(_WIRE_129, 7, 7)
connect _WIRE_128.px, _T_1759
node _T_1760 = bits(_WIRE_129, 8, 8)
connect _WIRE_128.pw, _T_1760
node _T_1761 = bits(_WIRE_129, 9, 9)
connect _WIRE_128.hr, _T_1761
node _T_1762 = bits(_WIRE_129, 10, 10)
connect _WIRE_128.hx, _T_1762
node _T_1763 = bits(_WIRE_129, 11, 11)
connect _WIRE_128.hw, _T_1763
node _T_1764 = bits(_WIRE_129, 12, 12)
connect _WIRE_128.sr, _T_1764
node _T_1765 = bits(_WIRE_129, 13, 13)
connect _WIRE_128.sx, _T_1765
node _T_1766 = bits(_WIRE_129, 14, 14)
connect _WIRE_128.sw, _T_1766
node _T_1767 = bits(_WIRE_129, 15, 15)
connect _WIRE_128.gf, _T_1767
node _T_1768 = bits(_WIRE_129, 16, 16)
connect _WIRE_128.pf, _T_1768
node _T_1769 = bits(_WIRE_129, 17, 17)
connect _WIRE_128.ae_stage2, _T_1769
node _T_1770 = bits(_WIRE_129, 18, 18)
connect _WIRE_128.ae_final, _T_1770
node _T_1771 = bits(_WIRE_129, 19, 19)
connect _WIRE_128.ae_ptw, _T_1771
node _T_1772 = bits(_WIRE_129, 20, 20)
connect _WIRE_128.g, _T_1772
node _T_1773 = bits(_WIRE_129, 21, 21)
connect _WIRE_128.u, _T_1773
node _T_1774 = bits(_WIRE_129, 41, 22)
connect _WIRE_128.ppn, _T_1774
wire _WIRE_130 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_131 : UInt<42>
connect _WIRE_131, sectored_entries[0][4].data[1]
node _T_1775 = bits(_WIRE_131, 0, 0)
connect _WIRE_130.fragmented_superpage, _T_1775
node _T_1776 = bits(_WIRE_131, 1, 1)
connect _WIRE_130.c, _T_1776
node _T_1777 = bits(_WIRE_131, 2, 2)
connect _WIRE_130.eff, _T_1777
node _T_1778 = bits(_WIRE_131, 3, 3)
connect _WIRE_130.paa, _T_1778
node _T_1779 = bits(_WIRE_131, 4, 4)
connect _WIRE_130.pal, _T_1779
node _T_1780 = bits(_WIRE_131, 5, 5)
connect _WIRE_130.ppp, _T_1780
node _T_1781 = bits(_WIRE_131, 6, 6)
connect _WIRE_130.pr, _T_1781
node _T_1782 = bits(_WIRE_131, 7, 7)
connect _WIRE_130.px, _T_1782
node _T_1783 = bits(_WIRE_131, 8, 8)
connect _WIRE_130.pw, _T_1783
node _T_1784 = bits(_WIRE_131, 9, 9)
connect _WIRE_130.hr, _T_1784
node _T_1785 = bits(_WIRE_131, 10, 10)
connect _WIRE_130.hx, _T_1785
node _T_1786 = bits(_WIRE_131, 11, 11)
connect _WIRE_130.hw, _T_1786
node _T_1787 = bits(_WIRE_131, 12, 12)
connect _WIRE_130.sr, _T_1787
node _T_1788 = bits(_WIRE_131, 13, 13)
connect _WIRE_130.sx, _T_1788
node _T_1789 = bits(_WIRE_131, 14, 14)
connect _WIRE_130.sw, _T_1789
node _T_1790 = bits(_WIRE_131, 15, 15)
connect _WIRE_130.gf, _T_1790
node _T_1791 = bits(_WIRE_131, 16, 16)
connect _WIRE_130.pf, _T_1791
node _T_1792 = bits(_WIRE_131, 17, 17)
connect _WIRE_130.ae_stage2, _T_1792
node _T_1793 = bits(_WIRE_131, 18, 18)
connect _WIRE_130.ae_final, _T_1793
node _T_1794 = bits(_WIRE_131, 19, 19)
connect _WIRE_130.ae_ptw, _T_1794
node _T_1795 = bits(_WIRE_131, 20, 20)
connect _WIRE_130.g, _T_1795
node _T_1796 = bits(_WIRE_131, 21, 21)
connect _WIRE_130.u, _T_1796
node _T_1797 = bits(_WIRE_131, 41, 22)
connect _WIRE_130.ppn, _T_1797
wire _WIRE_132 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_133 : UInt<42>
connect _WIRE_133, sectored_entries[0][4].data[2]
node _T_1798 = bits(_WIRE_133, 0, 0)
connect _WIRE_132.fragmented_superpage, _T_1798
node _T_1799 = bits(_WIRE_133, 1, 1)
connect _WIRE_132.c, _T_1799
node _T_1800 = bits(_WIRE_133, 2, 2)
connect _WIRE_132.eff, _T_1800
node _T_1801 = bits(_WIRE_133, 3, 3)
connect _WIRE_132.paa, _T_1801
node _T_1802 = bits(_WIRE_133, 4, 4)
connect _WIRE_132.pal, _T_1802
node _T_1803 = bits(_WIRE_133, 5, 5)
connect _WIRE_132.ppp, _T_1803
node _T_1804 = bits(_WIRE_133, 6, 6)
connect _WIRE_132.pr, _T_1804
node _T_1805 = bits(_WIRE_133, 7, 7)
connect _WIRE_132.px, _T_1805
node _T_1806 = bits(_WIRE_133, 8, 8)
connect _WIRE_132.pw, _T_1806
node _T_1807 = bits(_WIRE_133, 9, 9)
connect _WIRE_132.hr, _T_1807
node _T_1808 = bits(_WIRE_133, 10, 10)
connect _WIRE_132.hx, _T_1808
node _T_1809 = bits(_WIRE_133, 11, 11)
connect _WIRE_132.hw, _T_1809
node _T_1810 = bits(_WIRE_133, 12, 12)
connect _WIRE_132.sr, _T_1810
node _T_1811 = bits(_WIRE_133, 13, 13)
connect _WIRE_132.sx, _T_1811
node _T_1812 = bits(_WIRE_133, 14, 14)
connect _WIRE_132.sw, _T_1812
node _T_1813 = bits(_WIRE_133, 15, 15)
connect _WIRE_132.gf, _T_1813
node _T_1814 = bits(_WIRE_133, 16, 16)
connect _WIRE_132.pf, _T_1814
node _T_1815 = bits(_WIRE_133, 17, 17)
connect _WIRE_132.ae_stage2, _T_1815
node _T_1816 = bits(_WIRE_133, 18, 18)
connect _WIRE_132.ae_final, _T_1816
node _T_1817 = bits(_WIRE_133, 19, 19)
connect _WIRE_132.ae_ptw, _T_1817
node _T_1818 = bits(_WIRE_133, 20, 20)
connect _WIRE_132.g, _T_1818
node _T_1819 = bits(_WIRE_133, 21, 21)
connect _WIRE_132.u, _T_1819
node _T_1820 = bits(_WIRE_133, 41, 22)
connect _WIRE_132.ppn, _T_1820
wire _WIRE_134 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_135 : UInt<42>
connect _WIRE_135, sectored_entries[0][4].data[3]
node _T_1821 = bits(_WIRE_135, 0, 0)
connect _WIRE_134.fragmented_superpage, _T_1821
node _T_1822 = bits(_WIRE_135, 1, 1)
connect _WIRE_134.c, _T_1822
node _T_1823 = bits(_WIRE_135, 2, 2)
connect _WIRE_134.eff, _T_1823
node _T_1824 = bits(_WIRE_135, 3, 3)
connect _WIRE_134.paa, _T_1824
node _T_1825 = bits(_WIRE_135, 4, 4)
connect _WIRE_134.pal, _T_1825
node _T_1826 = bits(_WIRE_135, 5, 5)
connect _WIRE_134.ppp, _T_1826
node _T_1827 = bits(_WIRE_135, 6, 6)
connect _WIRE_134.pr, _T_1827
node _T_1828 = bits(_WIRE_135, 7, 7)
connect _WIRE_134.px, _T_1828
node _T_1829 = bits(_WIRE_135, 8, 8)
connect _WIRE_134.pw, _T_1829
node _T_1830 = bits(_WIRE_135, 9, 9)
connect _WIRE_134.hr, _T_1830
node _T_1831 = bits(_WIRE_135, 10, 10)
connect _WIRE_134.hx, _T_1831
node _T_1832 = bits(_WIRE_135, 11, 11)
connect _WIRE_134.hw, _T_1832
node _T_1833 = bits(_WIRE_135, 12, 12)
connect _WIRE_134.sr, _T_1833
node _T_1834 = bits(_WIRE_135, 13, 13)
connect _WIRE_134.sx, _T_1834
node _T_1835 = bits(_WIRE_135, 14, 14)
connect _WIRE_134.sw, _T_1835
node _T_1836 = bits(_WIRE_135, 15, 15)
connect _WIRE_134.gf, _T_1836
node _T_1837 = bits(_WIRE_135, 16, 16)
connect _WIRE_134.pf, _T_1837
node _T_1838 = bits(_WIRE_135, 17, 17)
connect _WIRE_134.ae_stage2, _T_1838
node _T_1839 = bits(_WIRE_135, 18, 18)
connect _WIRE_134.ae_final, _T_1839
node _T_1840 = bits(_WIRE_135, 19, 19)
connect _WIRE_134.ae_ptw, _T_1840
node _T_1841 = bits(_WIRE_135, 20, 20)
connect _WIRE_134.g, _T_1841
node _T_1842 = bits(_WIRE_135, 21, 21)
connect _WIRE_134.u, _T_1842
node _T_1843 = bits(_WIRE_135, 41, 22)
connect _WIRE_134.ppn, _T_1843
node _T_1844 = eq(sectored_entries[0][4].tag_v, hv_4)
node _T_1845 = bits(vpn, 1, 0)
node _T_1846 = eq(UInt<1>(0h0), _T_1845)
node _T_1847 = and(_T_1844, _T_1846)
when _T_1847 :
connect sectored_entries[0][4].valid[0], UInt<1>(0h0)
node _T_1848 = eq(sectored_entries[0][4].tag_v, hv_4)
node _T_1849 = bits(vpn, 1, 0)
node _T_1850 = eq(UInt<1>(0h1), _T_1849)
node _T_1851 = and(_T_1848, _T_1850)
when _T_1851 :
connect sectored_entries[0][4].valid[1], UInt<1>(0h0)
node _T_1852 = eq(sectored_entries[0][4].tag_v, hv_4)
node _T_1853 = bits(vpn, 1, 0)
node _T_1854 = eq(UInt<2>(0h2), _T_1853)
node _T_1855 = and(_T_1852, _T_1854)
when _T_1855 :
connect sectored_entries[0][4].valid[2], UInt<1>(0h0)
node _T_1856 = eq(sectored_entries[0][4].tag_v, hv_4)
node _T_1857 = bits(vpn, 1, 0)
node _T_1858 = eq(UInt<2>(0h3), _T_1857)
node _T_1859 = and(_T_1856, _T_1858)
when _T_1859 :
connect sectored_entries[0][4].valid[3], UInt<1>(0h0)
node _T_1860 = xor(sectored_entries[0][4].tag_vpn, vpn)
node _T_1861 = shr(_T_1860, 18)
node _T_1862 = eq(_T_1861, UInt<1>(0h0))
when _T_1862 :
wire _WIRE_136 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_137 : UInt<42>
connect _WIRE_137, sectored_entries[0][4].data[0]
node _T_1863 = bits(_WIRE_137, 0, 0)
connect _WIRE_136.fragmented_superpage, _T_1863
node _T_1864 = bits(_WIRE_137, 1, 1)
connect _WIRE_136.c, _T_1864
node _T_1865 = bits(_WIRE_137, 2, 2)
connect _WIRE_136.eff, _T_1865
node _T_1866 = bits(_WIRE_137, 3, 3)
connect _WIRE_136.paa, _T_1866
node _T_1867 = bits(_WIRE_137, 4, 4)
connect _WIRE_136.pal, _T_1867
node _T_1868 = bits(_WIRE_137, 5, 5)
connect _WIRE_136.ppp, _T_1868
node _T_1869 = bits(_WIRE_137, 6, 6)
connect _WIRE_136.pr, _T_1869
node _T_1870 = bits(_WIRE_137, 7, 7)
connect _WIRE_136.px, _T_1870
node _T_1871 = bits(_WIRE_137, 8, 8)
connect _WIRE_136.pw, _T_1871
node _T_1872 = bits(_WIRE_137, 9, 9)
connect _WIRE_136.hr, _T_1872
node _T_1873 = bits(_WIRE_137, 10, 10)
connect _WIRE_136.hx, _T_1873
node _T_1874 = bits(_WIRE_137, 11, 11)
connect _WIRE_136.hw, _T_1874
node _T_1875 = bits(_WIRE_137, 12, 12)
connect _WIRE_136.sr, _T_1875
node _T_1876 = bits(_WIRE_137, 13, 13)
connect _WIRE_136.sx, _T_1876
node _T_1877 = bits(_WIRE_137, 14, 14)
connect _WIRE_136.sw, _T_1877
node _T_1878 = bits(_WIRE_137, 15, 15)
connect _WIRE_136.gf, _T_1878
node _T_1879 = bits(_WIRE_137, 16, 16)
connect _WIRE_136.pf, _T_1879
node _T_1880 = bits(_WIRE_137, 17, 17)
connect _WIRE_136.ae_stage2, _T_1880
node _T_1881 = bits(_WIRE_137, 18, 18)
connect _WIRE_136.ae_final, _T_1881
node _T_1882 = bits(_WIRE_137, 19, 19)
connect _WIRE_136.ae_ptw, _T_1882
node _T_1883 = bits(_WIRE_137, 20, 20)
connect _WIRE_136.g, _T_1883
node _T_1884 = bits(_WIRE_137, 21, 21)
connect _WIRE_136.u, _T_1884
node _T_1885 = bits(_WIRE_137, 41, 22)
connect _WIRE_136.ppn, _T_1885
wire _WIRE_138 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_139 : UInt<42>
connect _WIRE_139, sectored_entries[0][4].data[1]
node _T_1886 = bits(_WIRE_139, 0, 0)
connect _WIRE_138.fragmented_superpage, _T_1886
node _T_1887 = bits(_WIRE_139, 1, 1)
connect _WIRE_138.c, _T_1887
node _T_1888 = bits(_WIRE_139, 2, 2)
connect _WIRE_138.eff, _T_1888
node _T_1889 = bits(_WIRE_139, 3, 3)
connect _WIRE_138.paa, _T_1889
node _T_1890 = bits(_WIRE_139, 4, 4)
connect _WIRE_138.pal, _T_1890
node _T_1891 = bits(_WIRE_139, 5, 5)
connect _WIRE_138.ppp, _T_1891
node _T_1892 = bits(_WIRE_139, 6, 6)
connect _WIRE_138.pr, _T_1892
node _T_1893 = bits(_WIRE_139, 7, 7)
connect _WIRE_138.px, _T_1893
node _T_1894 = bits(_WIRE_139, 8, 8)
connect _WIRE_138.pw, _T_1894
node _T_1895 = bits(_WIRE_139, 9, 9)
connect _WIRE_138.hr, _T_1895
node _T_1896 = bits(_WIRE_139, 10, 10)
connect _WIRE_138.hx, _T_1896
node _T_1897 = bits(_WIRE_139, 11, 11)
connect _WIRE_138.hw, _T_1897
node _T_1898 = bits(_WIRE_139, 12, 12)
connect _WIRE_138.sr, _T_1898
node _T_1899 = bits(_WIRE_139, 13, 13)
connect _WIRE_138.sx, _T_1899
node _T_1900 = bits(_WIRE_139, 14, 14)
connect _WIRE_138.sw, _T_1900
node _T_1901 = bits(_WIRE_139, 15, 15)
connect _WIRE_138.gf, _T_1901
node _T_1902 = bits(_WIRE_139, 16, 16)
connect _WIRE_138.pf, _T_1902
node _T_1903 = bits(_WIRE_139, 17, 17)
connect _WIRE_138.ae_stage2, _T_1903
node _T_1904 = bits(_WIRE_139, 18, 18)
connect _WIRE_138.ae_final, _T_1904
node _T_1905 = bits(_WIRE_139, 19, 19)
connect _WIRE_138.ae_ptw, _T_1905
node _T_1906 = bits(_WIRE_139, 20, 20)
connect _WIRE_138.g, _T_1906
node _T_1907 = bits(_WIRE_139, 21, 21)
connect _WIRE_138.u, _T_1907
node _T_1908 = bits(_WIRE_139, 41, 22)
connect _WIRE_138.ppn, _T_1908
wire _WIRE_140 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_141 : UInt<42>
connect _WIRE_141, sectored_entries[0][4].data[2]
node _T_1909 = bits(_WIRE_141, 0, 0)
connect _WIRE_140.fragmented_superpage, _T_1909
node _T_1910 = bits(_WIRE_141, 1, 1)
connect _WIRE_140.c, _T_1910
node _T_1911 = bits(_WIRE_141, 2, 2)
connect _WIRE_140.eff, _T_1911
node _T_1912 = bits(_WIRE_141, 3, 3)
connect _WIRE_140.paa, _T_1912
node _T_1913 = bits(_WIRE_141, 4, 4)
connect _WIRE_140.pal, _T_1913
node _T_1914 = bits(_WIRE_141, 5, 5)
connect _WIRE_140.ppp, _T_1914
node _T_1915 = bits(_WIRE_141, 6, 6)
connect _WIRE_140.pr, _T_1915
node _T_1916 = bits(_WIRE_141, 7, 7)
connect _WIRE_140.px, _T_1916
node _T_1917 = bits(_WIRE_141, 8, 8)
connect _WIRE_140.pw, _T_1917
node _T_1918 = bits(_WIRE_141, 9, 9)
connect _WIRE_140.hr, _T_1918
node _T_1919 = bits(_WIRE_141, 10, 10)
connect _WIRE_140.hx, _T_1919
node _T_1920 = bits(_WIRE_141, 11, 11)
connect _WIRE_140.hw, _T_1920
node _T_1921 = bits(_WIRE_141, 12, 12)
connect _WIRE_140.sr, _T_1921
node _T_1922 = bits(_WIRE_141, 13, 13)
connect _WIRE_140.sx, _T_1922
node _T_1923 = bits(_WIRE_141, 14, 14)
connect _WIRE_140.sw, _T_1923
node _T_1924 = bits(_WIRE_141, 15, 15)
connect _WIRE_140.gf, _T_1924
node _T_1925 = bits(_WIRE_141, 16, 16)
connect _WIRE_140.pf, _T_1925
node _T_1926 = bits(_WIRE_141, 17, 17)
connect _WIRE_140.ae_stage2, _T_1926
node _T_1927 = bits(_WIRE_141, 18, 18)
connect _WIRE_140.ae_final, _T_1927
node _T_1928 = bits(_WIRE_141, 19, 19)
connect _WIRE_140.ae_ptw, _T_1928
node _T_1929 = bits(_WIRE_141, 20, 20)
connect _WIRE_140.g, _T_1929
node _T_1930 = bits(_WIRE_141, 21, 21)
connect _WIRE_140.u, _T_1930
node _T_1931 = bits(_WIRE_141, 41, 22)
connect _WIRE_140.ppn, _T_1931
wire _WIRE_142 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_143 : UInt<42>
connect _WIRE_143, sectored_entries[0][4].data[3]
node _T_1932 = bits(_WIRE_143, 0, 0)
connect _WIRE_142.fragmented_superpage, _T_1932
node _T_1933 = bits(_WIRE_143, 1, 1)
connect _WIRE_142.c, _T_1933
node _T_1934 = bits(_WIRE_143, 2, 2)
connect _WIRE_142.eff, _T_1934
node _T_1935 = bits(_WIRE_143, 3, 3)
connect _WIRE_142.paa, _T_1935
node _T_1936 = bits(_WIRE_143, 4, 4)
connect _WIRE_142.pal, _T_1936
node _T_1937 = bits(_WIRE_143, 5, 5)
connect _WIRE_142.ppp, _T_1937
node _T_1938 = bits(_WIRE_143, 6, 6)
connect _WIRE_142.pr, _T_1938
node _T_1939 = bits(_WIRE_143, 7, 7)
connect _WIRE_142.px, _T_1939
node _T_1940 = bits(_WIRE_143, 8, 8)
connect _WIRE_142.pw, _T_1940
node _T_1941 = bits(_WIRE_143, 9, 9)
connect _WIRE_142.hr, _T_1941
node _T_1942 = bits(_WIRE_143, 10, 10)
connect _WIRE_142.hx, _T_1942
node _T_1943 = bits(_WIRE_143, 11, 11)
connect _WIRE_142.hw, _T_1943
node _T_1944 = bits(_WIRE_143, 12, 12)
connect _WIRE_142.sr, _T_1944
node _T_1945 = bits(_WIRE_143, 13, 13)
connect _WIRE_142.sx, _T_1945
node _T_1946 = bits(_WIRE_143, 14, 14)
connect _WIRE_142.sw, _T_1946
node _T_1947 = bits(_WIRE_143, 15, 15)
connect _WIRE_142.gf, _T_1947
node _T_1948 = bits(_WIRE_143, 16, 16)
connect _WIRE_142.pf, _T_1948
node _T_1949 = bits(_WIRE_143, 17, 17)
connect _WIRE_142.ae_stage2, _T_1949
node _T_1950 = bits(_WIRE_143, 18, 18)
connect _WIRE_142.ae_final, _T_1950
node _T_1951 = bits(_WIRE_143, 19, 19)
connect _WIRE_142.ae_ptw, _T_1951
node _T_1952 = bits(_WIRE_143, 20, 20)
connect _WIRE_142.g, _T_1952
node _T_1953 = bits(_WIRE_143, 21, 21)
connect _WIRE_142.u, _T_1953
node _T_1954 = bits(_WIRE_143, 41, 22)
connect _WIRE_142.ppn, _T_1954
node _T_1955 = eq(sectored_entries[0][4].tag_v, hv_4)
node _T_1956 = and(_T_1955, _WIRE_136.fragmented_superpage)
when _T_1956 :
connect sectored_entries[0][4].valid[0], UInt<1>(0h0)
node _T_1957 = eq(sectored_entries[0][4].tag_v, hv_4)
node _T_1958 = and(_T_1957, _WIRE_138.fragmented_superpage)
when _T_1958 :
connect sectored_entries[0][4].valid[1], UInt<1>(0h0)
node _T_1959 = eq(sectored_entries[0][4].tag_v, hv_4)
node _T_1960 = and(_T_1959, _WIRE_140.fragmented_superpage)
when _T_1960 :
connect sectored_entries[0][4].valid[2], UInt<1>(0h0)
node _T_1961 = eq(sectored_entries[0][4].tag_v, hv_4)
node _T_1962 = and(_T_1961, _WIRE_142.fragmented_superpage)
when _T_1962 :
connect sectored_entries[0][4].valid[3], UInt<1>(0h0)
else :
node _T_1963 = eq(hg_4, UInt<1>(0h0))
node _T_1964 = and(_T_1963, io.sfence.bits.rs2)
when _T_1964 :
wire _WIRE_144 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_145 : UInt<42>
connect _WIRE_145, sectored_entries[0][4].data[0]
node _T_1965 = bits(_WIRE_145, 0, 0)
connect _WIRE_144.fragmented_superpage, _T_1965
node _T_1966 = bits(_WIRE_145, 1, 1)
connect _WIRE_144.c, _T_1966
node _T_1967 = bits(_WIRE_145, 2, 2)
connect _WIRE_144.eff, _T_1967
node _T_1968 = bits(_WIRE_145, 3, 3)
connect _WIRE_144.paa, _T_1968
node _T_1969 = bits(_WIRE_145, 4, 4)
connect _WIRE_144.pal, _T_1969
node _T_1970 = bits(_WIRE_145, 5, 5)
connect _WIRE_144.ppp, _T_1970
node _T_1971 = bits(_WIRE_145, 6, 6)
connect _WIRE_144.pr, _T_1971
node _T_1972 = bits(_WIRE_145, 7, 7)
connect _WIRE_144.px, _T_1972
node _T_1973 = bits(_WIRE_145, 8, 8)
connect _WIRE_144.pw, _T_1973
node _T_1974 = bits(_WIRE_145, 9, 9)
connect _WIRE_144.hr, _T_1974
node _T_1975 = bits(_WIRE_145, 10, 10)
connect _WIRE_144.hx, _T_1975
node _T_1976 = bits(_WIRE_145, 11, 11)
connect _WIRE_144.hw, _T_1976
node _T_1977 = bits(_WIRE_145, 12, 12)
connect _WIRE_144.sr, _T_1977
node _T_1978 = bits(_WIRE_145, 13, 13)
connect _WIRE_144.sx, _T_1978
node _T_1979 = bits(_WIRE_145, 14, 14)
connect _WIRE_144.sw, _T_1979
node _T_1980 = bits(_WIRE_145, 15, 15)
connect _WIRE_144.gf, _T_1980
node _T_1981 = bits(_WIRE_145, 16, 16)
connect _WIRE_144.pf, _T_1981
node _T_1982 = bits(_WIRE_145, 17, 17)
connect _WIRE_144.ae_stage2, _T_1982
node _T_1983 = bits(_WIRE_145, 18, 18)
connect _WIRE_144.ae_final, _T_1983
node _T_1984 = bits(_WIRE_145, 19, 19)
connect _WIRE_144.ae_ptw, _T_1984
node _T_1985 = bits(_WIRE_145, 20, 20)
connect _WIRE_144.g, _T_1985
node _T_1986 = bits(_WIRE_145, 21, 21)
connect _WIRE_144.u, _T_1986
node _T_1987 = bits(_WIRE_145, 41, 22)
connect _WIRE_144.ppn, _T_1987
wire _WIRE_146 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_147 : UInt<42>
connect _WIRE_147, sectored_entries[0][4].data[1]
node _T_1988 = bits(_WIRE_147, 0, 0)
connect _WIRE_146.fragmented_superpage, _T_1988
node _T_1989 = bits(_WIRE_147, 1, 1)
connect _WIRE_146.c, _T_1989
node _T_1990 = bits(_WIRE_147, 2, 2)
connect _WIRE_146.eff, _T_1990
node _T_1991 = bits(_WIRE_147, 3, 3)
connect _WIRE_146.paa, _T_1991
node _T_1992 = bits(_WIRE_147, 4, 4)
connect _WIRE_146.pal, _T_1992
node _T_1993 = bits(_WIRE_147, 5, 5)
connect _WIRE_146.ppp, _T_1993
node _T_1994 = bits(_WIRE_147, 6, 6)
connect _WIRE_146.pr, _T_1994
node _T_1995 = bits(_WIRE_147, 7, 7)
connect _WIRE_146.px, _T_1995
node _T_1996 = bits(_WIRE_147, 8, 8)
connect _WIRE_146.pw, _T_1996
node _T_1997 = bits(_WIRE_147, 9, 9)
connect _WIRE_146.hr, _T_1997
node _T_1998 = bits(_WIRE_147, 10, 10)
connect _WIRE_146.hx, _T_1998
node _T_1999 = bits(_WIRE_147, 11, 11)
connect _WIRE_146.hw, _T_1999
node _T_2000 = bits(_WIRE_147, 12, 12)
connect _WIRE_146.sr, _T_2000
node _T_2001 = bits(_WIRE_147, 13, 13)
connect _WIRE_146.sx, _T_2001
node _T_2002 = bits(_WIRE_147, 14, 14)
connect _WIRE_146.sw, _T_2002
node _T_2003 = bits(_WIRE_147, 15, 15)
connect _WIRE_146.gf, _T_2003
node _T_2004 = bits(_WIRE_147, 16, 16)
connect _WIRE_146.pf, _T_2004
node _T_2005 = bits(_WIRE_147, 17, 17)
connect _WIRE_146.ae_stage2, _T_2005
node _T_2006 = bits(_WIRE_147, 18, 18)
connect _WIRE_146.ae_final, _T_2006
node _T_2007 = bits(_WIRE_147, 19, 19)
connect _WIRE_146.ae_ptw, _T_2007
node _T_2008 = bits(_WIRE_147, 20, 20)
connect _WIRE_146.g, _T_2008
node _T_2009 = bits(_WIRE_147, 21, 21)
connect _WIRE_146.u, _T_2009
node _T_2010 = bits(_WIRE_147, 41, 22)
connect _WIRE_146.ppn, _T_2010
wire _WIRE_148 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_149 : UInt<42>
connect _WIRE_149, sectored_entries[0][4].data[2]
node _T_2011 = bits(_WIRE_149, 0, 0)
connect _WIRE_148.fragmented_superpage, _T_2011
node _T_2012 = bits(_WIRE_149, 1, 1)
connect _WIRE_148.c, _T_2012
node _T_2013 = bits(_WIRE_149, 2, 2)
connect _WIRE_148.eff, _T_2013
node _T_2014 = bits(_WIRE_149, 3, 3)
connect _WIRE_148.paa, _T_2014
node _T_2015 = bits(_WIRE_149, 4, 4)
connect _WIRE_148.pal, _T_2015
node _T_2016 = bits(_WIRE_149, 5, 5)
connect _WIRE_148.ppp, _T_2016
node _T_2017 = bits(_WIRE_149, 6, 6)
connect _WIRE_148.pr, _T_2017
node _T_2018 = bits(_WIRE_149, 7, 7)
connect _WIRE_148.px, _T_2018
node _T_2019 = bits(_WIRE_149, 8, 8)
connect _WIRE_148.pw, _T_2019
node _T_2020 = bits(_WIRE_149, 9, 9)
connect _WIRE_148.hr, _T_2020
node _T_2021 = bits(_WIRE_149, 10, 10)
connect _WIRE_148.hx, _T_2021
node _T_2022 = bits(_WIRE_149, 11, 11)
connect _WIRE_148.hw, _T_2022
node _T_2023 = bits(_WIRE_149, 12, 12)
connect _WIRE_148.sr, _T_2023
node _T_2024 = bits(_WIRE_149, 13, 13)
connect _WIRE_148.sx, _T_2024
node _T_2025 = bits(_WIRE_149, 14, 14)
connect _WIRE_148.sw, _T_2025
node _T_2026 = bits(_WIRE_149, 15, 15)
connect _WIRE_148.gf, _T_2026
node _T_2027 = bits(_WIRE_149, 16, 16)
connect _WIRE_148.pf, _T_2027
node _T_2028 = bits(_WIRE_149, 17, 17)
connect _WIRE_148.ae_stage2, _T_2028
node _T_2029 = bits(_WIRE_149, 18, 18)
connect _WIRE_148.ae_final, _T_2029
node _T_2030 = bits(_WIRE_149, 19, 19)
connect _WIRE_148.ae_ptw, _T_2030
node _T_2031 = bits(_WIRE_149, 20, 20)
connect _WIRE_148.g, _T_2031
node _T_2032 = bits(_WIRE_149, 21, 21)
connect _WIRE_148.u, _T_2032
node _T_2033 = bits(_WIRE_149, 41, 22)
connect _WIRE_148.ppn, _T_2033
wire _WIRE_150 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_151 : UInt<42>
connect _WIRE_151, sectored_entries[0][4].data[3]
node _T_2034 = bits(_WIRE_151, 0, 0)
connect _WIRE_150.fragmented_superpage, _T_2034
node _T_2035 = bits(_WIRE_151, 1, 1)
connect _WIRE_150.c, _T_2035
node _T_2036 = bits(_WIRE_151, 2, 2)
connect _WIRE_150.eff, _T_2036
node _T_2037 = bits(_WIRE_151, 3, 3)
connect _WIRE_150.paa, _T_2037
node _T_2038 = bits(_WIRE_151, 4, 4)
connect _WIRE_150.pal, _T_2038
node _T_2039 = bits(_WIRE_151, 5, 5)
connect _WIRE_150.ppp, _T_2039
node _T_2040 = bits(_WIRE_151, 6, 6)
connect _WIRE_150.pr, _T_2040
node _T_2041 = bits(_WIRE_151, 7, 7)
connect _WIRE_150.px, _T_2041
node _T_2042 = bits(_WIRE_151, 8, 8)
connect _WIRE_150.pw, _T_2042
node _T_2043 = bits(_WIRE_151, 9, 9)
connect _WIRE_150.hr, _T_2043
node _T_2044 = bits(_WIRE_151, 10, 10)
connect _WIRE_150.hx, _T_2044
node _T_2045 = bits(_WIRE_151, 11, 11)
connect _WIRE_150.hw, _T_2045
node _T_2046 = bits(_WIRE_151, 12, 12)
connect _WIRE_150.sr, _T_2046
node _T_2047 = bits(_WIRE_151, 13, 13)
connect _WIRE_150.sx, _T_2047
node _T_2048 = bits(_WIRE_151, 14, 14)
connect _WIRE_150.sw, _T_2048
node _T_2049 = bits(_WIRE_151, 15, 15)
connect _WIRE_150.gf, _T_2049
node _T_2050 = bits(_WIRE_151, 16, 16)
connect _WIRE_150.pf, _T_2050
node _T_2051 = bits(_WIRE_151, 17, 17)
connect _WIRE_150.ae_stage2, _T_2051
node _T_2052 = bits(_WIRE_151, 18, 18)
connect _WIRE_150.ae_final, _T_2052
node _T_2053 = bits(_WIRE_151, 19, 19)
connect _WIRE_150.ae_ptw, _T_2053
node _T_2054 = bits(_WIRE_151, 20, 20)
connect _WIRE_150.g, _T_2054
node _T_2055 = bits(_WIRE_151, 21, 21)
connect _WIRE_150.u, _T_2055
node _T_2056 = bits(_WIRE_151, 41, 22)
connect _WIRE_150.ppn, _T_2056
node _T_2057 = eq(sectored_entries[0][4].tag_v, hv_4)
node _T_2058 = eq(_WIRE_144.g, UInt<1>(0h0))
node _T_2059 = and(_T_2057, _T_2058)
when _T_2059 :
connect sectored_entries[0][4].valid[0], UInt<1>(0h0)
node _T_2060 = eq(sectored_entries[0][4].tag_v, hv_4)
node _T_2061 = eq(_WIRE_146.g, UInt<1>(0h0))
node _T_2062 = and(_T_2060, _T_2061)
when _T_2062 :
connect sectored_entries[0][4].valid[1], UInt<1>(0h0)
node _T_2063 = eq(sectored_entries[0][4].tag_v, hv_4)
node _T_2064 = eq(_WIRE_148.g, UInt<1>(0h0))
node _T_2065 = and(_T_2063, _T_2064)
when _T_2065 :
connect sectored_entries[0][4].valid[2], UInt<1>(0h0)
node _T_2066 = eq(sectored_entries[0][4].tag_v, hv_4)
node _T_2067 = eq(_WIRE_150.g, UInt<1>(0h0))
node _T_2068 = and(_T_2066, _T_2067)
when _T_2068 :
connect sectored_entries[0][4].valid[3], UInt<1>(0h0)
else :
node _T_2069 = or(hv_4, hg_4)
wire _WIRE_152 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_153 : UInt<42>
connect _WIRE_153, sectored_entries[0][4].data[0]
node _T_2070 = bits(_WIRE_153, 0, 0)
connect _WIRE_152.fragmented_superpage, _T_2070
node _T_2071 = bits(_WIRE_153, 1, 1)
connect _WIRE_152.c, _T_2071
node _T_2072 = bits(_WIRE_153, 2, 2)
connect _WIRE_152.eff, _T_2072
node _T_2073 = bits(_WIRE_153, 3, 3)
connect _WIRE_152.paa, _T_2073
node _T_2074 = bits(_WIRE_153, 4, 4)
connect _WIRE_152.pal, _T_2074
node _T_2075 = bits(_WIRE_153, 5, 5)
connect _WIRE_152.ppp, _T_2075
node _T_2076 = bits(_WIRE_153, 6, 6)
connect _WIRE_152.pr, _T_2076
node _T_2077 = bits(_WIRE_153, 7, 7)
connect _WIRE_152.px, _T_2077
node _T_2078 = bits(_WIRE_153, 8, 8)
connect _WIRE_152.pw, _T_2078
node _T_2079 = bits(_WIRE_153, 9, 9)
connect _WIRE_152.hr, _T_2079
node _T_2080 = bits(_WIRE_153, 10, 10)
connect _WIRE_152.hx, _T_2080
node _T_2081 = bits(_WIRE_153, 11, 11)
connect _WIRE_152.hw, _T_2081
node _T_2082 = bits(_WIRE_153, 12, 12)
connect _WIRE_152.sr, _T_2082
node _T_2083 = bits(_WIRE_153, 13, 13)
connect _WIRE_152.sx, _T_2083
node _T_2084 = bits(_WIRE_153, 14, 14)
connect _WIRE_152.sw, _T_2084
node _T_2085 = bits(_WIRE_153, 15, 15)
connect _WIRE_152.gf, _T_2085
node _T_2086 = bits(_WIRE_153, 16, 16)
connect _WIRE_152.pf, _T_2086
node _T_2087 = bits(_WIRE_153, 17, 17)
connect _WIRE_152.ae_stage2, _T_2087
node _T_2088 = bits(_WIRE_153, 18, 18)
connect _WIRE_152.ae_final, _T_2088
node _T_2089 = bits(_WIRE_153, 19, 19)
connect _WIRE_152.ae_ptw, _T_2089
node _T_2090 = bits(_WIRE_153, 20, 20)
connect _WIRE_152.g, _T_2090
node _T_2091 = bits(_WIRE_153, 21, 21)
connect _WIRE_152.u, _T_2091
node _T_2092 = bits(_WIRE_153, 41, 22)
connect _WIRE_152.ppn, _T_2092
wire _WIRE_154 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_155 : UInt<42>
connect _WIRE_155, sectored_entries[0][4].data[1]
node _T_2093 = bits(_WIRE_155, 0, 0)
connect _WIRE_154.fragmented_superpage, _T_2093
node _T_2094 = bits(_WIRE_155, 1, 1)
connect _WIRE_154.c, _T_2094
node _T_2095 = bits(_WIRE_155, 2, 2)
connect _WIRE_154.eff, _T_2095
node _T_2096 = bits(_WIRE_155, 3, 3)
connect _WIRE_154.paa, _T_2096
node _T_2097 = bits(_WIRE_155, 4, 4)
connect _WIRE_154.pal, _T_2097
node _T_2098 = bits(_WIRE_155, 5, 5)
connect _WIRE_154.ppp, _T_2098
node _T_2099 = bits(_WIRE_155, 6, 6)
connect _WIRE_154.pr, _T_2099
node _T_2100 = bits(_WIRE_155, 7, 7)
connect _WIRE_154.px, _T_2100
node _T_2101 = bits(_WIRE_155, 8, 8)
connect _WIRE_154.pw, _T_2101
node _T_2102 = bits(_WIRE_155, 9, 9)
connect _WIRE_154.hr, _T_2102
node _T_2103 = bits(_WIRE_155, 10, 10)
connect _WIRE_154.hx, _T_2103
node _T_2104 = bits(_WIRE_155, 11, 11)
connect _WIRE_154.hw, _T_2104
node _T_2105 = bits(_WIRE_155, 12, 12)
connect _WIRE_154.sr, _T_2105
node _T_2106 = bits(_WIRE_155, 13, 13)
connect _WIRE_154.sx, _T_2106
node _T_2107 = bits(_WIRE_155, 14, 14)
connect _WIRE_154.sw, _T_2107
node _T_2108 = bits(_WIRE_155, 15, 15)
connect _WIRE_154.gf, _T_2108
node _T_2109 = bits(_WIRE_155, 16, 16)
connect _WIRE_154.pf, _T_2109
node _T_2110 = bits(_WIRE_155, 17, 17)
connect _WIRE_154.ae_stage2, _T_2110
node _T_2111 = bits(_WIRE_155, 18, 18)
connect _WIRE_154.ae_final, _T_2111
node _T_2112 = bits(_WIRE_155, 19, 19)
connect _WIRE_154.ae_ptw, _T_2112
node _T_2113 = bits(_WIRE_155, 20, 20)
connect _WIRE_154.g, _T_2113
node _T_2114 = bits(_WIRE_155, 21, 21)
connect _WIRE_154.u, _T_2114
node _T_2115 = bits(_WIRE_155, 41, 22)
connect _WIRE_154.ppn, _T_2115
wire _WIRE_156 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_157 : UInt<42>
connect _WIRE_157, sectored_entries[0][4].data[2]
node _T_2116 = bits(_WIRE_157, 0, 0)
connect _WIRE_156.fragmented_superpage, _T_2116
node _T_2117 = bits(_WIRE_157, 1, 1)
connect _WIRE_156.c, _T_2117
node _T_2118 = bits(_WIRE_157, 2, 2)
connect _WIRE_156.eff, _T_2118
node _T_2119 = bits(_WIRE_157, 3, 3)
connect _WIRE_156.paa, _T_2119
node _T_2120 = bits(_WIRE_157, 4, 4)
connect _WIRE_156.pal, _T_2120
node _T_2121 = bits(_WIRE_157, 5, 5)
connect _WIRE_156.ppp, _T_2121
node _T_2122 = bits(_WIRE_157, 6, 6)
connect _WIRE_156.pr, _T_2122
node _T_2123 = bits(_WIRE_157, 7, 7)
connect _WIRE_156.px, _T_2123
node _T_2124 = bits(_WIRE_157, 8, 8)
connect _WIRE_156.pw, _T_2124
node _T_2125 = bits(_WIRE_157, 9, 9)
connect _WIRE_156.hr, _T_2125
node _T_2126 = bits(_WIRE_157, 10, 10)
connect _WIRE_156.hx, _T_2126
node _T_2127 = bits(_WIRE_157, 11, 11)
connect _WIRE_156.hw, _T_2127
node _T_2128 = bits(_WIRE_157, 12, 12)
connect _WIRE_156.sr, _T_2128
node _T_2129 = bits(_WIRE_157, 13, 13)
connect _WIRE_156.sx, _T_2129
node _T_2130 = bits(_WIRE_157, 14, 14)
connect _WIRE_156.sw, _T_2130
node _T_2131 = bits(_WIRE_157, 15, 15)
connect _WIRE_156.gf, _T_2131
node _T_2132 = bits(_WIRE_157, 16, 16)
connect _WIRE_156.pf, _T_2132
node _T_2133 = bits(_WIRE_157, 17, 17)
connect _WIRE_156.ae_stage2, _T_2133
node _T_2134 = bits(_WIRE_157, 18, 18)
connect _WIRE_156.ae_final, _T_2134
node _T_2135 = bits(_WIRE_157, 19, 19)
connect _WIRE_156.ae_ptw, _T_2135
node _T_2136 = bits(_WIRE_157, 20, 20)
connect _WIRE_156.g, _T_2136
node _T_2137 = bits(_WIRE_157, 21, 21)
connect _WIRE_156.u, _T_2137
node _T_2138 = bits(_WIRE_157, 41, 22)
connect _WIRE_156.ppn, _T_2138
wire _WIRE_158 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_159 : UInt<42>
connect _WIRE_159, sectored_entries[0][4].data[3]
node _T_2139 = bits(_WIRE_159, 0, 0)
connect _WIRE_158.fragmented_superpage, _T_2139
node _T_2140 = bits(_WIRE_159, 1, 1)
connect _WIRE_158.c, _T_2140
node _T_2141 = bits(_WIRE_159, 2, 2)
connect _WIRE_158.eff, _T_2141
node _T_2142 = bits(_WIRE_159, 3, 3)
connect _WIRE_158.paa, _T_2142
node _T_2143 = bits(_WIRE_159, 4, 4)
connect _WIRE_158.pal, _T_2143
node _T_2144 = bits(_WIRE_159, 5, 5)
connect _WIRE_158.ppp, _T_2144
node _T_2145 = bits(_WIRE_159, 6, 6)
connect _WIRE_158.pr, _T_2145
node _T_2146 = bits(_WIRE_159, 7, 7)
connect _WIRE_158.px, _T_2146
node _T_2147 = bits(_WIRE_159, 8, 8)
connect _WIRE_158.pw, _T_2147
node _T_2148 = bits(_WIRE_159, 9, 9)
connect _WIRE_158.hr, _T_2148
node _T_2149 = bits(_WIRE_159, 10, 10)
connect _WIRE_158.hx, _T_2149
node _T_2150 = bits(_WIRE_159, 11, 11)
connect _WIRE_158.hw, _T_2150
node _T_2151 = bits(_WIRE_159, 12, 12)
connect _WIRE_158.sr, _T_2151
node _T_2152 = bits(_WIRE_159, 13, 13)
connect _WIRE_158.sx, _T_2152
node _T_2153 = bits(_WIRE_159, 14, 14)
connect _WIRE_158.sw, _T_2153
node _T_2154 = bits(_WIRE_159, 15, 15)
connect _WIRE_158.gf, _T_2154
node _T_2155 = bits(_WIRE_159, 16, 16)
connect _WIRE_158.pf, _T_2155
node _T_2156 = bits(_WIRE_159, 17, 17)
connect _WIRE_158.ae_stage2, _T_2156
node _T_2157 = bits(_WIRE_159, 18, 18)
connect _WIRE_158.ae_final, _T_2157
node _T_2158 = bits(_WIRE_159, 19, 19)
connect _WIRE_158.ae_ptw, _T_2158
node _T_2159 = bits(_WIRE_159, 20, 20)
connect _WIRE_158.g, _T_2159
node _T_2160 = bits(_WIRE_159, 21, 21)
connect _WIRE_158.u, _T_2160
node _T_2161 = bits(_WIRE_159, 41, 22)
connect _WIRE_158.ppn, _T_2161
node _T_2162 = eq(sectored_entries[0][4].tag_v, _T_2069)
when _T_2162 :
connect sectored_entries[0][4].valid[0], UInt<1>(0h0)
node _T_2163 = eq(sectored_entries[0][4].tag_v, _T_2069)
when _T_2163 :
connect sectored_entries[0][4].valid[1], UInt<1>(0h0)
node _T_2164 = eq(sectored_entries[0][4].tag_v, _T_2069)
when _T_2164 :
connect sectored_entries[0][4].valid[2], UInt<1>(0h0)
node _T_2165 = eq(sectored_entries[0][4].tag_v, _T_2069)
when _T_2165 :
connect sectored_entries[0][4].valid[3], UInt<1>(0h0)
node hv_5 = and(UInt<1>(0h0), io.sfence.bits.hv)
node hg_5 = and(UInt<1>(0h0), io.sfence.bits.hg)
node _T_2166 = eq(hg_5, UInt<1>(0h0))
node _T_2167 = and(_T_2166, io.sfence.bits.rs1)
when _T_2167 :
node _T_2168 = xor(sectored_entries[0][5].tag_vpn, vpn)
node _T_2169 = shr(_T_2168, 2)
node _T_2170 = eq(_T_2169, UInt<1>(0h0))
node _T_2171 = eq(sectored_entries[0][5].tag_v, hv_5)
node _T_2172 = and(_T_2170, _T_2171)
when _T_2172 :
wire _WIRE_160 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_161 : UInt<42>
connect _WIRE_161, sectored_entries[0][5].data[0]
node _T_2173 = bits(_WIRE_161, 0, 0)
connect _WIRE_160.fragmented_superpage, _T_2173
node _T_2174 = bits(_WIRE_161, 1, 1)
connect _WIRE_160.c, _T_2174
node _T_2175 = bits(_WIRE_161, 2, 2)
connect _WIRE_160.eff, _T_2175
node _T_2176 = bits(_WIRE_161, 3, 3)
connect _WIRE_160.paa, _T_2176
node _T_2177 = bits(_WIRE_161, 4, 4)
connect _WIRE_160.pal, _T_2177
node _T_2178 = bits(_WIRE_161, 5, 5)
connect _WIRE_160.ppp, _T_2178
node _T_2179 = bits(_WIRE_161, 6, 6)
connect _WIRE_160.pr, _T_2179
node _T_2180 = bits(_WIRE_161, 7, 7)
connect _WIRE_160.px, _T_2180
node _T_2181 = bits(_WIRE_161, 8, 8)
connect _WIRE_160.pw, _T_2181
node _T_2182 = bits(_WIRE_161, 9, 9)
connect _WIRE_160.hr, _T_2182
node _T_2183 = bits(_WIRE_161, 10, 10)
connect _WIRE_160.hx, _T_2183
node _T_2184 = bits(_WIRE_161, 11, 11)
connect _WIRE_160.hw, _T_2184
node _T_2185 = bits(_WIRE_161, 12, 12)
connect _WIRE_160.sr, _T_2185
node _T_2186 = bits(_WIRE_161, 13, 13)
connect _WIRE_160.sx, _T_2186
node _T_2187 = bits(_WIRE_161, 14, 14)
connect _WIRE_160.sw, _T_2187
node _T_2188 = bits(_WIRE_161, 15, 15)
connect _WIRE_160.gf, _T_2188
node _T_2189 = bits(_WIRE_161, 16, 16)
connect _WIRE_160.pf, _T_2189
node _T_2190 = bits(_WIRE_161, 17, 17)
connect _WIRE_160.ae_stage2, _T_2190
node _T_2191 = bits(_WIRE_161, 18, 18)
connect _WIRE_160.ae_final, _T_2191
node _T_2192 = bits(_WIRE_161, 19, 19)
connect _WIRE_160.ae_ptw, _T_2192
node _T_2193 = bits(_WIRE_161, 20, 20)
connect _WIRE_160.g, _T_2193
node _T_2194 = bits(_WIRE_161, 21, 21)
connect _WIRE_160.u, _T_2194
node _T_2195 = bits(_WIRE_161, 41, 22)
connect _WIRE_160.ppn, _T_2195
wire _WIRE_162 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_163 : UInt<42>
connect _WIRE_163, sectored_entries[0][5].data[1]
node _T_2196 = bits(_WIRE_163, 0, 0)
connect _WIRE_162.fragmented_superpage, _T_2196
node _T_2197 = bits(_WIRE_163, 1, 1)
connect _WIRE_162.c, _T_2197
node _T_2198 = bits(_WIRE_163, 2, 2)
connect _WIRE_162.eff, _T_2198
node _T_2199 = bits(_WIRE_163, 3, 3)
connect _WIRE_162.paa, _T_2199
node _T_2200 = bits(_WIRE_163, 4, 4)
connect _WIRE_162.pal, _T_2200
node _T_2201 = bits(_WIRE_163, 5, 5)
connect _WIRE_162.ppp, _T_2201
node _T_2202 = bits(_WIRE_163, 6, 6)
connect _WIRE_162.pr, _T_2202
node _T_2203 = bits(_WIRE_163, 7, 7)
connect _WIRE_162.px, _T_2203
node _T_2204 = bits(_WIRE_163, 8, 8)
connect _WIRE_162.pw, _T_2204
node _T_2205 = bits(_WIRE_163, 9, 9)
connect _WIRE_162.hr, _T_2205
node _T_2206 = bits(_WIRE_163, 10, 10)
connect _WIRE_162.hx, _T_2206
node _T_2207 = bits(_WIRE_163, 11, 11)
connect _WIRE_162.hw, _T_2207
node _T_2208 = bits(_WIRE_163, 12, 12)
connect _WIRE_162.sr, _T_2208
node _T_2209 = bits(_WIRE_163, 13, 13)
connect _WIRE_162.sx, _T_2209
node _T_2210 = bits(_WIRE_163, 14, 14)
connect _WIRE_162.sw, _T_2210
node _T_2211 = bits(_WIRE_163, 15, 15)
connect _WIRE_162.gf, _T_2211
node _T_2212 = bits(_WIRE_163, 16, 16)
connect _WIRE_162.pf, _T_2212
node _T_2213 = bits(_WIRE_163, 17, 17)
connect _WIRE_162.ae_stage2, _T_2213
node _T_2214 = bits(_WIRE_163, 18, 18)
connect _WIRE_162.ae_final, _T_2214
node _T_2215 = bits(_WIRE_163, 19, 19)
connect _WIRE_162.ae_ptw, _T_2215
node _T_2216 = bits(_WIRE_163, 20, 20)
connect _WIRE_162.g, _T_2216
node _T_2217 = bits(_WIRE_163, 21, 21)
connect _WIRE_162.u, _T_2217
node _T_2218 = bits(_WIRE_163, 41, 22)
connect _WIRE_162.ppn, _T_2218
wire _WIRE_164 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_165 : UInt<42>
connect _WIRE_165, sectored_entries[0][5].data[2]
node _T_2219 = bits(_WIRE_165, 0, 0)
connect _WIRE_164.fragmented_superpage, _T_2219
node _T_2220 = bits(_WIRE_165, 1, 1)
connect _WIRE_164.c, _T_2220
node _T_2221 = bits(_WIRE_165, 2, 2)
connect _WIRE_164.eff, _T_2221
node _T_2222 = bits(_WIRE_165, 3, 3)
connect _WIRE_164.paa, _T_2222
node _T_2223 = bits(_WIRE_165, 4, 4)
connect _WIRE_164.pal, _T_2223
node _T_2224 = bits(_WIRE_165, 5, 5)
connect _WIRE_164.ppp, _T_2224
node _T_2225 = bits(_WIRE_165, 6, 6)
connect _WIRE_164.pr, _T_2225
node _T_2226 = bits(_WIRE_165, 7, 7)
connect _WIRE_164.px, _T_2226
node _T_2227 = bits(_WIRE_165, 8, 8)
connect _WIRE_164.pw, _T_2227
node _T_2228 = bits(_WIRE_165, 9, 9)
connect _WIRE_164.hr, _T_2228
node _T_2229 = bits(_WIRE_165, 10, 10)
connect _WIRE_164.hx, _T_2229
node _T_2230 = bits(_WIRE_165, 11, 11)
connect _WIRE_164.hw, _T_2230
node _T_2231 = bits(_WIRE_165, 12, 12)
connect _WIRE_164.sr, _T_2231
node _T_2232 = bits(_WIRE_165, 13, 13)
connect _WIRE_164.sx, _T_2232
node _T_2233 = bits(_WIRE_165, 14, 14)
connect _WIRE_164.sw, _T_2233
node _T_2234 = bits(_WIRE_165, 15, 15)
connect _WIRE_164.gf, _T_2234
node _T_2235 = bits(_WIRE_165, 16, 16)
connect _WIRE_164.pf, _T_2235
node _T_2236 = bits(_WIRE_165, 17, 17)
connect _WIRE_164.ae_stage2, _T_2236
node _T_2237 = bits(_WIRE_165, 18, 18)
connect _WIRE_164.ae_final, _T_2237
node _T_2238 = bits(_WIRE_165, 19, 19)
connect _WIRE_164.ae_ptw, _T_2238
node _T_2239 = bits(_WIRE_165, 20, 20)
connect _WIRE_164.g, _T_2239
node _T_2240 = bits(_WIRE_165, 21, 21)
connect _WIRE_164.u, _T_2240
node _T_2241 = bits(_WIRE_165, 41, 22)
connect _WIRE_164.ppn, _T_2241
wire _WIRE_166 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_167 : UInt<42>
connect _WIRE_167, sectored_entries[0][5].data[3]
node _T_2242 = bits(_WIRE_167, 0, 0)
connect _WIRE_166.fragmented_superpage, _T_2242
node _T_2243 = bits(_WIRE_167, 1, 1)
connect _WIRE_166.c, _T_2243
node _T_2244 = bits(_WIRE_167, 2, 2)
connect _WIRE_166.eff, _T_2244
node _T_2245 = bits(_WIRE_167, 3, 3)
connect _WIRE_166.paa, _T_2245
node _T_2246 = bits(_WIRE_167, 4, 4)
connect _WIRE_166.pal, _T_2246
node _T_2247 = bits(_WIRE_167, 5, 5)
connect _WIRE_166.ppp, _T_2247
node _T_2248 = bits(_WIRE_167, 6, 6)
connect _WIRE_166.pr, _T_2248
node _T_2249 = bits(_WIRE_167, 7, 7)
connect _WIRE_166.px, _T_2249
node _T_2250 = bits(_WIRE_167, 8, 8)
connect _WIRE_166.pw, _T_2250
node _T_2251 = bits(_WIRE_167, 9, 9)
connect _WIRE_166.hr, _T_2251
node _T_2252 = bits(_WIRE_167, 10, 10)
connect _WIRE_166.hx, _T_2252
node _T_2253 = bits(_WIRE_167, 11, 11)
connect _WIRE_166.hw, _T_2253
node _T_2254 = bits(_WIRE_167, 12, 12)
connect _WIRE_166.sr, _T_2254
node _T_2255 = bits(_WIRE_167, 13, 13)
connect _WIRE_166.sx, _T_2255
node _T_2256 = bits(_WIRE_167, 14, 14)
connect _WIRE_166.sw, _T_2256
node _T_2257 = bits(_WIRE_167, 15, 15)
connect _WIRE_166.gf, _T_2257
node _T_2258 = bits(_WIRE_167, 16, 16)
connect _WIRE_166.pf, _T_2258
node _T_2259 = bits(_WIRE_167, 17, 17)
connect _WIRE_166.ae_stage2, _T_2259
node _T_2260 = bits(_WIRE_167, 18, 18)
connect _WIRE_166.ae_final, _T_2260
node _T_2261 = bits(_WIRE_167, 19, 19)
connect _WIRE_166.ae_ptw, _T_2261
node _T_2262 = bits(_WIRE_167, 20, 20)
connect _WIRE_166.g, _T_2262
node _T_2263 = bits(_WIRE_167, 21, 21)
connect _WIRE_166.u, _T_2263
node _T_2264 = bits(_WIRE_167, 41, 22)
connect _WIRE_166.ppn, _T_2264
node _T_2265 = eq(sectored_entries[0][5].tag_v, hv_5)
node _T_2266 = bits(vpn, 1, 0)
node _T_2267 = eq(UInt<1>(0h0), _T_2266)
node _T_2268 = and(_T_2265, _T_2267)
when _T_2268 :
connect sectored_entries[0][5].valid[0], UInt<1>(0h0)
node _T_2269 = eq(sectored_entries[0][5].tag_v, hv_5)
node _T_2270 = bits(vpn, 1, 0)
node _T_2271 = eq(UInt<1>(0h1), _T_2270)
node _T_2272 = and(_T_2269, _T_2271)
when _T_2272 :
connect sectored_entries[0][5].valid[1], UInt<1>(0h0)
node _T_2273 = eq(sectored_entries[0][5].tag_v, hv_5)
node _T_2274 = bits(vpn, 1, 0)
node _T_2275 = eq(UInt<2>(0h2), _T_2274)
node _T_2276 = and(_T_2273, _T_2275)
when _T_2276 :
connect sectored_entries[0][5].valid[2], UInt<1>(0h0)
node _T_2277 = eq(sectored_entries[0][5].tag_v, hv_5)
node _T_2278 = bits(vpn, 1, 0)
node _T_2279 = eq(UInt<2>(0h3), _T_2278)
node _T_2280 = and(_T_2277, _T_2279)
when _T_2280 :
connect sectored_entries[0][5].valid[3], UInt<1>(0h0)
node _T_2281 = xor(sectored_entries[0][5].tag_vpn, vpn)
node _T_2282 = shr(_T_2281, 18)
node _T_2283 = eq(_T_2282, UInt<1>(0h0))
when _T_2283 :
wire _WIRE_168 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_169 : UInt<42>
connect _WIRE_169, sectored_entries[0][5].data[0]
node _T_2284 = bits(_WIRE_169, 0, 0)
connect _WIRE_168.fragmented_superpage, _T_2284
node _T_2285 = bits(_WIRE_169, 1, 1)
connect _WIRE_168.c, _T_2285
node _T_2286 = bits(_WIRE_169, 2, 2)
connect _WIRE_168.eff, _T_2286
node _T_2287 = bits(_WIRE_169, 3, 3)
connect _WIRE_168.paa, _T_2287
node _T_2288 = bits(_WIRE_169, 4, 4)
connect _WIRE_168.pal, _T_2288
node _T_2289 = bits(_WIRE_169, 5, 5)
connect _WIRE_168.ppp, _T_2289
node _T_2290 = bits(_WIRE_169, 6, 6)
connect _WIRE_168.pr, _T_2290
node _T_2291 = bits(_WIRE_169, 7, 7)
connect _WIRE_168.px, _T_2291
node _T_2292 = bits(_WIRE_169, 8, 8)
connect _WIRE_168.pw, _T_2292
node _T_2293 = bits(_WIRE_169, 9, 9)
connect _WIRE_168.hr, _T_2293
node _T_2294 = bits(_WIRE_169, 10, 10)
connect _WIRE_168.hx, _T_2294
node _T_2295 = bits(_WIRE_169, 11, 11)
connect _WIRE_168.hw, _T_2295
node _T_2296 = bits(_WIRE_169, 12, 12)
connect _WIRE_168.sr, _T_2296
node _T_2297 = bits(_WIRE_169, 13, 13)
connect _WIRE_168.sx, _T_2297
node _T_2298 = bits(_WIRE_169, 14, 14)
connect _WIRE_168.sw, _T_2298
node _T_2299 = bits(_WIRE_169, 15, 15)
connect _WIRE_168.gf, _T_2299
node _T_2300 = bits(_WIRE_169, 16, 16)
connect _WIRE_168.pf, _T_2300
node _T_2301 = bits(_WIRE_169, 17, 17)
connect _WIRE_168.ae_stage2, _T_2301
node _T_2302 = bits(_WIRE_169, 18, 18)
connect _WIRE_168.ae_final, _T_2302
node _T_2303 = bits(_WIRE_169, 19, 19)
connect _WIRE_168.ae_ptw, _T_2303
node _T_2304 = bits(_WIRE_169, 20, 20)
connect _WIRE_168.g, _T_2304
node _T_2305 = bits(_WIRE_169, 21, 21)
connect _WIRE_168.u, _T_2305
node _T_2306 = bits(_WIRE_169, 41, 22)
connect _WIRE_168.ppn, _T_2306
wire _WIRE_170 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_171 : UInt<42>
connect _WIRE_171, sectored_entries[0][5].data[1]
node _T_2307 = bits(_WIRE_171, 0, 0)
connect _WIRE_170.fragmented_superpage, _T_2307
node _T_2308 = bits(_WIRE_171, 1, 1)
connect _WIRE_170.c, _T_2308
node _T_2309 = bits(_WIRE_171, 2, 2)
connect _WIRE_170.eff, _T_2309
node _T_2310 = bits(_WIRE_171, 3, 3)
connect _WIRE_170.paa, _T_2310
node _T_2311 = bits(_WIRE_171, 4, 4)
connect _WIRE_170.pal, _T_2311
node _T_2312 = bits(_WIRE_171, 5, 5)
connect _WIRE_170.ppp, _T_2312
node _T_2313 = bits(_WIRE_171, 6, 6)
connect _WIRE_170.pr, _T_2313
node _T_2314 = bits(_WIRE_171, 7, 7)
connect _WIRE_170.px, _T_2314
node _T_2315 = bits(_WIRE_171, 8, 8)
connect _WIRE_170.pw, _T_2315
node _T_2316 = bits(_WIRE_171, 9, 9)
connect _WIRE_170.hr, _T_2316
node _T_2317 = bits(_WIRE_171, 10, 10)
connect _WIRE_170.hx, _T_2317
node _T_2318 = bits(_WIRE_171, 11, 11)
connect _WIRE_170.hw, _T_2318
node _T_2319 = bits(_WIRE_171, 12, 12)
connect _WIRE_170.sr, _T_2319
node _T_2320 = bits(_WIRE_171, 13, 13)
connect _WIRE_170.sx, _T_2320
node _T_2321 = bits(_WIRE_171, 14, 14)
connect _WIRE_170.sw, _T_2321
node _T_2322 = bits(_WIRE_171, 15, 15)
connect _WIRE_170.gf, _T_2322
node _T_2323 = bits(_WIRE_171, 16, 16)
connect _WIRE_170.pf, _T_2323
node _T_2324 = bits(_WIRE_171, 17, 17)
connect _WIRE_170.ae_stage2, _T_2324
node _T_2325 = bits(_WIRE_171, 18, 18)
connect _WIRE_170.ae_final, _T_2325
node _T_2326 = bits(_WIRE_171, 19, 19)
connect _WIRE_170.ae_ptw, _T_2326
node _T_2327 = bits(_WIRE_171, 20, 20)
connect _WIRE_170.g, _T_2327
node _T_2328 = bits(_WIRE_171, 21, 21)
connect _WIRE_170.u, _T_2328
node _T_2329 = bits(_WIRE_171, 41, 22)
connect _WIRE_170.ppn, _T_2329
wire _WIRE_172 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_173 : UInt<42>
connect _WIRE_173, sectored_entries[0][5].data[2]
node _T_2330 = bits(_WIRE_173, 0, 0)
connect _WIRE_172.fragmented_superpage, _T_2330
node _T_2331 = bits(_WIRE_173, 1, 1)
connect _WIRE_172.c, _T_2331
node _T_2332 = bits(_WIRE_173, 2, 2)
connect _WIRE_172.eff, _T_2332
node _T_2333 = bits(_WIRE_173, 3, 3)
connect _WIRE_172.paa, _T_2333
node _T_2334 = bits(_WIRE_173, 4, 4)
connect _WIRE_172.pal, _T_2334
node _T_2335 = bits(_WIRE_173, 5, 5)
connect _WIRE_172.ppp, _T_2335
node _T_2336 = bits(_WIRE_173, 6, 6)
connect _WIRE_172.pr, _T_2336
node _T_2337 = bits(_WIRE_173, 7, 7)
connect _WIRE_172.px, _T_2337
node _T_2338 = bits(_WIRE_173, 8, 8)
connect _WIRE_172.pw, _T_2338
node _T_2339 = bits(_WIRE_173, 9, 9)
connect _WIRE_172.hr, _T_2339
node _T_2340 = bits(_WIRE_173, 10, 10)
connect _WIRE_172.hx, _T_2340
node _T_2341 = bits(_WIRE_173, 11, 11)
connect _WIRE_172.hw, _T_2341
node _T_2342 = bits(_WIRE_173, 12, 12)
connect _WIRE_172.sr, _T_2342
node _T_2343 = bits(_WIRE_173, 13, 13)
connect _WIRE_172.sx, _T_2343
node _T_2344 = bits(_WIRE_173, 14, 14)
connect _WIRE_172.sw, _T_2344
node _T_2345 = bits(_WIRE_173, 15, 15)
connect _WIRE_172.gf, _T_2345
node _T_2346 = bits(_WIRE_173, 16, 16)
connect _WIRE_172.pf, _T_2346
node _T_2347 = bits(_WIRE_173, 17, 17)
connect _WIRE_172.ae_stage2, _T_2347
node _T_2348 = bits(_WIRE_173, 18, 18)
connect _WIRE_172.ae_final, _T_2348
node _T_2349 = bits(_WIRE_173, 19, 19)
connect _WIRE_172.ae_ptw, _T_2349
node _T_2350 = bits(_WIRE_173, 20, 20)
connect _WIRE_172.g, _T_2350
node _T_2351 = bits(_WIRE_173, 21, 21)
connect _WIRE_172.u, _T_2351
node _T_2352 = bits(_WIRE_173, 41, 22)
connect _WIRE_172.ppn, _T_2352
wire _WIRE_174 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_175 : UInt<42>
connect _WIRE_175, sectored_entries[0][5].data[3]
node _T_2353 = bits(_WIRE_175, 0, 0)
connect _WIRE_174.fragmented_superpage, _T_2353
node _T_2354 = bits(_WIRE_175, 1, 1)
connect _WIRE_174.c, _T_2354
node _T_2355 = bits(_WIRE_175, 2, 2)
connect _WIRE_174.eff, _T_2355
node _T_2356 = bits(_WIRE_175, 3, 3)
connect _WIRE_174.paa, _T_2356
node _T_2357 = bits(_WIRE_175, 4, 4)
connect _WIRE_174.pal, _T_2357
node _T_2358 = bits(_WIRE_175, 5, 5)
connect _WIRE_174.ppp, _T_2358
node _T_2359 = bits(_WIRE_175, 6, 6)
connect _WIRE_174.pr, _T_2359
node _T_2360 = bits(_WIRE_175, 7, 7)
connect _WIRE_174.px, _T_2360
node _T_2361 = bits(_WIRE_175, 8, 8)
connect _WIRE_174.pw, _T_2361
node _T_2362 = bits(_WIRE_175, 9, 9)
connect _WIRE_174.hr, _T_2362
node _T_2363 = bits(_WIRE_175, 10, 10)
connect _WIRE_174.hx, _T_2363
node _T_2364 = bits(_WIRE_175, 11, 11)
connect _WIRE_174.hw, _T_2364
node _T_2365 = bits(_WIRE_175, 12, 12)
connect _WIRE_174.sr, _T_2365
node _T_2366 = bits(_WIRE_175, 13, 13)
connect _WIRE_174.sx, _T_2366
node _T_2367 = bits(_WIRE_175, 14, 14)
connect _WIRE_174.sw, _T_2367
node _T_2368 = bits(_WIRE_175, 15, 15)
connect _WIRE_174.gf, _T_2368
node _T_2369 = bits(_WIRE_175, 16, 16)
connect _WIRE_174.pf, _T_2369
node _T_2370 = bits(_WIRE_175, 17, 17)
connect _WIRE_174.ae_stage2, _T_2370
node _T_2371 = bits(_WIRE_175, 18, 18)
connect _WIRE_174.ae_final, _T_2371
node _T_2372 = bits(_WIRE_175, 19, 19)
connect _WIRE_174.ae_ptw, _T_2372
node _T_2373 = bits(_WIRE_175, 20, 20)
connect _WIRE_174.g, _T_2373
node _T_2374 = bits(_WIRE_175, 21, 21)
connect _WIRE_174.u, _T_2374
node _T_2375 = bits(_WIRE_175, 41, 22)
connect _WIRE_174.ppn, _T_2375
node _T_2376 = eq(sectored_entries[0][5].tag_v, hv_5)
node _T_2377 = and(_T_2376, _WIRE_168.fragmented_superpage)
when _T_2377 :
connect sectored_entries[0][5].valid[0], UInt<1>(0h0)
node _T_2378 = eq(sectored_entries[0][5].tag_v, hv_5)
node _T_2379 = and(_T_2378, _WIRE_170.fragmented_superpage)
when _T_2379 :
connect sectored_entries[0][5].valid[1], UInt<1>(0h0)
node _T_2380 = eq(sectored_entries[0][5].tag_v, hv_5)
node _T_2381 = and(_T_2380, _WIRE_172.fragmented_superpage)
when _T_2381 :
connect sectored_entries[0][5].valid[2], UInt<1>(0h0)
node _T_2382 = eq(sectored_entries[0][5].tag_v, hv_5)
node _T_2383 = and(_T_2382, _WIRE_174.fragmented_superpage)
when _T_2383 :
connect sectored_entries[0][5].valid[3], UInt<1>(0h0)
else :
node _T_2384 = eq(hg_5, UInt<1>(0h0))
node _T_2385 = and(_T_2384, io.sfence.bits.rs2)
when _T_2385 :
wire _WIRE_176 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_177 : UInt<42>
connect _WIRE_177, sectored_entries[0][5].data[0]
node _T_2386 = bits(_WIRE_177, 0, 0)
connect _WIRE_176.fragmented_superpage, _T_2386
node _T_2387 = bits(_WIRE_177, 1, 1)
connect _WIRE_176.c, _T_2387
node _T_2388 = bits(_WIRE_177, 2, 2)
connect _WIRE_176.eff, _T_2388
node _T_2389 = bits(_WIRE_177, 3, 3)
connect _WIRE_176.paa, _T_2389
node _T_2390 = bits(_WIRE_177, 4, 4)
connect _WIRE_176.pal, _T_2390
node _T_2391 = bits(_WIRE_177, 5, 5)
connect _WIRE_176.ppp, _T_2391
node _T_2392 = bits(_WIRE_177, 6, 6)
connect _WIRE_176.pr, _T_2392
node _T_2393 = bits(_WIRE_177, 7, 7)
connect _WIRE_176.px, _T_2393
node _T_2394 = bits(_WIRE_177, 8, 8)
connect _WIRE_176.pw, _T_2394
node _T_2395 = bits(_WIRE_177, 9, 9)
connect _WIRE_176.hr, _T_2395
node _T_2396 = bits(_WIRE_177, 10, 10)
connect _WIRE_176.hx, _T_2396
node _T_2397 = bits(_WIRE_177, 11, 11)
connect _WIRE_176.hw, _T_2397
node _T_2398 = bits(_WIRE_177, 12, 12)
connect _WIRE_176.sr, _T_2398
node _T_2399 = bits(_WIRE_177, 13, 13)
connect _WIRE_176.sx, _T_2399
node _T_2400 = bits(_WIRE_177, 14, 14)
connect _WIRE_176.sw, _T_2400
node _T_2401 = bits(_WIRE_177, 15, 15)
connect _WIRE_176.gf, _T_2401
node _T_2402 = bits(_WIRE_177, 16, 16)
connect _WIRE_176.pf, _T_2402
node _T_2403 = bits(_WIRE_177, 17, 17)
connect _WIRE_176.ae_stage2, _T_2403
node _T_2404 = bits(_WIRE_177, 18, 18)
connect _WIRE_176.ae_final, _T_2404
node _T_2405 = bits(_WIRE_177, 19, 19)
connect _WIRE_176.ae_ptw, _T_2405
node _T_2406 = bits(_WIRE_177, 20, 20)
connect _WIRE_176.g, _T_2406
node _T_2407 = bits(_WIRE_177, 21, 21)
connect _WIRE_176.u, _T_2407
node _T_2408 = bits(_WIRE_177, 41, 22)
connect _WIRE_176.ppn, _T_2408
wire _WIRE_178 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_179 : UInt<42>
connect _WIRE_179, sectored_entries[0][5].data[1]
node _T_2409 = bits(_WIRE_179, 0, 0)
connect _WIRE_178.fragmented_superpage, _T_2409
node _T_2410 = bits(_WIRE_179, 1, 1)
connect _WIRE_178.c, _T_2410
node _T_2411 = bits(_WIRE_179, 2, 2)
connect _WIRE_178.eff, _T_2411
node _T_2412 = bits(_WIRE_179, 3, 3)
connect _WIRE_178.paa, _T_2412
node _T_2413 = bits(_WIRE_179, 4, 4)
connect _WIRE_178.pal, _T_2413
node _T_2414 = bits(_WIRE_179, 5, 5)
connect _WIRE_178.ppp, _T_2414
node _T_2415 = bits(_WIRE_179, 6, 6)
connect _WIRE_178.pr, _T_2415
node _T_2416 = bits(_WIRE_179, 7, 7)
connect _WIRE_178.px, _T_2416
node _T_2417 = bits(_WIRE_179, 8, 8)
connect _WIRE_178.pw, _T_2417
node _T_2418 = bits(_WIRE_179, 9, 9)
connect _WIRE_178.hr, _T_2418
node _T_2419 = bits(_WIRE_179, 10, 10)
connect _WIRE_178.hx, _T_2419
node _T_2420 = bits(_WIRE_179, 11, 11)
connect _WIRE_178.hw, _T_2420
node _T_2421 = bits(_WIRE_179, 12, 12)
connect _WIRE_178.sr, _T_2421
node _T_2422 = bits(_WIRE_179, 13, 13)
connect _WIRE_178.sx, _T_2422
node _T_2423 = bits(_WIRE_179, 14, 14)
connect _WIRE_178.sw, _T_2423
node _T_2424 = bits(_WIRE_179, 15, 15)
connect _WIRE_178.gf, _T_2424
node _T_2425 = bits(_WIRE_179, 16, 16)
connect _WIRE_178.pf, _T_2425
node _T_2426 = bits(_WIRE_179, 17, 17)
connect _WIRE_178.ae_stage2, _T_2426
node _T_2427 = bits(_WIRE_179, 18, 18)
connect _WIRE_178.ae_final, _T_2427
node _T_2428 = bits(_WIRE_179, 19, 19)
connect _WIRE_178.ae_ptw, _T_2428
node _T_2429 = bits(_WIRE_179, 20, 20)
connect _WIRE_178.g, _T_2429
node _T_2430 = bits(_WIRE_179, 21, 21)
connect _WIRE_178.u, _T_2430
node _T_2431 = bits(_WIRE_179, 41, 22)
connect _WIRE_178.ppn, _T_2431
wire _WIRE_180 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_181 : UInt<42>
connect _WIRE_181, sectored_entries[0][5].data[2]
node _T_2432 = bits(_WIRE_181, 0, 0)
connect _WIRE_180.fragmented_superpage, _T_2432
node _T_2433 = bits(_WIRE_181, 1, 1)
connect _WIRE_180.c, _T_2433
node _T_2434 = bits(_WIRE_181, 2, 2)
connect _WIRE_180.eff, _T_2434
node _T_2435 = bits(_WIRE_181, 3, 3)
connect _WIRE_180.paa, _T_2435
node _T_2436 = bits(_WIRE_181, 4, 4)
connect _WIRE_180.pal, _T_2436
node _T_2437 = bits(_WIRE_181, 5, 5)
connect _WIRE_180.ppp, _T_2437
node _T_2438 = bits(_WIRE_181, 6, 6)
connect _WIRE_180.pr, _T_2438
node _T_2439 = bits(_WIRE_181, 7, 7)
connect _WIRE_180.px, _T_2439
node _T_2440 = bits(_WIRE_181, 8, 8)
connect _WIRE_180.pw, _T_2440
node _T_2441 = bits(_WIRE_181, 9, 9)
connect _WIRE_180.hr, _T_2441
node _T_2442 = bits(_WIRE_181, 10, 10)
connect _WIRE_180.hx, _T_2442
node _T_2443 = bits(_WIRE_181, 11, 11)
connect _WIRE_180.hw, _T_2443
node _T_2444 = bits(_WIRE_181, 12, 12)
connect _WIRE_180.sr, _T_2444
node _T_2445 = bits(_WIRE_181, 13, 13)
connect _WIRE_180.sx, _T_2445
node _T_2446 = bits(_WIRE_181, 14, 14)
connect _WIRE_180.sw, _T_2446
node _T_2447 = bits(_WIRE_181, 15, 15)
connect _WIRE_180.gf, _T_2447
node _T_2448 = bits(_WIRE_181, 16, 16)
connect _WIRE_180.pf, _T_2448
node _T_2449 = bits(_WIRE_181, 17, 17)
connect _WIRE_180.ae_stage2, _T_2449
node _T_2450 = bits(_WIRE_181, 18, 18)
connect _WIRE_180.ae_final, _T_2450
node _T_2451 = bits(_WIRE_181, 19, 19)
connect _WIRE_180.ae_ptw, _T_2451
node _T_2452 = bits(_WIRE_181, 20, 20)
connect _WIRE_180.g, _T_2452
node _T_2453 = bits(_WIRE_181, 21, 21)
connect _WIRE_180.u, _T_2453
node _T_2454 = bits(_WIRE_181, 41, 22)
connect _WIRE_180.ppn, _T_2454
wire _WIRE_182 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_183 : UInt<42>
connect _WIRE_183, sectored_entries[0][5].data[3]
node _T_2455 = bits(_WIRE_183, 0, 0)
connect _WIRE_182.fragmented_superpage, _T_2455
node _T_2456 = bits(_WIRE_183, 1, 1)
connect _WIRE_182.c, _T_2456
node _T_2457 = bits(_WIRE_183, 2, 2)
connect _WIRE_182.eff, _T_2457
node _T_2458 = bits(_WIRE_183, 3, 3)
connect _WIRE_182.paa, _T_2458
node _T_2459 = bits(_WIRE_183, 4, 4)
connect _WIRE_182.pal, _T_2459
node _T_2460 = bits(_WIRE_183, 5, 5)
connect _WIRE_182.ppp, _T_2460
node _T_2461 = bits(_WIRE_183, 6, 6)
connect _WIRE_182.pr, _T_2461
node _T_2462 = bits(_WIRE_183, 7, 7)
connect _WIRE_182.px, _T_2462
node _T_2463 = bits(_WIRE_183, 8, 8)
connect _WIRE_182.pw, _T_2463
node _T_2464 = bits(_WIRE_183, 9, 9)
connect _WIRE_182.hr, _T_2464
node _T_2465 = bits(_WIRE_183, 10, 10)
connect _WIRE_182.hx, _T_2465
node _T_2466 = bits(_WIRE_183, 11, 11)
connect _WIRE_182.hw, _T_2466
node _T_2467 = bits(_WIRE_183, 12, 12)
connect _WIRE_182.sr, _T_2467
node _T_2468 = bits(_WIRE_183, 13, 13)
connect _WIRE_182.sx, _T_2468
node _T_2469 = bits(_WIRE_183, 14, 14)
connect _WIRE_182.sw, _T_2469
node _T_2470 = bits(_WIRE_183, 15, 15)
connect _WIRE_182.gf, _T_2470
node _T_2471 = bits(_WIRE_183, 16, 16)
connect _WIRE_182.pf, _T_2471
node _T_2472 = bits(_WIRE_183, 17, 17)
connect _WIRE_182.ae_stage2, _T_2472
node _T_2473 = bits(_WIRE_183, 18, 18)
connect _WIRE_182.ae_final, _T_2473
node _T_2474 = bits(_WIRE_183, 19, 19)
connect _WIRE_182.ae_ptw, _T_2474
node _T_2475 = bits(_WIRE_183, 20, 20)
connect _WIRE_182.g, _T_2475
node _T_2476 = bits(_WIRE_183, 21, 21)
connect _WIRE_182.u, _T_2476
node _T_2477 = bits(_WIRE_183, 41, 22)
connect _WIRE_182.ppn, _T_2477
node _T_2478 = eq(sectored_entries[0][5].tag_v, hv_5)
node _T_2479 = eq(_WIRE_176.g, UInt<1>(0h0))
node _T_2480 = and(_T_2478, _T_2479)
when _T_2480 :
connect sectored_entries[0][5].valid[0], UInt<1>(0h0)
node _T_2481 = eq(sectored_entries[0][5].tag_v, hv_5)
node _T_2482 = eq(_WIRE_178.g, UInt<1>(0h0))
node _T_2483 = and(_T_2481, _T_2482)
when _T_2483 :
connect sectored_entries[0][5].valid[1], UInt<1>(0h0)
node _T_2484 = eq(sectored_entries[0][5].tag_v, hv_5)
node _T_2485 = eq(_WIRE_180.g, UInt<1>(0h0))
node _T_2486 = and(_T_2484, _T_2485)
when _T_2486 :
connect sectored_entries[0][5].valid[2], UInt<1>(0h0)
node _T_2487 = eq(sectored_entries[0][5].tag_v, hv_5)
node _T_2488 = eq(_WIRE_182.g, UInt<1>(0h0))
node _T_2489 = and(_T_2487, _T_2488)
when _T_2489 :
connect sectored_entries[0][5].valid[3], UInt<1>(0h0)
else :
node _T_2490 = or(hv_5, hg_5)
wire _WIRE_184 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_185 : UInt<42>
connect _WIRE_185, sectored_entries[0][5].data[0]
node _T_2491 = bits(_WIRE_185, 0, 0)
connect _WIRE_184.fragmented_superpage, _T_2491
node _T_2492 = bits(_WIRE_185, 1, 1)
connect _WIRE_184.c, _T_2492
node _T_2493 = bits(_WIRE_185, 2, 2)
connect _WIRE_184.eff, _T_2493
node _T_2494 = bits(_WIRE_185, 3, 3)
connect _WIRE_184.paa, _T_2494
node _T_2495 = bits(_WIRE_185, 4, 4)
connect _WIRE_184.pal, _T_2495
node _T_2496 = bits(_WIRE_185, 5, 5)
connect _WIRE_184.ppp, _T_2496
node _T_2497 = bits(_WIRE_185, 6, 6)
connect _WIRE_184.pr, _T_2497
node _T_2498 = bits(_WIRE_185, 7, 7)
connect _WIRE_184.px, _T_2498
node _T_2499 = bits(_WIRE_185, 8, 8)
connect _WIRE_184.pw, _T_2499
node _T_2500 = bits(_WIRE_185, 9, 9)
connect _WIRE_184.hr, _T_2500
node _T_2501 = bits(_WIRE_185, 10, 10)
connect _WIRE_184.hx, _T_2501
node _T_2502 = bits(_WIRE_185, 11, 11)
connect _WIRE_184.hw, _T_2502
node _T_2503 = bits(_WIRE_185, 12, 12)
connect _WIRE_184.sr, _T_2503
node _T_2504 = bits(_WIRE_185, 13, 13)
connect _WIRE_184.sx, _T_2504
node _T_2505 = bits(_WIRE_185, 14, 14)
connect _WIRE_184.sw, _T_2505
node _T_2506 = bits(_WIRE_185, 15, 15)
connect _WIRE_184.gf, _T_2506
node _T_2507 = bits(_WIRE_185, 16, 16)
connect _WIRE_184.pf, _T_2507
node _T_2508 = bits(_WIRE_185, 17, 17)
connect _WIRE_184.ae_stage2, _T_2508
node _T_2509 = bits(_WIRE_185, 18, 18)
connect _WIRE_184.ae_final, _T_2509
node _T_2510 = bits(_WIRE_185, 19, 19)
connect _WIRE_184.ae_ptw, _T_2510
node _T_2511 = bits(_WIRE_185, 20, 20)
connect _WIRE_184.g, _T_2511
node _T_2512 = bits(_WIRE_185, 21, 21)
connect _WIRE_184.u, _T_2512
node _T_2513 = bits(_WIRE_185, 41, 22)
connect _WIRE_184.ppn, _T_2513
wire _WIRE_186 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_187 : UInt<42>
connect _WIRE_187, sectored_entries[0][5].data[1]
node _T_2514 = bits(_WIRE_187, 0, 0)
connect _WIRE_186.fragmented_superpage, _T_2514
node _T_2515 = bits(_WIRE_187, 1, 1)
connect _WIRE_186.c, _T_2515
node _T_2516 = bits(_WIRE_187, 2, 2)
connect _WIRE_186.eff, _T_2516
node _T_2517 = bits(_WIRE_187, 3, 3)
connect _WIRE_186.paa, _T_2517
node _T_2518 = bits(_WIRE_187, 4, 4)
connect _WIRE_186.pal, _T_2518
node _T_2519 = bits(_WIRE_187, 5, 5)
connect _WIRE_186.ppp, _T_2519
node _T_2520 = bits(_WIRE_187, 6, 6)
connect _WIRE_186.pr, _T_2520
node _T_2521 = bits(_WIRE_187, 7, 7)
connect _WIRE_186.px, _T_2521
node _T_2522 = bits(_WIRE_187, 8, 8)
connect _WIRE_186.pw, _T_2522
node _T_2523 = bits(_WIRE_187, 9, 9)
connect _WIRE_186.hr, _T_2523
node _T_2524 = bits(_WIRE_187, 10, 10)
connect _WIRE_186.hx, _T_2524
node _T_2525 = bits(_WIRE_187, 11, 11)
connect _WIRE_186.hw, _T_2525
node _T_2526 = bits(_WIRE_187, 12, 12)
connect _WIRE_186.sr, _T_2526
node _T_2527 = bits(_WIRE_187, 13, 13)
connect _WIRE_186.sx, _T_2527
node _T_2528 = bits(_WIRE_187, 14, 14)
connect _WIRE_186.sw, _T_2528
node _T_2529 = bits(_WIRE_187, 15, 15)
connect _WIRE_186.gf, _T_2529
node _T_2530 = bits(_WIRE_187, 16, 16)
connect _WIRE_186.pf, _T_2530
node _T_2531 = bits(_WIRE_187, 17, 17)
connect _WIRE_186.ae_stage2, _T_2531
node _T_2532 = bits(_WIRE_187, 18, 18)
connect _WIRE_186.ae_final, _T_2532
node _T_2533 = bits(_WIRE_187, 19, 19)
connect _WIRE_186.ae_ptw, _T_2533
node _T_2534 = bits(_WIRE_187, 20, 20)
connect _WIRE_186.g, _T_2534
node _T_2535 = bits(_WIRE_187, 21, 21)
connect _WIRE_186.u, _T_2535
node _T_2536 = bits(_WIRE_187, 41, 22)
connect _WIRE_186.ppn, _T_2536
wire _WIRE_188 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_189 : UInt<42>
connect _WIRE_189, sectored_entries[0][5].data[2]
node _T_2537 = bits(_WIRE_189, 0, 0)
connect _WIRE_188.fragmented_superpage, _T_2537
node _T_2538 = bits(_WIRE_189, 1, 1)
connect _WIRE_188.c, _T_2538
node _T_2539 = bits(_WIRE_189, 2, 2)
connect _WIRE_188.eff, _T_2539
node _T_2540 = bits(_WIRE_189, 3, 3)
connect _WIRE_188.paa, _T_2540
node _T_2541 = bits(_WIRE_189, 4, 4)
connect _WIRE_188.pal, _T_2541
node _T_2542 = bits(_WIRE_189, 5, 5)
connect _WIRE_188.ppp, _T_2542
node _T_2543 = bits(_WIRE_189, 6, 6)
connect _WIRE_188.pr, _T_2543
node _T_2544 = bits(_WIRE_189, 7, 7)
connect _WIRE_188.px, _T_2544
node _T_2545 = bits(_WIRE_189, 8, 8)
connect _WIRE_188.pw, _T_2545
node _T_2546 = bits(_WIRE_189, 9, 9)
connect _WIRE_188.hr, _T_2546
node _T_2547 = bits(_WIRE_189, 10, 10)
connect _WIRE_188.hx, _T_2547
node _T_2548 = bits(_WIRE_189, 11, 11)
connect _WIRE_188.hw, _T_2548
node _T_2549 = bits(_WIRE_189, 12, 12)
connect _WIRE_188.sr, _T_2549
node _T_2550 = bits(_WIRE_189, 13, 13)
connect _WIRE_188.sx, _T_2550
node _T_2551 = bits(_WIRE_189, 14, 14)
connect _WIRE_188.sw, _T_2551
node _T_2552 = bits(_WIRE_189, 15, 15)
connect _WIRE_188.gf, _T_2552
node _T_2553 = bits(_WIRE_189, 16, 16)
connect _WIRE_188.pf, _T_2553
node _T_2554 = bits(_WIRE_189, 17, 17)
connect _WIRE_188.ae_stage2, _T_2554
node _T_2555 = bits(_WIRE_189, 18, 18)
connect _WIRE_188.ae_final, _T_2555
node _T_2556 = bits(_WIRE_189, 19, 19)
connect _WIRE_188.ae_ptw, _T_2556
node _T_2557 = bits(_WIRE_189, 20, 20)
connect _WIRE_188.g, _T_2557
node _T_2558 = bits(_WIRE_189, 21, 21)
connect _WIRE_188.u, _T_2558
node _T_2559 = bits(_WIRE_189, 41, 22)
connect _WIRE_188.ppn, _T_2559
wire _WIRE_190 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_191 : UInt<42>
connect _WIRE_191, sectored_entries[0][5].data[3]
node _T_2560 = bits(_WIRE_191, 0, 0)
connect _WIRE_190.fragmented_superpage, _T_2560
node _T_2561 = bits(_WIRE_191, 1, 1)
connect _WIRE_190.c, _T_2561
node _T_2562 = bits(_WIRE_191, 2, 2)
connect _WIRE_190.eff, _T_2562
node _T_2563 = bits(_WIRE_191, 3, 3)
connect _WIRE_190.paa, _T_2563
node _T_2564 = bits(_WIRE_191, 4, 4)
connect _WIRE_190.pal, _T_2564
node _T_2565 = bits(_WIRE_191, 5, 5)
connect _WIRE_190.ppp, _T_2565
node _T_2566 = bits(_WIRE_191, 6, 6)
connect _WIRE_190.pr, _T_2566
node _T_2567 = bits(_WIRE_191, 7, 7)
connect _WIRE_190.px, _T_2567
node _T_2568 = bits(_WIRE_191, 8, 8)
connect _WIRE_190.pw, _T_2568
node _T_2569 = bits(_WIRE_191, 9, 9)
connect _WIRE_190.hr, _T_2569
node _T_2570 = bits(_WIRE_191, 10, 10)
connect _WIRE_190.hx, _T_2570
node _T_2571 = bits(_WIRE_191, 11, 11)
connect _WIRE_190.hw, _T_2571
node _T_2572 = bits(_WIRE_191, 12, 12)
connect _WIRE_190.sr, _T_2572
node _T_2573 = bits(_WIRE_191, 13, 13)
connect _WIRE_190.sx, _T_2573
node _T_2574 = bits(_WIRE_191, 14, 14)
connect _WIRE_190.sw, _T_2574
node _T_2575 = bits(_WIRE_191, 15, 15)
connect _WIRE_190.gf, _T_2575
node _T_2576 = bits(_WIRE_191, 16, 16)
connect _WIRE_190.pf, _T_2576
node _T_2577 = bits(_WIRE_191, 17, 17)
connect _WIRE_190.ae_stage2, _T_2577
node _T_2578 = bits(_WIRE_191, 18, 18)
connect _WIRE_190.ae_final, _T_2578
node _T_2579 = bits(_WIRE_191, 19, 19)
connect _WIRE_190.ae_ptw, _T_2579
node _T_2580 = bits(_WIRE_191, 20, 20)
connect _WIRE_190.g, _T_2580
node _T_2581 = bits(_WIRE_191, 21, 21)
connect _WIRE_190.u, _T_2581
node _T_2582 = bits(_WIRE_191, 41, 22)
connect _WIRE_190.ppn, _T_2582
node _T_2583 = eq(sectored_entries[0][5].tag_v, _T_2490)
when _T_2583 :
connect sectored_entries[0][5].valid[0], UInt<1>(0h0)
node _T_2584 = eq(sectored_entries[0][5].tag_v, _T_2490)
when _T_2584 :
connect sectored_entries[0][5].valid[1], UInt<1>(0h0)
node _T_2585 = eq(sectored_entries[0][5].tag_v, _T_2490)
when _T_2585 :
connect sectored_entries[0][5].valid[2], UInt<1>(0h0)
node _T_2586 = eq(sectored_entries[0][5].tag_v, _T_2490)
when _T_2586 :
connect sectored_entries[0][5].valid[3], UInt<1>(0h0)
node hv_6 = and(UInt<1>(0h0), io.sfence.bits.hv)
node hg_6 = and(UInt<1>(0h0), io.sfence.bits.hg)
node _T_2587 = eq(hg_6, UInt<1>(0h0))
node _T_2588 = and(_T_2587, io.sfence.bits.rs1)
when _T_2588 :
node _T_2589 = xor(sectored_entries[0][6].tag_vpn, vpn)
node _T_2590 = shr(_T_2589, 2)
node _T_2591 = eq(_T_2590, UInt<1>(0h0))
node _T_2592 = eq(sectored_entries[0][6].tag_v, hv_6)
node _T_2593 = and(_T_2591, _T_2592)
when _T_2593 :
wire _WIRE_192 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_193 : UInt<42>
connect _WIRE_193, sectored_entries[0][6].data[0]
node _T_2594 = bits(_WIRE_193, 0, 0)
connect _WIRE_192.fragmented_superpage, _T_2594
node _T_2595 = bits(_WIRE_193, 1, 1)
connect _WIRE_192.c, _T_2595
node _T_2596 = bits(_WIRE_193, 2, 2)
connect _WIRE_192.eff, _T_2596
node _T_2597 = bits(_WIRE_193, 3, 3)
connect _WIRE_192.paa, _T_2597
node _T_2598 = bits(_WIRE_193, 4, 4)
connect _WIRE_192.pal, _T_2598
node _T_2599 = bits(_WIRE_193, 5, 5)
connect _WIRE_192.ppp, _T_2599
node _T_2600 = bits(_WIRE_193, 6, 6)
connect _WIRE_192.pr, _T_2600
node _T_2601 = bits(_WIRE_193, 7, 7)
connect _WIRE_192.px, _T_2601
node _T_2602 = bits(_WIRE_193, 8, 8)
connect _WIRE_192.pw, _T_2602
node _T_2603 = bits(_WIRE_193, 9, 9)
connect _WIRE_192.hr, _T_2603
node _T_2604 = bits(_WIRE_193, 10, 10)
connect _WIRE_192.hx, _T_2604
node _T_2605 = bits(_WIRE_193, 11, 11)
connect _WIRE_192.hw, _T_2605
node _T_2606 = bits(_WIRE_193, 12, 12)
connect _WIRE_192.sr, _T_2606
node _T_2607 = bits(_WIRE_193, 13, 13)
connect _WIRE_192.sx, _T_2607
node _T_2608 = bits(_WIRE_193, 14, 14)
connect _WIRE_192.sw, _T_2608
node _T_2609 = bits(_WIRE_193, 15, 15)
connect _WIRE_192.gf, _T_2609
node _T_2610 = bits(_WIRE_193, 16, 16)
connect _WIRE_192.pf, _T_2610
node _T_2611 = bits(_WIRE_193, 17, 17)
connect _WIRE_192.ae_stage2, _T_2611
node _T_2612 = bits(_WIRE_193, 18, 18)
connect _WIRE_192.ae_final, _T_2612
node _T_2613 = bits(_WIRE_193, 19, 19)
connect _WIRE_192.ae_ptw, _T_2613
node _T_2614 = bits(_WIRE_193, 20, 20)
connect _WIRE_192.g, _T_2614
node _T_2615 = bits(_WIRE_193, 21, 21)
connect _WIRE_192.u, _T_2615
node _T_2616 = bits(_WIRE_193, 41, 22)
connect _WIRE_192.ppn, _T_2616
wire _WIRE_194 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_195 : UInt<42>
connect _WIRE_195, sectored_entries[0][6].data[1]
node _T_2617 = bits(_WIRE_195, 0, 0)
connect _WIRE_194.fragmented_superpage, _T_2617
node _T_2618 = bits(_WIRE_195, 1, 1)
connect _WIRE_194.c, _T_2618
node _T_2619 = bits(_WIRE_195, 2, 2)
connect _WIRE_194.eff, _T_2619
node _T_2620 = bits(_WIRE_195, 3, 3)
connect _WIRE_194.paa, _T_2620
node _T_2621 = bits(_WIRE_195, 4, 4)
connect _WIRE_194.pal, _T_2621
node _T_2622 = bits(_WIRE_195, 5, 5)
connect _WIRE_194.ppp, _T_2622
node _T_2623 = bits(_WIRE_195, 6, 6)
connect _WIRE_194.pr, _T_2623
node _T_2624 = bits(_WIRE_195, 7, 7)
connect _WIRE_194.px, _T_2624
node _T_2625 = bits(_WIRE_195, 8, 8)
connect _WIRE_194.pw, _T_2625
node _T_2626 = bits(_WIRE_195, 9, 9)
connect _WIRE_194.hr, _T_2626
node _T_2627 = bits(_WIRE_195, 10, 10)
connect _WIRE_194.hx, _T_2627
node _T_2628 = bits(_WIRE_195, 11, 11)
connect _WIRE_194.hw, _T_2628
node _T_2629 = bits(_WIRE_195, 12, 12)
connect _WIRE_194.sr, _T_2629
node _T_2630 = bits(_WIRE_195, 13, 13)
connect _WIRE_194.sx, _T_2630
node _T_2631 = bits(_WIRE_195, 14, 14)
connect _WIRE_194.sw, _T_2631
node _T_2632 = bits(_WIRE_195, 15, 15)
connect _WIRE_194.gf, _T_2632
node _T_2633 = bits(_WIRE_195, 16, 16)
connect _WIRE_194.pf, _T_2633
node _T_2634 = bits(_WIRE_195, 17, 17)
connect _WIRE_194.ae_stage2, _T_2634
node _T_2635 = bits(_WIRE_195, 18, 18)
connect _WIRE_194.ae_final, _T_2635
node _T_2636 = bits(_WIRE_195, 19, 19)
connect _WIRE_194.ae_ptw, _T_2636
node _T_2637 = bits(_WIRE_195, 20, 20)
connect _WIRE_194.g, _T_2637
node _T_2638 = bits(_WIRE_195, 21, 21)
connect _WIRE_194.u, _T_2638
node _T_2639 = bits(_WIRE_195, 41, 22)
connect _WIRE_194.ppn, _T_2639
wire _WIRE_196 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_197 : UInt<42>
connect _WIRE_197, sectored_entries[0][6].data[2]
node _T_2640 = bits(_WIRE_197, 0, 0)
connect _WIRE_196.fragmented_superpage, _T_2640
node _T_2641 = bits(_WIRE_197, 1, 1)
connect _WIRE_196.c, _T_2641
node _T_2642 = bits(_WIRE_197, 2, 2)
connect _WIRE_196.eff, _T_2642
node _T_2643 = bits(_WIRE_197, 3, 3)
connect _WIRE_196.paa, _T_2643
node _T_2644 = bits(_WIRE_197, 4, 4)
connect _WIRE_196.pal, _T_2644
node _T_2645 = bits(_WIRE_197, 5, 5)
connect _WIRE_196.ppp, _T_2645
node _T_2646 = bits(_WIRE_197, 6, 6)
connect _WIRE_196.pr, _T_2646
node _T_2647 = bits(_WIRE_197, 7, 7)
connect _WIRE_196.px, _T_2647
node _T_2648 = bits(_WIRE_197, 8, 8)
connect _WIRE_196.pw, _T_2648
node _T_2649 = bits(_WIRE_197, 9, 9)
connect _WIRE_196.hr, _T_2649
node _T_2650 = bits(_WIRE_197, 10, 10)
connect _WIRE_196.hx, _T_2650
node _T_2651 = bits(_WIRE_197, 11, 11)
connect _WIRE_196.hw, _T_2651
node _T_2652 = bits(_WIRE_197, 12, 12)
connect _WIRE_196.sr, _T_2652
node _T_2653 = bits(_WIRE_197, 13, 13)
connect _WIRE_196.sx, _T_2653
node _T_2654 = bits(_WIRE_197, 14, 14)
connect _WIRE_196.sw, _T_2654
node _T_2655 = bits(_WIRE_197, 15, 15)
connect _WIRE_196.gf, _T_2655
node _T_2656 = bits(_WIRE_197, 16, 16)
connect _WIRE_196.pf, _T_2656
node _T_2657 = bits(_WIRE_197, 17, 17)
connect _WIRE_196.ae_stage2, _T_2657
node _T_2658 = bits(_WIRE_197, 18, 18)
connect _WIRE_196.ae_final, _T_2658
node _T_2659 = bits(_WIRE_197, 19, 19)
connect _WIRE_196.ae_ptw, _T_2659
node _T_2660 = bits(_WIRE_197, 20, 20)
connect _WIRE_196.g, _T_2660
node _T_2661 = bits(_WIRE_197, 21, 21)
connect _WIRE_196.u, _T_2661
node _T_2662 = bits(_WIRE_197, 41, 22)
connect _WIRE_196.ppn, _T_2662
wire _WIRE_198 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_199 : UInt<42>
connect _WIRE_199, sectored_entries[0][6].data[3]
node _T_2663 = bits(_WIRE_199, 0, 0)
connect _WIRE_198.fragmented_superpage, _T_2663
node _T_2664 = bits(_WIRE_199, 1, 1)
connect _WIRE_198.c, _T_2664
node _T_2665 = bits(_WIRE_199, 2, 2)
connect _WIRE_198.eff, _T_2665
node _T_2666 = bits(_WIRE_199, 3, 3)
connect _WIRE_198.paa, _T_2666
node _T_2667 = bits(_WIRE_199, 4, 4)
connect _WIRE_198.pal, _T_2667
node _T_2668 = bits(_WIRE_199, 5, 5)
connect _WIRE_198.ppp, _T_2668
node _T_2669 = bits(_WIRE_199, 6, 6)
connect _WIRE_198.pr, _T_2669
node _T_2670 = bits(_WIRE_199, 7, 7)
connect _WIRE_198.px, _T_2670
node _T_2671 = bits(_WIRE_199, 8, 8)
connect _WIRE_198.pw, _T_2671
node _T_2672 = bits(_WIRE_199, 9, 9)
connect _WIRE_198.hr, _T_2672
node _T_2673 = bits(_WIRE_199, 10, 10)
connect _WIRE_198.hx, _T_2673
node _T_2674 = bits(_WIRE_199, 11, 11)
connect _WIRE_198.hw, _T_2674
node _T_2675 = bits(_WIRE_199, 12, 12)
connect _WIRE_198.sr, _T_2675
node _T_2676 = bits(_WIRE_199, 13, 13)
connect _WIRE_198.sx, _T_2676
node _T_2677 = bits(_WIRE_199, 14, 14)
connect _WIRE_198.sw, _T_2677
node _T_2678 = bits(_WIRE_199, 15, 15)
connect _WIRE_198.gf, _T_2678
node _T_2679 = bits(_WIRE_199, 16, 16)
connect _WIRE_198.pf, _T_2679
node _T_2680 = bits(_WIRE_199, 17, 17)
connect _WIRE_198.ae_stage2, _T_2680
node _T_2681 = bits(_WIRE_199, 18, 18)
connect _WIRE_198.ae_final, _T_2681
node _T_2682 = bits(_WIRE_199, 19, 19)
connect _WIRE_198.ae_ptw, _T_2682
node _T_2683 = bits(_WIRE_199, 20, 20)
connect _WIRE_198.g, _T_2683
node _T_2684 = bits(_WIRE_199, 21, 21)
connect _WIRE_198.u, _T_2684
node _T_2685 = bits(_WIRE_199, 41, 22)
connect _WIRE_198.ppn, _T_2685
node _T_2686 = eq(sectored_entries[0][6].tag_v, hv_6)
node _T_2687 = bits(vpn, 1, 0)
node _T_2688 = eq(UInt<1>(0h0), _T_2687)
node _T_2689 = and(_T_2686, _T_2688)
when _T_2689 :
connect sectored_entries[0][6].valid[0], UInt<1>(0h0)
node _T_2690 = eq(sectored_entries[0][6].tag_v, hv_6)
node _T_2691 = bits(vpn, 1, 0)
node _T_2692 = eq(UInt<1>(0h1), _T_2691)
node _T_2693 = and(_T_2690, _T_2692)
when _T_2693 :
connect sectored_entries[0][6].valid[1], UInt<1>(0h0)
node _T_2694 = eq(sectored_entries[0][6].tag_v, hv_6)
node _T_2695 = bits(vpn, 1, 0)
node _T_2696 = eq(UInt<2>(0h2), _T_2695)
node _T_2697 = and(_T_2694, _T_2696)
when _T_2697 :
connect sectored_entries[0][6].valid[2], UInt<1>(0h0)
node _T_2698 = eq(sectored_entries[0][6].tag_v, hv_6)
node _T_2699 = bits(vpn, 1, 0)
node _T_2700 = eq(UInt<2>(0h3), _T_2699)
node _T_2701 = and(_T_2698, _T_2700)
when _T_2701 :
connect sectored_entries[0][6].valid[3], UInt<1>(0h0)
node _T_2702 = xor(sectored_entries[0][6].tag_vpn, vpn)
node _T_2703 = shr(_T_2702, 18)
node _T_2704 = eq(_T_2703, UInt<1>(0h0))
when _T_2704 :
wire _WIRE_200 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_201 : UInt<42>
connect _WIRE_201, sectored_entries[0][6].data[0]
node _T_2705 = bits(_WIRE_201, 0, 0)
connect _WIRE_200.fragmented_superpage, _T_2705
node _T_2706 = bits(_WIRE_201, 1, 1)
connect _WIRE_200.c, _T_2706
node _T_2707 = bits(_WIRE_201, 2, 2)
connect _WIRE_200.eff, _T_2707
node _T_2708 = bits(_WIRE_201, 3, 3)
connect _WIRE_200.paa, _T_2708
node _T_2709 = bits(_WIRE_201, 4, 4)
connect _WIRE_200.pal, _T_2709
node _T_2710 = bits(_WIRE_201, 5, 5)
connect _WIRE_200.ppp, _T_2710
node _T_2711 = bits(_WIRE_201, 6, 6)
connect _WIRE_200.pr, _T_2711
node _T_2712 = bits(_WIRE_201, 7, 7)
connect _WIRE_200.px, _T_2712
node _T_2713 = bits(_WIRE_201, 8, 8)
connect _WIRE_200.pw, _T_2713
node _T_2714 = bits(_WIRE_201, 9, 9)
connect _WIRE_200.hr, _T_2714
node _T_2715 = bits(_WIRE_201, 10, 10)
connect _WIRE_200.hx, _T_2715
node _T_2716 = bits(_WIRE_201, 11, 11)
connect _WIRE_200.hw, _T_2716
node _T_2717 = bits(_WIRE_201, 12, 12)
connect _WIRE_200.sr, _T_2717
node _T_2718 = bits(_WIRE_201, 13, 13)
connect _WIRE_200.sx, _T_2718
node _T_2719 = bits(_WIRE_201, 14, 14)
connect _WIRE_200.sw, _T_2719
node _T_2720 = bits(_WIRE_201, 15, 15)
connect _WIRE_200.gf, _T_2720
node _T_2721 = bits(_WIRE_201, 16, 16)
connect _WIRE_200.pf, _T_2721
node _T_2722 = bits(_WIRE_201, 17, 17)
connect _WIRE_200.ae_stage2, _T_2722
node _T_2723 = bits(_WIRE_201, 18, 18)
connect _WIRE_200.ae_final, _T_2723
node _T_2724 = bits(_WIRE_201, 19, 19)
connect _WIRE_200.ae_ptw, _T_2724
node _T_2725 = bits(_WIRE_201, 20, 20)
connect _WIRE_200.g, _T_2725
node _T_2726 = bits(_WIRE_201, 21, 21)
connect _WIRE_200.u, _T_2726
node _T_2727 = bits(_WIRE_201, 41, 22)
connect _WIRE_200.ppn, _T_2727
wire _WIRE_202 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_203 : UInt<42>
connect _WIRE_203, sectored_entries[0][6].data[1]
node _T_2728 = bits(_WIRE_203, 0, 0)
connect _WIRE_202.fragmented_superpage, _T_2728
node _T_2729 = bits(_WIRE_203, 1, 1)
connect _WIRE_202.c, _T_2729
node _T_2730 = bits(_WIRE_203, 2, 2)
connect _WIRE_202.eff, _T_2730
node _T_2731 = bits(_WIRE_203, 3, 3)
connect _WIRE_202.paa, _T_2731
node _T_2732 = bits(_WIRE_203, 4, 4)
connect _WIRE_202.pal, _T_2732
node _T_2733 = bits(_WIRE_203, 5, 5)
connect _WIRE_202.ppp, _T_2733
node _T_2734 = bits(_WIRE_203, 6, 6)
connect _WIRE_202.pr, _T_2734
node _T_2735 = bits(_WIRE_203, 7, 7)
connect _WIRE_202.px, _T_2735
node _T_2736 = bits(_WIRE_203, 8, 8)
connect _WIRE_202.pw, _T_2736
node _T_2737 = bits(_WIRE_203, 9, 9)
connect _WIRE_202.hr, _T_2737
node _T_2738 = bits(_WIRE_203, 10, 10)
connect _WIRE_202.hx, _T_2738
node _T_2739 = bits(_WIRE_203, 11, 11)
connect _WIRE_202.hw, _T_2739
node _T_2740 = bits(_WIRE_203, 12, 12)
connect _WIRE_202.sr, _T_2740
node _T_2741 = bits(_WIRE_203, 13, 13)
connect _WIRE_202.sx, _T_2741
node _T_2742 = bits(_WIRE_203, 14, 14)
connect _WIRE_202.sw, _T_2742
node _T_2743 = bits(_WIRE_203, 15, 15)
connect _WIRE_202.gf, _T_2743
node _T_2744 = bits(_WIRE_203, 16, 16)
connect _WIRE_202.pf, _T_2744
node _T_2745 = bits(_WIRE_203, 17, 17)
connect _WIRE_202.ae_stage2, _T_2745
node _T_2746 = bits(_WIRE_203, 18, 18)
connect _WIRE_202.ae_final, _T_2746
node _T_2747 = bits(_WIRE_203, 19, 19)
connect _WIRE_202.ae_ptw, _T_2747
node _T_2748 = bits(_WIRE_203, 20, 20)
connect _WIRE_202.g, _T_2748
node _T_2749 = bits(_WIRE_203, 21, 21)
connect _WIRE_202.u, _T_2749
node _T_2750 = bits(_WIRE_203, 41, 22)
connect _WIRE_202.ppn, _T_2750
wire _WIRE_204 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_205 : UInt<42>
connect _WIRE_205, sectored_entries[0][6].data[2]
node _T_2751 = bits(_WIRE_205, 0, 0)
connect _WIRE_204.fragmented_superpage, _T_2751
node _T_2752 = bits(_WIRE_205, 1, 1)
connect _WIRE_204.c, _T_2752
node _T_2753 = bits(_WIRE_205, 2, 2)
connect _WIRE_204.eff, _T_2753
node _T_2754 = bits(_WIRE_205, 3, 3)
connect _WIRE_204.paa, _T_2754
node _T_2755 = bits(_WIRE_205, 4, 4)
connect _WIRE_204.pal, _T_2755
node _T_2756 = bits(_WIRE_205, 5, 5)
connect _WIRE_204.ppp, _T_2756
node _T_2757 = bits(_WIRE_205, 6, 6)
connect _WIRE_204.pr, _T_2757
node _T_2758 = bits(_WIRE_205, 7, 7)
connect _WIRE_204.px, _T_2758
node _T_2759 = bits(_WIRE_205, 8, 8)
connect _WIRE_204.pw, _T_2759
node _T_2760 = bits(_WIRE_205, 9, 9)
connect _WIRE_204.hr, _T_2760
node _T_2761 = bits(_WIRE_205, 10, 10)
connect _WIRE_204.hx, _T_2761
node _T_2762 = bits(_WIRE_205, 11, 11)
connect _WIRE_204.hw, _T_2762
node _T_2763 = bits(_WIRE_205, 12, 12)
connect _WIRE_204.sr, _T_2763
node _T_2764 = bits(_WIRE_205, 13, 13)
connect _WIRE_204.sx, _T_2764
node _T_2765 = bits(_WIRE_205, 14, 14)
connect _WIRE_204.sw, _T_2765
node _T_2766 = bits(_WIRE_205, 15, 15)
connect _WIRE_204.gf, _T_2766
node _T_2767 = bits(_WIRE_205, 16, 16)
connect _WIRE_204.pf, _T_2767
node _T_2768 = bits(_WIRE_205, 17, 17)
connect _WIRE_204.ae_stage2, _T_2768
node _T_2769 = bits(_WIRE_205, 18, 18)
connect _WIRE_204.ae_final, _T_2769
node _T_2770 = bits(_WIRE_205, 19, 19)
connect _WIRE_204.ae_ptw, _T_2770
node _T_2771 = bits(_WIRE_205, 20, 20)
connect _WIRE_204.g, _T_2771
node _T_2772 = bits(_WIRE_205, 21, 21)
connect _WIRE_204.u, _T_2772
node _T_2773 = bits(_WIRE_205, 41, 22)
connect _WIRE_204.ppn, _T_2773
wire _WIRE_206 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_207 : UInt<42>
connect _WIRE_207, sectored_entries[0][6].data[3]
node _T_2774 = bits(_WIRE_207, 0, 0)
connect _WIRE_206.fragmented_superpage, _T_2774
node _T_2775 = bits(_WIRE_207, 1, 1)
connect _WIRE_206.c, _T_2775
node _T_2776 = bits(_WIRE_207, 2, 2)
connect _WIRE_206.eff, _T_2776
node _T_2777 = bits(_WIRE_207, 3, 3)
connect _WIRE_206.paa, _T_2777
node _T_2778 = bits(_WIRE_207, 4, 4)
connect _WIRE_206.pal, _T_2778
node _T_2779 = bits(_WIRE_207, 5, 5)
connect _WIRE_206.ppp, _T_2779
node _T_2780 = bits(_WIRE_207, 6, 6)
connect _WIRE_206.pr, _T_2780
node _T_2781 = bits(_WIRE_207, 7, 7)
connect _WIRE_206.px, _T_2781
node _T_2782 = bits(_WIRE_207, 8, 8)
connect _WIRE_206.pw, _T_2782
node _T_2783 = bits(_WIRE_207, 9, 9)
connect _WIRE_206.hr, _T_2783
node _T_2784 = bits(_WIRE_207, 10, 10)
connect _WIRE_206.hx, _T_2784
node _T_2785 = bits(_WIRE_207, 11, 11)
connect _WIRE_206.hw, _T_2785
node _T_2786 = bits(_WIRE_207, 12, 12)
connect _WIRE_206.sr, _T_2786
node _T_2787 = bits(_WIRE_207, 13, 13)
connect _WIRE_206.sx, _T_2787
node _T_2788 = bits(_WIRE_207, 14, 14)
connect _WIRE_206.sw, _T_2788
node _T_2789 = bits(_WIRE_207, 15, 15)
connect _WIRE_206.gf, _T_2789
node _T_2790 = bits(_WIRE_207, 16, 16)
connect _WIRE_206.pf, _T_2790
node _T_2791 = bits(_WIRE_207, 17, 17)
connect _WIRE_206.ae_stage2, _T_2791
node _T_2792 = bits(_WIRE_207, 18, 18)
connect _WIRE_206.ae_final, _T_2792
node _T_2793 = bits(_WIRE_207, 19, 19)
connect _WIRE_206.ae_ptw, _T_2793
node _T_2794 = bits(_WIRE_207, 20, 20)
connect _WIRE_206.g, _T_2794
node _T_2795 = bits(_WIRE_207, 21, 21)
connect _WIRE_206.u, _T_2795
node _T_2796 = bits(_WIRE_207, 41, 22)
connect _WIRE_206.ppn, _T_2796
node _T_2797 = eq(sectored_entries[0][6].tag_v, hv_6)
node _T_2798 = and(_T_2797, _WIRE_200.fragmented_superpage)
when _T_2798 :
connect sectored_entries[0][6].valid[0], UInt<1>(0h0)
node _T_2799 = eq(sectored_entries[0][6].tag_v, hv_6)
node _T_2800 = and(_T_2799, _WIRE_202.fragmented_superpage)
when _T_2800 :
connect sectored_entries[0][6].valid[1], UInt<1>(0h0)
node _T_2801 = eq(sectored_entries[0][6].tag_v, hv_6)
node _T_2802 = and(_T_2801, _WIRE_204.fragmented_superpage)
when _T_2802 :
connect sectored_entries[0][6].valid[2], UInt<1>(0h0)
node _T_2803 = eq(sectored_entries[0][6].tag_v, hv_6)
node _T_2804 = and(_T_2803, _WIRE_206.fragmented_superpage)
when _T_2804 :
connect sectored_entries[0][6].valid[3], UInt<1>(0h0)
else :
node _T_2805 = eq(hg_6, UInt<1>(0h0))
node _T_2806 = and(_T_2805, io.sfence.bits.rs2)
when _T_2806 :
wire _WIRE_208 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_209 : UInt<42>
connect _WIRE_209, sectored_entries[0][6].data[0]
node _T_2807 = bits(_WIRE_209, 0, 0)
connect _WIRE_208.fragmented_superpage, _T_2807
node _T_2808 = bits(_WIRE_209, 1, 1)
connect _WIRE_208.c, _T_2808
node _T_2809 = bits(_WIRE_209, 2, 2)
connect _WIRE_208.eff, _T_2809
node _T_2810 = bits(_WIRE_209, 3, 3)
connect _WIRE_208.paa, _T_2810
node _T_2811 = bits(_WIRE_209, 4, 4)
connect _WIRE_208.pal, _T_2811
node _T_2812 = bits(_WIRE_209, 5, 5)
connect _WIRE_208.ppp, _T_2812
node _T_2813 = bits(_WIRE_209, 6, 6)
connect _WIRE_208.pr, _T_2813
node _T_2814 = bits(_WIRE_209, 7, 7)
connect _WIRE_208.px, _T_2814
node _T_2815 = bits(_WIRE_209, 8, 8)
connect _WIRE_208.pw, _T_2815
node _T_2816 = bits(_WIRE_209, 9, 9)
connect _WIRE_208.hr, _T_2816
node _T_2817 = bits(_WIRE_209, 10, 10)
connect _WIRE_208.hx, _T_2817
node _T_2818 = bits(_WIRE_209, 11, 11)
connect _WIRE_208.hw, _T_2818
node _T_2819 = bits(_WIRE_209, 12, 12)
connect _WIRE_208.sr, _T_2819
node _T_2820 = bits(_WIRE_209, 13, 13)
connect _WIRE_208.sx, _T_2820
node _T_2821 = bits(_WIRE_209, 14, 14)
connect _WIRE_208.sw, _T_2821
node _T_2822 = bits(_WIRE_209, 15, 15)
connect _WIRE_208.gf, _T_2822
node _T_2823 = bits(_WIRE_209, 16, 16)
connect _WIRE_208.pf, _T_2823
node _T_2824 = bits(_WIRE_209, 17, 17)
connect _WIRE_208.ae_stage2, _T_2824
node _T_2825 = bits(_WIRE_209, 18, 18)
connect _WIRE_208.ae_final, _T_2825
node _T_2826 = bits(_WIRE_209, 19, 19)
connect _WIRE_208.ae_ptw, _T_2826
node _T_2827 = bits(_WIRE_209, 20, 20)
connect _WIRE_208.g, _T_2827
node _T_2828 = bits(_WIRE_209, 21, 21)
connect _WIRE_208.u, _T_2828
node _T_2829 = bits(_WIRE_209, 41, 22)
connect _WIRE_208.ppn, _T_2829
wire _WIRE_210 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_211 : UInt<42>
connect _WIRE_211, sectored_entries[0][6].data[1]
node _T_2830 = bits(_WIRE_211, 0, 0)
connect _WIRE_210.fragmented_superpage, _T_2830
node _T_2831 = bits(_WIRE_211, 1, 1)
connect _WIRE_210.c, _T_2831
node _T_2832 = bits(_WIRE_211, 2, 2)
connect _WIRE_210.eff, _T_2832
node _T_2833 = bits(_WIRE_211, 3, 3)
connect _WIRE_210.paa, _T_2833
node _T_2834 = bits(_WIRE_211, 4, 4)
connect _WIRE_210.pal, _T_2834
node _T_2835 = bits(_WIRE_211, 5, 5)
connect _WIRE_210.ppp, _T_2835
node _T_2836 = bits(_WIRE_211, 6, 6)
connect _WIRE_210.pr, _T_2836
node _T_2837 = bits(_WIRE_211, 7, 7)
connect _WIRE_210.px, _T_2837
node _T_2838 = bits(_WIRE_211, 8, 8)
connect _WIRE_210.pw, _T_2838
node _T_2839 = bits(_WIRE_211, 9, 9)
connect _WIRE_210.hr, _T_2839
node _T_2840 = bits(_WIRE_211, 10, 10)
connect _WIRE_210.hx, _T_2840
node _T_2841 = bits(_WIRE_211, 11, 11)
connect _WIRE_210.hw, _T_2841
node _T_2842 = bits(_WIRE_211, 12, 12)
connect _WIRE_210.sr, _T_2842
node _T_2843 = bits(_WIRE_211, 13, 13)
connect _WIRE_210.sx, _T_2843
node _T_2844 = bits(_WIRE_211, 14, 14)
connect _WIRE_210.sw, _T_2844
node _T_2845 = bits(_WIRE_211, 15, 15)
connect _WIRE_210.gf, _T_2845
node _T_2846 = bits(_WIRE_211, 16, 16)
connect _WIRE_210.pf, _T_2846
node _T_2847 = bits(_WIRE_211, 17, 17)
connect _WIRE_210.ae_stage2, _T_2847
node _T_2848 = bits(_WIRE_211, 18, 18)
connect _WIRE_210.ae_final, _T_2848
node _T_2849 = bits(_WIRE_211, 19, 19)
connect _WIRE_210.ae_ptw, _T_2849
node _T_2850 = bits(_WIRE_211, 20, 20)
connect _WIRE_210.g, _T_2850
node _T_2851 = bits(_WIRE_211, 21, 21)
connect _WIRE_210.u, _T_2851
node _T_2852 = bits(_WIRE_211, 41, 22)
connect _WIRE_210.ppn, _T_2852
wire _WIRE_212 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_213 : UInt<42>
connect _WIRE_213, sectored_entries[0][6].data[2]
node _T_2853 = bits(_WIRE_213, 0, 0)
connect _WIRE_212.fragmented_superpage, _T_2853
node _T_2854 = bits(_WIRE_213, 1, 1)
connect _WIRE_212.c, _T_2854
node _T_2855 = bits(_WIRE_213, 2, 2)
connect _WIRE_212.eff, _T_2855
node _T_2856 = bits(_WIRE_213, 3, 3)
connect _WIRE_212.paa, _T_2856
node _T_2857 = bits(_WIRE_213, 4, 4)
connect _WIRE_212.pal, _T_2857
node _T_2858 = bits(_WIRE_213, 5, 5)
connect _WIRE_212.ppp, _T_2858
node _T_2859 = bits(_WIRE_213, 6, 6)
connect _WIRE_212.pr, _T_2859
node _T_2860 = bits(_WIRE_213, 7, 7)
connect _WIRE_212.px, _T_2860
node _T_2861 = bits(_WIRE_213, 8, 8)
connect _WIRE_212.pw, _T_2861
node _T_2862 = bits(_WIRE_213, 9, 9)
connect _WIRE_212.hr, _T_2862
node _T_2863 = bits(_WIRE_213, 10, 10)
connect _WIRE_212.hx, _T_2863
node _T_2864 = bits(_WIRE_213, 11, 11)
connect _WIRE_212.hw, _T_2864
node _T_2865 = bits(_WIRE_213, 12, 12)
connect _WIRE_212.sr, _T_2865
node _T_2866 = bits(_WIRE_213, 13, 13)
connect _WIRE_212.sx, _T_2866
node _T_2867 = bits(_WIRE_213, 14, 14)
connect _WIRE_212.sw, _T_2867
node _T_2868 = bits(_WIRE_213, 15, 15)
connect _WIRE_212.gf, _T_2868
node _T_2869 = bits(_WIRE_213, 16, 16)
connect _WIRE_212.pf, _T_2869
node _T_2870 = bits(_WIRE_213, 17, 17)
connect _WIRE_212.ae_stage2, _T_2870
node _T_2871 = bits(_WIRE_213, 18, 18)
connect _WIRE_212.ae_final, _T_2871
node _T_2872 = bits(_WIRE_213, 19, 19)
connect _WIRE_212.ae_ptw, _T_2872
node _T_2873 = bits(_WIRE_213, 20, 20)
connect _WIRE_212.g, _T_2873
node _T_2874 = bits(_WIRE_213, 21, 21)
connect _WIRE_212.u, _T_2874
node _T_2875 = bits(_WIRE_213, 41, 22)
connect _WIRE_212.ppn, _T_2875
wire _WIRE_214 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_215 : UInt<42>
connect _WIRE_215, sectored_entries[0][6].data[3]
node _T_2876 = bits(_WIRE_215, 0, 0)
connect _WIRE_214.fragmented_superpage, _T_2876
node _T_2877 = bits(_WIRE_215, 1, 1)
connect _WIRE_214.c, _T_2877
node _T_2878 = bits(_WIRE_215, 2, 2)
connect _WIRE_214.eff, _T_2878
node _T_2879 = bits(_WIRE_215, 3, 3)
connect _WIRE_214.paa, _T_2879
node _T_2880 = bits(_WIRE_215, 4, 4)
connect _WIRE_214.pal, _T_2880
node _T_2881 = bits(_WIRE_215, 5, 5)
connect _WIRE_214.ppp, _T_2881
node _T_2882 = bits(_WIRE_215, 6, 6)
connect _WIRE_214.pr, _T_2882
node _T_2883 = bits(_WIRE_215, 7, 7)
connect _WIRE_214.px, _T_2883
node _T_2884 = bits(_WIRE_215, 8, 8)
connect _WIRE_214.pw, _T_2884
node _T_2885 = bits(_WIRE_215, 9, 9)
connect _WIRE_214.hr, _T_2885
node _T_2886 = bits(_WIRE_215, 10, 10)
connect _WIRE_214.hx, _T_2886
node _T_2887 = bits(_WIRE_215, 11, 11)
connect _WIRE_214.hw, _T_2887
node _T_2888 = bits(_WIRE_215, 12, 12)
connect _WIRE_214.sr, _T_2888
node _T_2889 = bits(_WIRE_215, 13, 13)
connect _WIRE_214.sx, _T_2889
node _T_2890 = bits(_WIRE_215, 14, 14)
connect _WIRE_214.sw, _T_2890
node _T_2891 = bits(_WIRE_215, 15, 15)
connect _WIRE_214.gf, _T_2891
node _T_2892 = bits(_WIRE_215, 16, 16)
connect _WIRE_214.pf, _T_2892
node _T_2893 = bits(_WIRE_215, 17, 17)
connect _WIRE_214.ae_stage2, _T_2893
node _T_2894 = bits(_WIRE_215, 18, 18)
connect _WIRE_214.ae_final, _T_2894
node _T_2895 = bits(_WIRE_215, 19, 19)
connect _WIRE_214.ae_ptw, _T_2895
node _T_2896 = bits(_WIRE_215, 20, 20)
connect _WIRE_214.g, _T_2896
node _T_2897 = bits(_WIRE_215, 21, 21)
connect _WIRE_214.u, _T_2897
node _T_2898 = bits(_WIRE_215, 41, 22)
connect _WIRE_214.ppn, _T_2898
node _T_2899 = eq(sectored_entries[0][6].tag_v, hv_6)
node _T_2900 = eq(_WIRE_208.g, UInt<1>(0h0))
node _T_2901 = and(_T_2899, _T_2900)
when _T_2901 :
connect sectored_entries[0][6].valid[0], UInt<1>(0h0)
node _T_2902 = eq(sectored_entries[0][6].tag_v, hv_6)
node _T_2903 = eq(_WIRE_210.g, UInt<1>(0h0))
node _T_2904 = and(_T_2902, _T_2903)
when _T_2904 :
connect sectored_entries[0][6].valid[1], UInt<1>(0h0)
node _T_2905 = eq(sectored_entries[0][6].tag_v, hv_6)
node _T_2906 = eq(_WIRE_212.g, UInt<1>(0h0))
node _T_2907 = and(_T_2905, _T_2906)
when _T_2907 :
connect sectored_entries[0][6].valid[2], UInt<1>(0h0)
node _T_2908 = eq(sectored_entries[0][6].tag_v, hv_6)
node _T_2909 = eq(_WIRE_214.g, UInt<1>(0h0))
node _T_2910 = and(_T_2908, _T_2909)
when _T_2910 :
connect sectored_entries[0][6].valid[3], UInt<1>(0h0)
else :
node _T_2911 = or(hv_6, hg_6)
wire _WIRE_216 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_217 : UInt<42>
connect _WIRE_217, sectored_entries[0][6].data[0]
node _T_2912 = bits(_WIRE_217, 0, 0)
connect _WIRE_216.fragmented_superpage, _T_2912
node _T_2913 = bits(_WIRE_217, 1, 1)
connect _WIRE_216.c, _T_2913
node _T_2914 = bits(_WIRE_217, 2, 2)
connect _WIRE_216.eff, _T_2914
node _T_2915 = bits(_WIRE_217, 3, 3)
connect _WIRE_216.paa, _T_2915
node _T_2916 = bits(_WIRE_217, 4, 4)
connect _WIRE_216.pal, _T_2916
node _T_2917 = bits(_WIRE_217, 5, 5)
connect _WIRE_216.ppp, _T_2917
node _T_2918 = bits(_WIRE_217, 6, 6)
connect _WIRE_216.pr, _T_2918
node _T_2919 = bits(_WIRE_217, 7, 7)
connect _WIRE_216.px, _T_2919
node _T_2920 = bits(_WIRE_217, 8, 8)
connect _WIRE_216.pw, _T_2920
node _T_2921 = bits(_WIRE_217, 9, 9)
connect _WIRE_216.hr, _T_2921
node _T_2922 = bits(_WIRE_217, 10, 10)
connect _WIRE_216.hx, _T_2922
node _T_2923 = bits(_WIRE_217, 11, 11)
connect _WIRE_216.hw, _T_2923
node _T_2924 = bits(_WIRE_217, 12, 12)
connect _WIRE_216.sr, _T_2924
node _T_2925 = bits(_WIRE_217, 13, 13)
connect _WIRE_216.sx, _T_2925
node _T_2926 = bits(_WIRE_217, 14, 14)
connect _WIRE_216.sw, _T_2926
node _T_2927 = bits(_WIRE_217, 15, 15)
connect _WIRE_216.gf, _T_2927
node _T_2928 = bits(_WIRE_217, 16, 16)
connect _WIRE_216.pf, _T_2928
node _T_2929 = bits(_WIRE_217, 17, 17)
connect _WIRE_216.ae_stage2, _T_2929
node _T_2930 = bits(_WIRE_217, 18, 18)
connect _WIRE_216.ae_final, _T_2930
node _T_2931 = bits(_WIRE_217, 19, 19)
connect _WIRE_216.ae_ptw, _T_2931
node _T_2932 = bits(_WIRE_217, 20, 20)
connect _WIRE_216.g, _T_2932
node _T_2933 = bits(_WIRE_217, 21, 21)
connect _WIRE_216.u, _T_2933
node _T_2934 = bits(_WIRE_217, 41, 22)
connect _WIRE_216.ppn, _T_2934
wire _WIRE_218 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_219 : UInt<42>
connect _WIRE_219, sectored_entries[0][6].data[1]
node _T_2935 = bits(_WIRE_219, 0, 0)
connect _WIRE_218.fragmented_superpage, _T_2935
node _T_2936 = bits(_WIRE_219, 1, 1)
connect _WIRE_218.c, _T_2936
node _T_2937 = bits(_WIRE_219, 2, 2)
connect _WIRE_218.eff, _T_2937
node _T_2938 = bits(_WIRE_219, 3, 3)
connect _WIRE_218.paa, _T_2938
node _T_2939 = bits(_WIRE_219, 4, 4)
connect _WIRE_218.pal, _T_2939
node _T_2940 = bits(_WIRE_219, 5, 5)
connect _WIRE_218.ppp, _T_2940
node _T_2941 = bits(_WIRE_219, 6, 6)
connect _WIRE_218.pr, _T_2941
node _T_2942 = bits(_WIRE_219, 7, 7)
connect _WIRE_218.px, _T_2942
node _T_2943 = bits(_WIRE_219, 8, 8)
connect _WIRE_218.pw, _T_2943
node _T_2944 = bits(_WIRE_219, 9, 9)
connect _WIRE_218.hr, _T_2944
node _T_2945 = bits(_WIRE_219, 10, 10)
connect _WIRE_218.hx, _T_2945
node _T_2946 = bits(_WIRE_219, 11, 11)
connect _WIRE_218.hw, _T_2946
node _T_2947 = bits(_WIRE_219, 12, 12)
connect _WIRE_218.sr, _T_2947
node _T_2948 = bits(_WIRE_219, 13, 13)
connect _WIRE_218.sx, _T_2948
node _T_2949 = bits(_WIRE_219, 14, 14)
connect _WIRE_218.sw, _T_2949
node _T_2950 = bits(_WIRE_219, 15, 15)
connect _WIRE_218.gf, _T_2950
node _T_2951 = bits(_WIRE_219, 16, 16)
connect _WIRE_218.pf, _T_2951
node _T_2952 = bits(_WIRE_219, 17, 17)
connect _WIRE_218.ae_stage2, _T_2952
node _T_2953 = bits(_WIRE_219, 18, 18)
connect _WIRE_218.ae_final, _T_2953
node _T_2954 = bits(_WIRE_219, 19, 19)
connect _WIRE_218.ae_ptw, _T_2954
node _T_2955 = bits(_WIRE_219, 20, 20)
connect _WIRE_218.g, _T_2955
node _T_2956 = bits(_WIRE_219, 21, 21)
connect _WIRE_218.u, _T_2956
node _T_2957 = bits(_WIRE_219, 41, 22)
connect _WIRE_218.ppn, _T_2957
wire _WIRE_220 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_221 : UInt<42>
connect _WIRE_221, sectored_entries[0][6].data[2]
node _T_2958 = bits(_WIRE_221, 0, 0)
connect _WIRE_220.fragmented_superpage, _T_2958
node _T_2959 = bits(_WIRE_221, 1, 1)
connect _WIRE_220.c, _T_2959
node _T_2960 = bits(_WIRE_221, 2, 2)
connect _WIRE_220.eff, _T_2960
node _T_2961 = bits(_WIRE_221, 3, 3)
connect _WIRE_220.paa, _T_2961
node _T_2962 = bits(_WIRE_221, 4, 4)
connect _WIRE_220.pal, _T_2962
node _T_2963 = bits(_WIRE_221, 5, 5)
connect _WIRE_220.ppp, _T_2963
node _T_2964 = bits(_WIRE_221, 6, 6)
connect _WIRE_220.pr, _T_2964
node _T_2965 = bits(_WIRE_221, 7, 7)
connect _WIRE_220.px, _T_2965
node _T_2966 = bits(_WIRE_221, 8, 8)
connect _WIRE_220.pw, _T_2966
node _T_2967 = bits(_WIRE_221, 9, 9)
connect _WIRE_220.hr, _T_2967
node _T_2968 = bits(_WIRE_221, 10, 10)
connect _WIRE_220.hx, _T_2968
node _T_2969 = bits(_WIRE_221, 11, 11)
connect _WIRE_220.hw, _T_2969
node _T_2970 = bits(_WIRE_221, 12, 12)
connect _WIRE_220.sr, _T_2970
node _T_2971 = bits(_WIRE_221, 13, 13)
connect _WIRE_220.sx, _T_2971
node _T_2972 = bits(_WIRE_221, 14, 14)
connect _WIRE_220.sw, _T_2972
node _T_2973 = bits(_WIRE_221, 15, 15)
connect _WIRE_220.gf, _T_2973
node _T_2974 = bits(_WIRE_221, 16, 16)
connect _WIRE_220.pf, _T_2974
node _T_2975 = bits(_WIRE_221, 17, 17)
connect _WIRE_220.ae_stage2, _T_2975
node _T_2976 = bits(_WIRE_221, 18, 18)
connect _WIRE_220.ae_final, _T_2976
node _T_2977 = bits(_WIRE_221, 19, 19)
connect _WIRE_220.ae_ptw, _T_2977
node _T_2978 = bits(_WIRE_221, 20, 20)
connect _WIRE_220.g, _T_2978
node _T_2979 = bits(_WIRE_221, 21, 21)
connect _WIRE_220.u, _T_2979
node _T_2980 = bits(_WIRE_221, 41, 22)
connect _WIRE_220.ppn, _T_2980
wire _WIRE_222 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_223 : UInt<42>
connect _WIRE_223, sectored_entries[0][6].data[3]
node _T_2981 = bits(_WIRE_223, 0, 0)
connect _WIRE_222.fragmented_superpage, _T_2981
node _T_2982 = bits(_WIRE_223, 1, 1)
connect _WIRE_222.c, _T_2982
node _T_2983 = bits(_WIRE_223, 2, 2)
connect _WIRE_222.eff, _T_2983
node _T_2984 = bits(_WIRE_223, 3, 3)
connect _WIRE_222.paa, _T_2984
node _T_2985 = bits(_WIRE_223, 4, 4)
connect _WIRE_222.pal, _T_2985
node _T_2986 = bits(_WIRE_223, 5, 5)
connect _WIRE_222.ppp, _T_2986
node _T_2987 = bits(_WIRE_223, 6, 6)
connect _WIRE_222.pr, _T_2987
node _T_2988 = bits(_WIRE_223, 7, 7)
connect _WIRE_222.px, _T_2988
node _T_2989 = bits(_WIRE_223, 8, 8)
connect _WIRE_222.pw, _T_2989
node _T_2990 = bits(_WIRE_223, 9, 9)
connect _WIRE_222.hr, _T_2990
node _T_2991 = bits(_WIRE_223, 10, 10)
connect _WIRE_222.hx, _T_2991
node _T_2992 = bits(_WIRE_223, 11, 11)
connect _WIRE_222.hw, _T_2992
node _T_2993 = bits(_WIRE_223, 12, 12)
connect _WIRE_222.sr, _T_2993
node _T_2994 = bits(_WIRE_223, 13, 13)
connect _WIRE_222.sx, _T_2994
node _T_2995 = bits(_WIRE_223, 14, 14)
connect _WIRE_222.sw, _T_2995
node _T_2996 = bits(_WIRE_223, 15, 15)
connect _WIRE_222.gf, _T_2996
node _T_2997 = bits(_WIRE_223, 16, 16)
connect _WIRE_222.pf, _T_2997
node _T_2998 = bits(_WIRE_223, 17, 17)
connect _WIRE_222.ae_stage2, _T_2998
node _T_2999 = bits(_WIRE_223, 18, 18)
connect _WIRE_222.ae_final, _T_2999
node _T_3000 = bits(_WIRE_223, 19, 19)
connect _WIRE_222.ae_ptw, _T_3000
node _T_3001 = bits(_WIRE_223, 20, 20)
connect _WIRE_222.g, _T_3001
node _T_3002 = bits(_WIRE_223, 21, 21)
connect _WIRE_222.u, _T_3002
node _T_3003 = bits(_WIRE_223, 41, 22)
connect _WIRE_222.ppn, _T_3003
node _T_3004 = eq(sectored_entries[0][6].tag_v, _T_2911)
when _T_3004 :
connect sectored_entries[0][6].valid[0], UInt<1>(0h0)
node _T_3005 = eq(sectored_entries[0][6].tag_v, _T_2911)
when _T_3005 :
connect sectored_entries[0][6].valid[1], UInt<1>(0h0)
node _T_3006 = eq(sectored_entries[0][6].tag_v, _T_2911)
when _T_3006 :
connect sectored_entries[0][6].valid[2], UInt<1>(0h0)
node _T_3007 = eq(sectored_entries[0][6].tag_v, _T_2911)
when _T_3007 :
connect sectored_entries[0][6].valid[3], UInt<1>(0h0)
node hv_7 = and(UInt<1>(0h0), io.sfence.bits.hv)
node hg_7 = and(UInt<1>(0h0), io.sfence.bits.hg)
node _T_3008 = eq(hg_7, UInt<1>(0h0))
node _T_3009 = and(_T_3008, io.sfence.bits.rs1)
when _T_3009 :
node _T_3010 = xor(sectored_entries[0][7].tag_vpn, vpn)
node _T_3011 = shr(_T_3010, 2)
node _T_3012 = eq(_T_3011, UInt<1>(0h0))
node _T_3013 = eq(sectored_entries[0][7].tag_v, hv_7)
node _T_3014 = and(_T_3012, _T_3013)
when _T_3014 :
wire _WIRE_224 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_225 : UInt<42>
connect _WIRE_225, sectored_entries[0][7].data[0]
node _T_3015 = bits(_WIRE_225, 0, 0)
connect _WIRE_224.fragmented_superpage, _T_3015
node _T_3016 = bits(_WIRE_225, 1, 1)
connect _WIRE_224.c, _T_3016
node _T_3017 = bits(_WIRE_225, 2, 2)
connect _WIRE_224.eff, _T_3017
node _T_3018 = bits(_WIRE_225, 3, 3)
connect _WIRE_224.paa, _T_3018
node _T_3019 = bits(_WIRE_225, 4, 4)
connect _WIRE_224.pal, _T_3019
node _T_3020 = bits(_WIRE_225, 5, 5)
connect _WIRE_224.ppp, _T_3020
node _T_3021 = bits(_WIRE_225, 6, 6)
connect _WIRE_224.pr, _T_3021
node _T_3022 = bits(_WIRE_225, 7, 7)
connect _WIRE_224.px, _T_3022
node _T_3023 = bits(_WIRE_225, 8, 8)
connect _WIRE_224.pw, _T_3023
node _T_3024 = bits(_WIRE_225, 9, 9)
connect _WIRE_224.hr, _T_3024
node _T_3025 = bits(_WIRE_225, 10, 10)
connect _WIRE_224.hx, _T_3025
node _T_3026 = bits(_WIRE_225, 11, 11)
connect _WIRE_224.hw, _T_3026
node _T_3027 = bits(_WIRE_225, 12, 12)
connect _WIRE_224.sr, _T_3027
node _T_3028 = bits(_WIRE_225, 13, 13)
connect _WIRE_224.sx, _T_3028
node _T_3029 = bits(_WIRE_225, 14, 14)
connect _WIRE_224.sw, _T_3029
node _T_3030 = bits(_WIRE_225, 15, 15)
connect _WIRE_224.gf, _T_3030
node _T_3031 = bits(_WIRE_225, 16, 16)
connect _WIRE_224.pf, _T_3031
node _T_3032 = bits(_WIRE_225, 17, 17)
connect _WIRE_224.ae_stage2, _T_3032
node _T_3033 = bits(_WIRE_225, 18, 18)
connect _WIRE_224.ae_final, _T_3033
node _T_3034 = bits(_WIRE_225, 19, 19)
connect _WIRE_224.ae_ptw, _T_3034
node _T_3035 = bits(_WIRE_225, 20, 20)
connect _WIRE_224.g, _T_3035
node _T_3036 = bits(_WIRE_225, 21, 21)
connect _WIRE_224.u, _T_3036
node _T_3037 = bits(_WIRE_225, 41, 22)
connect _WIRE_224.ppn, _T_3037
wire _WIRE_226 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_227 : UInt<42>
connect _WIRE_227, sectored_entries[0][7].data[1]
node _T_3038 = bits(_WIRE_227, 0, 0)
connect _WIRE_226.fragmented_superpage, _T_3038
node _T_3039 = bits(_WIRE_227, 1, 1)
connect _WIRE_226.c, _T_3039
node _T_3040 = bits(_WIRE_227, 2, 2)
connect _WIRE_226.eff, _T_3040
node _T_3041 = bits(_WIRE_227, 3, 3)
connect _WIRE_226.paa, _T_3041
node _T_3042 = bits(_WIRE_227, 4, 4)
connect _WIRE_226.pal, _T_3042
node _T_3043 = bits(_WIRE_227, 5, 5)
connect _WIRE_226.ppp, _T_3043
node _T_3044 = bits(_WIRE_227, 6, 6)
connect _WIRE_226.pr, _T_3044
node _T_3045 = bits(_WIRE_227, 7, 7)
connect _WIRE_226.px, _T_3045
node _T_3046 = bits(_WIRE_227, 8, 8)
connect _WIRE_226.pw, _T_3046
node _T_3047 = bits(_WIRE_227, 9, 9)
connect _WIRE_226.hr, _T_3047
node _T_3048 = bits(_WIRE_227, 10, 10)
connect _WIRE_226.hx, _T_3048
node _T_3049 = bits(_WIRE_227, 11, 11)
connect _WIRE_226.hw, _T_3049
node _T_3050 = bits(_WIRE_227, 12, 12)
connect _WIRE_226.sr, _T_3050
node _T_3051 = bits(_WIRE_227, 13, 13)
connect _WIRE_226.sx, _T_3051
node _T_3052 = bits(_WIRE_227, 14, 14)
connect _WIRE_226.sw, _T_3052
node _T_3053 = bits(_WIRE_227, 15, 15)
connect _WIRE_226.gf, _T_3053
node _T_3054 = bits(_WIRE_227, 16, 16)
connect _WIRE_226.pf, _T_3054
node _T_3055 = bits(_WIRE_227, 17, 17)
connect _WIRE_226.ae_stage2, _T_3055
node _T_3056 = bits(_WIRE_227, 18, 18)
connect _WIRE_226.ae_final, _T_3056
node _T_3057 = bits(_WIRE_227, 19, 19)
connect _WIRE_226.ae_ptw, _T_3057
node _T_3058 = bits(_WIRE_227, 20, 20)
connect _WIRE_226.g, _T_3058
node _T_3059 = bits(_WIRE_227, 21, 21)
connect _WIRE_226.u, _T_3059
node _T_3060 = bits(_WIRE_227, 41, 22)
connect _WIRE_226.ppn, _T_3060
wire _WIRE_228 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_229 : UInt<42>
connect _WIRE_229, sectored_entries[0][7].data[2]
node _T_3061 = bits(_WIRE_229, 0, 0)
connect _WIRE_228.fragmented_superpage, _T_3061
node _T_3062 = bits(_WIRE_229, 1, 1)
connect _WIRE_228.c, _T_3062
node _T_3063 = bits(_WIRE_229, 2, 2)
connect _WIRE_228.eff, _T_3063
node _T_3064 = bits(_WIRE_229, 3, 3)
connect _WIRE_228.paa, _T_3064
node _T_3065 = bits(_WIRE_229, 4, 4)
connect _WIRE_228.pal, _T_3065
node _T_3066 = bits(_WIRE_229, 5, 5)
connect _WIRE_228.ppp, _T_3066
node _T_3067 = bits(_WIRE_229, 6, 6)
connect _WIRE_228.pr, _T_3067
node _T_3068 = bits(_WIRE_229, 7, 7)
connect _WIRE_228.px, _T_3068
node _T_3069 = bits(_WIRE_229, 8, 8)
connect _WIRE_228.pw, _T_3069
node _T_3070 = bits(_WIRE_229, 9, 9)
connect _WIRE_228.hr, _T_3070
node _T_3071 = bits(_WIRE_229, 10, 10)
connect _WIRE_228.hx, _T_3071
node _T_3072 = bits(_WIRE_229, 11, 11)
connect _WIRE_228.hw, _T_3072
node _T_3073 = bits(_WIRE_229, 12, 12)
connect _WIRE_228.sr, _T_3073
node _T_3074 = bits(_WIRE_229, 13, 13)
connect _WIRE_228.sx, _T_3074
node _T_3075 = bits(_WIRE_229, 14, 14)
connect _WIRE_228.sw, _T_3075
node _T_3076 = bits(_WIRE_229, 15, 15)
connect _WIRE_228.gf, _T_3076
node _T_3077 = bits(_WIRE_229, 16, 16)
connect _WIRE_228.pf, _T_3077
node _T_3078 = bits(_WIRE_229, 17, 17)
connect _WIRE_228.ae_stage2, _T_3078
node _T_3079 = bits(_WIRE_229, 18, 18)
connect _WIRE_228.ae_final, _T_3079
node _T_3080 = bits(_WIRE_229, 19, 19)
connect _WIRE_228.ae_ptw, _T_3080
node _T_3081 = bits(_WIRE_229, 20, 20)
connect _WIRE_228.g, _T_3081
node _T_3082 = bits(_WIRE_229, 21, 21)
connect _WIRE_228.u, _T_3082
node _T_3083 = bits(_WIRE_229, 41, 22)
connect _WIRE_228.ppn, _T_3083
wire _WIRE_230 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_231 : UInt<42>
connect _WIRE_231, sectored_entries[0][7].data[3]
node _T_3084 = bits(_WIRE_231, 0, 0)
connect _WIRE_230.fragmented_superpage, _T_3084
node _T_3085 = bits(_WIRE_231, 1, 1)
connect _WIRE_230.c, _T_3085
node _T_3086 = bits(_WIRE_231, 2, 2)
connect _WIRE_230.eff, _T_3086
node _T_3087 = bits(_WIRE_231, 3, 3)
connect _WIRE_230.paa, _T_3087
node _T_3088 = bits(_WIRE_231, 4, 4)
connect _WIRE_230.pal, _T_3088
node _T_3089 = bits(_WIRE_231, 5, 5)
connect _WIRE_230.ppp, _T_3089
node _T_3090 = bits(_WIRE_231, 6, 6)
connect _WIRE_230.pr, _T_3090
node _T_3091 = bits(_WIRE_231, 7, 7)
connect _WIRE_230.px, _T_3091
node _T_3092 = bits(_WIRE_231, 8, 8)
connect _WIRE_230.pw, _T_3092
node _T_3093 = bits(_WIRE_231, 9, 9)
connect _WIRE_230.hr, _T_3093
node _T_3094 = bits(_WIRE_231, 10, 10)
connect _WIRE_230.hx, _T_3094
node _T_3095 = bits(_WIRE_231, 11, 11)
connect _WIRE_230.hw, _T_3095
node _T_3096 = bits(_WIRE_231, 12, 12)
connect _WIRE_230.sr, _T_3096
node _T_3097 = bits(_WIRE_231, 13, 13)
connect _WIRE_230.sx, _T_3097
node _T_3098 = bits(_WIRE_231, 14, 14)
connect _WIRE_230.sw, _T_3098
node _T_3099 = bits(_WIRE_231, 15, 15)
connect _WIRE_230.gf, _T_3099
node _T_3100 = bits(_WIRE_231, 16, 16)
connect _WIRE_230.pf, _T_3100
node _T_3101 = bits(_WIRE_231, 17, 17)
connect _WIRE_230.ae_stage2, _T_3101
node _T_3102 = bits(_WIRE_231, 18, 18)
connect _WIRE_230.ae_final, _T_3102
node _T_3103 = bits(_WIRE_231, 19, 19)
connect _WIRE_230.ae_ptw, _T_3103
node _T_3104 = bits(_WIRE_231, 20, 20)
connect _WIRE_230.g, _T_3104
node _T_3105 = bits(_WIRE_231, 21, 21)
connect _WIRE_230.u, _T_3105
node _T_3106 = bits(_WIRE_231, 41, 22)
connect _WIRE_230.ppn, _T_3106
node _T_3107 = eq(sectored_entries[0][7].tag_v, hv_7)
node _T_3108 = bits(vpn, 1, 0)
node _T_3109 = eq(UInt<1>(0h0), _T_3108)
node _T_3110 = and(_T_3107, _T_3109)
when _T_3110 :
connect sectored_entries[0][7].valid[0], UInt<1>(0h0)
node _T_3111 = eq(sectored_entries[0][7].tag_v, hv_7)
node _T_3112 = bits(vpn, 1, 0)
node _T_3113 = eq(UInt<1>(0h1), _T_3112)
node _T_3114 = and(_T_3111, _T_3113)
when _T_3114 :
connect sectored_entries[0][7].valid[1], UInt<1>(0h0)
node _T_3115 = eq(sectored_entries[0][7].tag_v, hv_7)
node _T_3116 = bits(vpn, 1, 0)
node _T_3117 = eq(UInt<2>(0h2), _T_3116)
node _T_3118 = and(_T_3115, _T_3117)
when _T_3118 :
connect sectored_entries[0][7].valid[2], UInt<1>(0h0)
node _T_3119 = eq(sectored_entries[0][7].tag_v, hv_7)
node _T_3120 = bits(vpn, 1, 0)
node _T_3121 = eq(UInt<2>(0h3), _T_3120)
node _T_3122 = and(_T_3119, _T_3121)
when _T_3122 :
connect sectored_entries[0][7].valid[3], UInt<1>(0h0)
node _T_3123 = xor(sectored_entries[0][7].tag_vpn, vpn)
node _T_3124 = shr(_T_3123, 18)
node _T_3125 = eq(_T_3124, UInt<1>(0h0))
when _T_3125 :
wire _WIRE_232 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_233 : UInt<42>
connect _WIRE_233, sectored_entries[0][7].data[0]
node _T_3126 = bits(_WIRE_233, 0, 0)
connect _WIRE_232.fragmented_superpage, _T_3126
node _T_3127 = bits(_WIRE_233, 1, 1)
connect _WIRE_232.c, _T_3127
node _T_3128 = bits(_WIRE_233, 2, 2)
connect _WIRE_232.eff, _T_3128
node _T_3129 = bits(_WIRE_233, 3, 3)
connect _WIRE_232.paa, _T_3129
node _T_3130 = bits(_WIRE_233, 4, 4)
connect _WIRE_232.pal, _T_3130
node _T_3131 = bits(_WIRE_233, 5, 5)
connect _WIRE_232.ppp, _T_3131
node _T_3132 = bits(_WIRE_233, 6, 6)
connect _WIRE_232.pr, _T_3132
node _T_3133 = bits(_WIRE_233, 7, 7)
connect _WIRE_232.px, _T_3133
node _T_3134 = bits(_WIRE_233, 8, 8)
connect _WIRE_232.pw, _T_3134
node _T_3135 = bits(_WIRE_233, 9, 9)
connect _WIRE_232.hr, _T_3135
node _T_3136 = bits(_WIRE_233, 10, 10)
connect _WIRE_232.hx, _T_3136
node _T_3137 = bits(_WIRE_233, 11, 11)
connect _WIRE_232.hw, _T_3137
node _T_3138 = bits(_WIRE_233, 12, 12)
connect _WIRE_232.sr, _T_3138
node _T_3139 = bits(_WIRE_233, 13, 13)
connect _WIRE_232.sx, _T_3139
node _T_3140 = bits(_WIRE_233, 14, 14)
connect _WIRE_232.sw, _T_3140
node _T_3141 = bits(_WIRE_233, 15, 15)
connect _WIRE_232.gf, _T_3141
node _T_3142 = bits(_WIRE_233, 16, 16)
connect _WIRE_232.pf, _T_3142
node _T_3143 = bits(_WIRE_233, 17, 17)
connect _WIRE_232.ae_stage2, _T_3143
node _T_3144 = bits(_WIRE_233, 18, 18)
connect _WIRE_232.ae_final, _T_3144
node _T_3145 = bits(_WIRE_233, 19, 19)
connect _WIRE_232.ae_ptw, _T_3145
node _T_3146 = bits(_WIRE_233, 20, 20)
connect _WIRE_232.g, _T_3146
node _T_3147 = bits(_WIRE_233, 21, 21)
connect _WIRE_232.u, _T_3147
node _T_3148 = bits(_WIRE_233, 41, 22)
connect _WIRE_232.ppn, _T_3148
wire _WIRE_234 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_235 : UInt<42>
connect _WIRE_235, sectored_entries[0][7].data[1]
node _T_3149 = bits(_WIRE_235, 0, 0)
connect _WIRE_234.fragmented_superpage, _T_3149
node _T_3150 = bits(_WIRE_235, 1, 1)
connect _WIRE_234.c, _T_3150
node _T_3151 = bits(_WIRE_235, 2, 2)
connect _WIRE_234.eff, _T_3151
node _T_3152 = bits(_WIRE_235, 3, 3)
connect _WIRE_234.paa, _T_3152
node _T_3153 = bits(_WIRE_235, 4, 4)
connect _WIRE_234.pal, _T_3153
node _T_3154 = bits(_WIRE_235, 5, 5)
connect _WIRE_234.ppp, _T_3154
node _T_3155 = bits(_WIRE_235, 6, 6)
connect _WIRE_234.pr, _T_3155
node _T_3156 = bits(_WIRE_235, 7, 7)
connect _WIRE_234.px, _T_3156
node _T_3157 = bits(_WIRE_235, 8, 8)
connect _WIRE_234.pw, _T_3157
node _T_3158 = bits(_WIRE_235, 9, 9)
connect _WIRE_234.hr, _T_3158
node _T_3159 = bits(_WIRE_235, 10, 10)
connect _WIRE_234.hx, _T_3159
node _T_3160 = bits(_WIRE_235, 11, 11)
connect _WIRE_234.hw, _T_3160
node _T_3161 = bits(_WIRE_235, 12, 12)
connect _WIRE_234.sr, _T_3161
node _T_3162 = bits(_WIRE_235, 13, 13)
connect _WIRE_234.sx, _T_3162
node _T_3163 = bits(_WIRE_235, 14, 14)
connect _WIRE_234.sw, _T_3163
node _T_3164 = bits(_WIRE_235, 15, 15)
connect _WIRE_234.gf, _T_3164
node _T_3165 = bits(_WIRE_235, 16, 16)
connect _WIRE_234.pf, _T_3165
node _T_3166 = bits(_WIRE_235, 17, 17)
connect _WIRE_234.ae_stage2, _T_3166
node _T_3167 = bits(_WIRE_235, 18, 18)
connect _WIRE_234.ae_final, _T_3167
node _T_3168 = bits(_WIRE_235, 19, 19)
connect _WIRE_234.ae_ptw, _T_3168
node _T_3169 = bits(_WIRE_235, 20, 20)
connect _WIRE_234.g, _T_3169
node _T_3170 = bits(_WIRE_235, 21, 21)
connect _WIRE_234.u, _T_3170
node _T_3171 = bits(_WIRE_235, 41, 22)
connect _WIRE_234.ppn, _T_3171
wire _WIRE_236 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_237 : UInt<42>
connect _WIRE_237, sectored_entries[0][7].data[2]
node _T_3172 = bits(_WIRE_237, 0, 0)
connect _WIRE_236.fragmented_superpage, _T_3172
node _T_3173 = bits(_WIRE_237, 1, 1)
connect _WIRE_236.c, _T_3173
node _T_3174 = bits(_WIRE_237, 2, 2)
connect _WIRE_236.eff, _T_3174
node _T_3175 = bits(_WIRE_237, 3, 3)
connect _WIRE_236.paa, _T_3175
node _T_3176 = bits(_WIRE_237, 4, 4)
connect _WIRE_236.pal, _T_3176
node _T_3177 = bits(_WIRE_237, 5, 5)
connect _WIRE_236.ppp, _T_3177
node _T_3178 = bits(_WIRE_237, 6, 6)
connect _WIRE_236.pr, _T_3178
node _T_3179 = bits(_WIRE_237, 7, 7)
connect _WIRE_236.px, _T_3179
node _T_3180 = bits(_WIRE_237, 8, 8)
connect _WIRE_236.pw, _T_3180
node _T_3181 = bits(_WIRE_237, 9, 9)
connect _WIRE_236.hr, _T_3181
node _T_3182 = bits(_WIRE_237, 10, 10)
connect _WIRE_236.hx, _T_3182
node _T_3183 = bits(_WIRE_237, 11, 11)
connect _WIRE_236.hw, _T_3183
node _T_3184 = bits(_WIRE_237, 12, 12)
connect _WIRE_236.sr, _T_3184
node _T_3185 = bits(_WIRE_237, 13, 13)
connect _WIRE_236.sx, _T_3185
node _T_3186 = bits(_WIRE_237, 14, 14)
connect _WIRE_236.sw, _T_3186
node _T_3187 = bits(_WIRE_237, 15, 15)
connect _WIRE_236.gf, _T_3187
node _T_3188 = bits(_WIRE_237, 16, 16)
connect _WIRE_236.pf, _T_3188
node _T_3189 = bits(_WIRE_237, 17, 17)
connect _WIRE_236.ae_stage2, _T_3189
node _T_3190 = bits(_WIRE_237, 18, 18)
connect _WIRE_236.ae_final, _T_3190
node _T_3191 = bits(_WIRE_237, 19, 19)
connect _WIRE_236.ae_ptw, _T_3191
node _T_3192 = bits(_WIRE_237, 20, 20)
connect _WIRE_236.g, _T_3192
node _T_3193 = bits(_WIRE_237, 21, 21)
connect _WIRE_236.u, _T_3193
node _T_3194 = bits(_WIRE_237, 41, 22)
connect _WIRE_236.ppn, _T_3194
wire _WIRE_238 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_239 : UInt<42>
connect _WIRE_239, sectored_entries[0][7].data[3]
node _T_3195 = bits(_WIRE_239, 0, 0)
connect _WIRE_238.fragmented_superpage, _T_3195
node _T_3196 = bits(_WIRE_239, 1, 1)
connect _WIRE_238.c, _T_3196
node _T_3197 = bits(_WIRE_239, 2, 2)
connect _WIRE_238.eff, _T_3197
node _T_3198 = bits(_WIRE_239, 3, 3)
connect _WIRE_238.paa, _T_3198
node _T_3199 = bits(_WIRE_239, 4, 4)
connect _WIRE_238.pal, _T_3199
node _T_3200 = bits(_WIRE_239, 5, 5)
connect _WIRE_238.ppp, _T_3200
node _T_3201 = bits(_WIRE_239, 6, 6)
connect _WIRE_238.pr, _T_3201
node _T_3202 = bits(_WIRE_239, 7, 7)
connect _WIRE_238.px, _T_3202
node _T_3203 = bits(_WIRE_239, 8, 8)
connect _WIRE_238.pw, _T_3203
node _T_3204 = bits(_WIRE_239, 9, 9)
connect _WIRE_238.hr, _T_3204
node _T_3205 = bits(_WIRE_239, 10, 10)
connect _WIRE_238.hx, _T_3205
node _T_3206 = bits(_WIRE_239, 11, 11)
connect _WIRE_238.hw, _T_3206
node _T_3207 = bits(_WIRE_239, 12, 12)
connect _WIRE_238.sr, _T_3207
node _T_3208 = bits(_WIRE_239, 13, 13)
connect _WIRE_238.sx, _T_3208
node _T_3209 = bits(_WIRE_239, 14, 14)
connect _WIRE_238.sw, _T_3209
node _T_3210 = bits(_WIRE_239, 15, 15)
connect _WIRE_238.gf, _T_3210
node _T_3211 = bits(_WIRE_239, 16, 16)
connect _WIRE_238.pf, _T_3211
node _T_3212 = bits(_WIRE_239, 17, 17)
connect _WIRE_238.ae_stage2, _T_3212
node _T_3213 = bits(_WIRE_239, 18, 18)
connect _WIRE_238.ae_final, _T_3213
node _T_3214 = bits(_WIRE_239, 19, 19)
connect _WIRE_238.ae_ptw, _T_3214
node _T_3215 = bits(_WIRE_239, 20, 20)
connect _WIRE_238.g, _T_3215
node _T_3216 = bits(_WIRE_239, 21, 21)
connect _WIRE_238.u, _T_3216
node _T_3217 = bits(_WIRE_239, 41, 22)
connect _WIRE_238.ppn, _T_3217
node _T_3218 = eq(sectored_entries[0][7].tag_v, hv_7)
node _T_3219 = and(_T_3218, _WIRE_232.fragmented_superpage)
when _T_3219 :
connect sectored_entries[0][7].valid[0], UInt<1>(0h0)
node _T_3220 = eq(sectored_entries[0][7].tag_v, hv_7)
node _T_3221 = and(_T_3220, _WIRE_234.fragmented_superpage)
when _T_3221 :
connect sectored_entries[0][7].valid[1], UInt<1>(0h0)
node _T_3222 = eq(sectored_entries[0][7].tag_v, hv_7)
node _T_3223 = and(_T_3222, _WIRE_236.fragmented_superpage)
when _T_3223 :
connect sectored_entries[0][7].valid[2], UInt<1>(0h0)
node _T_3224 = eq(sectored_entries[0][7].tag_v, hv_7)
node _T_3225 = and(_T_3224, _WIRE_238.fragmented_superpage)
when _T_3225 :
connect sectored_entries[0][7].valid[3], UInt<1>(0h0)
else :
node _T_3226 = eq(hg_7, UInt<1>(0h0))
node _T_3227 = and(_T_3226, io.sfence.bits.rs2)
when _T_3227 :
wire _WIRE_240 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_241 : UInt<42>
connect _WIRE_241, sectored_entries[0][7].data[0]
node _T_3228 = bits(_WIRE_241, 0, 0)
connect _WIRE_240.fragmented_superpage, _T_3228
node _T_3229 = bits(_WIRE_241, 1, 1)
connect _WIRE_240.c, _T_3229
node _T_3230 = bits(_WIRE_241, 2, 2)
connect _WIRE_240.eff, _T_3230
node _T_3231 = bits(_WIRE_241, 3, 3)
connect _WIRE_240.paa, _T_3231
node _T_3232 = bits(_WIRE_241, 4, 4)
connect _WIRE_240.pal, _T_3232
node _T_3233 = bits(_WIRE_241, 5, 5)
connect _WIRE_240.ppp, _T_3233
node _T_3234 = bits(_WIRE_241, 6, 6)
connect _WIRE_240.pr, _T_3234
node _T_3235 = bits(_WIRE_241, 7, 7)
connect _WIRE_240.px, _T_3235
node _T_3236 = bits(_WIRE_241, 8, 8)
connect _WIRE_240.pw, _T_3236
node _T_3237 = bits(_WIRE_241, 9, 9)
connect _WIRE_240.hr, _T_3237
node _T_3238 = bits(_WIRE_241, 10, 10)
connect _WIRE_240.hx, _T_3238
node _T_3239 = bits(_WIRE_241, 11, 11)
connect _WIRE_240.hw, _T_3239
node _T_3240 = bits(_WIRE_241, 12, 12)
connect _WIRE_240.sr, _T_3240
node _T_3241 = bits(_WIRE_241, 13, 13)
connect _WIRE_240.sx, _T_3241
node _T_3242 = bits(_WIRE_241, 14, 14)
connect _WIRE_240.sw, _T_3242
node _T_3243 = bits(_WIRE_241, 15, 15)
connect _WIRE_240.gf, _T_3243
node _T_3244 = bits(_WIRE_241, 16, 16)
connect _WIRE_240.pf, _T_3244
node _T_3245 = bits(_WIRE_241, 17, 17)
connect _WIRE_240.ae_stage2, _T_3245
node _T_3246 = bits(_WIRE_241, 18, 18)
connect _WIRE_240.ae_final, _T_3246
node _T_3247 = bits(_WIRE_241, 19, 19)
connect _WIRE_240.ae_ptw, _T_3247
node _T_3248 = bits(_WIRE_241, 20, 20)
connect _WIRE_240.g, _T_3248
node _T_3249 = bits(_WIRE_241, 21, 21)
connect _WIRE_240.u, _T_3249
node _T_3250 = bits(_WIRE_241, 41, 22)
connect _WIRE_240.ppn, _T_3250
wire _WIRE_242 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_243 : UInt<42>
connect _WIRE_243, sectored_entries[0][7].data[1]
node _T_3251 = bits(_WIRE_243, 0, 0)
connect _WIRE_242.fragmented_superpage, _T_3251
node _T_3252 = bits(_WIRE_243, 1, 1)
connect _WIRE_242.c, _T_3252
node _T_3253 = bits(_WIRE_243, 2, 2)
connect _WIRE_242.eff, _T_3253
node _T_3254 = bits(_WIRE_243, 3, 3)
connect _WIRE_242.paa, _T_3254
node _T_3255 = bits(_WIRE_243, 4, 4)
connect _WIRE_242.pal, _T_3255
node _T_3256 = bits(_WIRE_243, 5, 5)
connect _WIRE_242.ppp, _T_3256
node _T_3257 = bits(_WIRE_243, 6, 6)
connect _WIRE_242.pr, _T_3257
node _T_3258 = bits(_WIRE_243, 7, 7)
connect _WIRE_242.px, _T_3258
node _T_3259 = bits(_WIRE_243, 8, 8)
connect _WIRE_242.pw, _T_3259
node _T_3260 = bits(_WIRE_243, 9, 9)
connect _WIRE_242.hr, _T_3260
node _T_3261 = bits(_WIRE_243, 10, 10)
connect _WIRE_242.hx, _T_3261
node _T_3262 = bits(_WIRE_243, 11, 11)
connect _WIRE_242.hw, _T_3262
node _T_3263 = bits(_WIRE_243, 12, 12)
connect _WIRE_242.sr, _T_3263
node _T_3264 = bits(_WIRE_243, 13, 13)
connect _WIRE_242.sx, _T_3264
node _T_3265 = bits(_WIRE_243, 14, 14)
connect _WIRE_242.sw, _T_3265
node _T_3266 = bits(_WIRE_243, 15, 15)
connect _WIRE_242.gf, _T_3266
node _T_3267 = bits(_WIRE_243, 16, 16)
connect _WIRE_242.pf, _T_3267
node _T_3268 = bits(_WIRE_243, 17, 17)
connect _WIRE_242.ae_stage2, _T_3268
node _T_3269 = bits(_WIRE_243, 18, 18)
connect _WIRE_242.ae_final, _T_3269
node _T_3270 = bits(_WIRE_243, 19, 19)
connect _WIRE_242.ae_ptw, _T_3270
node _T_3271 = bits(_WIRE_243, 20, 20)
connect _WIRE_242.g, _T_3271
node _T_3272 = bits(_WIRE_243, 21, 21)
connect _WIRE_242.u, _T_3272
node _T_3273 = bits(_WIRE_243, 41, 22)
connect _WIRE_242.ppn, _T_3273
wire _WIRE_244 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_245 : UInt<42>
connect _WIRE_245, sectored_entries[0][7].data[2]
node _T_3274 = bits(_WIRE_245, 0, 0)
connect _WIRE_244.fragmented_superpage, _T_3274
node _T_3275 = bits(_WIRE_245, 1, 1)
connect _WIRE_244.c, _T_3275
node _T_3276 = bits(_WIRE_245, 2, 2)
connect _WIRE_244.eff, _T_3276
node _T_3277 = bits(_WIRE_245, 3, 3)
connect _WIRE_244.paa, _T_3277
node _T_3278 = bits(_WIRE_245, 4, 4)
connect _WIRE_244.pal, _T_3278
node _T_3279 = bits(_WIRE_245, 5, 5)
connect _WIRE_244.ppp, _T_3279
node _T_3280 = bits(_WIRE_245, 6, 6)
connect _WIRE_244.pr, _T_3280
node _T_3281 = bits(_WIRE_245, 7, 7)
connect _WIRE_244.px, _T_3281
node _T_3282 = bits(_WIRE_245, 8, 8)
connect _WIRE_244.pw, _T_3282
node _T_3283 = bits(_WIRE_245, 9, 9)
connect _WIRE_244.hr, _T_3283
node _T_3284 = bits(_WIRE_245, 10, 10)
connect _WIRE_244.hx, _T_3284
node _T_3285 = bits(_WIRE_245, 11, 11)
connect _WIRE_244.hw, _T_3285
node _T_3286 = bits(_WIRE_245, 12, 12)
connect _WIRE_244.sr, _T_3286
node _T_3287 = bits(_WIRE_245, 13, 13)
connect _WIRE_244.sx, _T_3287
node _T_3288 = bits(_WIRE_245, 14, 14)
connect _WIRE_244.sw, _T_3288
node _T_3289 = bits(_WIRE_245, 15, 15)
connect _WIRE_244.gf, _T_3289
node _T_3290 = bits(_WIRE_245, 16, 16)
connect _WIRE_244.pf, _T_3290
node _T_3291 = bits(_WIRE_245, 17, 17)
connect _WIRE_244.ae_stage2, _T_3291
node _T_3292 = bits(_WIRE_245, 18, 18)
connect _WIRE_244.ae_final, _T_3292
node _T_3293 = bits(_WIRE_245, 19, 19)
connect _WIRE_244.ae_ptw, _T_3293
node _T_3294 = bits(_WIRE_245, 20, 20)
connect _WIRE_244.g, _T_3294
node _T_3295 = bits(_WIRE_245, 21, 21)
connect _WIRE_244.u, _T_3295
node _T_3296 = bits(_WIRE_245, 41, 22)
connect _WIRE_244.ppn, _T_3296
wire _WIRE_246 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_247 : UInt<42>
connect _WIRE_247, sectored_entries[0][7].data[3]
node _T_3297 = bits(_WIRE_247, 0, 0)
connect _WIRE_246.fragmented_superpage, _T_3297
node _T_3298 = bits(_WIRE_247, 1, 1)
connect _WIRE_246.c, _T_3298
node _T_3299 = bits(_WIRE_247, 2, 2)
connect _WIRE_246.eff, _T_3299
node _T_3300 = bits(_WIRE_247, 3, 3)
connect _WIRE_246.paa, _T_3300
node _T_3301 = bits(_WIRE_247, 4, 4)
connect _WIRE_246.pal, _T_3301
node _T_3302 = bits(_WIRE_247, 5, 5)
connect _WIRE_246.ppp, _T_3302
node _T_3303 = bits(_WIRE_247, 6, 6)
connect _WIRE_246.pr, _T_3303
node _T_3304 = bits(_WIRE_247, 7, 7)
connect _WIRE_246.px, _T_3304
node _T_3305 = bits(_WIRE_247, 8, 8)
connect _WIRE_246.pw, _T_3305
node _T_3306 = bits(_WIRE_247, 9, 9)
connect _WIRE_246.hr, _T_3306
node _T_3307 = bits(_WIRE_247, 10, 10)
connect _WIRE_246.hx, _T_3307
node _T_3308 = bits(_WIRE_247, 11, 11)
connect _WIRE_246.hw, _T_3308
node _T_3309 = bits(_WIRE_247, 12, 12)
connect _WIRE_246.sr, _T_3309
node _T_3310 = bits(_WIRE_247, 13, 13)
connect _WIRE_246.sx, _T_3310
node _T_3311 = bits(_WIRE_247, 14, 14)
connect _WIRE_246.sw, _T_3311
node _T_3312 = bits(_WIRE_247, 15, 15)
connect _WIRE_246.gf, _T_3312
node _T_3313 = bits(_WIRE_247, 16, 16)
connect _WIRE_246.pf, _T_3313
node _T_3314 = bits(_WIRE_247, 17, 17)
connect _WIRE_246.ae_stage2, _T_3314
node _T_3315 = bits(_WIRE_247, 18, 18)
connect _WIRE_246.ae_final, _T_3315
node _T_3316 = bits(_WIRE_247, 19, 19)
connect _WIRE_246.ae_ptw, _T_3316
node _T_3317 = bits(_WIRE_247, 20, 20)
connect _WIRE_246.g, _T_3317
node _T_3318 = bits(_WIRE_247, 21, 21)
connect _WIRE_246.u, _T_3318
node _T_3319 = bits(_WIRE_247, 41, 22)
connect _WIRE_246.ppn, _T_3319
node _T_3320 = eq(sectored_entries[0][7].tag_v, hv_7)
node _T_3321 = eq(_WIRE_240.g, UInt<1>(0h0))
node _T_3322 = and(_T_3320, _T_3321)
when _T_3322 :
connect sectored_entries[0][7].valid[0], UInt<1>(0h0)
node _T_3323 = eq(sectored_entries[0][7].tag_v, hv_7)
node _T_3324 = eq(_WIRE_242.g, UInt<1>(0h0))
node _T_3325 = and(_T_3323, _T_3324)
when _T_3325 :
connect sectored_entries[0][7].valid[1], UInt<1>(0h0)
node _T_3326 = eq(sectored_entries[0][7].tag_v, hv_7)
node _T_3327 = eq(_WIRE_244.g, UInt<1>(0h0))
node _T_3328 = and(_T_3326, _T_3327)
when _T_3328 :
connect sectored_entries[0][7].valid[2], UInt<1>(0h0)
node _T_3329 = eq(sectored_entries[0][7].tag_v, hv_7)
node _T_3330 = eq(_WIRE_246.g, UInt<1>(0h0))
node _T_3331 = and(_T_3329, _T_3330)
when _T_3331 :
connect sectored_entries[0][7].valid[3], UInt<1>(0h0)
else :
node _T_3332 = or(hv_7, hg_7)
wire _WIRE_248 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_249 : UInt<42>
connect _WIRE_249, sectored_entries[0][7].data[0]
node _T_3333 = bits(_WIRE_249, 0, 0)
connect _WIRE_248.fragmented_superpage, _T_3333
node _T_3334 = bits(_WIRE_249, 1, 1)
connect _WIRE_248.c, _T_3334
node _T_3335 = bits(_WIRE_249, 2, 2)
connect _WIRE_248.eff, _T_3335
node _T_3336 = bits(_WIRE_249, 3, 3)
connect _WIRE_248.paa, _T_3336
node _T_3337 = bits(_WIRE_249, 4, 4)
connect _WIRE_248.pal, _T_3337
node _T_3338 = bits(_WIRE_249, 5, 5)
connect _WIRE_248.ppp, _T_3338
node _T_3339 = bits(_WIRE_249, 6, 6)
connect _WIRE_248.pr, _T_3339
node _T_3340 = bits(_WIRE_249, 7, 7)
connect _WIRE_248.px, _T_3340
node _T_3341 = bits(_WIRE_249, 8, 8)
connect _WIRE_248.pw, _T_3341
node _T_3342 = bits(_WIRE_249, 9, 9)
connect _WIRE_248.hr, _T_3342
node _T_3343 = bits(_WIRE_249, 10, 10)
connect _WIRE_248.hx, _T_3343
node _T_3344 = bits(_WIRE_249, 11, 11)
connect _WIRE_248.hw, _T_3344
node _T_3345 = bits(_WIRE_249, 12, 12)
connect _WIRE_248.sr, _T_3345
node _T_3346 = bits(_WIRE_249, 13, 13)
connect _WIRE_248.sx, _T_3346
node _T_3347 = bits(_WIRE_249, 14, 14)
connect _WIRE_248.sw, _T_3347
node _T_3348 = bits(_WIRE_249, 15, 15)
connect _WIRE_248.gf, _T_3348
node _T_3349 = bits(_WIRE_249, 16, 16)
connect _WIRE_248.pf, _T_3349
node _T_3350 = bits(_WIRE_249, 17, 17)
connect _WIRE_248.ae_stage2, _T_3350
node _T_3351 = bits(_WIRE_249, 18, 18)
connect _WIRE_248.ae_final, _T_3351
node _T_3352 = bits(_WIRE_249, 19, 19)
connect _WIRE_248.ae_ptw, _T_3352
node _T_3353 = bits(_WIRE_249, 20, 20)
connect _WIRE_248.g, _T_3353
node _T_3354 = bits(_WIRE_249, 21, 21)
connect _WIRE_248.u, _T_3354
node _T_3355 = bits(_WIRE_249, 41, 22)
connect _WIRE_248.ppn, _T_3355
wire _WIRE_250 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_251 : UInt<42>
connect _WIRE_251, sectored_entries[0][7].data[1]
node _T_3356 = bits(_WIRE_251, 0, 0)
connect _WIRE_250.fragmented_superpage, _T_3356
node _T_3357 = bits(_WIRE_251, 1, 1)
connect _WIRE_250.c, _T_3357
node _T_3358 = bits(_WIRE_251, 2, 2)
connect _WIRE_250.eff, _T_3358
node _T_3359 = bits(_WIRE_251, 3, 3)
connect _WIRE_250.paa, _T_3359
node _T_3360 = bits(_WIRE_251, 4, 4)
connect _WIRE_250.pal, _T_3360
node _T_3361 = bits(_WIRE_251, 5, 5)
connect _WIRE_250.ppp, _T_3361
node _T_3362 = bits(_WIRE_251, 6, 6)
connect _WIRE_250.pr, _T_3362
node _T_3363 = bits(_WIRE_251, 7, 7)
connect _WIRE_250.px, _T_3363
node _T_3364 = bits(_WIRE_251, 8, 8)
connect _WIRE_250.pw, _T_3364
node _T_3365 = bits(_WIRE_251, 9, 9)
connect _WIRE_250.hr, _T_3365
node _T_3366 = bits(_WIRE_251, 10, 10)
connect _WIRE_250.hx, _T_3366
node _T_3367 = bits(_WIRE_251, 11, 11)
connect _WIRE_250.hw, _T_3367
node _T_3368 = bits(_WIRE_251, 12, 12)
connect _WIRE_250.sr, _T_3368
node _T_3369 = bits(_WIRE_251, 13, 13)
connect _WIRE_250.sx, _T_3369
node _T_3370 = bits(_WIRE_251, 14, 14)
connect _WIRE_250.sw, _T_3370
node _T_3371 = bits(_WIRE_251, 15, 15)
connect _WIRE_250.gf, _T_3371
node _T_3372 = bits(_WIRE_251, 16, 16)
connect _WIRE_250.pf, _T_3372
node _T_3373 = bits(_WIRE_251, 17, 17)
connect _WIRE_250.ae_stage2, _T_3373
node _T_3374 = bits(_WIRE_251, 18, 18)
connect _WIRE_250.ae_final, _T_3374
node _T_3375 = bits(_WIRE_251, 19, 19)
connect _WIRE_250.ae_ptw, _T_3375
node _T_3376 = bits(_WIRE_251, 20, 20)
connect _WIRE_250.g, _T_3376
node _T_3377 = bits(_WIRE_251, 21, 21)
connect _WIRE_250.u, _T_3377
node _T_3378 = bits(_WIRE_251, 41, 22)
connect _WIRE_250.ppn, _T_3378
wire _WIRE_252 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_253 : UInt<42>
connect _WIRE_253, sectored_entries[0][7].data[2]
node _T_3379 = bits(_WIRE_253, 0, 0)
connect _WIRE_252.fragmented_superpage, _T_3379
node _T_3380 = bits(_WIRE_253, 1, 1)
connect _WIRE_252.c, _T_3380
node _T_3381 = bits(_WIRE_253, 2, 2)
connect _WIRE_252.eff, _T_3381
node _T_3382 = bits(_WIRE_253, 3, 3)
connect _WIRE_252.paa, _T_3382
node _T_3383 = bits(_WIRE_253, 4, 4)
connect _WIRE_252.pal, _T_3383
node _T_3384 = bits(_WIRE_253, 5, 5)
connect _WIRE_252.ppp, _T_3384
node _T_3385 = bits(_WIRE_253, 6, 6)
connect _WIRE_252.pr, _T_3385
node _T_3386 = bits(_WIRE_253, 7, 7)
connect _WIRE_252.px, _T_3386
node _T_3387 = bits(_WIRE_253, 8, 8)
connect _WIRE_252.pw, _T_3387
node _T_3388 = bits(_WIRE_253, 9, 9)
connect _WIRE_252.hr, _T_3388
node _T_3389 = bits(_WIRE_253, 10, 10)
connect _WIRE_252.hx, _T_3389
node _T_3390 = bits(_WIRE_253, 11, 11)
connect _WIRE_252.hw, _T_3390
node _T_3391 = bits(_WIRE_253, 12, 12)
connect _WIRE_252.sr, _T_3391
node _T_3392 = bits(_WIRE_253, 13, 13)
connect _WIRE_252.sx, _T_3392
node _T_3393 = bits(_WIRE_253, 14, 14)
connect _WIRE_252.sw, _T_3393
node _T_3394 = bits(_WIRE_253, 15, 15)
connect _WIRE_252.gf, _T_3394
node _T_3395 = bits(_WIRE_253, 16, 16)
connect _WIRE_252.pf, _T_3395
node _T_3396 = bits(_WIRE_253, 17, 17)
connect _WIRE_252.ae_stage2, _T_3396
node _T_3397 = bits(_WIRE_253, 18, 18)
connect _WIRE_252.ae_final, _T_3397
node _T_3398 = bits(_WIRE_253, 19, 19)
connect _WIRE_252.ae_ptw, _T_3398
node _T_3399 = bits(_WIRE_253, 20, 20)
connect _WIRE_252.g, _T_3399
node _T_3400 = bits(_WIRE_253, 21, 21)
connect _WIRE_252.u, _T_3400
node _T_3401 = bits(_WIRE_253, 41, 22)
connect _WIRE_252.ppn, _T_3401
wire _WIRE_254 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_255 : UInt<42>
connect _WIRE_255, sectored_entries[0][7].data[3]
node _T_3402 = bits(_WIRE_255, 0, 0)
connect _WIRE_254.fragmented_superpage, _T_3402
node _T_3403 = bits(_WIRE_255, 1, 1)
connect _WIRE_254.c, _T_3403
node _T_3404 = bits(_WIRE_255, 2, 2)
connect _WIRE_254.eff, _T_3404
node _T_3405 = bits(_WIRE_255, 3, 3)
connect _WIRE_254.paa, _T_3405
node _T_3406 = bits(_WIRE_255, 4, 4)
connect _WIRE_254.pal, _T_3406
node _T_3407 = bits(_WIRE_255, 5, 5)
connect _WIRE_254.ppp, _T_3407
node _T_3408 = bits(_WIRE_255, 6, 6)
connect _WIRE_254.pr, _T_3408
node _T_3409 = bits(_WIRE_255, 7, 7)
connect _WIRE_254.px, _T_3409
node _T_3410 = bits(_WIRE_255, 8, 8)
connect _WIRE_254.pw, _T_3410
node _T_3411 = bits(_WIRE_255, 9, 9)
connect _WIRE_254.hr, _T_3411
node _T_3412 = bits(_WIRE_255, 10, 10)
connect _WIRE_254.hx, _T_3412
node _T_3413 = bits(_WIRE_255, 11, 11)
connect _WIRE_254.hw, _T_3413
node _T_3414 = bits(_WIRE_255, 12, 12)
connect _WIRE_254.sr, _T_3414
node _T_3415 = bits(_WIRE_255, 13, 13)
connect _WIRE_254.sx, _T_3415
node _T_3416 = bits(_WIRE_255, 14, 14)
connect _WIRE_254.sw, _T_3416
node _T_3417 = bits(_WIRE_255, 15, 15)
connect _WIRE_254.gf, _T_3417
node _T_3418 = bits(_WIRE_255, 16, 16)
connect _WIRE_254.pf, _T_3418
node _T_3419 = bits(_WIRE_255, 17, 17)
connect _WIRE_254.ae_stage2, _T_3419
node _T_3420 = bits(_WIRE_255, 18, 18)
connect _WIRE_254.ae_final, _T_3420
node _T_3421 = bits(_WIRE_255, 19, 19)
connect _WIRE_254.ae_ptw, _T_3421
node _T_3422 = bits(_WIRE_255, 20, 20)
connect _WIRE_254.g, _T_3422
node _T_3423 = bits(_WIRE_255, 21, 21)
connect _WIRE_254.u, _T_3423
node _T_3424 = bits(_WIRE_255, 41, 22)
connect _WIRE_254.ppn, _T_3424
node _T_3425 = eq(sectored_entries[0][7].tag_v, _T_3332)
when _T_3425 :
connect sectored_entries[0][7].valid[0], UInt<1>(0h0)
node _T_3426 = eq(sectored_entries[0][7].tag_v, _T_3332)
when _T_3426 :
connect sectored_entries[0][7].valid[1], UInt<1>(0h0)
node _T_3427 = eq(sectored_entries[0][7].tag_v, _T_3332)
when _T_3427 :
connect sectored_entries[0][7].valid[2], UInt<1>(0h0)
node _T_3428 = eq(sectored_entries[0][7].tag_v, _T_3332)
when _T_3428 :
connect sectored_entries[0][7].valid[3], UInt<1>(0h0)
node hv_8 = and(UInt<1>(0h0), io.sfence.bits.hv)
node hg_8 = and(UInt<1>(0h0), io.sfence.bits.hg)
node _T_3429 = eq(hg_8, UInt<1>(0h0))
node _T_3430 = and(_T_3429, io.sfence.bits.rs1)
when _T_3430 :
node _tagMatch_T = eq(superpage_entries[0].tag_v, hv_8)
node tagMatch = and(superpage_entries[0].valid[0], _tagMatch_T)
node _ignore_T = lt(superpage_entries[0].level, UInt<1>(0h0))
node ignore = or(_ignore_T, UInt<1>(0h0))
node _T_3431 = xor(superpage_entries[0].tag_vpn, vpn)
node _T_3432 = bits(_T_3431, 26, 18)
node _T_3433 = eq(_T_3432, UInt<1>(0h0))
node _T_3434 = or(ignore, _T_3433)
node _T_3435 = and(tagMatch, _T_3434)
node _ignore_T_1 = lt(superpage_entries[0].level, UInt<1>(0h1))
node ignore_1 = or(_ignore_T_1, UInt<1>(0h0))
node _T_3436 = xor(superpage_entries[0].tag_vpn, vpn)
node _T_3437 = bits(_T_3436, 17, 9)
node _T_3438 = eq(_T_3437, UInt<1>(0h0))
node _T_3439 = or(ignore_1, _T_3438)
node _T_3440 = and(_T_3435, _T_3439)
node _ignore_T_2 = lt(superpage_entries[0].level, UInt<2>(0h2))
node ignore_2 = or(_ignore_T_2, UInt<1>(0h1))
node _T_3441 = xor(superpage_entries[0].tag_vpn, vpn)
node _T_3442 = bits(_T_3441, 8, 0)
node _T_3443 = eq(_T_3442, UInt<1>(0h0))
node _T_3444 = or(ignore_2, _T_3443)
node _T_3445 = and(_T_3440, _T_3444)
when _T_3445 :
connect superpage_entries[0].valid[0], UInt<1>(0h0)
node _T_3446 = xor(superpage_entries[0].tag_vpn, vpn)
node _T_3447 = shr(_T_3446, 18)
node _T_3448 = eq(_T_3447, UInt<1>(0h0))
when _T_3448 :
wire _WIRE_256 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_257 : UInt<42>
connect _WIRE_257, superpage_entries[0].data[0]
node _T_3449 = bits(_WIRE_257, 0, 0)
connect _WIRE_256.fragmented_superpage, _T_3449
node _T_3450 = bits(_WIRE_257, 1, 1)
connect _WIRE_256.c, _T_3450
node _T_3451 = bits(_WIRE_257, 2, 2)
connect _WIRE_256.eff, _T_3451
node _T_3452 = bits(_WIRE_257, 3, 3)
connect _WIRE_256.paa, _T_3452
node _T_3453 = bits(_WIRE_257, 4, 4)
connect _WIRE_256.pal, _T_3453
node _T_3454 = bits(_WIRE_257, 5, 5)
connect _WIRE_256.ppp, _T_3454
node _T_3455 = bits(_WIRE_257, 6, 6)
connect _WIRE_256.pr, _T_3455
node _T_3456 = bits(_WIRE_257, 7, 7)
connect _WIRE_256.px, _T_3456
node _T_3457 = bits(_WIRE_257, 8, 8)
connect _WIRE_256.pw, _T_3457
node _T_3458 = bits(_WIRE_257, 9, 9)
connect _WIRE_256.hr, _T_3458
node _T_3459 = bits(_WIRE_257, 10, 10)
connect _WIRE_256.hx, _T_3459
node _T_3460 = bits(_WIRE_257, 11, 11)
connect _WIRE_256.hw, _T_3460
node _T_3461 = bits(_WIRE_257, 12, 12)
connect _WIRE_256.sr, _T_3461
node _T_3462 = bits(_WIRE_257, 13, 13)
connect _WIRE_256.sx, _T_3462
node _T_3463 = bits(_WIRE_257, 14, 14)
connect _WIRE_256.sw, _T_3463
node _T_3464 = bits(_WIRE_257, 15, 15)
connect _WIRE_256.gf, _T_3464
node _T_3465 = bits(_WIRE_257, 16, 16)
connect _WIRE_256.pf, _T_3465
node _T_3466 = bits(_WIRE_257, 17, 17)
connect _WIRE_256.ae_stage2, _T_3466
node _T_3467 = bits(_WIRE_257, 18, 18)
connect _WIRE_256.ae_final, _T_3467
node _T_3468 = bits(_WIRE_257, 19, 19)
connect _WIRE_256.ae_ptw, _T_3468
node _T_3469 = bits(_WIRE_257, 20, 20)
connect _WIRE_256.g, _T_3469
node _T_3470 = bits(_WIRE_257, 21, 21)
connect _WIRE_256.u, _T_3470
node _T_3471 = bits(_WIRE_257, 41, 22)
connect _WIRE_256.ppn, _T_3471
node _T_3472 = eq(superpage_entries[0].tag_v, hv_8)
node _T_3473 = and(_T_3472, _WIRE_256.fragmented_superpage)
when _T_3473 :
connect superpage_entries[0].valid[0], UInt<1>(0h0)
else :
node _T_3474 = eq(hg_8, UInt<1>(0h0))
node _T_3475 = and(_T_3474, io.sfence.bits.rs2)
when _T_3475 :
wire _WIRE_258 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_259 : UInt<42>
connect _WIRE_259, superpage_entries[0].data[0]
node _T_3476 = bits(_WIRE_259, 0, 0)
connect _WIRE_258.fragmented_superpage, _T_3476
node _T_3477 = bits(_WIRE_259, 1, 1)
connect _WIRE_258.c, _T_3477
node _T_3478 = bits(_WIRE_259, 2, 2)
connect _WIRE_258.eff, _T_3478
node _T_3479 = bits(_WIRE_259, 3, 3)
connect _WIRE_258.paa, _T_3479
node _T_3480 = bits(_WIRE_259, 4, 4)
connect _WIRE_258.pal, _T_3480
node _T_3481 = bits(_WIRE_259, 5, 5)
connect _WIRE_258.ppp, _T_3481
node _T_3482 = bits(_WIRE_259, 6, 6)
connect _WIRE_258.pr, _T_3482
node _T_3483 = bits(_WIRE_259, 7, 7)
connect _WIRE_258.px, _T_3483
node _T_3484 = bits(_WIRE_259, 8, 8)
connect _WIRE_258.pw, _T_3484
node _T_3485 = bits(_WIRE_259, 9, 9)
connect _WIRE_258.hr, _T_3485
node _T_3486 = bits(_WIRE_259, 10, 10)
connect _WIRE_258.hx, _T_3486
node _T_3487 = bits(_WIRE_259, 11, 11)
connect _WIRE_258.hw, _T_3487
node _T_3488 = bits(_WIRE_259, 12, 12)
connect _WIRE_258.sr, _T_3488
node _T_3489 = bits(_WIRE_259, 13, 13)
connect _WIRE_258.sx, _T_3489
node _T_3490 = bits(_WIRE_259, 14, 14)
connect _WIRE_258.sw, _T_3490
node _T_3491 = bits(_WIRE_259, 15, 15)
connect _WIRE_258.gf, _T_3491
node _T_3492 = bits(_WIRE_259, 16, 16)
connect _WIRE_258.pf, _T_3492
node _T_3493 = bits(_WIRE_259, 17, 17)
connect _WIRE_258.ae_stage2, _T_3493
node _T_3494 = bits(_WIRE_259, 18, 18)
connect _WIRE_258.ae_final, _T_3494
node _T_3495 = bits(_WIRE_259, 19, 19)
connect _WIRE_258.ae_ptw, _T_3495
node _T_3496 = bits(_WIRE_259, 20, 20)
connect _WIRE_258.g, _T_3496
node _T_3497 = bits(_WIRE_259, 21, 21)
connect _WIRE_258.u, _T_3497
node _T_3498 = bits(_WIRE_259, 41, 22)
connect _WIRE_258.ppn, _T_3498
node _T_3499 = eq(superpage_entries[0].tag_v, hv_8)
node _T_3500 = eq(_WIRE_258.g, UInt<1>(0h0))
node _T_3501 = and(_T_3499, _T_3500)
when _T_3501 :
connect superpage_entries[0].valid[0], UInt<1>(0h0)
else :
node _T_3502 = or(hv_8, hg_8)
wire _WIRE_260 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_261 : UInt<42>
connect _WIRE_261, superpage_entries[0].data[0]
node _T_3503 = bits(_WIRE_261, 0, 0)
connect _WIRE_260.fragmented_superpage, _T_3503
node _T_3504 = bits(_WIRE_261, 1, 1)
connect _WIRE_260.c, _T_3504
node _T_3505 = bits(_WIRE_261, 2, 2)
connect _WIRE_260.eff, _T_3505
node _T_3506 = bits(_WIRE_261, 3, 3)
connect _WIRE_260.paa, _T_3506
node _T_3507 = bits(_WIRE_261, 4, 4)
connect _WIRE_260.pal, _T_3507
node _T_3508 = bits(_WIRE_261, 5, 5)
connect _WIRE_260.ppp, _T_3508
node _T_3509 = bits(_WIRE_261, 6, 6)
connect _WIRE_260.pr, _T_3509
node _T_3510 = bits(_WIRE_261, 7, 7)
connect _WIRE_260.px, _T_3510
node _T_3511 = bits(_WIRE_261, 8, 8)
connect _WIRE_260.pw, _T_3511
node _T_3512 = bits(_WIRE_261, 9, 9)
connect _WIRE_260.hr, _T_3512
node _T_3513 = bits(_WIRE_261, 10, 10)
connect _WIRE_260.hx, _T_3513
node _T_3514 = bits(_WIRE_261, 11, 11)
connect _WIRE_260.hw, _T_3514
node _T_3515 = bits(_WIRE_261, 12, 12)
connect _WIRE_260.sr, _T_3515
node _T_3516 = bits(_WIRE_261, 13, 13)
connect _WIRE_260.sx, _T_3516
node _T_3517 = bits(_WIRE_261, 14, 14)
connect _WIRE_260.sw, _T_3517
node _T_3518 = bits(_WIRE_261, 15, 15)
connect _WIRE_260.gf, _T_3518
node _T_3519 = bits(_WIRE_261, 16, 16)
connect _WIRE_260.pf, _T_3519
node _T_3520 = bits(_WIRE_261, 17, 17)
connect _WIRE_260.ae_stage2, _T_3520
node _T_3521 = bits(_WIRE_261, 18, 18)
connect _WIRE_260.ae_final, _T_3521
node _T_3522 = bits(_WIRE_261, 19, 19)
connect _WIRE_260.ae_ptw, _T_3522
node _T_3523 = bits(_WIRE_261, 20, 20)
connect _WIRE_260.g, _T_3523
node _T_3524 = bits(_WIRE_261, 21, 21)
connect _WIRE_260.u, _T_3524
node _T_3525 = bits(_WIRE_261, 41, 22)
connect _WIRE_260.ppn, _T_3525
node _T_3526 = eq(superpage_entries[0].tag_v, _T_3502)
when _T_3526 :
connect superpage_entries[0].valid[0], UInt<1>(0h0)
node hv_9 = and(UInt<1>(0h0), io.sfence.bits.hv)
node hg_9 = and(UInt<1>(0h0), io.sfence.bits.hg)
node _T_3527 = eq(hg_9, UInt<1>(0h0))
node _T_3528 = and(_T_3527, io.sfence.bits.rs1)
when _T_3528 :
node _tagMatch_T_1 = eq(superpage_entries[1].tag_v, hv_9)
node tagMatch_1 = and(superpage_entries[1].valid[0], _tagMatch_T_1)
node _ignore_T_3 = lt(superpage_entries[1].level, UInt<1>(0h0))
node ignore_3 = or(_ignore_T_3, UInt<1>(0h0))
node _T_3529 = xor(superpage_entries[1].tag_vpn, vpn)
node _T_3530 = bits(_T_3529, 26, 18)
node _T_3531 = eq(_T_3530, UInt<1>(0h0))
node _T_3532 = or(ignore_3, _T_3531)
node _T_3533 = and(tagMatch_1, _T_3532)
node _ignore_T_4 = lt(superpage_entries[1].level, UInt<1>(0h1))
node ignore_4 = or(_ignore_T_4, UInt<1>(0h0))
node _T_3534 = xor(superpage_entries[1].tag_vpn, vpn)
node _T_3535 = bits(_T_3534, 17, 9)
node _T_3536 = eq(_T_3535, UInt<1>(0h0))
node _T_3537 = or(ignore_4, _T_3536)
node _T_3538 = and(_T_3533, _T_3537)
node _ignore_T_5 = lt(superpage_entries[1].level, UInt<2>(0h2))
node ignore_5 = or(_ignore_T_5, UInt<1>(0h1))
node _T_3539 = xor(superpage_entries[1].tag_vpn, vpn)
node _T_3540 = bits(_T_3539, 8, 0)
node _T_3541 = eq(_T_3540, UInt<1>(0h0))
node _T_3542 = or(ignore_5, _T_3541)
node _T_3543 = and(_T_3538, _T_3542)
when _T_3543 :
connect superpage_entries[1].valid[0], UInt<1>(0h0)
node _T_3544 = xor(superpage_entries[1].tag_vpn, vpn)
node _T_3545 = shr(_T_3544, 18)
node _T_3546 = eq(_T_3545, UInt<1>(0h0))
when _T_3546 :
wire _WIRE_262 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_263 : UInt<42>
connect _WIRE_263, superpage_entries[1].data[0]
node _T_3547 = bits(_WIRE_263, 0, 0)
connect _WIRE_262.fragmented_superpage, _T_3547
node _T_3548 = bits(_WIRE_263, 1, 1)
connect _WIRE_262.c, _T_3548
node _T_3549 = bits(_WIRE_263, 2, 2)
connect _WIRE_262.eff, _T_3549
node _T_3550 = bits(_WIRE_263, 3, 3)
connect _WIRE_262.paa, _T_3550
node _T_3551 = bits(_WIRE_263, 4, 4)
connect _WIRE_262.pal, _T_3551
node _T_3552 = bits(_WIRE_263, 5, 5)
connect _WIRE_262.ppp, _T_3552
node _T_3553 = bits(_WIRE_263, 6, 6)
connect _WIRE_262.pr, _T_3553
node _T_3554 = bits(_WIRE_263, 7, 7)
connect _WIRE_262.px, _T_3554
node _T_3555 = bits(_WIRE_263, 8, 8)
connect _WIRE_262.pw, _T_3555
node _T_3556 = bits(_WIRE_263, 9, 9)
connect _WIRE_262.hr, _T_3556
node _T_3557 = bits(_WIRE_263, 10, 10)
connect _WIRE_262.hx, _T_3557
node _T_3558 = bits(_WIRE_263, 11, 11)
connect _WIRE_262.hw, _T_3558
node _T_3559 = bits(_WIRE_263, 12, 12)
connect _WIRE_262.sr, _T_3559
node _T_3560 = bits(_WIRE_263, 13, 13)
connect _WIRE_262.sx, _T_3560
node _T_3561 = bits(_WIRE_263, 14, 14)
connect _WIRE_262.sw, _T_3561
node _T_3562 = bits(_WIRE_263, 15, 15)
connect _WIRE_262.gf, _T_3562
node _T_3563 = bits(_WIRE_263, 16, 16)
connect _WIRE_262.pf, _T_3563
node _T_3564 = bits(_WIRE_263, 17, 17)
connect _WIRE_262.ae_stage2, _T_3564
node _T_3565 = bits(_WIRE_263, 18, 18)
connect _WIRE_262.ae_final, _T_3565
node _T_3566 = bits(_WIRE_263, 19, 19)
connect _WIRE_262.ae_ptw, _T_3566
node _T_3567 = bits(_WIRE_263, 20, 20)
connect _WIRE_262.g, _T_3567
node _T_3568 = bits(_WIRE_263, 21, 21)
connect _WIRE_262.u, _T_3568
node _T_3569 = bits(_WIRE_263, 41, 22)
connect _WIRE_262.ppn, _T_3569
node _T_3570 = eq(superpage_entries[1].tag_v, hv_9)
node _T_3571 = and(_T_3570, _WIRE_262.fragmented_superpage)
when _T_3571 :
connect superpage_entries[1].valid[0], UInt<1>(0h0)
else :
node _T_3572 = eq(hg_9, UInt<1>(0h0))
node _T_3573 = and(_T_3572, io.sfence.bits.rs2)
when _T_3573 :
wire _WIRE_264 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_265 : UInt<42>
connect _WIRE_265, superpage_entries[1].data[0]
node _T_3574 = bits(_WIRE_265, 0, 0)
connect _WIRE_264.fragmented_superpage, _T_3574
node _T_3575 = bits(_WIRE_265, 1, 1)
connect _WIRE_264.c, _T_3575
node _T_3576 = bits(_WIRE_265, 2, 2)
connect _WIRE_264.eff, _T_3576
node _T_3577 = bits(_WIRE_265, 3, 3)
connect _WIRE_264.paa, _T_3577
node _T_3578 = bits(_WIRE_265, 4, 4)
connect _WIRE_264.pal, _T_3578
node _T_3579 = bits(_WIRE_265, 5, 5)
connect _WIRE_264.ppp, _T_3579
node _T_3580 = bits(_WIRE_265, 6, 6)
connect _WIRE_264.pr, _T_3580
node _T_3581 = bits(_WIRE_265, 7, 7)
connect _WIRE_264.px, _T_3581
node _T_3582 = bits(_WIRE_265, 8, 8)
connect _WIRE_264.pw, _T_3582
node _T_3583 = bits(_WIRE_265, 9, 9)
connect _WIRE_264.hr, _T_3583
node _T_3584 = bits(_WIRE_265, 10, 10)
connect _WIRE_264.hx, _T_3584
node _T_3585 = bits(_WIRE_265, 11, 11)
connect _WIRE_264.hw, _T_3585
node _T_3586 = bits(_WIRE_265, 12, 12)
connect _WIRE_264.sr, _T_3586
node _T_3587 = bits(_WIRE_265, 13, 13)
connect _WIRE_264.sx, _T_3587
node _T_3588 = bits(_WIRE_265, 14, 14)
connect _WIRE_264.sw, _T_3588
node _T_3589 = bits(_WIRE_265, 15, 15)
connect _WIRE_264.gf, _T_3589
node _T_3590 = bits(_WIRE_265, 16, 16)
connect _WIRE_264.pf, _T_3590
node _T_3591 = bits(_WIRE_265, 17, 17)
connect _WIRE_264.ae_stage2, _T_3591
node _T_3592 = bits(_WIRE_265, 18, 18)
connect _WIRE_264.ae_final, _T_3592
node _T_3593 = bits(_WIRE_265, 19, 19)
connect _WIRE_264.ae_ptw, _T_3593
node _T_3594 = bits(_WIRE_265, 20, 20)
connect _WIRE_264.g, _T_3594
node _T_3595 = bits(_WIRE_265, 21, 21)
connect _WIRE_264.u, _T_3595
node _T_3596 = bits(_WIRE_265, 41, 22)
connect _WIRE_264.ppn, _T_3596
node _T_3597 = eq(superpage_entries[1].tag_v, hv_9)
node _T_3598 = eq(_WIRE_264.g, UInt<1>(0h0))
node _T_3599 = and(_T_3597, _T_3598)
when _T_3599 :
connect superpage_entries[1].valid[0], UInt<1>(0h0)
else :
node _T_3600 = or(hv_9, hg_9)
wire _WIRE_266 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_267 : UInt<42>
connect _WIRE_267, superpage_entries[1].data[0]
node _T_3601 = bits(_WIRE_267, 0, 0)
connect _WIRE_266.fragmented_superpage, _T_3601
node _T_3602 = bits(_WIRE_267, 1, 1)
connect _WIRE_266.c, _T_3602
node _T_3603 = bits(_WIRE_267, 2, 2)
connect _WIRE_266.eff, _T_3603
node _T_3604 = bits(_WIRE_267, 3, 3)
connect _WIRE_266.paa, _T_3604
node _T_3605 = bits(_WIRE_267, 4, 4)
connect _WIRE_266.pal, _T_3605
node _T_3606 = bits(_WIRE_267, 5, 5)
connect _WIRE_266.ppp, _T_3606
node _T_3607 = bits(_WIRE_267, 6, 6)
connect _WIRE_266.pr, _T_3607
node _T_3608 = bits(_WIRE_267, 7, 7)
connect _WIRE_266.px, _T_3608
node _T_3609 = bits(_WIRE_267, 8, 8)
connect _WIRE_266.pw, _T_3609
node _T_3610 = bits(_WIRE_267, 9, 9)
connect _WIRE_266.hr, _T_3610
node _T_3611 = bits(_WIRE_267, 10, 10)
connect _WIRE_266.hx, _T_3611
node _T_3612 = bits(_WIRE_267, 11, 11)
connect _WIRE_266.hw, _T_3612
node _T_3613 = bits(_WIRE_267, 12, 12)
connect _WIRE_266.sr, _T_3613
node _T_3614 = bits(_WIRE_267, 13, 13)
connect _WIRE_266.sx, _T_3614
node _T_3615 = bits(_WIRE_267, 14, 14)
connect _WIRE_266.sw, _T_3615
node _T_3616 = bits(_WIRE_267, 15, 15)
connect _WIRE_266.gf, _T_3616
node _T_3617 = bits(_WIRE_267, 16, 16)
connect _WIRE_266.pf, _T_3617
node _T_3618 = bits(_WIRE_267, 17, 17)
connect _WIRE_266.ae_stage2, _T_3618
node _T_3619 = bits(_WIRE_267, 18, 18)
connect _WIRE_266.ae_final, _T_3619
node _T_3620 = bits(_WIRE_267, 19, 19)
connect _WIRE_266.ae_ptw, _T_3620
node _T_3621 = bits(_WIRE_267, 20, 20)
connect _WIRE_266.g, _T_3621
node _T_3622 = bits(_WIRE_267, 21, 21)
connect _WIRE_266.u, _T_3622
node _T_3623 = bits(_WIRE_267, 41, 22)
connect _WIRE_266.ppn, _T_3623
node _T_3624 = eq(superpage_entries[1].tag_v, _T_3600)
when _T_3624 :
connect superpage_entries[1].valid[0], UInt<1>(0h0)
node hv_10 = and(UInt<1>(0h0), io.sfence.bits.hv)
node hg_10 = and(UInt<1>(0h0), io.sfence.bits.hg)
node _T_3625 = eq(hg_10, UInt<1>(0h0))
node _T_3626 = and(_T_3625, io.sfence.bits.rs1)
when _T_3626 :
node _tagMatch_T_2 = eq(superpage_entries[2].tag_v, hv_10)
node tagMatch_2 = and(superpage_entries[2].valid[0], _tagMatch_T_2)
node _ignore_T_6 = lt(superpage_entries[2].level, UInt<1>(0h0))
node ignore_6 = or(_ignore_T_6, UInt<1>(0h0))
node _T_3627 = xor(superpage_entries[2].tag_vpn, vpn)
node _T_3628 = bits(_T_3627, 26, 18)
node _T_3629 = eq(_T_3628, UInt<1>(0h0))
node _T_3630 = or(ignore_6, _T_3629)
node _T_3631 = and(tagMatch_2, _T_3630)
node _ignore_T_7 = lt(superpage_entries[2].level, UInt<1>(0h1))
node ignore_7 = or(_ignore_T_7, UInt<1>(0h0))
node _T_3632 = xor(superpage_entries[2].tag_vpn, vpn)
node _T_3633 = bits(_T_3632, 17, 9)
node _T_3634 = eq(_T_3633, UInt<1>(0h0))
node _T_3635 = or(ignore_7, _T_3634)
node _T_3636 = and(_T_3631, _T_3635)
node _ignore_T_8 = lt(superpage_entries[2].level, UInt<2>(0h2))
node ignore_8 = or(_ignore_T_8, UInt<1>(0h1))
node _T_3637 = xor(superpage_entries[2].tag_vpn, vpn)
node _T_3638 = bits(_T_3637, 8, 0)
node _T_3639 = eq(_T_3638, UInt<1>(0h0))
node _T_3640 = or(ignore_8, _T_3639)
node _T_3641 = and(_T_3636, _T_3640)
when _T_3641 :
connect superpage_entries[2].valid[0], UInt<1>(0h0)
node _T_3642 = xor(superpage_entries[2].tag_vpn, vpn)
node _T_3643 = shr(_T_3642, 18)
node _T_3644 = eq(_T_3643, UInt<1>(0h0))
when _T_3644 :
wire _WIRE_268 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_269 : UInt<42>
connect _WIRE_269, superpage_entries[2].data[0]
node _T_3645 = bits(_WIRE_269, 0, 0)
connect _WIRE_268.fragmented_superpage, _T_3645
node _T_3646 = bits(_WIRE_269, 1, 1)
connect _WIRE_268.c, _T_3646
node _T_3647 = bits(_WIRE_269, 2, 2)
connect _WIRE_268.eff, _T_3647
node _T_3648 = bits(_WIRE_269, 3, 3)
connect _WIRE_268.paa, _T_3648
node _T_3649 = bits(_WIRE_269, 4, 4)
connect _WIRE_268.pal, _T_3649
node _T_3650 = bits(_WIRE_269, 5, 5)
connect _WIRE_268.ppp, _T_3650
node _T_3651 = bits(_WIRE_269, 6, 6)
connect _WIRE_268.pr, _T_3651
node _T_3652 = bits(_WIRE_269, 7, 7)
connect _WIRE_268.px, _T_3652
node _T_3653 = bits(_WIRE_269, 8, 8)
connect _WIRE_268.pw, _T_3653
node _T_3654 = bits(_WIRE_269, 9, 9)
connect _WIRE_268.hr, _T_3654
node _T_3655 = bits(_WIRE_269, 10, 10)
connect _WIRE_268.hx, _T_3655
node _T_3656 = bits(_WIRE_269, 11, 11)
connect _WIRE_268.hw, _T_3656
node _T_3657 = bits(_WIRE_269, 12, 12)
connect _WIRE_268.sr, _T_3657
node _T_3658 = bits(_WIRE_269, 13, 13)
connect _WIRE_268.sx, _T_3658
node _T_3659 = bits(_WIRE_269, 14, 14)
connect _WIRE_268.sw, _T_3659
node _T_3660 = bits(_WIRE_269, 15, 15)
connect _WIRE_268.gf, _T_3660
node _T_3661 = bits(_WIRE_269, 16, 16)
connect _WIRE_268.pf, _T_3661
node _T_3662 = bits(_WIRE_269, 17, 17)
connect _WIRE_268.ae_stage2, _T_3662
node _T_3663 = bits(_WIRE_269, 18, 18)
connect _WIRE_268.ae_final, _T_3663
node _T_3664 = bits(_WIRE_269, 19, 19)
connect _WIRE_268.ae_ptw, _T_3664
node _T_3665 = bits(_WIRE_269, 20, 20)
connect _WIRE_268.g, _T_3665
node _T_3666 = bits(_WIRE_269, 21, 21)
connect _WIRE_268.u, _T_3666
node _T_3667 = bits(_WIRE_269, 41, 22)
connect _WIRE_268.ppn, _T_3667
node _T_3668 = eq(superpage_entries[2].tag_v, hv_10)
node _T_3669 = and(_T_3668, _WIRE_268.fragmented_superpage)
when _T_3669 :
connect superpage_entries[2].valid[0], UInt<1>(0h0)
else :
node _T_3670 = eq(hg_10, UInt<1>(0h0))
node _T_3671 = and(_T_3670, io.sfence.bits.rs2)
when _T_3671 :
wire _WIRE_270 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_271 : UInt<42>
connect _WIRE_271, superpage_entries[2].data[0]
node _T_3672 = bits(_WIRE_271, 0, 0)
connect _WIRE_270.fragmented_superpage, _T_3672
node _T_3673 = bits(_WIRE_271, 1, 1)
connect _WIRE_270.c, _T_3673
node _T_3674 = bits(_WIRE_271, 2, 2)
connect _WIRE_270.eff, _T_3674
node _T_3675 = bits(_WIRE_271, 3, 3)
connect _WIRE_270.paa, _T_3675
node _T_3676 = bits(_WIRE_271, 4, 4)
connect _WIRE_270.pal, _T_3676
node _T_3677 = bits(_WIRE_271, 5, 5)
connect _WIRE_270.ppp, _T_3677
node _T_3678 = bits(_WIRE_271, 6, 6)
connect _WIRE_270.pr, _T_3678
node _T_3679 = bits(_WIRE_271, 7, 7)
connect _WIRE_270.px, _T_3679
node _T_3680 = bits(_WIRE_271, 8, 8)
connect _WIRE_270.pw, _T_3680
node _T_3681 = bits(_WIRE_271, 9, 9)
connect _WIRE_270.hr, _T_3681
node _T_3682 = bits(_WIRE_271, 10, 10)
connect _WIRE_270.hx, _T_3682
node _T_3683 = bits(_WIRE_271, 11, 11)
connect _WIRE_270.hw, _T_3683
node _T_3684 = bits(_WIRE_271, 12, 12)
connect _WIRE_270.sr, _T_3684
node _T_3685 = bits(_WIRE_271, 13, 13)
connect _WIRE_270.sx, _T_3685
node _T_3686 = bits(_WIRE_271, 14, 14)
connect _WIRE_270.sw, _T_3686
node _T_3687 = bits(_WIRE_271, 15, 15)
connect _WIRE_270.gf, _T_3687
node _T_3688 = bits(_WIRE_271, 16, 16)
connect _WIRE_270.pf, _T_3688
node _T_3689 = bits(_WIRE_271, 17, 17)
connect _WIRE_270.ae_stage2, _T_3689
node _T_3690 = bits(_WIRE_271, 18, 18)
connect _WIRE_270.ae_final, _T_3690
node _T_3691 = bits(_WIRE_271, 19, 19)
connect _WIRE_270.ae_ptw, _T_3691
node _T_3692 = bits(_WIRE_271, 20, 20)
connect _WIRE_270.g, _T_3692
node _T_3693 = bits(_WIRE_271, 21, 21)
connect _WIRE_270.u, _T_3693
node _T_3694 = bits(_WIRE_271, 41, 22)
connect _WIRE_270.ppn, _T_3694
node _T_3695 = eq(superpage_entries[2].tag_v, hv_10)
node _T_3696 = eq(_WIRE_270.g, UInt<1>(0h0))
node _T_3697 = and(_T_3695, _T_3696)
when _T_3697 :
connect superpage_entries[2].valid[0], UInt<1>(0h0)
else :
node _T_3698 = or(hv_10, hg_10)
wire _WIRE_272 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_273 : UInt<42>
connect _WIRE_273, superpage_entries[2].data[0]
node _T_3699 = bits(_WIRE_273, 0, 0)
connect _WIRE_272.fragmented_superpage, _T_3699
node _T_3700 = bits(_WIRE_273, 1, 1)
connect _WIRE_272.c, _T_3700
node _T_3701 = bits(_WIRE_273, 2, 2)
connect _WIRE_272.eff, _T_3701
node _T_3702 = bits(_WIRE_273, 3, 3)
connect _WIRE_272.paa, _T_3702
node _T_3703 = bits(_WIRE_273, 4, 4)
connect _WIRE_272.pal, _T_3703
node _T_3704 = bits(_WIRE_273, 5, 5)
connect _WIRE_272.ppp, _T_3704
node _T_3705 = bits(_WIRE_273, 6, 6)
connect _WIRE_272.pr, _T_3705
node _T_3706 = bits(_WIRE_273, 7, 7)
connect _WIRE_272.px, _T_3706
node _T_3707 = bits(_WIRE_273, 8, 8)
connect _WIRE_272.pw, _T_3707
node _T_3708 = bits(_WIRE_273, 9, 9)
connect _WIRE_272.hr, _T_3708
node _T_3709 = bits(_WIRE_273, 10, 10)
connect _WIRE_272.hx, _T_3709
node _T_3710 = bits(_WIRE_273, 11, 11)
connect _WIRE_272.hw, _T_3710
node _T_3711 = bits(_WIRE_273, 12, 12)
connect _WIRE_272.sr, _T_3711
node _T_3712 = bits(_WIRE_273, 13, 13)
connect _WIRE_272.sx, _T_3712
node _T_3713 = bits(_WIRE_273, 14, 14)
connect _WIRE_272.sw, _T_3713
node _T_3714 = bits(_WIRE_273, 15, 15)
connect _WIRE_272.gf, _T_3714
node _T_3715 = bits(_WIRE_273, 16, 16)
connect _WIRE_272.pf, _T_3715
node _T_3716 = bits(_WIRE_273, 17, 17)
connect _WIRE_272.ae_stage2, _T_3716
node _T_3717 = bits(_WIRE_273, 18, 18)
connect _WIRE_272.ae_final, _T_3717
node _T_3718 = bits(_WIRE_273, 19, 19)
connect _WIRE_272.ae_ptw, _T_3718
node _T_3719 = bits(_WIRE_273, 20, 20)
connect _WIRE_272.g, _T_3719
node _T_3720 = bits(_WIRE_273, 21, 21)
connect _WIRE_272.u, _T_3720
node _T_3721 = bits(_WIRE_273, 41, 22)
connect _WIRE_272.ppn, _T_3721
node _T_3722 = eq(superpage_entries[2].tag_v, _T_3698)
when _T_3722 :
connect superpage_entries[2].valid[0], UInt<1>(0h0)
node hv_11 = and(UInt<1>(0h0), io.sfence.bits.hv)
node hg_11 = and(UInt<1>(0h0), io.sfence.bits.hg)
node _T_3723 = eq(hg_11, UInt<1>(0h0))
node _T_3724 = and(_T_3723, io.sfence.bits.rs1)
when _T_3724 :
node _tagMatch_T_3 = eq(superpage_entries[3].tag_v, hv_11)
node tagMatch_3 = and(superpage_entries[3].valid[0], _tagMatch_T_3)
node _ignore_T_9 = lt(superpage_entries[3].level, UInt<1>(0h0))
node ignore_9 = or(_ignore_T_9, UInt<1>(0h0))
node _T_3725 = xor(superpage_entries[3].tag_vpn, vpn)
node _T_3726 = bits(_T_3725, 26, 18)
node _T_3727 = eq(_T_3726, UInt<1>(0h0))
node _T_3728 = or(ignore_9, _T_3727)
node _T_3729 = and(tagMatch_3, _T_3728)
node _ignore_T_10 = lt(superpage_entries[3].level, UInt<1>(0h1))
node ignore_10 = or(_ignore_T_10, UInt<1>(0h0))
node _T_3730 = xor(superpage_entries[3].tag_vpn, vpn)
node _T_3731 = bits(_T_3730, 17, 9)
node _T_3732 = eq(_T_3731, UInt<1>(0h0))
node _T_3733 = or(ignore_10, _T_3732)
node _T_3734 = and(_T_3729, _T_3733)
node _ignore_T_11 = lt(superpage_entries[3].level, UInt<2>(0h2))
node ignore_11 = or(_ignore_T_11, UInt<1>(0h1))
node _T_3735 = xor(superpage_entries[3].tag_vpn, vpn)
node _T_3736 = bits(_T_3735, 8, 0)
node _T_3737 = eq(_T_3736, UInt<1>(0h0))
node _T_3738 = or(ignore_11, _T_3737)
node _T_3739 = and(_T_3734, _T_3738)
when _T_3739 :
connect superpage_entries[3].valid[0], UInt<1>(0h0)
node _T_3740 = xor(superpage_entries[3].tag_vpn, vpn)
node _T_3741 = shr(_T_3740, 18)
node _T_3742 = eq(_T_3741, UInt<1>(0h0))
when _T_3742 :
wire _WIRE_274 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_275 : UInt<42>
connect _WIRE_275, superpage_entries[3].data[0]
node _T_3743 = bits(_WIRE_275, 0, 0)
connect _WIRE_274.fragmented_superpage, _T_3743
node _T_3744 = bits(_WIRE_275, 1, 1)
connect _WIRE_274.c, _T_3744
node _T_3745 = bits(_WIRE_275, 2, 2)
connect _WIRE_274.eff, _T_3745
node _T_3746 = bits(_WIRE_275, 3, 3)
connect _WIRE_274.paa, _T_3746
node _T_3747 = bits(_WIRE_275, 4, 4)
connect _WIRE_274.pal, _T_3747
node _T_3748 = bits(_WIRE_275, 5, 5)
connect _WIRE_274.ppp, _T_3748
node _T_3749 = bits(_WIRE_275, 6, 6)
connect _WIRE_274.pr, _T_3749
node _T_3750 = bits(_WIRE_275, 7, 7)
connect _WIRE_274.px, _T_3750
node _T_3751 = bits(_WIRE_275, 8, 8)
connect _WIRE_274.pw, _T_3751
node _T_3752 = bits(_WIRE_275, 9, 9)
connect _WIRE_274.hr, _T_3752
node _T_3753 = bits(_WIRE_275, 10, 10)
connect _WIRE_274.hx, _T_3753
node _T_3754 = bits(_WIRE_275, 11, 11)
connect _WIRE_274.hw, _T_3754
node _T_3755 = bits(_WIRE_275, 12, 12)
connect _WIRE_274.sr, _T_3755
node _T_3756 = bits(_WIRE_275, 13, 13)
connect _WIRE_274.sx, _T_3756
node _T_3757 = bits(_WIRE_275, 14, 14)
connect _WIRE_274.sw, _T_3757
node _T_3758 = bits(_WIRE_275, 15, 15)
connect _WIRE_274.gf, _T_3758
node _T_3759 = bits(_WIRE_275, 16, 16)
connect _WIRE_274.pf, _T_3759
node _T_3760 = bits(_WIRE_275, 17, 17)
connect _WIRE_274.ae_stage2, _T_3760
node _T_3761 = bits(_WIRE_275, 18, 18)
connect _WIRE_274.ae_final, _T_3761
node _T_3762 = bits(_WIRE_275, 19, 19)
connect _WIRE_274.ae_ptw, _T_3762
node _T_3763 = bits(_WIRE_275, 20, 20)
connect _WIRE_274.g, _T_3763
node _T_3764 = bits(_WIRE_275, 21, 21)
connect _WIRE_274.u, _T_3764
node _T_3765 = bits(_WIRE_275, 41, 22)
connect _WIRE_274.ppn, _T_3765
node _T_3766 = eq(superpage_entries[3].tag_v, hv_11)
node _T_3767 = and(_T_3766, _WIRE_274.fragmented_superpage)
when _T_3767 :
connect superpage_entries[3].valid[0], UInt<1>(0h0)
else :
node _T_3768 = eq(hg_11, UInt<1>(0h0))
node _T_3769 = and(_T_3768, io.sfence.bits.rs2)
when _T_3769 :
wire _WIRE_276 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_277 : UInt<42>
connect _WIRE_277, superpage_entries[3].data[0]
node _T_3770 = bits(_WIRE_277, 0, 0)
connect _WIRE_276.fragmented_superpage, _T_3770
node _T_3771 = bits(_WIRE_277, 1, 1)
connect _WIRE_276.c, _T_3771
node _T_3772 = bits(_WIRE_277, 2, 2)
connect _WIRE_276.eff, _T_3772
node _T_3773 = bits(_WIRE_277, 3, 3)
connect _WIRE_276.paa, _T_3773
node _T_3774 = bits(_WIRE_277, 4, 4)
connect _WIRE_276.pal, _T_3774
node _T_3775 = bits(_WIRE_277, 5, 5)
connect _WIRE_276.ppp, _T_3775
node _T_3776 = bits(_WIRE_277, 6, 6)
connect _WIRE_276.pr, _T_3776
node _T_3777 = bits(_WIRE_277, 7, 7)
connect _WIRE_276.px, _T_3777
node _T_3778 = bits(_WIRE_277, 8, 8)
connect _WIRE_276.pw, _T_3778
node _T_3779 = bits(_WIRE_277, 9, 9)
connect _WIRE_276.hr, _T_3779
node _T_3780 = bits(_WIRE_277, 10, 10)
connect _WIRE_276.hx, _T_3780
node _T_3781 = bits(_WIRE_277, 11, 11)
connect _WIRE_276.hw, _T_3781
node _T_3782 = bits(_WIRE_277, 12, 12)
connect _WIRE_276.sr, _T_3782
node _T_3783 = bits(_WIRE_277, 13, 13)
connect _WIRE_276.sx, _T_3783
node _T_3784 = bits(_WIRE_277, 14, 14)
connect _WIRE_276.sw, _T_3784
node _T_3785 = bits(_WIRE_277, 15, 15)
connect _WIRE_276.gf, _T_3785
node _T_3786 = bits(_WIRE_277, 16, 16)
connect _WIRE_276.pf, _T_3786
node _T_3787 = bits(_WIRE_277, 17, 17)
connect _WIRE_276.ae_stage2, _T_3787
node _T_3788 = bits(_WIRE_277, 18, 18)
connect _WIRE_276.ae_final, _T_3788
node _T_3789 = bits(_WIRE_277, 19, 19)
connect _WIRE_276.ae_ptw, _T_3789
node _T_3790 = bits(_WIRE_277, 20, 20)
connect _WIRE_276.g, _T_3790
node _T_3791 = bits(_WIRE_277, 21, 21)
connect _WIRE_276.u, _T_3791
node _T_3792 = bits(_WIRE_277, 41, 22)
connect _WIRE_276.ppn, _T_3792
node _T_3793 = eq(superpage_entries[3].tag_v, hv_11)
node _T_3794 = eq(_WIRE_276.g, UInt<1>(0h0))
node _T_3795 = and(_T_3793, _T_3794)
when _T_3795 :
connect superpage_entries[3].valid[0], UInt<1>(0h0)
else :
node _T_3796 = or(hv_11, hg_11)
wire _WIRE_278 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_279 : UInt<42>
connect _WIRE_279, superpage_entries[3].data[0]
node _T_3797 = bits(_WIRE_279, 0, 0)
connect _WIRE_278.fragmented_superpage, _T_3797
node _T_3798 = bits(_WIRE_279, 1, 1)
connect _WIRE_278.c, _T_3798
node _T_3799 = bits(_WIRE_279, 2, 2)
connect _WIRE_278.eff, _T_3799
node _T_3800 = bits(_WIRE_279, 3, 3)
connect _WIRE_278.paa, _T_3800
node _T_3801 = bits(_WIRE_279, 4, 4)
connect _WIRE_278.pal, _T_3801
node _T_3802 = bits(_WIRE_279, 5, 5)
connect _WIRE_278.ppp, _T_3802
node _T_3803 = bits(_WIRE_279, 6, 6)
connect _WIRE_278.pr, _T_3803
node _T_3804 = bits(_WIRE_279, 7, 7)
connect _WIRE_278.px, _T_3804
node _T_3805 = bits(_WIRE_279, 8, 8)
connect _WIRE_278.pw, _T_3805
node _T_3806 = bits(_WIRE_279, 9, 9)
connect _WIRE_278.hr, _T_3806
node _T_3807 = bits(_WIRE_279, 10, 10)
connect _WIRE_278.hx, _T_3807
node _T_3808 = bits(_WIRE_279, 11, 11)
connect _WIRE_278.hw, _T_3808
node _T_3809 = bits(_WIRE_279, 12, 12)
connect _WIRE_278.sr, _T_3809
node _T_3810 = bits(_WIRE_279, 13, 13)
connect _WIRE_278.sx, _T_3810
node _T_3811 = bits(_WIRE_279, 14, 14)
connect _WIRE_278.sw, _T_3811
node _T_3812 = bits(_WIRE_279, 15, 15)
connect _WIRE_278.gf, _T_3812
node _T_3813 = bits(_WIRE_279, 16, 16)
connect _WIRE_278.pf, _T_3813
node _T_3814 = bits(_WIRE_279, 17, 17)
connect _WIRE_278.ae_stage2, _T_3814
node _T_3815 = bits(_WIRE_279, 18, 18)
connect _WIRE_278.ae_final, _T_3815
node _T_3816 = bits(_WIRE_279, 19, 19)
connect _WIRE_278.ae_ptw, _T_3816
node _T_3817 = bits(_WIRE_279, 20, 20)
connect _WIRE_278.g, _T_3817
node _T_3818 = bits(_WIRE_279, 21, 21)
connect _WIRE_278.u, _T_3818
node _T_3819 = bits(_WIRE_279, 41, 22)
connect _WIRE_278.ppn, _T_3819
node _T_3820 = eq(superpage_entries[3].tag_v, _T_3796)
when _T_3820 :
connect superpage_entries[3].valid[0], UInt<1>(0h0)
node hv_12 = and(UInt<1>(0h0), io.sfence.bits.hv)
node hg_12 = and(UInt<1>(0h0), io.sfence.bits.hg)
node _T_3821 = eq(hg_12, UInt<1>(0h0))
node _T_3822 = and(_T_3821, io.sfence.bits.rs1)
when _T_3822 :
node _tagMatch_T_4 = eq(special_entry.tag_v, hv_12)
node tagMatch_4 = and(special_entry.valid[0], _tagMatch_T_4)
node _ignore_T_12 = lt(special_entry.level, UInt<1>(0h0))
node ignore_12 = or(_ignore_T_12, UInt<1>(0h0))
node _T_3823 = xor(special_entry.tag_vpn, vpn)
node _T_3824 = bits(_T_3823, 26, 18)
node _T_3825 = eq(_T_3824, UInt<1>(0h0))
node _T_3826 = or(ignore_12, _T_3825)
node _T_3827 = and(tagMatch_4, _T_3826)
node _ignore_T_13 = lt(special_entry.level, UInt<1>(0h1))
node ignore_13 = or(_ignore_T_13, UInt<1>(0h0))
node _T_3828 = xor(special_entry.tag_vpn, vpn)
node _T_3829 = bits(_T_3828, 17, 9)
node _T_3830 = eq(_T_3829, UInt<1>(0h0))
node _T_3831 = or(ignore_13, _T_3830)
node _T_3832 = and(_T_3827, _T_3831)
node _ignore_T_14 = lt(special_entry.level, UInt<2>(0h2))
node ignore_14 = or(_ignore_T_14, UInt<1>(0h0))
node _T_3833 = xor(special_entry.tag_vpn, vpn)
node _T_3834 = bits(_T_3833, 8, 0)
node _T_3835 = eq(_T_3834, UInt<1>(0h0))
node _T_3836 = or(ignore_14, _T_3835)
node _T_3837 = and(_T_3832, _T_3836)
when _T_3837 :
connect special_entry.valid[0], UInt<1>(0h0)
node _T_3838 = xor(special_entry.tag_vpn, vpn)
node _T_3839 = shr(_T_3838, 18)
node _T_3840 = eq(_T_3839, UInt<1>(0h0))
when _T_3840 :
wire _WIRE_280 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_281 : UInt<42>
connect _WIRE_281, special_entry.data[0]
node _T_3841 = bits(_WIRE_281, 0, 0)
connect _WIRE_280.fragmented_superpage, _T_3841
node _T_3842 = bits(_WIRE_281, 1, 1)
connect _WIRE_280.c, _T_3842
node _T_3843 = bits(_WIRE_281, 2, 2)
connect _WIRE_280.eff, _T_3843
node _T_3844 = bits(_WIRE_281, 3, 3)
connect _WIRE_280.paa, _T_3844
node _T_3845 = bits(_WIRE_281, 4, 4)
connect _WIRE_280.pal, _T_3845
node _T_3846 = bits(_WIRE_281, 5, 5)
connect _WIRE_280.ppp, _T_3846
node _T_3847 = bits(_WIRE_281, 6, 6)
connect _WIRE_280.pr, _T_3847
node _T_3848 = bits(_WIRE_281, 7, 7)
connect _WIRE_280.px, _T_3848
node _T_3849 = bits(_WIRE_281, 8, 8)
connect _WIRE_280.pw, _T_3849
node _T_3850 = bits(_WIRE_281, 9, 9)
connect _WIRE_280.hr, _T_3850
node _T_3851 = bits(_WIRE_281, 10, 10)
connect _WIRE_280.hx, _T_3851
node _T_3852 = bits(_WIRE_281, 11, 11)
connect _WIRE_280.hw, _T_3852
node _T_3853 = bits(_WIRE_281, 12, 12)
connect _WIRE_280.sr, _T_3853
node _T_3854 = bits(_WIRE_281, 13, 13)
connect _WIRE_280.sx, _T_3854
node _T_3855 = bits(_WIRE_281, 14, 14)
connect _WIRE_280.sw, _T_3855
node _T_3856 = bits(_WIRE_281, 15, 15)
connect _WIRE_280.gf, _T_3856
node _T_3857 = bits(_WIRE_281, 16, 16)
connect _WIRE_280.pf, _T_3857
node _T_3858 = bits(_WIRE_281, 17, 17)
connect _WIRE_280.ae_stage2, _T_3858
node _T_3859 = bits(_WIRE_281, 18, 18)
connect _WIRE_280.ae_final, _T_3859
node _T_3860 = bits(_WIRE_281, 19, 19)
connect _WIRE_280.ae_ptw, _T_3860
node _T_3861 = bits(_WIRE_281, 20, 20)
connect _WIRE_280.g, _T_3861
node _T_3862 = bits(_WIRE_281, 21, 21)
connect _WIRE_280.u, _T_3862
node _T_3863 = bits(_WIRE_281, 41, 22)
connect _WIRE_280.ppn, _T_3863
node _T_3864 = eq(special_entry.tag_v, hv_12)
node _T_3865 = and(_T_3864, _WIRE_280.fragmented_superpage)
when _T_3865 :
connect special_entry.valid[0], UInt<1>(0h0)
else :
node _T_3866 = eq(hg_12, UInt<1>(0h0))
node _T_3867 = and(_T_3866, io.sfence.bits.rs2)
when _T_3867 :
wire _WIRE_282 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_283 : UInt<42>
connect _WIRE_283, special_entry.data[0]
node _T_3868 = bits(_WIRE_283, 0, 0)
connect _WIRE_282.fragmented_superpage, _T_3868
node _T_3869 = bits(_WIRE_283, 1, 1)
connect _WIRE_282.c, _T_3869
node _T_3870 = bits(_WIRE_283, 2, 2)
connect _WIRE_282.eff, _T_3870
node _T_3871 = bits(_WIRE_283, 3, 3)
connect _WIRE_282.paa, _T_3871
node _T_3872 = bits(_WIRE_283, 4, 4)
connect _WIRE_282.pal, _T_3872
node _T_3873 = bits(_WIRE_283, 5, 5)
connect _WIRE_282.ppp, _T_3873
node _T_3874 = bits(_WIRE_283, 6, 6)
connect _WIRE_282.pr, _T_3874
node _T_3875 = bits(_WIRE_283, 7, 7)
connect _WIRE_282.px, _T_3875
node _T_3876 = bits(_WIRE_283, 8, 8)
connect _WIRE_282.pw, _T_3876
node _T_3877 = bits(_WIRE_283, 9, 9)
connect _WIRE_282.hr, _T_3877
node _T_3878 = bits(_WIRE_283, 10, 10)
connect _WIRE_282.hx, _T_3878
node _T_3879 = bits(_WIRE_283, 11, 11)
connect _WIRE_282.hw, _T_3879
node _T_3880 = bits(_WIRE_283, 12, 12)
connect _WIRE_282.sr, _T_3880
node _T_3881 = bits(_WIRE_283, 13, 13)
connect _WIRE_282.sx, _T_3881
node _T_3882 = bits(_WIRE_283, 14, 14)
connect _WIRE_282.sw, _T_3882
node _T_3883 = bits(_WIRE_283, 15, 15)
connect _WIRE_282.gf, _T_3883
node _T_3884 = bits(_WIRE_283, 16, 16)
connect _WIRE_282.pf, _T_3884
node _T_3885 = bits(_WIRE_283, 17, 17)
connect _WIRE_282.ae_stage2, _T_3885
node _T_3886 = bits(_WIRE_283, 18, 18)
connect _WIRE_282.ae_final, _T_3886
node _T_3887 = bits(_WIRE_283, 19, 19)
connect _WIRE_282.ae_ptw, _T_3887
node _T_3888 = bits(_WIRE_283, 20, 20)
connect _WIRE_282.g, _T_3888
node _T_3889 = bits(_WIRE_283, 21, 21)
connect _WIRE_282.u, _T_3889
node _T_3890 = bits(_WIRE_283, 41, 22)
connect _WIRE_282.ppn, _T_3890
node _T_3891 = eq(special_entry.tag_v, hv_12)
node _T_3892 = eq(_WIRE_282.g, UInt<1>(0h0))
node _T_3893 = and(_T_3891, _T_3892)
when _T_3893 :
connect special_entry.valid[0], UInt<1>(0h0)
else :
node _T_3894 = or(hv_12, hg_12)
wire _WIRE_284 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_285 : UInt<42>
connect _WIRE_285, special_entry.data[0]
node _T_3895 = bits(_WIRE_285, 0, 0)
connect _WIRE_284.fragmented_superpage, _T_3895
node _T_3896 = bits(_WIRE_285, 1, 1)
connect _WIRE_284.c, _T_3896
node _T_3897 = bits(_WIRE_285, 2, 2)
connect _WIRE_284.eff, _T_3897
node _T_3898 = bits(_WIRE_285, 3, 3)
connect _WIRE_284.paa, _T_3898
node _T_3899 = bits(_WIRE_285, 4, 4)
connect _WIRE_284.pal, _T_3899
node _T_3900 = bits(_WIRE_285, 5, 5)
connect _WIRE_284.ppp, _T_3900
node _T_3901 = bits(_WIRE_285, 6, 6)
connect _WIRE_284.pr, _T_3901
node _T_3902 = bits(_WIRE_285, 7, 7)
connect _WIRE_284.px, _T_3902
node _T_3903 = bits(_WIRE_285, 8, 8)
connect _WIRE_284.pw, _T_3903
node _T_3904 = bits(_WIRE_285, 9, 9)
connect _WIRE_284.hr, _T_3904
node _T_3905 = bits(_WIRE_285, 10, 10)
connect _WIRE_284.hx, _T_3905
node _T_3906 = bits(_WIRE_285, 11, 11)
connect _WIRE_284.hw, _T_3906
node _T_3907 = bits(_WIRE_285, 12, 12)
connect _WIRE_284.sr, _T_3907
node _T_3908 = bits(_WIRE_285, 13, 13)
connect _WIRE_284.sx, _T_3908
node _T_3909 = bits(_WIRE_285, 14, 14)
connect _WIRE_284.sw, _T_3909
node _T_3910 = bits(_WIRE_285, 15, 15)
connect _WIRE_284.gf, _T_3910
node _T_3911 = bits(_WIRE_285, 16, 16)
connect _WIRE_284.pf, _T_3911
node _T_3912 = bits(_WIRE_285, 17, 17)
connect _WIRE_284.ae_stage2, _T_3912
node _T_3913 = bits(_WIRE_285, 18, 18)
connect _WIRE_284.ae_final, _T_3913
node _T_3914 = bits(_WIRE_285, 19, 19)
connect _WIRE_284.ae_ptw, _T_3914
node _T_3915 = bits(_WIRE_285, 20, 20)
connect _WIRE_284.g, _T_3915
node _T_3916 = bits(_WIRE_285, 21, 21)
connect _WIRE_284.u, _T_3916
node _T_3917 = bits(_WIRE_285, 41, 22)
connect _WIRE_284.ppn, _T_3917
node _T_3918 = eq(special_entry.tag_v, _T_3894)
when _T_3918 :
connect special_entry.valid[0], UInt<1>(0h0)
node _T_3919 = and(io.req.ready, io.req.valid)
node _T_3920 = and(_T_3919, vsatp_mode_mismatch)
when _T_3920 :
wire _WIRE_286 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_287 : UInt<42>
connect _WIRE_287, sectored_entries[0][0].data[0]
node _T_3921 = bits(_WIRE_287, 0, 0)
connect _WIRE_286.fragmented_superpage, _T_3921
node _T_3922 = bits(_WIRE_287, 1, 1)
connect _WIRE_286.c, _T_3922
node _T_3923 = bits(_WIRE_287, 2, 2)
connect _WIRE_286.eff, _T_3923
node _T_3924 = bits(_WIRE_287, 3, 3)
connect _WIRE_286.paa, _T_3924
node _T_3925 = bits(_WIRE_287, 4, 4)
connect _WIRE_286.pal, _T_3925
node _T_3926 = bits(_WIRE_287, 5, 5)
connect _WIRE_286.ppp, _T_3926
node _T_3927 = bits(_WIRE_287, 6, 6)
connect _WIRE_286.pr, _T_3927
node _T_3928 = bits(_WIRE_287, 7, 7)
connect _WIRE_286.px, _T_3928
node _T_3929 = bits(_WIRE_287, 8, 8)
connect _WIRE_286.pw, _T_3929
node _T_3930 = bits(_WIRE_287, 9, 9)
connect _WIRE_286.hr, _T_3930
node _T_3931 = bits(_WIRE_287, 10, 10)
connect _WIRE_286.hx, _T_3931
node _T_3932 = bits(_WIRE_287, 11, 11)
connect _WIRE_286.hw, _T_3932
node _T_3933 = bits(_WIRE_287, 12, 12)
connect _WIRE_286.sr, _T_3933
node _T_3934 = bits(_WIRE_287, 13, 13)
connect _WIRE_286.sx, _T_3934
node _T_3935 = bits(_WIRE_287, 14, 14)
connect _WIRE_286.sw, _T_3935
node _T_3936 = bits(_WIRE_287, 15, 15)
connect _WIRE_286.gf, _T_3936
node _T_3937 = bits(_WIRE_287, 16, 16)
connect _WIRE_286.pf, _T_3937
node _T_3938 = bits(_WIRE_287, 17, 17)
connect _WIRE_286.ae_stage2, _T_3938
node _T_3939 = bits(_WIRE_287, 18, 18)
connect _WIRE_286.ae_final, _T_3939
node _T_3940 = bits(_WIRE_287, 19, 19)
connect _WIRE_286.ae_ptw, _T_3940
node _T_3941 = bits(_WIRE_287, 20, 20)
connect _WIRE_286.g, _T_3941
node _T_3942 = bits(_WIRE_287, 21, 21)
connect _WIRE_286.u, _T_3942
node _T_3943 = bits(_WIRE_287, 41, 22)
connect _WIRE_286.ppn, _T_3943
wire _WIRE_288 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_289 : UInt<42>
connect _WIRE_289, sectored_entries[0][0].data[1]
node _T_3944 = bits(_WIRE_289, 0, 0)
connect _WIRE_288.fragmented_superpage, _T_3944
node _T_3945 = bits(_WIRE_289, 1, 1)
connect _WIRE_288.c, _T_3945
node _T_3946 = bits(_WIRE_289, 2, 2)
connect _WIRE_288.eff, _T_3946
node _T_3947 = bits(_WIRE_289, 3, 3)
connect _WIRE_288.paa, _T_3947
node _T_3948 = bits(_WIRE_289, 4, 4)
connect _WIRE_288.pal, _T_3948
node _T_3949 = bits(_WIRE_289, 5, 5)
connect _WIRE_288.ppp, _T_3949
node _T_3950 = bits(_WIRE_289, 6, 6)
connect _WIRE_288.pr, _T_3950
node _T_3951 = bits(_WIRE_289, 7, 7)
connect _WIRE_288.px, _T_3951
node _T_3952 = bits(_WIRE_289, 8, 8)
connect _WIRE_288.pw, _T_3952
node _T_3953 = bits(_WIRE_289, 9, 9)
connect _WIRE_288.hr, _T_3953
node _T_3954 = bits(_WIRE_289, 10, 10)
connect _WIRE_288.hx, _T_3954
node _T_3955 = bits(_WIRE_289, 11, 11)
connect _WIRE_288.hw, _T_3955
node _T_3956 = bits(_WIRE_289, 12, 12)
connect _WIRE_288.sr, _T_3956
node _T_3957 = bits(_WIRE_289, 13, 13)
connect _WIRE_288.sx, _T_3957
node _T_3958 = bits(_WIRE_289, 14, 14)
connect _WIRE_288.sw, _T_3958
node _T_3959 = bits(_WIRE_289, 15, 15)
connect _WIRE_288.gf, _T_3959
node _T_3960 = bits(_WIRE_289, 16, 16)
connect _WIRE_288.pf, _T_3960
node _T_3961 = bits(_WIRE_289, 17, 17)
connect _WIRE_288.ae_stage2, _T_3961
node _T_3962 = bits(_WIRE_289, 18, 18)
connect _WIRE_288.ae_final, _T_3962
node _T_3963 = bits(_WIRE_289, 19, 19)
connect _WIRE_288.ae_ptw, _T_3963
node _T_3964 = bits(_WIRE_289, 20, 20)
connect _WIRE_288.g, _T_3964
node _T_3965 = bits(_WIRE_289, 21, 21)
connect _WIRE_288.u, _T_3965
node _T_3966 = bits(_WIRE_289, 41, 22)
connect _WIRE_288.ppn, _T_3966
wire _WIRE_290 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_291 : UInt<42>
connect _WIRE_291, sectored_entries[0][0].data[2]
node _T_3967 = bits(_WIRE_291, 0, 0)
connect _WIRE_290.fragmented_superpage, _T_3967
node _T_3968 = bits(_WIRE_291, 1, 1)
connect _WIRE_290.c, _T_3968
node _T_3969 = bits(_WIRE_291, 2, 2)
connect _WIRE_290.eff, _T_3969
node _T_3970 = bits(_WIRE_291, 3, 3)
connect _WIRE_290.paa, _T_3970
node _T_3971 = bits(_WIRE_291, 4, 4)
connect _WIRE_290.pal, _T_3971
node _T_3972 = bits(_WIRE_291, 5, 5)
connect _WIRE_290.ppp, _T_3972
node _T_3973 = bits(_WIRE_291, 6, 6)
connect _WIRE_290.pr, _T_3973
node _T_3974 = bits(_WIRE_291, 7, 7)
connect _WIRE_290.px, _T_3974
node _T_3975 = bits(_WIRE_291, 8, 8)
connect _WIRE_290.pw, _T_3975
node _T_3976 = bits(_WIRE_291, 9, 9)
connect _WIRE_290.hr, _T_3976
node _T_3977 = bits(_WIRE_291, 10, 10)
connect _WIRE_290.hx, _T_3977
node _T_3978 = bits(_WIRE_291, 11, 11)
connect _WIRE_290.hw, _T_3978
node _T_3979 = bits(_WIRE_291, 12, 12)
connect _WIRE_290.sr, _T_3979
node _T_3980 = bits(_WIRE_291, 13, 13)
connect _WIRE_290.sx, _T_3980
node _T_3981 = bits(_WIRE_291, 14, 14)
connect _WIRE_290.sw, _T_3981
node _T_3982 = bits(_WIRE_291, 15, 15)
connect _WIRE_290.gf, _T_3982
node _T_3983 = bits(_WIRE_291, 16, 16)
connect _WIRE_290.pf, _T_3983
node _T_3984 = bits(_WIRE_291, 17, 17)
connect _WIRE_290.ae_stage2, _T_3984
node _T_3985 = bits(_WIRE_291, 18, 18)
connect _WIRE_290.ae_final, _T_3985
node _T_3986 = bits(_WIRE_291, 19, 19)
connect _WIRE_290.ae_ptw, _T_3986
node _T_3987 = bits(_WIRE_291, 20, 20)
connect _WIRE_290.g, _T_3987
node _T_3988 = bits(_WIRE_291, 21, 21)
connect _WIRE_290.u, _T_3988
node _T_3989 = bits(_WIRE_291, 41, 22)
connect _WIRE_290.ppn, _T_3989
wire _WIRE_292 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_293 : UInt<42>
connect _WIRE_293, sectored_entries[0][0].data[3]
node _T_3990 = bits(_WIRE_293, 0, 0)
connect _WIRE_292.fragmented_superpage, _T_3990
node _T_3991 = bits(_WIRE_293, 1, 1)
connect _WIRE_292.c, _T_3991
node _T_3992 = bits(_WIRE_293, 2, 2)
connect _WIRE_292.eff, _T_3992
node _T_3993 = bits(_WIRE_293, 3, 3)
connect _WIRE_292.paa, _T_3993
node _T_3994 = bits(_WIRE_293, 4, 4)
connect _WIRE_292.pal, _T_3994
node _T_3995 = bits(_WIRE_293, 5, 5)
connect _WIRE_292.ppp, _T_3995
node _T_3996 = bits(_WIRE_293, 6, 6)
connect _WIRE_292.pr, _T_3996
node _T_3997 = bits(_WIRE_293, 7, 7)
connect _WIRE_292.px, _T_3997
node _T_3998 = bits(_WIRE_293, 8, 8)
connect _WIRE_292.pw, _T_3998
node _T_3999 = bits(_WIRE_293, 9, 9)
connect _WIRE_292.hr, _T_3999
node _T_4000 = bits(_WIRE_293, 10, 10)
connect _WIRE_292.hx, _T_4000
node _T_4001 = bits(_WIRE_293, 11, 11)
connect _WIRE_292.hw, _T_4001
node _T_4002 = bits(_WIRE_293, 12, 12)
connect _WIRE_292.sr, _T_4002
node _T_4003 = bits(_WIRE_293, 13, 13)
connect _WIRE_292.sx, _T_4003
node _T_4004 = bits(_WIRE_293, 14, 14)
connect _WIRE_292.sw, _T_4004
node _T_4005 = bits(_WIRE_293, 15, 15)
connect _WIRE_292.gf, _T_4005
node _T_4006 = bits(_WIRE_293, 16, 16)
connect _WIRE_292.pf, _T_4006
node _T_4007 = bits(_WIRE_293, 17, 17)
connect _WIRE_292.ae_stage2, _T_4007
node _T_4008 = bits(_WIRE_293, 18, 18)
connect _WIRE_292.ae_final, _T_4008
node _T_4009 = bits(_WIRE_293, 19, 19)
connect _WIRE_292.ae_ptw, _T_4009
node _T_4010 = bits(_WIRE_293, 20, 20)
connect _WIRE_292.g, _T_4010
node _T_4011 = bits(_WIRE_293, 21, 21)
connect _WIRE_292.u, _T_4011
node _T_4012 = bits(_WIRE_293, 41, 22)
connect _WIRE_292.ppn, _T_4012
node _T_4013 = eq(sectored_entries[0][0].tag_v, UInt<1>(0h1))
when _T_4013 :
connect sectored_entries[0][0].valid[0], UInt<1>(0h0)
node _T_4014 = eq(sectored_entries[0][0].tag_v, UInt<1>(0h1))
when _T_4014 :
connect sectored_entries[0][0].valid[1], UInt<1>(0h0)
node _T_4015 = eq(sectored_entries[0][0].tag_v, UInt<1>(0h1))
when _T_4015 :
connect sectored_entries[0][0].valid[2], UInt<1>(0h0)
node _T_4016 = eq(sectored_entries[0][0].tag_v, UInt<1>(0h1))
when _T_4016 :
connect sectored_entries[0][0].valid[3], UInt<1>(0h0)
wire _WIRE_294 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_295 : UInt<42>
connect _WIRE_295, sectored_entries[0][1].data[0]
node _T_4017 = bits(_WIRE_295, 0, 0)
connect _WIRE_294.fragmented_superpage, _T_4017
node _T_4018 = bits(_WIRE_295, 1, 1)
connect _WIRE_294.c, _T_4018
node _T_4019 = bits(_WIRE_295, 2, 2)
connect _WIRE_294.eff, _T_4019
node _T_4020 = bits(_WIRE_295, 3, 3)
connect _WIRE_294.paa, _T_4020
node _T_4021 = bits(_WIRE_295, 4, 4)
connect _WIRE_294.pal, _T_4021
node _T_4022 = bits(_WIRE_295, 5, 5)
connect _WIRE_294.ppp, _T_4022
node _T_4023 = bits(_WIRE_295, 6, 6)
connect _WIRE_294.pr, _T_4023
node _T_4024 = bits(_WIRE_295, 7, 7)
connect _WIRE_294.px, _T_4024
node _T_4025 = bits(_WIRE_295, 8, 8)
connect _WIRE_294.pw, _T_4025
node _T_4026 = bits(_WIRE_295, 9, 9)
connect _WIRE_294.hr, _T_4026
node _T_4027 = bits(_WIRE_295, 10, 10)
connect _WIRE_294.hx, _T_4027
node _T_4028 = bits(_WIRE_295, 11, 11)
connect _WIRE_294.hw, _T_4028
node _T_4029 = bits(_WIRE_295, 12, 12)
connect _WIRE_294.sr, _T_4029
node _T_4030 = bits(_WIRE_295, 13, 13)
connect _WIRE_294.sx, _T_4030
node _T_4031 = bits(_WIRE_295, 14, 14)
connect _WIRE_294.sw, _T_4031
node _T_4032 = bits(_WIRE_295, 15, 15)
connect _WIRE_294.gf, _T_4032
node _T_4033 = bits(_WIRE_295, 16, 16)
connect _WIRE_294.pf, _T_4033
node _T_4034 = bits(_WIRE_295, 17, 17)
connect _WIRE_294.ae_stage2, _T_4034
node _T_4035 = bits(_WIRE_295, 18, 18)
connect _WIRE_294.ae_final, _T_4035
node _T_4036 = bits(_WIRE_295, 19, 19)
connect _WIRE_294.ae_ptw, _T_4036
node _T_4037 = bits(_WIRE_295, 20, 20)
connect _WIRE_294.g, _T_4037
node _T_4038 = bits(_WIRE_295, 21, 21)
connect _WIRE_294.u, _T_4038
node _T_4039 = bits(_WIRE_295, 41, 22)
connect _WIRE_294.ppn, _T_4039
wire _WIRE_296 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_297 : UInt<42>
connect _WIRE_297, sectored_entries[0][1].data[1]
node _T_4040 = bits(_WIRE_297, 0, 0)
connect _WIRE_296.fragmented_superpage, _T_4040
node _T_4041 = bits(_WIRE_297, 1, 1)
connect _WIRE_296.c, _T_4041
node _T_4042 = bits(_WIRE_297, 2, 2)
connect _WIRE_296.eff, _T_4042
node _T_4043 = bits(_WIRE_297, 3, 3)
connect _WIRE_296.paa, _T_4043
node _T_4044 = bits(_WIRE_297, 4, 4)
connect _WIRE_296.pal, _T_4044
node _T_4045 = bits(_WIRE_297, 5, 5)
connect _WIRE_296.ppp, _T_4045
node _T_4046 = bits(_WIRE_297, 6, 6)
connect _WIRE_296.pr, _T_4046
node _T_4047 = bits(_WIRE_297, 7, 7)
connect _WIRE_296.px, _T_4047
node _T_4048 = bits(_WIRE_297, 8, 8)
connect _WIRE_296.pw, _T_4048
node _T_4049 = bits(_WIRE_297, 9, 9)
connect _WIRE_296.hr, _T_4049
node _T_4050 = bits(_WIRE_297, 10, 10)
connect _WIRE_296.hx, _T_4050
node _T_4051 = bits(_WIRE_297, 11, 11)
connect _WIRE_296.hw, _T_4051
node _T_4052 = bits(_WIRE_297, 12, 12)
connect _WIRE_296.sr, _T_4052
node _T_4053 = bits(_WIRE_297, 13, 13)
connect _WIRE_296.sx, _T_4053
node _T_4054 = bits(_WIRE_297, 14, 14)
connect _WIRE_296.sw, _T_4054
node _T_4055 = bits(_WIRE_297, 15, 15)
connect _WIRE_296.gf, _T_4055
node _T_4056 = bits(_WIRE_297, 16, 16)
connect _WIRE_296.pf, _T_4056
node _T_4057 = bits(_WIRE_297, 17, 17)
connect _WIRE_296.ae_stage2, _T_4057
node _T_4058 = bits(_WIRE_297, 18, 18)
connect _WIRE_296.ae_final, _T_4058
node _T_4059 = bits(_WIRE_297, 19, 19)
connect _WIRE_296.ae_ptw, _T_4059
node _T_4060 = bits(_WIRE_297, 20, 20)
connect _WIRE_296.g, _T_4060
node _T_4061 = bits(_WIRE_297, 21, 21)
connect _WIRE_296.u, _T_4061
node _T_4062 = bits(_WIRE_297, 41, 22)
connect _WIRE_296.ppn, _T_4062
wire _WIRE_298 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_299 : UInt<42>
connect _WIRE_299, sectored_entries[0][1].data[2]
node _T_4063 = bits(_WIRE_299, 0, 0)
connect _WIRE_298.fragmented_superpage, _T_4063
node _T_4064 = bits(_WIRE_299, 1, 1)
connect _WIRE_298.c, _T_4064
node _T_4065 = bits(_WIRE_299, 2, 2)
connect _WIRE_298.eff, _T_4065
node _T_4066 = bits(_WIRE_299, 3, 3)
connect _WIRE_298.paa, _T_4066
node _T_4067 = bits(_WIRE_299, 4, 4)
connect _WIRE_298.pal, _T_4067
node _T_4068 = bits(_WIRE_299, 5, 5)
connect _WIRE_298.ppp, _T_4068
node _T_4069 = bits(_WIRE_299, 6, 6)
connect _WIRE_298.pr, _T_4069
node _T_4070 = bits(_WIRE_299, 7, 7)
connect _WIRE_298.px, _T_4070
node _T_4071 = bits(_WIRE_299, 8, 8)
connect _WIRE_298.pw, _T_4071
node _T_4072 = bits(_WIRE_299, 9, 9)
connect _WIRE_298.hr, _T_4072
node _T_4073 = bits(_WIRE_299, 10, 10)
connect _WIRE_298.hx, _T_4073
node _T_4074 = bits(_WIRE_299, 11, 11)
connect _WIRE_298.hw, _T_4074
node _T_4075 = bits(_WIRE_299, 12, 12)
connect _WIRE_298.sr, _T_4075
node _T_4076 = bits(_WIRE_299, 13, 13)
connect _WIRE_298.sx, _T_4076
node _T_4077 = bits(_WIRE_299, 14, 14)
connect _WIRE_298.sw, _T_4077
node _T_4078 = bits(_WIRE_299, 15, 15)
connect _WIRE_298.gf, _T_4078
node _T_4079 = bits(_WIRE_299, 16, 16)
connect _WIRE_298.pf, _T_4079
node _T_4080 = bits(_WIRE_299, 17, 17)
connect _WIRE_298.ae_stage2, _T_4080
node _T_4081 = bits(_WIRE_299, 18, 18)
connect _WIRE_298.ae_final, _T_4081
node _T_4082 = bits(_WIRE_299, 19, 19)
connect _WIRE_298.ae_ptw, _T_4082
node _T_4083 = bits(_WIRE_299, 20, 20)
connect _WIRE_298.g, _T_4083
node _T_4084 = bits(_WIRE_299, 21, 21)
connect _WIRE_298.u, _T_4084
node _T_4085 = bits(_WIRE_299, 41, 22)
connect _WIRE_298.ppn, _T_4085
wire _WIRE_300 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_301 : UInt<42>
connect _WIRE_301, sectored_entries[0][1].data[3]
node _T_4086 = bits(_WIRE_301, 0, 0)
connect _WIRE_300.fragmented_superpage, _T_4086
node _T_4087 = bits(_WIRE_301, 1, 1)
connect _WIRE_300.c, _T_4087
node _T_4088 = bits(_WIRE_301, 2, 2)
connect _WIRE_300.eff, _T_4088
node _T_4089 = bits(_WIRE_301, 3, 3)
connect _WIRE_300.paa, _T_4089
node _T_4090 = bits(_WIRE_301, 4, 4)
connect _WIRE_300.pal, _T_4090
node _T_4091 = bits(_WIRE_301, 5, 5)
connect _WIRE_300.ppp, _T_4091
node _T_4092 = bits(_WIRE_301, 6, 6)
connect _WIRE_300.pr, _T_4092
node _T_4093 = bits(_WIRE_301, 7, 7)
connect _WIRE_300.px, _T_4093
node _T_4094 = bits(_WIRE_301, 8, 8)
connect _WIRE_300.pw, _T_4094
node _T_4095 = bits(_WIRE_301, 9, 9)
connect _WIRE_300.hr, _T_4095
node _T_4096 = bits(_WIRE_301, 10, 10)
connect _WIRE_300.hx, _T_4096
node _T_4097 = bits(_WIRE_301, 11, 11)
connect _WIRE_300.hw, _T_4097
node _T_4098 = bits(_WIRE_301, 12, 12)
connect _WIRE_300.sr, _T_4098
node _T_4099 = bits(_WIRE_301, 13, 13)
connect _WIRE_300.sx, _T_4099
node _T_4100 = bits(_WIRE_301, 14, 14)
connect _WIRE_300.sw, _T_4100
node _T_4101 = bits(_WIRE_301, 15, 15)
connect _WIRE_300.gf, _T_4101
node _T_4102 = bits(_WIRE_301, 16, 16)
connect _WIRE_300.pf, _T_4102
node _T_4103 = bits(_WIRE_301, 17, 17)
connect _WIRE_300.ae_stage2, _T_4103
node _T_4104 = bits(_WIRE_301, 18, 18)
connect _WIRE_300.ae_final, _T_4104
node _T_4105 = bits(_WIRE_301, 19, 19)
connect _WIRE_300.ae_ptw, _T_4105
node _T_4106 = bits(_WIRE_301, 20, 20)
connect _WIRE_300.g, _T_4106
node _T_4107 = bits(_WIRE_301, 21, 21)
connect _WIRE_300.u, _T_4107
node _T_4108 = bits(_WIRE_301, 41, 22)
connect _WIRE_300.ppn, _T_4108
node _T_4109 = eq(sectored_entries[0][1].tag_v, UInt<1>(0h1))
when _T_4109 :
connect sectored_entries[0][1].valid[0], UInt<1>(0h0)
node _T_4110 = eq(sectored_entries[0][1].tag_v, UInt<1>(0h1))
when _T_4110 :
connect sectored_entries[0][1].valid[1], UInt<1>(0h0)
node _T_4111 = eq(sectored_entries[0][1].tag_v, UInt<1>(0h1))
when _T_4111 :
connect sectored_entries[0][1].valid[2], UInt<1>(0h0)
node _T_4112 = eq(sectored_entries[0][1].tag_v, UInt<1>(0h1))
when _T_4112 :
connect sectored_entries[0][1].valid[3], UInt<1>(0h0)
wire _WIRE_302 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_303 : UInt<42>
connect _WIRE_303, sectored_entries[0][2].data[0]
node _T_4113 = bits(_WIRE_303, 0, 0)
connect _WIRE_302.fragmented_superpage, _T_4113
node _T_4114 = bits(_WIRE_303, 1, 1)
connect _WIRE_302.c, _T_4114
node _T_4115 = bits(_WIRE_303, 2, 2)
connect _WIRE_302.eff, _T_4115
node _T_4116 = bits(_WIRE_303, 3, 3)
connect _WIRE_302.paa, _T_4116
node _T_4117 = bits(_WIRE_303, 4, 4)
connect _WIRE_302.pal, _T_4117
node _T_4118 = bits(_WIRE_303, 5, 5)
connect _WIRE_302.ppp, _T_4118
node _T_4119 = bits(_WIRE_303, 6, 6)
connect _WIRE_302.pr, _T_4119
node _T_4120 = bits(_WIRE_303, 7, 7)
connect _WIRE_302.px, _T_4120
node _T_4121 = bits(_WIRE_303, 8, 8)
connect _WIRE_302.pw, _T_4121
node _T_4122 = bits(_WIRE_303, 9, 9)
connect _WIRE_302.hr, _T_4122
node _T_4123 = bits(_WIRE_303, 10, 10)
connect _WIRE_302.hx, _T_4123
node _T_4124 = bits(_WIRE_303, 11, 11)
connect _WIRE_302.hw, _T_4124
node _T_4125 = bits(_WIRE_303, 12, 12)
connect _WIRE_302.sr, _T_4125
node _T_4126 = bits(_WIRE_303, 13, 13)
connect _WIRE_302.sx, _T_4126
node _T_4127 = bits(_WIRE_303, 14, 14)
connect _WIRE_302.sw, _T_4127
node _T_4128 = bits(_WIRE_303, 15, 15)
connect _WIRE_302.gf, _T_4128
node _T_4129 = bits(_WIRE_303, 16, 16)
connect _WIRE_302.pf, _T_4129
node _T_4130 = bits(_WIRE_303, 17, 17)
connect _WIRE_302.ae_stage2, _T_4130
node _T_4131 = bits(_WIRE_303, 18, 18)
connect _WIRE_302.ae_final, _T_4131
node _T_4132 = bits(_WIRE_303, 19, 19)
connect _WIRE_302.ae_ptw, _T_4132
node _T_4133 = bits(_WIRE_303, 20, 20)
connect _WIRE_302.g, _T_4133
node _T_4134 = bits(_WIRE_303, 21, 21)
connect _WIRE_302.u, _T_4134
node _T_4135 = bits(_WIRE_303, 41, 22)
connect _WIRE_302.ppn, _T_4135
wire _WIRE_304 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_305 : UInt<42>
connect _WIRE_305, sectored_entries[0][2].data[1]
node _T_4136 = bits(_WIRE_305, 0, 0)
connect _WIRE_304.fragmented_superpage, _T_4136
node _T_4137 = bits(_WIRE_305, 1, 1)
connect _WIRE_304.c, _T_4137
node _T_4138 = bits(_WIRE_305, 2, 2)
connect _WIRE_304.eff, _T_4138
node _T_4139 = bits(_WIRE_305, 3, 3)
connect _WIRE_304.paa, _T_4139
node _T_4140 = bits(_WIRE_305, 4, 4)
connect _WIRE_304.pal, _T_4140
node _T_4141 = bits(_WIRE_305, 5, 5)
connect _WIRE_304.ppp, _T_4141
node _T_4142 = bits(_WIRE_305, 6, 6)
connect _WIRE_304.pr, _T_4142
node _T_4143 = bits(_WIRE_305, 7, 7)
connect _WIRE_304.px, _T_4143
node _T_4144 = bits(_WIRE_305, 8, 8)
connect _WIRE_304.pw, _T_4144
node _T_4145 = bits(_WIRE_305, 9, 9)
connect _WIRE_304.hr, _T_4145
node _T_4146 = bits(_WIRE_305, 10, 10)
connect _WIRE_304.hx, _T_4146
node _T_4147 = bits(_WIRE_305, 11, 11)
connect _WIRE_304.hw, _T_4147
node _T_4148 = bits(_WIRE_305, 12, 12)
connect _WIRE_304.sr, _T_4148
node _T_4149 = bits(_WIRE_305, 13, 13)
connect _WIRE_304.sx, _T_4149
node _T_4150 = bits(_WIRE_305, 14, 14)
connect _WIRE_304.sw, _T_4150
node _T_4151 = bits(_WIRE_305, 15, 15)
connect _WIRE_304.gf, _T_4151
node _T_4152 = bits(_WIRE_305, 16, 16)
connect _WIRE_304.pf, _T_4152
node _T_4153 = bits(_WIRE_305, 17, 17)
connect _WIRE_304.ae_stage2, _T_4153
node _T_4154 = bits(_WIRE_305, 18, 18)
connect _WIRE_304.ae_final, _T_4154
node _T_4155 = bits(_WIRE_305, 19, 19)
connect _WIRE_304.ae_ptw, _T_4155
node _T_4156 = bits(_WIRE_305, 20, 20)
connect _WIRE_304.g, _T_4156
node _T_4157 = bits(_WIRE_305, 21, 21)
connect _WIRE_304.u, _T_4157
node _T_4158 = bits(_WIRE_305, 41, 22)
connect _WIRE_304.ppn, _T_4158
wire _WIRE_306 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_307 : UInt<42>
connect _WIRE_307, sectored_entries[0][2].data[2]
node _T_4159 = bits(_WIRE_307, 0, 0)
connect _WIRE_306.fragmented_superpage, _T_4159
node _T_4160 = bits(_WIRE_307, 1, 1)
connect _WIRE_306.c, _T_4160
node _T_4161 = bits(_WIRE_307, 2, 2)
connect _WIRE_306.eff, _T_4161
node _T_4162 = bits(_WIRE_307, 3, 3)
connect _WIRE_306.paa, _T_4162
node _T_4163 = bits(_WIRE_307, 4, 4)
connect _WIRE_306.pal, _T_4163
node _T_4164 = bits(_WIRE_307, 5, 5)
connect _WIRE_306.ppp, _T_4164
node _T_4165 = bits(_WIRE_307, 6, 6)
connect _WIRE_306.pr, _T_4165
node _T_4166 = bits(_WIRE_307, 7, 7)
connect _WIRE_306.px, _T_4166
node _T_4167 = bits(_WIRE_307, 8, 8)
connect _WIRE_306.pw, _T_4167
node _T_4168 = bits(_WIRE_307, 9, 9)
connect _WIRE_306.hr, _T_4168
node _T_4169 = bits(_WIRE_307, 10, 10)
connect _WIRE_306.hx, _T_4169
node _T_4170 = bits(_WIRE_307, 11, 11)
connect _WIRE_306.hw, _T_4170
node _T_4171 = bits(_WIRE_307, 12, 12)
connect _WIRE_306.sr, _T_4171
node _T_4172 = bits(_WIRE_307, 13, 13)
connect _WIRE_306.sx, _T_4172
node _T_4173 = bits(_WIRE_307, 14, 14)
connect _WIRE_306.sw, _T_4173
node _T_4174 = bits(_WIRE_307, 15, 15)
connect _WIRE_306.gf, _T_4174
node _T_4175 = bits(_WIRE_307, 16, 16)
connect _WIRE_306.pf, _T_4175
node _T_4176 = bits(_WIRE_307, 17, 17)
connect _WIRE_306.ae_stage2, _T_4176
node _T_4177 = bits(_WIRE_307, 18, 18)
connect _WIRE_306.ae_final, _T_4177
node _T_4178 = bits(_WIRE_307, 19, 19)
connect _WIRE_306.ae_ptw, _T_4178
node _T_4179 = bits(_WIRE_307, 20, 20)
connect _WIRE_306.g, _T_4179
node _T_4180 = bits(_WIRE_307, 21, 21)
connect _WIRE_306.u, _T_4180
node _T_4181 = bits(_WIRE_307, 41, 22)
connect _WIRE_306.ppn, _T_4181
wire _WIRE_308 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_309 : UInt<42>
connect _WIRE_309, sectored_entries[0][2].data[3]
node _T_4182 = bits(_WIRE_309, 0, 0)
connect _WIRE_308.fragmented_superpage, _T_4182
node _T_4183 = bits(_WIRE_309, 1, 1)
connect _WIRE_308.c, _T_4183
node _T_4184 = bits(_WIRE_309, 2, 2)
connect _WIRE_308.eff, _T_4184
node _T_4185 = bits(_WIRE_309, 3, 3)
connect _WIRE_308.paa, _T_4185
node _T_4186 = bits(_WIRE_309, 4, 4)
connect _WIRE_308.pal, _T_4186
node _T_4187 = bits(_WIRE_309, 5, 5)
connect _WIRE_308.ppp, _T_4187
node _T_4188 = bits(_WIRE_309, 6, 6)
connect _WIRE_308.pr, _T_4188
node _T_4189 = bits(_WIRE_309, 7, 7)
connect _WIRE_308.px, _T_4189
node _T_4190 = bits(_WIRE_309, 8, 8)
connect _WIRE_308.pw, _T_4190
node _T_4191 = bits(_WIRE_309, 9, 9)
connect _WIRE_308.hr, _T_4191
node _T_4192 = bits(_WIRE_309, 10, 10)
connect _WIRE_308.hx, _T_4192
node _T_4193 = bits(_WIRE_309, 11, 11)
connect _WIRE_308.hw, _T_4193
node _T_4194 = bits(_WIRE_309, 12, 12)
connect _WIRE_308.sr, _T_4194
node _T_4195 = bits(_WIRE_309, 13, 13)
connect _WIRE_308.sx, _T_4195
node _T_4196 = bits(_WIRE_309, 14, 14)
connect _WIRE_308.sw, _T_4196
node _T_4197 = bits(_WIRE_309, 15, 15)
connect _WIRE_308.gf, _T_4197
node _T_4198 = bits(_WIRE_309, 16, 16)
connect _WIRE_308.pf, _T_4198
node _T_4199 = bits(_WIRE_309, 17, 17)
connect _WIRE_308.ae_stage2, _T_4199
node _T_4200 = bits(_WIRE_309, 18, 18)
connect _WIRE_308.ae_final, _T_4200
node _T_4201 = bits(_WIRE_309, 19, 19)
connect _WIRE_308.ae_ptw, _T_4201
node _T_4202 = bits(_WIRE_309, 20, 20)
connect _WIRE_308.g, _T_4202
node _T_4203 = bits(_WIRE_309, 21, 21)
connect _WIRE_308.u, _T_4203
node _T_4204 = bits(_WIRE_309, 41, 22)
connect _WIRE_308.ppn, _T_4204
node _T_4205 = eq(sectored_entries[0][2].tag_v, UInt<1>(0h1))
when _T_4205 :
connect sectored_entries[0][2].valid[0], UInt<1>(0h0)
node _T_4206 = eq(sectored_entries[0][2].tag_v, UInt<1>(0h1))
when _T_4206 :
connect sectored_entries[0][2].valid[1], UInt<1>(0h0)
node _T_4207 = eq(sectored_entries[0][2].tag_v, UInt<1>(0h1))
when _T_4207 :
connect sectored_entries[0][2].valid[2], UInt<1>(0h0)
node _T_4208 = eq(sectored_entries[0][2].tag_v, UInt<1>(0h1))
when _T_4208 :
connect sectored_entries[0][2].valid[3], UInt<1>(0h0)
wire _WIRE_310 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_311 : UInt<42>
connect _WIRE_311, sectored_entries[0][3].data[0]
node _T_4209 = bits(_WIRE_311, 0, 0)
connect _WIRE_310.fragmented_superpage, _T_4209
node _T_4210 = bits(_WIRE_311, 1, 1)
connect _WIRE_310.c, _T_4210
node _T_4211 = bits(_WIRE_311, 2, 2)
connect _WIRE_310.eff, _T_4211
node _T_4212 = bits(_WIRE_311, 3, 3)
connect _WIRE_310.paa, _T_4212
node _T_4213 = bits(_WIRE_311, 4, 4)
connect _WIRE_310.pal, _T_4213
node _T_4214 = bits(_WIRE_311, 5, 5)
connect _WIRE_310.ppp, _T_4214
node _T_4215 = bits(_WIRE_311, 6, 6)
connect _WIRE_310.pr, _T_4215
node _T_4216 = bits(_WIRE_311, 7, 7)
connect _WIRE_310.px, _T_4216
node _T_4217 = bits(_WIRE_311, 8, 8)
connect _WIRE_310.pw, _T_4217
node _T_4218 = bits(_WIRE_311, 9, 9)
connect _WIRE_310.hr, _T_4218
node _T_4219 = bits(_WIRE_311, 10, 10)
connect _WIRE_310.hx, _T_4219
node _T_4220 = bits(_WIRE_311, 11, 11)
connect _WIRE_310.hw, _T_4220
node _T_4221 = bits(_WIRE_311, 12, 12)
connect _WIRE_310.sr, _T_4221
node _T_4222 = bits(_WIRE_311, 13, 13)
connect _WIRE_310.sx, _T_4222
node _T_4223 = bits(_WIRE_311, 14, 14)
connect _WIRE_310.sw, _T_4223
node _T_4224 = bits(_WIRE_311, 15, 15)
connect _WIRE_310.gf, _T_4224
node _T_4225 = bits(_WIRE_311, 16, 16)
connect _WIRE_310.pf, _T_4225
node _T_4226 = bits(_WIRE_311, 17, 17)
connect _WIRE_310.ae_stage2, _T_4226
node _T_4227 = bits(_WIRE_311, 18, 18)
connect _WIRE_310.ae_final, _T_4227
node _T_4228 = bits(_WIRE_311, 19, 19)
connect _WIRE_310.ae_ptw, _T_4228
node _T_4229 = bits(_WIRE_311, 20, 20)
connect _WIRE_310.g, _T_4229
node _T_4230 = bits(_WIRE_311, 21, 21)
connect _WIRE_310.u, _T_4230
node _T_4231 = bits(_WIRE_311, 41, 22)
connect _WIRE_310.ppn, _T_4231
wire _WIRE_312 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_313 : UInt<42>
connect _WIRE_313, sectored_entries[0][3].data[1]
node _T_4232 = bits(_WIRE_313, 0, 0)
connect _WIRE_312.fragmented_superpage, _T_4232
node _T_4233 = bits(_WIRE_313, 1, 1)
connect _WIRE_312.c, _T_4233
node _T_4234 = bits(_WIRE_313, 2, 2)
connect _WIRE_312.eff, _T_4234
node _T_4235 = bits(_WIRE_313, 3, 3)
connect _WIRE_312.paa, _T_4235
node _T_4236 = bits(_WIRE_313, 4, 4)
connect _WIRE_312.pal, _T_4236
node _T_4237 = bits(_WIRE_313, 5, 5)
connect _WIRE_312.ppp, _T_4237
node _T_4238 = bits(_WIRE_313, 6, 6)
connect _WIRE_312.pr, _T_4238
node _T_4239 = bits(_WIRE_313, 7, 7)
connect _WIRE_312.px, _T_4239
node _T_4240 = bits(_WIRE_313, 8, 8)
connect _WIRE_312.pw, _T_4240
node _T_4241 = bits(_WIRE_313, 9, 9)
connect _WIRE_312.hr, _T_4241
node _T_4242 = bits(_WIRE_313, 10, 10)
connect _WIRE_312.hx, _T_4242
node _T_4243 = bits(_WIRE_313, 11, 11)
connect _WIRE_312.hw, _T_4243
node _T_4244 = bits(_WIRE_313, 12, 12)
connect _WIRE_312.sr, _T_4244
node _T_4245 = bits(_WIRE_313, 13, 13)
connect _WIRE_312.sx, _T_4245
node _T_4246 = bits(_WIRE_313, 14, 14)
connect _WIRE_312.sw, _T_4246
node _T_4247 = bits(_WIRE_313, 15, 15)
connect _WIRE_312.gf, _T_4247
node _T_4248 = bits(_WIRE_313, 16, 16)
connect _WIRE_312.pf, _T_4248
node _T_4249 = bits(_WIRE_313, 17, 17)
connect _WIRE_312.ae_stage2, _T_4249
node _T_4250 = bits(_WIRE_313, 18, 18)
connect _WIRE_312.ae_final, _T_4250
node _T_4251 = bits(_WIRE_313, 19, 19)
connect _WIRE_312.ae_ptw, _T_4251
node _T_4252 = bits(_WIRE_313, 20, 20)
connect _WIRE_312.g, _T_4252
node _T_4253 = bits(_WIRE_313, 21, 21)
connect _WIRE_312.u, _T_4253
node _T_4254 = bits(_WIRE_313, 41, 22)
connect _WIRE_312.ppn, _T_4254
wire _WIRE_314 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_315 : UInt<42>
connect _WIRE_315, sectored_entries[0][3].data[2]
node _T_4255 = bits(_WIRE_315, 0, 0)
connect _WIRE_314.fragmented_superpage, _T_4255
node _T_4256 = bits(_WIRE_315, 1, 1)
connect _WIRE_314.c, _T_4256
node _T_4257 = bits(_WIRE_315, 2, 2)
connect _WIRE_314.eff, _T_4257
node _T_4258 = bits(_WIRE_315, 3, 3)
connect _WIRE_314.paa, _T_4258
node _T_4259 = bits(_WIRE_315, 4, 4)
connect _WIRE_314.pal, _T_4259
node _T_4260 = bits(_WIRE_315, 5, 5)
connect _WIRE_314.ppp, _T_4260
node _T_4261 = bits(_WIRE_315, 6, 6)
connect _WIRE_314.pr, _T_4261
node _T_4262 = bits(_WIRE_315, 7, 7)
connect _WIRE_314.px, _T_4262
node _T_4263 = bits(_WIRE_315, 8, 8)
connect _WIRE_314.pw, _T_4263
node _T_4264 = bits(_WIRE_315, 9, 9)
connect _WIRE_314.hr, _T_4264
node _T_4265 = bits(_WIRE_315, 10, 10)
connect _WIRE_314.hx, _T_4265
node _T_4266 = bits(_WIRE_315, 11, 11)
connect _WIRE_314.hw, _T_4266
node _T_4267 = bits(_WIRE_315, 12, 12)
connect _WIRE_314.sr, _T_4267
node _T_4268 = bits(_WIRE_315, 13, 13)
connect _WIRE_314.sx, _T_4268
node _T_4269 = bits(_WIRE_315, 14, 14)
connect _WIRE_314.sw, _T_4269
node _T_4270 = bits(_WIRE_315, 15, 15)
connect _WIRE_314.gf, _T_4270
node _T_4271 = bits(_WIRE_315, 16, 16)
connect _WIRE_314.pf, _T_4271
node _T_4272 = bits(_WIRE_315, 17, 17)
connect _WIRE_314.ae_stage2, _T_4272
node _T_4273 = bits(_WIRE_315, 18, 18)
connect _WIRE_314.ae_final, _T_4273
node _T_4274 = bits(_WIRE_315, 19, 19)
connect _WIRE_314.ae_ptw, _T_4274
node _T_4275 = bits(_WIRE_315, 20, 20)
connect _WIRE_314.g, _T_4275
node _T_4276 = bits(_WIRE_315, 21, 21)
connect _WIRE_314.u, _T_4276
node _T_4277 = bits(_WIRE_315, 41, 22)
connect _WIRE_314.ppn, _T_4277
wire _WIRE_316 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_317 : UInt<42>
connect _WIRE_317, sectored_entries[0][3].data[3]
node _T_4278 = bits(_WIRE_317, 0, 0)
connect _WIRE_316.fragmented_superpage, _T_4278
node _T_4279 = bits(_WIRE_317, 1, 1)
connect _WIRE_316.c, _T_4279
node _T_4280 = bits(_WIRE_317, 2, 2)
connect _WIRE_316.eff, _T_4280
node _T_4281 = bits(_WIRE_317, 3, 3)
connect _WIRE_316.paa, _T_4281
node _T_4282 = bits(_WIRE_317, 4, 4)
connect _WIRE_316.pal, _T_4282
node _T_4283 = bits(_WIRE_317, 5, 5)
connect _WIRE_316.ppp, _T_4283
node _T_4284 = bits(_WIRE_317, 6, 6)
connect _WIRE_316.pr, _T_4284
node _T_4285 = bits(_WIRE_317, 7, 7)
connect _WIRE_316.px, _T_4285
node _T_4286 = bits(_WIRE_317, 8, 8)
connect _WIRE_316.pw, _T_4286
node _T_4287 = bits(_WIRE_317, 9, 9)
connect _WIRE_316.hr, _T_4287
node _T_4288 = bits(_WIRE_317, 10, 10)
connect _WIRE_316.hx, _T_4288
node _T_4289 = bits(_WIRE_317, 11, 11)
connect _WIRE_316.hw, _T_4289
node _T_4290 = bits(_WIRE_317, 12, 12)
connect _WIRE_316.sr, _T_4290
node _T_4291 = bits(_WIRE_317, 13, 13)
connect _WIRE_316.sx, _T_4291
node _T_4292 = bits(_WIRE_317, 14, 14)
connect _WIRE_316.sw, _T_4292
node _T_4293 = bits(_WIRE_317, 15, 15)
connect _WIRE_316.gf, _T_4293
node _T_4294 = bits(_WIRE_317, 16, 16)
connect _WIRE_316.pf, _T_4294
node _T_4295 = bits(_WIRE_317, 17, 17)
connect _WIRE_316.ae_stage2, _T_4295
node _T_4296 = bits(_WIRE_317, 18, 18)
connect _WIRE_316.ae_final, _T_4296
node _T_4297 = bits(_WIRE_317, 19, 19)
connect _WIRE_316.ae_ptw, _T_4297
node _T_4298 = bits(_WIRE_317, 20, 20)
connect _WIRE_316.g, _T_4298
node _T_4299 = bits(_WIRE_317, 21, 21)
connect _WIRE_316.u, _T_4299
node _T_4300 = bits(_WIRE_317, 41, 22)
connect _WIRE_316.ppn, _T_4300
node _T_4301 = eq(sectored_entries[0][3].tag_v, UInt<1>(0h1))
when _T_4301 :
connect sectored_entries[0][3].valid[0], UInt<1>(0h0)
node _T_4302 = eq(sectored_entries[0][3].tag_v, UInt<1>(0h1))
when _T_4302 :
connect sectored_entries[0][3].valid[1], UInt<1>(0h0)
node _T_4303 = eq(sectored_entries[0][3].tag_v, UInt<1>(0h1))
when _T_4303 :
connect sectored_entries[0][3].valid[2], UInt<1>(0h0)
node _T_4304 = eq(sectored_entries[0][3].tag_v, UInt<1>(0h1))
when _T_4304 :
connect sectored_entries[0][3].valid[3], UInt<1>(0h0)
wire _WIRE_318 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_319 : UInt<42>
connect _WIRE_319, sectored_entries[0][4].data[0]
node _T_4305 = bits(_WIRE_319, 0, 0)
connect _WIRE_318.fragmented_superpage, _T_4305
node _T_4306 = bits(_WIRE_319, 1, 1)
connect _WIRE_318.c, _T_4306
node _T_4307 = bits(_WIRE_319, 2, 2)
connect _WIRE_318.eff, _T_4307
node _T_4308 = bits(_WIRE_319, 3, 3)
connect _WIRE_318.paa, _T_4308
node _T_4309 = bits(_WIRE_319, 4, 4)
connect _WIRE_318.pal, _T_4309
node _T_4310 = bits(_WIRE_319, 5, 5)
connect _WIRE_318.ppp, _T_4310
node _T_4311 = bits(_WIRE_319, 6, 6)
connect _WIRE_318.pr, _T_4311
node _T_4312 = bits(_WIRE_319, 7, 7)
connect _WIRE_318.px, _T_4312
node _T_4313 = bits(_WIRE_319, 8, 8)
connect _WIRE_318.pw, _T_4313
node _T_4314 = bits(_WIRE_319, 9, 9)
connect _WIRE_318.hr, _T_4314
node _T_4315 = bits(_WIRE_319, 10, 10)
connect _WIRE_318.hx, _T_4315
node _T_4316 = bits(_WIRE_319, 11, 11)
connect _WIRE_318.hw, _T_4316
node _T_4317 = bits(_WIRE_319, 12, 12)
connect _WIRE_318.sr, _T_4317
node _T_4318 = bits(_WIRE_319, 13, 13)
connect _WIRE_318.sx, _T_4318
node _T_4319 = bits(_WIRE_319, 14, 14)
connect _WIRE_318.sw, _T_4319
node _T_4320 = bits(_WIRE_319, 15, 15)
connect _WIRE_318.gf, _T_4320
node _T_4321 = bits(_WIRE_319, 16, 16)
connect _WIRE_318.pf, _T_4321
node _T_4322 = bits(_WIRE_319, 17, 17)
connect _WIRE_318.ae_stage2, _T_4322
node _T_4323 = bits(_WIRE_319, 18, 18)
connect _WIRE_318.ae_final, _T_4323
node _T_4324 = bits(_WIRE_319, 19, 19)
connect _WIRE_318.ae_ptw, _T_4324
node _T_4325 = bits(_WIRE_319, 20, 20)
connect _WIRE_318.g, _T_4325
node _T_4326 = bits(_WIRE_319, 21, 21)
connect _WIRE_318.u, _T_4326
node _T_4327 = bits(_WIRE_319, 41, 22)
connect _WIRE_318.ppn, _T_4327
wire _WIRE_320 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_321 : UInt<42>
connect _WIRE_321, sectored_entries[0][4].data[1]
node _T_4328 = bits(_WIRE_321, 0, 0)
connect _WIRE_320.fragmented_superpage, _T_4328
node _T_4329 = bits(_WIRE_321, 1, 1)
connect _WIRE_320.c, _T_4329
node _T_4330 = bits(_WIRE_321, 2, 2)
connect _WIRE_320.eff, _T_4330
node _T_4331 = bits(_WIRE_321, 3, 3)
connect _WIRE_320.paa, _T_4331
node _T_4332 = bits(_WIRE_321, 4, 4)
connect _WIRE_320.pal, _T_4332
node _T_4333 = bits(_WIRE_321, 5, 5)
connect _WIRE_320.ppp, _T_4333
node _T_4334 = bits(_WIRE_321, 6, 6)
connect _WIRE_320.pr, _T_4334
node _T_4335 = bits(_WIRE_321, 7, 7)
connect _WIRE_320.px, _T_4335
node _T_4336 = bits(_WIRE_321, 8, 8)
connect _WIRE_320.pw, _T_4336
node _T_4337 = bits(_WIRE_321, 9, 9)
connect _WIRE_320.hr, _T_4337
node _T_4338 = bits(_WIRE_321, 10, 10)
connect _WIRE_320.hx, _T_4338
node _T_4339 = bits(_WIRE_321, 11, 11)
connect _WIRE_320.hw, _T_4339
node _T_4340 = bits(_WIRE_321, 12, 12)
connect _WIRE_320.sr, _T_4340
node _T_4341 = bits(_WIRE_321, 13, 13)
connect _WIRE_320.sx, _T_4341
node _T_4342 = bits(_WIRE_321, 14, 14)
connect _WIRE_320.sw, _T_4342
node _T_4343 = bits(_WIRE_321, 15, 15)
connect _WIRE_320.gf, _T_4343
node _T_4344 = bits(_WIRE_321, 16, 16)
connect _WIRE_320.pf, _T_4344
node _T_4345 = bits(_WIRE_321, 17, 17)
connect _WIRE_320.ae_stage2, _T_4345
node _T_4346 = bits(_WIRE_321, 18, 18)
connect _WIRE_320.ae_final, _T_4346
node _T_4347 = bits(_WIRE_321, 19, 19)
connect _WIRE_320.ae_ptw, _T_4347
node _T_4348 = bits(_WIRE_321, 20, 20)
connect _WIRE_320.g, _T_4348
node _T_4349 = bits(_WIRE_321, 21, 21)
connect _WIRE_320.u, _T_4349
node _T_4350 = bits(_WIRE_321, 41, 22)
connect _WIRE_320.ppn, _T_4350
wire _WIRE_322 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_323 : UInt<42>
connect _WIRE_323, sectored_entries[0][4].data[2]
node _T_4351 = bits(_WIRE_323, 0, 0)
connect _WIRE_322.fragmented_superpage, _T_4351
node _T_4352 = bits(_WIRE_323, 1, 1)
connect _WIRE_322.c, _T_4352
node _T_4353 = bits(_WIRE_323, 2, 2)
connect _WIRE_322.eff, _T_4353
node _T_4354 = bits(_WIRE_323, 3, 3)
connect _WIRE_322.paa, _T_4354
node _T_4355 = bits(_WIRE_323, 4, 4)
connect _WIRE_322.pal, _T_4355
node _T_4356 = bits(_WIRE_323, 5, 5)
connect _WIRE_322.ppp, _T_4356
node _T_4357 = bits(_WIRE_323, 6, 6)
connect _WIRE_322.pr, _T_4357
node _T_4358 = bits(_WIRE_323, 7, 7)
connect _WIRE_322.px, _T_4358
node _T_4359 = bits(_WIRE_323, 8, 8)
connect _WIRE_322.pw, _T_4359
node _T_4360 = bits(_WIRE_323, 9, 9)
connect _WIRE_322.hr, _T_4360
node _T_4361 = bits(_WIRE_323, 10, 10)
connect _WIRE_322.hx, _T_4361
node _T_4362 = bits(_WIRE_323, 11, 11)
connect _WIRE_322.hw, _T_4362
node _T_4363 = bits(_WIRE_323, 12, 12)
connect _WIRE_322.sr, _T_4363
node _T_4364 = bits(_WIRE_323, 13, 13)
connect _WIRE_322.sx, _T_4364
node _T_4365 = bits(_WIRE_323, 14, 14)
connect _WIRE_322.sw, _T_4365
node _T_4366 = bits(_WIRE_323, 15, 15)
connect _WIRE_322.gf, _T_4366
node _T_4367 = bits(_WIRE_323, 16, 16)
connect _WIRE_322.pf, _T_4367
node _T_4368 = bits(_WIRE_323, 17, 17)
connect _WIRE_322.ae_stage2, _T_4368
node _T_4369 = bits(_WIRE_323, 18, 18)
connect _WIRE_322.ae_final, _T_4369
node _T_4370 = bits(_WIRE_323, 19, 19)
connect _WIRE_322.ae_ptw, _T_4370
node _T_4371 = bits(_WIRE_323, 20, 20)
connect _WIRE_322.g, _T_4371
node _T_4372 = bits(_WIRE_323, 21, 21)
connect _WIRE_322.u, _T_4372
node _T_4373 = bits(_WIRE_323, 41, 22)
connect _WIRE_322.ppn, _T_4373
wire _WIRE_324 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_325 : UInt<42>
connect _WIRE_325, sectored_entries[0][4].data[3]
node _T_4374 = bits(_WIRE_325, 0, 0)
connect _WIRE_324.fragmented_superpage, _T_4374
node _T_4375 = bits(_WIRE_325, 1, 1)
connect _WIRE_324.c, _T_4375
node _T_4376 = bits(_WIRE_325, 2, 2)
connect _WIRE_324.eff, _T_4376
node _T_4377 = bits(_WIRE_325, 3, 3)
connect _WIRE_324.paa, _T_4377
node _T_4378 = bits(_WIRE_325, 4, 4)
connect _WIRE_324.pal, _T_4378
node _T_4379 = bits(_WIRE_325, 5, 5)
connect _WIRE_324.ppp, _T_4379
node _T_4380 = bits(_WIRE_325, 6, 6)
connect _WIRE_324.pr, _T_4380
node _T_4381 = bits(_WIRE_325, 7, 7)
connect _WIRE_324.px, _T_4381
node _T_4382 = bits(_WIRE_325, 8, 8)
connect _WIRE_324.pw, _T_4382
node _T_4383 = bits(_WIRE_325, 9, 9)
connect _WIRE_324.hr, _T_4383
node _T_4384 = bits(_WIRE_325, 10, 10)
connect _WIRE_324.hx, _T_4384
node _T_4385 = bits(_WIRE_325, 11, 11)
connect _WIRE_324.hw, _T_4385
node _T_4386 = bits(_WIRE_325, 12, 12)
connect _WIRE_324.sr, _T_4386
node _T_4387 = bits(_WIRE_325, 13, 13)
connect _WIRE_324.sx, _T_4387
node _T_4388 = bits(_WIRE_325, 14, 14)
connect _WIRE_324.sw, _T_4388
node _T_4389 = bits(_WIRE_325, 15, 15)
connect _WIRE_324.gf, _T_4389
node _T_4390 = bits(_WIRE_325, 16, 16)
connect _WIRE_324.pf, _T_4390
node _T_4391 = bits(_WIRE_325, 17, 17)
connect _WIRE_324.ae_stage2, _T_4391
node _T_4392 = bits(_WIRE_325, 18, 18)
connect _WIRE_324.ae_final, _T_4392
node _T_4393 = bits(_WIRE_325, 19, 19)
connect _WIRE_324.ae_ptw, _T_4393
node _T_4394 = bits(_WIRE_325, 20, 20)
connect _WIRE_324.g, _T_4394
node _T_4395 = bits(_WIRE_325, 21, 21)
connect _WIRE_324.u, _T_4395
node _T_4396 = bits(_WIRE_325, 41, 22)
connect _WIRE_324.ppn, _T_4396
node _T_4397 = eq(sectored_entries[0][4].tag_v, UInt<1>(0h1))
when _T_4397 :
connect sectored_entries[0][4].valid[0], UInt<1>(0h0)
node _T_4398 = eq(sectored_entries[0][4].tag_v, UInt<1>(0h1))
when _T_4398 :
connect sectored_entries[0][4].valid[1], UInt<1>(0h0)
node _T_4399 = eq(sectored_entries[0][4].tag_v, UInt<1>(0h1))
when _T_4399 :
connect sectored_entries[0][4].valid[2], UInt<1>(0h0)
node _T_4400 = eq(sectored_entries[0][4].tag_v, UInt<1>(0h1))
when _T_4400 :
connect sectored_entries[0][4].valid[3], UInt<1>(0h0)
wire _WIRE_326 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_327 : UInt<42>
connect _WIRE_327, sectored_entries[0][5].data[0]
node _T_4401 = bits(_WIRE_327, 0, 0)
connect _WIRE_326.fragmented_superpage, _T_4401
node _T_4402 = bits(_WIRE_327, 1, 1)
connect _WIRE_326.c, _T_4402
node _T_4403 = bits(_WIRE_327, 2, 2)
connect _WIRE_326.eff, _T_4403
node _T_4404 = bits(_WIRE_327, 3, 3)
connect _WIRE_326.paa, _T_4404
node _T_4405 = bits(_WIRE_327, 4, 4)
connect _WIRE_326.pal, _T_4405
node _T_4406 = bits(_WIRE_327, 5, 5)
connect _WIRE_326.ppp, _T_4406
node _T_4407 = bits(_WIRE_327, 6, 6)
connect _WIRE_326.pr, _T_4407
node _T_4408 = bits(_WIRE_327, 7, 7)
connect _WIRE_326.px, _T_4408
node _T_4409 = bits(_WIRE_327, 8, 8)
connect _WIRE_326.pw, _T_4409
node _T_4410 = bits(_WIRE_327, 9, 9)
connect _WIRE_326.hr, _T_4410
node _T_4411 = bits(_WIRE_327, 10, 10)
connect _WIRE_326.hx, _T_4411
node _T_4412 = bits(_WIRE_327, 11, 11)
connect _WIRE_326.hw, _T_4412
node _T_4413 = bits(_WIRE_327, 12, 12)
connect _WIRE_326.sr, _T_4413
node _T_4414 = bits(_WIRE_327, 13, 13)
connect _WIRE_326.sx, _T_4414
node _T_4415 = bits(_WIRE_327, 14, 14)
connect _WIRE_326.sw, _T_4415
node _T_4416 = bits(_WIRE_327, 15, 15)
connect _WIRE_326.gf, _T_4416
node _T_4417 = bits(_WIRE_327, 16, 16)
connect _WIRE_326.pf, _T_4417
node _T_4418 = bits(_WIRE_327, 17, 17)
connect _WIRE_326.ae_stage2, _T_4418
node _T_4419 = bits(_WIRE_327, 18, 18)
connect _WIRE_326.ae_final, _T_4419
node _T_4420 = bits(_WIRE_327, 19, 19)
connect _WIRE_326.ae_ptw, _T_4420
node _T_4421 = bits(_WIRE_327, 20, 20)
connect _WIRE_326.g, _T_4421
node _T_4422 = bits(_WIRE_327, 21, 21)
connect _WIRE_326.u, _T_4422
node _T_4423 = bits(_WIRE_327, 41, 22)
connect _WIRE_326.ppn, _T_4423
wire _WIRE_328 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_329 : UInt<42>
connect _WIRE_329, sectored_entries[0][5].data[1]
node _T_4424 = bits(_WIRE_329, 0, 0)
connect _WIRE_328.fragmented_superpage, _T_4424
node _T_4425 = bits(_WIRE_329, 1, 1)
connect _WIRE_328.c, _T_4425
node _T_4426 = bits(_WIRE_329, 2, 2)
connect _WIRE_328.eff, _T_4426
node _T_4427 = bits(_WIRE_329, 3, 3)
connect _WIRE_328.paa, _T_4427
node _T_4428 = bits(_WIRE_329, 4, 4)
connect _WIRE_328.pal, _T_4428
node _T_4429 = bits(_WIRE_329, 5, 5)
connect _WIRE_328.ppp, _T_4429
node _T_4430 = bits(_WIRE_329, 6, 6)
connect _WIRE_328.pr, _T_4430
node _T_4431 = bits(_WIRE_329, 7, 7)
connect _WIRE_328.px, _T_4431
node _T_4432 = bits(_WIRE_329, 8, 8)
connect _WIRE_328.pw, _T_4432
node _T_4433 = bits(_WIRE_329, 9, 9)
connect _WIRE_328.hr, _T_4433
node _T_4434 = bits(_WIRE_329, 10, 10)
connect _WIRE_328.hx, _T_4434
node _T_4435 = bits(_WIRE_329, 11, 11)
connect _WIRE_328.hw, _T_4435
node _T_4436 = bits(_WIRE_329, 12, 12)
connect _WIRE_328.sr, _T_4436
node _T_4437 = bits(_WIRE_329, 13, 13)
connect _WIRE_328.sx, _T_4437
node _T_4438 = bits(_WIRE_329, 14, 14)
connect _WIRE_328.sw, _T_4438
node _T_4439 = bits(_WIRE_329, 15, 15)
connect _WIRE_328.gf, _T_4439
node _T_4440 = bits(_WIRE_329, 16, 16)
connect _WIRE_328.pf, _T_4440
node _T_4441 = bits(_WIRE_329, 17, 17)
connect _WIRE_328.ae_stage2, _T_4441
node _T_4442 = bits(_WIRE_329, 18, 18)
connect _WIRE_328.ae_final, _T_4442
node _T_4443 = bits(_WIRE_329, 19, 19)
connect _WIRE_328.ae_ptw, _T_4443
node _T_4444 = bits(_WIRE_329, 20, 20)
connect _WIRE_328.g, _T_4444
node _T_4445 = bits(_WIRE_329, 21, 21)
connect _WIRE_328.u, _T_4445
node _T_4446 = bits(_WIRE_329, 41, 22)
connect _WIRE_328.ppn, _T_4446
wire _WIRE_330 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_331 : UInt<42>
connect _WIRE_331, sectored_entries[0][5].data[2]
node _T_4447 = bits(_WIRE_331, 0, 0)
connect _WIRE_330.fragmented_superpage, _T_4447
node _T_4448 = bits(_WIRE_331, 1, 1)
connect _WIRE_330.c, _T_4448
node _T_4449 = bits(_WIRE_331, 2, 2)
connect _WIRE_330.eff, _T_4449
node _T_4450 = bits(_WIRE_331, 3, 3)
connect _WIRE_330.paa, _T_4450
node _T_4451 = bits(_WIRE_331, 4, 4)
connect _WIRE_330.pal, _T_4451
node _T_4452 = bits(_WIRE_331, 5, 5)
connect _WIRE_330.ppp, _T_4452
node _T_4453 = bits(_WIRE_331, 6, 6)
connect _WIRE_330.pr, _T_4453
node _T_4454 = bits(_WIRE_331, 7, 7)
connect _WIRE_330.px, _T_4454
node _T_4455 = bits(_WIRE_331, 8, 8)
connect _WIRE_330.pw, _T_4455
node _T_4456 = bits(_WIRE_331, 9, 9)
connect _WIRE_330.hr, _T_4456
node _T_4457 = bits(_WIRE_331, 10, 10)
connect _WIRE_330.hx, _T_4457
node _T_4458 = bits(_WIRE_331, 11, 11)
connect _WIRE_330.hw, _T_4458
node _T_4459 = bits(_WIRE_331, 12, 12)
connect _WIRE_330.sr, _T_4459
node _T_4460 = bits(_WIRE_331, 13, 13)
connect _WIRE_330.sx, _T_4460
node _T_4461 = bits(_WIRE_331, 14, 14)
connect _WIRE_330.sw, _T_4461
node _T_4462 = bits(_WIRE_331, 15, 15)
connect _WIRE_330.gf, _T_4462
node _T_4463 = bits(_WIRE_331, 16, 16)
connect _WIRE_330.pf, _T_4463
node _T_4464 = bits(_WIRE_331, 17, 17)
connect _WIRE_330.ae_stage2, _T_4464
node _T_4465 = bits(_WIRE_331, 18, 18)
connect _WIRE_330.ae_final, _T_4465
node _T_4466 = bits(_WIRE_331, 19, 19)
connect _WIRE_330.ae_ptw, _T_4466
node _T_4467 = bits(_WIRE_331, 20, 20)
connect _WIRE_330.g, _T_4467
node _T_4468 = bits(_WIRE_331, 21, 21)
connect _WIRE_330.u, _T_4468
node _T_4469 = bits(_WIRE_331, 41, 22)
connect _WIRE_330.ppn, _T_4469
wire _WIRE_332 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_333 : UInt<42>
connect _WIRE_333, sectored_entries[0][5].data[3]
node _T_4470 = bits(_WIRE_333, 0, 0)
connect _WIRE_332.fragmented_superpage, _T_4470
node _T_4471 = bits(_WIRE_333, 1, 1)
connect _WIRE_332.c, _T_4471
node _T_4472 = bits(_WIRE_333, 2, 2)
connect _WIRE_332.eff, _T_4472
node _T_4473 = bits(_WIRE_333, 3, 3)
connect _WIRE_332.paa, _T_4473
node _T_4474 = bits(_WIRE_333, 4, 4)
connect _WIRE_332.pal, _T_4474
node _T_4475 = bits(_WIRE_333, 5, 5)
connect _WIRE_332.ppp, _T_4475
node _T_4476 = bits(_WIRE_333, 6, 6)
connect _WIRE_332.pr, _T_4476
node _T_4477 = bits(_WIRE_333, 7, 7)
connect _WIRE_332.px, _T_4477
node _T_4478 = bits(_WIRE_333, 8, 8)
connect _WIRE_332.pw, _T_4478
node _T_4479 = bits(_WIRE_333, 9, 9)
connect _WIRE_332.hr, _T_4479
node _T_4480 = bits(_WIRE_333, 10, 10)
connect _WIRE_332.hx, _T_4480
node _T_4481 = bits(_WIRE_333, 11, 11)
connect _WIRE_332.hw, _T_4481
node _T_4482 = bits(_WIRE_333, 12, 12)
connect _WIRE_332.sr, _T_4482
node _T_4483 = bits(_WIRE_333, 13, 13)
connect _WIRE_332.sx, _T_4483
node _T_4484 = bits(_WIRE_333, 14, 14)
connect _WIRE_332.sw, _T_4484
node _T_4485 = bits(_WIRE_333, 15, 15)
connect _WIRE_332.gf, _T_4485
node _T_4486 = bits(_WIRE_333, 16, 16)
connect _WIRE_332.pf, _T_4486
node _T_4487 = bits(_WIRE_333, 17, 17)
connect _WIRE_332.ae_stage2, _T_4487
node _T_4488 = bits(_WIRE_333, 18, 18)
connect _WIRE_332.ae_final, _T_4488
node _T_4489 = bits(_WIRE_333, 19, 19)
connect _WIRE_332.ae_ptw, _T_4489
node _T_4490 = bits(_WIRE_333, 20, 20)
connect _WIRE_332.g, _T_4490
node _T_4491 = bits(_WIRE_333, 21, 21)
connect _WIRE_332.u, _T_4491
node _T_4492 = bits(_WIRE_333, 41, 22)
connect _WIRE_332.ppn, _T_4492
node _T_4493 = eq(sectored_entries[0][5].tag_v, UInt<1>(0h1))
when _T_4493 :
connect sectored_entries[0][5].valid[0], UInt<1>(0h0)
node _T_4494 = eq(sectored_entries[0][5].tag_v, UInt<1>(0h1))
when _T_4494 :
connect sectored_entries[0][5].valid[1], UInt<1>(0h0)
node _T_4495 = eq(sectored_entries[0][5].tag_v, UInt<1>(0h1))
when _T_4495 :
connect sectored_entries[0][5].valid[2], UInt<1>(0h0)
node _T_4496 = eq(sectored_entries[0][5].tag_v, UInt<1>(0h1))
when _T_4496 :
connect sectored_entries[0][5].valid[3], UInt<1>(0h0)
wire _WIRE_334 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_335 : UInt<42>
connect _WIRE_335, sectored_entries[0][6].data[0]
node _T_4497 = bits(_WIRE_335, 0, 0)
connect _WIRE_334.fragmented_superpage, _T_4497
node _T_4498 = bits(_WIRE_335, 1, 1)
connect _WIRE_334.c, _T_4498
node _T_4499 = bits(_WIRE_335, 2, 2)
connect _WIRE_334.eff, _T_4499
node _T_4500 = bits(_WIRE_335, 3, 3)
connect _WIRE_334.paa, _T_4500
node _T_4501 = bits(_WIRE_335, 4, 4)
connect _WIRE_334.pal, _T_4501
node _T_4502 = bits(_WIRE_335, 5, 5)
connect _WIRE_334.ppp, _T_4502
node _T_4503 = bits(_WIRE_335, 6, 6)
connect _WIRE_334.pr, _T_4503
node _T_4504 = bits(_WIRE_335, 7, 7)
connect _WIRE_334.px, _T_4504
node _T_4505 = bits(_WIRE_335, 8, 8)
connect _WIRE_334.pw, _T_4505
node _T_4506 = bits(_WIRE_335, 9, 9)
connect _WIRE_334.hr, _T_4506
node _T_4507 = bits(_WIRE_335, 10, 10)
connect _WIRE_334.hx, _T_4507
node _T_4508 = bits(_WIRE_335, 11, 11)
connect _WIRE_334.hw, _T_4508
node _T_4509 = bits(_WIRE_335, 12, 12)
connect _WIRE_334.sr, _T_4509
node _T_4510 = bits(_WIRE_335, 13, 13)
connect _WIRE_334.sx, _T_4510
node _T_4511 = bits(_WIRE_335, 14, 14)
connect _WIRE_334.sw, _T_4511
node _T_4512 = bits(_WIRE_335, 15, 15)
connect _WIRE_334.gf, _T_4512
node _T_4513 = bits(_WIRE_335, 16, 16)
connect _WIRE_334.pf, _T_4513
node _T_4514 = bits(_WIRE_335, 17, 17)
connect _WIRE_334.ae_stage2, _T_4514
node _T_4515 = bits(_WIRE_335, 18, 18)
connect _WIRE_334.ae_final, _T_4515
node _T_4516 = bits(_WIRE_335, 19, 19)
connect _WIRE_334.ae_ptw, _T_4516
node _T_4517 = bits(_WIRE_335, 20, 20)
connect _WIRE_334.g, _T_4517
node _T_4518 = bits(_WIRE_335, 21, 21)
connect _WIRE_334.u, _T_4518
node _T_4519 = bits(_WIRE_335, 41, 22)
connect _WIRE_334.ppn, _T_4519
wire _WIRE_336 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_337 : UInt<42>
connect _WIRE_337, sectored_entries[0][6].data[1]
node _T_4520 = bits(_WIRE_337, 0, 0)
connect _WIRE_336.fragmented_superpage, _T_4520
node _T_4521 = bits(_WIRE_337, 1, 1)
connect _WIRE_336.c, _T_4521
node _T_4522 = bits(_WIRE_337, 2, 2)
connect _WIRE_336.eff, _T_4522
node _T_4523 = bits(_WIRE_337, 3, 3)
connect _WIRE_336.paa, _T_4523
node _T_4524 = bits(_WIRE_337, 4, 4)
connect _WIRE_336.pal, _T_4524
node _T_4525 = bits(_WIRE_337, 5, 5)
connect _WIRE_336.ppp, _T_4525
node _T_4526 = bits(_WIRE_337, 6, 6)
connect _WIRE_336.pr, _T_4526
node _T_4527 = bits(_WIRE_337, 7, 7)
connect _WIRE_336.px, _T_4527
node _T_4528 = bits(_WIRE_337, 8, 8)
connect _WIRE_336.pw, _T_4528
node _T_4529 = bits(_WIRE_337, 9, 9)
connect _WIRE_336.hr, _T_4529
node _T_4530 = bits(_WIRE_337, 10, 10)
connect _WIRE_336.hx, _T_4530
node _T_4531 = bits(_WIRE_337, 11, 11)
connect _WIRE_336.hw, _T_4531
node _T_4532 = bits(_WIRE_337, 12, 12)
connect _WIRE_336.sr, _T_4532
node _T_4533 = bits(_WIRE_337, 13, 13)
connect _WIRE_336.sx, _T_4533
node _T_4534 = bits(_WIRE_337, 14, 14)
connect _WIRE_336.sw, _T_4534
node _T_4535 = bits(_WIRE_337, 15, 15)
connect _WIRE_336.gf, _T_4535
node _T_4536 = bits(_WIRE_337, 16, 16)
connect _WIRE_336.pf, _T_4536
node _T_4537 = bits(_WIRE_337, 17, 17)
connect _WIRE_336.ae_stage2, _T_4537
node _T_4538 = bits(_WIRE_337, 18, 18)
connect _WIRE_336.ae_final, _T_4538
node _T_4539 = bits(_WIRE_337, 19, 19)
connect _WIRE_336.ae_ptw, _T_4539
node _T_4540 = bits(_WIRE_337, 20, 20)
connect _WIRE_336.g, _T_4540
node _T_4541 = bits(_WIRE_337, 21, 21)
connect _WIRE_336.u, _T_4541
node _T_4542 = bits(_WIRE_337, 41, 22)
connect _WIRE_336.ppn, _T_4542
wire _WIRE_338 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_339 : UInt<42>
connect _WIRE_339, sectored_entries[0][6].data[2]
node _T_4543 = bits(_WIRE_339, 0, 0)
connect _WIRE_338.fragmented_superpage, _T_4543
node _T_4544 = bits(_WIRE_339, 1, 1)
connect _WIRE_338.c, _T_4544
node _T_4545 = bits(_WIRE_339, 2, 2)
connect _WIRE_338.eff, _T_4545
node _T_4546 = bits(_WIRE_339, 3, 3)
connect _WIRE_338.paa, _T_4546
node _T_4547 = bits(_WIRE_339, 4, 4)
connect _WIRE_338.pal, _T_4547
node _T_4548 = bits(_WIRE_339, 5, 5)
connect _WIRE_338.ppp, _T_4548
node _T_4549 = bits(_WIRE_339, 6, 6)
connect _WIRE_338.pr, _T_4549
node _T_4550 = bits(_WIRE_339, 7, 7)
connect _WIRE_338.px, _T_4550
node _T_4551 = bits(_WIRE_339, 8, 8)
connect _WIRE_338.pw, _T_4551
node _T_4552 = bits(_WIRE_339, 9, 9)
connect _WIRE_338.hr, _T_4552
node _T_4553 = bits(_WIRE_339, 10, 10)
connect _WIRE_338.hx, _T_4553
node _T_4554 = bits(_WIRE_339, 11, 11)
connect _WIRE_338.hw, _T_4554
node _T_4555 = bits(_WIRE_339, 12, 12)
connect _WIRE_338.sr, _T_4555
node _T_4556 = bits(_WIRE_339, 13, 13)
connect _WIRE_338.sx, _T_4556
node _T_4557 = bits(_WIRE_339, 14, 14)
connect _WIRE_338.sw, _T_4557
node _T_4558 = bits(_WIRE_339, 15, 15)
connect _WIRE_338.gf, _T_4558
node _T_4559 = bits(_WIRE_339, 16, 16)
connect _WIRE_338.pf, _T_4559
node _T_4560 = bits(_WIRE_339, 17, 17)
connect _WIRE_338.ae_stage2, _T_4560
node _T_4561 = bits(_WIRE_339, 18, 18)
connect _WIRE_338.ae_final, _T_4561
node _T_4562 = bits(_WIRE_339, 19, 19)
connect _WIRE_338.ae_ptw, _T_4562
node _T_4563 = bits(_WIRE_339, 20, 20)
connect _WIRE_338.g, _T_4563
node _T_4564 = bits(_WIRE_339, 21, 21)
connect _WIRE_338.u, _T_4564
node _T_4565 = bits(_WIRE_339, 41, 22)
connect _WIRE_338.ppn, _T_4565
wire _WIRE_340 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_341 : UInt<42>
connect _WIRE_341, sectored_entries[0][6].data[3]
node _T_4566 = bits(_WIRE_341, 0, 0)
connect _WIRE_340.fragmented_superpage, _T_4566
node _T_4567 = bits(_WIRE_341, 1, 1)
connect _WIRE_340.c, _T_4567
node _T_4568 = bits(_WIRE_341, 2, 2)
connect _WIRE_340.eff, _T_4568
node _T_4569 = bits(_WIRE_341, 3, 3)
connect _WIRE_340.paa, _T_4569
node _T_4570 = bits(_WIRE_341, 4, 4)
connect _WIRE_340.pal, _T_4570
node _T_4571 = bits(_WIRE_341, 5, 5)
connect _WIRE_340.ppp, _T_4571
node _T_4572 = bits(_WIRE_341, 6, 6)
connect _WIRE_340.pr, _T_4572
node _T_4573 = bits(_WIRE_341, 7, 7)
connect _WIRE_340.px, _T_4573
node _T_4574 = bits(_WIRE_341, 8, 8)
connect _WIRE_340.pw, _T_4574
node _T_4575 = bits(_WIRE_341, 9, 9)
connect _WIRE_340.hr, _T_4575
node _T_4576 = bits(_WIRE_341, 10, 10)
connect _WIRE_340.hx, _T_4576
node _T_4577 = bits(_WIRE_341, 11, 11)
connect _WIRE_340.hw, _T_4577
node _T_4578 = bits(_WIRE_341, 12, 12)
connect _WIRE_340.sr, _T_4578
node _T_4579 = bits(_WIRE_341, 13, 13)
connect _WIRE_340.sx, _T_4579
node _T_4580 = bits(_WIRE_341, 14, 14)
connect _WIRE_340.sw, _T_4580
node _T_4581 = bits(_WIRE_341, 15, 15)
connect _WIRE_340.gf, _T_4581
node _T_4582 = bits(_WIRE_341, 16, 16)
connect _WIRE_340.pf, _T_4582
node _T_4583 = bits(_WIRE_341, 17, 17)
connect _WIRE_340.ae_stage2, _T_4583
node _T_4584 = bits(_WIRE_341, 18, 18)
connect _WIRE_340.ae_final, _T_4584
node _T_4585 = bits(_WIRE_341, 19, 19)
connect _WIRE_340.ae_ptw, _T_4585
node _T_4586 = bits(_WIRE_341, 20, 20)
connect _WIRE_340.g, _T_4586
node _T_4587 = bits(_WIRE_341, 21, 21)
connect _WIRE_340.u, _T_4587
node _T_4588 = bits(_WIRE_341, 41, 22)
connect _WIRE_340.ppn, _T_4588
node _T_4589 = eq(sectored_entries[0][6].tag_v, UInt<1>(0h1))
when _T_4589 :
connect sectored_entries[0][6].valid[0], UInt<1>(0h0)
node _T_4590 = eq(sectored_entries[0][6].tag_v, UInt<1>(0h1))
when _T_4590 :
connect sectored_entries[0][6].valid[1], UInt<1>(0h0)
node _T_4591 = eq(sectored_entries[0][6].tag_v, UInt<1>(0h1))
when _T_4591 :
connect sectored_entries[0][6].valid[2], UInt<1>(0h0)
node _T_4592 = eq(sectored_entries[0][6].tag_v, UInt<1>(0h1))
when _T_4592 :
connect sectored_entries[0][6].valid[3], UInt<1>(0h0)
wire _WIRE_342 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_343 : UInt<42>
connect _WIRE_343, sectored_entries[0][7].data[0]
node _T_4593 = bits(_WIRE_343, 0, 0)
connect _WIRE_342.fragmented_superpage, _T_4593
node _T_4594 = bits(_WIRE_343, 1, 1)
connect _WIRE_342.c, _T_4594
node _T_4595 = bits(_WIRE_343, 2, 2)
connect _WIRE_342.eff, _T_4595
node _T_4596 = bits(_WIRE_343, 3, 3)
connect _WIRE_342.paa, _T_4596
node _T_4597 = bits(_WIRE_343, 4, 4)
connect _WIRE_342.pal, _T_4597
node _T_4598 = bits(_WIRE_343, 5, 5)
connect _WIRE_342.ppp, _T_4598
node _T_4599 = bits(_WIRE_343, 6, 6)
connect _WIRE_342.pr, _T_4599
node _T_4600 = bits(_WIRE_343, 7, 7)
connect _WIRE_342.px, _T_4600
node _T_4601 = bits(_WIRE_343, 8, 8)
connect _WIRE_342.pw, _T_4601
node _T_4602 = bits(_WIRE_343, 9, 9)
connect _WIRE_342.hr, _T_4602
node _T_4603 = bits(_WIRE_343, 10, 10)
connect _WIRE_342.hx, _T_4603
node _T_4604 = bits(_WIRE_343, 11, 11)
connect _WIRE_342.hw, _T_4604
node _T_4605 = bits(_WIRE_343, 12, 12)
connect _WIRE_342.sr, _T_4605
node _T_4606 = bits(_WIRE_343, 13, 13)
connect _WIRE_342.sx, _T_4606
node _T_4607 = bits(_WIRE_343, 14, 14)
connect _WIRE_342.sw, _T_4607
node _T_4608 = bits(_WIRE_343, 15, 15)
connect _WIRE_342.gf, _T_4608
node _T_4609 = bits(_WIRE_343, 16, 16)
connect _WIRE_342.pf, _T_4609
node _T_4610 = bits(_WIRE_343, 17, 17)
connect _WIRE_342.ae_stage2, _T_4610
node _T_4611 = bits(_WIRE_343, 18, 18)
connect _WIRE_342.ae_final, _T_4611
node _T_4612 = bits(_WIRE_343, 19, 19)
connect _WIRE_342.ae_ptw, _T_4612
node _T_4613 = bits(_WIRE_343, 20, 20)
connect _WIRE_342.g, _T_4613
node _T_4614 = bits(_WIRE_343, 21, 21)
connect _WIRE_342.u, _T_4614
node _T_4615 = bits(_WIRE_343, 41, 22)
connect _WIRE_342.ppn, _T_4615
wire _WIRE_344 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_345 : UInt<42>
connect _WIRE_345, sectored_entries[0][7].data[1]
node _T_4616 = bits(_WIRE_345, 0, 0)
connect _WIRE_344.fragmented_superpage, _T_4616
node _T_4617 = bits(_WIRE_345, 1, 1)
connect _WIRE_344.c, _T_4617
node _T_4618 = bits(_WIRE_345, 2, 2)
connect _WIRE_344.eff, _T_4618
node _T_4619 = bits(_WIRE_345, 3, 3)
connect _WIRE_344.paa, _T_4619
node _T_4620 = bits(_WIRE_345, 4, 4)
connect _WIRE_344.pal, _T_4620
node _T_4621 = bits(_WIRE_345, 5, 5)
connect _WIRE_344.ppp, _T_4621
node _T_4622 = bits(_WIRE_345, 6, 6)
connect _WIRE_344.pr, _T_4622
node _T_4623 = bits(_WIRE_345, 7, 7)
connect _WIRE_344.px, _T_4623
node _T_4624 = bits(_WIRE_345, 8, 8)
connect _WIRE_344.pw, _T_4624
node _T_4625 = bits(_WIRE_345, 9, 9)
connect _WIRE_344.hr, _T_4625
node _T_4626 = bits(_WIRE_345, 10, 10)
connect _WIRE_344.hx, _T_4626
node _T_4627 = bits(_WIRE_345, 11, 11)
connect _WIRE_344.hw, _T_4627
node _T_4628 = bits(_WIRE_345, 12, 12)
connect _WIRE_344.sr, _T_4628
node _T_4629 = bits(_WIRE_345, 13, 13)
connect _WIRE_344.sx, _T_4629
node _T_4630 = bits(_WIRE_345, 14, 14)
connect _WIRE_344.sw, _T_4630
node _T_4631 = bits(_WIRE_345, 15, 15)
connect _WIRE_344.gf, _T_4631
node _T_4632 = bits(_WIRE_345, 16, 16)
connect _WIRE_344.pf, _T_4632
node _T_4633 = bits(_WIRE_345, 17, 17)
connect _WIRE_344.ae_stage2, _T_4633
node _T_4634 = bits(_WIRE_345, 18, 18)
connect _WIRE_344.ae_final, _T_4634
node _T_4635 = bits(_WIRE_345, 19, 19)
connect _WIRE_344.ae_ptw, _T_4635
node _T_4636 = bits(_WIRE_345, 20, 20)
connect _WIRE_344.g, _T_4636
node _T_4637 = bits(_WIRE_345, 21, 21)
connect _WIRE_344.u, _T_4637
node _T_4638 = bits(_WIRE_345, 41, 22)
connect _WIRE_344.ppn, _T_4638
wire _WIRE_346 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_347 : UInt<42>
connect _WIRE_347, sectored_entries[0][7].data[2]
node _T_4639 = bits(_WIRE_347, 0, 0)
connect _WIRE_346.fragmented_superpage, _T_4639
node _T_4640 = bits(_WIRE_347, 1, 1)
connect _WIRE_346.c, _T_4640
node _T_4641 = bits(_WIRE_347, 2, 2)
connect _WIRE_346.eff, _T_4641
node _T_4642 = bits(_WIRE_347, 3, 3)
connect _WIRE_346.paa, _T_4642
node _T_4643 = bits(_WIRE_347, 4, 4)
connect _WIRE_346.pal, _T_4643
node _T_4644 = bits(_WIRE_347, 5, 5)
connect _WIRE_346.ppp, _T_4644
node _T_4645 = bits(_WIRE_347, 6, 6)
connect _WIRE_346.pr, _T_4645
node _T_4646 = bits(_WIRE_347, 7, 7)
connect _WIRE_346.px, _T_4646
node _T_4647 = bits(_WIRE_347, 8, 8)
connect _WIRE_346.pw, _T_4647
node _T_4648 = bits(_WIRE_347, 9, 9)
connect _WIRE_346.hr, _T_4648
node _T_4649 = bits(_WIRE_347, 10, 10)
connect _WIRE_346.hx, _T_4649
node _T_4650 = bits(_WIRE_347, 11, 11)
connect _WIRE_346.hw, _T_4650
node _T_4651 = bits(_WIRE_347, 12, 12)
connect _WIRE_346.sr, _T_4651
node _T_4652 = bits(_WIRE_347, 13, 13)
connect _WIRE_346.sx, _T_4652
node _T_4653 = bits(_WIRE_347, 14, 14)
connect _WIRE_346.sw, _T_4653
node _T_4654 = bits(_WIRE_347, 15, 15)
connect _WIRE_346.gf, _T_4654
node _T_4655 = bits(_WIRE_347, 16, 16)
connect _WIRE_346.pf, _T_4655
node _T_4656 = bits(_WIRE_347, 17, 17)
connect _WIRE_346.ae_stage2, _T_4656
node _T_4657 = bits(_WIRE_347, 18, 18)
connect _WIRE_346.ae_final, _T_4657
node _T_4658 = bits(_WIRE_347, 19, 19)
connect _WIRE_346.ae_ptw, _T_4658
node _T_4659 = bits(_WIRE_347, 20, 20)
connect _WIRE_346.g, _T_4659
node _T_4660 = bits(_WIRE_347, 21, 21)
connect _WIRE_346.u, _T_4660
node _T_4661 = bits(_WIRE_347, 41, 22)
connect _WIRE_346.ppn, _T_4661
wire _WIRE_348 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_349 : UInt<42>
connect _WIRE_349, sectored_entries[0][7].data[3]
node _T_4662 = bits(_WIRE_349, 0, 0)
connect _WIRE_348.fragmented_superpage, _T_4662
node _T_4663 = bits(_WIRE_349, 1, 1)
connect _WIRE_348.c, _T_4663
node _T_4664 = bits(_WIRE_349, 2, 2)
connect _WIRE_348.eff, _T_4664
node _T_4665 = bits(_WIRE_349, 3, 3)
connect _WIRE_348.paa, _T_4665
node _T_4666 = bits(_WIRE_349, 4, 4)
connect _WIRE_348.pal, _T_4666
node _T_4667 = bits(_WIRE_349, 5, 5)
connect _WIRE_348.ppp, _T_4667
node _T_4668 = bits(_WIRE_349, 6, 6)
connect _WIRE_348.pr, _T_4668
node _T_4669 = bits(_WIRE_349, 7, 7)
connect _WIRE_348.px, _T_4669
node _T_4670 = bits(_WIRE_349, 8, 8)
connect _WIRE_348.pw, _T_4670
node _T_4671 = bits(_WIRE_349, 9, 9)
connect _WIRE_348.hr, _T_4671
node _T_4672 = bits(_WIRE_349, 10, 10)
connect _WIRE_348.hx, _T_4672
node _T_4673 = bits(_WIRE_349, 11, 11)
connect _WIRE_348.hw, _T_4673
node _T_4674 = bits(_WIRE_349, 12, 12)
connect _WIRE_348.sr, _T_4674
node _T_4675 = bits(_WIRE_349, 13, 13)
connect _WIRE_348.sx, _T_4675
node _T_4676 = bits(_WIRE_349, 14, 14)
connect _WIRE_348.sw, _T_4676
node _T_4677 = bits(_WIRE_349, 15, 15)
connect _WIRE_348.gf, _T_4677
node _T_4678 = bits(_WIRE_349, 16, 16)
connect _WIRE_348.pf, _T_4678
node _T_4679 = bits(_WIRE_349, 17, 17)
connect _WIRE_348.ae_stage2, _T_4679
node _T_4680 = bits(_WIRE_349, 18, 18)
connect _WIRE_348.ae_final, _T_4680
node _T_4681 = bits(_WIRE_349, 19, 19)
connect _WIRE_348.ae_ptw, _T_4681
node _T_4682 = bits(_WIRE_349, 20, 20)
connect _WIRE_348.g, _T_4682
node _T_4683 = bits(_WIRE_349, 21, 21)
connect _WIRE_348.u, _T_4683
node _T_4684 = bits(_WIRE_349, 41, 22)
connect _WIRE_348.ppn, _T_4684
node _T_4685 = eq(sectored_entries[0][7].tag_v, UInt<1>(0h1))
when _T_4685 :
connect sectored_entries[0][7].valid[0], UInt<1>(0h0)
node _T_4686 = eq(sectored_entries[0][7].tag_v, UInt<1>(0h1))
when _T_4686 :
connect sectored_entries[0][7].valid[1], UInt<1>(0h0)
node _T_4687 = eq(sectored_entries[0][7].tag_v, UInt<1>(0h1))
when _T_4687 :
connect sectored_entries[0][7].valid[2], UInt<1>(0h0)
node _T_4688 = eq(sectored_entries[0][7].tag_v, UInt<1>(0h1))
when _T_4688 :
connect sectored_entries[0][7].valid[3], UInt<1>(0h0)
wire _WIRE_350 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_351 : UInt<42>
connect _WIRE_351, superpage_entries[0].data[0]
node _T_4689 = bits(_WIRE_351, 0, 0)
connect _WIRE_350.fragmented_superpage, _T_4689
node _T_4690 = bits(_WIRE_351, 1, 1)
connect _WIRE_350.c, _T_4690
node _T_4691 = bits(_WIRE_351, 2, 2)
connect _WIRE_350.eff, _T_4691
node _T_4692 = bits(_WIRE_351, 3, 3)
connect _WIRE_350.paa, _T_4692
node _T_4693 = bits(_WIRE_351, 4, 4)
connect _WIRE_350.pal, _T_4693
node _T_4694 = bits(_WIRE_351, 5, 5)
connect _WIRE_350.ppp, _T_4694
node _T_4695 = bits(_WIRE_351, 6, 6)
connect _WIRE_350.pr, _T_4695
node _T_4696 = bits(_WIRE_351, 7, 7)
connect _WIRE_350.px, _T_4696
node _T_4697 = bits(_WIRE_351, 8, 8)
connect _WIRE_350.pw, _T_4697
node _T_4698 = bits(_WIRE_351, 9, 9)
connect _WIRE_350.hr, _T_4698
node _T_4699 = bits(_WIRE_351, 10, 10)
connect _WIRE_350.hx, _T_4699
node _T_4700 = bits(_WIRE_351, 11, 11)
connect _WIRE_350.hw, _T_4700
node _T_4701 = bits(_WIRE_351, 12, 12)
connect _WIRE_350.sr, _T_4701
node _T_4702 = bits(_WIRE_351, 13, 13)
connect _WIRE_350.sx, _T_4702
node _T_4703 = bits(_WIRE_351, 14, 14)
connect _WIRE_350.sw, _T_4703
node _T_4704 = bits(_WIRE_351, 15, 15)
connect _WIRE_350.gf, _T_4704
node _T_4705 = bits(_WIRE_351, 16, 16)
connect _WIRE_350.pf, _T_4705
node _T_4706 = bits(_WIRE_351, 17, 17)
connect _WIRE_350.ae_stage2, _T_4706
node _T_4707 = bits(_WIRE_351, 18, 18)
connect _WIRE_350.ae_final, _T_4707
node _T_4708 = bits(_WIRE_351, 19, 19)
connect _WIRE_350.ae_ptw, _T_4708
node _T_4709 = bits(_WIRE_351, 20, 20)
connect _WIRE_350.g, _T_4709
node _T_4710 = bits(_WIRE_351, 21, 21)
connect _WIRE_350.u, _T_4710
node _T_4711 = bits(_WIRE_351, 41, 22)
connect _WIRE_350.ppn, _T_4711
node _T_4712 = eq(superpage_entries[0].tag_v, UInt<1>(0h1))
when _T_4712 :
connect superpage_entries[0].valid[0], UInt<1>(0h0)
wire _WIRE_352 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_353 : UInt<42>
connect _WIRE_353, superpage_entries[1].data[0]
node _T_4713 = bits(_WIRE_353, 0, 0)
connect _WIRE_352.fragmented_superpage, _T_4713
node _T_4714 = bits(_WIRE_353, 1, 1)
connect _WIRE_352.c, _T_4714
node _T_4715 = bits(_WIRE_353, 2, 2)
connect _WIRE_352.eff, _T_4715
node _T_4716 = bits(_WIRE_353, 3, 3)
connect _WIRE_352.paa, _T_4716
node _T_4717 = bits(_WIRE_353, 4, 4)
connect _WIRE_352.pal, _T_4717
node _T_4718 = bits(_WIRE_353, 5, 5)
connect _WIRE_352.ppp, _T_4718
node _T_4719 = bits(_WIRE_353, 6, 6)
connect _WIRE_352.pr, _T_4719
node _T_4720 = bits(_WIRE_353, 7, 7)
connect _WIRE_352.px, _T_4720
node _T_4721 = bits(_WIRE_353, 8, 8)
connect _WIRE_352.pw, _T_4721
node _T_4722 = bits(_WIRE_353, 9, 9)
connect _WIRE_352.hr, _T_4722
node _T_4723 = bits(_WIRE_353, 10, 10)
connect _WIRE_352.hx, _T_4723
node _T_4724 = bits(_WIRE_353, 11, 11)
connect _WIRE_352.hw, _T_4724
node _T_4725 = bits(_WIRE_353, 12, 12)
connect _WIRE_352.sr, _T_4725
node _T_4726 = bits(_WIRE_353, 13, 13)
connect _WIRE_352.sx, _T_4726
node _T_4727 = bits(_WIRE_353, 14, 14)
connect _WIRE_352.sw, _T_4727
node _T_4728 = bits(_WIRE_353, 15, 15)
connect _WIRE_352.gf, _T_4728
node _T_4729 = bits(_WIRE_353, 16, 16)
connect _WIRE_352.pf, _T_4729
node _T_4730 = bits(_WIRE_353, 17, 17)
connect _WIRE_352.ae_stage2, _T_4730
node _T_4731 = bits(_WIRE_353, 18, 18)
connect _WIRE_352.ae_final, _T_4731
node _T_4732 = bits(_WIRE_353, 19, 19)
connect _WIRE_352.ae_ptw, _T_4732
node _T_4733 = bits(_WIRE_353, 20, 20)
connect _WIRE_352.g, _T_4733
node _T_4734 = bits(_WIRE_353, 21, 21)
connect _WIRE_352.u, _T_4734
node _T_4735 = bits(_WIRE_353, 41, 22)
connect _WIRE_352.ppn, _T_4735
node _T_4736 = eq(superpage_entries[1].tag_v, UInt<1>(0h1))
when _T_4736 :
connect superpage_entries[1].valid[0], UInt<1>(0h0)
wire _WIRE_354 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_355 : UInt<42>
connect _WIRE_355, superpage_entries[2].data[0]
node _T_4737 = bits(_WIRE_355, 0, 0)
connect _WIRE_354.fragmented_superpage, _T_4737
node _T_4738 = bits(_WIRE_355, 1, 1)
connect _WIRE_354.c, _T_4738
node _T_4739 = bits(_WIRE_355, 2, 2)
connect _WIRE_354.eff, _T_4739
node _T_4740 = bits(_WIRE_355, 3, 3)
connect _WIRE_354.paa, _T_4740
node _T_4741 = bits(_WIRE_355, 4, 4)
connect _WIRE_354.pal, _T_4741
node _T_4742 = bits(_WIRE_355, 5, 5)
connect _WIRE_354.ppp, _T_4742
node _T_4743 = bits(_WIRE_355, 6, 6)
connect _WIRE_354.pr, _T_4743
node _T_4744 = bits(_WIRE_355, 7, 7)
connect _WIRE_354.px, _T_4744
node _T_4745 = bits(_WIRE_355, 8, 8)
connect _WIRE_354.pw, _T_4745
node _T_4746 = bits(_WIRE_355, 9, 9)
connect _WIRE_354.hr, _T_4746
node _T_4747 = bits(_WIRE_355, 10, 10)
connect _WIRE_354.hx, _T_4747
node _T_4748 = bits(_WIRE_355, 11, 11)
connect _WIRE_354.hw, _T_4748
node _T_4749 = bits(_WIRE_355, 12, 12)
connect _WIRE_354.sr, _T_4749
node _T_4750 = bits(_WIRE_355, 13, 13)
connect _WIRE_354.sx, _T_4750
node _T_4751 = bits(_WIRE_355, 14, 14)
connect _WIRE_354.sw, _T_4751
node _T_4752 = bits(_WIRE_355, 15, 15)
connect _WIRE_354.gf, _T_4752
node _T_4753 = bits(_WIRE_355, 16, 16)
connect _WIRE_354.pf, _T_4753
node _T_4754 = bits(_WIRE_355, 17, 17)
connect _WIRE_354.ae_stage2, _T_4754
node _T_4755 = bits(_WIRE_355, 18, 18)
connect _WIRE_354.ae_final, _T_4755
node _T_4756 = bits(_WIRE_355, 19, 19)
connect _WIRE_354.ae_ptw, _T_4756
node _T_4757 = bits(_WIRE_355, 20, 20)
connect _WIRE_354.g, _T_4757
node _T_4758 = bits(_WIRE_355, 21, 21)
connect _WIRE_354.u, _T_4758
node _T_4759 = bits(_WIRE_355, 41, 22)
connect _WIRE_354.ppn, _T_4759
node _T_4760 = eq(superpage_entries[2].tag_v, UInt<1>(0h1))
when _T_4760 :
connect superpage_entries[2].valid[0], UInt<1>(0h0)
wire _WIRE_356 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_357 : UInt<42>
connect _WIRE_357, superpage_entries[3].data[0]
node _T_4761 = bits(_WIRE_357, 0, 0)
connect _WIRE_356.fragmented_superpage, _T_4761
node _T_4762 = bits(_WIRE_357, 1, 1)
connect _WIRE_356.c, _T_4762
node _T_4763 = bits(_WIRE_357, 2, 2)
connect _WIRE_356.eff, _T_4763
node _T_4764 = bits(_WIRE_357, 3, 3)
connect _WIRE_356.paa, _T_4764
node _T_4765 = bits(_WIRE_357, 4, 4)
connect _WIRE_356.pal, _T_4765
node _T_4766 = bits(_WIRE_357, 5, 5)
connect _WIRE_356.ppp, _T_4766
node _T_4767 = bits(_WIRE_357, 6, 6)
connect _WIRE_356.pr, _T_4767
node _T_4768 = bits(_WIRE_357, 7, 7)
connect _WIRE_356.px, _T_4768
node _T_4769 = bits(_WIRE_357, 8, 8)
connect _WIRE_356.pw, _T_4769
node _T_4770 = bits(_WIRE_357, 9, 9)
connect _WIRE_356.hr, _T_4770
node _T_4771 = bits(_WIRE_357, 10, 10)
connect _WIRE_356.hx, _T_4771
node _T_4772 = bits(_WIRE_357, 11, 11)
connect _WIRE_356.hw, _T_4772
node _T_4773 = bits(_WIRE_357, 12, 12)
connect _WIRE_356.sr, _T_4773
node _T_4774 = bits(_WIRE_357, 13, 13)
connect _WIRE_356.sx, _T_4774
node _T_4775 = bits(_WIRE_357, 14, 14)
connect _WIRE_356.sw, _T_4775
node _T_4776 = bits(_WIRE_357, 15, 15)
connect _WIRE_356.gf, _T_4776
node _T_4777 = bits(_WIRE_357, 16, 16)
connect _WIRE_356.pf, _T_4777
node _T_4778 = bits(_WIRE_357, 17, 17)
connect _WIRE_356.ae_stage2, _T_4778
node _T_4779 = bits(_WIRE_357, 18, 18)
connect _WIRE_356.ae_final, _T_4779
node _T_4780 = bits(_WIRE_357, 19, 19)
connect _WIRE_356.ae_ptw, _T_4780
node _T_4781 = bits(_WIRE_357, 20, 20)
connect _WIRE_356.g, _T_4781
node _T_4782 = bits(_WIRE_357, 21, 21)
connect _WIRE_356.u, _T_4782
node _T_4783 = bits(_WIRE_357, 41, 22)
connect _WIRE_356.ppn, _T_4783
node _T_4784 = eq(superpage_entries[3].tag_v, UInt<1>(0h1))
when _T_4784 :
connect superpage_entries[3].valid[0], UInt<1>(0h0)
wire _WIRE_358 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_359 : UInt<42>
connect _WIRE_359, special_entry.data[0]
node _T_4785 = bits(_WIRE_359, 0, 0)
connect _WIRE_358.fragmented_superpage, _T_4785
node _T_4786 = bits(_WIRE_359, 1, 1)
connect _WIRE_358.c, _T_4786
node _T_4787 = bits(_WIRE_359, 2, 2)
connect _WIRE_358.eff, _T_4787
node _T_4788 = bits(_WIRE_359, 3, 3)
connect _WIRE_358.paa, _T_4788
node _T_4789 = bits(_WIRE_359, 4, 4)
connect _WIRE_358.pal, _T_4789
node _T_4790 = bits(_WIRE_359, 5, 5)
connect _WIRE_358.ppp, _T_4790
node _T_4791 = bits(_WIRE_359, 6, 6)
connect _WIRE_358.pr, _T_4791
node _T_4792 = bits(_WIRE_359, 7, 7)
connect _WIRE_358.px, _T_4792
node _T_4793 = bits(_WIRE_359, 8, 8)
connect _WIRE_358.pw, _T_4793
node _T_4794 = bits(_WIRE_359, 9, 9)
connect _WIRE_358.hr, _T_4794
node _T_4795 = bits(_WIRE_359, 10, 10)
connect _WIRE_358.hx, _T_4795
node _T_4796 = bits(_WIRE_359, 11, 11)
connect _WIRE_358.hw, _T_4796
node _T_4797 = bits(_WIRE_359, 12, 12)
connect _WIRE_358.sr, _T_4797
node _T_4798 = bits(_WIRE_359, 13, 13)
connect _WIRE_358.sx, _T_4798
node _T_4799 = bits(_WIRE_359, 14, 14)
connect _WIRE_358.sw, _T_4799
node _T_4800 = bits(_WIRE_359, 15, 15)
connect _WIRE_358.gf, _T_4800
node _T_4801 = bits(_WIRE_359, 16, 16)
connect _WIRE_358.pf, _T_4801
node _T_4802 = bits(_WIRE_359, 17, 17)
connect _WIRE_358.ae_stage2, _T_4802
node _T_4803 = bits(_WIRE_359, 18, 18)
connect _WIRE_358.ae_final, _T_4803
node _T_4804 = bits(_WIRE_359, 19, 19)
connect _WIRE_358.ae_ptw, _T_4804
node _T_4805 = bits(_WIRE_359, 20, 20)
connect _WIRE_358.g, _T_4805
node _T_4806 = bits(_WIRE_359, 21, 21)
connect _WIRE_358.u, _T_4806
node _T_4807 = bits(_WIRE_359, 41, 22)
connect _WIRE_358.ppn, _T_4807
node _T_4808 = eq(special_entry.tag_v, UInt<1>(0h1))
when _T_4808 :
connect special_entry.valid[0], UInt<1>(0h0)
connect v_entries_use_stage1, vstage1_en
node _T_4809 = asUInt(reset)
node _T_4810 = or(multipleHits, _T_4809)
when _T_4810 :
connect sectored_entries[0][0].valid[0], UInt<1>(0h0)
connect sectored_entries[0][0].valid[1], UInt<1>(0h0)
connect sectored_entries[0][0].valid[2], UInt<1>(0h0)
connect sectored_entries[0][0].valid[3], UInt<1>(0h0)
connect sectored_entries[0][1].valid[0], UInt<1>(0h0)
connect sectored_entries[0][1].valid[1], UInt<1>(0h0)
connect sectored_entries[0][1].valid[2], UInt<1>(0h0)
connect sectored_entries[0][1].valid[3], UInt<1>(0h0)
connect sectored_entries[0][2].valid[0], UInt<1>(0h0)
connect sectored_entries[0][2].valid[1], UInt<1>(0h0)
connect sectored_entries[0][2].valid[2], UInt<1>(0h0)
connect sectored_entries[0][2].valid[3], UInt<1>(0h0)
connect sectored_entries[0][3].valid[0], UInt<1>(0h0)
connect sectored_entries[0][3].valid[1], UInt<1>(0h0)
connect sectored_entries[0][3].valid[2], UInt<1>(0h0)
connect sectored_entries[0][3].valid[3], UInt<1>(0h0)
connect sectored_entries[0][4].valid[0], UInt<1>(0h0)
connect sectored_entries[0][4].valid[1], UInt<1>(0h0)
connect sectored_entries[0][4].valid[2], UInt<1>(0h0)
connect sectored_entries[0][4].valid[3], UInt<1>(0h0)
connect sectored_entries[0][5].valid[0], UInt<1>(0h0)
connect sectored_entries[0][5].valid[1], UInt<1>(0h0)
connect sectored_entries[0][5].valid[2], UInt<1>(0h0)
connect sectored_entries[0][5].valid[3], UInt<1>(0h0)
connect sectored_entries[0][6].valid[0], UInt<1>(0h0)
connect sectored_entries[0][6].valid[1], UInt<1>(0h0)
connect sectored_entries[0][6].valid[2], UInt<1>(0h0)
connect sectored_entries[0][6].valid[3], UInt<1>(0h0)
connect sectored_entries[0][7].valid[0], UInt<1>(0h0)
connect sectored_entries[0][7].valid[1], UInt<1>(0h0)
connect sectored_entries[0][7].valid[2], UInt<1>(0h0)
connect sectored_entries[0][7].valid[3], UInt<1>(0h0)
connect superpage_entries[0].valid[0], UInt<1>(0h0)
connect superpage_entries[1].valid[0], UInt<1>(0h0)
connect superpage_entries[2].valid[0], UInt<1>(0h0)
connect superpage_entries[3].valid[0], UInt<1>(0h0)
connect special_entry.valid[0], UInt<1>(0h0)
node _T_4811 = and(io.ptw.req.ready, io.ptw.req.valid)
node _T_4812 = eq(io.ptw.req.ready, UInt<1>(0h0))
node _T_4813 = and(io.ptw.req.valid, _T_4812)
node _T_4814 = eq(state, UInt<2>(0h3))
node _T_4815 = eq(io.sfence.bits.rs1, UInt<1>(0h0))
node _T_4816 = and(io.sfence.valid, _T_4815)
node _T_4817 = eq(io.sfence.bits.rs2, UInt<1>(0h0))
node _T_4818 = and(_T_4816, _T_4817)
node _T_4819 = eq(io.sfence.bits.rs1, UInt<1>(0h0))
node _T_4820 = and(io.sfence.valid, _T_4819)
node _T_4821 = and(_T_4820, io.sfence.bits.rs2)
node _T_4822 = and(io.sfence.valid, io.sfence.bits.rs1)
node _T_4823 = eq(io.sfence.bits.rs2, UInt<1>(0h0))
node _T_4824 = and(_T_4822, _T_4823)
node _T_4825 = and(io.sfence.valid, io.sfence.bits.rs1)
node _T_4826 = and(_T_4825, io.sfence.bits.rs2) | module DTLB_2( // @[TLB.scala:318:7]
input clock, // @[TLB.scala:318:7]
input reset, // @[TLB.scala:318:7]
output io_req_ready, // @[TLB.scala:320:14]
input io_req_valid, // @[TLB.scala:320:14]
input [39:0] io_req_bits_vaddr, // @[TLB.scala:320:14]
input io_req_bits_passthrough, // @[TLB.scala:320:14]
input [1:0] io_req_bits_size, // @[TLB.scala:320:14]
input [4:0] io_req_bits_cmd, // @[TLB.scala:320:14]
input [1:0] io_req_bits_prv, // @[TLB.scala:320:14]
input io_req_bits_v, // @[TLB.scala:320:14]
output io_resp_miss, // @[TLB.scala:320:14]
output [31:0] io_resp_paddr, // @[TLB.scala:320:14]
output [39:0] io_resp_gpa, // @[TLB.scala:320:14]
output io_resp_pf_ld, // @[TLB.scala:320:14]
output io_resp_pf_st, // @[TLB.scala:320:14]
output io_resp_pf_inst, // @[TLB.scala:320:14]
output io_resp_ae_ld, // @[TLB.scala:320:14]
output io_resp_ae_st, // @[TLB.scala:320:14]
output io_resp_ae_inst, // @[TLB.scala:320:14]
output io_resp_ma_ld, // @[TLB.scala:320:14]
output io_resp_ma_st, // @[TLB.scala:320:14]
output io_resp_cacheable, // @[TLB.scala:320:14]
output io_resp_must_alloc, // @[TLB.scala:320:14]
output io_resp_prefetchable, // @[TLB.scala:320:14]
output [1:0] io_resp_size, // @[TLB.scala:320:14]
output [4:0] io_resp_cmd, // @[TLB.scala:320:14]
input io_sfence_valid, // @[TLB.scala:320:14]
input io_sfence_bits_rs1, // @[TLB.scala:320:14]
input io_sfence_bits_rs2, // @[TLB.scala:320:14]
input [38:0] io_sfence_bits_addr, // @[TLB.scala:320:14]
input io_sfence_bits_asid, // @[TLB.scala:320:14]
input io_sfence_bits_hv, // @[TLB.scala:320:14]
input io_sfence_bits_hg, // @[TLB.scala:320:14]
input io_ptw_req_ready, // @[TLB.scala:320:14]
output io_ptw_req_valid, // @[TLB.scala:320:14]
output [26:0] io_ptw_req_bits_bits_addr, // @[TLB.scala:320:14]
output io_ptw_req_bits_bits_need_gpa, // @[TLB.scala:320:14]
input io_ptw_resp_valid, // @[TLB.scala:320:14]
input io_ptw_resp_bits_ae_ptw, // @[TLB.scala:320:14]
input io_ptw_resp_bits_ae_final, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pf, // @[TLB.scala:320:14]
input io_ptw_resp_bits_gf, // @[TLB.scala:320:14]
input io_ptw_resp_bits_hr, // @[TLB.scala:320:14]
input io_ptw_resp_bits_hw, // @[TLB.scala:320:14]
input io_ptw_resp_bits_hx, // @[TLB.scala:320:14]
input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[TLB.scala:320:14]
input [43:0] io_ptw_resp_bits_pte_ppn, // @[TLB.scala:320:14]
input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_d, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_a, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_g, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_u, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_x, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_w, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_r, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_v, // @[TLB.scala:320:14]
input [1:0] io_ptw_resp_bits_level, // @[TLB.scala:320:14]
input io_ptw_resp_bits_homogeneous, // @[TLB.scala:320:14]
input io_ptw_resp_bits_gpa_valid, // @[TLB.scala:320:14]
input [38:0] io_ptw_resp_bits_gpa_bits, // @[TLB.scala:320:14]
input io_ptw_resp_bits_gpa_is_pte, // @[TLB.scala:320:14]
input [3:0] io_ptw_ptbr_mode, // @[TLB.scala:320:14]
input [15:0] io_ptw_ptbr_asid, // @[TLB.scala:320:14]
input [43:0] io_ptw_ptbr_ppn, // @[TLB.scala:320:14]
input io_ptw_status_debug, // @[TLB.scala:320:14]
input io_ptw_status_cease, // @[TLB.scala:320:14]
input io_ptw_status_wfi, // @[TLB.scala:320:14]
input [31:0] io_ptw_status_isa, // @[TLB.scala:320:14]
input [1:0] io_ptw_status_dprv, // @[TLB.scala:320:14]
input io_ptw_status_dv, // @[TLB.scala:320:14]
input [1:0] io_ptw_status_prv, // @[TLB.scala:320:14]
input io_ptw_status_v, // @[TLB.scala:320:14]
input io_ptw_status_sd, // @[TLB.scala:320:14]
input [22:0] io_ptw_status_zero2, // @[TLB.scala:320:14]
input io_ptw_status_mpv, // @[TLB.scala:320:14]
input io_ptw_status_gva, // @[TLB.scala:320:14]
input io_ptw_status_mbe, // @[TLB.scala:320:14]
input io_ptw_status_sbe, // @[TLB.scala:320:14]
input [1:0] io_ptw_status_sxl, // @[TLB.scala:320:14]
input [1:0] io_ptw_status_uxl, // @[TLB.scala:320:14]
input io_ptw_status_sd_rv32, // @[TLB.scala:320:14]
input [7:0] io_ptw_status_zero1, // @[TLB.scala:320:14]
input io_ptw_status_tsr, // @[TLB.scala:320:14]
input io_ptw_status_tw, // @[TLB.scala:320:14]
input io_ptw_status_tvm, // @[TLB.scala:320:14]
input io_ptw_status_mxr, // @[TLB.scala:320:14]
input io_ptw_status_sum, // @[TLB.scala:320:14]
input io_ptw_status_mprv, // @[TLB.scala:320:14]
input [1:0] io_ptw_status_xs, // @[TLB.scala:320:14]
input [1:0] io_ptw_status_fs, // @[TLB.scala:320:14]
input [1:0] io_ptw_status_mpp, // @[TLB.scala:320:14]
input [1:0] io_ptw_status_vs, // @[TLB.scala:320:14]
input io_ptw_status_spp, // @[TLB.scala:320:14]
input io_ptw_status_mpie, // @[TLB.scala:320:14]
input io_ptw_status_ube, // @[TLB.scala:320:14]
input io_ptw_status_spie, // @[TLB.scala:320:14]
input io_ptw_status_upie, // @[TLB.scala:320:14]
input io_ptw_status_mie, // @[TLB.scala:320:14]
input io_ptw_status_hie, // @[TLB.scala:320:14]
input io_ptw_status_sie, // @[TLB.scala:320:14]
input io_ptw_status_uie // @[TLB.scala:320:14]
);
wire [19:0] _entries_barrier_12_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_hr; // @[package.scala:267:25]
wire [19:0] _entries_barrier_11_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_10_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_9_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_8_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_7_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_6_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_5_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_4_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_3_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_2_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_1_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_io_y_c; // @[package.scala:267:25]
wire _pma_io_resp_r; // @[TLB.scala:422:19]
wire _pma_io_resp_w; // @[TLB.scala:422:19]
wire _pma_io_resp_pp; // @[TLB.scala:422:19]
wire _pma_io_resp_al; // @[TLB.scala:422:19]
wire _pma_io_resp_aa; // @[TLB.scala:422:19]
wire _pma_io_resp_x; // @[TLB.scala:422:19]
wire _pma_io_resp_eff; // @[TLB.scala:422:19]
wire [19:0] _mpu_ppn_barrier_io_y_ppn; // @[package.scala:267:25]
wire io_req_valid_0 = io_req_valid; // @[TLB.scala:318:7]
wire [39:0] io_req_bits_vaddr_0 = io_req_bits_vaddr; // @[TLB.scala:318:7]
wire io_req_bits_passthrough_0 = io_req_bits_passthrough; // @[TLB.scala:318:7]
wire [1:0] io_req_bits_size_0 = io_req_bits_size; // @[TLB.scala:318:7]
wire [4:0] io_req_bits_cmd_0 = io_req_bits_cmd; // @[TLB.scala:318:7]
wire [1:0] io_req_bits_prv_0 = io_req_bits_prv; // @[TLB.scala:318:7]
wire io_req_bits_v_0 = io_req_bits_v; // @[TLB.scala:318:7]
wire io_sfence_valid_0 = io_sfence_valid; // @[TLB.scala:318:7]
wire io_sfence_bits_rs1_0 = io_sfence_bits_rs1; // @[TLB.scala:318:7]
wire io_sfence_bits_rs2_0 = io_sfence_bits_rs2; // @[TLB.scala:318:7]
wire [38:0] io_sfence_bits_addr_0 = io_sfence_bits_addr; // @[TLB.scala:318:7]
wire io_sfence_bits_asid_0 = io_sfence_bits_asid; // @[TLB.scala:318:7]
wire io_sfence_bits_hv_0 = io_sfence_bits_hv; // @[TLB.scala:318:7]
wire io_sfence_bits_hg_0 = io_sfence_bits_hg; // @[TLB.scala:318:7]
wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[TLB.scala:318:7]
wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[TLB.scala:318:7]
wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[TLB.scala:318:7]
wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[TLB.scala:318:7]
wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[TLB.scala:318:7]
wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[TLB.scala:318:7]
wire [38:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[TLB.scala:318:7]
wire [3:0] io_ptw_ptbr_mode_0 = io_ptw_ptbr_mode; // @[TLB.scala:318:7]
wire [15:0] io_ptw_ptbr_asid_0 = io_ptw_ptbr_asid; // @[TLB.scala:318:7]
wire [43:0] io_ptw_ptbr_ppn_0 = io_ptw_ptbr_ppn; // @[TLB.scala:318:7]
wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[TLB.scala:318:7]
wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[TLB.scala:318:7]
wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[TLB.scala:318:7]
wire [31:0] io_ptw_status_isa_0 = io_ptw_status_isa; // @[TLB.scala:318:7]
wire [1:0] io_ptw_status_dprv_0 = io_ptw_status_dprv; // @[TLB.scala:318:7]
wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[TLB.scala:318:7]
wire [1:0] io_ptw_status_prv_0 = io_ptw_status_prv; // @[TLB.scala:318:7]
wire io_ptw_status_v_0 = io_ptw_status_v; // @[TLB.scala:318:7]
wire io_ptw_status_sd_0 = io_ptw_status_sd; // @[TLB.scala:318:7]
wire [22:0] io_ptw_status_zero2_0 = io_ptw_status_zero2; // @[TLB.scala:318:7]
wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[TLB.scala:318:7]
wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[TLB.scala:318:7]
wire io_ptw_status_mbe_0 = io_ptw_status_mbe; // @[TLB.scala:318:7]
wire io_ptw_status_sbe_0 = io_ptw_status_sbe; // @[TLB.scala:318:7]
wire [1:0] io_ptw_status_sxl_0 = io_ptw_status_sxl; // @[TLB.scala:318:7]
wire [1:0] io_ptw_status_uxl_0 = io_ptw_status_uxl; // @[TLB.scala:318:7]
wire io_ptw_status_sd_rv32_0 = io_ptw_status_sd_rv32; // @[TLB.scala:318:7]
wire [7:0] io_ptw_status_zero1_0 = io_ptw_status_zero1; // @[TLB.scala:318:7]
wire io_ptw_status_tsr_0 = io_ptw_status_tsr; // @[TLB.scala:318:7]
wire io_ptw_status_tw_0 = io_ptw_status_tw; // @[TLB.scala:318:7]
wire io_ptw_status_tvm_0 = io_ptw_status_tvm; // @[TLB.scala:318:7]
wire io_ptw_status_mxr_0 = io_ptw_status_mxr; // @[TLB.scala:318:7]
wire io_ptw_status_sum_0 = io_ptw_status_sum; // @[TLB.scala:318:7]
wire io_ptw_status_mprv_0 = io_ptw_status_mprv; // @[TLB.scala:318:7]
wire [1:0] io_ptw_status_xs_0 = io_ptw_status_xs; // @[TLB.scala:318:7]
wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[TLB.scala:318:7]
wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[TLB.scala:318:7]
wire [1:0] io_ptw_status_vs_0 = io_ptw_status_vs; // @[TLB.scala:318:7]
wire io_ptw_status_spp_0 = io_ptw_status_spp; // @[TLB.scala:318:7]
wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[TLB.scala:318:7]
wire io_ptw_status_ube_0 = io_ptw_status_ube; // @[TLB.scala:318:7]
wire io_ptw_status_spie_0 = io_ptw_status_spie; // @[TLB.scala:318:7]
wire io_ptw_status_upie_0 = io_ptw_status_upie; // @[TLB.scala:318:7]
wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[TLB.scala:318:7]
wire io_ptw_status_hie_0 = io_ptw_status_hie; // @[TLB.scala:318:7]
wire io_ptw_status_sie_0 = io_ptw_status_sie; // @[TLB.scala:318:7]
wire io_ptw_status_uie_0 = io_ptw_status_uie; // @[TLB.scala:318:7]
wire io_resp_gpa_is_pte = 1'h0; // @[TLB.scala:318:7]
wire io_resp_gf_ld = 1'h0; // @[TLB.scala:318:7]
wire io_resp_gf_st = 1'h0; // @[TLB.scala:318:7]
wire io_resp_gf_inst = 1'h0; // @[TLB.scala:318:7]
wire io_resp_ma_inst = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_req_bits_bits_vstage1 = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_req_bits_bits_stage2 = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_hstatus_vtsr = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_hstatus_vtw = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_hstatus_vtvm = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_hstatus_hu = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_hstatus_spvp = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_hstatus_spv = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_hstatus_gva = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_hstatus_vsbe = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_debug = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_cease = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_wfi = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_dv = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_v = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_sd = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_mpv = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_gva = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_mbe = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_sbe = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_tsr = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_tw = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_tvm = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_mxr = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_sum = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_mprv = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_spp = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_mpie = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_ube = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_spie = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_upie = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_mie = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_hie = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_sie = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_uie = 1'h0; // @[TLB.scala:318:7]
wire io_kill = 1'h0; // @[TLB.scala:318:7]
wire priv_v = 1'h0; // @[TLB.scala:369:34]
wire _vstage1_en_T = 1'h0; // @[TLB.scala:376:38]
wire _vstage1_en_T_1 = 1'h0; // @[TLB.scala:376:68]
wire vstage1_en = 1'h0; // @[TLB.scala:376:48]
wire _stage2_en_T = 1'h0; // @[TLB.scala:378:38]
wire _stage2_en_T_1 = 1'h0; // @[TLB.scala:378:68]
wire stage2_en = 1'h0; // @[TLB.scala:378:48]
wire _vsatp_mode_mismatch_T = 1'h0; // @[TLB.scala:403:52]
wire _vsatp_mode_mismatch_T_1 = 1'h0; // @[TLB.scala:403:37]
wire vsatp_mode_mismatch = 1'h0; // @[TLB.scala:403:78]
wire _superpage_hits_ignore_T = 1'h0; // @[TLB.scala:182:28]
wire superpage_hits_ignore = 1'h0; // @[TLB.scala:182:34]
wire _superpage_hits_ignore_T_3 = 1'h0; // @[TLB.scala:182:28]
wire superpage_hits_ignore_3 = 1'h0; // @[TLB.scala:182:34]
wire _superpage_hits_ignore_T_6 = 1'h0; // @[TLB.scala:182:28]
wire superpage_hits_ignore_6 = 1'h0; // @[TLB.scala:182:34]
wire _superpage_hits_ignore_T_9 = 1'h0; // @[TLB.scala:182:28]
wire superpage_hits_ignore_9 = 1'h0; // @[TLB.scala:182:34]
wire _hitsVec_ignore_T = 1'h0; // @[TLB.scala:182:28]
wire hitsVec_ignore = 1'h0; // @[TLB.scala:182:34]
wire _hitsVec_ignore_T_3 = 1'h0; // @[TLB.scala:182:28]
wire hitsVec_ignore_3 = 1'h0; // @[TLB.scala:182:34]
wire _hitsVec_ignore_T_6 = 1'h0; // @[TLB.scala:182:28]
wire hitsVec_ignore_6 = 1'h0; // @[TLB.scala:182:34]
wire _hitsVec_ignore_T_9 = 1'h0; // @[TLB.scala:182:28]
wire hitsVec_ignore_9 = 1'h0; // @[TLB.scala:182:34]
wire _hitsVec_ignore_T_12 = 1'h0; // @[TLB.scala:182:28]
wire hitsVec_ignore_12 = 1'h0; // @[TLB.scala:182:34]
wire refill_v = 1'h0; // @[TLB.scala:448:33]
wire newEntry_ae_stage2 = 1'h0; // @[TLB.scala:449:24]
wire newEntry_fragmented_superpage = 1'h0; // @[TLB.scala:449:24]
wire _newEntry_ae_stage2_T_1 = 1'h0; // @[TLB.scala:456:84]
wire _waddr_T = 1'h0; // @[TLB.scala:477:45]
wire _mxr_T = 1'h0; // @[TLB.scala:518:36]
wire cmd_lrsc = 1'h0; // @[TLB.scala:570:33]
wire cmd_amo_logical = 1'h0; // @[TLB.scala:571:40]
wire cmd_amo_arithmetic = 1'h0; // @[TLB.scala:572:43]
wire cmd_readx = 1'h0; // @[TLB.scala:575:37]
wire _gf_ld_array_T = 1'h0; // @[TLB.scala:600:32]
wire _gf_st_array_T = 1'h0; // @[TLB.scala:601:32]
wire _multipleHits_T_6 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_15 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_27 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_35 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_40 = 1'h0; // @[Misc.scala:183:37]
wire _io_resp_gf_ld_T = 1'h0; // @[TLB.scala:637:29]
wire _io_resp_gf_ld_T_2 = 1'h0; // @[TLB.scala:637:66]
wire _io_resp_gf_ld_T_3 = 1'h0; // @[TLB.scala:637:42]
wire _io_resp_gf_st_T = 1'h0; // @[TLB.scala:638:29]
wire _io_resp_gf_st_T_2 = 1'h0; // @[TLB.scala:638:73]
wire _io_resp_gf_st_T_3 = 1'h0; // @[TLB.scala:638:49]
wire _io_resp_gf_inst_T_1 = 1'h0; // @[TLB.scala:639:56]
wire _io_resp_gf_inst_T_2 = 1'h0; // @[TLB.scala:639:30]
wire _io_resp_gpa_is_pte_T = 1'h0; // @[TLB.scala:655:36]
wire hv = 1'h0; // @[TLB.scala:721:36]
wire hg = 1'h0; // @[TLB.scala:722:36]
wire hv_1 = 1'h0; // @[TLB.scala:721:36]
wire hg_1 = 1'h0; // @[TLB.scala:722:36]
wire hv_2 = 1'h0; // @[TLB.scala:721:36]
wire hg_2 = 1'h0; // @[TLB.scala:722:36]
wire hv_3 = 1'h0; // @[TLB.scala:721:36]
wire hg_3 = 1'h0; // @[TLB.scala:722:36]
wire hv_4 = 1'h0; // @[TLB.scala:721:36]
wire hg_4 = 1'h0; // @[TLB.scala:722:36]
wire hv_5 = 1'h0; // @[TLB.scala:721:36]
wire hg_5 = 1'h0; // @[TLB.scala:722:36]
wire hv_6 = 1'h0; // @[TLB.scala:721:36]
wire hg_6 = 1'h0; // @[TLB.scala:722:36]
wire hv_7 = 1'h0; // @[TLB.scala:721:36]
wire hg_7 = 1'h0; // @[TLB.scala:722:36]
wire hv_8 = 1'h0; // @[TLB.scala:721:36]
wire hg_8 = 1'h0; // @[TLB.scala:722:36]
wire _ignore_T = 1'h0; // @[TLB.scala:182:28]
wire ignore = 1'h0; // @[TLB.scala:182:34]
wire hv_9 = 1'h0; // @[TLB.scala:721:36]
wire hg_9 = 1'h0; // @[TLB.scala:722:36]
wire _ignore_T_3 = 1'h0; // @[TLB.scala:182:28]
wire ignore_3 = 1'h0; // @[TLB.scala:182:34]
wire hv_10 = 1'h0; // @[TLB.scala:721:36]
wire hg_10 = 1'h0; // @[TLB.scala:722:36]
wire _ignore_T_6 = 1'h0; // @[TLB.scala:182:28]
wire ignore_6 = 1'h0; // @[TLB.scala:182:34]
wire hv_11 = 1'h0; // @[TLB.scala:721:36]
wire hg_11 = 1'h0; // @[TLB.scala:722:36]
wire _ignore_T_9 = 1'h0; // @[TLB.scala:182:28]
wire ignore_9 = 1'h0; // @[TLB.scala:182:34]
wire hv_12 = 1'h0; // @[TLB.scala:721:36]
wire hg_12 = 1'h0; // @[TLB.scala:722:36]
wire _ignore_T_12 = 1'h0; // @[TLB.scala:182:28]
wire ignore_12 = 1'h0; // @[TLB.scala:182:34]
wire io_ptw_req_bits_valid = 1'h1; // @[TLB.scala:318:7]
wire _homogeneous_T_71 = 1'h1; // @[TLBPermissions.scala:87:22]
wire superpage_hits_ignore_2 = 1'h1; // @[TLB.scala:182:34]
wire _superpage_hits_T_13 = 1'h1; // @[TLB.scala:183:40]
wire superpage_hits_ignore_5 = 1'h1; // @[TLB.scala:182:34]
wire _superpage_hits_T_27 = 1'h1; // @[TLB.scala:183:40]
wire superpage_hits_ignore_8 = 1'h1; // @[TLB.scala:182:34]
wire _superpage_hits_T_41 = 1'h1; // @[TLB.scala:183:40]
wire superpage_hits_ignore_11 = 1'h1; // @[TLB.scala:182:34]
wire _superpage_hits_T_55 = 1'h1; // @[TLB.scala:183:40]
wire hitsVec_ignore_2 = 1'h1; // @[TLB.scala:182:34]
wire _hitsVec_T_61 = 1'h1; // @[TLB.scala:183:40]
wire hitsVec_ignore_5 = 1'h1; // @[TLB.scala:182:34]
wire _hitsVec_T_76 = 1'h1; // @[TLB.scala:183:40]
wire hitsVec_ignore_8 = 1'h1; // @[TLB.scala:182:34]
wire _hitsVec_T_91 = 1'h1; // @[TLB.scala:183:40]
wire hitsVec_ignore_11 = 1'h1; // @[TLB.scala:182:34]
wire _hitsVec_T_106 = 1'h1; // @[TLB.scala:183:40]
wire ppn_ignore_1 = 1'h1; // @[TLB.scala:197:34]
wire ppn_ignore_3 = 1'h1; // @[TLB.scala:197:34]
wire ppn_ignore_5 = 1'h1; // @[TLB.scala:197:34]
wire ppn_ignore_7 = 1'h1; // @[TLB.scala:197:34]
wire _stage2_bypass_T = 1'h1; // @[TLB.scala:523:42]
wire _bad_va_T_1 = 1'h1; // @[TLB.scala:560:26]
wire _gpa_hits_hit_mask_T_3 = 1'h1; // @[TLB.scala:606:107]
wire _tlb_miss_T = 1'h1; // @[TLB.scala:613:32]
wire _io_resp_gpa_page_T = 1'h1; // @[TLB.scala:657:20]
wire _io_ptw_req_bits_valid_T = 1'h1; // @[TLB.scala:663:28]
wire ignore_2 = 1'h1; // @[TLB.scala:182:34]
wire ignore_5 = 1'h1; // @[TLB.scala:182:34]
wire ignore_8 = 1'h1; // @[TLB.scala:182:34]
wire ignore_11 = 1'h1; // @[TLB.scala:182:34]
wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[TLB.scala:318:7]
wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[TLB.scala:318:7]
wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[TLB.scala:318:7]
wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[TLB.scala:318:7]
wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[TLB.scala:318:7]
wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[TLB.scala:318:7]
wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_hstatus_vsxl = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_dprv = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_prv = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_sxl = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_uxl = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_xs = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_fs = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_mpp = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_vs = 2'h0; // @[TLB.scala:318:7]
wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[TLB.scala:318:7]
wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[TLB.scala:318:7]
wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[TLB.scala:318:7]
wire [31:0] io_ptw_gstatus_isa = 32'h0; // @[TLB.scala:318:7]
wire [22:0] io_ptw_gstatus_zero2 = 23'h0; // @[TLB.scala:318:7]
wire [7:0] io_ptw_gstatus_zero1 = 8'h0; // @[TLB.scala:318:7]
wire [13:0] _ae_array_T_2 = 14'h0; // @[TLB.scala:583:8]
wire [13:0] _ae_st_array_T_7 = 14'h0; // @[TLB.scala:590:8]
wire [13:0] _ae_st_array_T_10 = 14'h0; // @[TLB.scala:591:8]
wire [13:0] _must_alloc_array_T_3 = 14'h0; // @[TLB.scala:594:8]
wire [13:0] _must_alloc_array_T_6 = 14'h0; // @[TLB.scala:595:8]
wire [13:0] _must_alloc_array_T_9 = 14'h0; // @[TLB.scala:596:8]
wire [13:0] _gf_ld_array_T_2 = 14'h0; // @[TLB.scala:600:46]
wire [13:0] gf_ld_array = 14'h0; // @[TLB.scala:600:24]
wire [13:0] _gf_st_array_T_1 = 14'h0; // @[TLB.scala:601:53]
wire [13:0] gf_st_array = 14'h0; // @[TLB.scala:601:24]
wire [13:0] _gf_inst_array_T = 14'h0; // @[TLB.scala:602:36]
wire [13:0] gf_inst_array = 14'h0; // @[TLB.scala:602:26]
wire [13:0] gpa_hits_need_gpa_mask = 14'h0; // @[TLB.scala:605:73]
wire [13:0] _io_resp_gf_ld_T_1 = 14'h0; // @[TLB.scala:637:58]
wire [13:0] _io_resp_gf_st_T_1 = 14'h0; // @[TLB.scala:638:65]
wire [13:0] _io_resp_gf_inst_T = 14'h0; // @[TLB.scala:639:48]
wire [6:0] _state_vec_WIRE_0 = 7'h0; // @[Replacement.scala:305:25]
wire [12:0] stage2_bypass = 13'h1FFF; // @[TLB.scala:523:27]
wire [12:0] _hr_array_T_4 = 13'h1FFF; // @[TLB.scala:524:111]
wire [12:0] _hw_array_T_1 = 13'h1FFF; // @[TLB.scala:525:55]
wire [12:0] _hx_array_T_1 = 13'h1FFF; // @[TLB.scala:526:55]
wire [12:0] _gpa_hits_hit_mask_T_4 = 13'h1FFF; // @[TLB.scala:606:88]
wire [12:0] gpa_hits_hit_mask = 13'h1FFF; // @[TLB.scala:606:82]
wire [12:0] _gpa_hits_T_1 = 13'h1FFF; // @[TLB.scala:607:16]
wire [12:0] gpa_hits = 13'h1FFF; // @[TLB.scala:607:14]
wire [12:0] _stage1_bypass_T = 13'h0; // @[TLB.scala:517:27]
wire [12:0] stage1_bypass = 13'h0; // @[TLB.scala:517:61]
wire [12:0] _gpa_hits_T = 13'h0; // @[TLB.scala:607:30]
wire [13:0] hr_array = 14'h3FFF; // @[TLB.scala:524:21]
wire [13:0] hw_array = 14'h3FFF; // @[TLB.scala:525:21]
wire [13:0] hx_array = 14'h3FFF; // @[TLB.scala:526:21]
wire [13:0] _must_alloc_array_T_8 = 14'h3FFF; // @[TLB.scala:596:19]
wire [13:0] _gf_ld_array_T_1 = 14'h3FFF; // @[TLB.scala:600:50]
wire _io_req_ready_T; // @[TLB.scala:631:25]
wire [1:0] io_resp_size_0 = io_req_bits_size_0; // @[TLB.scala:318:7]
wire [4:0] io_resp_cmd_0 = io_req_bits_cmd_0; // @[TLB.scala:318:7]
wire _io_resp_miss_T_2; // @[TLB.scala:651:64]
wire [31:0] _io_resp_paddr_T_1; // @[TLB.scala:652:23]
wire [39:0] _io_resp_gpa_T; // @[TLB.scala:659:8]
wire _io_resp_pf_ld_T_3; // @[TLB.scala:633:41]
wire _io_resp_pf_st_T_3; // @[TLB.scala:634:48]
wire _io_resp_pf_inst_T_2; // @[TLB.scala:635:29]
wire _io_resp_ae_ld_T_1; // @[TLB.scala:641:41]
wire _io_resp_ae_st_T_1; // @[TLB.scala:642:41]
wire _io_resp_ae_inst_T_2; // @[TLB.scala:643:41]
wire _io_resp_ma_ld_T; // @[TLB.scala:645:31]
wire _io_resp_ma_st_T; // @[TLB.scala:646:31]
wire _io_resp_cacheable_T_1; // @[TLB.scala:648:41]
wire _io_resp_must_alloc_T_1; // @[TLB.scala:649:51]
wire _io_resp_prefetchable_T_2; // @[TLB.scala:650:59]
wire _io_ptw_req_valid_T; // @[TLB.scala:662:29]
wire do_refill = io_ptw_resp_valid_0; // @[TLB.scala:318:7, :408:29]
wire newEntry_ae_ptw = io_ptw_resp_bits_ae_ptw_0; // @[TLB.scala:318:7, :449:24]
wire newEntry_ae_final = io_ptw_resp_bits_ae_final_0; // @[TLB.scala:318:7, :449:24]
wire newEntry_pf = io_ptw_resp_bits_pf_0; // @[TLB.scala:318:7, :449:24]
wire newEntry_gf = io_ptw_resp_bits_gf_0; // @[TLB.scala:318:7, :449:24]
wire newEntry_hr = io_ptw_resp_bits_hr_0; // @[TLB.scala:318:7, :449:24]
wire newEntry_hw = io_ptw_resp_bits_hw_0; // @[TLB.scala:318:7, :449:24]
wire newEntry_hx = io_ptw_resp_bits_hx_0; // @[TLB.scala:318:7, :449:24]
wire newEntry_u = io_ptw_resp_bits_pte_u_0; // @[TLB.scala:318:7, :449:24]
wire [1:0] _special_entry_level_T = io_ptw_resp_bits_level_0; // @[package.scala:163:13]
wire [3:0] satp_mode = io_ptw_ptbr_mode_0; // @[TLB.scala:318:7, :373:17]
wire [15:0] satp_asid = io_ptw_ptbr_asid_0; // @[TLB.scala:318:7, :373:17]
wire [43:0] satp_ppn = io_ptw_ptbr_ppn_0; // @[TLB.scala:318:7, :373:17]
wire mxr = io_ptw_status_mxr_0; // @[TLB.scala:318:7, :518:31]
wire sum = io_ptw_status_sum_0; // @[TLB.scala:318:7, :510:16]
wire io_req_ready_0; // @[TLB.scala:318:7]
wire io_resp_pf_ld_0; // @[TLB.scala:318:7]
wire io_resp_pf_st_0; // @[TLB.scala:318:7]
wire io_resp_pf_inst_0; // @[TLB.scala:318:7]
wire io_resp_ae_ld_0; // @[TLB.scala:318:7]
wire io_resp_ae_st_0; // @[TLB.scala:318:7]
wire io_resp_ae_inst_0; // @[TLB.scala:318:7]
wire io_resp_ma_ld_0; // @[TLB.scala:318:7]
wire io_resp_ma_st_0; // @[TLB.scala:318:7]
wire io_resp_miss_0; // @[TLB.scala:318:7]
wire [31:0] io_resp_paddr_0; // @[TLB.scala:318:7]
wire [39:0] io_resp_gpa_0; // @[TLB.scala:318:7]
wire io_resp_cacheable_0; // @[TLB.scala:318:7]
wire io_resp_must_alloc_0; // @[TLB.scala:318:7]
wire io_resp_prefetchable_0; // @[TLB.scala:318:7]
wire [26:0] io_ptw_req_bits_bits_addr_0; // @[TLB.scala:318:7]
wire io_ptw_req_bits_bits_need_gpa_0; // @[TLB.scala:318:7]
wire io_ptw_req_valid_0; // @[TLB.scala:318:7]
wire [26:0] vpn = io_req_bits_vaddr_0[38:12]; // @[TLB.scala:318:7, :335:30]
wire [26:0] _ppn_T_5 = vpn; // @[TLB.scala:198:28, :335:30]
wire [26:0] _ppn_T_13 = vpn; // @[TLB.scala:198:28, :335:30]
wire [26:0] _ppn_T_21 = vpn; // @[TLB.scala:198:28, :335:30]
wire [26:0] _ppn_T_29 = vpn; // @[TLB.scala:198:28, :335:30]
reg [1:0] sectored_entries_0_0_level; // @[TLB.scala:339:29]
reg [26:0] sectored_entries_0_0_tag_vpn; // @[TLB.scala:339:29]
reg sectored_entries_0_0_tag_v; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_0_data_0; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_0_data_1; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_0_data_2; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_0_data_3; // @[TLB.scala:339:29]
reg sectored_entries_0_0_valid_0; // @[TLB.scala:339:29]
reg sectored_entries_0_0_valid_1; // @[TLB.scala:339:29]
reg sectored_entries_0_0_valid_2; // @[TLB.scala:339:29]
reg sectored_entries_0_0_valid_3; // @[TLB.scala:339:29]
reg [1:0] sectored_entries_0_1_level; // @[TLB.scala:339:29]
reg [26:0] sectored_entries_0_1_tag_vpn; // @[TLB.scala:339:29]
reg sectored_entries_0_1_tag_v; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_1_data_0; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_1_data_1; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_1_data_2; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_1_data_3; // @[TLB.scala:339:29]
reg sectored_entries_0_1_valid_0; // @[TLB.scala:339:29]
reg sectored_entries_0_1_valid_1; // @[TLB.scala:339:29]
reg sectored_entries_0_1_valid_2; // @[TLB.scala:339:29]
reg sectored_entries_0_1_valid_3; // @[TLB.scala:339:29]
reg [1:0] sectored_entries_0_2_level; // @[TLB.scala:339:29]
reg [26:0] sectored_entries_0_2_tag_vpn; // @[TLB.scala:339:29]
reg sectored_entries_0_2_tag_v; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_2_data_0; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_2_data_1; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_2_data_2; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_2_data_3; // @[TLB.scala:339:29]
reg sectored_entries_0_2_valid_0; // @[TLB.scala:339:29]
reg sectored_entries_0_2_valid_1; // @[TLB.scala:339:29]
reg sectored_entries_0_2_valid_2; // @[TLB.scala:339:29]
reg sectored_entries_0_2_valid_3; // @[TLB.scala:339:29]
reg [1:0] sectored_entries_0_3_level; // @[TLB.scala:339:29]
reg [26:0] sectored_entries_0_3_tag_vpn; // @[TLB.scala:339:29]
reg sectored_entries_0_3_tag_v; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_3_data_0; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_3_data_1; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_3_data_2; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_3_data_3; // @[TLB.scala:339:29]
reg sectored_entries_0_3_valid_0; // @[TLB.scala:339:29]
reg sectored_entries_0_3_valid_1; // @[TLB.scala:339:29]
reg sectored_entries_0_3_valid_2; // @[TLB.scala:339:29]
reg sectored_entries_0_3_valid_3; // @[TLB.scala:339:29]
reg [1:0] sectored_entries_0_4_level; // @[TLB.scala:339:29]
reg [26:0] sectored_entries_0_4_tag_vpn; // @[TLB.scala:339:29]
reg sectored_entries_0_4_tag_v; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_4_data_0; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_4_data_1; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_4_data_2; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_4_data_3; // @[TLB.scala:339:29]
reg sectored_entries_0_4_valid_0; // @[TLB.scala:339:29]
reg sectored_entries_0_4_valid_1; // @[TLB.scala:339:29]
reg sectored_entries_0_4_valid_2; // @[TLB.scala:339:29]
reg sectored_entries_0_4_valid_3; // @[TLB.scala:339:29]
reg [1:0] sectored_entries_0_5_level; // @[TLB.scala:339:29]
reg [26:0] sectored_entries_0_5_tag_vpn; // @[TLB.scala:339:29]
reg sectored_entries_0_5_tag_v; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_5_data_0; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_5_data_1; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_5_data_2; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_5_data_3; // @[TLB.scala:339:29]
reg sectored_entries_0_5_valid_0; // @[TLB.scala:339:29]
reg sectored_entries_0_5_valid_1; // @[TLB.scala:339:29]
reg sectored_entries_0_5_valid_2; // @[TLB.scala:339:29]
reg sectored_entries_0_5_valid_3; // @[TLB.scala:339:29]
reg [1:0] sectored_entries_0_6_level; // @[TLB.scala:339:29]
reg [26:0] sectored_entries_0_6_tag_vpn; // @[TLB.scala:339:29]
reg sectored_entries_0_6_tag_v; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_6_data_0; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_6_data_1; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_6_data_2; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_6_data_3; // @[TLB.scala:339:29]
reg sectored_entries_0_6_valid_0; // @[TLB.scala:339:29]
reg sectored_entries_0_6_valid_1; // @[TLB.scala:339:29]
reg sectored_entries_0_6_valid_2; // @[TLB.scala:339:29]
reg sectored_entries_0_6_valid_3; // @[TLB.scala:339:29]
reg [1:0] sectored_entries_0_7_level; // @[TLB.scala:339:29]
reg [26:0] sectored_entries_0_7_tag_vpn; // @[TLB.scala:339:29]
reg sectored_entries_0_7_tag_v; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_7_data_0; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_7_data_1; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_7_data_2; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_7_data_3; // @[TLB.scala:339:29]
reg sectored_entries_0_7_valid_0; // @[TLB.scala:339:29]
reg sectored_entries_0_7_valid_1; // @[TLB.scala:339:29]
reg sectored_entries_0_7_valid_2; // @[TLB.scala:339:29]
reg sectored_entries_0_7_valid_3; // @[TLB.scala:339:29]
reg [1:0] superpage_entries_0_level; // @[TLB.scala:341:30]
reg [26:0] superpage_entries_0_tag_vpn; // @[TLB.scala:341:30]
reg superpage_entries_0_tag_v; // @[TLB.scala:341:30]
reg [41:0] superpage_entries_0_data_0; // @[TLB.scala:341:30]
wire [41:0] _entries_WIRE_17 = superpage_entries_0_data_0; // @[TLB.scala:170:77, :341:30]
reg superpage_entries_0_valid_0; // @[TLB.scala:341:30]
reg [1:0] superpage_entries_1_level; // @[TLB.scala:341:30]
reg [26:0] superpage_entries_1_tag_vpn; // @[TLB.scala:341:30]
reg superpage_entries_1_tag_v; // @[TLB.scala:341:30]
reg [41:0] superpage_entries_1_data_0; // @[TLB.scala:341:30]
wire [41:0] _entries_WIRE_19 = superpage_entries_1_data_0; // @[TLB.scala:170:77, :341:30]
reg superpage_entries_1_valid_0; // @[TLB.scala:341:30]
reg [1:0] superpage_entries_2_level; // @[TLB.scala:341:30]
reg [26:0] superpage_entries_2_tag_vpn; // @[TLB.scala:341:30]
reg superpage_entries_2_tag_v; // @[TLB.scala:341:30]
reg [41:0] superpage_entries_2_data_0; // @[TLB.scala:341:30]
wire [41:0] _entries_WIRE_21 = superpage_entries_2_data_0; // @[TLB.scala:170:77, :341:30]
reg superpage_entries_2_valid_0; // @[TLB.scala:341:30]
reg [1:0] superpage_entries_3_level; // @[TLB.scala:341:30]
reg [26:0] superpage_entries_3_tag_vpn; // @[TLB.scala:341:30]
reg superpage_entries_3_tag_v; // @[TLB.scala:341:30]
reg [41:0] superpage_entries_3_data_0; // @[TLB.scala:341:30]
wire [41:0] _entries_WIRE_23 = superpage_entries_3_data_0; // @[TLB.scala:170:77, :341:30]
reg superpage_entries_3_valid_0; // @[TLB.scala:341:30]
reg [1:0] special_entry_level; // @[TLB.scala:346:56]
reg [26:0] special_entry_tag_vpn; // @[TLB.scala:346:56]
reg special_entry_tag_v; // @[TLB.scala:346:56]
reg [41:0] special_entry_data_0; // @[TLB.scala:346:56]
wire [41:0] _mpu_ppn_WIRE_1 = special_entry_data_0; // @[TLB.scala:170:77, :346:56]
wire [41:0] _entries_WIRE_25 = special_entry_data_0; // @[TLB.scala:170:77, :346:56]
reg special_entry_valid_0; // @[TLB.scala:346:56]
reg [1:0] state; // @[TLB.scala:352:22]
reg [26:0] r_refill_tag; // @[TLB.scala:354:25]
assign io_ptw_req_bits_bits_addr_0 = r_refill_tag; // @[TLB.scala:318:7, :354:25]
reg [1:0] r_superpage_repl_addr; // @[TLB.scala:355:34]
wire [1:0] waddr = r_superpage_repl_addr; // @[TLB.scala:355:34, :477:22]
reg [2:0] r_sectored_repl_addr; // @[TLB.scala:356:33]
reg r_sectored_hit_valid; // @[TLB.scala:357:27]
reg [2:0] r_sectored_hit_bits; // @[TLB.scala:357:27]
reg r_superpage_hit_valid; // @[TLB.scala:358:28]
reg [1:0] r_superpage_hit_bits; // @[TLB.scala:358:28]
reg r_need_gpa; // @[TLB.scala:361:23]
assign io_ptw_req_bits_bits_need_gpa_0 = r_need_gpa; // @[TLB.scala:318:7, :361:23]
reg r_gpa_valid; // @[TLB.scala:362:24]
reg [38:0] r_gpa; // @[TLB.scala:363:18]
reg [26:0] r_gpa_vpn; // @[TLB.scala:364:22]
reg r_gpa_is_pte; // @[TLB.scala:365:25]
wire priv_s = io_req_bits_prv_0[0]; // @[TLB.scala:318:7, :370:20]
wire priv_uses_vm = ~(io_req_bits_prv_0[1]); // @[TLB.scala:318:7, :372:27]
wire _stage1_en_T = satp_mode[3]; // @[TLB.scala:373:17, :374:41]
wire stage1_en = _stage1_en_T; // @[TLB.scala:374:{29,41}]
wire _vm_enabled_T = stage1_en; // @[TLB.scala:374:29, :399:31]
wire _vm_enabled_T_1 = _vm_enabled_T & priv_uses_vm; // @[TLB.scala:372:27, :399:{31,45}]
wire _vm_enabled_T_2 = ~io_req_bits_passthrough_0; // @[TLB.scala:318:7, :399:64]
wire vm_enabled = _vm_enabled_T_1 & _vm_enabled_T_2; // @[TLB.scala:399:{45,61,64}]
wire _mpu_ppn_T = vm_enabled; // @[TLB.scala:399:61, :413:32]
wire _tlb_miss_T_1 = vm_enabled; // @[TLB.scala:399:61, :613:29]
wire _vsatp_mode_mismatch_T_2 = ~io_req_bits_passthrough_0; // @[TLB.scala:318:7, :399:64, :403:81]
wire [19:0] refill_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[TLB.scala:318:7, :406:44]
wire [19:0] newEntry_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[TLB.scala:318:7, :406:44, :449:24]
wire _io_resp_miss_T = do_refill; // @[TLB.scala:408:29, :651:29]
wire _T_51 = state == 2'h1; // @[package.scala:16:47]
wire _invalidate_refill_T; // @[package.scala:16:47]
assign _invalidate_refill_T = _T_51; // @[package.scala:16:47]
assign _io_ptw_req_valid_T = _T_51; // @[package.scala:16:47]
wire _invalidate_refill_T_1 = &state; // @[package.scala:16:47]
wire _invalidate_refill_T_2 = _invalidate_refill_T | _invalidate_refill_T_1; // @[package.scala:16:47, :81:59]
wire invalidate_refill = _invalidate_refill_T_2 | io_sfence_valid_0; // @[package.scala:81:59]
wire [19:0] _mpu_ppn_T_23; // @[TLB.scala:170:77]
wire _mpu_ppn_T_22; // @[TLB.scala:170:77]
wire _mpu_ppn_T_21; // @[TLB.scala:170:77]
wire _mpu_ppn_T_20; // @[TLB.scala:170:77]
wire _mpu_ppn_T_19; // @[TLB.scala:170:77]
wire _mpu_ppn_T_18; // @[TLB.scala:170:77]
wire _mpu_ppn_T_17; // @[TLB.scala:170:77]
wire _mpu_ppn_T_16; // @[TLB.scala:170:77]
wire _mpu_ppn_T_15; // @[TLB.scala:170:77]
wire _mpu_ppn_T_14; // @[TLB.scala:170:77]
wire _mpu_ppn_T_13; // @[TLB.scala:170:77]
wire _mpu_ppn_T_12; // @[TLB.scala:170:77]
wire _mpu_ppn_T_11; // @[TLB.scala:170:77]
wire _mpu_ppn_T_10; // @[TLB.scala:170:77]
wire _mpu_ppn_T_9; // @[TLB.scala:170:77]
wire _mpu_ppn_T_8; // @[TLB.scala:170:77]
wire _mpu_ppn_T_7; // @[TLB.scala:170:77]
wire _mpu_ppn_T_6; // @[TLB.scala:170:77]
wire _mpu_ppn_T_5; // @[TLB.scala:170:77]
wire _mpu_ppn_T_4; // @[TLB.scala:170:77]
wire _mpu_ppn_T_3; // @[TLB.scala:170:77]
wire _mpu_ppn_T_2; // @[TLB.scala:170:77]
wire _mpu_ppn_T_1; // @[TLB.scala:170:77]
assign _mpu_ppn_T_1 = _mpu_ppn_WIRE_1[0]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_fragmented_superpage = _mpu_ppn_T_1; // @[TLB.scala:170:77]
assign _mpu_ppn_T_2 = _mpu_ppn_WIRE_1[1]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_c = _mpu_ppn_T_2; // @[TLB.scala:170:77]
assign _mpu_ppn_T_3 = _mpu_ppn_WIRE_1[2]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_eff = _mpu_ppn_T_3; // @[TLB.scala:170:77]
assign _mpu_ppn_T_4 = _mpu_ppn_WIRE_1[3]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_paa = _mpu_ppn_T_4; // @[TLB.scala:170:77]
assign _mpu_ppn_T_5 = _mpu_ppn_WIRE_1[4]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_pal = _mpu_ppn_T_5; // @[TLB.scala:170:77]
assign _mpu_ppn_T_6 = _mpu_ppn_WIRE_1[5]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_ppp = _mpu_ppn_T_6; // @[TLB.scala:170:77]
assign _mpu_ppn_T_7 = _mpu_ppn_WIRE_1[6]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_pr = _mpu_ppn_T_7; // @[TLB.scala:170:77]
assign _mpu_ppn_T_8 = _mpu_ppn_WIRE_1[7]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_px = _mpu_ppn_T_8; // @[TLB.scala:170:77]
assign _mpu_ppn_T_9 = _mpu_ppn_WIRE_1[8]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_pw = _mpu_ppn_T_9; // @[TLB.scala:170:77]
assign _mpu_ppn_T_10 = _mpu_ppn_WIRE_1[9]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_hr = _mpu_ppn_T_10; // @[TLB.scala:170:77]
assign _mpu_ppn_T_11 = _mpu_ppn_WIRE_1[10]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_hx = _mpu_ppn_T_11; // @[TLB.scala:170:77]
assign _mpu_ppn_T_12 = _mpu_ppn_WIRE_1[11]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_hw = _mpu_ppn_T_12; // @[TLB.scala:170:77]
assign _mpu_ppn_T_13 = _mpu_ppn_WIRE_1[12]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_sr = _mpu_ppn_T_13; // @[TLB.scala:170:77]
assign _mpu_ppn_T_14 = _mpu_ppn_WIRE_1[13]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_sx = _mpu_ppn_T_14; // @[TLB.scala:170:77]
assign _mpu_ppn_T_15 = _mpu_ppn_WIRE_1[14]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_sw = _mpu_ppn_T_15; // @[TLB.scala:170:77]
assign _mpu_ppn_T_16 = _mpu_ppn_WIRE_1[15]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_gf = _mpu_ppn_T_16; // @[TLB.scala:170:77]
assign _mpu_ppn_T_17 = _mpu_ppn_WIRE_1[16]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_pf = _mpu_ppn_T_17; // @[TLB.scala:170:77]
assign _mpu_ppn_T_18 = _mpu_ppn_WIRE_1[17]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_ae_stage2 = _mpu_ppn_T_18; // @[TLB.scala:170:77]
assign _mpu_ppn_T_19 = _mpu_ppn_WIRE_1[18]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_ae_final = _mpu_ppn_T_19; // @[TLB.scala:170:77]
assign _mpu_ppn_T_20 = _mpu_ppn_WIRE_1[19]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_ae_ptw = _mpu_ppn_T_20; // @[TLB.scala:170:77]
assign _mpu_ppn_T_21 = _mpu_ppn_WIRE_1[20]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_g = _mpu_ppn_T_21; // @[TLB.scala:170:77]
assign _mpu_ppn_T_22 = _mpu_ppn_WIRE_1[21]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_u = _mpu_ppn_T_22; // @[TLB.scala:170:77]
assign _mpu_ppn_T_23 = _mpu_ppn_WIRE_1[41:22]; // @[TLB.scala:170:77]
wire [19:0] _mpu_ppn_WIRE_ppn = _mpu_ppn_T_23; // @[TLB.scala:170:77]
wire [1:0] mpu_ppn_res = _mpu_ppn_barrier_io_y_ppn[19:18]; // @[package.scala:267:25]
wire _GEN = special_entry_level == 2'h0; // @[TLB.scala:197:28, :346:56]
wire _mpu_ppn_ignore_T; // @[TLB.scala:197:28]
assign _mpu_ppn_ignore_T = _GEN; // @[TLB.scala:197:28]
wire _hitsVec_ignore_T_13; // @[TLB.scala:182:28]
assign _hitsVec_ignore_T_13 = _GEN; // @[TLB.scala:182:28, :197:28]
wire _ppn_ignore_T_8; // @[TLB.scala:197:28]
assign _ppn_ignore_T_8 = _GEN; // @[TLB.scala:197:28]
wire _ignore_T_13; // @[TLB.scala:182:28]
assign _ignore_T_13 = _GEN; // @[TLB.scala:182:28, :197:28]
wire mpu_ppn_ignore = _mpu_ppn_ignore_T; // @[TLB.scala:197:{28,34}]
wire [26:0] _mpu_ppn_T_24 = mpu_ppn_ignore ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30]
wire [26:0] _mpu_ppn_T_25 = {_mpu_ppn_T_24[26:20], _mpu_ppn_T_24[19:0] | _mpu_ppn_barrier_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _mpu_ppn_T_26 = _mpu_ppn_T_25[17:9]; // @[TLB.scala:198:{47,58}]
wire [10:0] _mpu_ppn_T_27 = {mpu_ppn_res, _mpu_ppn_T_26}; // @[TLB.scala:195:26, :198:{18,58}]
wire _mpu_ppn_ignore_T_1 = ~(special_entry_level[1]); // @[TLB.scala:197:28, :346:56]
wire mpu_ppn_ignore_1 = _mpu_ppn_ignore_T_1; // @[TLB.scala:197:{28,34}]
wire [26:0] _mpu_ppn_T_28 = mpu_ppn_ignore_1 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30]
wire [26:0] _mpu_ppn_T_29 = {_mpu_ppn_T_28[26:20], _mpu_ppn_T_28[19:0] | _mpu_ppn_barrier_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _mpu_ppn_T_30 = _mpu_ppn_T_29[8:0]; // @[TLB.scala:198:{47,58}]
wire [19:0] _mpu_ppn_T_31 = {_mpu_ppn_T_27, _mpu_ppn_T_30}; // @[TLB.scala:198:{18,58}]
wire [27:0] _mpu_ppn_T_32 = io_req_bits_vaddr_0[39:12]; // @[TLB.scala:318:7, :413:146]
wire [27:0] _mpu_ppn_T_33 = _mpu_ppn_T ? {8'h0, _mpu_ppn_T_31} : _mpu_ppn_T_32; // @[TLB.scala:198:18, :413:{20,32,146}]
wire [27:0] mpu_ppn = do_refill ? {8'h0, refill_ppn} : _mpu_ppn_T_33; // @[TLB.scala:406:44, :408:29, :412:20, :413:20]
wire [11:0] _mpu_physaddr_T = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52]
wire [11:0] _io_resp_paddr_T = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52, :652:46]
wire [11:0] _io_resp_gpa_offset_T_1 = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52, :658:82]
wire [39:0] mpu_physaddr = {mpu_ppn, _mpu_physaddr_T}; // @[TLB.scala:412:20, :414:{25,52}]
wire [39:0] _homogeneous_T = mpu_physaddr; // @[TLB.scala:414:25]
wire [39:0] _homogeneous_T_79 = mpu_physaddr; // @[TLB.scala:414:25]
wire [39:0] _deny_access_to_debug_T_1 = mpu_physaddr; // @[TLB.scala:414:25]
wire _mpu_priv_T = do_refill | io_req_bits_passthrough_0; // @[TLB.scala:318:7, :408:29, :415:52]
wire _mpu_priv_T_1 = _mpu_priv_T; // @[TLB.scala:415:{38,52}]
wire [2:0] _mpu_priv_T_2 = {io_ptw_status_debug_0, io_req_bits_prv_0}; // @[TLB.scala:318:7, :415:103]
wire [2:0] mpu_priv = _mpu_priv_T_1 ? 3'h1 : _mpu_priv_T_2; // @[TLB.scala:415:{27,38,103}]
wire cacheable; // @[TLB.scala:425:41]
wire newEntry_c = cacheable; // @[TLB.scala:425:41, :449:24]
wire [40:0] _homogeneous_T_1 = {1'h0, _homogeneous_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_2 = _homogeneous_T_1 & 41'h1FFFFFFE000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_3 = _homogeneous_T_2; // @[Parameters.scala:137:46]
wire _homogeneous_T_4 = _homogeneous_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_60 = _homogeneous_T_4; // @[TLBPermissions.scala:101:65]
wire [39:0] _GEN_0 = {mpu_physaddr[39:14], mpu_physaddr[13:0] ^ 14'h3000}; // @[TLB.scala:414:25]
wire [39:0] _homogeneous_T_5; // @[Parameters.scala:137:31]
assign _homogeneous_T_5 = _GEN_0; // @[Parameters.scala:137:31]
wire [39:0] _homogeneous_T_84; // @[Parameters.scala:137:31]
assign _homogeneous_T_84 = _GEN_0; // @[Parameters.scala:137:31]
wire [40:0] _homogeneous_T_6 = {1'h0, _homogeneous_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_7 = _homogeneous_T_6 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_8 = _homogeneous_T_7; // @[Parameters.scala:137:46]
wire _homogeneous_T_9 = _homogeneous_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _GEN_1 = {mpu_physaddr[39:17], mpu_physaddr[16:0] ^ 17'h10000}; // @[TLB.scala:414:25]
wire [39:0] _homogeneous_T_10; // @[Parameters.scala:137:31]
assign _homogeneous_T_10 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _homogeneous_T_72; // @[Parameters.scala:137:31]
assign _homogeneous_T_72 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _homogeneous_T_89; // @[Parameters.scala:137:31]
assign _homogeneous_T_89 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _homogeneous_T_121; // @[Parameters.scala:137:31]
assign _homogeneous_T_121 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _homogeneous_T_128; // @[Parameters.scala:137:31]
assign _homogeneous_T_128 = _GEN_1; // @[Parameters.scala:137:31]
wire [40:0] _homogeneous_T_11 = {1'h0, _homogeneous_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_12 = _homogeneous_T_11 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_13 = _homogeneous_T_12; // @[Parameters.scala:137:46]
wire _homogeneous_T_14 = _homogeneous_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _homogeneous_T_15 = {mpu_physaddr[39:18], mpu_physaddr[17:0] ^ 18'h20000}; // @[TLB.scala:414:25]
wire [40:0] _homogeneous_T_16 = {1'h0, _homogeneous_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_17 = _homogeneous_T_16 & 41'h1FFFFFFC000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_18 = _homogeneous_T_17; // @[Parameters.scala:137:46]
wire _homogeneous_T_19 = _homogeneous_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _homogeneous_T_20 = {mpu_physaddr[39:18], mpu_physaddr[17:0] ^ 18'h24000}; // @[TLB.scala:414:25]
wire [40:0] _homogeneous_T_21 = {1'h0, _homogeneous_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_22 = _homogeneous_T_21 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_23 = _homogeneous_T_22; // @[Parameters.scala:137:46]
wire _homogeneous_T_24 = _homogeneous_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _homogeneous_T_25 = {mpu_physaddr[39:21], mpu_physaddr[20:0] ^ 21'h100000}; // @[TLB.scala:414:25]
wire [40:0] _homogeneous_T_26 = {1'h0, _homogeneous_T_25}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_27 = _homogeneous_T_26 & 41'h1FFFFFEF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_28 = _homogeneous_T_27; // @[Parameters.scala:137:46]
wire _homogeneous_T_29 = _homogeneous_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _homogeneous_T_30 = {mpu_physaddr[39:26], mpu_physaddr[25:0] ^ 26'h2000000}; // @[TLB.scala:414:25]
wire [40:0] _homogeneous_T_31 = {1'h0, _homogeneous_T_30}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_32 = _homogeneous_T_31 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_33 = _homogeneous_T_32; // @[Parameters.scala:137:46]
wire _homogeneous_T_34 = _homogeneous_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _homogeneous_T_35 = {mpu_physaddr[39:26], mpu_physaddr[25:0] ^ 26'h2010000}; // @[TLB.scala:414:25]
wire [40:0] _homogeneous_T_36 = {1'h0, _homogeneous_T_35}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_37 = _homogeneous_T_36 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_38 = _homogeneous_T_37; // @[Parameters.scala:137:46]
wire _homogeneous_T_39 = _homogeneous_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _GEN_2 = {mpu_physaddr[39:28], mpu_physaddr[27:0] ^ 28'h8000000}; // @[TLB.scala:414:25]
wire [39:0] _homogeneous_T_40; // @[Parameters.scala:137:31]
assign _homogeneous_T_40 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _homogeneous_T_94; // @[Parameters.scala:137:31]
assign _homogeneous_T_94 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _homogeneous_T_109; // @[Parameters.scala:137:31]
assign _homogeneous_T_109 = _GEN_2; // @[Parameters.scala:137:31]
wire [40:0] _homogeneous_T_41 = {1'h0, _homogeneous_T_40}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_42 = _homogeneous_T_41 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_43 = _homogeneous_T_42; // @[Parameters.scala:137:46]
wire _homogeneous_T_44 = _homogeneous_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _homogeneous_T_45 = {mpu_physaddr[39:28], mpu_physaddr[27:0] ^ 28'hC000000}; // @[TLB.scala:414:25]
wire [40:0] _homogeneous_T_46 = {1'h0, _homogeneous_T_45}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_47 = _homogeneous_T_46 & 41'h1FFFC000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_48 = _homogeneous_T_47; // @[Parameters.scala:137:46]
wire _homogeneous_T_49 = _homogeneous_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _homogeneous_T_50 = {mpu_physaddr[39:29], mpu_physaddr[28:0] ^ 29'h10020000}; // @[TLB.scala:414:25]
wire [40:0] _homogeneous_T_51 = {1'h0, _homogeneous_T_50}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_52 = _homogeneous_T_51 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_53 = _homogeneous_T_52; // @[Parameters.scala:137:46]
wire _homogeneous_T_54 = _homogeneous_T_53 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _GEN_3 = {mpu_physaddr[39:32], mpu_physaddr[31:0] ^ 32'h80000000}; // @[TLB.scala:414:25, :417:15]
wire [39:0] _homogeneous_T_55; // @[Parameters.scala:137:31]
assign _homogeneous_T_55 = _GEN_3; // @[Parameters.scala:137:31]
wire [39:0] _homogeneous_T_99; // @[Parameters.scala:137:31]
assign _homogeneous_T_99 = _GEN_3; // @[Parameters.scala:137:31]
wire [39:0] _homogeneous_T_114; // @[Parameters.scala:137:31]
assign _homogeneous_T_114 = _GEN_3; // @[Parameters.scala:137:31]
wire [40:0] _homogeneous_T_56 = {1'h0, _homogeneous_T_55}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_57 = _homogeneous_T_56 & 41'h1FFF0000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_58 = _homogeneous_T_57; // @[Parameters.scala:137:46]
wire _homogeneous_T_59 = _homogeneous_T_58 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_61 = _homogeneous_T_60 | _homogeneous_T_9; // @[TLBPermissions.scala:101:65]
wire _homogeneous_T_62 = _homogeneous_T_61 | _homogeneous_T_14; // @[TLBPermissions.scala:101:65]
wire _homogeneous_T_63 = _homogeneous_T_62 | _homogeneous_T_19; // @[TLBPermissions.scala:101:65]
wire _homogeneous_T_64 = _homogeneous_T_63 | _homogeneous_T_24; // @[TLBPermissions.scala:101:65]
wire _homogeneous_T_65 = _homogeneous_T_64 | _homogeneous_T_29; // @[TLBPermissions.scala:101:65]
wire _homogeneous_T_66 = _homogeneous_T_65 | _homogeneous_T_34; // @[TLBPermissions.scala:101:65]
wire _homogeneous_T_67 = _homogeneous_T_66 | _homogeneous_T_39; // @[TLBPermissions.scala:101:65]
wire _homogeneous_T_68 = _homogeneous_T_67 | _homogeneous_T_44; // @[TLBPermissions.scala:101:65]
wire _homogeneous_T_69 = _homogeneous_T_68 | _homogeneous_T_49; // @[TLBPermissions.scala:101:65]
wire _homogeneous_T_70 = _homogeneous_T_69 | _homogeneous_T_54; // @[TLBPermissions.scala:101:65]
wire homogeneous = _homogeneous_T_70 | _homogeneous_T_59; // @[TLBPermissions.scala:101:65]
wire [40:0] _homogeneous_T_73 = {1'h0, _homogeneous_T_72}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_74 = _homogeneous_T_73 & 41'h8A130000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_75 = _homogeneous_T_74; // @[Parameters.scala:137:46]
wire _homogeneous_T_76 = _homogeneous_T_75 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_77 = _homogeneous_T_76; // @[TLBPermissions.scala:87:66]
wire _homogeneous_T_78 = ~_homogeneous_T_77; // @[TLBPermissions.scala:87:{22,66}]
wire [40:0] _homogeneous_T_80 = {1'h0, _homogeneous_T_79}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_81 = _homogeneous_T_80 & 41'hFFFF3000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_82 = _homogeneous_T_81; // @[Parameters.scala:137:46]
wire _homogeneous_T_83 = _homogeneous_T_82 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_104 = _homogeneous_T_83; // @[TLBPermissions.scala:85:66]
wire [40:0] _homogeneous_T_85 = {1'h0, _homogeneous_T_84}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_86 = _homogeneous_T_85 & 41'hFFFF3000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_87 = _homogeneous_T_86; // @[Parameters.scala:137:46]
wire _homogeneous_T_88 = _homogeneous_T_87 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _homogeneous_T_90 = {1'h0, _homogeneous_T_89}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_91 = _homogeneous_T_90 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_92 = _homogeneous_T_91; // @[Parameters.scala:137:46]
wire _homogeneous_T_93 = _homogeneous_T_92 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _homogeneous_T_95 = {1'h0, _homogeneous_T_94}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_96 = _homogeneous_T_95 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_97 = _homogeneous_T_96; // @[Parameters.scala:137:46]
wire _homogeneous_T_98 = _homogeneous_T_97 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _homogeneous_T_100 = {1'h0, _homogeneous_T_99}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_101 = _homogeneous_T_100 & 41'hF0000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_102 = _homogeneous_T_101; // @[Parameters.scala:137:46]
wire _homogeneous_T_103 = _homogeneous_T_102 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_105 = _homogeneous_T_104 | _homogeneous_T_88; // @[TLBPermissions.scala:85:66]
wire _homogeneous_T_106 = _homogeneous_T_105 | _homogeneous_T_93; // @[TLBPermissions.scala:85:66]
wire _homogeneous_T_107 = _homogeneous_T_106 | _homogeneous_T_98; // @[TLBPermissions.scala:85:66]
wire _homogeneous_T_108 = _homogeneous_T_107 | _homogeneous_T_103; // @[TLBPermissions.scala:85:66]
wire [40:0] _homogeneous_T_110 = {1'h0, _homogeneous_T_109}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_111 = _homogeneous_T_110 & 41'h8E020000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_112 = _homogeneous_T_111; // @[Parameters.scala:137:46]
wire _homogeneous_T_113 = _homogeneous_T_112 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_119 = _homogeneous_T_113; // @[TLBPermissions.scala:85:66]
wire [40:0] _homogeneous_T_115 = {1'h0, _homogeneous_T_114}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_116 = _homogeneous_T_115 & 41'h80000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_117 = _homogeneous_T_116; // @[Parameters.scala:137:46]
wire _homogeneous_T_118 = _homogeneous_T_117 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_120 = _homogeneous_T_119 | _homogeneous_T_118; // @[TLBPermissions.scala:85:66]
wire [40:0] _homogeneous_T_122 = {1'h0, _homogeneous_T_121}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_123 = _homogeneous_T_122 & 41'h8A130000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_124 = _homogeneous_T_123; // @[Parameters.scala:137:46]
wire _homogeneous_T_125 = _homogeneous_T_124 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_126 = _homogeneous_T_125; // @[TLBPermissions.scala:87:66]
wire _homogeneous_T_127 = ~_homogeneous_T_126; // @[TLBPermissions.scala:87:{22,66}]
wire [40:0] _homogeneous_T_129 = {1'h0, _homogeneous_T_128}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_130 = _homogeneous_T_129 & 41'h8A130000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_131 = _homogeneous_T_130; // @[Parameters.scala:137:46]
wire _homogeneous_T_132 = _homogeneous_T_131 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_133 = _homogeneous_T_132; // @[TLBPermissions.scala:87:66]
wire _homogeneous_T_134 = ~_homogeneous_T_133; // @[TLBPermissions.scala:87:{22,66}]
wire _deny_access_to_debug_T = ~(mpu_priv[2]); // @[TLB.scala:415:27, :428:39]
wire [40:0] _deny_access_to_debug_T_2 = {1'h0, _deny_access_to_debug_T_1}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _deny_access_to_debug_T_3 = _deny_access_to_debug_T_2 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _deny_access_to_debug_T_4 = _deny_access_to_debug_T_3; // @[Parameters.scala:137:46]
wire _deny_access_to_debug_T_5 = _deny_access_to_debug_T_4 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire deny_access_to_debug = _deny_access_to_debug_T & _deny_access_to_debug_T_5; // @[TLB.scala:428:{39,50}]
wire _prot_r_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33]
wire _prot_r_T_1 = _pma_io_resp_r & _prot_r_T; // @[TLB.scala:422:19, :429:{30,33}]
wire prot_r = _prot_r_T_1; // @[TLB.scala:429:{30,55}]
wire newEntry_pr = prot_r; // @[TLB.scala:429:55, :449:24]
wire _prot_w_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :430:33]
wire _prot_w_T_1 = _pma_io_resp_w & _prot_w_T; // @[TLB.scala:422:19, :430:{30,33}]
wire prot_w = _prot_w_T_1; // @[TLB.scala:430:{30,55}]
wire newEntry_pw = prot_w; // @[TLB.scala:430:55, :449:24]
wire _prot_x_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :434:33]
wire _prot_x_T_1 = _pma_io_resp_x & _prot_x_T; // @[TLB.scala:422:19, :434:{30,33}]
wire prot_x = _prot_x_T_1; // @[TLB.scala:434:{30,55}]
wire newEntry_px = prot_x; // @[TLB.scala:434:55, :449:24]
wire _GEN_4 = sectored_entries_0_0_valid_0 | sectored_entries_0_0_valid_1; // @[package.scala:81:59]
wire _sector_hits_T; // @[package.scala:81:59]
assign _sector_hits_T = _GEN_4; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T; // @[package.scala:81:59]
assign _r_sectored_repl_addr_valids_T = _GEN_4; // @[package.scala:81:59]
wire _sector_hits_T_1 = _sector_hits_T | sectored_entries_0_0_valid_2; // @[package.scala:81:59]
wire _sector_hits_T_2 = _sector_hits_T_1 | sectored_entries_0_0_valid_3; // @[package.scala:81:59]
wire [26:0] _T_176 = sectored_entries_0_0_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29]
wire [26:0] _sector_hits_T_3; // @[TLB.scala:174:61]
assign _sector_hits_T_3 = _T_176; // @[TLB.scala:174:61]
wire [26:0] _hitsVec_T; // @[TLB.scala:174:61]
assign _hitsVec_T = _T_176; // @[TLB.scala:174:61]
wire [24:0] _sector_hits_T_4 = _sector_hits_T_3[26:2]; // @[TLB.scala:174:{61,68}]
wire _sector_hits_T_5 = _sector_hits_T_4 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _sector_hits_T_6 = ~sectored_entries_0_0_tag_v; // @[TLB.scala:174:105, :339:29]
wire _sector_hits_T_7 = _sector_hits_T_5 & _sector_hits_T_6; // @[TLB.scala:174:{86,95,105}]
wire sector_hits_0 = _sector_hits_T_2 & _sector_hits_T_7; // @[package.scala:81:59]
wire _GEN_5 = sectored_entries_0_1_valid_0 | sectored_entries_0_1_valid_1; // @[package.scala:81:59]
wire _sector_hits_T_8; // @[package.scala:81:59]
assign _sector_hits_T_8 = _GEN_5; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_3; // @[package.scala:81:59]
assign _r_sectored_repl_addr_valids_T_3 = _GEN_5; // @[package.scala:81:59]
wire _sector_hits_T_9 = _sector_hits_T_8 | sectored_entries_0_1_valid_2; // @[package.scala:81:59]
wire _sector_hits_T_10 = _sector_hits_T_9 | sectored_entries_0_1_valid_3; // @[package.scala:81:59]
wire [26:0] _T_597 = sectored_entries_0_1_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29]
wire [26:0] _sector_hits_T_11; // @[TLB.scala:174:61]
assign _sector_hits_T_11 = _T_597; // @[TLB.scala:174:61]
wire [26:0] _hitsVec_T_6; // @[TLB.scala:174:61]
assign _hitsVec_T_6 = _T_597; // @[TLB.scala:174:61]
wire [24:0] _sector_hits_T_12 = _sector_hits_T_11[26:2]; // @[TLB.scala:174:{61,68}]
wire _sector_hits_T_13 = _sector_hits_T_12 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _sector_hits_T_14 = ~sectored_entries_0_1_tag_v; // @[TLB.scala:174:105, :339:29]
wire _sector_hits_T_15 = _sector_hits_T_13 & _sector_hits_T_14; // @[TLB.scala:174:{86,95,105}]
wire sector_hits_1 = _sector_hits_T_10 & _sector_hits_T_15; // @[package.scala:81:59]
wire _GEN_6 = sectored_entries_0_2_valid_0 | sectored_entries_0_2_valid_1; // @[package.scala:81:59]
wire _sector_hits_T_16; // @[package.scala:81:59]
assign _sector_hits_T_16 = _GEN_6; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_6; // @[package.scala:81:59]
assign _r_sectored_repl_addr_valids_T_6 = _GEN_6; // @[package.scala:81:59]
wire _sector_hits_T_17 = _sector_hits_T_16 | sectored_entries_0_2_valid_2; // @[package.scala:81:59]
wire _sector_hits_T_18 = _sector_hits_T_17 | sectored_entries_0_2_valid_3; // @[package.scala:81:59]
wire [26:0] _T_1018 = sectored_entries_0_2_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29]
wire [26:0] _sector_hits_T_19; // @[TLB.scala:174:61]
assign _sector_hits_T_19 = _T_1018; // @[TLB.scala:174:61]
wire [26:0] _hitsVec_T_12; // @[TLB.scala:174:61]
assign _hitsVec_T_12 = _T_1018; // @[TLB.scala:174:61]
wire [24:0] _sector_hits_T_20 = _sector_hits_T_19[26:2]; // @[TLB.scala:174:{61,68}]
wire _sector_hits_T_21 = _sector_hits_T_20 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _sector_hits_T_22 = ~sectored_entries_0_2_tag_v; // @[TLB.scala:174:105, :339:29]
wire _sector_hits_T_23 = _sector_hits_T_21 & _sector_hits_T_22; // @[TLB.scala:174:{86,95,105}]
wire sector_hits_2 = _sector_hits_T_18 & _sector_hits_T_23; // @[package.scala:81:59]
wire _GEN_7 = sectored_entries_0_3_valid_0 | sectored_entries_0_3_valid_1; // @[package.scala:81:59]
wire _sector_hits_T_24; // @[package.scala:81:59]
assign _sector_hits_T_24 = _GEN_7; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_9; // @[package.scala:81:59]
assign _r_sectored_repl_addr_valids_T_9 = _GEN_7; // @[package.scala:81:59]
wire _sector_hits_T_25 = _sector_hits_T_24 | sectored_entries_0_3_valid_2; // @[package.scala:81:59]
wire _sector_hits_T_26 = _sector_hits_T_25 | sectored_entries_0_3_valid_3; // @[package.scala:81:59]
wire [26:0] _T_1439 = sectored_entries_0_3_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29]
wire [26:0] _sector_hits_T_27; // @[TLB.scala:174:61]
assign _sector_hits_T_27 = _T_1439; // @[TLB.scala:174:61]
wire [26:0] _hitsVec_T_18; // @[TLB.scala:174:61]
assign _hitsVec_T_18 = _T_1439; // @[TLB.scala:174:61]
wire [24:0] _sector_hits_T_28 = _sector_hits_T_27[26:2]; // @[TLB.scala:174:{61,68}]
wire _sector_hits_T_29 = _sector_hits_T_28 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _sector_hits_T_30 = ~sectored_entries_0_3_tag_v; // @[TLB.scala:174:105, :339:29]
wire _sector_hits_T_31 = _sector_hits_T_29 & _sector_hits_T_30; // @[TLB.scala:174:{86,95,105}]
wire sector_hits_3 = _sector_hits_T_26 & _sector_hits_T_31; // @[package.scala:81:59]
wire _GEN_8 = sectored_entries_0_4_valid_0 | sectored_entries_0_4_valid_1; // @[package.scala:81:59]
wire _sector_hits_T_32; // @[package.scala:81:59]
assign _sector_hits_T_32 = _GEN_8; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_12; // @[package.scala:81:59]
assign _r_sectored_repl_addr_valids_T_12 = _GEN_8; // @[package.scala:81:59]
wire _sector_hits_T_33 = _sector_hits_T_32 | sectored_entries_0_4_valid_2; // @[package.scala:81:59]
wire _sector_hits_T_34 = _sector_hits_T_33 | sectored_entries_0_4_valid_3; // @[package.scala:81:59]
wire [26:0] _T_1860 = sectored_entries_0_4_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29]
wire [26:0] _sector_hits_T_35; // @[TLB.scala:174:61]
assign _sector_hits_T_35 = _T_1860; // @[TLB.scala:174:61]
wire [26:0] _hitsVec_T_24; // @[TLB.scala:174:61]
assign _hitsVec_T_24 = _T_1860; // @[TLB.scala:174:61]
wire [24:0] _sector_hits_T_36 = _sector_hits_T_35[26:2]; // @[TLB.scala:174:{61,68}]
wire _sector_hits_T_37 = _sector_hits_T_36 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _sector_hits_T_38 = ~sectored_entries_0_4_tag_v; // @[TLB.scala:174:105, :339:29]
wire _sector_hits_T_39 = _sector_hits_T_37 & _sector_hits_T_38; // @[TLB.scala:174:{86,95,105}]
wire sector_hits_4 = _sector_hits_T_34 & _sector_hits_T_39; // @[package.scala:81:59]
wire _GEN_9 = sectored_entries_0_5_valid_0 | sectored_entries_0_5_valid_1; // @[package.scala:81:59]
wire _sector_hits_T_40; // @[package.scala:81:59]
assign _sector_hits_T_40 = _GEN_9; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_15; // @[package.scala:81:59]
assign _r_sectored_repl_addr_valids_T_15 = _GEN_9; // @[package.scala:81:59]
wire _sector_hits_T_41 = _sector_hits_T_40 | sectored_entries_0_5_valid_2; // @[package.scala:81:59]
wire _sector_hits_T_42 = _sector_hits_T_41 | sectored_entries_0_5_valid_3; // @[package.scala:81:59]
wire [26:0] _T_2281 = sectored_entries_0_5_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29]
wire [26:0] _sector_hits_T_43; // @[TLB.scala:174:61]
assign _sector_hits_T_43 = _T_2281; // @[TLB.scala:174:61]
wire [26:0] _hitsVec_T_30; // @[TLB.scala:174:61]
assign _hitsVec_T_30 = _T_2281; // @[TLB.scala:174:61]
wire [24:0] _sector_hits_T_44 = _sector_hits_T_43[26:2]; // @[TLB.scala:174:{61,68}]
wire _sector_hits_T_45 = _sector_hits_T_44 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _sector_hits_T_46 = ~sectored_entries_0_5_tag_v; // @[TLB.scala:174:105, :339:29]
wire _sector_hits_T_47 = _sector_hits_T_45 & _sector_hits_T_46; // @[TLB.scala:174:{86,95,105}]
wire sector_hits_5 = _sector_hits_T_42 & _sector_hits_T_47; // @[package.scala:81:59]
wire _GEN_10 = sectored_entries_0_6_valid_0 | sectored_entries_0_6_valid_1; // @[package.scala:81:59]
wire _sector_hits_T_48; // @[package.scala:81:59]
assign _sector_hits_T_48 = _GEN_10; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_18; // @[package.scala:81:59]
assign _r_sectored_repl_addr_valids_T_18 = _GEN_10; // @[package.scala:81:59]
wire _sector_hits_T_49 = _sector_hits_T_48 | sectored_entries_0_6_valid_2; // @[package.scala:81:59]
wire _sector_hits_T_50 = _sector_hits_T_49 | sectored_entries_0_6_valid_3; // @[package.scala:81:59]
wire [26:0] _T_2702 = sectored_entries_0_6_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29]
wire [26:0] _sector_hits_T_51; // @[TLB.scala:174:61]
assign _sector_hits_T_51 = _T_2702; // @[TLB.scala:174:61]
wire [26:0] _hitsVec_T_36; // @[TLB.scala:174:61]
assign _hitsVec_T_36 = _T_2702; // @[TLB.scala:174:61]
wire [24:0] _sector_hits_T_52 = _sector_hits_T_51[26:2]; // @[TLB.scala:174:{61,68}]
wire _sector_hits_T_53 = _sector_hits_T_52 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _sector_hits_T_54 = ~sectored_entries_0_6_tag_v; // @[TLB.scala:174:105, :339:29]
wire _sector_hits_T_55 = _sector_hits_T_53 & _sector_hits_T_54; // @[TLB.scala:174:{86,95,105}]
wire sector_hits_6 = _sector_hits_T_50 & _sector_hits_T_55; // @[package.scala:81:59]
wire _GEN_11 = sectored_entries_0_7_valid_0 | sectored_entries_0_7_valid_1; // @[package.scala:81:59]
wire _sector_hits_T_56; // @[package.scala:81:59]
assign _sector_hits_T_56 = _GEN_11; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_21; // @[package.scala:81:59]
assign _r_sectored_repl_addr_valids_T_21 = _GEN_11; // @[package.scala:81:59]
wire _sector_hits_T_57 = _sector_hits_T_56 | sectored_entries_0_7_valid_2; // @[package.scala:81:59]
wire _sector_hits_T_58 = _sector_hits_T_57 | sectored_entries_0_7_valid_3; // @[package.scala:81:59]
wire [26:0] _T_3123 = sectored_entries_0_7_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29]
wire [26:0] _sector_hits_T_59; // @[TLB.scala:174:61]
assign _sector_hits_T_59 = _T_3123; // @[TLB.scala:174:61]
wire [26:0] _hitsVec_T_42; // @[TLB.scala:174:61]
assign _hitsVec_T_42 = _T_3123; // @[TLB.scala:174:61]
wire [24:0] _sector_hits_T_60 = _sector_hits_T_59[26:2]; // @[TLB.scala:174:{61,68}]
wire _sector_hits_T_61 = _sector_hits_T_60 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _sector_hits_T_62 = ~sectored_entries_0_7_tag_v; // @[TLB.scala:174:105, :339:29]
wire _sector_hits_T_63 = _sector_hits_T_61 & _sector_hits_T_62; // @[TLB.scala:174:{86,95,105}]
wire sector_hits_7 = _sector_hits_T_58 & _sector_hits_T_63; // @[package.scala:81:59]
wire _superpage_hits_tagMatch_T = ~superpage_entries_0_tag_v; // @[TLB.scala:178:43, :341:30]
wire superpage_hits_tagMatch = superpage_entries_0_valid_0 & _superpage_hits_tagMatch_T; // @[TLB.scala:178:{33,43}, :341:30]
wire [26:0] _T_3446 = superpage_entries_0_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30]
wire [26:0] _superpage_hits_T; // @[TLB.scala:183:52]
assign _superpage_hits_T = _T_3446; // @[TLB.scala:183:52]
wire [26:0] _superpage_hits_T_5; // @[TLB.scala:183:52]
assign _superpage_hits_T_5 = _T_3446; // @[TLB.scala:183:52]
wire [26:0] _superpage_hits_T_10; // @[TLB.scala:183:52]
assign _superpage_hits_T_10 = _T_3446; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_48; // @[TLB.scala:183:52]
assign _hitsVec_T_48 = _T_3446; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_53; // @[TLB.scala:183:52]
assign _hitsVec_T_53 = _T_3446; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_58; // @[TLB.scala:183:52]
assign _hitsVec_T_58 = _T_3446; // @[TLB.scala:183:52]
wire [8:0] _superpage_hits_T_1 = _superpage_hits_T[26:18]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_2 = _superpage_hits_T_1 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _superpage_hits_T_3 = _superpage_hits_T_2; // @[TLB.scala:183:{40,79}]
wire _superpage_hits_T_4 = superpage_hits_tagMatch & _superpage_hits_T_3; // @[TLB.scala:178:33, :183:{29,40}]
wire _GEN_12 = superpage_entries_0_level == 2'h0; // @[TLB.scala:182:28, :341:30]
wire _superpage_hits_ignore_T_1; // @[TLB.scala:182:28]
assign _superpage_hits_ignore_T_1 = _GEN_12; // @[TLB.scala:182:28]
wire _hitsVec_ignore_T_1; // @[TLB.scala:182:28]
assign _hitsVec_ignore_T_1 = _GEN_12; // @[TLB.scala:182:28]
wire _ppn_ignore_T; // @[TLB.scala:197:28]
assign _ppn_ignore_T = _GEN_12; // @[TLB.scala:182:28, :197:28]
wire _ignore_T_1; // @[TLB.scala:182:28]
assign _ignore_T_1 = _GEN_12; // @[TLB.scala:182:28]
wire superpage_hits_ignore_1 = _superpage_hits_ignore_T_1; // @[TLB.scala:182:{28,34}]
wire [8:0] _superpage_hits_T_6 = _superpage_hits_T_5[17:9]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_7 = _superpage_hits_T_6 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _superpage_hits_T_8 = superpage_hits_ignore_1 | _superpage_hits_T_7; // @[TLB.scala:182:34, :183:{40,79}]
wire _superpage_hits_T_9 = _superpage_hits_T_4 & _superpage_hits_T_8; // @[TLB.scala:183:{29,40}]
wire superpage_hits_0 = _superpage_hits_T_9; // @[TLB.scala:183:29]
wire _superpage_hits_ignore_T_2 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :341:30]
wire [8:0] _superpage_hits_T_11 = _superpage_hits_T_10[8:0]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_12 = _superpage_hits_T_11 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _superpage_hits_tagMatch_T_1 = ~superpage_entries_1_tag_v; // @[TLB.scala:178:43, :341:30]
wire superpage_hits_tagMatch_1 = superpage_entries_1_valid_0 & _superpage_hits_tagMatch_T_1; // @[TLB.scala:178:{33,43}, :341:30]
wire [26:0] _T_3544 = superpage_entries_1_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30]
wire [26:0] _superpage_hits_T_14; // @[TLB.scala:183:52]
assign _superpage_hits_T_14 = _T_3544; // @[TLB.scala:183:52]
wire [26:0] _superpage_hits_T_19; // @[TLB.scala:183:52]
assign _superpage_hits_T_19 = _T_3544; // @[TLB.scala:183:52]
wire [26:0] _superpage_hits_T_24; // @[TLB.scala:183:52]
assign _superpage_hits_T_24 = _T_3544; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_63; // @[TLB.scala:183:52]
assign _hitsVec_T_63 = _T_3544; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_68; // @[TLB.scala:183:52]
assign _hitsVec_T_68 = _T_3544; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_73; // @[TLB.scala:183:52]
assign _hitsVec_T_73 = _T_3544; // @[TLB.scala:183:52]
wire [8:0] _superpage_hits_T_15 = _superpage_hits_T_14[26:18]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_16 = _superpage_hits_T_15 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _superpage_hits_T_17 = _superpage_hits_T_16; // @[TLB.scala:183:{40,79}]
wire _superpage_hits_T_18 = superpage_hits_tagMatch_1 & _superpage_hits_T_17; // @[TLB.scala:178:33, :183:{29,40}]
wire _GEN_13 = superpage_entries_1_level == 2'h0; // @[TLB.scala:182:28, :341:30]
wire _superpage_hits_ignore_T_4; // @[TLB.scala:182:28]
assign _superpage_hits_ignore_T_4 = _GEN_13; // @[TLB.scala:182:28]
wire _hitsVec_ignore_T_4; // @[TLB.scala:182:28]
assign _hitsVec_ignore_T_4 = _GEN_13; // @[TLB.scala:182:28]
wire _ppn_ignore_T_2; // @[TLB.scala:197:28]
assign _ppn_ignore_T_2 = _GEN_13; // @[TLB.scala:182:28, :197:28]
wire _ignore_T_4; // @[TLB.scala:182:28]
assign _ignore_T_4 = _GEN_13; // @[TLB.scala:182:28]
wire superpage_hits_ignore_4 = _superpage_hits_ignore_T_4; // @[TLB.scala:182:{28,34}]
wire [8:0] _superpage_hits_T_20 = _superpage_hits_T_19[17:9]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_21 = _superpage_hits_T_20 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _superpage_hits_T_22 = superpage_hits_ignore_4 | _superpage_hits_T_21; // @[TLB.scala:182:34, :183:{40,79}]
wire _superpage_hits_T_23 = _superpage_hits_T_18 & _superpage_hits_T_22; // @[TLB.scala:183:{29,40}]
wire superpage_hits_1 = _superpage_hits_T_23; // @[TLB.scala:183:29]
wire _superpage_hits_ignore_T_5 = ~(superpage_entries_1_level[1]); // @[TLB.scala:182:28, :341:30]
wire [8:0] _superpage_hits_T_25 = _superpage_hits_T_24[8:0]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_26 = _superpage_hits_T_25 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _superpage_hits_tagMatch_T_2 = ~superpage_entries_2_tag_v; // @[TLB.scala:178:43, :341:30]
wire superpage_hits_tagMatch_2 = superpage_entries_2_valid_0 & _superpage_hits_tagMatch_T_2; // @[TLB.scala:178:{33,43}, :341:30]
wire [26:0] _T_3642 = superpage_entries_2_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30]
wire [26:0] _superpage_hits_T_28; // @[TLB.scala:183:52]
assign _superpage_hits_T_28 = _T_3642; // @[TLB.scala:183:52]
wire [26:0] _superpage_hits_T_33; // @[TLB.scala:183:52]
assign _superpage_hits_T_33 = _T_3642; // @[TLB.scala:183:52]
wire [26:0] _superpage_hits_T_38; // @[TLB.scala:183:52]
assign _superpage_hits_T_38 = _T_3642; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_78; // @[TLB.scala:183:52]
assign _hitsVec_T_78 = _T_3642; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_83; // @[TLB.scala:183:52]
assign _hitsVec_T_83 = _T_3642; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_88; // @[TLB.scala:183:52]
assign _hitsVec_T_88 = _T_3642; // @[TLB.scala:183:52]
wire [8:0] _superpage_hits_T_29 = _superpage_hits_T_28[26:18]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_30 = _superpage_hits_T_29 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _superpage_hits_T_31 = _superpage_hits_T_30; // @[TLB.scala:183:{40,79}]
wire _superpage_hits_T_32 = superpage_hits_tagMatch_2 & _superpage_hits_T_31; // @[TLB.scala:178:33, :183:{29,40}]
wire _GEN_14 = superpage_entries_2_level == 2'h0; // @[TLB.scala:182:28, :341:30]
wire _superpage_hits_ignore_T_7; // @[TLB.scala:182:28]
assign _superpage_hits_ignore_T_7 = _GEN_14; // @[TLB.scala:182:28]
wire _hitsVec_ignore_T_7; // @[TLB.scala:182:28]
assign _hitsVec_ignore_T_7 = _GEN_14; // @[TLB.scala:182:28]
wire _ppn_ignore_T_4; // @[TLB.scala:197:28]
assign _ppn_ignore_T_4 = _GEN_14; // @[TLB.scala:182:28, :197:28]
wire _ignore_T_7; // @[TLB.scala:182:28]
assign _ignore_T_7 = _GEN_14; // @[TLB.scala:182:28]
wire superpage_hits_ignore_7 = _superpage_hits_ignore_T_7; // @[TLB.scala:182:{28,34}]
wire [8:0] _superpage_hits_T_34 = _superpage_hits_T_33[17:9]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_35 = _superpage_hits_T_34 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _superpage_hits_T_36 = superpage_hits_ignore_7 | _superpage_hits_T_35; // @[TLB.scala:182:34, :183:{40,79}]
wire _superpage_hits_T_37 = _superpage_hits_T_32 & _superpage_hits_T_36; // @[TLB.scala:183:{29,40}]
wire superpage_hits_2 = _superpage_hits_T_37; // @[TLB.scala:183:29]
wire _superpage_hits_ignore_T_8 = ~(superpage_entries_2_level[1]); // @[TLB.scala:182:28, :341:30]
wire [8:0] _superpage_hits_T_39 = _superpage_hits_T_38[8:0]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_40 = _superpage_hits_T_39 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _superpage_hits_tagMatch_T_3 = ~superpage_entries_3_tag_v; // @[TLB.scala:178:43, :341:30]
wire superpage_hits_tagMatch_3 = superpage_entries_3_valid_0 & _superpage_hits_tagMatch_T_3; // @[TLB.scala:178:{33,43}, :341:30]
wire [26:0] _T_3740 = superpage_entries_3_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30]
wire [26:0] _superpage_hits_T_42; // @[TLB.scala:183:52]
assign _superpage_hits_T_42 = _T_3740; // @[TLB.scala:183:52]
wire [26:0] _superpage_hits_T_47; // @[TLB.scala:183:52]
assign _superpage_hits_T_47 = _T_3740; // @[TLB.scala:183:52]
wire [26:0] _superpage_hits_T_52; // @[TLB.scala:183:52]
assign _superpage_hits_T_52 = _T_3740; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_93; // @[TLB.scala:183:52]
assign _hitsVec_T_93 = _T_3740; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_98; // @[TLB.scala:183:52]
assign _hitsVec_T_98 = _T_3740; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_103; // @[TLB.scala:183:52]
assign _hitsVec_T_103 = _T_3740; // @[TLB.scala:183:52]
wire [8:0] _superpage_hits_T_43 = _superpage_hits_T_42[26:18]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_44 = _superpage_hits_T_43 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _superpage_hits_T_45 = _superpage_hits_T_44; // @[TLB.scala:183:{40,79}]
wire _superpage_hits_T_46 = superpage_hits_tagMatch_3 & _superpage_hits_T_45; // @[TLB.scala:178:33, :183:{29,40}]
wire _GEN_15 = superpage_entries_3_level == 2'h0; // @[TLB.scala:182:28, :341:30]
wire _superpage_hits_ignore_T_10; // @[TLB.scala:182:28]
assign _superpage_hits_ignore_T_10 = _GEN_15; // @[TLB.scala:182:28]
wire _hitsVec_ignore_T_10; // @[TLB.scala:182:28]
assign _hitsVec_ignore_T_10 = _GEN_15; // @[TLB.scala:182:28]
wire _ppn_ignore_T_6; // @[TLB.scala:197:28]
assign _ppn_ignore_T_6 = _GEN_15; // @[TLB.scala:182:28, :197:28]
wire _ignore_T_10; // @[TLB.scala:182:28]
assign _ignore_T_10 = _GEN_15; // @[TLB.scala:182:28]
wire superpage_hits_ignore_10 = _superpage_hits_ignore_T_10; // @[TLB.scala:182:{28,34}]
wire [8:0] _superpage_hits_T_48 = _superpage_hits_T_47[17:9]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_49 = _superpage_hits_T_48 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _superpage_hits_T_50 = superpage_hits_ignore_10 | _superpage_hits_T_49; // @[TLB.scala:182:34, :183:{40,79}]
wire _superpage_hits_T_51 = _superpage_hits_T_46 & _superpage_hits_T_50; // @[TLB.scala:183:{29,40}]
wire superpage_hits_3 = _superpage_hits_T_51; // @[TLB.scala:183:29]
wire _superpage_hits_ignore_T_11 = ~(superpage_entries_3_level[1]); // @[TLB.scala:182:28, :341:30]
wire [8:0] _superpage_hits_T_53 = _superpage_hits_T_52[8:0]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_54 = _superpage_hits_T_53 == 9'h0; // @[TLB.scala:183:{58,79}]
wire [1:0] hitsVec_idx = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_1 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_2 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_3 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_4 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_5 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_6 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_7 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_24 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_48 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_72 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_96 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_120 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_144 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_168 = vpn[1:0]; // @[package.scala:163:13]
wire [24:0] _hitsVec_T_1 = _hitsVec_T[26:2]; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_2 = _hitsVec_T_1 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _hitsVec_T_3 = ~sectored_entries_0_0_tag_v; // @[TLB.scala:174:105, :339:29]
wire _hitsVec_T_4 = _hitsVec_T_2 & _hitsVec_T_3; // @[TLB.scala:174:{86,95,105}]
wire [3:0] _GEN_16 = {{sectored_entries_0_0_valid_3}, {sectored_entries_0_0_valid_2}, {sectored_entries_0_0_valid_1}, {sectored_entries_0_0_valid_0}}; // @[TLB.scala:188:18, :339:29]
wire _hitsVec_T_5 = _GEN_16[hitsVec_idx] & _hitsVec_T_4; // @[package.scala:163:13]
wire hitsVec_0 = vm_enabled & _hitsVec_T_5; // @[TLB.scala:188:18, :399:61, :440:44]
wire [24:0] _hitsVec_T_7 = _hitsVec_T_6[26:2]; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_8 = _hitsVec_T_7 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _hitsVec_T_9 = ~sectored_entries_0_1_tag_v; // @[TLB.scala:174:105, :339:29]
wire _hitsVec_T_10 = _hitsVec_T_8 & _hitsVec_T_9; // @[TLB.scala:174:{86,95,105}]
wire [3:0] _GEN_17 = {{sectored_entries_0_1_valid_3}, {sectored_entries_0_1_valid_2}, {sectored_entries_0_1_valid_1}, {sectored_entries_0_1_valid_0}}; // @[TLB.scala:188:18, :339:29]
wire _hitsVec_T_11 = _GEN_17[hitsVec_idx_1] & _hitsVec_T_10; // @[package.scala:163:13]
wire hitsVec_1 = vm_enabled & _hitsVec_T_11; // @[TLB.scala:188:18, :399:61, :440:44]
wire [24:0] _hitsVec_T_13 = _hitsVec_T_12[26:2]; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_14 = _hitsVec_T_13 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _hitsVec_T_15 = ~sectored_entries_0_2_tag_v; // @[TLB.scala:174:105, :339:29]
wire _hitsVec_T_16 = _hitsVec_T_14 & _hitsVec_T_15; // @[TLB.scala:174:{86,95,105}]
wire [3:0] _GEN_18 = {{sectored_entries_0_2_valid_3}, {sectored_entries_0_2_valid_2}, {sectored_entries_0_2_valid_1}, {sectored_entries_0_2_valid_0}}; // @[TLB.scala:188:18, :339:29]
wire _hitsVec_T_17 = _GEN_18[hitsVec_idx_2] & _hitsVec_T_16; // @[package.scala:163:13]
wire hitsVec_2 = vm_enabled & _hitsVec_T_17; // @[TLB.scala:188:18, :399:61, :440:44]
wire [24:0] _hitsVec_T_19 = _hitsVec_T_18[26:2]; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_20 = _hitsVec_T_19 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _hitsVec_T_21 = ~sectored_entries_0_3_tag_v; // @[TLB.scala:174:105, :339:29]
wire _hitsVec_T_22 = _hitsVec_T_20 & _hitsVec_T_21; // @[TLB.scala:174:{86,95,105}]
wire [3:0] _GEN_19 = {{sectored_entries_0_3_valid_3}, {sectored_entries_0_3_valid_2}, {sectored_entries_0_3_valid_1}, {sectored_entries_0_3_valid_0}}; // @[TLB.scala:188:18, :339:29]
wire _hitsVec_T_23 = _GEN_19[hitsVec_idx_3] & _hitsVec_T_22; // @[package.scala:163:13]
wire hitsVec_3 = vm_enabled & _hitsVec_T_23; // @[TLB.scala:188:18, :399:61, :440:44]
wire [24:0] _hitsVec_T_25 = _hitsVec_T_24[26:2]; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_26 = _hitsVec_T_25 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _hitsVec_T_27 = ~sectored_entries_0_4_tag_v; // @[TLB.scala:174:105, :339:29]
wire _hitsVec_T_28 = _hitsVec_T_26 & _hitsVec_T_27; // @[TLB.scala:174:{86,95,105}]
wire [3:0] _GEN_20 = {{sectored_entries_0_4_valid_3}, {sectored_entries_0_4_valid_2}, {sectored_entries_0_4_valid_1}, {sectored_entries_0_4_valid_0}}; // @[TLB.scala:188:18, :339:29]
wire _hitsVec_T_29 = _GEN_20[hitsVec_idx_4] & _hitsVec_T_28; // @[package.scala:163:13]
wire hitsVec_4 = vm_enabled & _hitsVec_T_29; // @[TLB.scala:188:18, :399:61, :440:44]
wire [24:0] _hitsVec_T_31 = _hitsVec_T_30[26:2]; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_32 = _hitsVec_T_31 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _hitsVec_T_33 = ~sectored_entries_0_5_tag_v; // @[TLB.scala:174:105, :339:29]
wire _hitsVec_T_34 = _hitsVec_T_32 & _hitsVec_T_33; // @[TLB.scala:174:{86,95,105}]
wire [3:0] _GEN_21 = {{sectored_entries_0_5_valid_3}, {sectored_entries_0_5_valid_2}, {sectored_entries_0_5_valid_1}, {sectored_entries_0_5_valid_0}}; // @[TLB.scala:188:18, :339:29]
wire _hitsVec_T_35 = _GEN_21[hitsVec_idx_5] & _hitsVec_T_34; // @[package.scala:163:13]
wire hitsVec_5 = vm_enabled & _hitsVec_T_35; // @[TLB.scala:188:18, :399:61, :440:44]
wire [24:0] _hitsVec_T_37 = _hitsVec_T_36[26:2]; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_38 = _hitsVec_T_37 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _hitsVec_T_39 = ~sectored_entries_0_6_tag_v; // @[TLB.scala:174:105, :339:29]
wire _hitsVec_T_40 = _hitsVec_T_38 & _hitsVec_T_39; // @[TLB.scala:174:{86,95,105}]
wire [3:0] _GEN_22 = {{sectored_entries_0_6_valid_3}, {sectored_entries_0_6_valid_2}, {sectored_entries_0_6_valid_1}, {sectored_entries_0_6_valid_0}}; // @[TLB.scala:188:18, :339:29]
wire _hitsVec_T_41 = _GEN_22[hitsVec_idx_6] & _hitsVec_T_40; // @[package.scala:163:13]
wire hitsVec_6 = vm_enabled & _hitsVec_T_41; // @[TLB.scala:188:18, :399:61, :440:44]
wire [24:0] _hitsVec_T_43 = _hitsVec_T_42[26:2]; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_44 = _hitsVec_T_43 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _hitsVec_T_45 = ~sectored_entries_0_7_tag_v; // @[TLB.scala:174:105, :339:29]
wire _hitsVec_T_46 = _hitsVec_T_44 & _hitsVec_T_45; // @[TLB.scala:174:{86,95,105}]
wire [3:0] _GEN_23 = {{sectored_entries_0_7_valid_3}, {sectored_entries_0_7_valid_2}, {sectored_entries_0_7_valid_1}, {sectored_entries_0_7_valid_0}}; // @[TLB.scala:188:18, :339:29]
wire _hitsVec_T_47 = _GEN_23[hitsVec_idx_7] & _hitsVec_T_46; // @[package.scala:163:13]
wire hitsVec_7 = vm_enabled & _hitsVec_T_47; // @[TLB.scala:188:18, :399:61, :440:44]
wire _hitsVec_tagMatch_T = ~superpage_entries_0_tag_v; // @[TLB.scala:178:43, :341:30]
wire hitsVec_tagMatch = superpage_entries_0_valid_0 & _hitsVec_tagMatch_T; // @[TLB.scala:178:{33,43}, :341:30]
wire [8:0] _hitsVec_T_49 = _hitsVec_T_48[26:18]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_50 = _hitsVec_T_49 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _hitsVec_T_51 = _hitsVec_T_50; // @[TLB.scala:183:{40,79}]
wire _hitsVec_T_52 = hitsVec_tagMatch & _hitsVec_T_51; // @[TLB.scala:178:33, :183:{29,40}]
wire hitsVec_ignore_1 = _hitsVec_ignore_T_1; // @[TLB.scala:182:{28,34}]
wire [8:0] _hitsVec_T_54 = _hitsVec_T_53[17:9]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_55 = _hitsVec_T_54 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _hitsVec_T_56 = hitsVec_ignore_1 | _hitsVec_T_55; // @[TLB.scala:182:34, :183:{40,79}]
wire _hitsVec_T_57 = _hitsVec_T_52 & _hitsVec_T_56; // @[TLB.scala:183:{29,40}]
wire _hitsVec_T_62 = _hitsVec_T_57; // @[TLB.scala:183:29]
wire _hitsVec_ignore_T_2 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :341:30]
wire [8:0] _hitsVec_T_59 = _hitsVec_T_58[8:0]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_60 = _hitsVec_T_59 == 9'h0; // @[TLB.scala:183:{58,79}]
wire hitsVec_8 = vm_enabled & _hitsVec_T_62; // @[TLB.scala:183:29, :399:61, :440:44]
wire _hitsVec_tagMatch_T_1 = ~superpage_entries_1_tag_v; // @[TLB.scala:178:43, :341:30]
wire hitsVec_tagMatch_1 = superpage_entries_1_valid_0 & _hitsVec_tagMatch_T_1; // @[TLB.scala:178:{33,43}, :341:30]
wire [8:0] _hitsVec_T_64 = _hitsVec_T_63[26:18]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_65 = _hitsVec_T_64 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _hitsVec_T_66 = _hitsVec_T_65; // @[TLB.scala:183:{40,79}]
wire _hitsVec_T_67 = hitsVec_tagMatch_1 & _hitsVec_T_66; // @[TLB.scala:178:33, :183:{29,40}]
wire hitsVec_ignore_4 = _hitsVec_ignore_T_4; // @[TLB.scala:182:{28,34}]
wire [8:0] _hitsVec_T_69 = _hitsVec_T_68[17:9]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_70 = _hitsVec_T_69 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _hitsVec_T_71 = hitsVec_ignore_4 | _hitsVec_T_70; // @[TLB.scala:182:34, :183:{40,79}]
wire _hitsVec_T_72 = _hitsVec_T_67 & _hitsVec_T_71; // @[TLB.scala:183:{29,40}]
wire _hitsVec_T_77 = _hitsVec_T_72; // @[TLB.scala:183:29]
wire _hitsVec_ignore_T_5 = ~(superpage_entries_1_level[1]); // @[TLB.scala:182:28, :341:30]
wire [8:0] _hitsVec_T_74 = _hitsVec_T_73[8:0]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_75 = _hitsVec_T_74 == 9'h0; // @[TLB.scala:183:{58,79}]
wire hitsVec_9 = vm_enabled & _hitsVec_T_77; // @[TLB.scala:183:29, :399:61, :440:44]
wire _hitsVec_tagMatch_T_2 = ~superpage_entries_2_tag_v; // @[TLB.scala:178:43, :341:30]
wire hitsVec_tagMatch_2 = superpage_entries_2_valid_0 & _hitsVec_tagMatch_T_2; // @[TLB.scala:178:{33,43}, :341:30]
wire [8:0] _hitsVec_T_79 = _hitsVec_T_78[26:18]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_80 = _hitsVec_T_79 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _hitsVec_T_81 = _hitsVec_T_80; // @[TLB.scala:183:{40,79}]
wire _hitsVec_T_82 = hitsVec_tagMatch_2 & _hitsVec_T_81; // @[TLB.scala:178:33, :183:{29,40}]
wire hitsVec_ignore_7 = _hitsVec_ignore_T_7; // @[TLB.scala:182:{28,34}]
wire [8:0] _hitsVec_T_84 = _hitsVec_T_83[17:9]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_85 = _hitsVec_T_84 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _hitsVec_T_86 = hitsVec_ignore_7 | _hitsVec_T_85; // @[TLB.scala:182:34, :183:{40,79}]
wire _hitsVec_T_87 = _hitsVec_T_82 & _hitsVec_T_86; // @[TLB.scala:183:{29,40}]
wire _hitsVec_T_92 = _hitsVec_T_87; // @[TLB.scala:183:29]
wire _hitsVec_ignore_T_8 = ~(superpage_entries_2_level[1]); // @[TLB.scala:182:28, :341:30]
wire [8:0] _hitsVec_T_89 = _hitsVec_T_88[8:0]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_90 = _hitsVec_T_89 == 9'h0; // @[TLB.scala:183:{58,79}]
wire hitsVec_10 = vm_enabled & _hitsVec_T_92; // @[TLB.scala:183:29, :399:61, :440:44]
wire _hitsVec_tagMatch_T_3 = ~superpage_entries_3_tag_v; // @[TLB.scala:178:43, :341:30]
wire hitsVec_tagMatch_3 = superpage_entries_3_valid_0 & _hitsVec_tagMatch_T_3; // @[TLB.scala:178:{33,43}, :341:30]
wire [8:0] _hitsVec_T_94 = _hitsVec_T_93[26:18]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_95 = _hitsVec_T_94 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _hitsVec_T_96 = _hitsVec_T_95; // @[TLB.scala:183:{40,79}]
wire _hitsVec_T_97 = hitsVec_tagMatch_3 & _hitsVec_T_96; // @[TLB.scala:178:33, :183:{29,40}]
wire hitsVec_ignore_10 = _hitsVec_ignore_T_10; // @[TLB.scala:182:{28,34}]
wire [8:0] _hitsVec_T_99 = _hitsVec_T_98[17:9]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_100 = _hitsVec_T_99 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _hitsVec_T_101 = hitsVec_ignore_10 | _hitsVec_T_100; // @[TLB.scala:182:34, :183:{40,79}]
wire _hitsVec_T_102 = _hitsVec_T_97 & _hitsVec_T_101; // @[TLB.scala:183:{29,40}]
wire _hitsVec_T_107 = _hitsVec_T_102; // @[TLB.scala:183:29]
wire _hitsVec_ignore_T_11 = ~(superpage_entries_3_level[1]); // @[TLB.scala:182:28, :341:30]
wire [8:0] _hitsVec_T_104 = _hitsVec_T_103[8:0]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_105 = _hitsVec_T_104 == 9'h0; // @[TLB.scala:183:{58,79}]
wire hitsVec_11 = vm_enabled & _hitsVec_T_107; // @[TLB.scala:183:29, :399:61, :440:44]
wire _hitsVec_tagMatch_T_4 = ~special_entry_tag_v; // @[TLB.scala:178:43, :346:56]
wire hitsVec_tagMatch_4 = special_entry_valid_0 & _hitsVec_tagMatch_T_4; // @[TLB.scala:178:{33,43}, :346:56]
wire [26:0] _T_3838 = special_entry_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :346:56]
wire [26:0] _hitsVec_T_108; // @[TLB.scala:183:52]
assign _hitsVec_T_108 = _T_3838; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_113; // @[TLB.scala:183:52]
assign _hitsVec_T_113 = _T_3838; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_118; // @[TLB.scala:183:52]
assign _hitsVec_T_118 = _T_3838; // @[TLB.scala:183:52]
wire [8:0] _hitsVec_T_109 = _hitsVec_T_108[26:18]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_110 = _hitsVec_T_109 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _hitsVec_T_111 = _hitsVec_T_110; // @[TLB.scala:183:{40,79}]
wire _hitsVec_T_112 = hitsVec_tagMatch_4 & _hitsVec_T_111; // @[TLB.scala:178:33, :183:{29,40}]
wire hitsVec_ignore_13 = _hitsVec_ignore_T_13; // @[TLB.scala:182:{28,34}]
wire [8:0] _hitsVec_T_114 = _hitsVec_T_113[17:9]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_115 = _hitsVec_T_114 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _hitsVec_T_116 = hitsVec_ignore_13 | _hitsVec_T_115; // @[TLB.scala:182:34, :183:{40,79}]
wire _hitsVec_T_117 = _hitsVec_T_112 & _hitsVec_T_116; // @[TLB.scala:183:{29,40}]
wire _hitsVec_ignore_T_14 = ~(special_entry_level[1]); // @[TLB.scala:182:28, :197:28, :346:56]
wire hitsVec_ignore_14 = _hitsVec_ignore_T_14; // @[TLB.scala:182:{28,34}]
wire [8:0] _hitsVec_T_119 = _hitsVec_T_118[8:0]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_120 = _hitsVec_T_119 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _hitsVec_T_121 = hitsVec_ignore_14 | _hitsVec_T_120; // @[TLB.scala:182:34, :183:{40,79}]
wire _hitsVec_T_122 = _hitsVec_T_117 & _hitsVec_T_121; // @[TLB.scala:183:{29,40}]
wire hitsVec_12 = vm_enabled & _hitsVec_T_122; // @[TLB.scala:183:29, :399:61, :440:44]
wire [1:0] real_hits_lo_lo_hi = {hitsVec_2, hitsVec_1}; // @[package.scala:45:27]
wire [2:0] real_hits_lo_lo = {real_hits_lo_lo_hi, hitsVec_0}; // @[package.scala:45:27]
wire [1:0] real_hits_lo_hi_hi = {hitsVec_5, hitsVec_4}; // @[package.scala:45:27]
wire [2:0] real_hits_lo_hi = {real_hits_lo_hi_hi, hitsVec_3}; // @[package.scala:45:27]
wire [5:0] real_hits_lo = {real_hits_lo_hi, real_hits_lo_lo}; // @[package.scala:45:27]
wire [1:0] real_hits_hi_lo_hi = {hitsVec_8, hitsVec_7}; // @[package.scala:45:27]
wire [2:0] real_hits_hi_lo = {real_hits_hi_lo_hi, hitsVec_6}; // @[package.scala:45:27]
wire [1:0] real_hits_hi_hi_lo = {hitsVec_10, hitsVec_9}; // @[package.scala:45:27]
wire [1:0] real_hits_hi_hi_hi = {hitsVec_12, hitsVec_11}; // @[package.scala:45:27]
wire [3:0] real_hits_hi_hi = {real_hits_hi_hi_hi, real_hits_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] real_hits_hi = {real_hits_hi_hi, real_hits_hi_lo}; // @[package.scala:45:27]
wire [12:0] real_hits = {real_hits_hi, real_hits_lo}; // @[package.scala:45:27]
wire [12:0] _tlb_hit_T = real_hits; // @[package.scala:45:27]
wire _hits_T = ~vm_enabled; // @[TLB.scala:399:61, :442:18]
wire [13:0] hits = {_hits_T, real_hits}; // @[package.scala:45:27]
wire _newEntry_g_T; // @[TLB.scala:453:25]
wire _newEntry_sw_T_6; // @[PTW.scala:151:40]
wire _newEntry_sx_T_5; // @[PTW.scala:153:35]
wire _newEntry_sr_T_5; // @[PTW.scala:149:35]
wire newEntry_g; // @[TLB.scala:449:24]
wire newEntry_sw; // @[TLB.scala:449:24]
wire newEntry_sx; // @[TLB.scala:449:24]
wire newEntry_sr; // @[TLB.scala:449:24]
wire newEntry_ppp; // @[TLB.scala:449:24]
wire newEntry_pal; // @[TLB.scala:449:24]
wire newEntry_paa; // @[TLB.scala:449:24]
wire newEntry_eff; // @[TLB.scala:449:24]
assign _newEntry_g_T = io_ptw_resp_bits_pte_g_0 & io_ptw_resp_bits_pte_v_0; // @[TLB.scala:318:7, :453:25]
assign newEntry_g = _newEntry_g_T; // @[TLB.scala:449:24, :453:25]
wire _newEntry_ae_stage2_T = io_ptw_resp_bits_ae_final_0 & io_ptw_resp_bits_gpa_is_pte_0; // @[TLB.scala:318:7, :456:53]
wire _newEntry_sr_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7]
wire _newEntry_sr_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sr_T; // @[TLB.scala:318:7]
wire _newEntry_sr_T_2 = io_ptw_resp_bits_pte_r_0 | _newEntry_sr_T_1; // @[TLB.scala:318:7]
wire _newEntry_sr_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sr_T_2; // @[TLB.scala:318:7]
wire _newEntry_sr_T_4 = _newEntry_sr_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7]
assign _newEntry_sr_T_5 = _newEntry_sr_T_4 & io_ptw_resp_bits_pte_r_0; // @[TLB.scala:318:7]
assign newEntry_sr = _newEntry_sr_T_5; // @[TLB.scala:449:24]
wire _newEntry_sw_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7]
wire _newEntry_sw_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sw_T; // @[TLB.scala:318:7]
wire _newEntry_sw_T_2 = io_ptw_resp_bits_pte_r_0 | _newEntry_sw_T_1; // @[TLB.scala:318:7]
wire _newEntry_sw_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sw_T_2; // @[TLB.scala:318:7]
wire _newEntry_sw_T_4 = _newEntry_sw_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7]
wire _newEntry_sw_T_5 = _newEntry_sw_T_4 & io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7]
assign _newEntry_sw_T_6 = _newEntry_sw_T_5 & io_ptw_resp_bits_pte_d_0; // @[TLB.scala:318:7]
assign newEntry_sw = _newEntry_sw_T_6; // @[TLB.scala:449:24]
wire _newEntry_sx_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7]
wire _newEntry_sx_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sx_T; // @[TLB.scala:318:7]
wire _newEntry_sx_T_2 = io_ptw_resp_bits_pte_r_0 | _newEntry_sx_T_1; // @[TLB.scala:318:7]
wire _newEntry_sx_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sx_T_2; // @[TLB.scala:318:7]
wire _newEntry_sx_T_4 = _newEntry_sx_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7]
assign _newEntry_sx_T_5 = _newEntry_sx_T_4 & io_ptw_resp_bits_pte_x_0; // @[TLB.scala:318:7]
assign newEntry_sx = _newEntry_sx_T_5; // @[TLB.scala:449:24]
wire [1:0] _GEN_24 = {newEntry_c, 1'h0}; // @[TLB.scala:217:24, :449:24]
wire [1:0] special_entry_data_0_lo_lo_lo; // @[TLB.scala:217:24]
assign special_entry_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_0_data_0_lo_lo_lo; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_1_data_0_lo_lo_lo; // @[TLB.scala:217:24]
assign superpage_entries_1_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_2_data_0_lo_lo_lo; // @[TLB.scala:217:24]
assign superpage_entries_2_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_3_data_0_lo_lo_lo; // @[TLB.scala:217:24]
assign superpage_entries_3_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_0_data_lo_lo_lo; // @[TLB.scala:217:24]
assign sectored_entries_0_0_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_1_data_lo_lo_lo; // @[TLB.scala:217:24]
assign sectored_entries_0_1_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_2_data_lo_lo_lo; // @[TLB.scala:217:24]
assign sectored_entries_0_2_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_3_data_lo_lo_lo; // @[TLB.scala:217:24]
assign sectored_entries_0_3_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_4_data_lo_lo_lo; // @[TLB.scala:217:24]
assign sectored_entries_0_4_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_5_data_lo_lo_lo; // @[TLB.scala:217:24]
assign sectored_entries_0_5_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_6_data_lo_lo_lo; // @[TLB.scala:217:24]
assign sectored_entries_0_6_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_7_data_lo_lo_lo; // @[TLB.scala:217:24]
assign sectored_entries_0_7_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] _GEN_25 = {newEntry_pal, newEntry_paa}; // @[TLB.scala:217:24, :449:24]
wire [1:0] special_entry_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign special_entry_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_0_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_1_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_1_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_2_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_2_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_3_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_3_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_0_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_0_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_1_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_1_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_2_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_2_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_3_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_3_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_4_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_4_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_5_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_5_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_6_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_6_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_7_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_7_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [2:0] special_entry_data_0_lo_lo_hi = {special_entry_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] special_entry_data_0_lo_lo = {special_entry_data_0_lo_lo_hi, special_entry_data_0_lo_lo_lo}; // @[TLB.scala:217:24]
wire [1:0] _GEN_26 = {newEntry_px, newEntry_pr}; // @[TLB.scala:217:24, :449:24]
wire [1:0] special_entry_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign special_entry_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_0_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_1_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_1_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_2_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_2_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_3_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_3_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_0_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_0_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_1_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_1_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_2_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_2_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_3_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_3_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_4_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_4_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_5_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_5_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_6_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_6_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_7_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_7_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [2:0] special_entry_data_0_lo_hi_lo = {special_entry_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [1:0] _GEN_27 = {newEntry_hx, newEntry_hr}; // @[TLB.scala:217:24, :449:24]
wire [1:0] special_entry_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign special_entry_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_0_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_1_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_1_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_2_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_2_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_3_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_3_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_0_data_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_0_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_1_data_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_1_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_2_data_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_2_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_3_data_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_3_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_4_data_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_4_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_5_data_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_5_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_6_data_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_6_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_7_data_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_7_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [2:0] special_entry_data_0_lo_hi_hi = {special_entry_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] special_entry_data_0_lo_hi = {special_entry_data_0_lo_hi_hi, special_entry_data_0_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] special_entry_data_0_lo = {special_entry_data_0_lo_hi, special_entry_data_0_lo_lo}; // @[TLB.scala:217:24]
wire [1:0] _GEN_28 = {newEntry_sx, newEntry_sr}; // @[TLB.scala:217:24, :449:24]
wire [1:0] special_entry_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign special_entry_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_0_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_1_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_1_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_2_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_2_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_3_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_3_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_0_data_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_0_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_1_data_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_1_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_2_data_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_2_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_3_data_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_3_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_4_data_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_4_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_5_data_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_5_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_6_data_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_6_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_7_data_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_7_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [2:0] special_entry_data_0_hi_lo_lo = {special_entry_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [1:0] _GEN_29 = {newEntry_pf, newEntry_gf}; // @[TLB.scala:217:24, :449:24]
wire [1:0] special_entry_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign special_entry_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_0_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_1_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_1_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_2_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_2_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_3_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_3_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_0_data_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_0_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_1_data_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_1_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_2_data_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_2_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_3_data_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_3_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_4_data_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_4_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_5_data_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_5_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_6_data_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_6_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_7_data_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_7_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [2:0] special_entry_data_0_hi_lo_hi = {special_entry_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] special_entry_data_0_hi_lo = {special_entry_data_0_hi_lo_hi, special_entry_data_0_hi_lo_lo}; // @[TLB.scala:217:24]
wire [1:0] _GEN_30 = {newEntry_ae_ptw, newEntry_ae_final}; // @[TLB.scala:217:24, :449:24]
wire [1:0] special_entry_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign special_entry_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_0_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_1_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_1_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_2_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_2_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_3_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_3_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_0_data_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_0_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_1_data_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_1_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_2_data_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_2_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_3_data_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_3_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_4_data_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_4_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_5_data_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_5_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_6_data_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_6_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_7_data_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_7_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [2:0] special_entry_data_0_hi_hi_lo = {special_entry_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [20:0] _GEN_31 = {newEntry_ppn, newEntry_u}; // @[TLB.scala:217:24, :449:24]
wire [20:0] special_entry_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign special_entry_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] superpage_entries_0_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] superpage_entries_1_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_1_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] superpage_entries_2_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_2_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] superpage_entries_3_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_3_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] sectored_entries_0_0_data_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_0_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] sectored_entries_0_1_data_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_1_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] sectored_entries_0_2_data_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_2_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] sectored_entries_0_3_data_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_3_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] sectored_entries_0_4_data_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_4_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] sectored_entries_0_5_data_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_5_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] sectored_entries_0_6_data_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_6_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] sectored_entries_0_7_data_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_7_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [21:0] special_entry_data_0_hi_hi_hi = {special_entry_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] special_entry_data_0_hi_hi = {special_entry_data_0_hi_hi_hi, special_entry_data_0_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] special_entry_data_0_hi = {special_entry_data_0_hi_hi, special_entry_data_0_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _special_entry_data_0_T = {special_entry_data_0_hi, special_entry_data_0_lo}; // @[TLB.scala:217:24]
wire _superpage_entries_0_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13]
wire _superpage_entries_1_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13]
wire _superpage_entries_2_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13]
wire _superpage_entries_3_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13]
wire [2:0] superpage_entries_0_data_0_lo_lo_hi = {superpage_entries_0_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] superpage_entries_0_data_0_lo_lo = {superpage_entries_0_data_0_lo_lo_hi, superpage_entries_0_data_0_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_0_data_0_lo_hi_lo = {superpage_entries_0_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] superpage_entries_0_data_0_lo_hi_hi = {superpage_entries_0_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] superpage_entries_0_data_0_lo_hi = {superpage_entries_0_data_0_lo_hi_hi, superpage_entries_0_data_0_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] superpage_entries_0_data_0_lo = {superpage_entries_0_data_0_lo_hi, superpage_entries_0_data_0_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_0_data_0_hi_lo_lo = {superpage_entries_0_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] superpage_entries_0_data_0_hi_lo_hi = {superpage_entries_0_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] superpage_entries_0_data_0_hi_lo = {superpage_entries_0_data_0_hi_lo_hi, superpage_entries_0_data_0_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_0_data_0_hi_hi_lo = {superpage_entries_0_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] superpage_entries_0_data_0_hi_hi_hi = {superpage_entries_0_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] superpage_entries_0_data_0_hi_hi = {superpage_entries_0_data_0_hi_hi_hi, superpage_entries_0_data_0_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] superpage_entries_0_data_0_hi = {superpage_entries_0_data_0_hi_hi, superpage_entries_0_data_0_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _superpage_entries_0_data_0_T = {superpage_entries_0_data_0_hi, superpage_entries_0_data_0_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_1_data_0_lo_lo_hi = {superpage_entries_1_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] superpage_entries_1_data_0_lo_lo = {superpage_entries_1_data_0_lo_lo_hi, superpage_entries_1_data_0_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_1_data_0_lo_hi_lo = {superpage_entries_1_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] superpage_entries_1_data_0_lo_hi_hi = {superpage_entries_1_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] superpage_entries_1_data_0_lo_hi = {superpage_entries_1_data_0_lo_hi_hi, superpage_entries_1_data_0_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] superpage_entries_1_data_0_lo = {superpage_entries_1_data_0_lo_hi, superpage_entries_1_data_0_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_1_data_0_hi_lo_lo = {superpage_entries_1_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] superpage_entries_1_data_0_hi_lo_hi = {superpage_entries_1_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] superpage_entries_1_data_0_hi_lo = {superpage_entries_1_data_0_hi_lo_hi, superpage_entries_1_data_0_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_1_data_0_hi_hi_lo = {superpage_entries_1_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] superpage_entries_1_data_0_hi_hi_hi = {superpage_entries_1_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] superpage_entries_1_data_0_hi_hi = {superpage_entries_1_data_0_hi_hi_hi, superpage_entries_1_data_0_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] superpage_entries_1_data_0_hi = {superpage_entries_1_data_0_hi_hi, superpage_entries_1_data_0_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _superpage_entries_1_data_0_T = {superpage_entries_1_data_0_hi, superpage_entries_1_data_0_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_2_data_0_lo_lo_hi = {superpage_entries_2_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] superpage_entries_2_data_0_lo_lo = {superpage_entries_2_data_0_lo_lo_hi, superpage_entries_2_data_0_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_2_data_0_lo_hi_lo = {superpage_entries_2_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] superpage_entries_2_data_0_lo_hi_hi = {superpage_entries_2_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] superpage_entries_2_data_0_lo_hi = {superpage_entries_2_data_0_lo_hi_hi, superpage_entries_2_data_0_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] superpage_entries_2_data_0_lo = {superpage_entries_2_data_0_lo_hi, superpage_entries_2_data_0_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_2_data_0_hi_lo_lo = {superpage_entries_2_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] superpage_entries_2_data_0_hi_lo_hi = {superpage_entries_2_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] superpage_entries_2_data_0_hi_lo = {superpage_entries_2_data_0_hi_lo_hi, superpage_entries_2_data_0_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_2_data_0_hi_hi_lo = {superpage_entries_2_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] superpage_entries_2_data_0_hi_hi_hi = {superpage_entries_2_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] superpage_entries_2_data_0_hi_hi = {superpage_entries_2_data_0_hi_hi_hi, superpage_entries_2_data_0_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] superpage_entries_2_data_0_hi = {superpage_entries_2_data_0_hi_hi, superpage_entries_2_data_0_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _superpage_entries_2_data_0_T = {superpage_entries_2_data_0_hi, superpage_entries_2_data_0_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_3_data_0_lo_lo_hi = {superpage_entries_3_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] superpage_entries_3_data_0_lo_lo = {superpage_entries_3_data_0_lo_lo_hi, superpage_entries_3_data_0_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_3_data_0_lo_hi_lo = {superpage_entries_3_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] superpage_entries_3_data_0_lo_hi_hi = {superpage_entries_3_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] superpage_entries_3_data_0_lo_hi = {superpage_entries_3_data_0_lo_hi_hi, superpage_entries_3_data_0_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] superpage_entries_3_data_0_lo = {superpage_entries_3_data_0_lo_hi, superpage_entries_3_data_0_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_3_data_0_hi_lo_lo = {superpage_entries_3_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] superpage_entries_3_data_0_hi_lo_hi = {superpage_entries_3_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] superpage_entries_3_data_0_hi_lo = {superpage_entries_3_data_0_hi_lo_hi, superpage_entries_3_data_0_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_3_data_0_hi_hi_lo = {superpage_entries_3_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] superpage_entries_3_data_0_hi_hi_hi = {superpage_entries_3_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] superpage_entries_3_data_0_hi_hi = {superpage_entries_3_data_0_hi_hi_hi, superpage_entries_3_data_0_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] superpage_entries_3_data_0_hi = {superpage_entries_3_data_0_hi_hi, superpage_entries_3_data_0_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _superpage_entries_3_data_0_T = {superpage_entries_3_data_0_hi, superpage_entries_3_data_0_lo}; // @[TLB.scala:217:24]
wire [2:0] waddr_1 = r_sectored_hit_valid ? r_sectored_hit_bits : r_sectored_repl_addr; // @[TLB.scala:356:33, :357:27, :485:22]
wire [1:0] idx = r_refill_tag[1:0]; // @[package.scala:163:13]
wire [1:0] idx_1 = r_refill_tag[1:0]; // @[package.scala:163:13]
wire [1:0] idx_2 = r_refill_tag[1:0]; // @[package.scala:163:13]
wire [1:0] idx_3 = r_refill_tag[1:0]; // @[package.scala:163:13]
wire [1:0] idx_4 = r_refill_tag[1:0]; // @[package.scala:163:13]
wire [1:0] idx_5 = r_refill_tag[1:0]; // @[package.scala:163:13]
wire [1:0] idx_6 = r_refill_tag[1:0]; // @[package.scala:163:13]
wire [1:0] idx_7 = r_refill_tag[1:0]; // @[package.scala:163:13]
wire [2:0] sectored_entries_0_0_data_lo_lo_hi = {sectored_entries_0_0_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] sectored_entries_0_0_data_lo_lo = {sectored_entries_0_0_data_lo_lo_hi, sectored_entries_0_0_data_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_0_data_lo_hi_lo = {sectored_entries_0_0_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_0_data_lo_hi_hi = {sectored_entries_0_0_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_0_data_lo_hi = {sectored_entries_0_0_data_lo_hi_hi, sectored_entries_0_0_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] sectored_entries_0_0_data_lo = {sectored_entries_0_0_data_lo_hi, sectored_entries_0_0_data_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_0_data_hi_lo_lo = {sectored_entries_0_0_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_0_data_hi_lo_hi = {sectored_entries_0_0_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_0_data_hi_lo = {sectored_entries_0_0_data_hi_lo_hi, sectored_entries_0_0_data_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_0_data_hi_hi_lo = {sectored_entries_0_0_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] sectored_entries_0_0_data_hi_hi_hi = {sectored_entries_0_0_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] sectored_entries_0_0_data_hi_hi = {sectored_entries_0_0_data_hi_hi_hi, sectored_entries_0_0_data_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] sectored_entries_0_0_data_hi = {sectored_entries_0_0_data_hi_hi, sectored_entries_0_0_data_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _sectored_entries_0_0_data_T = {sectored_entries_0_0_data_hi, sectored_entries_0_0_data_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_1_data_lo_lo_hi = {sectored_entries_0_1_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] sectored_entries_0_1_data_lo_lo = {sectored_entries_0_1_data_lo_lo_hi, sectored_entries_0_1_data_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_1_data_lo_hi_lo = {sectored_entries_0_1_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_1_data_lo_hi_hi = {sectored_entries_0_1_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_1_data_lo_hi = {sectored_entries_0_1_data_lo_hi_hi, sectored_entries_0_1_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] sectored_entries_0_1_data_lo = {sectored_entries_0_1_data_lo_hi, sectored_entries_0_1_data_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_1_data_hi_lo_lo = {sectored_entries_0_1_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_1_data_hi_lo_hi = {sectored_entries_0_1_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_1_data_hi_lo = {sectored_entries_0_1_data_hi_lo_hi, sectored_entries_0_1_data_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_1_data_hi_hi_lo = {sectored_entries_0_1_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] sectored_entries_0_1_data_hi_hi_hi = {sectored_entries_0_1_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] sectored_entries_0_1_data_hi_hi = {sectored_entries_0_1_data_hi_hi_hi, sectored_entries_0_1_data_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] sectored_entries_0_1_data_hi = {sectored_entries_0_1_data_hi_hi, sectored_entries_0_1_data_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _sectored_entries_0_1_data_T = {sectored_entries_0_1_data_hi, sectored_entries_0_1_data_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_2_data_lo_lo_hi = {sectored_entries_0_2_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] sectored_entries_0_2_data_lo_lo = {sectored_entries_0_2_data_lo_lo_hi, sectored_entries_0_2_data_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_2_data_lo_hi_lo = {sectored_entries_0_2_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_2_data_lo_hi_hi = {sectored_entries_0_2_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_2_data_lo_hi = {sectored_entries_0_2_data_lo_hi_hi, sectored_entries_0_2_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] sectored_entries_0_2_data_lo = {sectored_entries_0_2_data_lo_hi, sectored_entries_0_2_data_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_2_data_hi_lo_lo = {sectored_entries_0_2_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_2_data_hi_lo_hi = {sectored_entries_0_2_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_2_data_hi_lo = {sectored_entries_0_2_data_hi_lo_hi, sectored_entries_0_2_data_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_2_data_hi_hi_lo = {sectored_entries_0_2_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] sectored_entries_0_2_data_hi_hi_hi = {sectored_entries_0_2_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] sectored_entries_0_2_data_hi_hi = {sectored_entries_0_2_data_hi_hi_hi, sectored_entries_0_2_data_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] sectored_entries_0_2_data_hi = {sectored_entries_0_2_data_hi_hi, sectored_entries_0_2_data_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _sectored_entries_0_2_data_T = {sectored_entries_0_2_data_hi, sectored_entries_0_2_data_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_3_data_lo_lo_hi = {sectored_entries_0_3_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] sectored_entries_0_3_data_lo_lo = {sectored_entries_0_3_data_lo_lo_hi, sectored_entries_0_3_data_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_3_data_lo_hi_lo = {sectored_entries_0_3_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_3_data_lo_hi_hi = {sectored_entries_0_3_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_3_data_lo_hi = {sectored_entries_0_3_data_lo_hi_hi, sectored_entries_0_3_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] sectored_entries_0_3_data_lo = {sectored_entries_0_3_data_lo_hi, sectored_entries_0_3_data_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_3_data_hi_lo_lo = {sectored_entries_0_3_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_3_data_hi_lo_hi = {sectored_entries_0_3_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_3_data_hi_lo = {sectored_entries_0_3_data_hi_lo_hi, sectored_entries_0_3_data_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_3_data_hi_hi_lo = {sectored_entries_0_3_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] sectored_entries_0_3_data_hi_hi_hi = {sectored_entries_0_3_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] sectored_entries_0_3_data_hi_hi = {sectored_entries_0_3_data_hi_hi_hi, sectored_entries_0_3_data_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] sectored_entries_0_3_data_hi = {sectored_entries_0_3_data_hi_hi, sectored_entries_0_3_data_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _sectored_entries_0_3_data_T = {sectored_entries_0_3_data_hi, sectored_entries_0_3_data_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_4_data_lo_lo_hi = {sectored_entries_0_4_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] sectored_entries_0_4_data_lo_lo = {sectored_entries_0_4_data_lo_lo_hi, sectored_entries_0_4_data_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_4_data_lo_hi_lo = {sectored_entries_0_4_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_4_data_lo_hi_hi = {sectored_entries_0_4_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_4_data_lo_hi = {sectored_entries_0_4_data_lo_hi_hi, sectored_entries_0_4_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] sectored_entries_0_4_data_lo = {sectored_entries_0_4_data_lo_hi, sectored_entries_0_4_data_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_4_data_hi_lo_lo = {sectored_entries_0_4_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_4_data_hi_lo_hi = {sectored_entries_0_4_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_4_data_hi_lo = {sectored_entries_0_4_data_hi_lo_hi, sectored_entries_0_4_data_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_4_data_hi_hi_lo = {sectored_entries_0_4_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] sectored_entries_0_4_data_hi_hi_hi = {sectored_entries_0_4_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] sectored_entries_0_4_data_hi_hi = {sectored_entries_0_4_data_hi_hi_hi, sectored_entries_0_4_data_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] sectored_entries_0_4_data_hi = {sectored_entries_0_4_data_hi_hi, sectored_entries_0_4_data_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _sectored_entries_0_4_data_T = {sectored_entries_0_4_data_hi, sectored_entries_0_4_data_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_5_data_lo_lo_hi = {sectored_entries_0_5_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] sectored_entries_0_5_data_lo_lo = {sectored_entries_0_5_data_lo_lo_hi, sectored_entries_0_5_data_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_5_data_lo_hi_lo = {sectored_entries_0_5_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_5_data_lo_hi_hi = {sectored_entries_0_5_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_5_data_lo_hi = {sectored_entries_0_5_data_lo_hi_hi, sectored_entries_0_5_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] sectored_entries_0_5_data_lo = {sectored_entries_0_5_data_lo_hi, sectored_entries_0_5_data_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_5_data_hi_lo_lo = {sectored_entries_0_5_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_5_data_hi_lo_hi = {sectored_entries_0_5_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_5_data_hi_lo = {sectored_entries_0_5_data_hi_lo_hi, sectored_entries_0_5_data_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_5_data_hi_hi_lo = {sectored_entries_0_5_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] sectored_entries_0_5_data_hi_hi_hi = {sectored_entries_0_5_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] sectored_entries_0_5_data_hi_hi = {sectored_entries_0_5_data_hi_hi_hi, sectored_entries_0_5_data_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] sectored_entries_0_5_data_hi = {sectored_entries_0_5_data_hi_hi, sectored_entries_0_5_data_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _sectored_entries_0_5_data_T = {sectored_entries_0_5_data_hi, sectored_entries_0_5_data_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_6_data_lo_lo_hi = {sectored_entries_0_6_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] sectored_entries_0_6_data_lo_lo = {sectored_entries_0_6_data_lo_lo_hi, sectored_entries_0_6_data_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_6_data_lo_hi_lo = {sectored_entries_0_6_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_6_data_lo_hi_hi = {sectored_entries_0_6_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_6_data_lo_hi = {sectored_entries_0_6_data_lo_hi_hi, sectored_entries_0_6_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] sectored_entries_0_6_data_lo = {sectored_entries_0_6_data_lo_hi, sectored_entries_0_6_data_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_6_data_hi_lo_lo = {sectored_entries_0_6_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_6_data_hi_lo_hi = {sectored_entries_0_6_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_6_data_hi_lo = {sectored_entries_0_6_data_hi_lo_hi, sectored_entries_0_6_data_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_6_data_hi_hi_lo = {sectored_entries_0_6_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] sectored_entries_0_6_data_hi_hi_hi = {sectored_entries_0_6_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] sectored_entries_0_6_data_hi_hi = {sectored_entries_0_6_data_hi_hi_hi, sectored_entries_0_6_data_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] sectored_entries_0_6_data_hi = {sectored_entries_0_6_data_hi_hi, sectored_entries_0_6_data_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _sectored_entries_0_6_data_T = {sectored_entries_0_6_data_hi, sectored_entries_0_6_data_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_7_data_lo_lo_hi = {sectored_entries_0_7_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] sectored_entries_0_7_data_lo_lo = {sectored_entries_0_7_data_lo_lo_hi, sectored_entries_0_7_data_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_7_data_lo_hi_lo = {sectored_entries_0_7_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_7_data_lo_hi_hi = {sectored_entries_0_7_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_7_data_lo_hi = {sectored_entries_0_7_data_lo_hi_hi, sectored_entries_0_7_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] sectored_entries_0_7_data_lo = {sectored_entries_0_7_data_lo_hi, sectored_entries_0_7_data_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_7_data_hi_lo_lo = {sectored_entries_0_7_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_7_data_hi_lo_hi = {sectored_entries_0_7_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_7_data_hi_lo = {sectored_entries_0_7_data_hi_lo_hi, sectored_entries_0_7_data_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_7_data_hi_hi_lo = {sectored_entries_0_7_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] sectored_entries_0_7_data_hi_hi_hi = {sectored_entries_0_7_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] sectored_entries_0_7_data_hi_hi = {sectored_entries_0_7_data_hi_hi_hi, sectored_entries_0_7_data_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] sectored_entries_0_7_data_hi = {sectored_entries_0_7_data_hi_hi, sectored_entries_0_7_data_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _sectored_entries_0_7_data_T = {sectored_entries_0_7_data_hi, sectored_entries_0_7_data_lo}; // @[TLB.scala:217:24]
wire [19:0] _entries_T_23; // @[TLB.scala:170:77]
wire _entries_T_22; // @[TLB.scala:170:77]
wire _entries_T_21; // @[TLB.scala:170:77]
wire _entries_T_20; // @[TLB.scala:170:77]
wire _entries_T_19; // @[TLB.scala:170:77]
wire _entries_T_18; // @[TLB.scala:170:77]
wire _entries_T_17; // @[TLB.scala:170:77]
wire _entries_T_16; // @[TLB.scala:170:77]
wire _entries_T_15; // @[TLB.scala:170:77]
wire _entries_T_14; // @[TLB.scala:170:77]
wire _entries_T_13; // @[TLB.scala:170:77]
wire _entries_T_12; // @[TLB.scala:170:77]
wire _entries_T_11; // @[TLB.scala:170:77]
wire _entries_T_10; // @[TLB.scala:170:77]
wire _entries_T_9; // @[TLB.scala:170:77]
wire _entries_T_8; // @[TLB.scala:170:77]
wire _entries_T_7; // @[TLB.scala:170:77]
wire _entries_T_6; // @[TLB.scala:170:77]
wire _entries_T_5; // @[TLB.scala:170:77]
wire _entries_T_4; // @[TLB.scala:170:77]
wire _entries_T_3; // @[TLB.scala:170:77]
wire _entries_T_2; // @[TLB.scala:170:77]
wire _entries_T_1; // @[TLB.scala:170:77]
wire [3:0][41:0] _GEN_32 = {{sectored_entries_0_0_data_3}, {sectored_entries_0_0_data_2}, {sectored_entries_0_0_data_1}, {sectored_entries_0_0_data_0}}; // @[TLB.scala:170:77, :339:29]
wire [41:0] _entries_WIRE_1 = _GEN_32[_entries_T]; // @[package.scala:163:13]
assign _entries_T_1 = _entries_WIRE_1[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_fragmented_superpage = _entries_T_1; // @[TLB.scala:170:77]
assign _entries_T_2 = _entries_WIRE_1[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_c = _entries_T_2; // @[TLB.scala:170:77]
assign _entries_T_3 = _entries_WIRE_1[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_eff = _entries_T_3; // @[TLB.scala:170:77]
assign _entries_T_4 = _entries_WIRE_1[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_paa = _entries_T_4; // @[TLB.scala:170:77]
assign _entries_T_5 = _entries_WIRE_1[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_pal = _entries_T_5; // @[TLB.scala:170:77]
assign _entries_T_6 = _entries_WIRE_1[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_ppp = _entries_T_6; // @[TLB.scala:170:77]
assign _entries_T_7 = _entries_WIRE_1[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_pr = _entries_T_7; // @[TLB.scala:170:77]
assign _entries_T_8 = _entries_WIRE_1[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_px = _entries_T_8; // @[TLB.scala:170:77]
assign _entries_T_9 = _entries_WIRE_1[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_pw = _entries_T_9; // @[TLB.scala:170:77]
assign _entries_T_10 = _entries_WIRE_1[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_hr = _entries_T_10; // @[TLB.scala:170:77]
assign _entries_T_11 = _entries_WIRE_1[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_hx = _entries_T_11; // @[TLB.scala:170:77]
assign _entries_T_12 = _entries_WIRE_1[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_hw = _entries_T_12; // @[TLB.scala:170:77]
assign _entries_T_13 = _entries_WIRE_1[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_sr = _entries_T_13; // @[TLB.scala:170:77]
assign _entries_T_14 = _entries_WIRE_1[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_sx = _entries_T_14; // @[TLB.scala:170:77]
assign _entries_T_15 = _entries_WIRE_1[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_sw = _entries_T_15; // @[TLB.scala:170:77]
assign _entries_T_16 = _entries_WIRE_1[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_gf = _entries_T_16; // @[TLB.scala:170:77]
assign _entries_T_17 = _entries_WIRE_1[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_pf = _entries_T_17; // @[TLB.scala:170:77]
assign _entries_T_18 = _entries_WIRE_1[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_ae_stage2 = _entries_T_18; // @[TLB.scala:170:77]
assign _entries_T_19 = _entries_WIRE_1[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_ae_final = _entries_T_19; // @[TLB.scala:170:77]
assign _entries_T_20 = _entries_WIRE_1[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_ae_ptw = _entries_T_20; // @[TLB.scala:170:77]
assign _entries_T_21 = _entries_WIRE_1[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_g = _entries_T_21; // @[TLB.scala:170:77]
assign _entries_T_22 = _entries_WIRE_1[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_u = _entries_T_22; // @[TLB.scala:170:77]
assign _entries_T_23 = _entries_WIRE_1[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_ppn = _entries_T_23; // @[TLB.scala:170:77]
wire [19:0] _entries_T_47; // @[TLB.scala:170:77]
wire _entries_T_46; // @[TLB.scala:170:77]
wire _entries_T_45; // @[TLB.scala:170:77]
wire _entries_T_44; // @[TLB.scala:170:77]
wire _entries_T_43; // @[TLB.scala:170:77]
wire _entries_T_42; // @[TLB.scala:170:77]
wire _entries_T_41; // @[TLB.scala:170:77]
wire _entries_T_40; // @[TLB.scala:170:77]
wire _entries_T_39; // @[TLB.scala:170:77]
wire _entries_T_38; // @[TLB.scala:170:77]
wire _entries_T_37; // @[TLB.scala:170:77]
wire _entries_T_36; // @[TLB.scala:170:77]
wire _entries_T_35; // @[TLB.scala:170:77]
wire _entries_T_34; // @[TLB.scala:170:77]
wire _entries_T_33; // @[TLB.scala:170:77]
wire _entries_T_32; // @[TLB.scala:170:77]
wire _entries_T_31; // @[TLB.scala:170:77]
wire _entries_T_30; // @[TLB.scala:170:77]
wire _entries_T_29; // @[TLB.scala:170:77]
wire _entries_T_28; // @[TLB.scala:170:77]
wire _entries_T_27; // @[TLB.scala:170:77]
wire _entries_T_26; // @[TLB.scala:170:77]
wire _entries_T_25; // @[TLB.scala:170:77]
wire [3:0][41:0] _GEN_33 = {{sectored_entries_0_1_data_3}, {sectored_entries_0_1_data_2}, {sectored_entries_0_1_data_1}, {sectored_entries_0_1_data_0}}; // @[TLB.scala:170:77, :339:29]
wire [41:0] _entries_WIRE_3 = _GEN_33[_entries_T_24]; // @[package.scala:163:13]
assign _entries_T_25 = _entries_WIRE_3[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_fragmented_superpage = _entries_T_25; // @[TLB.scala:170:77]
assign _entries_T_26 = _entries_WIRE_3[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_c = _entries_T_26; // @[TLB.scala:170:77]
assign _entries_T_27 = _entries_WIRE_3[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_eff = _entries_T_27; // @[TLB.scala:170:77]
assign _entries_T_28 = _entries_WIRE_3[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_paa = _entries_T_28; // @[TLB.scala:170:77]
assign _entries_T_29 = _entries_WIRE_3[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_pal = _entries_T_29; // @[TLB.scala:170:77]
assign _entries_T_30 = _entries_WIRE_3[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_ppp = _entries_T_30; // @[TLB.scala:170:77]
assign _entries_T_31 = _entries_WIRE_3[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_pr = _entries_T_31; // @[TLB.scala:170:77]
assign _entries_T_32 = _entries_WIRE_3[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_px = _entries_T_32; // @[TLB.scala:170:77]
assign _entries_T_33 = _entries_WIRE_3[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_pw = _entries_T_33; // @[TLB.scala:170:77]
assign _entries_T_34 = _entries_WIRE_3[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_hr = _entries_T_34; // @[TLB.scala:170:77]
assign _entries_T_35 = _entries_WIRE_3[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_hx = _entries_T_35; // @[TLB.scala:170:77]
assign _entries_T_36 = _entries_WIRE_3[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_hw = _entries_T_36; // @[TLB.scala:170:77]
assign _entries_T_37 = _entries_WIRE_3[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_sr = _entries_T_37; // @[TLB.scala:170:77]
assign _entries_T_38 = _entries_WIRE_3[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_sx = _entries_T_38; // @[TLB.scala:170:77]
assign _entries_T_39 = _entries_WIRE_3[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_sw = _entries_T_39; // @[TLB.scala:170:77]
assign _entries_T_40 = _entries_WIRE_3[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_gf = _entries_T_40; // @[TLB.scala:170:77]
assign _entries_T_41 = _entries_WIRE_3[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_pf = _entries_T_41; // @[TLB.scala:170:77]
assign _entries_T_42 = _entries_WIRE_3[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_ae_stage2 = _entries_T_42; // @[TLB.scala:170:77]
assign _entries_T_43 = _entries_WIRE_3[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_ae_final = _entries_T_43; // @[TLB.scala:170:77]
assign _entries_T_44 = _entries_WIRE_3[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_ae_ptw = _entries_T_44; // @[TLB.scala:170:77]
assign _entries_T_45 = _entries_WIRE_3[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_g = _entries_T_45; // @[TLB.scala:170:77]
assign _entries_T_46 = _entries_WIRE_3[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_u = _entries_T_46; // @[TLB.scala:170:77]
assign _entries_T_47 = _entries_WIRE_3[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_2_ppn = _entries_T_47; // @[TLB.scala:170:77]
wire [19:0] _entries_T_71; // @[TLB.scala:170:77]
wire _entries_T_70; // @[TLB.scala:170:77]
wire _entries_T_69; // @[TLB.scala:170:77]
wire _entries_T_68; // @[TLB.scala:170:77]
wire _entries_T_67; // @[TLB.scala:170:77]
wire _entries_T_66; // @[TLB.scala:170:77]
wire _entries_T_65; // @[TLB.scala:170:77]
wire _entries_T_64; // @[TLB.scala:170:77]
wire _entries_T_63; // @[TLB.scala:170:77]
wire _entries_T_62; // @[TLB.scala:170:77]
wire _entries_T_61; // @[TLB.scala:170:77]
wire _entries_T_60; // @[TLB.scala:170:77]
wire _entries_T_59; // @[TLB.scala:170:77]
wire _entries_T_58; // @[TLB.scala:170:77]
wire _entries_T_57; // @[TLB.scala:170:77]
wire _entries_T_56; // @[TLB.scala:170:77]
wire _entries_T_55; // @[TLB.scala:170:77]
wire _entries_T_54; // @[TLB.scala:170:77]
wire _entries_T_53; // @[TLB.scala:170:77]
wire _entries_T_52; // @[TLB.scala:170:77]
wire _entries_T_51; // @[TLB.scala:170:77]
wire _entries_T_50; // @[TLB.scala:170:77]
wire _entries_T_49; // @[TLB.scala:170:77]
wire [3:0][41:0] _GEN_34 = {{sectored_entries_0_2_data_3}, {sectored_entries_0_2_data_2}, {sectored_entries_0_2_data_1}, {sectored_entries_0_2_data_0}}; // @[TLB.scala:170:77, :339:29]
wire [41:0] _entries_WIRE_5 = _GEN_34[_entries_T_48]; // @[package.scala:163:13]
assign _entries_T_49 = _entries_WIRE_5[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_fragmented_superpage = _entries_T_49; // @[TLB.scala:170:77]
assign _entries_T_50 = _entries_WIRE_5[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_c = _entries_T_50; // @[TLB.scala:170:77]
assign _entries_T_51 = _entries_WIRE_5[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_eff = _entries_T_51; // @[TLB.scala:170:77]
assign _entries_T_52 = _entries_WIRE_5[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_paa = _entries_T_52; // @[TLB.scala:170:77]
assign _entries_T_53 = _entries_WIRE_5[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_pal = _entries_T_53; // @[TLB.scala:170:77]
assign _entries_T_54 = _entries_WIRE_5[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_ppp = _entries_T_54; // @[TLB.scala:170:77]
assign _entries_T_55 = _entries_WIRE_5[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_pr = _entries_T_55; // @[TLB.scala:170:77]
assign _entries_T_56 = _entries_WIRE_5[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_px = _entries_T_56; // @[TLB.scala:170:77]
assign _entries_T_57 = _entries_WIRE_5[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_pw = _entries_T_57; // @[TLB.scala:170:77]
assign _entries_T_58 = _entries_WIRE_5[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_hr = _entries_T_58; // @[TLB.scala:170:77]
assign _entries_T_59 = _entries_WIRE_5[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_hx = _entries_T_59; // @[TLB.scala:170:77]
assign _entries_T_60 = _entries_WIRE_5[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_hw = _entries_T_60; // @[TLB.scala:170:77]
assign _entries_T_61 = _entries_WIRE_5[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_sr = _entries_T_61; // @[TLB.scala:170:77]
assign _entries_T_62 = _entries_WIRE_5[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_sx = _entries_T_62; // @[TLB.scala:170:77]
assign _entries_T_63 = _entries_WIRE_5[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_sw = _entries_T_63; // @[TLB.scala:170:77]
assign _entries_T_64 = _entries_WIRE_5[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_gf = _entries_T_64; // @[TLB.scala:170:77]
assign _entries_T_65 = _entries_WIRE_5[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_pf = _entries_T_65; // @[TLB.scala:170:77]
assign _entries_T_66 = _entries_WIRE_5[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_ae_stage2 = _entries_T_66; // @[TLB.scala:170:77]
assign _entries_T_67 = _entries_WIRE_5[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_ae_final = _entries_T_67; // @[TLB.scala:170:77]
assign _entries_T_68 = _entries_WIRE_5[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_ae_ptw = _entries_T_68; // @[TLB.scala:170:77]
assign _entries_T_69 = _entries_WIRE_5[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_g = _entries_T_69; // @[TLB.scala:170:77]
assign _entries_T_70 = _entries_WIRE_5[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_u = _entries_T_70; // @[TLB.scala:170:77]
assign _entries_T_71 = _entries_WIRE_5[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_4_ppn = _entries_T_71; // @[TLB.scala:170:77]
wire [19:0] _entries_T_95; // @[TLB.scala:170:77]
wire _entries_T_94; // @[TLB.scala:170:77]
wire _entries_T_93; // @[TLB.scala:170:77]
wire _entries_T_92; // @[TLB.scala:170:77]
wire _entries_T_91; // @[TLB.scala:170:77]
wire _entries_T_90; // @[TLB.scala:170:77]
wire _entries_T_89; // @[TLB.scala:170:77]
wire _entries_T_88; // @[TLB.scala:170:77]
wire _entries_T_87; // @[TLB.scala:170:77]
wire _entries_T_86; // @[TLB.scala:170:77]
wire _entries_T_85; // @[TLB.scala:170:77]
wire _entries_T_84; // @[TLB.scala:170:77]
wire _entries_T_83; // @[TLB.scala:170:77]
wire _entries_T_82; // @[TLB.scala:170:77]
wire _entries_T_81; // @[TLB.scala:170:77]
wire _entries_T_80; // @[TLB.scala:170:77]
wire _entries_T_79; // @[TLB.scala:170:77]
wire _entries_T_78; // @[TLB.scala:170:77]
wire _entries_T_77; // @[TLB.scala:170:77]
wire _entries_T_76; // @[TLB.scala:170:77]
wire _entries_T_75; // @[TLB.scala:170:77]
wire _entries_T_74; // @[TLB.scala:170:77]
wire _entries_T_73; // @[TLB.scala:170:77]
wire [3:0][41:0] _GEN_35 = {{sectored_entries_0_3_data_3}, {sectored_entries_0_3_data_2}, {sectored_entries_0_3_data_1}, {sectored_entries_0_3_data_0}}; // @[TLB.scala:170:77, :339:29]
wire [41:0] _entries_WIRE_7 = _GEN_35[_entries_T_72]; // @[package.scala:163:13]
assign _entries_T_73 = _entries_WIRE_7[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_fragmented_superpage = _entries_T_73; // @[TLB.scala:170:77]
assign _entries_T_74 = _entries_WIRE_7[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_c = _entries_T_74; // @[TLB.scala:170:77]
assign _entries_T_75 = _entries_WIRE_7[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_eff = _entries_T_75; // @[TLB.scala:170:77]
assign _entries_T_76 = _entries_WIRE_7[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_paa = _entries_T_76; // @[TLB.scala:170:77]
assign _entries_T_77 = _entries_WIRE_7[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_pal = _entries_T_77; // @[TLB.scala:170:77]
assign _entries_T_78 = _entries_WIRE_7[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_ppp = _entries_T_78; // @[TLB.scala:170:77]
assign _entries_T_79 = _entries_WIRE_7[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_pr = _entries_T_79; // @[TLB.scala:170:77]
assign _entries_T_80 = _entries_WIRE_7[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_px = _entries_T_80; // @[TLB.scala:170:77]
assign _entries_T_81 = _entries_WIRE_7[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_pw = _entries_T_81; // @[TLB.scala:170:77]
assign _entries_T_82 = _entries_WIRE_7[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_hr = _entries_T_82; // @[TLB.scala:170:77]
assign _entries_T_83 = _entries_WIRE_7[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_hx = _entries_T_83; // @[TLB.scala:170:77]
assign _entries_T_84 = _entries_WIRE_7[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_hw = _entries_T_84; // @[TLB.scala:170:77]
assign _entries_T_85 = _entries_WIRE_7[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_sr = _entries_T_85; // @[TLB.scala:170:77]
assign _entries_T_86 = _entries_WIRE_7[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_sx = _entries_T_86; // @[TLB.scala:170:77]
assign _entries_T_87 = _entries_WIRE_7[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_sw = _entries_T_87; // @[TLB.scala:170:77]
assign _entries_T_88 = _entries_WIRE_7[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_gf = _entries_T_88; // @[TLB.scala:170:77]
assign _entries_T_89 = _entries_WIRE_7[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_pf = _entries_T_89; // @[TLB.scala:170:77]
assign _entries_T_90 = _entries_WIRE_7[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_ae_stage2 = _entries_T_90; // @[TLB.scala:170:77]
assign _entries_T_91 = _entries_WIRE_7[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_ae_final = _entries_T_91; // @[TLB.scala:170:77]
assign _entries_T_92 = _entries_WIRE_7[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_ae_ptw = _entries_T_92; // @[TLB.scala:170:77]
assign _entries_T_93 = _entries_WIRE_7[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_g = _entries_T_93; // @[TLB.scala:170:77]
assign _entries_T_94 = _entries_WIRE_7[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_u = _entries_T_94; // @[TLB.scala:170:77]
assign _entries_T_95 = _entries_WIRE_7[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_6_ppn = _entries_T_95; // @[TLB.scala:170:77]
wire [19:0] _entries_T_119; // @[TLB.scala:170:77]
wire _entries_T_118; // @[TLB.scala:170:77]
wire _entries_T_117; // @[TLB.scala:170:77]
wire _entries_T_116; // @[TLB.scala:170:77]
wire _entries_T_115; // @[TLB.scala:170:77]
wire _entries_T_114; // @[TLB.scala:170:77]
wire _entries_T_113; // @[TLB.scala:170:77]
wire _entries_T_112; // @[TLB.scala:170:77]
wire _entries_T_111; // @[TLB.scala:170:77]
wire _entries_T_110; // @[TLB.scala:170:77]
wire _entries_T_109; // @[TLB.scala:170:77]
wire _entries_T_108; // @[TLB.scala:170:77]
wire _entries_T_107; // @[TLB.scala:170:77]
wire _entries_T_106; // @[TLB.scala:170:77]
wire _entries_T_105; // @[TLB.scala:170:77]
wire _entries_T_104; // @[TLB.scala:170:77]
wire _entries_T_103; // @[TLB.scala:170:77]
wire _entries_T_102; // @[TLB.scala:170:77]
wire _entries_T_101; // @[TLB.scala:170:77]
wire _entries_T_100; // @[TLB.scala:170:77]
wire _entries_T_99; // @[TLB.scala:170:77]
wire _entries_T_98; // @[TLB.scala:170:77]
wire _entries_T_97; // @[TLB.scala:170:77]
wire [3:0][41:0] _GEN_36 = {{sectored_entries_0_4_data_3}, {sectored_entries_0_4_data_2}, {sectored_entries_0_4_data_1}, {sectored_entries_0_4_data_0}}; // @[TLB.scala:170:77, :339:29]
wire [41:0] _entries_WIRE_9 = _GEN_36[_entries_T_96]; // @[package.scala:163:13]
assign _entries_T_97 = _entries_WIRE_9[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_fragmented_superpage = _entries_T_97; // @[TLB.scala:170:77]
assign _entries_T_98 = _entries_WIRE_9[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_c = _entries_T_98; // @[TLB.scala:170:77]
assign _entries_T_99 = _entries_WIRE_9[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_eff = _entries_T_99; // @[TLB.scala:170:77]
assign _entries_T_100 = _entries_WIRE_9[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_paa = _entries_T_100; // @[TLB.scala:170:77]
assign _entries_T_101 = _entries_WIRE_9[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_pal = _entries_T_101; // @[TLB.scala:170:77]
assign _entries_T_102 = _entries_WIRE_9[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_ppp = _entries_T_102; // @[TLB.scala:170:77]
assign _entries_T_103 = _entries_WIRE_9[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_pr = _entries_T_103; // @[TLB.scala:170:77]
assign _entries_T_104 = _entries_WIRE_9[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_px = _entries_T_104; // @[TLB.scala:170:77]
assign _entries_T_105 = _entries_WIRE_9[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_pw = _entries_T_105; // @[TLB.scala:170:77]
assign _entries_T_106 = _entries_WIRE_9[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_hr = _entries_T_106; // @[TLB.scala:170:77]
assign _entries_T_107 = _entries_WIRE_9[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_hx = _entries_T_107; // @[TLB.scala:170:77]
assign _entries_T_108 = _entries_WIRE_9[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_hw = _entries_T_108; // @[TLB.scala:170:77]
assign _entries_T_109 = _entries_WIRE_9[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_sr = _entries_T_109; // @[TLB.scala:170:77]
assign _entries_T_110 = _entries_WIRE_9[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_sx = _entries_T_110; // @[TLB.scala:170:77]
assign _entries_T_111 = _entries_WIRE_9[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_sw = _entries_T_111; // @[TLB.scala:170:77]
assign _entries_T_112 = _entries_WIRE_9[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_gf = _entries_T_112; // @[TLB.scala:170:77]
assign _entries_T_113 = _entries_WIRE_9[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_pf = _entries_T_113; // @[TLB.scala:170:77]
assign _entries_T_114 = _entries_WIRE_9[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_ae_stage2 = _entries_T_114; // @[TLB.scala:170:77]
assign _entries_T_115 = _entries_WIRE_9[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_ae_final = _entries_T_115; // @[TLB.scala:170:77]
assign _entries_T_116 = _entries_WIRE_9[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_ae_ptw = _entries_T_116; // @[TLB.scala:170:77]
assign _entries_T_117 = _entries_WIRE_9[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_g = _entries_T_117; // @[TLB.scala:170:77]
assign _entries_T_118 = _entries_WIRE_9[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_u = _entries_T_118; // @[TLB.scala:170:77]
assign _entries_T_119 = _entries_WIRE_9[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_8_ppn = _entries_T_119; // @[TLB.scala:170:77]
wire [19:0] _entries_T_143; // @[TLB.scala:170:77]
wire _entries_T_142; // @[TLB.scala:170:77]
wire _entries_T_141; // @[TLB.scala:170:77]
wire _entries_T_140; // @[TLB.scala:170:77]
wire _entries_T_139; // @[TLB.scala:170:77]
wire _entries_T_138; // @[TLB.scala:170:77]
wire _entries_T_137; // @[TLB.scala:170:77]
wire _entries_T_136; // @[TLB.scala:170:77]
wire _entries_T_135; // @[TLB.scala:170:77]
wire _entries_T_134; // @[TLB.scala:170:77]
wire _entries_T_133; // @[TLB.scala:170:77]
wire _entries_T_132; // @[TLB.scala:170:77]
wire _entries_T_131; // @[TLB.scala:170:77]
wire _entries_T_130; // @[TLB.scala:170:77]
wire _entries_T_129; // @[TLB.scala:170:77]
wire _entries_T_128; // @[TLB.scala:170:77]
wire _entries_T_127; // @[TLB.scala:170:77]
wire _entries_T_126; // @[TLB.scala:170:77]
wire _entries_T_125; // @[TLB.scala:170:77]
wire _entries_T_124; // @[TLB.scala:170:77]
wire _entries_T_123; // @[TLB.scala:170:77]
wire _entries_T_122; // @[TLB.scala:170:77]
wire _entries_T_121; // @[TLB.scala:170:77]
wire [3:0][41:0] _GEN_37 = {{sectored_entries_0_5_data_3}, {sectored_entries_0_5_data_2}, {sectored_entries_0_5_data_1}, {sectored_entries_0_5_data_0}}; // @[TLB.scala:170:77, :339:29]
wire [41:0] _entries_WIRE_11 = _GEN_37[_entries_T_120]; // @[package.scala:163:13]
assign _entries_T_121 = _entries_WIRE_11[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_fragmented_superpage = _entries_T_121; // @[TLB.scala:170:77]
assign _entries_T_122 = _entries_WIRE_11[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_c = _entries_T_122; // @[TLB.scala:170:77]
assign _entries_T_123 = _entries_WIRE_11[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_eff = _entries_T_123; // @[TLB.scala:170:77]
assign _entries_T_124 = _entries_WIRE_11[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_paa = _entries_T_124; // @[TLB.scala:170:77]
assign _entries_T_125 = _entries_WIRE_11[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_pal = _entries_T_125; // @[TLB.scala:170:77]
assign _entries_T_126 = _entries_WIRE_11[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_ppp = _entries_T_126; // @[TLB.scala:170:77]
assign _entries_T_127 = _entries_WIRE_11[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_pr = _entries_T_127; // @[TLB.scala:170:77]
assign _entries_T_128 = _entries_WIRE_11[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_px = _entries_T_128; // @[TLB.scala:170:77]
assign _entries_T_129 = _entries_WIRE_11[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_pw = _entries_T_129; // @[TLB.scala:170:77]
assign _entries_T_130 = _entries_WIRE_11[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_hr = _entries_T_130; // @[TLB.scala:170:77]
assign _entries_T_131 = _entries_WIRE_11[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_hx = _entries_T_131; // @[TLB.scala:170:77]
assign _entries_T_132 = _entries_WIRE_11[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_hw = _entries_T_132; // @[TLB.scala:170:77]
assign _entries_T_133 = _entries_WIRE_11[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_sr = _entries_T_133; // @[TLB.scala:170:77]
assign _entries_T_134 = _entries_WIRE_11[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_sx = _entries_T_134; // @[TLB.scala:170:77]
assign _entries_T_135 = _entries_WIRE_11[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_sw = _entries_T_135; // @[TLB.scala:170:77]
assign _entries_T_136 = _entries_WIRE_11[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_gf = _entries_T_136; // @[TLB.scala:170:77]
assign _entries_T_137 = _entries_WIRE_11[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_pf = _entries_T_137; // @[TLB.scala:170:77]
assign _entries_T_138 = _entries_WIRE_11[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_ae_stage2 = _entries_T_138; // @[TLB.scala:170:77]
assign _entries_T_139 = _entries_WIRE_11[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_ae_final = _entries_T_139; // @[TLB.scala:170:77]
assign _entries_T_140 = _entries_WIRE_11[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_ae_ptw = _entries_T_140; // @[TLB.scala:170:77]
assign _entries_T_141 = _entries_WIRE_11[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_g = _entries_T_141; // @[TLB.scala:170:77]
assign _entries_T_142 = _entries_WIRE_11[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_u = _entries_T_142; // @[TLB.scala:170:77]
assign _entries_T_143 = _entries_WIRE_11[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_10_ppn = _entries_T_143; // @[TLB.scala:170:77]
wire [19:0] _entries_T_167; // @[TLB.scala:170:77]
wire _entries_T_166; // @[TLB.scala:170:77]
wire _entries_T_165; // @[TLB.scala:170:77]
wire _entries_T_164; // @[TLB.scala:170:77]
wire _entries_T_163; // @[TLB.scala:170:77]
wire _entries_T_162; // @[TLB.scala:170:77]
wire _entries_T_161; // @[TLB.scala:170:77]
wire _entries_T_160; // @[TLB.scala:170:77]
wire _entries_T_159; // @[TLB.scala:170:77]
wire _entries_T_158; // @[TLB.scala:170:77]
wire _entries_T_157; // @[TLB.scala:170:77]
wire _entries_T_156; // @[TLB.scala:170:77]
wire _entries_T_155; // @[TLB.scala:170:77]
wire _entries_T_154; // @[TLB.scala:170:77]
wire _entries_T_153; // @[TLB.scala:170:77]
wire _entries_T_152; // @[TLB.scala:170:77]
wire _entries_T_151; // @[TLB.scala:170:77]
wire _entries_T_150; // @[TLB.scala:170:77]
wire _entries_T_149; // @[TLB.scala:170:77]
wire _entries_T_148; // @[TLB.scala:170:77]
wire _entries_T_147; // @[TLB.scala:170:77]
wire _entries_T_146; // @[TLB.scala:170:77]
wire _entries_T_145; // @[TLB.scala:170:77]
wire [3:0][41:0] _GEN_38 = {{sectored_entries_0_6_data_3}, {sectored_entries_0_6_data_2}, {sectored_entries_0_6_data_1}, {sectored_entries_0_6_data_0}}; // @[TLB.scala:170:77, :339:29]
wire [41:0] _entries_WIRE_13 = _GEN_38[_entries_T_144]; // @[package.scala:163:13]
assign _entries_T_145 = _entries_WIRE_13[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_fragmented_superpage = _entries_T_145; // @[TLB.scala:170:77]
assign _entries_T_146 = _entries_WIRE_13[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_c = _entries_T_146; // @[TLB.scala:170:77]
assign _entries_T_147 = _entries_WIRE_13[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_eff = _entries_T_147; // @[TLB.scala:170:77]
assign _entries_T_148 = _entries_WIRE_13[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_paa = _entries_T_148; // @[TLB.scala:170:77]
assign _entries_T_149 = _entries_WIRE_13[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_pal = _entries_T_149; // @[TLB.scala:170:77]
assign _entries_T_150 = _entries_WIRE_13[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_ppp = _entries_T_150; // @[TLB.scala:170:77]
assign _entries_T_151 = _entries_WIRE_13[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_pr = _entries_T_151; // @[TLB.scala:170:77]
assign _entries_T_152 = _entries_WIRE_13[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_px = _entries_T_152; // @[TLB.scala:170:77]
assign _entries_T_153 = _entries_WIRE_13[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_pw = _entries_T_153; // @[TLB.scala:170:77]
assign _entries_T_154 = _entries_WIRE_13[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_hr = _entries_T_154; // @[TLB.scala:170:77]
assign _entries_T_155 = _entries_WIRE_13[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_hx = _entries_T_155; // @[TLB.scala:170:77]
assign _entries_T_156 = _entries_WIRE_13[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_hw = _entries_T_156; // @[TLB.scala:170:77]
assign _entries_T_157 = _entries_WIRE_13[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_sr = _entries_T_157; // @[TLB.scala:170:77]
assign _entries_T_158 = _entries_WIRE_13[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_sx = _entries_T_158; // @[TLB.scala:170:77]
assign _entries_T_159 = _entries_WIRE_13[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_sw = _entries_T_159; // @[TLB.scala:170:77]
assign _entries_T_160 = _entries_WIRE_13[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_gf = _entries_T_160; // @[TLB.scala:170:77]
assign _entries_T_161 = _entries_WIRE_13[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_pf = _entries_T_161; // @[TLB.scala:170:77]
assign _entries_T_162 = _entries_WIRE_13[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_ae_stage2 = _entries_T_162; // @[TLB.scala:170:77]
assign _entries_T_163 = _entries_WIRE_13[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_ae_final = _entries_T_163; // @[TLB.scala:170:77]
assign _entries_T_164 = _entries_WIRE_13[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_ae_ptw = _entries_T_164; // @[TLB.scala:170:77]
assign _entries_T_165 = _entries_WIRE_13[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_g = _entries_T_165; // @[TLB.scala:170:77]
assign _entries_T_166 = _entries_WIRE_13[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_u = _entries_T_166; // @[TLB.scala:170:77]
assign _entries_T_167 = _entries_WIRE_13[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_12_ppn = _entries_T_167; // @[TLB.scala:170:77]
wire [19:0] _entries_T_191; // @[TLB.scala:170:77]
wire _entries_T_190; // @[TLB.scala:170:77]
wire _entries_T_189; // @[TLB.scala:170:77]
wire _entries_T_188; // @[TLB.scala:170:77]
wire _entries_T_187; // @[TLB.scala:170:77]
wire _entries_T_186; // @[TLB.scala:170:77]
wire _entries_T_185; // @[TLB.scala:170:77]
wire _entries_T_184; // @[TLB.scala:170:77]
wire _entries_T_183; // @[TLB.scala:170:77]
wire _entries_T_182; // @[TLB.scala:170:77]
wire _entries_T_181; // @[TLB.scala:170:77]
wire _entries_T_180; // @[TLB.scala:170:77]
wire _entries_T_179; // @[TLB.scala:170:77]
wire _entries_T_178; // @[TLB.scala:170:77]
wire _entries_T_177; // @[TLB.scala:170:77]
wire _entries_T_176; // @[TLB.scala:170:77]
wire _entries_T_175; // @[TLB.scala:170:77]
wire _entries_T_174; // @[TLB.scala:170:77]
wire _entries_T_173; // @[TLB.scala:170:77]
wire _entries_T_172; // @[TLB.scala:170:77]
wire _entries_T_171; // @[TLB.scala:170:77]
wire _entries_T_170; // @[TLB.scala:170:77]
wire _entries_T_169; // @[TLB.scala:170:77]
wire [3:0][41:0] _GEN_39 = {{sectored_entries_0_7_data_3}, {sectored_entries_0_7_data_2}, {sectored_entries_0_7_data_1}, {sectored_entries_0_7_data_0}}; // @[TLB.scala:170:77, :339:29]
wire [41:0] _entries_WIRE_15 = _GEN_39[_entries_T_168]; // @[package.scala:163:13]
assign _entries_T_169 = _entries_WIRE_15[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_fragmented_superpage = _entries_T_169; // @[TLB.scala:170:77]
assign _entries_T_170 = _entries_WIRE_15[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_c = _entries_T_170; // @[TLB.scala:170:77]
assign _entries_T_171 = _entries_WIRE_15[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_eff = _entries_T_171; // @[TLB.scala:170:77]
assign _entries_T_172 = _entries_WIRE_15[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_paa = _entries_T_172; // @[TLB.scala:170:77]
assign _entries_T_173 = _entries_WIRE_15[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_pal = _entries_T_173; // @[TLB.scala:170:77]
assign _entries_T_174 = _entries_WIRE_15[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_ppp = _entries_T_174; // @[TLB.scala:170:77]
assign _entries_T_175 = _entries_WIRE_15[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_pr = _entries_T_175; // @[TLB.scala:170:77]
assign _entries_T_176 = _entries_WIRE_15[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_px = _entries_T_176; // @[TLB.scala:170:77]
assign _entries_T_177 = _entries_WIRE_15[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_pw = _entries_T_177; // @[TLB.scala:170:77]
assign _entries_T_178 = _entries_WIRE_15[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_hr = _entries_T_178; // @[TLB.scala:170:77]
assign _entries_T_179 = _entries_WIRE_15[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_hx = _entries_T_179; // @[TLB.scala:170:77]
assign _entries_T_180 = _entries_WIRE_15[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_hw = _entries_T_180; // @[TLB.scala:170:77]
assign _entries_T_181 = _entries_WIRE_15[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_sr = _entries_T_181; // @[TLB.scala:170:77]
assign _entries_T_182 = _entries_WIRE_15[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_sx = _entries_T_182; // @[TLB.scala:170:77]
assign _entries_T_183 = _entries_WIRE_15[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_sw = _entries_T_183; // @[TLB.scala:170:77]
assign _entries_T_184 = _entries_WIRE_15[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_gf = _entries_T_184; // @[TLB.scala:170:77]
assign _entries_T_185 = _entries_WIRE_15[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_pf = _entries_T_185; // @[TLB.scala:170:77]
assign _entries_T_186 = _entries_WIRE_15[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_ae_stage2 = _entries_T_186; // @[TLB.scala:170:77]
assign _entries_T_187 = _entries_WIRE_15[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_ae_final = _entries_T_187; // @[TLB.scala:170:77]
assign _entries_T_188 = _entries_WIRE_15[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_ae_ptw = _entries_T_188; // @[TLB.scala:170:77]
assign _entries_T_189 = _entries_WIRE_15[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_g = _entries_T_189; // @[TLB.scala:170:77]
assign _entries_T_190 = _entries_WIRE_15[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_u = _entries_T_190; // @[TLB.scala:170:77]
assign _entries_T_191 = _entries_WIRE_15[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_14_ppn = _entries_T_191; // @[TLB.scala:170:77]
wire [19:0] _entries_T_214; // @[TLB.scala:170:77]
wire _entries_T_213; // @[TLB.scala:170:77]
wire _entries_T_212; // @[TLB.scala:170:77]
wire _entries_T_211; // @[TLB.scala:170:77]
wire _entries_T_210; // @[TLB.scala:170:77]
wire _entries_T_209; // @[TLB.scala:170:77]
wire _entries_T_208; // @[TLB.scala:170:77]
wire _entries_T_207; // @[TLB.scala:170:77]
wire _entries_T_206; // @[TLB.scala:170:77]
wire _entries_T_205; // @[TLB.scala:170:77]
wire _entries_T_204; // @[TLB.scala:170:77]
wire _entries_T_203; // @[TLB.scala:170:77]
wire _entries_T_202; // @[TLB.scala:170:77]
wire _entries_T_201; // @[TLB.scala:170:77]
wire _entries_T_200; // @[TLB.scala:170:77]
wire _entries_T_199; // @[TLB.scala:170:77]
wire _entries_T_198; // @[TLB.scala:170:77]
wire _entries_T_197; // @[TLB.scala:170:77]
wire _entries_T_196; // @[TLB.scala:170:77]
wire _entries_T_195; // @[TLB.scala:170:77]
wire _entries_T_194; // @[TLB.scala:170:77]
wire _entries_T_193; // @[TLB.scala:170:77]
wire _entries_T_192; // @[TLB.scala:170:77]
assign _entries_T_192 = _entries_WIRE_17[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_fragmented_superpage = _entries_T_192; // @[TLB.scala:170:77]
assign _entries_T_193 = _entries_WIRE_17[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_c = _entries_T_193; // @[TLB.scala:170:77]
assign _entries_T_194 = _entries_WIRE_17[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_eff = _entries_T_194; // @[TLB.scala:170:77]
assign _entries_T_195 = _entries_WIRE_17[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_paa = _entries_T_195; // @[TLB.scala:170:77]
assign _entries_T_196 = _entries_WIRE_17[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_pal = _entries_T_196; // @[TLB.scala:170:77]
assign _entries_T_197 = _entries_WIRE_17[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_ppp = _entries_T_197; // @[TLB.scala:170:77]
assign _entries_T_198 = _entries_WIRE_17[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_pr = _entries_T_198; // @[TLB.scala:170:77]
assign _entries_T_199 = _entries_WIRE_17[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_px = _entries_T_199; // @[TLB.scala:170:77]
assign _entries_T_200 = _entries_WIRE_17[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_pw = _entries_T_200; // @[TLB.scala:170:77]
assign _entries_T_201 = _entries_WIRE_17[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_hr = _entries_T_201; // @[TLB.scala:170:77]
assign _entries_T_202 = _entries_WIRE_17[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_hx = _entries_T_202; // @[TLB.scala:170:77]
assign _entries_T_203 = _entries_WIRE_17[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_hw = _entries_T_203; // @[TLB.scala:170:77]
assign _entries_T_204 = _entries_WIRE_17[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_sr = _entries_T_204; // @[TLB.scala:170:77]
assign _entries_T_205 = _entries_WIRE_17[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_sx = _entries_T_205; // @[TLB.scala:170:77]
assign _entries_T_206 = _entries_WIRE_17[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_sw = _entries_T_206; // @[TLB.scala:170:77]
assign _entries_T_207 = _entries_WIRE_17[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_gf = _entries_T_207; // @[TLB.scala:170:77]
assign _entries_T_208 = _entries_WIRE_17[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_pf = _entries_T_208; // @[TLB.scala:170:77]
assign _entries_T_209 = _entries_WIRE_17[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_ae_stage2 = _entries_T_209; // @[TLB.scala:170:77]
assign _entries_T_210 = _entries_WIRE_17[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_ae_final = _entries_T_210; // @[TLB.scala:170:77]
assign _entries_T_211 = _entries_WIRE_17[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_ae_ptw = _entries_T_211; // @[TLB.scala:170:77]
assign _entries_T_212 = _entries_WIRE_17[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_g = _entries_T_212; // @[TLB.scala:170:77]
assign _entries_T_213 = _entries_WIRE_17[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_u = _entries_T_213; // @[TLB.scala:170:77]
assign _entries_T_214 = _entries_WIRE_17[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_16_ppn = _entries_T_214; // @[TLB.scala:170:77]
wire [19:0] _entries_T_237; // @[TLB.scala:170:77]
wire _entries_T_236; // @[TLB.scala:170:77]
wire _entries_T_235; // @[TLB.scala:170:77]
wire _entries_T_234; // @[TLB.scala:170:77]
wire _entries_T_233; // @[TLB.scala:170:77]
wire _entries_T_232; // @[TLB.scala:170:77]
wire _entries_T_231; // @[TLB.scala:170:77]
wire _entries_T_230; // @[TLB.scala:170:77]
wire _entries_T_229; // @[TLB.scala:170:77]
wire _entries_T_228; // @[TLB.scala:170:77]
wire _entries_T_227; // @[TLB.scala:170:77]
wire _entries_T_226; // @[TLB.scala:170:77]
wire _entries_T_225; // @[TLB.scala:170:77]
wire _entries_T_224; // @[TLB.scala:170:77]
wire _entries_T_223; // @[TLB.scala:170:77]
wire _entries_T_222; // @[TLB.scala:170:77]
wire _entries_T_221; // @[TLB.scala:170:77]
wire _entries_T_220; // @[TLB.scala:170:77]
wire _entries_T_219; // @[TLB.scala:170:77]
wire _entries_T_218; // @[TLB.scala:170:77]
wire _entries_T_217; // @[TLB.scala:170:77]
wire _entries_T_216; // @[TLB.scala:170:77]
wire _entries_T_215; // @[TLB.scala:170:77]
assign _entries_T_215 = _entries_WIRE_19[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_fragmented_superpage = _entries_T_215; // @[TLB.scala:170:77]
assign _entries_T_216 = _entries_WIRE_19[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_c = _entries_T_216; // @[TLB.scala:170:77]
assign _entries_T_217 = _entries_WIRE_19[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_eff = _entries_T_217; // @[TLB.scala:170:77]
assign _entries_T_218 = _entries_WIRE_19[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_paa = _entries_T_218; // @[TLB.scala:170:77]
assign _entries_T_219 = _entries_WIRE_19[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_pal = _entries_T_219; // @[TLB.scala:170:77]
assign _entries_T_220 = _entries_WIRE_19[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_ppp = _entries_T_220; // @[TLB.scala:170:77]
assign _entries_T_221 = _entries_WIRE_19[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_pr = _entries_T_221; // @[TLB.scala:170:77]
assign _entries_T_222 = _entries_WIRE_19[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_px = _entries_T_222; // @[TLB.scala:170:77]
assign _entries_T_223 = _entries_WIRE_19[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_pw = _entries_T_223; // @[TLB.scala:170:77]
assign _entries_T_224 = _entries_WIRE_19[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_hr = _entries_T_224; // @[TLB.scala:170:77]
assign _entries_T_225 = _entries_WIRE_19[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_hx = _entries_T_225; // @[TLB.scala:170:77]
assign _entries_T_226 = _entries_WIRE_19[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_hw = _entries_T_226; // @[TLB.scala:170:77]
assign _entries_T_227 = _entries_WIRE_19[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_sr = _entries_T_227; // @[TLB.scala:170:77]
assign _entries_T_228 = _entries_WIRE_19[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_sx = _entries_T_228; // @[TLB.scala:170:77]
assign _entries_T_229 = _entries_WIRE_19[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_sw = _entries_T_229; // @[TLB.scala:170:77]
assign _entries_T_230 = _entries_WIRE_19[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_gf = _entries_T_230; // @[TLB.scala:170:77]
assign _entries_T_231 = _entries_WIRE_19[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_pf = _entries_T_231; // @[TLB.scala:170:77]
assign _entries_T_232 = _entries_WIRE_19[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_ae_stage2 = _entries_T_232; // @[TLB.scala:170:77]
assign _entries_T_233 = _entries_WIRE_19[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_ae_final = _entries_T_233; // @[TLB.scala:170:77]
assign _entries_T_234 = _entries_WIRE_19[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_ae_ptw = _entries_T_234; // @[TLB.scala:170:77]
assign _entries_T_235 = _entries_WIRE_19[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_g = _entries_T_235; // @[TLB.scala:170:77]
assign _entries_T_236 = _entries_WIRE_19[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_u = _entries_T_236; // @[TLB.scala:170:77]
assign _entries_T_237 = _entries_WIRE_19[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_18_ppn = _entries_T_237; // @[TLB.scala:170:77]
wire [19:0] _entries_T_260; // @[TLB.scala:170:77]
wire _entries_T_259; // @[TLB.scala:170:77]
wire _entries_T_258; // @[TLB.scala:170:77]
wire _entries_T_257; // @[TLB.scala:170:77]
wire _entries_T_256; // @[TLB.scala:170:77]
wire _entries_T_255; // @[TLB.scala:170:77]
wire _entries_T_254; // @[TLB.scala:170:77]
wire _entries_T_253; // @[TLB.scala:170:77]
wire _entries_T_252; // @[TLB.scala:170:77]
wire _entries_T_251; // @[TLB.scala:170:77]
wire _entries_T_250; // @[TLB.scala:170:77]
wire _entries_T_249; // @[TLB.scala:170:77]
wire _entries_T_248; // @[TLB.scala:170:77]
wire _entries_T_247; // @[TLB.scala:170:77]
wire _entries_T_246; // @[TLB.scala:170:77]
wire _entries_T_245; // @[TLB.scala:170:77]
wire _entries_T_244; // @[TLB.scala:170:77]
wire _entries_T_243; // @[TLB.scala:170:77]
wire _entries_T_242; // @[TLB.scala:170:77]
wire _entries_T_241; // @[TLB.scala:170:77]
wire _entries_T_240; // @[TLB.scala:170:77]
wire _entries_T_239; // @[TLB.scala:170:77]
wire _entries_T_238; // @[TLB.scala:170:77]
assign _entries_T_238 = _entries_WIRE_21[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_fragmented_superpage = _entries_T_238; // @[TLB.scala:170:77]
assign _entries_T_239 = _entries_WIRE_21[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_c = _entries_T_239; // @[TLB.scala:170:77]
assign _entries_T_240 = _entries_WIRE_21[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_eff = _entries_T_240; // @[TLB.scala:170:77]
assign _entries_T_241 = _entries_WIRE_21[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_paa = _entries_T_241; // @[TLB.scala:170:77]
assign _entries_T_242 = _entries_WIRE_21[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_pal = _entries_T_242; // @[TLB.scala:170:77]
assign _entries_T_243 = _entries_WIRE_21[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_ppp = _entries_T_243; // @[TLB.scala:170:77]
assign _entries_T_244 = _entries_WIRE_21[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_pr = _entries_T_244; // @[TLB.scala:170:77]
assign _entries_T_245 = _entries_WIRE_21[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_px = _entries_T_245; // @[TLB.scala:170:77]
assign _entries_T_246 = _entries_WIRE_21[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_pw = _entries_T_246; // @[TLB.scala:170:77]
assign _entries_T_247 = _entries_WIRE_21[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_hr = _entries_T_247; // @[TLB.scala:170:77]
assign _entries_T_248 = _entries_WIRE_21[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_hx = _entries_T_248; // @[TLB.scala:170:77]
assign _entries_T_249 = _entries_WIRE_21[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_hw = _entries_T_249; // @[TLB.scala:170:77]
assign _entries_T_250 = _entries_WIRE_21[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_sr = _entries_T_250; // @[TLB.scala:170:77]
assign _entries_T_251 = _entries_WIRE_21[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_sx = _entries_T_251; // @[TLB.scala:170:77]
assign _entries_T_252 = _entries_WIRE_21[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_sw = _entries_T_252; // @[TLB.scala:170:77]
assign _entries_T_253 = _entries_WIRE_21[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_gf = _entries_T_253; // @[TLB.scala:170:77]
assign _entries_T_254 = _entries_WIRE_21[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_pf = _entries_T_254; // @[TLB.scala:170:77]
assign _entries_T_255 = _entries_WIRE_21[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_ae_stage2 = _entries_T_255; // @[TLB.scala:170:77]
assign _entries_T_256 = _entries_WIRE_21[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_ae_final = _entries_T_256; // @[TLB.scala:170:77]
assign _entries_T_257 = _entries_WIRE_21[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_ae_ptw = _entries_T_257; // @[TLB.scala:170:77]
assign _entries_T_258 = _entries_WIRE_21[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_g = _entries_T_258; // @[TLB.scala:170:77]
assign _entries_T_259 = _entries_WIRE_21[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_u = _entries_T_259; // @[TLB.scala:170:77]
assign _entries_T_260 = _entries_WIRE_21[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_20_ppn = _entries_T_260; // @[TLB.scala:170:77]
wire [19:0] _entries_T_283; // @[TLB.scala:170:77]
wire _entries_T_282; // @[TLB.scala:170:77]
wire _entries_T_281; // @[TLB.scala:170:77]
wire _entries_T_280; // @[TLB.scala:170:77]
wire _entries_T_279; // @[TLB.scala:170:77]
wire _entries_T_278; // @[TLB.scala:170:77]
wire _entries_T_277; // @[TLB.scala:170:77]
wire _entries_T_276; // @[TLB.scala:170:77]
wire _entries_T_275; // @[TLB.scala:170:77]
wire _entries_T_274; // @[TLB.scala:170:77]
wire _entries_T_273; // @[TLB.scala:170:77]
wire _entries_T_272; // @[TLB.scala:170:77]
wire _entries_T_271; // @[TLB.scala:170:77]
wire _entries_T_270; // @[TLB.scala:170:77]
wire _entries_T_269; // @[TLB.scala:170:77]
wire _entries_T_268; // @[TLB.scala:170:77]
wire _entries_T_267; // @[TLB.scala:170:77]
wire _entries_T_266; // @[TLB.scala:170:77]
wire _entries_T_265; // @[TLB.scala:170:77]
wire _entries_T_264; // @[TLB.scala:170:77]
wire _entries_T_263; // @[TLB.scala:170:77]
wire _entries_T_262; // @[TLB.scala:170:77]
wire _entries_T_261; // @[TLB.scala:170:77]
assign _entries_T_261 = _entries_WIRE_23[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_fragmented_superpage = _entries_T_261; // @[TLB.scala:170:77]
assign _entries_T_262 = _entries_WIRE_23[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_c = _entries_T_262; // @[TLB.scala:170:77]
assign _entries_T_263 = _entries_WIRE_23[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_eff = _entries_T_263; // @[TLB.scala:170:77]
assign _entries_T_264 = _entries_WIRE_23[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_paa = _entries_T_264; // @[TLB.scala:170:77]
assign _entries_T_265 = _entries_WIRE_23[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_pal = _entries_T_265; // @[TLB.scala:170:77]
assign _entries_T_266 = _entries_WIRE_23[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_ppp = _entries_T_266; // @[TLB.scala:170:77]
assign _entries_T_267 = _entries_WIRE_23[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_pr = _entries_T_267; // @[TLB.scala:170:77]
assign _entries_T_268 = _entries_WIRE_23[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_px = _entries_T_268; // @[TLB.scala:170:77]
assign _entries_T_269 = _entries_WIRE_23[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_pw = _entries_T_269; // @[TLB.scala:170:77]
assign _entries_T_270 = _entries_WIRE_23[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_hr = _entries_T_270; // @[TLB.scala:170:77]
assign _entries_T_271 = _entries_WIRE_23[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_hx = _entries_T_271; // @[TLB.scala:170:77]
assign _entries_T_272 = _entries_WIRE_23[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_hw = _entries_T_272; // @[TLB.scala:170:77]
assign _entries_T_273 = _entries_WIRE_23[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_sr = _entries_T_273; // @[TLB.scala:170:77]
assign _entries_T_274 = _entries_WIRE_23[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_sx = _entries_T_274; // @[TLB.scala:170:77]
assign _entries_T_275 = _entries_WIRE_23[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_sw = _entries_T_275; // @[TLB.scala:170:77]
assign _entries_T_276 = _entries_WIRE_23[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_gf = _entries_T_276; // @[TLB.scala:170:77]
assign _entries_T_277 = _entries_WIRE_23[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_pf = _entries_T_277; // @[TLB.scala:170:77]
assign _entries_T_278 = _entries_WIRE_23[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_ae_stage2 = _entries_T_278; // @[TLB.scala:170:77]
assign _entries_T_279 = _entries_WIRE_23[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_ae_final = _entries_T_279; // @[TLB.scala:170:77]
assign _entries_T_280 = _entries_WIRE_23[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_ae_ptw = _entries_T_280; // @[TLB.scala:170:77]
assign _entries_T_281 = _entries_WIRE_23[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_g = _entries_T_281; // @[TLB.scala:170:77]
assign _entries_T_282 = _entries_WIRE_23[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_u = _entries_T_282; // @[TLB.scala:170:77]
assign _entries_T_283 = _entries_WIRE_23[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_22_ppn = _entries_T_283; // @[TLB.scala:170:77]
wire [19:0] _entries_T_306; // @[TLB.scala:170:77]
wire _entries_T_305; // @[TLB.scala:170:77]
wire _entries_T_304; // @[TLB.scala:170:77]
wire _entries_T_303; // @[TLB.scala:170:77]
wire _entries_T_302; // @[TLB.scala:170:77]
wire _entries_T_301; // @[TLB.scala:170:77]
wire _entries_T_300; // @[TLB.scala:170:77]
wire _entries_T_299; // @[TLB.scala:170:77]
wire _entries_T_298; // @[TLB.scala:170:77]
wire _entries_T_297; // @[TLB.scala:170:77]
wire _entries_T_296; // @[TLB.scala:170:77]
wire _entries_T_295; // @[TLB.scala:170:77]
wire _entries_T_294; // @[TLB.scala:170:77]
wire _entries_T_293; // @[TLB.scala:170:77]
wire _entries_T_292; // @[TLB.scala:170:77]
wire _entries_T_291; // @[TLB.scala:170:77]
wire _entries_T_290; // @[TLB.scala:170:77]
wire _entries_T_289; // @[TLB.scala:170:77]
wire _entries_T_288; // @[TLB.scala:170:77]
wire _entries_T_287; // @[TLB.scala:170:77]
wire _entries_T_286; // @[TLB.scala:170:77]
wire _entries_T_285; // @[TLB.scala:170:77]
wire _entries_T_284; // @[TLB.scala:170:77]
assign _entries_T_284 = _entries_WIRE_25[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_fragmented_superpage = _entries_T_284; // @[TLB.scala:170:77]
assign _entries_T_285 = _entries_WIRE_25[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_c = _entries_T_285; // @[TLB.scala:170:77]
assign _entries_T_286 = _entries_WIRE_25[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_eff = _entries_T_286; // @[TLB.scala:170:77]
assign _entries_T_287 = _entries_WIRE_25[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_paa = _entries_T_287; // @[TLB.scala:170:77]
assign _entries_T_288 = _entries_WIRE_25[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_pal = _entries_T_288; // @[TLB.scala:170:77]
assign _entries_T_289 = _entries_WIRE_25[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_ppp = _entries_T_289; // @[TLB.scala:170:77]
assign _entries_T_290 = _entries_WIRE_25[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_pr = _entries_T_290; // @[TLB.scala:170:77]
assign _entries_T_291 = _entries_WIRE_25[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_px = _entries_T_291; // @[TLB.scala:170:77]
assign _entries_T_292 = _entries_WIRE_25[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_pw = _entries_T_292; // @[TLB.scala:170:77]
assign _entries_T_293 = _entries_WIRE_25[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_hr = _entries_T_293; // @[TLB.scala:170:77]
assign _entries_T_294 = _entries_WIRE_25[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_hx = _entries_T_294; // @[TLB.scala:170:77]
assign _entries_T_295 = _entries_WIRE_25[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_hw = _entries_T_295; // @[TLB.scala:170:77]
assign _entries_T_296 = _entries_WIRE_25[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_sr = _entries_T_296; // @[TLB.scala:170:77]
assign _entries_T_297 = _entries_WIRE_25[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_sx = _entries_T_297; // @[TLB.scala:170:77]
assign _entries_T_298 = _entries_WIRE_25[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_sw = _entries_T_298; // @[TLB.scala:170:77]
assign _entries_T_299 = _entries_WIRE_25[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_gf = _entries_T_299; // @[TLB.scala:170:77]
assign _entries_T_300 = _entries_WIRE_25[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_pf = _entries_T_300; // @[TLB.scala:170:77]
assign _entries_T_301 = _entries_WIRE_25[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_ae_stage2 = _entries_T_301; // @[TLB.scala:170:77]
assign _entries_T_302 = _entries_WIRE_25[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_ae_final = _entries_T_302; // @[TLB.scala:170:77]
assign _entries_T_303 = _entries_WIRE_25[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_ae_ptw = _entries_T_303; // @[TLB.scala:170:77]
assign _entries_T_304 = _entries_WIRE_25[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_g = _entries_T_304; // @[TLB.scala:170:77]
assign _entries_T_305 = _entries_WIRE_25[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_u = _entries_T_305; // @[TLB.scala:170:77]
assign _entries_T_306 = _entries_WIRE_25[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_24_ppn = _entries_T_306; // @[TLB.scala:170:77]
wire _ppn_T = ~vm_enabled; // @[TLB.scala:399:61, :442:18, :502:30]
wire [1:0] ppn_res = _entries_barrier_8_io_y_ppn[19:18]; // @[package.scala:267:25]
wire ppn_ignore = _ppn_ignore_T; // @[TLB.scala:197:{28,34}]
wire [26:0] _ppn_T_1 = ppn_ignore ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30]
wire [26:0] _ppn_T_2 = {_ppn_T_1[26:20], _ppn_T_1[19:0] | _entries_barrier_8_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _ppn_T_3 = _ppn_T_2[17:9]; // @[TLB.scala:198:{47,58}]
wire [10:0] _ppn_T_4 = {ppn_res, _ppn_T_3}; // @[TLB.scala:195:26, :198:{18,58}]
wire _ppn_ignore_T_1 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :197:28, :341:30]
wire [26:0] _ppn_T_6 = {_ppn_T_5[26:20], _ppn_T_5[19:0] | _entries_barrier_8_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _ppn_T_7 = _ppn_T_6[8:0]; // @[TLB.scala:198:{47,58}]
wire [19:0] _ppn_T_8 = {_ppn_T_4, _ppn_T_7}; // @[TLB.scala:198:{18,58}]
wire [1:0] ppn_res_1 = _entries_barrier_9_io_y_ppn[19:18]; // @[package.scala:267:25]
wire ppn_ignore_2 = _ppn_ignore_T_2; // @[TLB.scala:197:{28,34}]
wire [26:0] _ppn_T_9 = ppn_ignore_2 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30]
wire [26:0] _ppn_T_10 = {_ppn_T_9[26:20], _ppn_T_9[19:0] | _entries_barrier_9_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _ppn_T_11 = _ppn_T_10[17:9]; // @[TLB.scala:198:{47,58}]
wire [10:0] _ppn_T_12 = {ppn_res_1, _ppn_T_11}; // @[TLB.scala:195:26, :198:{18,58}]
wire _ppn_ignore_T_3 = ~(superpage_entries_1_level[1]); // @[TLB.scala:182:28, :197:28, :341:30]
wire [26:0] _ppn_T_14 = {_ppn_T_13[26:20], _ppn_T_13[19:0] | _entries_barrier_9_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _ppn_T_15 = _ppn_T_14[8:0]; // @[TLB.scala:198:{47,58}]
wire [19:0] _ppn_T_16 = {_ppn_T_12, _ppn_T_15}; // @[TLB.scala:198:{18,58}]
wire [1:0] ppn_res_2 = _entries_barrier_10_io_y_ppn[19:18]; // @[package.scala:267:25]
wire ppn_ignore_4 = _ppn_ignore_T_4; // @[TLB.scala:197:{28,34}]
wire [26:0] _ppn_T_17 = ppn_ignore_4 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30]
wire [26:0] _ppn_T_18 = {_ppn_T_17[26:20], _ppn_T_17[19:0] | _entries_barrier_10_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _ppn_T_19 = _ppn_T_18[17:9]; // @[TLB.scala:198:{47,58}]
wire [10:0] _ppn_T_20 = {ppn_res_2, _ppn_T_19}; // @[TLB.scala:195:26, :198:{18,58}]
wire _ppn_ignore_T_5 = ~(superpage_entries_2_level[1]); // @[TLB.scala:182:28, :197:28, :341:30]
wire [26:0] _ppn_T_22 = {_ppn_T_21[26:20], _ppn_T_21[19:0] | _entries_barrier_10_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _ppn_T_23 = _ppn_T_22[8:0]; // @[TLB.scala:198:{47,58}]
wire [19:0] _ppn_T_24 = {_ppn_T_20, _ppn_T_23}; // @[TLB.scala:198:{18,58}]
wire [1:0] ppn_res_3 = _entries_barrier_11_io_y_ppn[19:18]; // @[package.scala:267:25]
wire ppn_ignore_6 = _ppn_ignore_T_6; // @[TLB.scala:197:{28,34}]
wire [26:0] _ppn_T_25 = ppn_ignore_6 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30]
wire [26:0] _ppn_T_26 = {_ppn_T_25[26:20], _ppn_T_25[19:0] | _entries_barrier_11_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _ppn_T_27 = _ppn_T_26[17:9]; // @[TLB.scala:198:{47,58}]
wire [10:0] _ppn_T_28 = {ppn_res_3, _ppn_T_27}; // @[TLB.scala:195:26, :198:{18,58}]
wire _ppn_ignore_T_7 = ~(superpage_entries_3_level[1]); // @[TLB.scala:182:28, :197:28, :341:30]
wire [26:0] _ppn_T_30 = {_ppn_T_29[26:20], _ppn_T_29[19:0] | _entries_barrier_11_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _ppn_T_31 = _ppn_T_30[8:0]; // @[TLB.scala:198:{47,58}]
wire [19:0] _ppn_T_32 = {_ppn_T_28, _ppn_T_31}; // @[TLB.scala:198:{18,58}]
wire [1:0] ppn_res_4 = _entries_barrier_12_io_y_ppn[19:18]; // @[package.scala:267:25]
wire ppn_ignore_8 = _ppn_ignore_T_8; // @[TLB.scala:197:{28,34}]
wire [26:0] _ppn_T_33 = ppn_ignore_8 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30]
wire [26:0] _ppn_T_34 = {_ppn_T_33[26:20], _ppn_T_33[19:0] | _entries_barrier_12_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _ppn_T_35 = _ppn_T_34[17:9]; // @[TLB.scala:198:{47,58}]
wire [10:0] _ppn_T_36 = {ppn_res_4, _ppn_T_35}; // @[TLB.scala:195:26, :198:{18,58}]
wire _ppn_ignore_T_9 = ~(special_entry_level[1]); // @[TLB.scala:197:28, :346:56]
wire ppn_ignore_9 = _ppn_ignore_T_9; // @[TLB.scala:197:{28,34}]
wire [26:0] _ppn_T_37 = ppn_ignore_9 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30]
wire [26:0] _ppn_T_38 = {_ppn_T_37[26:20], _ppn_T_37[19:0] | _entries_barrier_12_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _ppn_T_39 = _ppn_T_38[8:0]; // @[TLB.scala:198:{47,58}]
wire [19:0] _ppn_T_40 = {_ppn_T_36, _ppn_T_39}; // @[TLB.scala:198:{18,58}]
wire [19:0] _ppn_T_41 = vpn[19:0]; // @[TLB.scala:335:30, :502:125]
wire [19:0] _ppn_T_42 = hitsVec_0 ? _entries_barrier_io_y_ppn : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_43 = hitsVec_1 ? _entries_barrier_1_io_y_ppn : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_44 = hitsVec_2 ? _entries_barrier_2_io_y_ppn : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_45 = hitsVec_3 ? _entries_barrier_3_io_y_ppn : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_46 = hitsVec_4 ? _entries_barrier_4_io_y_ppn : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_47 = hitsVec_5 ? _entries_barrier_5_io_y_ppn : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_48 = hitsVec_6 ? _entries_barrier_6_io_y_ppn : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_49 = hitsVec_7 ? _entries_barrier_7_io_y_ppn : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_50 = hitsVec_8 ? _ppn_T_8 : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_51 = hitsVec_9 ? _ppn_T_16 : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_52 = hitsVec_10 ? _ppn_T_24 : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_53 = hitsVec_11 ? _ppn_T_32 : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_54 = hitsVec_12 ? _ppn_T_40 : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_55 = _ppn_T ? _ppn_T_41 : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_56 = _ppn_T_42 | _ppn_T_43; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_57 = _ppn_T_56 | _ppn_T_44; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_58 = _ppn_T_57 | _ppn_T_45; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_59 = _ppn_T_58 | _ppn_T_46; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_60 = _ppn_T_59 | _ppn_T_47; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_61 = _ppn_T_60 | _ppn_T_48; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_62 = _ppn_T_61 | _ppn_T_49; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_63 = _ppn_T_62 | _ppn_T_50; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_64 = _ppn_T_63 | _ppn_T_51; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_65 = _ppn_T_64 | _ppn_T_52; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_66 = _ppn_T_65 | _ppn_T_53; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_67 = _ppn_T_66 | _ppn_T_54; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_68 = _ppn_T_67 | _ppn_T_55; // @[Mux.scala:30:73]
wire [19:0] ppn = _ppn_T_68; // @[Mux.scala:30:73]
wire [1:0] ptw_ae_array_lo_lo_hi = {_entries_barrier_2_io_y_ae_ptw, _entries_barrier_1_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_ae_array_lo_lo = {ptw_ae_array_lo_lo_hi, _entries_barrier_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_ae_array_lo_hi_hi = {_entries_barrier_5_io_y_ae_ptw, _entries_barrier_4_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_ae_array_lo_hi = {ptw_ae_array_lo_hi_hi, _entries_barrier_3_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [5:0] ptw_ae_array_lo = {ptw_ae_array_lo_hi, ptw_ae_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] ptw_ae_array_hi_lo_hi = {_entries_barrier_8_io_y_ae_ptw, _entries_barrier_7_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_ae_array_hi_lo = {ptw_ae_array_hi_lo_hi, _entries_barrier_6_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_ae_array_hi_hi_lo = {_entries_barrier_10_io_y_ae_ptw, _entries_barrier_9_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_ae_array_hi_hi_hi = {_entries_barrier_12_io_y_ae_ptw, _entries_barrier_11_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [3:0] ptw_ae_array_hi_hi = {ptw_ae_array_hi_hi_hi, ptw_ae_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] ptw_ae_array_hi = {ptw_ae_array_hi_hi, ptw_ae_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _ptw_ae_array_T = {ptw_ae_array_hi, ptw_ae_array_lo}; // @[package.scala:45:27]
wire [13:0] ptw_ae_array = {1'h0, _ptw_ae_array_T}; // @[package.scala:45:27]
wire [1:0] final_ae_array_lo_lo_hi = {_entries_barrier_2_io_y_ae_final, _entries_barrier_1_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [2:0] final_ae_array_lo_lo = {final_ae_array_lo_lo_hi, _entries_barrier_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [1:0] final_ae_array_lo_hi_hi = {_entries_barrier_5_io_y_ae_final, _entries_barrier_4_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [2:0] final_ae_array_lo_hi = {final_ae_array_lo_hi_hi, _entries_barrier_3_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [5:0] final_ae_array_lo = {final_ae_array_lo_hi, final_ae_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] final_ae_array_hi_lo_hi = {_entries_barrier_8_io_y_ae_final, _entries_barrier_7_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [2:0] final_ae_array_hi_lo = {final_ae_array_hi_lo_hi, _entries_barrier_6_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [1:0] final_ae_array_hi_hi_lo = {_entries_barrier_10_io_y_ae_final, _entries_barrier_9_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [1:0] final_ae_array_hi_hi_hi = {_entries_barrier_12_io_y_ae_final, _entries_barrier_11_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [3:0] final_ae_array_hi_hi = {final_ae_array_hi_hi_hi, final_ae_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] final_ae_array_hi = {final_ae_array_hi_hi, final_ae_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _final_ae_array_T = {final_ae_array_hi, final_ae_array_lo}; // @[package.scala:45:27]
wire [13:0] final_ae_array = {1'h0, _final_ae_array_T}; // @[package.scala:45:27]
wire [1:0] ptw_pf_array_lo_lo_hi = {_entries_barrier_2_io_y_pf, _entries_barrier_1_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_pf_array_lo_lo = {ptw_pf_array_lo_lo_hi, _entries_barrier_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_pf_array_lo_hi_hi = {_entries_barrier_5_io_y_pf, _entries_barrier_4_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_pf_array_lo_hi = {ptw_pf_array_lo_hi_hi, _entries_barrier_3_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [5:0] ptw_pf_array_lo = {ptw_pf_array_lo_hi, ptw_pf_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] ptw_pf_array_hi_lo_hi = {_entries_barrier_8_io_y_pf, _entries_barrier_7_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_pf_array_hi_lo = {ptw_pf_array_hi_lo_hi, _entries_barrier_6_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_pf_array_hi_hi_lo = {_entries_barrier_10_io_y_pf, _entries_barrier_9_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_pf_array_hi_hi_hi = {_entries_barrier_12_io_y_pf, _entries_barrier_11_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [3:0] ptw_pf_array_hi_hi = {ptw_pf_array_hi_hi_hi, ptw_pf_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] ptw_pf_array_hi = {ptw_pf_array_hi_hi, ptw_pf_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _ptw_pf_array_T = {ptw_pf_array_hi, ptw_pf_array_lo}; // @[package.scala:45:27]
wire [13:0] ptw_pf_array = {1'h0, _ptw_pf_array_T}; // @[package.scala:45:27]
wire [1:0] ptw_gf_array_lo_lo_hi = {_entries_barrier_2_io_y_gf, _entries_barrier_1_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_gf_array_lo_lo = {ptw_gf_array_lo_lo_hi, _entries_barrier_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_gf_array_lo_hi_hi = {_entries_barrier_5_io_y_gf, _entries_barrier_4_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_gf_array_lo_hi = {ptw_gf_array_lo_hi_hi, _entries_barrier_3_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [5:0] ptw_gf_array_lo = {ptw_gf_array_lo_hi, ptw_gf_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] ptw_gf_array_hi_lo_hi = {_entries_barrier_8_io_y_gf, _entries_barrier_7_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_gf_array_hi_lo = {ptw_gf_array_hi_lo_hi, _entries_barrier_6_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_gf_array_hi_hi_lo = {_entries_barrier_10_io_y_gf, _entries_barrier_9_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_gf_array_hi_hi_hi = {_entries_barrier_12_io_y_gf, _entries_barrier_11_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [3:0] ptw_gf_array_hi_hi = {ptw_gf_array_hi_hi_hi, ptw_gf_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] ptw_gf_array_hi = {ptw_gf_array_hi_hi, ptw_gf_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _ptw_gf_array_T = {ptw_gf_array_hi, ptw_gf_array_lo}; // @[package.scala:45:27]
wire [13:0] ptw_gf_array = {1'h0, _ptw_gf_array_T}; // @[package.scala:45:27]
wire [13:0] _gf_ld_array_T_3 = ptw_gf_array; // @[TLB.scala:509:25, :600:82]
wire [13:0] _gf_st_array_T_2 = ptw_gf_array; // @[TLB.scala:509:25, :601:63]
wire [13:0] _gf_inst_array_T_1 = ptw_gf_array; // @[TLB.scala:509:25, :602:46]
wire _priv_rw_ok_T = ~priv_s; // @[TLB.scala:370:20, :513:24]
wire _priv_rw_ok_T_1 = _priv_rw_ok_T | sum; // @[TLB.scala:510:16, :513:{24,32}]
wire [1:0] _GEN_40 = {_entries_barrier_2_io_y_u, _entries_barrier_1_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] priv_rw_ok_lo_lo_hi; // @[package.scala:45:27]
assign priv_rw_ok_lo_lo_hi = _GEN_40; // @[package.scala:45:27]
wire [1:0] priv_rw_ok_lo_lo_hi_1; // @[package.scala:45:27]
assign priv_rw_ok_lo_lo_hi_1 = _GEN_40; // @[package.scala:45:27]
wire [1:0] priv_x_ok_lo_lo_hi; // @[package.scala:45:27]
assign priv_x_ok_lo_lo_hi = _GEN_40; // @[package.scala:45:27]
wire [1:0] priv_x_ok_lo_lo_hi_1; // @[package.scala:45:27]
assign priv_x_ok_lo_lo_hi_1 = _GEN_40; // @[package.scala:45:27]
wire [2:0] priv_rw_ok_lo_lo = {priv_rw_ok_lo_lo_hi, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_41 = {_entries_barrier_5_io_y_u, _entries_barrier_4_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] priv_rw_ok_lo_hi_hi; // @[package.scala:45:27]
assign priv_rw_ok_lo_hi_hi = _GEN_41; // @[package.scala:45:27]
wire [1:0] priv_rw_ok_lo_hi_hi_1; // @[package.scala:45:27]
assign priv_rw_ok_lo_hi_hi_1 = _GEN_41; // @[package.scala:45:27]
wire [1:0] priv_x_ok_lo_hi_hi; // @[package.scala:45:27]
assign priv_x_ok_lo_hi_hi = _GEN_41; // @[package.scala:45:27]
wire [1:0] priv_x_ok_lo_hi_hi_1; // @[package.scala:45:27]
assign priv_x_ok_lo_hi_hi_1 = _GEN_41; // @[package.scala:45:27]
wire [2:0] priv_rw_ok_lo_hi = {priv_rw_ok_lo_hi_hi, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25]
wire [5:0] priv_rw_ok_lo = {priv_rw_ok_lo_hi, priv_rw_ok_lo_lo}; // @[package.scala:45:27]
wire [1:0] _GEN_42 = {_entries_barrier_8_io_y_u, _entries_barrier_7_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] priv_rw_ok_hi_lo_hi; // @[package.scala:45:27]
assign priv_rw_ok_hi_lo_hi = _GEN_42; // @[package.scala:45:27]
wire [1:0] priv_rw_ok_hi_lo_hi_1; // @[package.scala:45:27]
assign priv_rw_ok_hi_lo_hi_1 = _GEN_42; // @[package.scala:45:27]
wire [1:0] priv_x_ok_hi_lo_hi; // @[package.scala:45:27]
assign priv_x_ok_hi_lo_hi = _GEN_42; // @[package.scala:45:27]
wire [1:0] priv_x_ok_hi_lo_hi_1; // @[package.scala:45:27]
assign priv_x_ok_hi_lo_hi_1 = _GEN_42; // @[package.scala:45:27]
wire [2:0] priv_rw_ok_hi_lo = {priv_rw_ok_hi_lo_hi, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_43 = {_entries_barrier_10_io_y_u, _entries_barrier_9_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] priv_rw_ok_hi_hi_lo; // @[package.scala:45:27]
assign priv_rw_ok_hi_hi_lo = _GEN_43; // @[package.scala:45:27]
wire [1:0] priv_rw_ok_hi_hi_lo_1; // @[package.scala:45:27]
assign priv_rw_ok_hi_hi_lo_1 = _GEN_43; // @[package.scala:45:27]
wire [1:0] priv_x_ok_hi_hi_lo; // @[package.scala:45:27]
assign priv_x_ok_hi_hi_lo = _GEN_43; // @[package.scala:45:27]
wire [1:0] priv_x_ok_hi_hi_lo_1; // @[package.scala:45:27]
assign priv_x_ok_hi_hi_lo_1 = _GEN_43; // @[package.scala:45:27]
wire [1:0] _GEN_44 = {_entries_barrier_12_io_y_u, _entries_barrier_11_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] priv_rw_ok_hi_hi_hi; // @[package.scala:45:27]
assign priv_rw_ok_hi_hi_hi = _GEN_44; // @[package.scala:45:27]
wire [1:0] priv_rw_ok_hi_hi_hi_1; // @[package.scala:45:27]
assign priv_rw_ok_hi_hi_hi_1 = _GEN_44; // @[package.scala:45:27]
wire [1:0] priv_x_ok_hi_hi_hi; // @[package.scala:45:27]
assign priv_x_ok_hi_hi_hi = _GEN_44; // @[package.scala:45:27]
wire [1:0] priv_x_ok_hi_hi_hi_1; // @[package.scala:45:27]
assign priv_x_ok_hi_hi_hi_1 = _GEN_44; // @[package.scala:45:27]
wire [3:0] priv_rw_ok_hi_hi = {priv_rw_ok_hi_hi_hi, priv_rw_ok_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] priv_rw_ok_hi = {priv_rw_ok_hi_hi, priv_rw_ok_hi_lo}; // @[package.scala:45:27]
wire [12:0] _priv_rw_ok_T_2 = {priv_rw_ok_hi, priv_rw_ok_lo}; // @[package.scala:45:27]
wire [12:0] _priv_rw_ok_T_3 = _priv_rw_ok_T_1 ? _priv_rw_ok_T_2 : 13'h0; // @[package.scala:45:27]
wire [2:0] priv_rw_ok_lo_lo_1 = {priv_rw_ok_lo_lo_hi_1, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25]
wire [2:0] priv_rw_ok_lo_hi_1 = {priv_rw_ok_lo_hi_hi_1, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25]
wire [5:0] priv_rw_ok_lo_1 = {priv_rw_ok_lo_hi_1, priv_rw_ok_lo_lo_1}; // @[package.scala:45:27]
wire [2:0] priv_rw_ok_hi_lo_1 = {priv_rw_ok_hi_lo_hi_1, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25]
wire [3:0] priv_rw_ok_hi_hi_1 = {priv_rw_ok_hi_hi_hi_1, priv_rw_ok_hi_hi_lo_1}; // @[package.scala:45:27]
wire [6:0] priv_rw_ok_hi_1 = {priv_rw_ok_hi_hi_1, priv_rw_ok_hi_lo_1}; // @[package.scala:45:27]
wire [12:0] _priv_rw_ok_T_4 = {priv_rw_ok_hi_1, priv_rw_ok_lo_1}; // @[package.scala:45:27]
wire [12:0] _priv_rw_ok_T_5 = ~_priv_rw_ok_T_4; // @[package.scala:45:27]
wire [12:0] _priv_rw_ok_T_6 = priv_s ? _priv_rw_ok_T_5 : 13'h0; // @[TLB.scala:370:20, :513:{75,84}]
wire [12:0] priv_rw_ok = _priv_rw_ok_T_3 | _priv_rw_ok_T_6; // @[TLB.scala:513:{23,70,75}]
wire [2:0] priv_x_ok_lo_lo = {priv_x_ok_lo_lo_hi, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25]
wire [2:0] priv_x_ok_lo_hi = {priv_x_ok_lo_hi_hi, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25]
wire [5:0] priv_x_ok_lo = {priv_x_ok_lo_hi, priv_x_ok_lo_lo}; // @[package.scala:45:27]
wire [2:0] priv_x_ok_hi_lo = {priv_x_ok_hi_lo_hi, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25]
wire [3:0] priv_x_ok_hi_hi = {priv_x_ok_hi_hi_hi, priv_x_ok_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] priv_x_ok_hi = {priv_x_ok_hi_hi, priv_x_ok_hi_lo}; // @[package.scala:45:27]
wire [12:0] _priv_x_ok_T = {priv_x_ok_hi, priv_x_ok_lo}; // @[package.scala:45:27]
wire [12:0] _priv_x_ok_T_1 = ~_priv_x_ok_T; // @[package.scala:45:27]
wire [2:0] priv_x_ok_lo_lo_1 = {priv_x_ok_lo_lo_hi_1, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25]
wire [2:0] priv_x_ok_lo_hi_1 = {priv_x_ok_lo_hi_hi_1, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25]
wire [5:0] priv_x_ok_lo_1 = {priv_x_ok_lo_hi_1, priv_x_ok_lo_lo_1}; // @[package.scala:45:27]
wire [2:0] priv_x_ok_hi_lo_1 = {priv_x_ok_hi_lo_hi_1, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25]
wire [3:0] priv_x_ok_hi_hi_1 = {priv_x_ok_hi_hi_hi_1, priv_x_ok_hi_hi_lo_1}; // @[package.scala:45:27]
wire [6:0] priv_x_ok_hi_1 = {priv_x_ok_hi_hi_1, priv_x_ok_hi_lo_1}; // @[package.scala:45:27]
wire [12:0] _priv_x_ok_T_2 = {priv_x_ok_hi_1, priv_x_ok_lo_1}; // @[package.scala:45:27]
wire [12:0] priv_x_ok = priv_s ? _priv_x_ok_T_1 : _priv_x_ok_T_2; // @[package.scala:45:27]
wire _stage1_bypass_T_1 = ~stage1_en; // @[TLB.scala:374:29, :517:83]
wire [12:0] _stage1_bypass_T_2 = {13{_stage1_bypass_T_1}}; // @[TLB.scala:517:{68,83}]
wire [1:0] stage1_bypass_lo_lo_hi = {_entries_barrier_2_io_y_ae_stage2, _entries_barrier_1_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [2:0] stage1_bypass_lo_lo = {stage1_bypass_lo_lo_hi, _entries_barrier_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [1:0] stage1_bypass_lo_hi_hi = {_entries_barrier_5_io_y_ae_stage2, _entries_barrier_4_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [2:0] stage1_bypass_lo_hi = {stage1_bypass_lo_hi_hi, _entries_barrier_3_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [5:0] stage1_bypass_lo = {stage1_bypass_lo_hi, stage1_bypass_lo_lo}; // @[package.scala:45:27]
wire [1:0] stage1_bypass_hi_lo_hi = {_entries_barrier_8_io_y_ae_stage2, _entries_barrier_7_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [2:0] stage1_bypass_hi_lo = {stage1_bypass_hi_lo_hi, _entries_barrier_6_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [1:0] stage1_bypass_hi_hi_lo = {_entries_barrier_10_io_y_ae_stage2, _entries_barrier_9_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [1:0] stage1_bypass_hi_hi_hi = {_entries_barrier_12_io_y_ae_stage2, _entries_barrier_11_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [3:0] stage1_bypass_hi_hi = {stage1_bypass_hi_hi_hi, stage1_bypass_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] stage1_bypass_hi = {stage1_bypass_hi_hi, stage1_bypass_hi_lo}; // @[package.scala:45:27]
wire [12:0] _stage1_bypass_T_3 = {stage1_bypass_hi, stage1_bypass_lo}; // @[package.scala:45:27]
wire [12:0] _stage1_bypass_T_4 = _stage1_bypass_T_2 | _stage1_bypass_T_3; // @[package.scala:45:27]
wire [1:0] r_array_lo_lo_hi = {_entries_barrier_2_io_y_sr, _entries_barrier_1_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [2:0] r_array_lo_lo = {r_array_lo_lo_hi, _entries_barrier_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [1:0] r_array_lo_hi_hi = {_entries_barrier_5_io_y_sr, _entries_barrier_4_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [2:0] r_array_lo_hi = {r_array_lo_hi_hi, _entries_barrier_3_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [5:0] r_array_lo = {r_array_lo_hi, r_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] r_array_hi_lo_hi = {_entries_barrier_8_io_y_sr, _entries_barrier_7_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [2:0] r_array_hi_lo = {r_array_hi_lo_hi, _entries_barrier_6_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [1:0] r_array_hi_hi_lo = {_entries_barrier_10_io_y_sr, _entries_barrier_9_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [1:0] r_array_hi_hi_hi = {_entries_barrier_12_io_y_sr, _entries_barrier_11_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [3:0] r_array_hi_hi = {r_array_hi_hi_hi, r_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] r_array_hi = {r_array_hi_hi, r_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _r_array_T = {r_array_hi, r_array_lo}; // @[package.scala:45:27]
wire [1:0] _GEN_45 = {_entries_barrier_2_io_y_sx, _entries_barrier_1_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] r_array_lo_lo_hi_1; // @[package.scala:45:27]
assign r_array_lo_lo_hi_1 = _GEN_45; // @[package.scala:45:27]
wire [1:0] x_array_lo_lo_hi; // @[package.scala:45:27]
assign x_array_lo_lo_hi = _GEN_45; // @[package.scala:45:27]
wire [2:0] r_array_lo_lo_1 = {r_array_lo_lo_hi_1, _entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_46 = {_entries_barrier_5_io_y_sx, _entries_barrier_4_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] r_array_lo_hi_hi_1; // @[package.scala:45:27]
assign r_array_lo_hi_hi_1 = _GEN_46; // @[package.scala:45:27]
wire [1:0] x_array_lo_hi_hi; // @[package.scala:45:27]
assign x_array_lo_hi_hi = _GEN_46; // @[package.scala:45:27]
wire [2:0] r_array_lo_hi_1 = {r_array_lo_hi_hi_1, _entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [5:0] r_array_lo_1 = {r_array_lo_hi_1, r_array_lo_lo_1}; // @[package.scala:45:27]
wire [1:0] _GEN_47 = {_entries_barrier_8_io_y_sx, _entries_barrier_7_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] r_array_hi_lo_hi_1; // @[package.scala:45:27]
assign r_array_hi_lo_hi_1 = _GEN_47; // @[package.scala:45:27]
wire [1:0] x_array_hi_lo_hi; // @[package.scala:45:27]
assign x_array_hi_lo_hi = _GEN_47; // @[package.scala:45:27]
wire [2:0] r_array_hi_lo_1 = {r_array_hi_lo_hi_1, _entries_barrier_6_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_48 = {_entries_barrier_10_io_y_sx, _entries_barrier_9_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] r_array_hi_hi_lo_1; // @[package.scala:45:27]
assign r_array_hi_hi_lo_1 = _GEN_48; // @[package.scala:45:27]
wire [1:0] x_array_hi_hi_lo; // @[package.scala:45:27]
assign x_array_hi_hi_lo = _GEN_48; // @[package.scala:45:27]
wire [1:0] _GEN_49 = {_entries_barrier_12_io_y_sx, _entries_barrier_11_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] r_array_hi_hi_hi_1; // @[package.scala:45:27]
assign r_array_hi_hi_hi_1 = _GEN_49; // @[package.scala:45:27]
wire [1:0] x_array_hi_hi_hi; // @[package.scala:45:27]
assign x_array_hi_hi_hi = _GEN_49; // @[package.scala:45:27]
wire [3:0] r_array_hi_hi_1 = {r_array_hi_hi_hi_1, r_array_hi_hi_lo_1}; // @[package.scala:45:27]
wire [6:0] r_array_hi_1 = {r_array_hi_hi_1, r_array_hi_lo_1}; // @[package.scala:45:27]
wire [12:0] _r_array_T_1 = {r_array_hi_1, r_array_lo_1}; // @[package.scala:45:27]
wire [12:0] _r_array_T_2 = mxr ? _r_array_T_1 : 13'h0; // @[package.scala:45:27]
wire [12:0] _r_array_T_3 = _r_array_T | _r_array_T_2; // @[package.scala:45:27]
wire [12:0] _r_array_T_4 = priv_rw_ok & _r_array_T_3; // @[TLB.scala:513:70, :520:{41,69}]
wire [12:0] _r_array_T_5 = _r_array_T_4; // @[TLB.scala:520:{41,113}]
wire [13:0] r_array = {1'h1, _r_array_T_5}; // @[TLB.scala:520:{20,113}]
wire [13:0] _pf_ld_array_T = r_array; // @[TLB.scala:520:20, :597:41]
wire [1:0] w_array_lo_lo_hi = {_entries_barrier_2_io_y_sw, _entries_barrier_1_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [2:0] w_array_lo_lo = {w_array_lo_lo_hi, _entries_barrier_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [1:0] w_array_lo_hi_hi = {_entries_barrier_5_io_y_sw, _entries_barrier_4_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [2:0] w_array_lo_hi = {w_array_lo_hi_hi, _entries_barrier_3_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [5:0] w_array_lo = {w_array_lo_hi, w_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] w_array_hi_lo_hi = {_entries_barrier_8_io_y_sw, _entries_barrier_7_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [2:0] w_array_hi_lo = {w_array_hi_lo_hi, _entries_barrier_6_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [1:0] w_array_hi_hi_lo = {_entries_barrier_10_io_y_sw, _entries_barrier_9_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [1:0] w_array_hi_hi_hi = {_entries_barrier_12_io_y_sw, _entries_barrier_11_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [3:0] w_array_hi_hi = {w_array_hi_hi_hi, w_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] w_array_hi = {w_array_hi_hi, w_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _w_array_T = {w_array_hi, w_array_lo}; // @[package.scala:45:27]
wire [12:0] _w_array_T_1 = priv_rw_ok & _w_array_T; // @[package.scala:45:27]
wire [12:0] _w_array_T_2 = _w_array_T_1; // @[TLB.scala:521:{41,69}]
wire [13:0] w_array = {1'h1, _w_array_T_2}; // @[TLB.scala:521:{20,69}]
wire [2:0] x_array_lo_lo = {x_array_lo_lo_hi, _entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [2:0] x_array_lo_hi = {x_array_lo_hi_hi, _entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [5:0] x_array_lo = {x_array_lo_hi, x_array_lo_lo}; // @[package.scala:45:27]
wire [2:0] x_array_hi_lo = {x_array_hi_lo_hi, _entries_barrier_6_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [3:0] x_array_hi_hi = {x_array_hi_hi_hi, x_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] x_array_hi = {x_array_hi_hi, x_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _x_array_T = {x_array_hi, x_array_lo}; // @[package.scala:45:27]
wire [12:0] _x_array_T_1 = priv_x_ok & _x_array_T; // @[package.scala:45:27]
wire [12:0] _x_array_T_2 = _x_array_T_1; // @[TLB.scala:522:{40,68}]
wire [13:0] x_array = {1'h1, _x_array_T_2}; // @[TLB.scala:522:{20,68}]
wire [1:0] hr_array_lo_lo_hi = {_entries_barrier_2_io_y_hr, _entries_barrier_1_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [2:0] hr_array_lo_lo = {hr_array_lo_lo_hi, _entries_barrier_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [1:0] hr_array_lo_hi_hi = {_entries_barrier_5_io_y_hr, _entries_barrier_4_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [2:0] hr_array_lo_hi = {hr_array_lo_hi_hi, _entries_barrier_3_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [5:0] hr_array_lo = {hr_array_lo_hi, hr_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] hr_array_hi_lo_hi = {_entries_barrier_8_io_y_hr, _entries_barrier_7_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [2:0] hr_array_hi_lo = {hr_array_hi_lo_hi, _entries_barrier_6_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [1:0] hr_array_hi_hi_lo = {_entries_barrier_10_io_y_hr, _entries_barrier_9_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [1:0] hr_array_hi_hi_hi = {_entries_barrier_12_io_y_hr, _entries_barrier_11_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [3:0] hr_array_hi_hi = {hr_array_hi_hi_hi, hr_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] hr_array_hi = {hr_array_hi_hi, hr_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _hr_array_T = {hr_array_hi, hr_array_lo}; // @[package.scala:45:27]
wire [1:0] _GEN_50 = {_entries_barrier_2_io_y_hx, _entries_barrier_1_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] hr_array_lo_lo_hi_1; // @[package.scala:45:27]
assign hr_array_lo_lo_hi_1 = _GEN_50; // @[package.scala:45:27]
wire [1:0] hx_array_lo_lo_hi; // @[package.scala:45:27]
assign hx_array_lo_lo_hi = _GEN_50; // @[package.scala:45:27]
wire [2:0] hr_array_lo_lo_1 = {hr_array_lo_lo_hi_1, _entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_51 = {_entries_barrier_5_io_y_hx, _entries_barrier_4_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] hr_array_lo_hi_hi_1; // @[package.scala:45:27]
assign hr_array_lo_hi_hi_1 = _GEN_51; // @[package.scala:45:27]
wire [1:0] hx_array_lo_hi_hi; // @[package.scala:45:27]
assign hx_array_lo_hi_hi = _GEN_51; // @[package.scala:45:27]
wire [2:0] hr_array_lo_hi_1 = {hr_array_lo_hi_hi_1, _entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [5:0] hr_array_lo_1 = {hr_array_lo_hi_1, hr_array_lo_lo_1}; // @[package.scala:45:27]
wire [1:0] _GEN_52 = {_entries_barrier_8_io_y_hx, _entries_barrier_7_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] hr_array_hi_lo_hi_1; // @[package.scala:45:27]
assign hr_array_hi_lo_hi_1 = _GEN_52; // @[package.scala:45:27]
wire [1:0] hx_array_hi_lo_hi; // @[package.scala:45:27]
assign hx_array_hi_lo_hi = _GEN_52; // @[package.scala:45:27]
wire [2:0] hr_array_hi_lo_1 = {hr_array_hi_lo_hi_1, _entries_barrier_6_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_53 = {_entries_barrier_10_io_y_hx, _entries_barrier_9_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] hr_array_hi_hi_lo_1; // @[package.scala:45:27]
assign hr_array_hi_hi_lo_1 = _GEN_53; // @[package.scala:45:27]
wire [1:0] hx_array_hi_hi_lo; // @[package.scala:45:27]
assign hx_array_hi_hi_lo = _GEN_53; // @[package.scala:45:27]
wire [1:0] _GEN_54 = {_entries_barrier_12_io_y_hx, _entries_barrier_11_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] hr_array_hi_hi_hi_1; // @[package.scala:45:27]
assign hr_array_hi_hi_hi_1 = _GEN_54; // @[package.scala:45:27]
wire [1:0] hx_array_hi_hi_hi; // @[package.scala:45:27]
assign hx_array_hi_hi_hi = _GEN_54; // @[package.scala:45:27]
wire [3:0] hr_array_hi_hi_1 = {hr_array_hi_hi_hi_1, hr_array_hi_hi_lo_1}; // @[package.scala:45:27]
wire [6:0] hr_array_hi_1 = {hr_array_hi_hi_1, hr_array_hi_lo_1}; // @[package.scala:45:27]
wire [12:0] _hr_array_T_1 = {hr_array_hi_1, hr_array_lo_1}; // @[package.scala:45:27]
wire [12:0] _hr_array_T_2 = io_ptw_status_mxr_0 ? _hr_array_T_1 : 13'h0; // @[package.scala:45:27]
wire [12:0] _hr_array_T_3 = _hr_array_T | _hr_array_T_2; // @[package.scala:45:27]
wire [1:0] hw_array_lo_lo_hi = {_entries_barrier_2_io_y_hw, _entries_barrier_1_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [2:0] hw_array_lo_lo = {hw_array_lo_lo_hi, _entries_barrier_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [1:0] hw_array_lo_hi_hi = {_entries_barrier_5_io_y_hw, _entries_barrier_4_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [2:0] hw_array_lo_hi = {hw_array_lo_hi_hi, _entries_barrier_3_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [5:0] hw_array_lo = {hw_array_lo_hi, hw_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] hw_array_hi_lo_hi = {_entries_barrier_8_io_y_hw, _entries_barrier_7_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [2:0] hw_array_hi_lo = {hw_array_hi_lo_hi, _entries_barrier_6_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [1:0] hw_array_hi_hi_lo = {_entries_barrier_10_io_y_hw, _entries_barrier_9_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [1:0] hw_array_hi_hi_hi = {_entries_barrier_12_io_y_hw, _entries_barrier_11_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [3:0] hw_array_hi_hi = {hw_array_hi_hi_hi, hw_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] hw_array_hi = {hw_array_hi_hi, hw_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _hw_array_T = {hw_array_hi, hw_array_lo}; // @[package.scala:45:27]
wire [2:0] hx_array_lo_lo = {hx_array_lo_lo_hi, _entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [2:0] hx_array_lo_hi = {hx_array_lo_hi_hi, _entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [5:0] hx_array_lo = {hx_array_lo_hi, hx_array_lo_lo}; // @[package.scala:45:27]
wire [2:0] hx_array_hi_lo = {hx_array_hi_lo_hi, _entries_barrier_6_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [3:0] hx_array_hi_hi = {hx_array_hi_hi_hi, hx_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] hx_array_hi = {hx_array_hi_hi, hx_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _hx_array_T = {hx_array_hi, hx_array_lo}; // @[package.scala:45:27]
wire [1:0] _pr_array_T = {2{prot_r}}; // @[TLB.scala:429:55, :529:26]
wire [1:0] pr_array_lo_lo_hi = {_entries_barrier_2_io_y_pr, _entries_barrier_1_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [2:0] pr_array_lo_lo = {pr_array_lo_lo_hi, _entries_barrier_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [1:0] pr_array_lo_hi_hi = {_entries_barrier_5_io_y_pr, _entries_barrier_4_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [2:0] pr_array_lo_hi = {pr_array_lo_hi_hi, _entries_barrier_3_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [5:0] pr_array_lo = {pr_array_lo_hi, pr_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pr_array_hi_lo_hi = {_entries_barrier_8_io_y_pr, _entries_barrier_7_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [2:0] pr_array_hi_lo = {pr_array_hi_lo_hi, _entries_barrier_6_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [1:0] pr_array_hi_hi_hi = {_entries_barrier_11_io_y_pr, _entries_barrier_10_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [2:0] pr_array_hi_hi = {pr_array_hi_hi_hi, _entries_barrier_9_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [5:0] pr_array_hi = {pr_array_hi_hi, pr_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _pr_array_T_1 = {pr_array_hi, pr_array_lo}; // @[package.scala:45:27]
wire [13:0] _pr_array_T_2 = {_pr_array_T, _pr_array_T_1}; // @[package.scala:45:27]
wire [13:0] _GEN_55 = ptw_ae_array | final_ae_array; // @[TLB.scala:506:25, :507:27, :529:104]
wire [13:0] _pr_array_T_3; // @[TLB.scala:529:104]
assign _pr_array_T_3 = _GEN_55; // @[TLB.scala:529:104]
wire [13:0] _pw_array_T_3; // @[TLB.scala:531:104]
assign _pw_array_T_3 = _GEN_55; // @[TLB.scala:529:104, :531:104]
wire [13:0] _px_array_T_3; // @[TLB.scala:533:104]
assign _px_array_T_3 = _GEN_55; // @[TLB.scala:529:104, :533:104]
wire [13:0] _pr_array_T_4 = ~_pr_array_T_3; // @[TLB.scala:529:{89,104}]
wire [13:0] pr_array = _pr_array_T_2 & _pr_array_T_4; // @[TLB.scala:529:{21,87,89}]
wire [1:0] _pw_array_T = {2{prot_w}}; // @[TLB.scala:430:55, :531:26]
wire [1:0] pw_array_lo_lo_hi = {_entries_barrier_2_io_y_pw, _entries_barrier_1_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [2:0] pw_array_lo_lo = {pw_array_lo_lo_hi, _entries_barrier_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [1:0] pw_array_lo_hi_hi = {_entries_barrier_5_io_y_pw, _entries_barrier_4_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [2:0] pw_array_lo_hi = {pw_array_lo_hi_hi, _entries_barrier_3_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [5:0] pw_array_lo = {pw_array_lo_hi, pw_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pw_array_hi_lo_hi = {_entries_barrier_8_io_y_pw, _entries_barrier_7_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [2:0] pw_array_hi_lo = {pw_array_hi_lo_hi, _entries_barrier_6_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [1:0] pw_array_hi_hi_hi = {_entries_barrier_11_io_y_pw, _entries_barrier_10_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [2:0] pw_array_hi_hi = {pw_array_hi_hi_hi, _entries_barrier_9_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [5:0] pw_array_hi = {pw_array_hi_hi, pw_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _pw_array_T_1 = {pw_array_hi, pw_array_lo}; // @[package.scala:45:27]
wire [13:0] _pw_array_T_2 = {_pw_array_T, _pw_array_T_1}; // @[package.scala:45:27]
wire [13:0] _pw_array_T_4 = ~_pw_array_T_3; // @[TLB.scala:531:{89,104}]
wire [13:0] pw_array = _pw_array_T_2 & _pw_array_T_4; // @[TLB.scala:531:{21,87,89}]
wire [1:0] _px_array_T = {2{prot_x}}; // @[TLB.scala:434:55, :533:26]
wire [1:0] px_array_lo_lo_hi = {_entries_barrier_2_io_y_px, _entries_barrier_1_io_y_px}; // @[package.scala:45:27, :267:25]
wire [2:0] px_array_lo_lo = {px_array_lo_lo_hi, _entries_barrier_io_y_px}; // @[package.scala:45:27, :267:25]
wire [1:0] px_array_lo_hi_hi = {_entries_barrier_5_io_y_px, _entries_barrier_4_io_y_px}; // @[package.scala:45:27, :267:25]
wire [2:0] px_array_lo_hi = {px_array_lo_hi_hi, _entries_barrier_3_io_y_px}; // @[package.scala:45:27, :267:25]
wire [5:0] px_array_lo = {px_array_lo_hi, px_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] px_array_hi_lo_hi = {_entries_barrier_8_io_y_px, _entries_barrier_7_io_y_px}; // @[package.scala:45:27, :267:25]
wire [2:0] px_array_hi_lo = {px_array_hi_lo_hi, _entries_barrier_6_io_y_px}; // @[package.scala:45:27, :267:25]
wire [1:0] px_array_hi_hi_hi = {_entries_barrier_11_io_y_px, _entries_barrier_10_io_y_px}; // @[package.scala:45:27, :267:25]
wire [2:0] px_array_hi_hi = {px_array_hi_hi_hi, _entries_barrier_9_io_y_px}; // @[package.scala:45:27, :267:25]
wire [5:0] px_array_hi = {px_array_hi_hi, px_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _px_array_T_1 = {px_array_hi, px_array_lo}; // @[package.scala:45:27]
wire [13:0] _px_array_T_2 = {_px_array_T, _px_array_T_1}; // @[package.scala:45:27]
wire [13:0] _px_array_T_4 = ~_px_array_T_3; // @[TLB.scala:533:{89,104}]
wire [13:0] px_array = _px_array_T_2 & _px_array_T_4; // @[TLB.scala:533:{21,87,89}]
wire [1:0] _eff_array_T = {2{_pma_io_resp_eff}}; // @[TLB.scala:422:19, :535:27]
wire [1:0] eff_array_lo_lo_hi = {_entries_barrier_2_io_y_eff, _entries_barrier_1_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [2:0] eff_array_lo_lo = {eff_array_lo_lo_hi, _entries_barrier_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [1:0] eff_array_lo_hi_hi = {_entries_barrier_5_io_y_eff, _entries_barrier_4_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [2:0] eff_array_lo_hi = {eff_array_lo_hi_hi, _entries_barrier_3_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [5:0] eff_array_lo = {eff_array_lo_hi, eff_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] eff_array_hi_lo_hi = {_entries_barrier_8_io_y_eff, _entries_barrier_7_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [2:0] eff_array_hi_lo = {eff_array_hi_lo_hi, _entries_barrier_6_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [1:0] eff_array_hi_hi_hi = {_entries_barrier_11_io_y_eff, _entries_barrier_10_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [2:0] eff_array_hi_hi = {eff_array_hi_hi_hi, _entries_barrier_9_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [5:0] eff_array_hi = {eff_array_hi_hi, eff_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _eff_array_T_1 = {eff_array_hi, eff_array_lo}; // @[package.scala:45:27]
wire [13:0] eff_array = {_eff_array_T, _eff_array_T_1}; // @[package.scala:45:27]
wire [1:0] _c_array_T = {2{cacheable}}; // @[TLB.scala:425:41, :537:25]
wire [1:0] _GEN_56 = {_entries_barrier_2_io_y_c, _entries_barrier_1_io_y_c}; // @[package.scala:45:27, :267:25]
wire [1:0] c_array_lo_lo_hi; // @[package.scala:45:27]
assign c_array_lo_lo_hi = _GEN_56; // @[package.scala:45:27]
wire [1:0] prefetchable_array_lo_lo_hi; // @[package.scala:45:27]
assign prefetchable_array_lo_lo_hi = _GEN_56; // @[package.scala:45:27]
wire [2:0] c_array_lo_lo = {c_array_lo_lo_hi, _entries_barrier_io_y_c}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_57 = {_entries_barrier_5_io_y_c, _entries_barrier_4_io_y_c}; // @[package.scala:45:27, :267:25]
wire [1:0] c_array_lo_hi_hi; // @[package.scala:45:27]
assign c_array_lo_hi_hi = _GEN_57; // @[package.scala:45:27]
wire [1:0] prefetchable_array_lo_hi_hi; // @[package.scala:45:27]
assign prefetchable_array_lo_hi_hi = _GEN_57; // @[package.scala:45:27]
wire [2:0] c_array_lo_hi = {c_array_lo_hi_hi, _entries_barrier_3_io_y_c}; // @[package.scala:45:27, :267:25]
wire [5:0] c_array_lo = {c_array_lo_hi, c_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] _GEN_58 = {_entries_barrier_8_io_y_c, _entries_barrier_7_io_y_c}; // @[package.scala:45:27, :267:25]
wire [1:0] c_array_hi_lo_hi; // @[package.scala:45:27]
assign c_array_hi_lo_hi = _GEN_58; // @[package.scala:45:27]
wire [1:0] prefetchable_array_hi_lo_hi; // @[package.scala:45:27]
assign prefetchable_array_hi_lo_hi = _GEN_58; // @[package.scala:45:27]
wire [2:0] c_array_hi_lo = {c_array_hi_lo_hi, _entries_barrier_6_io_y_c}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_59 = {_entries_barrier_11_io_y_c, _entries_barrier_10_io_y_c}; // @[package.scala:45:27, :267:25]
wire [1:0] c_array_hi_hi_hi; // @[package.scala:45:27]
assign c_array_hi_hi_hi = _GEN_59; // @[package.scala:45:27]
wire [1:0] prefetchable_array_hi_hi_hi; // @[package.scala:45:27]
assign prefetchable_array_hi_hi_hi = _GEN_59; // @[package.scala:45:27]
wire [2:0] c_array_hi_hi = {c_array_hi_hi_hi, _entries_barrier_9_io_y_c}; // @[package.scala:45:27, :267:25]
wire [5:0] c_array_hi = {c_array_hi_hi, c_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _c_array_T_1 = {c_array_hi, c_array_lo}; // @[package.scala:45:27]
wire [13:0] c_array = {_c_array_T, _c_array_T_1}; // @[package.scala:45:27]
wire [13:0] lrscAllowed = c_array; // @[TLB.scala:537:20, :580:24]
wire [1:0] _ppp_array_T = {2{_pma_io_resp_pp}}; // @[TLB.scala:422:19, :539:27]
wire [1:0] ppp_array_lo_lo_hi = {_entries_barrier_2_io_y_ppp, _entries_barrier_1_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [2:0] ppp_array_lo_lo = {ppp_array_lo_lo_hi, _entries_barrier_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [1:0] ppp_array_lo_hi_hi = {_entries_barrier_5_io_y_ppp, _entries_barrier_4_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [2:0] ppp_array_lo_hi = {ppp_array_lo_hi_hi, _entries_barrier_3_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [5:0] ppp_array_lo = {ppp_array_lo_hi, ppp_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] ppp_array_hi_lo_hi = {_entries_barrier_8_io_y_ppp, _entries_barrier_7_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [2:0] ppp_array_hi_lo = {ppp_array_hi_lo_hi, _entries_barrier_6_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [1:0] ppp_array_hi_hi_hi = {_entries_barrier_11_io_y_ppp, _entries_barrier_10_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [2:0] ppp_array_hi_hi = {ppp_array_hi_hi_hi, _entries_barrier_9_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [5:0] ppp_array_hi = {ppp_array_hi_hi, ppp_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _ppp_array_T_1 = {ppp_array_hi, ppp_array_lo}; // @[package.scala:45:27]
wire [13:0] ppp_array = {_ppp_array_T, _ppp_array_T_1}; // @[package.scala:45:27]
wire [1:0] _paa_array_T = {2{_pma_io_resp_aa}}; // @[TLB.scala:422:19, :541:27]
wire [1:0] paa_array_lo_lo_hi = {_entries_barrier_2_io_y_paa, _entries_barrier_1_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [2:0] paa_array_lo_lo = {paa_array_lo_lo_hi, _entries_barrier_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [1:0] paa_array_lo_hi_hi = {_entries_barrier_5_io_y_paa, _entries_barrier_4_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [2:0] paa_array_lo_hi = {paa_array_lo_hi_hi, _entries_barrier_3_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [5:0] paa_array_lo = {paa_array_lo_hi, paa_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] paa_array_hi_lo_hi = {_entries_barrier_8_io_y_paa, _entries_barrier_7_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [2:0] paa_array_hi_lo = {paa_array_hi_lo_hi, _entries_barrier_6_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [1:0] paa_array_hi_hi_hi = {_entries_barrier_11_io_y_paa, _entries_barrier_10_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [2:0] paa_array_hi_hi = {paa_array_hi_hi_hi, _entries_barrier_9_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [5:0] paa_array_hi = {paa_array_hi_hi, paa_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _paa_array_T_1 = {paa_array_hi, paa_array_lo}; // @[package.scala:45:27]
wire [13:0] paa_array = {_paa_array_T, _paa_array_T_1}; // @[package.scala:45:27]
wire [13:0] paa_array_if_cached = paa_array; // @[TLB.scala:541:22, :545:39]
wire [1:0] _pal_array_T = {2{_pma_io_resp_al}}; // @[TLB.scala:422:19, :543:27]
wire [1:0] pal_array_lo_lo_hi = {_entries_barrier_2_io_y_pal, _entries_barrier_1_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [2:0] pal_array_lo_lo = {pal_array_lo_lo_hi, _entries_barrier_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [1:0] pal_array_lo_hi_hi = {_entries_barrier_5_io_y_pal, _entries_barrier_4_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [2:0] pal_array_lo_hi = {pal_array_lo_hi_hi, _entries_barrier_3_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [5:0] pal_array_lo = {pal_array_lo_hi, pal_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pal_array_hi_lo_hi = {_entries_barrier_8_io_y_pal, _entries_barrier_7_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [2:0] pal_array_hi_lo = {pal_array_hi_lo_hi, _entries_barrier_6_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [1:0] pal_array_hi_hi_hi = {_entries_barrier_11_io_y_pal, _entries_barrier_10_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [2:0] pal_array_hi_hi = {pal_array_hi_hi_hi, _entries_barrier_9_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [5:0] pal_array_hi = {pal_array_hi_hi, pal_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _pal_array_T_1 = {pal_array_hi, pal_array_lo}; // @[package.scala:45:27]
wire [13:0] pal_array = {_pal_array_T, _pal_array_T_1}; // @[package.scala:45:27]
wire [13:0] pal_array_if_cached = pal_array; // @[TLB.scala:543:22, :546:39]
wire [13:0] ppp_array_if_cached = ppp_array | c_array; // @[TLB.scala:537:20, :539:22, :544:39]
wire _prefetchable_array_T = cacheable & homogeneous; // @[TLBPermissions.scala:101:65]
wire [1:0] _prefetchable_array_T_1 = {_prefetchable_array_T, 1'h0}; // @[TLB.scala:547:{43,59}]
wire [2:0] prefetchable_array_lo_lo = {prefetchable_array_lo_lo_hi, _entries_barrier_io_y_c}; // @[package.scala:45:27, :267:25]
wire [2:0] prefetchable_array_lo_hi = {prefetchable_array_lo_hi_hi, _entries_barrier_3_io_y_c}; // @[package.scala:45:27, :267:25]
wire [5:0] prefetchable_array_lo = {prefetchable_array_lo_hi, prefetchable_array_lo_lo}; // @[package.scala:45:27]
wire [2:0] prefetchable_array_hi_lo = {prefetchable_array_hi_lo_hi, _entries_barrier_6_io_y_c}; // @[package.scala:45:27, :267:25]
wire [2:0] prefetchable_array_hi_hi = {prefetchable_array_hi_hi_hi, _entries_barrier_9_io_y_c}; // @[package.scala:45:27, :267:25]
wire [5:0] prefetchable_array_hi = {prefetchable_array_hi_hi, prefetchable_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _prefetchable_array_T_2 = {prefetchable_array_hi, prefetchable_array_lo}; // @[package.scala:45:27]
wire [13:0] prefetchable_array = {_prefetchable_array_T_1, _prefetchable_array_T_2}; // @[package.scala:45:27]
wire [3:0] _misaligned_T = 4'h1 << io_req_bits_size_0; // @[OneHot.scala:58:35]
wire [4:0] _misaligned_T_1 = {1'h0, _misaligned_T} - 5'h1; // @[OneHot.scala:58:35]
wire [3:0] _misaligned_T_2 = _misaligned_T_1[3:0]; // @[TLB.scala:550:69]
wire [39:0] _misaligned_T_3 = {36'h0, io_req_bits_vaddr_0[3:0] & _misaligned_T_2}; // @[TLB.scala:318:7, :550:{39,69}]
wire misaligned = |_misaligned_T_3; // @[TLB.scala:550:{39,77}]
wire _bad_va_T = vm_enabled & stage1_en; // @[TLB.scala:374:29, :399:61, :568:21]
wire [39:0] bad_va_maskedVAddr = io_req_bits_vaddr_0 & 40'hC000000000; // @[TLB.scala:318:7, :559:43]
wire _bad_va_T_2 = bad_va_maskedVAddr == 40'h0; // @[TLB.scala:559:43, :560:51]
wire _bad_va_T_3 = bad_va_maskedVAddr == 40'hC000000000; // @[TLB.scala:559:43, :560:86]
wire _bad_va_T_4 = _bad_va_T_3; // @[TLB.scala:560:{71,86}]
wire _bad_va_T_5 = _bad_va_T_2 | _bad_va_T_4; // @[TLB.scala:560:{51,59,71}]
wire _bad_va_T_6 = ~_bad_va_T_5; // @[TLB.scala:560:{37,59}]
wire _bad_va_T_7 = _bad_va_T_6; // @[TLB.scala:560:{34,37}]
wire bad_va = _bad_va_T & _bad_va_T_7; // @[TLB.scala:560:34, :568:{21,34}]
wire _GEN_60 = io_req_bits_cmd_0 == 5'h6; // @[package.scala:16:47]
wire _cmd_lrsc_T; // @[package.scala:16:47]
assign _cmd_lrsc_T = _GEN_60; // @[package.scala:16:47]
wire _cmd_read_T_2; // @[package.scala:16:47]
assign _cmd_read_T_2 = _GEN_60; // @[package.scala:16:47]
wire _GEN_61 = io_req_bits_cmd_0 == 5'h7; // @[package.scala:16:47]
wire _cmd_lrsc_T_1; // @[package.scala:16:47]
assign _cmd_lrsc_T_1 = _GEN_61; // @[package.scala:16:47]
wire _cmd_read_T_3; // @[package.scala:16:47]
assign _cmd_read_T_3 = _GEN_61; // @[package.scala:16:47]
wire _cmd_write_T_3; // @[Consts.scala:90:66]
assign _cmd_write_T_3 = _GEN_61; // @[package.scala:16:47]
wire _cmd_lrsc_T_2 = _cmd_lrsc_T | _cmd_lrsc_T_1; // @[package.scala:16:47, :81:59]
wire _GEN_62 = io_req_bits_cmd_0 == 5'h4; // @[package.scala:16:47]
wire _cmd_amo_logical_T; // @[package.scala:16:47]
assign _cmd_amo_logical_T = _GEN_62; // @[package.scala:16:47]
wire _cmd_read_T_7; // @[package.scala:16:47]
assign _cmd_read_T_7 = _GEN_62; // @[package.scala:16:47]
wire _cmd_write_T_5; // @[package.scala:16:47]
assign _cmd_write_T_5 = _GEN_62; // @[package.scala:16:47]
wire _GEN_63 = io_req_bits_cmd_0 == 5'h9; // @[package.scala:16:47]
wire _cmd_amo_logical_T_1; // @[package.scala:16:47]
assign _cmd_amo_logical_T_1 = _GEN_63; // @[package.scala:16:47]
wire _cmd_read_T_8; // @[package.scala:16:47]
assign _cmd_read_T_8 = _GEN_63; // @[package.scala:16:47]
wire _cmd_write_T_6; // @[package.scala:16:47]
assign _cmd_write_T_6 = _GEN_63; // @[package.scala:16:47]
wire _GEN_64 = io_req_bits_cmd_0 == 5'hA; // @[package.scala:16:47]
wire _cmd_amo_logical_T_2; // @[package.scala:16:47]
assign _cmd_amo_logical_T_2 = _GEN_64; // @[package.scala:16:47]
wire _cmd_read_T_9; // @[package.scala:16:47]
assign _cmd_read_T_9 = _GEN_64; // @[package.scala:16:47]
wire _cmd_write_T_7; // @[package.scala:16:47]
assign _cmd_write_T_7 = _GEN_64; // @[package.scala:16:47]
wire _GEN_65 = io_req_bits_cmd_0 == 5'hB; // @[package.scala:16:47]
wire _cmd_amo_logical_T_3; // @[package.scala:16:47]
assign _cmd_amo_logical_T_3 = _GEN_65; // @[package.scala:16:47]
wire _cmd_read_T_10; // @[package.scala:16:47]
assign _cmd_read_T_10 = _GEN_65; // @[package.scala:16:47]
wire _cmd_write_T_8; // @[package.scala:16:47]
assign _cmd_write_T_8 = _GEN_65; // @[package.scala:16:47]
wire _cmd_amo_logical_T_4 = _cmd_amo_logical_T | _cmd_amo_logical_T_1; // @[package.scala:16:47, :81:59]
wire _cmd_amo_logical_T_5 = _cmd_amo_logical_T_4 | _cmd_amo_logical_T_2; // @[package.scala:16:47, :81:59]
wire _cmd_amo_logical_T_6 = _cmd_amo_logical_T_5 | _cmd_amo_logical_T_3; // @[package.scala:16:47, :81:59]
wire _GEN_66 = io_req_bits_cmd_0 == 5'h8; // @[package.scala:16:47]
wire _cmd_amo_arithmetic_T; // @[package.scala:16:47]
assign _cmd_amo_arithmetic_T = _GEN_66; // @[package.scala:16:47]
wire _cmd_read_T_14; // @[package.scala:16:47]
assign _cmd_read_T_14 = _GEN_66; // @[package.scala:16:47]
wire _cmd_write_T_12; // @[package.scala:16:47]
assign _cmd_write_T_12 = _GEN_66; // @[package.scala:16:47]
wire _GEN_67 = io_req_bits_cmd_0 == 5'hC; // @[package.scala:16:47]
wire _cmd_amo_arithmetic_T_1; // @[package.scala:16:47]
assign _cmd_amo_arithmetic_T_1 = _GEN_67; // @[package.scala:16:47]
wire _cmd_read_T_15; // @[package.scala:16:47]
assign _cmd_read_T_15 = _GEN_67; // @[package.scala:16:47]
wire _cmd_write_T_13; // @[package.scala:16:47]
assign _cmd_write_T_13 = _GEN_67; // @[package.scala:16:47]
wire _GEN_68 = io_req_bits_cmd_0 == 5'hD; // @[package.scala:16:47]
wire _cmd_amo_arithmetic_T_2; // @[package.scala:16:47]
assign _cmd_amo_arithmetic_T_2 = _GEN_68; // @[package.scala:16:47]
wire _cmd_read_T_16; // @[package.scala:16:47]
assign _cmd_read_T_16 = _GEN_68; // @[package.scala:16:47]
wire _cmd_write_T_14; // @[package.scala:16:47]
assign _cmd_write_T_14 = _GEN_68; // @[package.scala:16:47]
wire _GEN_69 = io_req_bits_cmd_0 == 5'hE; // @[package.scala:16:47]
wire _cmd_amo_arithmetic_T_3; // @[package.scala:16:47]
assign _cmd_amo_arithmetic_T_3 = _GEN_69; // @[package.scala:16:47]
wire _cmd_read_T_17; // @[package.scala:16:47]
assign _cmd_read_T_17 = _GEN_69; // @[package.scala:16:47]
wire _cmd_write_T_15; // @[package.scala:16:47]
assign _cmd_write_T_15 = _GEN_69; // @[package.scala:16:47]
wire _GEN_70 = io_req_bits_cmd_0 == 5'hF; // @[package.scala:16:47]
wire _cmd_amo_arithmetic_T_4; // @[package.scala:16:47]
assign _cmd_amo_arithmetic_T_4 = _GEN_70; // @[package.scala:16:47]
wire _cmd_read_T_18; // @[package.scala:16:47]
assign _cmd_read_T_18 = _GEN_70; // @[package.scala:16:47]
wire _cmd_write_T_16; // @[package.scala:16:47]
assign _cmd_write_T_16 = _GEN_70; // @[package.scala:16:47]
wire _cmd_amo_arithmetic_T_5 = _cmd_amo_arithmetic_T | _cmd_amo_arithmetic_T_1; // @[package.scala:16:47, :81:59]
wire _cmd_amo_arithmetic_T_6 = _cmd_amo_arithmetic_T_5 | _cmd_amo_arithmetic_T_2; // @[package.scala:16:47, :81:59]
wire _cmd_amo_arithmetic_T_7 = _cmd_amo_arithmetic_T_6 | _cmd_amo_arithmetic_T_3; // @[package.scala:16:47, :81:59]
wire _cmd_amo_arithmetic_T_8 = _cmd_amo_arithmetic_T_7 | _cmd_amo_arithmetic_T_4; // @[package.scala:16:47, :81:59]
wire _GEN_71 = io_req_bits_cmd_0 == 5'h11; // @[TLB.scala:318:7, :573:41]
wire cmd_put_partial; // @[TLB.scala:573:41]
assign cmd_put_partial = _GEN_71; // @[TLB.scala:573:41]
wire _cmd_write_T_1; // @[Consts.scala:90:49]
assign _cmd_write_T_1 = _GEN_71; // @[TLB.scala:573:41]
wire _cmd_read_T = io_req_bits_cmd_0 == 5'h0; // @[package.scala:16:47]
wire _GEN_72 = io_req_bits_cmd_0 == 5'h10; // @[package.scala:16:47]
wire _cmd_read_T_1; // @[package.scala:16:47]
assign _cmd_read_T_1 = _GEN_72; // @[package.scala:16:47]
wire _cmd_readx_T; // @[TLB.scala:575:56]
assign _cmd_readx_T = _GEN_72; // @[package.scala:16:47]
wire _cmd_read_T_4 = _cmd_read_T | _cmd_read_T_1; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_5 = _cmd_read_T_4 | _cmd_read_T_2; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_6 = _cmd_read_T_5 | _cmd_read_T_3; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_11 = _cmd_read_T_7 | _cmd_read_T_8; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_12 = _cmd_read_T_11 | _cmd_read_T_9; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_13 = _cmd_read_T_12 | _cmd_read_T_10; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_19 = _cmd_read_T_14 | _cmd_read_T_15; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_20 = _cmd_read_T_19 | _cmd_read_T_16; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_21 = _cmd_read_T_20 | _cmd_read_T_17; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_22 = _cmd_read_T_21 | _cmd_read_T_18; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_23 = _cmd_read_T_13 | _cmd_read_T_22; // @[package.scala:81:59]
wire cmd_read = _cmd_read_T_6 | _cmd_read_T_23; // @[package.scala:81:59]
wire _cmd_write_T = io_req_bits_cmd_0 == 5'h1; // @[TLB.scala:318:7]
wire _cmd_write_T_2 = _cmd_write_T | _cmd_write_T_1; // @[Consts.scala:90:{32,42,49}]
wire _cmd_write_T_4 = _cmd_write_T_2 | _cmd_write_T_3; // @[Consts.scala:90:{42,59,66}]
wire _cmd_write_T_9 = _cmd_write_T_5 | _cmd_write_T_6; // @[package.scala:16:47, :81:59]
wire _cmd_write_T_10 = _cmd_write_T_9 | _cmd_write_T_7; // @[package.scala:16:47, :81:59]
wire _cmd_write_T_11 = _cmd_write_T_10 | _cmd_write_T_8; // @[package.scala:16:47, :81:59]
wire _cmd_write_T_17 = _cmd_write_T_12 | _cmd_write_T_13; // @[package.scala:16:47, :81:59]
wire _cmd_write_T_18 = _cmd_write_T_17 | _cmd_write_T_14; // @[package.scala:16:47, :81:59]
wire _cmd_write_T_19 = _cmd_write_T_18 | _cmd_write_T_15; // @[package.scala:16:47, :81:59]
wire _cmd_write_T_20 = _cmd_write_T_19 | _cmd_write_T_16; // @[package.scala:16:47, :81:59]
wire _cmd_write_T_21 = _cmd_write_T_11 | _cmd_write_T_20; // @[package.scala:81:59]
wire cmd_write = _cmd_write_T_4 | _cmd_write_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _cmd_write_perms_T = io_req_bits_cmd_0 == 5'h5; // @[package.scala:16:47]
wire _cmd_write_perms_T_1 = io_req_bits_cmd_0 == 5'h17; // @[package.scala:16:47]
wire _cmd_write_perms_T_2 = _cmd_write_perms_T | _cmd_write_perms_T_1; // @[package.scala:16:47, :81:59]
wire cmd_write_perms = cmd_write | _cmd_write_perms_T_2; // @[package.scala:81:59]
wire [13:0] _ae_array_T = misaligned ? eff_array : 14'h0; // @[TLB.scala:535:22, :550:77, :582:8]
wire [13:0] ae_array = _ae_array_T; // @[TLB.scala:582:{8,37}]
wire [13:0] _ae_array_T_1 = ~lrscAllowed; // @[TLB.scala:580:24, :583:19]
wire [13:0] _ae_ld_array_T = ~pr_array; // @[TLB.scala:529:87, :586:46]
wire [13:0] _ae_ld_array_T_1 = ae_array | _ae_ld_array_T; // @[TLB.scala:582:37, :586:{44,46}]
wire [13:0] ae_ld_array = cmd_read ? _ae_ld_array_T_1 : 14'h0; // @[TLB.scala:586:{24,44}]
wire [13:0] _ae_st_array_T = ~pw_array; // @[TLB.scala:531:87, :588:37]
wire [13:0] _ae_st_array_T_1 = ae_array | _ae_st_array_T; // @[TLB.scala:582:37, :588:{35,37}]
wire [13:0] _ae_st_array_T_2 = cmd_write_perms ? _ae_st_array_T_1 : 14'h0; // @[TLB.scala:577:35, :588:{8,35}]
wire [13:0] _ae_st_array_T_3 = ~ppp_array_if_cached; // @[TLB.scala:544:39, :589:26]
wire [13:0] _ae_st_array_T_4 = cmd_put_partial ? _ae_st_array_T_3 : 14'h0; // @[TLB.scala:573:41, :589:{8,26}]
wire [13:0] _ae_st_array_T_5 = _ae_st_array_T_2 | _ae_st_array_T_4; // @[TLB.scala:588:{8,53}, :589:8]
wire [13:0] _ae_st_array_T_8 = _ae_st_array_T_5; // @[TLB.scala:588:53, :589:53]
wire [13:0] _ae_st_array_T_6 = ~pal_array_if_cached; // @[TLB.scala:546:39, :590:26]
wire [13:0] ae_st_array = _ae_st_array_T_8; // @[TLB.scala:589:53, :590:53]
wire [13:0] _ae_st_array_T_9 = ~paa_array_if_cached; // @[TLB.scala:545:39, :591:29]
wire [13:0] _must_alloc_array_T = ~ppp_array; // @[TLB.scala:539:22, :593:26]
wire [13:0] _must_alloc_array_T_1 = cmd_put_partial ? _must_alloc_array_T : 14'h0; // @[TLB.scala:573:41, :593:{8,26}]
wire [13:0] _must_alloc_array_T_4 = _must_alloc_array_T_1; // @[TLB.scala:593:{8,43}]
wire [13:0] _must_alloc_array_T_2 = ~pal_array; // @[TLB.scala:543:22, :594:26]
wire [13:0] _must_alloc_array_T_7 = _must_alloc_array_T_4; // @[TLB.scala:593:43, :594:43]
wire [13:0] _must_alloc_array_T_5 = ~paa_array; // @[TLB.scala:541:22, :595:29]
wire [13:0] must_alloc_array = _must_alloc_array_T_7; // @[TLB.scala:594:43, :595:46]
wire [13:0] _pf_ld_array_T_1 = ~_pf_ld_array_T; // @[TLB.scala:597:{37,41}]
wire [13:0] _pf_ld_array_T_2 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73]
wire [13:0] _pf_ld_array_T_3 = _pf_ld_array_T_1 & _pf_ld_array_T_2; // @[TLB.scala:597:{37,71,73}]
wire [13:0] _pf_ld_array_T_4 = _pf_ld_array_T_3 | ptw_pf_array; // @[TLB.scala:508:25, :597:{71,88}]
wire [13:0] _pf_ld_array_T_5 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106]
wire [13:0] _pf_ld_array_T_6 = _pf_ld_array_T_4 & _pf_ld_array_T_5; // @[TLB.scala:597:{88,104,106}]
wire [13:0] pf_ld_array = cmd_read ? _pf_ld_array_T_6 : 14'h0; // @[TLB.scala:597:{24,104}]
wire [13:0] _pf_st_array_T = ~w_array; // @[TLB.scala:521:20, :598:44]
wire [13:0] _pf_st_array_T_1 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :598:55]
wire [13:0] _pf_st_array_T_2 = _pf_st_array_T & _pf_st_array_T_1; // @[TLB.scala:598:{44,53,55}]
wire [13:0] _pf_st_array_T_3 = _pf_st_array_T_2 | ptw_pf_array; // @[TLB.scala:508:25, :598:{53,70}]
wire [13:0] _pf_st_array_T_4 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106, :598:88]
wire [13:0] _pf_st_array_T_5 = _pf_st_array_T_3 & _pf_st_array_T_4; // @[TLB.scala:598:{70,86,88}]
wire [13:0] pf_st_array = cmd_write_perms ? _pf_st_array_T_5 : 14'h0; // @[TLB.scala:577:35, :598:{24,86}]
wire [13:0] _pf_inst_array_T = ~x_array; // @[TLB.scala:522:20, :599:25]
wire [13:0] _pf_inst_array_T_1 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :599:36]
wire [13:0] _pf_inst_array_T_2 = _pf_inst_array_T & _pf_inst_array_T_1; // @[TLB.scala:599:{25,34,36}]
wire [13:0] _pf_inst_array_T_3 = _pf_inst_array_T_2 | ptw_pf_array; // @[TLB.scala:508:25, :599:{34,51}]
wire [13:0] _pf_inst_array_T_4 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106, :599:69]
wire [13:0] pf_inst_array = _pf_inst_array_T_3 & _pf_inst_array_T_4; // @[TLB.scala:599:{51,67,69}]
wire [13:0] _gf_ld_array_T_4 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :600:100]
wire [13:0] _gf_ld_array_T_5 = _gf_ld_array_T_3 & _gf_ld_array_T_4; // @[TLB.scala:600:{82,98,100}]
wire [13:0] _gf_st_array_T_3 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :601:81]
wire [13:0] _gf_st_array_T_4 = _gf_st_array_T_2 & _gf_st_array_T_3; // @[TLB.scala:601:{63,79,81}]
wire [13:0] _gf_inst_array_T_2 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :602:64]
wire [13:0] _gf_inst_array_T_3 = _gf_inst_array_T_1 & _gf_inst_array_T_2; // @[TLB.scala:602:{46,62,64}]
wire _gpa_hits_hit_mask_T = r_gpa_vpn == vpn; // @[TLB.scala:335:30, :364:22, :606:73]
wire _gpa_hits_hit_mask_T_1 = r_gpa_valid & _gpa_hits_hit_mask_T; // @[TLB.scala:362:24, :606:{60,73}]
wire [11:0] _gpa_hits_hit_mask_T_2 = {12{_gpa_hits_hit_mask_T_1}}; // @[TLB.scala:606:{24,60}]
wire tlb_hit_if_not_gpa_miss = |real_hits; // @[package.scala:45:27]
wire tlb_hit = |_tlb_hit_T; // @[TLB.scala:611:{28,40}]
wire _tlb_miss_T_2 = ~bad_va; // @[TLB.scala:568:34, :613:56]
wire _tlb_miss_T_3 = _tlb_miss_T_1 & _tlb_miss_T_2; // @[TLB.scala:613:{29,53,56}]
wire _tlb_miss_T_4 = ~tlb_hit; // @[TLB.scala:611:40, :613:67]
wire tlb_miss = _tlb_miss_T_3 & _tlb_miss_T_4; // @[TLB.scala:613:{53,64,67}]
reg [6:0] state_vec_0; // @[Replacement.scala:305:17]
reg [2:0] state_reg_1; // @[Replacement.scala:168:70]
wire [1:0] _GEN_73 = {sector_hits_1, sector_hits_0}; // @[OneHot.scala:21:45]
wire [1:0] lo_lo; // @[OneHot.scala:21:45]
assign lo_lo = _GEN_73; // @[OneHot.scala:21:45]
wire [1:0] r_sectored_hit_bits_lo_lo; // @[OneHot.scala:21:45]
assign r_sectored_hit_bits_lo_lo = _GEN_73; // @[OneHot.scala:21:45]
wire [1:0] _GEN_74 = {sector_hits_3, sector_hits_2}; // @[OneHot.scala:21:45]
wire [1:0] lo_hi; // @[OneHot.scala:21:45]
assign lo_hi = _GEN_74; // @[OneHot.scala:21:45]
wire [1:0] r_sectored_hit_bits_lo_hi; // @[OneHot.scala:21:45]
assign r_sectored_hit_bits_lo_hi = _GEN_74; // @[OneHot.scala:21:45]
wire [3:0] lo = {lo_hi, lo_lo}; // @[OneHot.scala:21:45]
wire [3:0] lo_1 = lo; // @[OneHot.scala:21:45, :31:18]
wire [1:0] _GEN_75 = {sector_hits_5, sector_hits_4}; // @[OneHot.scala:21:45]
wire [1:0] hi_lo; // @[OneHot.scala:21:45]
assign hi_lo = _GEN_75; // @[OneHot.scala:21:45]
wire [1:0] r_sectored_hit_bits_hi_lo; // @[OneHot.scala:21:45]
assign r_sectored_hit_bits_hi_lo = _GEN_75; // @[OneHot.scala:21:45]
wire [1:0] _GEN_76 = {sector_hits_7, sector_hits_6}; // @[OneHot.scala:21:45]
wire [1:0] hi_hi; // @[OneHot.scala:21:45]
assign hi_hi = _GEN_76; // @[OneHot.scala:21:45]
wire [1:0] r_sectored_hit_bits_hi_hi; // @[OneHot.scala:21:45]
assign r_sectored_hit_bits_hi_hi = _GEN_76; // @[OneHot.scala:21:45]
wire [3:0] hi = {hi_hi, hi_lo}; // @[OneHot.scala:21:45]
wire [3:0] hi_1 = hi; // @[OneHot.scala:21:45, :30:18]
wire [3:0] _T_33 = hi_1 | lo_1; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] hi_2 = _T_33[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] lo_2 = _T_33[1:0]; // @[OneHot.scala:31:18, :32:28]
wire [2:0] state_vec_0_touch_way_sized = {|hi_1, |hi_2, hi_2[1] | lo_2[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}]
wire _state_vec_0_set_left_older_T = state_vec_0_touch_way_sized[2]; // @[package.scala:163:13]
wire state_vec_0_set_left_older = ~_state_vec_0_set_left_older_T; // @[Replacement.scala:196:{33,43}]
wire [2:0] state_vec_0_left_subtree_state = state_vec_0[5:3]; // @[package.scala:163:13]
wire [2:0] r_sectored_repl_addr_left_subtree_state = state_vec_0[5:3]; // @[package.scala:163:13]
wire [2:0] state_vec_0_right_subtree_state = state_vec_0[2:0]; // @[Replacement.scala:198:38, :305:17]
wire [2:0] r_sectored_repl_addr_right_subtree_state = state_vec_0[2:0]; // @[Replacement.scala:198:38, :245:38, :305:17]
wire [1:0] _state_vec_0_T = state_vec_0_touch_way_sized[1:0]; // @[package.scala:163:13]
wire [1:0] _state_vec_0_T_11 = state_vec_0_touch_way_sized[1:0]; // @[package.scala:163:13]
wire _state_vec_0_set_left_older_T_1 = _state_vec_0_T[1]; // @[package.scala:163:13]
wire state_vec_0_set_left_older_1 = ~_state_vec_0_set_left_older_T_1; // @[Replacement.scala:196:{33,43}]
wire state_vec_0_left_subtree_state_1 = state_vec_0_left_subtree_state[1]; // @[package.scala:163:13]
wire state_vec_0_right_subtree_state_1 = state_vec_0_left_subtree_state[0]; // @[package.scala:163:13]
wire _state_vec_0_T_1 = _state_vec_0_T[0]; // @[package.scala:163:13]
wire _state_vec_0_T_5 = _state_vec_0_T[0]; // @[package.scala:163:13]
wire _state_vec_0_T_2 = _state_vec_0_T_1; // @[package.scala:163:13]
wire _state_vec_0_T_3 = ~_state_vec_0_T_2; // @[Replacement.scala:218:{7,17}]
wire _state_vec_0_T_4 = state_vec_0_set_left_older_1 ? state_vec_0_left_subtree_state_1 : _state_vec_0_T_3; // @[package.scala:163:13]
wire _state_vec_0_T_6 = _state_vec_0_T_5; // @[Replacement.scala:207:62, :218:17]
wire _state_vec_0_T_7 = ~_state_vec_0_T_6; // @[Replacement.scala:218:{7,17}]
wire _state_vec_0_T_8 = state_vec_0_set_left_older_1 ? _state_vec_0_T_7 : state_vec_0_right_subtree_state_1; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7]
wire [1:0] state_vec_0_hi = {state_vec_0_set_left_older_1, _state_vec_0_T_4}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [2:0] _state_vec_0_T_9 = {state_vec_0_hi, _state_vec_0_T_8}; // @[Replacement.scala:202:12, :206:16]
wire [2:0] _state_vec_0_T_10 = state_vec_0_set_left_older ? state_vec_0_left_subtree_state : _state_vec_0_T_9; // @[package.scala:163:13]
wire _state_vec_0_set_left_older_T_2 = _state_vec_0_T_11[1]; // @[Replacement.scala:196:43, :207:62]
wire state_vec_0_set_left_older_2 = ~_state_vec_0_set_left_older_T_2; // @[Replacement.scala:196:{33,43}]
wire state_vec_0_left_subtree_state_2 = state_vec_0_right_subtree_state[1]; // @[package.scala:163:13]
wire state_vec_0_right_subtree_state_2 = state_vec_0_right_subtree_state[0]; // @[Replacement.scala:198:38]
wire _state_vec_0_T_12 = _state_vec_0_T_11[0]; // @[package.scala:163:13]
wire _state_vec_0_T_16 = _state_vec_0_T_11[0]; // @[package.scala:163:13]
wire _state_vec_0_T_13 = _state_vec_0_T_12; // @[package.scala:163:13]
wire _state_vec_0_T_14 = ~_state_vec_0_T_13; // @[Replacement.scala:218:{7,17}]
wire _state_vec_0_T_15 = state_vec_0_set_left_older_2 ? state_vec_0_left_subtree_state_2 : _state_vec_0_T_14; // @[package.scala:163:13]
wire _state_vec_0_T_17 = _state_vec_0_T_16; // @[Replacement.scala:207:62, :218:17]
wire _state_vec_0_T_18 = ~_state_vec_0_T_17; // @[Replacement.scala:218:{7,17}]
wire _state_vec_0_T_19 = state_vec_0_set_left_older_2 ? _state_vec_0_T_18 : state_vec_0_right_subtree_state_2; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7]
wire [1:0] state_vec_0_hi_1 = {state_vec_0_set_left_older_2, _state_vec_0_T_15}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [2:0] _state_vec_0_T_20 = {state_vec_0_hi_1, _state_vec_0_T_19}; // @[Replacement.scala:202:12, :206:16]
wire [2:0] _state_vec_0_T_21 = state_vec_0_set_left_older ? _state_vec_0_T_20 : state_vec_0_right_subtree_state; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16]
wire [3:0] state_vec_0_hi_2 = {state_vec_0_set_left_older, _state_vec_0_T_10}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [6:0] _state_vec_0_T_22 = {state_vec_0_hi_2, _state_vec_0_T_21}; // @[Replacement.scala:202:12, :206:16]
wire [1:0] _GEN_77 = {superpage_hits_1, superpage_hits_0}; // @[OneHot.scala:21:45]
wire [1:0] lo_3; // @[OneHot.scala:21:45]
assign lo_3 = _GEN_77; // @[OneHot.scala:21:45]
wire [1:0] r_superpage_hit_bits_lo; // @[OneHot.scala:21:45]
assign r_superpage_hit_bits_lo = _GEN_77; // @[OneHot.scala:21:45]
wire [1:0] lo_4 = lo_3; // @[OneHot.scala:21:45, :31:18]
wire [1:0] _GEN_78 = {superpage_hits_3, superpage_hits_2}; // @[OneHot.scala:21:45]
wire [1:0] hi_3; // @[OneHot.scala:21:45]
assign hi_3 = _GEN_78; // @[OneHot.scala:21:45]
wire [1:0] r_superpage_hit_bits_hi; // @[OneHot.scala:21:45]
assign r_superpage_hit_bits_hi = _GEN_78; // @[OneHot.scala:21:45]
wire [1:0] hi_4 = hi_3; // @[OneHot.scala:21:45, :30:18]
wire [1:0] state_reg_touch_way_sized = {|hi_4, hi_4[1] | lo_4[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}]
wire _state_reg_set_left_older_T = state_reg_touch_way_sized[1]; // @[package.scala:163:13]
wire state_reg_set_left_older = ~_state_reg_set_left_older_T; // @[Replacement.scala:196:{33,43}]
wire state_reg_left_subtree_state = state_reg_1[1]; // @[package.scala:163:13]
wire r_superpage_repl_addr_left_subtree_state = state_reg_1[1]; // @[package.scala:163:13]
wire state_reg_right_subtree_state = state_reg_1[0]; // @[Replacement.scala:168:70, :198:38]
wire r_superpage_repl_addr_right_subtree_state = state_reg_1[0]; // @[Replacement.scala:168:70, :198:38, :245:38]
wire _state_reg_T = state_reg_touch_way_sized[0]; // @[package.scala:163:13]
wire _state_reg_T_4 = state_reg_touch_way_sized[0]; // @[package.scala:163:13]
wire _state_reg_T_1 = _state_reg_T; // @[package.scala:163:13]
wire _state_reg_T_2 = ~_state_reg_T_1; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_3 = state_reg_set_left_older ? state_reg_left_subtree_state : _state_reg_T_2; // @[package.scala:163:13]
wire _state_reg_T_5 = _state_reg_T_4; // @[Replacement.scala:207:62, :218:17]
wire _state_reg_T_6 = ~_state_reg_T_5; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_7 = state_reg_set_left_older ? _state_reg_T_6 : state_reg_right_subtree_state; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7]
wire [1:0] state_reg_hi = {state_reg_set_left_older, _state_reg_T_3}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [2:0] _state_reg_T_8 = {state_reg_hi, _state_reg_T_7}; // @[Replacement.scala:202:12, :206:16]
wire [5:0] _multipleHits_T = real_hits[5:0]; // @[package.scala:45:27]
wire [2:0] _multipleHits_T_1 = _multipleHits_T[2:0]; // @[Misc.scala:181:37]
wire _multipleHits_T_2 = _multipleHits_T_1[0]; // @[Misc.scala:181:37]
wire multipleHits_leftOne = _multipleHits_T_2; // @[Misc.scala:178:18, :181:37]
wire [1:0] _multipleHits_T_3 = _multipleHits_T_1[2:1]; // @[Misc.scala:181:37, :182:39]
wire _multipleHits_T_4 = _multipleHits_T_3[0]; // @[Misc.scala:181:37, :182:39]
wire multipleHits_leftOne_1 = _multipleHits_T_4; // @[Misc.scala:178:18, :181:37]
wire _multipleHits_T_5 = _multipleHits_T_3[1]; // @[Misc.scala:182:39]
wire multipleHits_rightOne = _multipleHits_T_5; // @[Misc.scala:178:18, :182:39]
wire multipleHits_rightOne_1 = multipleHits_leftOne_1 | multipleHits_rightOne; // @[Misc.scala:178:18, :183:16]
wire _multipleHits_T_7 = multipleHits_leftOne_1 & multipleHits_rightOne; // @[Misc.scala:178:18, :183:61]
wire multipleHits_rightTwo = _multipleHits_T_7; // @[Misc.scala:183:{49,61}]
wire _multipleHits_T_8 = multipleHits_rightTwo; // @[Misc.scala:183:{37,49}]
wire multipleHits_leftOne_2 = multipleHits_leftOne | multipleHits_rightOne_1; // @[Misc.scala:178:18, :183:16]
wire _multipleHits_T_9 = multipleHits_leftOne & multipleHits_rightOne_1; // @[Misc.scala:178:18, :183:{16,61}]
wire multipleHits_leftTwo = _multipleHits_T_8 | _multipleHits_T_9; // @[Misc.scala:183:{37,49,61}]
wire [2:0] _multipleHits_T_10 = _multipleHits_T[5:3]; // @[Misc.scala:181:37, :182:39]
wire _multipleHits_T_11 = _multipleHits_T_10[0]; // @[Misc.scala:181:37, :182:39]
wire multipleHits_leftOne_3 = _multipleHits_T_11; // @[Misc.scala:178:18, :181:37]
wire [1:0] _multipleHits_T_12 = _multipleHits_T_10[2:1]; // @[Misc.scala:182:39]
wire _multipleHits_T_13 = _multipleHits_T_12[0]; // @[Misc.scala:181:37, :182:39]
wire multipleHits_leftOne_4 = _multipleHits_T_13; // @[Misc.scala:178:18, :181:37]
wire _multipleHits_T_14 = _multipleHits_T_12[1]; // @[Misc.scala:182:39]
wire multipleHits_rightOne_2 = _multipleHits_T_14; // @[Misc.scala:178:18, :182:39]
wire multipleHits_rightOne_3 = multipleHits_leftOne_4 | multipleHits_rightOne_2; // @[Misc.scala:178:18, :183:16]
wire _multipleHits_T_16 = multipleHits_leftOne_4 & multipleHits_rightOne_2; // @[Misc.scala:178:18, :183:61]
wire multipleHits_rightTwo_1 = _multipleHits_T_16; // @[Misc.scala:183:{49,61}]
wire _multipleHits_T_17 = multipleHits_rightTwo_1; // @[Misc.scala:183:{37,49}]
wire multipleHits_rightOne_4 = multipleHits_leftOne_3 | multipleHits_rightOne_3; // @[Misc.scala:178:18, :183:16]
wire _multipleHits_T_18 = multipleHits_leftOne_3 & multipleHits_rightOne_3; // @[Misc.scala:178:18, :183:{16,61}]
wire multipleHits_rightTwo_2 = _multipleHits_T_17 | _multipleHits_T_18; // @[Misc.scala:183:{37,49,61}]
wire multipleHits_leftOne_5 = multipleHits_leftOne_2 | multipleHits_rightOne_4; // @[Misc.scala:183:16]
wire _multipleHits_T_19 = multipleHits_leftTwo | multipleHits_rightTwo_2; // @[Misc.scala:183:{37,49}]
wire _multipleHits_T_20 = multipleHits_leftOne_2 & multipleHits_rightOne_4; // @[Misc.scala:183:{16,61}]
wire multipleHits_leftTwo_1 = _multipleHits_T_19 | _multipleHits_T_20; // @[Misc.scala:183:{37,49,61}]
wire [6:0] _multipleHits_T_21 = real_hits[12:6]; // @[package.scala:45:27]
wire [2:0] _multipleHits_T_22 = _multipleHits_T_21[2:0]; // @[Misc.scala:181:37, :182:39]
wire _multipleHits_T_23 = _multipleHits_T_22[0]; // @[Misc.scala:181:37]
wire multipleHits_leftOne_6 = _multipleHits_T_23; // @[Misc.scala:178:18, :181:37]
wire [1:0] _multipleHits_T_24 = _multipleHits_T_22[2:1]; // @[Misc.scala:181:37, :182:39]
wire _multipleHits_T_25 = _multipleHits_T_24[0]; // @[Misc.scala:181:37, :182:39]
wire multipleHits_leftOne_7 = _multipleHits_T_25; // @[Misc.scala:178:18, :181:37]
wire _multipleHits_T_26 = _multipleHits_T_24[1]; // @[Misc.scala:182:39]
wire multipleHits_rightOne_5 = _multipleHits_T_26; // @[Misc.scala:178:18, :182:39]
wire multipleHits_rightOne_6 = multipleHits_leftOne_7 | multipleHits_rightOne_5; // @[Misc.scala:178:18, :183:16]
wire _multipleHits_T_28 = multipleHits_leftOne_7 & multipleHits_rightOne_5; // @[Misc.scala:178:18, :183:61]
wire multipleHits_rightTwo_3 = _multipleHits_T_28; // @[Misc.scala:183:{49,61}]
wire _multipleHits_T_29 = multipleHits_rightTwo_3; // @[Misc.scala:183:{37,49}]
wire multipleHits_leftOne_8 = multipleHits_leftOne_6 | multipleHits_rightOne_6; // @[Misc.scala:178:18, :183:16]
wire _multipleHits_T_30 = multipleHits_leftOne_6 & multipleHits_rightOne_6; // @[Misc.scala:178:18, :183:{16,61}]
wire multipleHits_leftTwo_2 = _multipleHits_T_29 | _multipleHits_T_30; // @[Misc.scala:183:{37,49,61}]
wire [3:0] _multipleHits_T_31 = _multipleHits_T_21[6:3]; // @[Misc.scala:182:39]
wire [1:0] _multipleHits_T_32 = _multipleHits_T_31[1:0]; // @[Misc.scala:181:37, :182:39]
wire _multipleHits_T_33 = _multipleHits_T_32[0]; // @[Misc.scala:181:37]
wire multipleHits_leftOne_9 = _multipleHits_T_33; // @[Misc.scala:178:18, :181:37]
wire _multipleHits_T_34 = _multipleHits_T_32[1]; // @[Misc.scala:181:37, :182:39]
wire multipleHits_rightOne_7 = _multipleHits_T_34; // @[Misc.scala:178:18, :182:39]
wire multipleHits_leftOne_10 = multipleHits_leftOne_9 | multipleHits_rightOne_7; // @[Misc.scala:178:18, :183:16]
wire _multipleHits_T_36 = multipleHits_leftOne_9 & multipleHits_rightOne_7; // @[Misc.scala:178:18, :183:61]
wire multipleHits_leftTwo_3 = _multipleHits_T_36; // @[Misc.scala:183:{49,61}]
wire [1:0] _multipleHits_T_37 = _multipleHits_T_31[3:2]; // @[Misc.scala:182:39]
wire _multipleHits_T_38 = _multipleHits_T_37[0]; // @[Misc.scala:181:37, :182:39]
wire multipleHits_leftOne_11 = _multipleHits_T_38; // @[Misc.scala:178:18, :181:37]
wire _multipleHits_T_39 = _multipleHits_T_37[1]; // @[Misc.scala:182:39]
wire multipleHits_rightOne_8 = _multipleHits_T_39; // @[Misc.scala:178:18, :182:39]
wire multipleHits_rightOne_9 = multipleHits_leftOne_11 | multipleHits_rightOne_8; // @[Misc.scala:178:18, :183:16]
wire _multipleHits_T_41 = multipleHits_leftOne_11 & multipleHits_rightOne_8; // @[Misc.scala:178:18, :183:61]
wire multipleHits_rightTwo_4 = _multipleHits_T_41; // @[Misc.scala:183:{49,61}]
wire multipleHits_rightOne_10 = multipleHits_leftOne_10 | multipleHits_rightOne_9; // @[Misc.scala:183:16]
wire _multipleHits_T_42 = multipleHits_leftTwo_3 | multipleHits_rightTwo_4; // @[Misc.scala:183:{37,49}]
wire _multipleHits_T_43 = multipleHits_leftOne_10 & multipleHits_rightOne_9; // @[Misc.scala:183:{16,61}]
wire multipleHits_rightTwo_5 = _multipleHits_T_42 | _multipleHits_T_43; // @[Misc.scala:183:{37,49,61}]
wire multipleHits_rightOne_11 = multipleHits_leftOne_8 | multipleHits_rightOne_10; // @[Misc.scala:183:16]
wire _multipleHits_T_44 = multipleHits_leftTwo_2 | multipleHits_rightTwo_5; // @[Misc.scala:183:{37,49}]
wire _multipleHits_T_45 = multipleHits_leftOne_8 & multipleHits_rightOne_10; // @[Misc.scala:183:{16,61}]
wire multipleHits_rightTwo_6 = _multipleHits_T_44 | _multipleHits_T_45; // @[Misc.scala:183:{37,49,61}]
wire _multipleHits_T_46 = multipleHits_leftOne_5 | multipleHits_rightOne_11; // @[Misc.scala:183:16]
wire _multipleHits_T_47 = multipleHits_leftTwo_1 | multipleHits_rightTwo_6; // @[Misc.scala:183:{37,49}]
wire _multipleHits_T_48 = multipleHits_leftOne_5 & multipleHits_rightOne_11; // @[Misc.scala:183:{16,61}]
wire multipleHits = _multipleHits_T_47 | _multipleHits_T_48; // @[Misc.scala:183:{37,49,61}]
assign _io_req_ready_T = state == 2'h0; // @[TLB.scala:352:22, :631:25]
assign io_req_ready_0 = _io_req_ready_T; // @[TLB.scala:318:7, :631:25]
wire _io_resp_pf_ld_T = bad_va & cmd_read; // @[TLB.scala:568:34, :633:28]
wire [13:0] _io_resp_pf_ld_T_1 = pf_ld_array & hits; // @[TLB.scala:442:17, :597:24, :633:57]
wire _io_resp_pf_ld_T_2 = |_io_resp_pf_ld_T_1; // @[TLB.scala:633:{57,65}]
assign _io_resp_pf_ld_T_3 = _io_resp_pf_ld_T | _io_resp_pf_ld_T_2; // @[TLB.scala:633:{28,41,65}]
assign io_resp_pf_ld_0 = _io_resp_pf_ld_T_3; // @[TLB.scala:318:7, :633:41]
wire _io_resp_pf_st_T = bad_va & cmd_write_perms; // @[TLB.scala:568:34, :577:35, :634:28]
wire [13:0] _io_resp_pf_st_T_1 = pf_st_array & hits; // @[TLB.scala:442:17, :598:24, :634:64]
wire _io_resp_pf_st_T_2 = |_io_resp_pf_st_T_1; // @[TLB.scala:634:{64,72}]
assign _io_resp_pf_st_T_3 = _io_resp_pf_st_T | _io_resp_pf_st_T_2; // @[TLB.scala:634:{28,48,72}]
assign io_resp_pf_st_0 = _io_resp_pf_st_T_3; // @[TLB.scala:318:7, :634:48]
wire [13:0] _io_resp_pf_inst_T = pf_inst_array & hits; // @[TLB.scala:442:17, :599:67, :635:47]
wire _io_resp_pf_inst_T_1 = |_io_resp_pf_inst_T; // @[TLB.scala:635:{47,55}]
assign _io_resp_pf_inst_T_2 = bad_va | _io_resp_pf_inst_T_1; // @[TLB.scala:568:34, :635:{29,55}]
assign io_resp_pf_inst_0 = _io_resp_pf_inst_T_2; // @[TLB.scala:318:7, :635:29]
wire [13:0] _io_resp_ae_ld_T = ae_ld_array & hits; // @[TLB.scala:442:17, :586:24, :641:33]
assign _io_resp_ae_ld_T_1 = |_io_resp_ae_ld_T; // @[TLB.scala:641:{33,41}]
assign io_resp_ae_ld_0 = _io_resp_ae_ld_T_1; // @[TLB.scala:318:7, :641:41]
wire [13:0] _io_resp_ae_st_T = ae_st_array & hits; // @[TLB.scala:442:17, :590:53, :642:33]
assign _io_resp_ae_st_T_1 = |_io_resp_ae_st_T; // @[TLB.scala:642:{33,41}]
assign io_resp_ae_st_0 = _io_resp_ae_st_T_1; // @[TLB.scala:318:7, :642:41]
wire [13:0] _io_resp_ae_inst_T = ~px_array; // @[TLB.scala:533:87, :643:23]
wire [13:0] _io_resp_ae_inst_T_1 = _io_resp_ae_inst_T & hits; // @[TLB.scala:442:17, :643:{23,33}]
assign _io_resp_ae_inst_T_2 = |_io_resp_ae_inst_T_1; // @[TLB.scala:643:{33,41}]
assign io_resp_ae_inst_0 = _io_resp_ae_inst_T_2; // @[TLB.scala:318:7, :643:41]
assign _io_resp_ma_ld_T = misaligned & cmd_read; // @[TLB.scala:550:77, :645:31]
assign io_resp_ma_ld_0 = _io_resp_ma_ld_T; // @[TLB.scala:318:7, :645:31]
assign _io_resp_ma_st_T = misaligned & cmd_write; // @[TLB.scala:550:77, :646:31]
assign io_resp_ma_st_0 = _io_resp_ma_st_T; // @[TLB.scala:318:7, :646:31]
wire [13:0] _io_resp_cacheable_T = c_array & hits; // @[TLB.scala:442:17, :537:20, :648:33]
assign _io_resp_cacheable_T_1 = |_io_resp_cacheable_T; // @[TLB.scala:648:{33,41}]
assign io_resp_cacheable_0 = _io_resp_cacheable_T_1; // @[TLB.scala:318:7, :648:41]
wire [13:0] _io_resp_must_alloc_T = must_alloc_array & hits; // @[TLB.scala:442:17, :595:46, :649:43]
assign _io_resp_must_alloc_T_1 = |_io_resp_must_alloc_T; // @[TLB.scala:649:{43,51}]
assign io_resp_must_alloc_0 = _io_resp_must_alloc_T_1; // @[TLB.scala:318:7, :649:51]
wire [13:0] _io_resp_prefetchable_T = prefetchable_array & hits; // @[TLB.scala:442:17, :547:31, :650:47]
wire _io_resp_prefetchable_T_1 = |_io_resp_prefetchable_T; // @[TLB.scala:650:{47,55}]
assign _io_resp_prefetchable_T_2 = _io_resp_prefetchable_T_1; // @[TLB.scala:650:{55,59}]
assign io_resp_prefetchable_0 = _io_resp_prefetchable_T_2; // @[TLB.scala:318:7, :650:59]
wire _io_resp_miss_T_1 = _io_resp_miss_T | tlb_miss; // @[TLB.scala:613:64, :651:{29,52}]
assign _io_resp_miss_T_2 = _io_resp_miss_T_1 | multipleHits; // @[Misc.scala:183:49]
assign io_resp_miss_0 = _io_resp_miss_T_2; // @[TLB.scala:318:7, :651:64]
assign _io_resp_paddr_T_1 = {ppn, _io_resp_paddr_T}; // @[Mux.scala:30:73]
assign io_resp_paddr_0 = _io_resp_paddr_T_1; // @[TLB.scala:318:7, :652:23]
wire [27:0] _io_resp_gpa_page_T_1 = {1'h0, vpn}; // @[TLB.scala:335:30, :657:36]
wire [27:0] io_resp_gpa_page = _io_resp_gpa_page_T_1; // @[TLB.scala:657:{19,36}]
wire [26:0] _io_resp_gpa_page_T_2 = r_gpa[38:12]; // @[TLB.scala:363:18, :657:58]
wire [11:0] _io_resp_gpa_offset_T = r_gpa[11:0]; // @[TLB.scala:363:18, :658:47]
wire [11:0] io_resp_gpa_offset = _io_resp_gpa_offset_T_1; // @[TLB.scala:658:{21,82}]
assign _io_resp_gpa_T = {io_resp_gpa_page, io_resp_gpa_offset}; // @[TLB.scala:657:19, :658:21, :659:8]
assign io_resp_gpa_0 = _io_resp_gpa_T; // @[TLB.scala:318:7, :659:8]
assign io_ptw_req_valid_0 = _io_ptw_req_valid_T; // @[TLB.scala:318:7, :662:29]
wire r_superpage_repl_addr_left_subtree_older = state_reg_1[2]; // @[Replacement.scala:168:70, :243:38]
wire _r_superpage_repl_addr_T = r_superpage_repl_addr_left_subtree_state; // @[package.scala:163:13]
wire _r_superpage_repl_addr_T_1 = r_superpage_repl_addr_right_subtree_state; // @[Replacement.scala:245:38, :262:12]
wire _r_superpage_repl_addr_T_2 = r_superpage_repl_addr_left_subtree_older ? _r_superpage_repl_addr_T : _r_superpage_repl_addr_T_1; // @[Replacement.scala:243:38, :250:16, :262:12]
wire [1:0] _r_superpage_repl_addr_T_3 = {r_superpage_repl_addr_left_subtree_older, _r_superpage_repl_addr_T_2}; // @[Replacement.scala:243:38, :249:12, :250:16]
wire [1:0] r_superpage_repl_addr_valids_lo = {superpage_entries_1_valid_0, superpage_entries_0_valid_0}; // @[package.scala:45:27]
wire [1:0] r_superpage_repl_addr_valids_hi = {superpage_entries_3_valid_0, superpage_entries_2_valid_0}; // @[package.scala:45:27]
wire [3:0] r_superpage_repl_addr_valids = {r_superpage_repl_addr_valids_hi, r_superpage_repl_addr_valids_lo}; // @[package.scala:45:27]
wire _r_superpage_repl_addr_T_4 = &r_superpage_repl_addr_valids; // @[package.scala:45:27]
wire [3:0] _r_superpage_repl_addr_T_5 = ~r_superpage_repl_addr_valids; // @[package.scala:45:27]
wire _r_superpage_repl_addr_T_6 = _r_superpage_repl_addr_T_5[0]; // @[OneHot.scala:48:45]
wire _r_superpage_repl_addr_T_7 = _r_superpage_repl_addr_T_5[1]; // @[OneHot.scala:48:45]
wire _r_superpage_repl_addr_T_8 = _r_superpage_repl_addr_T_5[2]; // @[OneHot.scala:48:45]
wire _r_superpage_repl_addr_T_9 = _r_superpage_repl_addr_T_5[3]; // @[OneHot.scala:48:45]
wire [1:0] _r_superpage_repl_addr_T_10 = {1'h1, ~_r_superpage_repl_addr_T_8}; // @[OneHot.scala:48:45]
wire [1:0] _r_superpage_repl_addr_T_11 = _r_superpage_repl_addr_T_7 ? 2'h1 : _r_superpage_repl_addr_T_10; // @[OneHot.scala:48:45]
wire [1:0] _r_superpage_repl_addr_T_12 = _r_superpage_repl_addr_T_6 ? 2'h0 : _r_superpage_repl_addr_T_11; // @[OneHot.scala:48:45]
wire [1:0] _r_superpage_repl_addr_T_13 = _r_superpage_repl_addr_T_4 ? _r_superpage_repl_addr_T_3 : _r_superpage_repl_addr_T_12; // @[Mux.scala:50:70]
wire r_sectored_repl_addr_left_subtree_older = state_vec_0[6]; // @[Replacement.scala:243:38, :305:17]
wire r_sectored_repl_addr_left_subtree_older_1 = r_sectored_repl_addr_left_subtree_state[2]; // @[package.scala:163:13]
wire r_sectored_repl_addr_left_subtree_state_1 = r_sectored_repl_addr_left_subtree_state[1]; // @[package.scala:163:13]
wire _r_sectored_repl_addr_T = r_sectored_repl_addr_left_subtree_state_1; // @[package.scala:163:13]
wire r_sectored_repl_addr_right_subtree_state_1 = r_sectored_repl_addr_left_subtree_state[0]; // @[package.scala:163:13]
wire _r_sectored_repl_addr_T_1 = r_sectored_repl_addr_right_subtree_state_1; // @[Replacement.scala:245:38, :262:12]
wire _r_sectored_repl_addr_T_2 = r_sectored_repl_addr_left_subtree_older_1 ? _r_sectored_repl_addr_T : _r_sectored_repl_addr_T_1; // @[Replacement.scala:243:38, :250:16, :262:12]
wire [1:0] _r_sectored_repl_addr_T_3 = {r_sectored_repl_addr_left_subtree_older_1, _r_sectored_repl_addr_T_2}; // @[Replacement.scala:243:38, :249:12, :250:16]
wire r_sectored_repl_addr_left_subtree_older_2 = r_sectored_repl_addr_right_subtree_state[2]; // @[Replacement.scala:243:38, :245:38]
wire r_sectored_repl_addr_left_subtree_state_2 = r_sectored_repl_addr_right_subtree_state[1]; // @[package.scala:163:13]
wire _r_sectored_repl_addr_T_4 = r_sectored_repl_addr_left_subtree_state_2; // @[package.scala:163:13]
wire r_sectored_repl_addr_right_subtree_state_2 = r_sectored_repl_addr_right_subtree_state[0]; // @[Replacement.scala:245:38]
wire _r_sectored_repl_addr_T_5 = r_sectored_repl_addr_right_subtree_state_2; // @[Replacement.scala:245:38, :262:12]
wire _r_sectored_repl_addr_T_6 = r_sectored_repl_addr_left_subtree_older_2 ? _r_sectored_repl_addr_T_4 : _r_sectored_repl_addr_T_5; // @[Replacement.scala:243:38, :250:16, :262:12]
wire [1:0] _r_sectored_repl_addr_T_7 = {r_sectored_repl_addr_left_subtree_older_2, _r_sectored_repl_addr_T_6}; // @[Replacement.scala:243:38, :249:12, :250:16]
wire [1:0] _r_sectored_repl_addr_T_8 = r_sectored_repl_addr_left_subtree_older ? _r_sectored_repl_addr_T_3 : _r_sectored_repl_addr_T_7; // @[Replacement.scala:243:38, :249:12, :250:16]
wire [2:0] _r_sectored_repl_addr_T_9 = {r_sectored_repl_addr_left_subtree_older, _r_sectored_repl_addr_T_8}; // @[Replacement.scala:243:38, :249:12, :250:16]
wire _r_sectored_repl_addr_valids_T_1 = _r_sectored_repl_addr_valids_T | sectored_entries_0_0_valid_2; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_2 = _r_sectored_repl_addr_valids_T_1 | sectored_entries_0_0_valid_3; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_4 = _r_sectored_repl_addr_valids_T_3 | sectored_entries_0_1_valid_2; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_5 = _r_sectored_repl_addr_valids_T_4 | sectored_entries_0_1_valid_3; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_7 = _r_sectored_repl_addr_valids_T_6 | sectored_entries_0_2_valid_2; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_8 = _r_sectored_repl_addr_valids_T_7 | sectored_entries_0_2_valid_3; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_10 = _r_sectored_repl_addr_valids_T_9 | sectored_entries_0_3_valid_2; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_11 = _r_sectored_repl_addr_valids_T_10 | sectored_entries_0_3_valid_3; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_13 = _r_sectored_repl_addr_valids_T_12 | sectored_entries_0_4_valid_2; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_14 = _r_sectored_repl_addr_valids_T_13 | sectored_entries_0_4_valid_3; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_16 = _r_sectored_repl_addr_valids_T_15 | sectored_entries_0_5_valid_2; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_17 = _r_sectored_repl_addr_valids_T_16 | sectored_entries_0_5_valid_3; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_19 = _r_sectored_repl_addr_valids_T_18 | sectored_entries_0_6_valid_2; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_20 = _r_sectored_repl_addr_valids_T_19 | sectored_entries_0_6_valid_3; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_22 = _r_sectored_repl_addr_valids_T_21 | sectored_entries_0_7_valid_2; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_23 = _r_sectored_repl_addr_valids_T_22 | sectored_entries_0_7_valid_3; // @[package.scala:81:59]
wire [1:0] r_sectored_repl_addr_valids_lo_lo = {_r_sectored_repl_addr_valids_T_5, _r_sectored_repl_addr_valids_T_2}; // @[package.scala:45:27, :81:59]
wire [1:0] r_sectored_repl_addr_valids_lo_hi = {_r_sectored_repl_addr_valids_T_11, _r_sectored_repl_addr_valids_T_8}; // @[package.scala:45:27, :81:59]
wire [3:0] r_sectored_repl_addr_valids_lo = {r_sectored_repl_addr_valids_lo_hi, r_sectored_repl_addr_valids_lo_lo}; // @[package.scala:45:27]
wire [1:0] r_sectored_repl_addr_valids_hi_lo = {_r_sectored_repl_addr_valids_T_17, _r_sectored_repl_addr_valids_T_14}; // @[package.scala:45:27, :81:59]
wire [1:0] r_sectored_repl_addr_valids_hi_hi = {_r_sectored_repl_addr_valids_T_23, _r_sectored_repl_addr_valids_T_20}; // @[package.scala:45:27, :81:59]
wire [3:0] r_sectored_repl_addr_valids_hi = {r_sectored_repl_addr_valids_hi_hi, r_sectored_repl_addr_valids_hi_lo}; // @[package.scala:45:27]
wire [7:0] r_sectored_repl_addr_valids = {r_sectored_repl_addr_valids_hi, r_sectored_repl_addr_valids_lo}; // @[package.scala:45:27]
wire _r_sectored_repl_addr_T_10 = &r_sectored_repl_addr_valids; // @[package.scala:45:27]
wire [7:0] _r_sectored_repl_addr_T_11 = ~r_sectored_repl_addr_valids; // @[package.scala:45:27]
wire _r_sectored_repl_addr_T_12 = _r_sectored_repl_addr_T_11[0]; // @[OneHot.scala:48:45]
wire _r_sectored_repl_addr_T_13 = _r_sectored_repl_addr_T_11[1]; // @[OneHot.scala:48:45]
wire _r_sectored_repl_addr_T_14 = _r_sectored_repl_addr_T_11[2]; // @[OneHot.scala:48:45]
wire _r_sectored_repl_addr_T_15 = _r_sectored_repl_addr_T_11[3]; // @[OneHot.scala:48:45]
wire _r_sectored_repl_addr_T_16 = _r_sectored_repl_addr_T_11[4]; // @[OneHot.scala:48:45]
wire _r_sectored_repl_addr_T_17 = _r_sectored_repl_addr_T_11[5]; // @[OneHot.scala:48:45]
wire _r_sectored_repl_addr_T_18 = _r_sectored_repl_addr_T_11[6]; // @[OneHot.scala:48:45]
wire _r_sectored_repl_addr_T_19 = _r_sectored_repl_addr_T_11[7]; // @[OneHot.scala:48:45]
wire [2:0] _r_sectored_repl_addr_T_20 = {2'h3, ~_r_sectored_repl_addr_T_18}; // @[OneHot.scala:48:45]
wire [2:0] _r_sectored_repl_addr_T_21 = _r_sectored_repl_addr_T_17 ? 3'h5 : _r_sectored_repl_addr_T_20; // @[OneHot.scala:48:45]
wire [2:0] _r_sectored_repl_addr_T_22 = _r_sectored_repl_addr_T_16 ? 3'h4 : _r_sectored_repl_addr_T_21; // @[OneHot.scala:48:45]
wire [2:0] _r_sectored_repl_addr_T_23 = _r_sectored_repl_addr_T_15 ? 3'h3 : _r_sectored_repl_addr_T_22; // @[OneHot.scala:48:45]
wire [2:0] _r_sectored_repl_addr_T_24 = _r_sectored_repl_addr_T_14 ? 3'h2 : _r_sectored_repl_addr_T_23; // @[OneHot.scala:48:45]
wire [2:0] _r_sectored_repl_addr_T_25 = _r_sectored_repl_addr_T_13 ? 3'h1 : _r_sectored_repl_addr_T_24; // @[OneHot.scala:48:45]
wire [2:0] _r_sectored_repl_addr_T_26 = _r_sectored_repl_addr_T_12 ? 3'h0 : _r_sectored_repl_addr_T_25; // @[OneHot.scala:48:45]
wire [2:0] _r_sectored_repl_addr_T_27 = _r_sectored_repl_addr_T_10 ? _r_sectored_repl_addr_T_9 : _r_sectored_repl_addr_T_26; // @[Mux.scala:50:70]
wire _r_sectored_hit_valid_T = sector_hits_0 | sector_hits_1; // @[package.scala:81:59]
wire _r_sectored_hit_valid_T_1 = _r_sectored_hit_valid_T | sector_hits_2; // @[package.scala:81:59]
wire _r_sectored_hit_valid_T_2 = _r_sectored_hit_valid_T_1 | sector_hits_3; // @[package.scala:81:59]
wire _r_sectored_hit_valid_T_3 = _r_sectored_hit_valid_T_2 | sector_hits_4; // @[package.scala:81:59]
wire _r_sectored_hit_valid_T_4 = _r_sectored_hit_valid_T_3 | sector_hits_5; // @[package.scala:81:59]
wire _r_sectored_hit_valid_T_5 = _r_sectored_hit_valid_T_4 | sector_hits_6; // @[package.scala:81:59]
wire _r_sectored_hit_valid_T_6 = _r_sectored_hit_valid_T_5 | sector_hits_7; // @[package.scala:81:59]
wire [3:0] r_sectored_hit_bits_lo = {r_sectored_hit_bits_lo_hi, r_sectored_hit_bits_lo_lo}; // @[OneHot.scala:21:45]
wire [3:0] r_sectored_hit_bits_hi = {r_sectored_hit_bits_hi_hi, r_sectored_hit_bits_hi_lo}; // @[OneHot.scala:21:45]
wire [7:0] _r_sectored_hit_bits_T = {r_sectored_hit_bits_hi, r_sectored_hit_bits_lo}; // @[OneHot.scala:21:45]
wire [3:0] r_sectored_hit_bits_hi_1 = _r_sectored_hit_bits_T[7:4]; // @[OneHot.scala:21:45, :30:18]
wire [3:0] r_sectored_hit_bits_lo_1 = _r_sectored_hit_bits_T[3:0]; // @[OneHot.scala:21:45, :31:18]
wire _r_sectored_hit_bits_T_1 = |r_sectored_hit_bits_hi_1; // @[OneHot.scala:30:18, :32:14]
wire [3:0] _r_sectored_hit_bits_T_2 = r_sectored_hit_bits_hi_1 | r_sectored_hit_bits_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] r_sectored_hit_bits_hi_2 = _r_sectored_hit_bits_T_2[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] r_sectored_hit_bits_lo_2 = _r_sectored_hit_bits_T_2[1:0]; // @[OneHot.scala:31:18, :32:28]
wire _r_sectored_hit_bits_T_3 = |r_sectored_hit_bits_hi_2; // @[OneHot.scala:30:18, :32:14]
wire [1:0] _r_sectored_hit_bits_T_4 = r_sectored_hit_bits_hi_2 | r_sectored_hit_bits_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28]
wire _r_sectored_hit_bits_T_5 = _r_sectored_hit_bits_T_4[1]; // @[OneHot.scala:32:28]
wire [1:0] _r_sectored_hit_bits_T_6 = {_r_sectored_hit_bits_T_3, _r_sectored_hit_bits_T_5}; // @[OneHot.scala:32:{10,14}]
wire [2:0] _r_sectored_hit_bits_T_7 = {_r_sectored_hit_bits_T_1, _r_sectored_hit_bits_T_6}; // @[OneHot.scala:32:{10,14}]
wire _r_superpage_hit_valid_T = superpage_hits_0 | superpage_hits_1; // @[package.scala:81:59]
wire _r_superpage_hit_valid_T_1 = _r_superpage_hit_valid_T | superpage_hits_2; // @[package.scala:81:59]
wire _r_superpage_hit_valid_T_2 = _r_superpage_hit_valid_T_1 | superpage_hits_3; // @[package.scala:81:59]
wire [3:0] _r_superpage_hit_bits_T = {r_superpage_hit_bits_hi, r_superpage_hit_bits_lo}; // @[OneHot.scala:21:45]
wire [1:0] r_superpage_hit_bits_hi_1 = _r_superpage_hit_bits_T[3:2]; // @[OneHot.scala:21:45, :30:18]
wire [1:0] r_superpage_hit_bits_lo_1 = _r_superpage_hit_bits_T[1:0]; // @[OneHot.scala:21:45, :31:18]
wire _r_superpage_hit_bits_T_1 = |r_superpage_hit_bits_hi_1; // @[OneHot.scala:30:18, :32:14]
wire [1:0] _r_superpage_hit_bits_T_2 = r_superpage_hit_bits_hi_1 | r_superpage_hit_bits_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28]
wire _r_superpage_hit_bits_T_3 = _r_superpage_hit_bits_T_2[1]; // @[OneHot.scala:32:28]
wire [1:0] _r_superpage_hit_bits_T_4 = {_r_superpage_hit_bits_T_1, _r_superpage_hit_bits_T_3}; // @[OneHot.scala:32:{10,14}]
wire [1:0] _state_T = {1'h1, io_sfence_valid_0}; // @[TLB.scala:318:7, :704:45] |
Generate the Verilog code corresponding to this FIRRTL code module TLDebugModuleInnerAsync :
output auto : { flip dmiXing_in : { a : { mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip b : { mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, c : { mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip d : { mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, e : { mem : { sink : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}}, dmInner_sb2tlOpt_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}}, flip dmInner_custom_in : { flip addr : UInt<1>, data : UInt<0>, ready : UInt<1>, flip valid : UInt<1>}, flip dmInner_tl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
output io : { flip debug_clock : Clock, flip debug_reset : Reset, flip tl_clock : Clock, flip tl_reset : Reset, flip dmactive : UInt<1>, flip innerCtrl : { mem : { resumereq : UInt<1>, hartsel : UInt<10>, ackhavereset : UInt<1>, hasel : UInt<1>, hamask : UInt<1>[1], hrmask : UInt<1>[1]}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip debugUnavail : UInt<1>[1], hgDebugInt : UInt<1>[1], flip hartIsInReset : UInt<1>[1]}
input rf_reset : Reset
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset
inst dmInner of TLDebugModuleInner
connect dmInner.clock, childClock
connect dmInner.reset, childReset
inst dmiXing of TLAsyncCrossingSink_a9d32s1k1z2u
connect dmiXing.clock, childClock
connect dmiXing.reset, childReset
connect dmInner.auto.dmi_in, dmiXing.auto.out
connect dmInner.auto.tl_in, auto.dmInner_tl_in
connect dmInner.auto.custom_in, auto.dmInner_custom_in
connect dmInner.auto.sb2tlOpt_out.d, auto.dmInner_sb2tlOpt_out.d
connect auto.dmInner_sb2tlOpt_out.a.bits, dmInner.auto.sb2tlOpt_out.a.bits
connect auto.dmInner_sb2tlOpt_out.a.valid, dmInner.auto.sb2tlOpt_out.a.valid
connect dmInner.auto.sb2tlOpt_out.a.ready, auto.dmInner_sb2tlOpt_out.a.ready
connect dmiXing.auto.in, auto.dmiXing_in
connect childClock, io.debug_clock
connect childReset, io.debug_reset
inst dmactive_synced_dmactive_synced_dmactiveSync of AsyncResetSynchronizerShiftReg_w1_d3_i0_27
connect dmactive_synced_dmactive_synced_dmactiveSync.clock, childClock
connect dmactive_synced_dmactive_synced_dmactiveSync.reset, childReset
connect dmactive_synced_dmactive_synced_dmactiveSync.io.d, io.dmactive
wire dmactive_synced : UInt<1>
connect dmactive_synced, dmactive_synced_dmactive_synced_dmactiveSync.io.q
connect dmInner.clock, io.debug_clock
connect dmInner.reset, io.debug_reset
connect dmInner.io.tl_clock, io.tl_clock
connect dmInner.io.tl_reset, io.tl_reset
connect dmInner.io.dmactive, dmactive_synced
inst dmactive_synced_dmInner_io_innerCtrl_sink of AsyncQueueSink_DebugInternalBundle
connect dmactive_synced_dmInner_io_innerCtrl_sink.clock, childClock
connect dmactive_synced_dmInner_io_innerCtrl_sink.reset, childReset
connect dmactive_synced_dmInner_io_innerCtrl_sink.io.async, io.innerCtrl
connect dmInner.io.innerCtrl, dmactive_synced_dmInner_io_innerCtrl_sink.io.deq
connect dmInner.io.debugUnavail[0], io.debugUnavail[0]
connect io.hgDebugInt, dmInner.io.hgDebugInt
connect dmInner.io.hartIsInReset[0], io.hartIsInReset[0] | module TLDebugModuleInnerAsync( // @[Debug.scala:1871:9]
input [2:0] auto_dmiXing_in_a_mem_0_opcode, // @[LazyModuleImp.scala:107:25]
input [8:0] auto_dmiXing_in_a_mem_0_address, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_dmiXing_in_a_mem_0_data, // @[LazyModuleImp.scala:107:25]
output auto_dmiXing_in_a_ridx, // @[LazyModuleImp.scala:107:25]
input auto_dmiXing_in_a_widx, // @[LazyModuleImp.scala:107:25]
output auto_dmiXing_in_a_safe_ridx_valid, // @[LazyModuleImp.scala:107:25]
input auto_dmiXing_in_a_safe_widx_valid, // @[LazyModuleImp.scala:107:25]
input auto_dmiXing_in_a_safe_source_reset_n, // @[LazyModuleImp.scala:107:25]
output auto_dmiXing_in_a_safe_sink_reset_n, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_dmiXing_in_d_mem_0_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_dmiXing_in_d_mem_0_size, // @[LazyModuleImp.scala:107:25]
output auto_dmiXing_in_d_mem_0_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_dmiXing_in_d_mem_0_data, // @[LazyModuleImp.scala:107:25]
input auto_dmiXing_in_d_ridx, // @[LazyModuleImp.scala:107:25]
output auto_dmiXing_in_d_widx, // @[LazyModuleImp.scala:107:25]
input auto_dmiXing_in_d_safe_ridx_valid, // @[LazyModuleImp.scala:107:25]
output auto_dmiXing_in_d_safe_widx_valid, // @[LazyModuleImp.scala:107:25]
output auto_dmiXing_in_d_safe_source_reset_n, // @[LazyModuleImp.scala:107:25]
input auto_dmiXing_in_d_safe_sink_reset_n, // @[LazyModuleImp.scala:107:25]
input auto_dmInner_sb2tlOpt_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_dmInner_sb2tlOpt_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_dmInner_sb2tlOpt_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_dmInner_sb2tlOpt_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_dmInner_sb2tlOpt_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_dmInner_sb2tlOpt_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_dmInner_sb2tlOpt_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_dmInner_sb2tlOpt_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dmInner_sb2tlOpt_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dmInner_sb2tlOpt_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_dmInner_sb2tlOpt_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_dmInner_sb2tlOpt_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_dmInner_sb2tlOpt_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_dmInner_sb2tlOpt_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_dmInner_sb2tlOpt_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_dmInner_tl_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_dmInner_tl_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dmInner_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dmInner_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dmInner_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [11:0] auto_dmInner_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [11:0] auto_dmInner_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_dmInner_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_dmInner_tl_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_dmInner_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_dmInner_tl_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_dmInner_tl_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_dmInner_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_dmInner_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [11:0] auto_dmInner_tl_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_dmInner_tl_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
input io_debug_clock, // @[Debug.scala:1877:16]
input io_debug_reset, // @[Debug.scala:1877:16]
input io_tl_clock, // @[Debug.scala:1877:16]
input io_tl_reset, // @[Debug.scala:1877:16]
input io_dmactive, // @[Debug.scala:1877:16]
input io_innerCtrl_mem_0_resumereq, // @[Debug.scala:1877:16]
input [9:0] io_innerCtrl_mem_0_hartsel, // @[Debug.scala:1877:16]
input io_innerCtrl_mem_0_ackhavereset, // @[Debug.scala:1877:16]
input io_innerCtrl_mem_0_hrmask_0, // @[Debug.scala:1877:16]
output io_innerCtrl_ridx, // @[Debug.scala:1877:16]
input io_innerCtrl_widx, // @[Debug.scala:1877:16]
output io_innerCtrl_safe_ridx_valid, // @[Debug.scala:1877:16]
input io_innerCtrl_safe_widx_valid, // @[Debug.scala:1877:16]
input io_innerCtrl_safe_source_reset_n, // @[Debug.scala:1877:16]
output io_innerCtrl_safe_sink_reset_n, // @[Debug.scala:1877:16]
output io_hgDebugInt_0, // @[Debug.scala:1877:16]
input io_hartIsInReset_0, // @[Debug.scala:1877:16]
input rf_reset // @[Debug.scala:1904:22]
);
wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_valid; // @[AsyncQueue.scala:211:22]
wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_resumereq; // @[AsyncQueue.scala:211:22]
wire [9:0] _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hartsel; // @[AsyncQueue.scala:211:22]
wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_ackhavereset; // @[AsyncQueue.scala:211:22]
wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hasel; // @[AsyncQueue.scala:211:22]
wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_0; // @[AsyncQueue.scala:211:22]
wire _dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_0; // @[AsyncQueue.scala:211:22]
wire _dmiXing_auto_out_a_valid; // @[Debug.scala:1858:27]
wire [2:0] _dmiXing_auto_out_a_bits_opcode; // @[Debug.scala:1858:27]
wire [2:0] _dmiXing_auto_out_a_bits_param; // @[Debug.scala:1858:27]
wire [1:0] _dmiXing_auto_out_a_bits_size; // @[Debug.scala:1858:27]
wire _dmiXing_auto_out_a_bits_source; // @[Debug.scala:1858:27]
wire [8:0] _dmiXing_auto_out_a_bits_address; // @[Debug.scala:1858:27]
wire [3:0] _dmiXing_auto_out_a_bits_mask; // @[Debug.scala:1858:27]
wire [31:0] _dmiXing_auto_out_a_bits_data; // @[Debug.scala:1858:27]
wire _dmiXing_auto_out_a_bits_corrupt; // @[Debug.scala:1858:27]
wire _dmiXing_auto_out_d_ready; // @[Debug.scala:1858:27]
wire _dmInner_auto_dmi_in_a_ready; // @[Debug.scala:1857:27]
wire _dmInner_auto_dmi_in_d_valid; // @[Debug.scala:1857:27]
wire [2:0] _dmInner_auto_dmi_in_d_bits_opcode; // @[Debug.scala:1857:27]
wire [1:0] _dmInner_auto_dmi_in_d_bits_size; // @[Debug.scala:1857:27]
wire _dmInner_auto_dmi_in_d_bits_source; // @[Debug.scala:1857:27]
wire [31:0] _dmInner_auto_dmi_in_d_bits_data; // @[Debug.scala:1857:27]
wire [2:0] auto_dmiXing_in_a_mem_0_opcode_0 = auto_dmiXing_in_a_mem_0_opcode; // @[Debug.scala:1871:9]
wire [8:0] auto_dmiXing_in_a_mem_0_address_0 = auto_dmiXing_in_a_mem_0_address; // @[Debug.scala:1871:9]
wire [31:0] auto_dmiXing_in_a_mem_0_data_0 = auto_dmiXing_in_a_mem_0_data; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_a_widx_0 = auto_dmiXing_in_a_widx; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_a_safe_widx_valid_0 = auto_dmiXing_in_a_safe_widx_valid; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_a_safe_source_reset_n_0 = auto_dmiXing_in_a_safe_source_reset_n; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_d_ridx_0 = auto_dmiXing_in_d_ridx; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_d_safe_ridx_valid_0 = auto_dmiXing_in_d_safe_ridx_valid; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_d_safe_sink_reset_n_0 = auto_dmiXing_in_d_safe_sink_reset_n; // @[Debug.scala:1871:9]
wire auto_dmInner_sb2tlOpt_out_a_ready_0 = auto_dmInner_sb2tlOpt_out_a_ready; // @[Debug.scala:1871:9]
wire auto_dmInner_sb2tlOpt_out_d_valid_0 = auto_dmInner_sb2tlOpt_out_d_valid; // @[Debug.scala:1871:9]
wire [2:0] auto_dmInner_sb2tlOpt_out_d_bits_opcode_0 = auto_dmInner_sb2tlOpt_out_d_bits_opcode; // @[Debug.scala:1871:9]
wire [1:0] auto_dmInner_sb2tlOpt_out_d_bits_param_0 = auto_dmInner_sb2tlOpt_out_d_bits_param; // @[Debug.scala:1871:9]
wire [3:0] auto_dmInner_sb2tlOpt_out_d_bits_size_0 = auto_dmInner_sb2tlOpt_out_d_bits_size; // @[Debug.scala:1871:9]
wire [3:0] auto_dmInner_sb2tlOpt_out_d_bits_sink_0 = auto_dmInner_sb2tlOpt_out_d_bits_sink; // @[Debug.scala:1871:9]
wire auto_dmInner_sb2tlOpt_out_d_bits_denied_0 = auto_dmInner_sb2tlOpt_out_d_bits_denied; // @[Debug.scala:1871:9]
wire [7:0] auto_dmInner_sb2tlOpt_out_d_bits_data_0 = auto_dmInner_sb2tlOpt_out_d_bits_data; // @[Debug.scala:1871:9]
wire auto_dmInner_sb2tlOpt_out_d_bits_corrupt_0 = auto_dmInner_sb2tlOpt_out_d_bits_corrupt; // @[Debug.scala:1871:9]
wire auto_dmInner_tl_in_a_valid_0 = auto_dmInner_tl_in_a_valid; // @[Debug.scala:1871:9]
wire [2:0] auto_dmInner_tl_in_a_bits_opcode_0 = auto_dmInner_tl_in_a_bits_opcode; // @[Debug.scala:1871:9]
wire [2:0] auto_dmInner_tl_in_a_bits_param_0 = auto_dmInner_tl_in_a_bits_param; // @[Debug.scala:1871:9]
wire [1:0] auto_dmInner_tl_in_a_bits_size_0 = auto_dmInner_tl_in_a_bits_size; // @[Debug.scala:1871:9]
wire [11:0] auto_dmInner_tl_in_a_bits_source_0 = auto_dmInner_tl_in_a_bits_source; // @[Debug.scala:1871:9]
wire [11:0] auto_dmInner_tl_in_a_bits_address_0 = auto_dmInner_tl_in_a_bits_address; // @[Debug.scala:1871:9]
wire [7:0] auto_dmInner_tl_in_a_bits_mask_0 = auto_dmInner_tl_in_a_bits_mask; // @[Debug.scala:1871:9]
wire [63:0] auto_dmInner_tl_in_a_bits_data_0 = auto_dmInner_tl_in_a_bits_data; // @[Debug.scala:1871:9]
wire auto_dmInner_tl_in_a_bits_corrupt_0 = auto_dmInner_tl_in_a_bits_corrupt; // @[Debug.scala:1871:9]
wire auto_dmInner_tl_in_d_ready_0 = auto_dmInner_tl_in_d_ready; // @[Debug.scala:1871:9]
wire io_debug_clock_0 = io_debug_clock; // @[Debug.scala:1871:9]
wire io_debug_reset_0 = io_debug_reset; // @[Debug.scala:1871:9]
wire io_tl_clock_0 = io_tl_clock; // @[Debug.scala:1871:9]
wire io_tl_reset_0 = io_tl_reset; // @[Debug.scala:1871:9]
wire io_dmactive_0 = io_dmactive; // @[Debug.scala:1871:9]
wire io_innerCtrl_mem_0_resumereq_0 = io_innerCtrl_mem_0_resumereq; // @[Debug.scala:1871:9]
wire [9:0] io_innerCtrl_mem_0_hartsel_0 = io_innerCtrl_mem_0_hartsel; // @[Debug.scala:1871:9]
wire io_innerCtrl_mem_0_ackhavereset_0 = io_innerCtrl_mem_0_ackhavereset; // @[Debug.scala:1871:9]
wire io_innerCtrl_mem_0_hrmask_0_0 = io_innerCtrl_mem_0_hrmask_0; // @[Debug.scala:1871:9]
wire io_innerCtrl_widx_0 = io_innerCtrl_widx; // @[Debug.scala:1871:9]
wire io_innerCtrl_safe_widx_valid_0 = io_innerCtrl_safe_widx_valid; // @[Debug.scala:1871:9]
wire io_innerCtrl_safe_source_reset_n_0 = io_innerCtrl_safe_source_reset_n; // @[Debug.scala:1871:9]
wire io_hartIsInReset_0_0 = io_hartIsInReset_0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_a_mem_0_source = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_a_mem_0_corrupt = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_b_mem_0_source = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_b_mem_0_corrupt = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_b_ridx = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_b_widx = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_b_safe_ridx_valid = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_b_safe_widx_valid = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_b_safe_source_reset_n = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_b_safe_sink_reset_n = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_c_mem_0_source = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_c_mem_0_corrupt = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_c_ridx = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_c_widx = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_c_safe_ridx_valid = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_c_safe_widx_valid = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_c_safe_source_reset_n = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_c_safe_sink_reset_n = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_d_mem_0_sink = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_d_mem_0_denied = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_d_mem_0_corrupt = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_e_mem_0_sink = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_e_ridx = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_e_widx = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_e_safe_ridx_valid = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_e_safe_widx_valid = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_e_safe_source_reset_n = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_e_safe_sink_reset_n = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmInner_sb2tlOpt_out_a_bits_source = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmInner_sb2tlOpt_out_a_bits_corrupt = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmInner_sb2tlOpt_out_d_bits_source = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmInner_custom_in_addr = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmInner_custom_in_ready = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmInner_custom_in_valid = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmInner_tl_in_d_bits_sink = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmInner_tl_in_d_bits_denied = 1'h0; // @[Debug.scala:1871:9]
wire auto_dmInner_tl_in_d_bits_corrupt = 1'h0; // @[Debug.scala:1871:9]
wire io_innerCtrl_mem_0_hasel = 1'h0; // @[Debug.scala:1871:9]
wire io_innerCtrl_mem_0_hamask_0 = 1'h0; // @[Debug.scala:1871:9]
wire io_debugUnavail_0 = 1'h0; // @[Debug.scala:1871:9]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire auto_dmInner_sb2tlOpt_out_a_bits_mask = 1'h1; // @[AsyncQueue.scala:211:22]
wire [31:0] auto_dmiXing_in_b_mem_0_data = 32'h0; // @[Debug.scala:1858:27, :1871:9]
wire [31:0] auto_dmiXing_in_c_mem_0_data = 32'h0; // @[Debug.scala:1858:27, :1871:9]
wire [3:0] auto_dmiXing_in_b_mem_0_mask = 4'h0; // @[Debug.scala:1858:27, :1871:9]
wire [8:0] auto_dmiXing_in_b_mem_0_address = 9'h0; // @[Debug.scala:1858:27, :1871:9]
wire [8:0] auto_dmiXing_in_c_mem_0_address = 9'h0; // @[Debug.scala:1858:27, :1871:9]
wire [1:0] auto_dmiXing_in_b_mem_0_param = 2'h0; // @[Debug.scala:1871:9]
wire [1:0] auto_dmiXing_in_b_mem_0_size = 2'h0; // @[Debug.scala:1871:9]
wire [1:0] auto_dmiXing_in_c_mem_0_size = 2'h0; // @[Debug.scala:1871:9]
wire [1:0] auto_dmiXing_in_d_mem_0_param = 2'h0; // @[Debug.scala:1871:9]
wire [1:0] auto_dmInner_tl_in_d_bits_param = 2'h0; // @[Debug.scala:1871:9]
wire [3:0] auto_dmiXing_in_a_mem_0_mask = 4'hF; // @[Debug.scala:1858:27, :1871:9]
wire [1:0] auto_dmiXing_in_a_mem_0_size = 2'h2; // @[Debug.scala:1858:27, :1871:9]
wire [2:0] auto_dmiXing_in_a_mem_0_param = 3'h0; // @[Debug.scala:1871:9]
wire [2:0] auto_dmiXing_in_b_mem_0_opcode = 3'h0; // @[Debug.scala:1871:9]
wire [2:0] auto_dmiXing_in_c_mem_0_opcode = 3'h0; // @[Debug.scala:1871:9]
wire [2:0] auto_dmiXing_in_c_mem_0_param = 3'h0; // @[Debug.scala:1871:9]
wire [2:0] auto_dmInner_sb2tlOpt_out_a_bits_param = 3'h0; // @[Debug.scala:1871:9]
wire childClock = io_debug_clock_0; // @[Debug.scala:1871:9]
wire childReset = io_debug_reset_0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_a_safe_ridx_valid_0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_a_safe_sink_reset_n_0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_a_ridx_0; // @[Debug.scala:1871:9]
wire [2:0] auto_dmiXing_in_d_mem_0_opcode_0; // @[Debug.scala:1871:9]
wire [1:0] auto_dmiXing_in_d_mem_0_size_0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_d_mem_0_source_0; // @[Debug.scala:1871:9]
wire [31:0] auto_dmiXing_in_d_mem_0_data_0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_d_safe_widx_valid_0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_d_safe_source_reset_n_0; // @[Debug.scala:1871:9]
wire auto_dmiXing_in_d_widx_0; // @[Debug.scala:1871:9]
wire [2:0] auto_dmInner_sb2tlOpt_out_a_bits_opcode_0; // @[Debug.scala:1871:9]
wire [3:0] auto_dmInner_sb2tlOpt_out_a_bits_size_0; // @[Debug.scala:1871:9]
wire [31:0] auto_dmInner_sb2tlOpt_out_a_bits_address_0; // @[Debug.scala:1871:9]
wire [7:0] auto_dmInner_sb2tlOpt_out_a_bits_data_0; // @[Debug.scala:1871:9]
wire auto_dmInner_sb2tlOpt_out_a_valid_0; // @[Debug.scala:1871:9]
wire auto_dmInner_sb2tlOpt_out_d_ready_0; // @[Debug.scala:1871:9]
wire auto_dmInner_tl_in_a_ready_0; // @[Debug.scala:1871:9]
wire [2:0] auto_dmInner_tl_in_d_bits_opcode_0; // @[Debug.scala:1871:9]
wire [1:0] auto_dmInner_tl_in_d_bits_size_0; // @[Debug.scala:1871:9]
wire [11:0] auto_dmInner_tl_in_d_bits_source_0; // @[Debug.scala:1871:9]
wire [63:0] auto_dmInner_tl_in_d_bits_data_0; // @[Debug.scala:1871:9]
wire auto_dmInner_tl_in_d_valid_0; // @[Debug.scala:1871:9]
wire io_innerCtrl_safe_ridx_valid_0; // @[Debug.scala:1871:9]
wire io_innerCtrl_safe_sink_reset_n_0; // @[Debug.scala:1871:9]
wire io_innerCtrl_ridx_0; // @[Debug.scala:1871:9]
wire io_hgDebugInt_0_0; // @[Debug.scala:1871:9]
wire dmactive_synced; // @[ShiftReg.scala:48:24]
TLDebugModuleInner dmInner ( // @[Debug.scala:1857:27]
.clock (io_debug_clock_0), // @[Debug.scala:1871:9]
.reset (io_debug_reset_0), // @[Debug.scala:1871:9]
.auto_sb2tlOpt_out_a_ready (auto_dmInner_sb2tlOpt_out_a_ready_0), // @[Debug.scala:1871:9]
.auto_sb2tlOpt_out_a_valid (auto_dmInner_sb2tlOpt_out_a_valid_0),
.auto_sb2tlOpt_out_a_bits_opcode (auto_dmInner_sb2tlOpt_out_a_bits_opcode_0),
.auto_sb2tlOpt_out_a_bits_size (auto_dmInner_sb2tlOpt_out_a_bits_size_0),
.auto_sb2tlOpt_out_a_bits_address (auto_dmInner_sb2tlOpt_out_a_bits_address_0),
.auto_sb2tlOpt_out_a_bits_data (auto_dmInner_sb2tlOpt_out_a_bits_data_0),
.auto_sb2tlOpt_out_d_ready (auto_dmInner_sb2tlOpt_out_d_ready_0),
.auto_sb2tlOpt_out_d_valid (auto_dmInner_sb2tlOpt_out_d_valid_0), // @[Debug.scala:1871:9]
.auto_sb2tlOpt_out_d_bits_opcode (auto_dmInner_sb2tlOpt_out_d_bits_opcode_0), // @[Debug.scala:1871:9]
.auto_sb2tlOpt_out_d_bits_param (auto_dmInner_sb2tlOpt_out_d_bits_param_0), // @[Debug.scala:1871:9]
.auto_sb2tlOpt_out_d_bits_size (auto_dmInner_sb2tlOpt_out_d_bits_size_0), // @[Debug.scala:1871:9]
.auto_sb2tlOpt_out_d_bits_sink (auto_dmInner_sb2tlOpt_out_d_bits_sink_0), // @[Debug.scala:1871:9]
.auto_sb2tlOpt_out_d_bits_denied (auto_dmInner_sb2tlOpt_out_d_bits_denied_0), // @[Debug.scala:1871:9]
.auto_sb2tlOpt_out_d_bits_data (auto_dmInner_sb2tlOpt_out_d_bits_data_0), // @[Debug.scala:1871:9]
.auto_sb2tlOpt_out_d_bits_corrupt (auto_dmInner_sb2tlOpt_out_d_bits_corrupt_0), // @[Debug.scala:1871:9]
.auto_tl_in_a_ready (auto_dmInner_tl_in_a_ready_0),
.auto_tl_in_a_valid (auto_dmInner_tl_in_a_valid_0), // @[Debug.scala:1871:9]
.auto_tl_in_a_bits_opcode (auto_dmInner_tl_in_a_bits_opcode_0), // @[Debug.scala:1871:9]
.auto_tl_in_a_bits_param (auto_dmInner_tl_in_a_bits_param_0), // @[Debug.scala:1871:9]
.auto_tl_in_a_bits_size (auto_dmInner_tl_in_a_bits_size_0), // @[Debug.scala:1871:9]
.auto_tl_in_a_bits_source (auto_dmInner_tl_in_a_bits_source_0), // @[Debug.scala:1871:9]
.auto_tl_in_a_bits_address (auto_dmInner_tl_in_a_bits_address_0), // @[Debug.scala:1871:9]
.auto_tl_in_a_bits_mask (auto_dmInner_tl_in_a_bits_mask_0), // @[Debug.scala:1871:9]
.auto_tl_in_a_bits_data (auto_dmInner_tl_in_a_bits_data_0), // @[Debug.scala:1871:9]
.auto_tl_in_a_bits_corrupt (auto_dmInner_tl_in_a_bits_corrupt_0), // @[Debug.scala:1871:9]
.auto_tl_in_d_ready (auto_dmInner_tl_in_d_ready_0), // @[Debug.scala:1871:9]
.auto_tl_in_d_valid (auto_dmInner_tl_in_d_valid_0),
.auto_tl_in_d_bits_opcode (auto_dmInner_tl_in_d_bits_opcode_0),
.auto_tl_in_d_bits_size (auto_dmInner_tl_in_d_bits_size_0),
.auto_tl_in_d_bits_source (auto_dmInner_tl_in_d_bits_source_0),
.auto_tl_in_d_bits_data (auto_dmInner_tl_in_d_bits_data_0),
.auto_dmi_in_a_ready (_dmInner_auto_dmi_in_a_ready),
.auto_dmi_in_a_valid (_dmiXing_auto_out_a_valid), // @[Debug.scala:1858:27]
.auto_dmi_in_a_bits_opcode (_dmiXing_auto_out_a_bits_opcode), // @[Debug.scala:1858:27]
.auto_dmi_in_a_bits_param (_dmiXing_auto_out_a_bits_param), // @[Debug.scala:1858:27]
.auto_dmi_in_a_bits_size (_dmiXing_auto_out_a_bits_size), // @[Debug.scala:1858:27]
.auto_dmi_in_a_bits_source (_dmiXing_auto_out_a_bits_source), // @[Debug.scala:1858:27]
.auto_dmi_in_a_bits_address (_dmiXing_auto_out_a_bits_address), // @[Debug.scala:1858:27]
.auto_dmi_in_a_bits_mask (_dmiXing_auto_out_a_bits_mask), // @[Debug.scala:1858:27]
.auto_dmi_in_a_bits_data (_dmiXing_auto_out_a_bits_data), // @[Debug.scala:1858:27]
.auto_dmi_in_a_bits_corrupt (_dmiXing_auto_out_a_bits_corrupt), // @[Debug.scala:1858:27]
.auto_dmi_in_d_ready (_dmiXing_auto_out_d_ready), // @[Debug.scala:1858:27]
.auto_dmi_in_d_valid (_dmInner_auto_dmi_in_d_valid),
.auto_dmi_in_d_bits_opcode (_dmInner_auto_dmi_in_d_bits_opcode),
.auto_dmi_in_d_bits_size (_dmInner_auto_dmi_in_d_bits_size),
.auto_dmi_in_d_bits_source (_dmInner_auto_dmi_in_d_bits_source),
.auto_dmi_in_d_bits_data (_dmInner_auto_dmi_in_d_bits_data),
.io_dmactive (dmactive_synced), // @[ShiftReg.scala:48:24]
.io_innerCtrl_valid (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_valid), // @[AsyncQueue.scala:211:22]
.io_innerCtrl_bits_resumereq (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_resumereq), // @[AsyncQueue.scala:211:22]
.io_innerCtrl_bits_hartsel (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hartsel), // @[AsyncQueue.scala:211:22]
.io_innerCtrl_bits_ackhavereset (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_ackhavereset), // @[AsyncQueue.scala:211:22]
.io_innerCtrl_bits_hasel (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hasel), // @[AsyncQueue.scala:211:22]
.io_innerCtrl_bits_hamask_0 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_0), // @[AsyncQueue.scala:211:22]
.io_innerCtrl_bits_hrmask_0 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_0), // @[AsyncQueue.scala:211:22]
.io_hgDebugInt_0 (io_hgDebugInt_0_0),
.io_hartIsInReset_0 (io_hartIsInReset_0_0), // @[Debug.scala:1871:9]
.io_tl_clock (io_tl_clock_0), // @[Debug.scala:1871:9]
.io_tl_reset (io_tl_reset_0) // @[Debug.scala:1871:9]
); // @[Debug.scala:1857:27]
TLAsyncCrossingSink_a9d32s1k1z2u dmiXing ( // @[Debug.scala:1858:27]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_in_a_mem_0_opcode (auto_dmiXing_in_a_mem_0_opcode_0), // @[Debug.scala:1871:9]
.auto_in_a_mem_0_address (auto_dmiXing_in_a_mem_0_address_0), // @[Debug.scala:1871:9]
.auto_in_a_mem_0_data (auto_dmiXing_in_a_mem_0_data_0), // @[Debug.scala:1871:9]
.auto_in_a_ridx (auto_dmiXing_in_a_ridx_0),
.auto_in_a_widx (auto_dmiXing_in_a_widx_0), // @[Debug.scala:1871:9]
.auto_in_a_safe_ridx_valid (auto_dmiXing_in_a_safe_ridx_valid_0),
.auto_in_a_safe_widx_valid (auto_dmiXing_in_a_safe_widx_valid_0), // @[Debug.scala:1871:9]
.auto_in_a_safe_source_reset_n (auto_dmiXing_in_a_safe_source_reset_n_0), // @[Debug.scala:1871:9]
.auto_in_a_safe_sink_reset_n (auto_dmiXing_in_a_safe_sink_reset_n_0),
.auto_in_d_mem_0_opcode (auto_dmiXing_in_d_mem_0_opcode_0),
.auto_in_d_mem_0_size (auto_dmiXing_in_d_mem_0_size_0),
.auto_in_d_mem_0_source (auto_dmiXing_in_d_mem_0_source_0),
.auto_in_d_mem_0_data (auto_dmiXing_in_d_mem_0_data_0),
.auto_in_d_ridx (auto_dmiXing_in_d_ridx_0), // @[Debug.scala:1871:9]
.auto_in_d_widx (auto_dmiXing_in_d_widx_0),
.auto_in_d_safe_ridx_valid (auto_dmiXing_in_d_safe_ridx_valid_0), // @[Debug.scala:1871:9]
.auto_in_d_safe_widx_valid (auto_dmiXing_in_d_safe_widx_valid_0),
.auto_in_d_safe_source_reset_n (auto_dmiXing_in_d_safe_source_reset_n_0),
.auto_in_d_safe_sink_reset_n (auto_dmiXing_in_d_safe_sink_reset_n_0), // @[Debug.scala:1871:9]
.auto_out_a_ready (_dmInner_auto_dmi_in_a_ready), // @[Debug.scala:1857:27]
.auto_out_a_valid (_dmiXing_auto_out_a_valid),
.auto_out_a_bits_opcode (_dmiXing_auto_out_a_bits_opcode),
.auto_out_a_bits_param (_dmiXing_auto_out_a_bits_param),
.auto_out_a_bits_size (_dmiXing_auto_out_a_bits_size),
.auto_out_a_bits_source (_dmiXing_auto_out_a_bits_source),
.auto_out_a_bits_address (_dmiXing_auto_out_a_bits_address),
.auto_out_a_bits_mask (_dmiXing_auto_out_a_bits_mask),
.auto_out_a_bits_data (_dmiXing_auto_out_a_bits_data),
.auto_out_a_bits_corrupt (_dmiXing_auto_out_a_bits_corrupt),
.auto_out_d_ready (_dmiXing_auto_out_d_ready),
.auto_out_d_valid (_dmInner_auto_dmi_in_d_valid), // @[Debug.scala:1857:27]
.auto_out_d_bits_opcode (_dmInner_auto_dmi_in_d_bits_opcode), // @[Debug.scala:1857:27]
.auto_out_d_bits_size (_dmInner_auto_dmi_in_d_bits_size), // @[Debug.scala:1857:27]
.auto_out_d_bits_source (_dmInner_auto_dmi_in_d_bits_source), // @[Debug.scala:1857:27]
.auto_out_d_bits_data (_dmInner_auto_dmi_in_d_bits_data) // @[Debug.scala:1857:27]
); // @[Debug.scala:1858:27]
AsyncResetSynchronizerShiftReg_w1_d3_i0_27 dmactive_synced_dmactive_synced_dmactiveSync ( // @[ShiftReg.scala:45:23]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.io_d (io_dmactive_0), // @[Debug.scala:1871:9]
.io_q (dmactive_synced)
); // @[ShiftReg.scala:45:23]
AsyncQueueSink_DebugInternalBundle dmactive_synced_dmInner_io_innerCtrl_sink ( // @[AsyncQueue.scala:211:22]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.io_deq_valid (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_valid),
.io_deq_bits_resumereq (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_resumereq),
.io_deq_bits_hartsel (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hartsel),
.io_deq_bits_ackhavereset (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_ackhavereset),
.io_deq_bits_hasel (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hasel),
.io_deq_bits_hamask_0 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hamask_0),
.io_deq_bits_hrmask_0 (_dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_0),
.io_async_mem_0_resumereq (io_innerCtrl_mem_0_resumereq_0), // @[Debug.scala:1871:9]
.io_async_mem_0_hartsel (io_innerCtrl_mem_0_hartsel_0), // @[Debug.scala:1871:9]
.io_async_mem_0_ackhavereset (io_innerCtrl_mem_0_ackhavereset_0), // @[Debug.scala:1871:9]
.io_async_mem_0_hrmask_0 (io_innerCtrl_mem_0_hrmask_0_0), // @[Debug.scala:1871:9]
.io_async_ridx (io_innerCtrl_ridx_0),
.io_async_widx (io_innerCtrl_widx_0), // @[Debug.scala:1871:9]
.io_async_safe_ridx_valid (io_innerCtrl_safe_ridx_valid_0),
.io_async_safe_widx_valid (io_innerCtrl_safe_widx_valid_0), // @[Debug.scala:1871:9]
.io_async_safe_source_reset_n (io_innerCtrl_safe_source_reset_n_0), // @[Debug.scala:1871:9]
.io_async_safe_sink_reset_n (io_innerCtrl_safe_sink_reset_n_0)
); // @[AsyncQueue.scala:211:22]
assign auto_dmiXing_in_a_ridx = auto_dmiXing_in_a_ridx_0; // @[Debug.scala:1871:9]
assign auto_dmiXing_in_a_safe_ridx_valid = auto_dmiXing_in_a_safe_ridx_valid_0; // @[Debug.scala:1871:9]
assign auto_dmiXing_in_a_safe_sink_reset_n = auto_dmiXing_in_a_safe_sink_reset_n_0; // @[Debug.scala:1871:9]
assign auto_dmiXing_in_d_mem_0_opcode = auto_dmiXing_in_d_mem_0_opcode_0; // @[Debug.scala:1871:9]
assign auto_dmiXing_in_d_mem_0_size = auto_dmiXing_in_d_mem_0_size_0; // @[Debug.scala:1871:9]
assign auto_dmiXing_in_d_mem_0_source = auto_dmiXing_in_d_mem_0_source_0; // @[Debug.scala:1871:9]
assign auto_dmiXing_in_d_mem_0_data = auto_dmiXing_in_d_mem_0_data_0; // @[Debug.scala:1871:9]
assign auto_dmiXing_in_d_widx = auto_dmiXing_in_d_widx_0; // @[Debug.scala:1871:9]
assign auto_dmiXing_in_d_safe_widx_valid = auto_dmiXing_in_d_safe_widx_valid_0; // @[Debug.scala:1871:9]
assign auto_dmiXing_in_d_safe_source_reset_n = auto_dmiXing_in_d_safe_source_reset_n_0; // @[Debug.scala:1871:9]
assign auto_dmInner_sb2tlOpt_out_a_valid = auto_dmInner_sb2tlOpt_out_a_valid_0; // @[Debug.scala:1871:9]
assign auto_dmInner_sb2tlOpt_out_a_bits_opcode = auto_dmInner_sb2tlOpt_out_a_bits_opcode_0; // @[Debug.scala:1871:9]
assign auto_dmInner_sb2tlOpt_out_a_bits_size = auto_dmInner_sb2tlOpt_out_a_bits_size_0; // @[Debug.scala:1871:9]
assign auto_dmInner_sb2tlOpt_out_a_bits_address = auto_dmInner_sb2tlOpt_out_a_bits_address_0; // @[Debug.scala:1871:9]
assign auto_dmInner_sb2tlOpt_out_a_bits_data = auto_dmInner_sb2tlOpt_out_a_bits_data_0; // @[Debug.scala:1871:9]
assign auto_dmInner_sb2tlOpt_out_d_ready = auto_dmInner_sb2tlOpt_out_d_ready_0; // @[Debug.scala:1871:9]
assign auto_dmInner_tl_in_a_ready = auto_dmInner_tl_in_a_ready_0; // @[Debug.scala:1871:9]
assign auto_dmInner_tl_in_d_valid = auto_dmInner_tl_in_d_valid_0; // @[Debug.scala:1871:9]
assign auto_dmInner_tl_in_d_bits_opcode = auto_dmInner_tl_in_d_bits_opcode_0; // @[Debug.scala:1871:9]
assign auto_dmInner_tl_in_d_bits_size = auto_dmInner_tl_in_d_bits_size_0; // @[Debug.scala:1871:9]
assign auto_dmInner_tl_in_d_bits_source = auto_dmInner_tl_in_d_bits_source_0; // @[Debug.scala:1871:9]
assign auto_dmInner_tl_in_d_bits_data = auto_dmInner_tl_in_d_bits_data_0; // @[Debug.scala:1871:9]
assign io_innerCtrl_ridx = io_innerCtrl_ridx_0; // @[Debug.scala:1871:9]
assign io_innerCtrl_safe_ridx_valid = io_innerCtrl_safe_ridx_valid_0; // @[Debug.scala:1871:9]
assign io_innerCtrl_safe_sink_reset_n = io_innerCtrl_safe_sink_reset_n_0; // @[Debug.scala:1871:9]
assign io_hgDebugInt_0 = io_hgDebugInt_0_0; // @[Debug.scala:1871:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_28 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<6>(0h2f))
node _source_ok_T_30 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _source_ok_T_33 = eq(io.in.a.bits.source, UInt<6>(0h2b))
node _source_ok_T_34 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _source_ok_T_35 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _source_ok_T_36 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _source_ok_T_37 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _source_ok_T_38 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _source_ok_T_39 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE : UInt<1>[20]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_25
connect _source_ok_WIRE[6], _source_ok_T_26
connect _source_ok_WIRE[7], _source_ok_T_27
connect _source_ok_WIRE[8], _source_ok_T_28
connect _source_ok_WIRE[9], _source_ok_T_29
connect _source_ok_WIRE[10], _source_ok_T_30
connect _source_ok_WIRE[11], _source_ok_T_31
connect _source_ok_WIRE[12], _source_ok_T_32
connect _source_ok_WIRE[13], _source_ok_T_33
connect _source_ok_WIRE[14], _source_ok_T_34
connect _source_ok_WIRE[15], _source_ok_T_35
connect _source_ok_WIRE[16], _source_ok_T_36
connect _source_ok_WIRE[17], _source_ok_T_37
connect _source_ok_WIRE[18], _source_ok_T_38
connect _source_ok_WIRE[19], _source_ok_T_39
node _source_ok_T_40 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_41 = or(_source_ok_T_40, _source_ok_WIRE[2])
node _source_ok_T_42 = or(_source_ok_T_41, _source_ok_WIRE[3])
node _source_ok_T_43 = or(_source_ok_T_42, _source_ok_WIRE[4])
node _source_ok_T_44 = or(_source_ok_T_43, _source_ok_WIRE[5])
node _source_ok_T_45 = or(_source_ok_T_44, _source_ok_WIRE[6])
node _source_ok_T_46 = or(_source_ok_T_45, _source_ok_WIRE[7])
node _source_ok_T_47 = or(_source_ok_T_46, _source_ok_WIRE[8])
node _source_ok_T_48 = or(_source_ok_T_47, _source_ok_WIRE[9])
node _source_ok_T_49 = or(_source_ok_T_48, _source_ok_WIRE[10])
node _source_ok_T_50 = or(_source_ok_T_49, _source_ok_WIRE[11])
node _source_ok_T_51 = or(_source_ok_T_50, _source_ok_WIRE[12])
node _source_ok_T_52 = or(_source_ok_T_51, _source_ok_WIRE[13])
node _source_ok_T_53 = or(_source_ok_T_52, _source_ok_WIRE[14])
node _source_ok_T_54 = or(_source_ok_T_53, _source_ok_WIRE[15])
node _source_ok_T_55 = or(_source_ok_T_54, _source_ok_WIRE[16])
node _source_ok_T_56 = or(_source_ok_T_55, _source_ok_WIRE[17])
node _source_ok_T_57 = or(_source_ok_T_56, _source_ok_WIRE[18])
node source_ok = or(_source_ok_T_57, _source_ok_WIRE[19])
node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<1>(0h0))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<1>(0h1))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<2>(0h2))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<2>(0h3))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_67 = cvt(_T_66)
node _T_68 = and(_T_67, asSInt(UInt<1>(0h0)))
node _T_69 = asSInt(_T_68)
node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0)))
node _T_71 = or(_T_65, _T_70)
node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_73 = eq(_T_72, UInt<1>(0h0))
node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_75 = cvt(_T_74)
node _T_76 = and(_T_75, asSInt(UInt<1>(0h0)))
node _T_77 = asSInt(_T_76)
node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0)))
node _T_79 = or(_T_73, _T_78)
node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_81 = eq(_T_80, UInt<1>(0h0))
node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_83 = cvt(_T_82)
node _T_84 = and(_T_83, asSInt(UInt<1>(0h0)))
node _T_85 = asSInt(_T_84)
node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0)))
node _T_87 = or(_T_81, _T_86)
node _T_88 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_89 = eq(_T_88, UInt<1>(0h0))
node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_91 = cvt(_T_90)
node _T_92 = and(_T_91, asSInt(UInt<1>(0h0)))
node _T_93 = asSInt(_T_92)
node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0)))
node _T_95 = or(_T_89, _T_94)
node _T_96 = eq(io.in.a.bits.source, UInt<6>(0h2f))
node _T_97 = eq(_T_96, UInt<1>(0h0))
node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_99 = cvt(_T_98)
node _T_100 = and(_T_99, asSInt(UInt<1>(0h0)))
node _T_101 = asSInt(_T_100)
node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0)))
node _T_103 = or(_T_97, _T_102)
node _T_104 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_105 = eq(_T_104, UInt<1>(0h0))
node _T_106 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_107 = cvt(_T_106)
node _T_108 = and(_T_107, asSInt(UInt<1>(0h0)))
node _T_109 = asSInt(_T_108)
node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0)))
node _T_111 = or(_T_105, _T_110)
node _T_112 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_113 = eq(_T_112, UInt<1>(0h0))
node _T_114 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_115 = cvt(_T_114)
node _T_116 = and(_T_115, asSInt(UInt<1>(0h0)))
node _T_117 = asSInt(_T_116)
node _T_118 = eq(_T_117, asSInt(UInt<1>(0h0)))
node _T_119 = or(_T_113, _T_118)
node _T_120 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_121 = eq(_T_120, UInt<1>(0h0))
node _T_122 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_123 = cvt(_T_122)
node _T_124 = and(_T_123, asSInt(UInt<1>(0h0)))
node _T_125 = asSInt(_T_124)
node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0)))
node _T_127 = or(_T_121, _T_126)
node _T_128 = eq(io.in.a.bits.source, UInt<6>(0h2b))
node _T_129 = eq(_T_128, UInt<1>(0h0))
node _T_130 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_131 = cvt(_T_130)
node _T_132 = and(_T_131, asSInt(UInt<1>(0h0)))
node _T_133 = asSInt(_T_132)
node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0)))
node _T_135 = or(_T_129, _T_134)
node _T_136 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_137 = eq(_T_136, UInt<1>(0h0))
node _T_138 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_139 = cvt(_T_138)
node _T_140 = and(_T_139, asSInt(UInt<1>(0h0)))
node _T_141 = asSInt(_T_140)
node _T_142 = eq(_T_141, asSInt(UInt<1>(0h0)))
node _T_143 = or(_T_137, _T_142)
node _T_144 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_145 = eq(_T_144, UInt<1>(0h0))
node _T_146 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_147 = cvt(_T_146)
node _T_148 = and(_T_147, asSInt(UInt<1>(0h0)))
node _T_149 = asSInt(_T_148)
node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0)))
node _T_151 = or(_T_145, _T_150)
node _T_152 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_153 = eq(_T_152, UInt<1>(0h0))
node _T_154 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_155 = cvt(_T_154)
node _T_156 = and(_T_155, asSInt(UInt<1>(0h0)))
node _T_157 = asSInt(_T_156)
node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0)))
node _T_159 = or(_T_153, _T_158)
node _T_160 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_161 = eq(_T_160, UInt<1>(0h0))
node _T_162 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_163 = cvt(_T_162)
node _T_164 = and(_T_163, asSInt(UInt<1>(0h0)))
node _T_165 = asSInt(_T_164)
node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0)))
node _T_167 = or(_T_161, _T_166)
node _T_168 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_169 = eq(_T_168, UInt<1>(0h0))
node _T_170 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_171 = cvt(_T_170)
node _T_172 = and(_T_171, asSInt(UInt<1>(0h0)))
node _T_173 = asSInt(_T_172)
node _T_174 = eq(_T_173, asSInt(UInt<1>(0h0)))
node _T_175 = or(_T_169, _T_174)
node _T_176 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_177 = eq(_T_176, UInt<1>(0h0))
node _T_178 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_179 = cvt(_T_178)
node _T_180 = and(_T_179, asSInt(UInt<1>(0h0)))
node _T_181 = asSInt(_T_180)
node _T_182 = eq(_T_181, asSInt(UInt<1>(0h0)))
node _T_183 = or(_T_177, _T_182)
node _T_184 = and(_T_11, _T_24)
node _T_185 = and(_T_184, _T_37)
node _T_186 = and(_T_185, _T_50)
node _T_187 = and(_T_186, _T_63)
node _T_188 = and(_T_187, _T_71)
node _T_189 = and(_T_188, _T_79)
node _T_190 = and(_T_189, _T_87)
node _T_191 = and(_T_190, _T_95)
node _T_192 = and(_T_191, _T_103)
node _T_193 = and(_T_192, _T_111)
node _T_194 = and(_T_193, _T_119)
node _T_195 = and(_T_194, _T_127)
node _T_196 = and(_T_195, _T_135)
node _T_197 = and(_T_196, _T_143)
node _T_198 = and(_T_197, _T_151)
node _T_199 = and(_T_198, _T_159)
node _T_200 = and(_T_199, _T_167)
node _T_201 = and(_T_200, _T_175)
node _T_202 = and(_T_201, _T_183)
node _T_203 = asUInt(reset)
node _T_204 = eq(_T_203, UInt<1>(0h0))
when _T_204 :
node _T_205 = eq(_T_202, UInt<1>(0h0))
when _T_205 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_202, UInt<1>(0h1), "") : assert_1
node _T_206 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_206 :
node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_208 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_209 = and(_T_207, _T_208)
node _T_210 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0)
node _T_211 = shr(io.in.a.bits.source, 2)
node _T_212 = eq(_T_211, UInt<1>(0h0))
node _T_213 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_214 = and(_T_212, _T_213)
node _T_215 = leq(uncommonBits_4, UInt<2>(0h3))
node _T_216 = and(_T_214, _T_215)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0)
node _T_217 = shr(io.in.a.bits.source, 2)
node _T_218 = eq(_T_217, UInt<1>(0h1))
node _T_219 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_220 = and(_T_218, _T_219)
node _T_221 = leq(uncommonBits_5, UInt<2>(0h3))
node _T_222 = and(_T_220, _T_221)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_223 = shr(io.in.a.bits.source, 2)
node _T_224 = eq(_T_223, UInt<2>(0h2))
node _T_225 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_226 = and(_T_224, _T_225)
node _T_227 = leq(uncommonBits_6, UInt<2>(0h3))
node _T_228 = and(_T_226, _T_227)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_229 = shr(io.in.a.bits.source, 2)
node _T_230 = eq(_T_229, UInt<2>(0h3))
node _T_231 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_232 = and(_T_230, _T_231)
node _T_233 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_234 = and(_T_232, _T_233)
node _T_235 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_236 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_237 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_238 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_239 = eq(io.in.a.bits.source, UInt<6>(0h2f))
node _T_240 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_241 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_242 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_243 = eq(io.in.a.bits.source, UInt<6>(0h2b))
node _T_244 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_245 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_246 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_247 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_248 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_249 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_250 = or(_T_210, _T_216)
node _T_251 = or(_T_250, _T_222)
node _T_252 = or(_T_251, _T_228)
node _T_253 = or(_T_252, _T_234)
node _T_254 = or(_T_253, _T_235)
node _T_255 = or(_T_254, _T_236)
node _T_256 = or(_T_255, _T_237)
node _T_257 = or(_T_256, _T_238)
node _T_258 = or(_T_257, _T_239)
node _T_259 = or(_T_258, _T_240)
node _T_260 = or(_T_259, _T_241)
node _T_261 = or(_T_260, _T_242)
node _T_262 = or(_T_261, _T_243)
node _T_263 = or(_T_262, _T_244)
node _T_264 = or(_T_263, _T_245)
node _T_265 = or(_T_264, _T_246)
node _T_266 = or(_T_265, _T_247)
node _T_267 = or(_T_266, _T_248)
node _T_268 = or(_T_267, _T_249)
node _T_269 = and(_T_209, _T_268)
node _T_270 = or(UInt<1>(0h0), _T_269)
node _T_271 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_272 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_273 = cvt(_T_272)
node _T_274 = and(_T_273, asSInt(UInt<14>(0h2000)))
node _T_275 = asSInt(_T_274)
node _T_276 = eq(_T_275, asSInt(UInt<1>(0h0)))
node _T_277 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_278 = cvt(_T_277)
node _T_279 = and(_T_278, asSInt(UInt<13>(0h1000)))
node _T_280 = asSInt(_T_279)
node _T_281 = eq(_T_280, asSInt(UInt<1>(0h0)))
node _T_282 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_283 = cvt(_T_282)
node _T_284 = and(_T_283, asSInt(UInt<17>(0h10000)))
node _T_285 = asSInt(_T_284)
node _T_286 = eq(_T_285, asSInt(UInt<1>(0h0)))
node _T_287 = xor(io.in.a.bits.address, UInt<18>(0h20000))
node _T_288 = cvt(_T_287)
node _T_289 = and(_T_288, asSInt(UInt<15>(0h4000)))
node _T_290 = asSInt(_T_289)
node _T_291 = eq(_T_290, asSInt(UInt<1>(0h0)))
node _T_292 = xor(io.in.a.bits.address, UInt<18>(0h24000))
node _T_293 = cvt(_T_292)
node _T_294 = and(_T_293, asSInt(UInt<13>(0h1000)))
node _T_295 = asSInt(_T_294)
node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0)))
node _T_297 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_298 = cvt(_T_297)
node _T_299 = and(_T_298, asSInt(UInt<18>(0h2f000)))
node _T_300 = asSInt(_T_299)
node _T_301 = eq(_T_300, asSInt(UInt<1>(0h0)))
node _T_302 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_303 = cvt(_T_302)
node _T_304 = and(_T_303, asSInt(UInt<17>(0h10000)))
node _T_305 = asSInt(_T_304)
node _T_306 = eq(_T_305, asSInt(UInt<1>(0h0)))
node _T_307 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_308 = cvt(_T_307)
node _T_309 = and(_T_308, asSInt(UInt<13>(0h1000)))
node _T_310 = asSInt(_T_309)
node _T_311 = eq(_T_310, asSInt(UInt<1>(0h0)))
node _T_312 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_313 = cvt(_T_312)
node _T_314 = and(_T_313, asSInt(UInt<27>(0h4000000)))
node _T_315 = asSInt(_T_314)
node _T_316 = eq(_T_315, asSInt(UInt<1>(0h0)))
node _T_317 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_318 = cvt(_T_317)
node _T_319 = and(_T_318, asSInt(UInt<13>(0h1000)))
node _T_320 = asSInt(_T_319)
node _T_321 = eq(_T_320, asSInt(UInt<1>(0h0)))
node _T_322 = or(_T_276, _T_281)
node _T_323 = or(_T_322, _T_286)
node _T_324 = or(_T_323, _T_291)
node _T_325 = or(_T_324, _T_296)
node _T_326 = or(_T_325, _T_301)
node _T_327 = or(_T_326, _T_306)
node _T_328 = or(_T_327, _T_311)
node _T_329 = or(_T_328, _T_316)
node _T_330 = or(_T_329, _T_321)
node _T_331 = and(_T_271, _T_330)
node _T_332 = or(UInt<1>(0h0), _T_331)
node _T_333 = and(_T_270, _T_332)
node _T_334 = asUInt(reset)
node _T_335 = eq(_T_334, UInt<1>(0h0))
when _T_335 :
node _T_336 = eq(_T_333, UInt<1>(0h0))
when _T_336 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_333, UInt<1>(0h1), "") : assert_2
node _T_337 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_338 = shr(io.in.a.bits.source, 2)
node _T_339 = eq(_T_338, UInt<1>(0h0))
node _T_340 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_341 = and(_T_339, _T_340)
node _T_342 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_343 = and(_T_341, _T_342)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_344 = shr(io.in.a.bits.source, 2)
node _T_345 = eq(_T_344, UInt<1>(0h1))
node _T_346 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_347 = and(_T_345, _T_346)
node _T_348 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_349 = and(_T_347, _T_348)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0)
node _T_350 = shr(io.in.a.bits.source, 2)
node _T_351 = eq(_T_350, UInt<2>(0h2))
node _T_352 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_353 = and(_T_351, _T_352)
node _T_354 = leq(uncommonBits_10, UInt<2>(0h3))
node _T_355 = and(_T_353, _T_354)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0)
node _T_356 = shr(io.in.a.bits.source, 2)
node _T_357 = eq(_T_356, UInt<2>(0h3))
node _T_358 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_359 = and(_T_357, _T_358)
node _T_360 = leq(uncommonBits_11, UInt<2>(0h3))
node _T_361 = and(_T_359, _T_360)
node _T_362 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_363 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_364 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_365 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_366 = eq(io.in.a.bits.source, UInt<6>(0h2f))
node _T_367 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_368 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_369 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_370 = eq(io.in.a.bits.source, UInt<6>(0h2b))
node _T_371 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_372 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_373 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_374 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_375 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_376 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _WIRE : UInt<1>[20]
connect _WIRE[0], _T_337
connect _WIRE[1], _T_343
connect _WIRE[2], _T_349
connect _WIRE[3], _T_355
connect _WIRE[4], _T_361
connect _WIRE[5], _T_362
connect _WIRE[6], _T_363
connect _WIRE[7], _T_364
connect _WIRE[8], _T_365
connect _WIRE[9], _T_366
connect _WIRE[10], _T_367
connect _WIRE[11], _T_368
connect _WIRE[12], _T_369
connect _WIRE[13], _T_370
connect _WIRE[14], _T_371
connect _WIRE[15], _T_372
connect _WIRE[16], _T_373
connect _WIRE[17], _T_374
connect _WIRE[18], _T_375
connect _WIRE[19], _T_376
node _T_377 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_378 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_379 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_380 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_381 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_382 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_383 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_384 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_385 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_386 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_387 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_388 = mux(_WIRE[5], _T_377, UInt<1>(0h0))
node _T_389 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_390 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_391 = mux(_WIRE[8], _T_378, UInt<1>(0h0))
node _T_392 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_393 = mux(_WIRE[10], _T_379, UInt<1>(0h0))
node _T_394 = mux(_WIRE[11], UInt<1>(0h0), UInt<1>(0h0))
node _T_395 = mux(_WIRE[12], _T_380, UInt<1>(0h0))
node _T_396 = mux(_WIRE[13], UInt<1>(0h0), UInt<1>(0h0))
node _T_397 = mux(_WIRE[14], _T_381, UInt<1>(0h0))
node _T_398 = mux(_WIRE[15], UInt<1>(0h0), UInt<1>(0h0))
node _T_399 = mux(_WIRE[16], UInt<1>(0h0), UInt<1>(0h0))
node _T_400 = mux(_WIRE[17], _T_382, UInt<1>(0h0))
node _T_401 = mux(_WIRE[18], UInt<1>(0h0), UInt<1>(0h0))
node _T_402 = mux(_WIRE[19], UInt<1>(0h0), UInt<1>(0h0))
node _T_403 = or(_T_383, _T_384)
node _T_404 = or(_T_403, _T_385)
node _T_405 = or(_T_404, _T_386)
node _T_406 = or(_T_405, _T_387)
node _T_407 = or(_T_406, _T_388)
node _T_408 = or(_T_407, _T_389)
node _T_409 = or(_T_408, _T_390)
node _T_410 = or(_T_409, _T_391)
node _T_411 = or(_T_410, _T_392)
node _T_412 = or(_T_411, _T_393)
node _T_413 = or(_T_412, _T_394)
node _T_414 = or(_T_413, _T_395)
node _T_415 = or(_T_414, _T_396)
node _T_416 = or(_T_415, _T_397)
node _T_417 = or(_T_416, _T_398)
node _T_418 = or(_T_417, _T_399)
node _T_419 = or(_T_418, _T_400)
node _T_420 = or(_T_419, _T_401)
node _T_421 = or(_T_420, _T_402)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_421
node _T_422 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_423 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_424 = and(_T_422, _T_423)
node _T_425 = or(UInt<1>(0h0), _T_424)
node _T_426 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_427 = cvt(_T_426)
node _T_428 = and(_T_427, asSInt(UInt<14>(0h2000)))
node _T_429 = asSInt(_T_428)
node _T_430 = eq(_T_429, asSInt(UInt<1>(0h0)))
node _T_431 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_432 = cvt(_T_431)
node _T_433 = and(_T_432, asSInt(UInt<13>(0h1000)))
node _T_434 = asSInt(_T_433)
node _T_435 = eq(_T_434, asSInt(UInt<1>(0h0)))
node _T_436 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_437 = cvt(_T_436)
node _T_438 = and(_T_437, asSInt(UInt<17>(0h10000)))
node _T_439 = asSInt(_T_438)
node _T_440 = eq(_T_439, asSInt(UInt<1>(0h0)))
node _T_441 = xor(io.in.a.bits.address, UInt<18>(0h20000))
node _T_442 = cvt(_T_441)
node _T_443 = and(_T_442, asSInt(UInt<15>(0h4000)))
node _T_444 = asSInt(_T_443)
node _T_445 = eq(_T_444, asSInt(UInt<1>(0h0)))
node _T_446 = xor(io.in.a.bits.address, UInt<18>(0h24000))
node _T_447 = cvt(_T_446)
node _T_448 = and(_T_447, asSInt(UInt<13>(0h1000)))
node _T_449 = asSInt(_T_448)
node _T_450 = eq(_T_449, asSInt(UInt<1>(0h0)))
node _T_451 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_452 = cvt(_T_451)
node _T_453 = and(_T_452, asSInt(UInt<18>(0h2f000)))
node _T_454 = asSInt(_T_453)
node _T_455 = eq(_T_454, asSInt(UInt<1>(0h0)))
node _T_456 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_457 = cvt(_T_456)
node _T_458 = and(_T_457, asSInt(UInt<17>(0h10000)))
node _T_459 = asSInt(_T_458)
node _T_460 = eq(_T_459, asSInt(UInt<1>(0h0)))
node _T_461 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_462 = cvt(_T_461)
node _T_463 = and(_T_462, asSInt(UInt<13>(0h1000)))
node _T_464 = asSInt(_T_463)
node _T_465 = eq(_T_464, asSInt(UInt<1>(0h0)))
node _T_466 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_467 = cvt(_T_466)
node _T_468 = and(_T_467, asSInt(UInt<27>(0h4000000)))
node _T_469 = asSInt(_T_468)
node _T_470 = eq(_T_469, asSInt(UInt<1>(0h0)))
node _T_471 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_472 = cvt(_T_471)
node _T_473 = and(_T_472, asSInt(UInt<13>(0h1000)))
node _T_474 = asSInt(_T_473)
node _T_475 = eq(_T_474, asSInt(UInt<1>(0h0)))
node _T_476 = or(_T_430, _T_435)
node _T_477 = or(_T_476, _T_440)
node _T_478 = or(_T_477, _T_445)
node _T_479 = or(_T_478, _T_450)
node _T_480 = or(_T_479, _T_455)
node _T_481 = or(_T_480, _T_460)
node _T_482 = or(_T_481, _T_465)
node _T_483 = or(_T_482, _T_470)
node _T_484 = or(_T_483, _T_475)
node _T_485 = and(_T_425, _T_484)
node _T_486 = or(UInt<1>(0h0), _T_485)
node _T_487 = and(_WIRE_1, _T_486)
node _T_488 = asUInt(reset)
node _T_489 = eq(_T_488, UInt<1>(0h0))
when _T_489 :
node _T_490 = eq(_T_487, UInt<1>(0h0))
when _T_490 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_487, UInt<1>(0h1), "") : assert_3
node _T_491 = asUInt(reset)
node _T_492 = eq(_T_491, UInt<1>(0h0))
when _T_492 :
node _T_493 = eq(source_ok, UInt<1>(0h0))
when _T_493 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_494 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_495 = asUInt(reset)
node _T_496 = eq(_T_495, UInt<1>(0h0))
when _T_496 :
node _T_497 = eq(_T_494, UInt<1>(0h0))
when _T_497 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_494, UInt<1>(0h1), "") : assert_5
node _T_498 = asUInt(reset)
node _T_499 = eq(_T_498, UInt<1>(0h0))
when _T_499 :
node _T_500 = eq(is_aligned, UInt<1>(0h0))
when _T_500 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_501 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_502 = asUInt(reset)
node _T_503 = eq(_T_502, UInt<1>(0h0))
when _T_503 :
node _T_504 = eq(_T_501, UInt<1>(0h0))
when _T_504 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_501, UInt<1>(0h1), "") : assert_7
node _T_505 = not(io.in.a.bits.mask)
node _T_506 = eq(_T_505, UInt<1>(0h0))
node _T_507 = asUInt(reset)
node _T_508 = eq(_T_507, UInt<1>(0h0))
when _T_508 :
node _T_509 = eq(_T_506, UInt<1>(0h0))
when _T_509 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_506, UInt<1>(0h1), "") : assert_8
node _T_510 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_511 = asUInt(reset)
node _T_512 = eq(_T_511, UInt<1>(0h0))
when _T_512 :
node _T_513 = eq(_T_510, UInt<1>(0h0))
when _T_513 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_510, UInt<1>(0h1), "") : assert_9
node _T_514 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_514 :
node _T_515 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_516 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_517 = and(_T_515, _T_516)
node _T_518 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_519 = shr(io.in.a.bits.source, 2)
node _T_520 = eq(_T_519, UInt<1>(0h0))
node _T_521 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_522 = and(_T_520, _T_521)
node _T_523 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_524 = and(_T_522, _T_523)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_525 = shr(io.in.a.bits.source, 2)
node _T_526 = eq(_T_525, UInt<1>(0h1))
node _T_527 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_528 = and(_T_526, _T_527)
node _T_529 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_530 = and(_T_528, _T_529)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_531 = shr(io.in.a.bits.source, 2)
node _T_532 = eq(_T_531, UInt<2>(0h2))
node _T_533 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_534 = and(_T_532, _T_533)
node _T_535 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_536 = and(_T_534, _T_535)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_537 = shr(io.in.a.bits.source, 2)
node _T_538 = eq(_T_537, UInt<2>(0h3))
node _T_539 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_540 = and(_T_538, _T_539)
node _T_541 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_542 = and(_T_540, _T_541)
node _T_543 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_544 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_545 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_546 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_547 = eq(io.in.a.bits.source, UInt<6>(0h2f))
node _T_548 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_549 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_550 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_551 = eq(io.in.a.bits.source, UInt<6>(0h2b))
node _T_552 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_553 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_554 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_555 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_556 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_557 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_558 = or(_T_518, _T_524)
node _T_559 = or(_T_558, _T_530)
node _T_560 = or(_T_559, _T_536)
node _T_561 = or(_T_560, _T_542)
node _T_562 = or(_T_561, _T_543)
node _T_563 = or(_T_562, _T_544)
node _T_564 = or(_T_563, _T_545)
node _T_565 = or(_T_564, _T_546)
node _T_566 = or(_T_565, _T_547)
node _T_567 = or(_T_566, _T_548)
node _T_568 = or(_T_567, _T_549)
node _T_569 = or(_T_568, _T_550)
node _T_570 = or(_T_569, _T_551)
node _T_571 = or(_T_570, _T_552)
node _T_572 = or(_T_571, _T_553)
node _T_573 = or(_T_572, _T_554)
node _T_574 = or(_T_573, _T_555)
node _T_575 = or(_T_574, _T_556)
node _T_576 = or(_T_575, _T_557)
node _T_577 = and(_T_517, _T_576)
node _T_578 = or(UInt<1>(0h0), _T_577)
node _T_579 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_580 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_581 = cvt(_T_580)
node _T_582 = and(_T_581, asSInt(UInt<14>(0h2000)))
node _T_583 = asSInt(_T_582)
node _T_584 = eq(_T_583, asSInt(UInt<1>(0h0)))
node _T_585 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_586 = cvt(_T_585)
node _T_587 = and(_T_586, asSInt(UInt<13>(0h1000)))
node _T_588 = asSInt(_T_587)
node _T_589 = eq(_T_588, asSInt(UInt<1>(0h0)))
node _T_590 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_591 = cvt(_T_590)
node _T_592 = and(_T_591, asSInt(UInt<17>(0h10000)))
node _T_593 = asSInt(_T_592)
node _T_594 = eq(_T_593, asSInt(UInt<1>(0h0)))
node _T_595 = xor(io.in.a.bits.address, UInt<18>(0h20000))
node _T_596 = cvt(_T_595)
node _T_597 = and(_T_596, asSInt(UInt<15>(0h4000)))
node _T_598 = asSInt(_T_597)
node _T_599 = eq(_T_598, asSInt(UInt<1>(0h0)))
node _T_600 = xor(io.in.a.bits.address, UInt<18>(0h24000))
node _T_601 = cvt(_T_600)
node _T_602 = and(_T_601, asSInt(UInt<13>(0h1000)))
node _T_603 = asSInt(_T_602)
node _T_604 = eq(_T_603, asSInt(UInt<1>(0h0)))
node _T_605 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_606 = cvt(_T_605)
node _T_607 = and(_T_606, asSInt(UInt<18>(0h2f000)))
node _T_608 = asSInt(_T_607)
node _T_609 = eq(_T_608, asSInt(UInt<1>(0h0)))
node _T_610 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_611 = cvt(_T_610)
node _T_612 = and(_T_611, asSInt(UInt<17>(0h10000)))
node _T_613 = asSInt(_T_612)
node _T_614 = eq(_T_613, asSInt(UInt<1>(0h0)))
node _T_615 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_616 = cvt(_T_615)
node _T_617 = and(_T_616, asSInt(UInt<13>(0h1000)))
node _T_618 = asSInt(_T_617)
node _T_619 = eq(_T_618, asSInt(UInt<1>(0h0)))
node _T_620 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_621 = cvt(_T_620)
node _T_622 = and(_T_621, asSInt(UInt<27>(0h4000000)))
node _T_623 = asSInt(_T_622)
node _T_624 = eq(_T_623, asSInt(UInt<1>(0h0)))
node _T_625 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_626 = cvt(_T_625)
node _T_627 = and(_T_626, asSInt(UInt<13>(0h1000)))
node _T_628 = asSInt(_T_627)
node _T_629 = eq(_T_628, asSInt(UInt<1>(0h0)))
node _T_630 = or(_T_584, _T_589)
node _T_631 = or(_T_630, _T_594)
node _T_632 = or(_T_631, _T_599)
node _T_633 = or(_T_632, _T_604)
node _T_634 = or(_T_633, _T_609)
node _T_635 = or(_T_634, _T_614)
node _T_636 = or(_T_635, _T_619)
node _T_637 = or(_T_636, _T_624)
node _T_638 = or(_T_637, _T_629)
node _T_639 = and(_T_579, _T_638)
node _T_640 = or(UInt<1>(0h0), _T_639)
node _T_641 = and(_T_578, _T_640)
node _T_642 = asUInt(reset)
node _T_643 = eq(_T_642, UInt<1>(0h0))
when _T_643 :
node _T_644 = eq(_T_641, UInt<1>(0h0))
when _T_644 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_641, UInt<1>(0h1), "") : assert_10
node _T_645 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0)
node _T_646 = shr(io.in.a.bits.source, 2)
node _T_647 = eq(_T_646, UInt<1>(0h0))
node _T_648 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_649 = and(_T_647, _T_648)
node _T_650 = leq(uncommonBits_16, UInt<2>(0h3))
node _T_651 = and(_T_649, _T_650)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0)
node _T_652 = shr(io.in.a.bits.source, 2)
node _T_653 = eq(_T_652, UInt<1>(0h1))
node _T_654 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_655 = and(_T_653, _T_654)
node _T_656 = leq(uncommonBits_17, UInt<2>(0h3))
node _T_657 = and(_T_655, _T_656)
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0)
node _T_658 = shr(io.in.a.bits.source, 2)
node _T_659 = eq(_T_658, UInt<2>(0h2))
node _T_660 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_661 = and(_T_659, _T_660)
node _T_662 = leq(uncommonBits_18, UInt<2>(0h3))
node _T_663 = and(_T_661, _T_662)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0)
node _T_664 = shr(io.in.a.bits.source, 2)
node _T_665 = eq(_T_664, UInt<2>(0h3))
node _T_666 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_667 = and(_T_665, _T_666)
node _T_668 = leq(uncommonBits_19, UInt<2>(0h3))
node _T_669 = and(_T_667, _T_668)
node _T_670 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_671 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_672 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_673 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_674 = eq(io.in.a.bits.source, UInt<6>(0h2f))
node _T_675 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_676 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_677 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_678 = eq(io.in.a.bits.source, UInt<6>(0h2b))
node _T_679 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_680 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_681 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_682 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_683 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_684 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _WIRE_2 : UInt<1>[20]
connect _WIRE_2[0], _T_645
connect _WIRE_2[1], _T_651
connect _WIRE_2[2], _T_657
connect _WIRE_2[3], _T_663
connect _WIRE_2[4], _T_669
connect _WIRE_2[5], _T_670
connect _WIRE_2[6], _T_671
connect _WIRE_2[7], _T_672
connect _WIRE_2[8], _T_673
connect _WIRE_2[9], _T_674
connect _WIRE_2[10], _T_675
connect _WIRE_2[11], _T_676
connect _WIRE_2[12], _T_677
connect _WIRE_2[13], _T_678
connect _WIRE_2[14], _T_679
connect _WIRE_2[15], _T_680
connect _WIRE_2[16], _T_681
connect _WIRE_2[17], _T_682
connect _WIRE_2[18], _T_683
connect _WIRE_2[19], _T_684
node _T_685 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_686 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_687 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_688 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_689 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_690 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_691 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_692 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_693 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_694 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_695 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_696 = mux(_WIRE_2[5], _T_685, UInt<1>(0h0))
node _T_697 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_698 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_699 = mux(_WIRE_2[8], _T_686, UInt<1>(0h0))
node _T_700 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_701 = mux(_WIRE_2[10], _T_687, UInt<1>(0h0))
node _T_702 = mux(_WIRE_2[11], UInt<1>(0h0), UInt<1>(0h0))
node _T_703 = mux(_WIRE_2[12], _T_688, UInt<1>(0h0))
node _T_704 = mux(_WIRE_2[13], UInt<1>(0h0), UInt<1>(0h0))
node _T_705 = mux(_WIRE_2[14], _T_689, UInt<1>(0h0))
node _T_706 = mux(_WIRE_2[15], UInt<1>(0h0), UInt<1>(0h0))
node _T_707 = mux(_WIRE_2[16], UInt<1>(0h0), UInt<1>(0h0))
node _T_708 = mux(_WIRE_2[17], _T_690, UInt<1>(0h0))
node _T_709 = mux(_WIRE_2[18], UInt<1>(0h0), UInt<1>(0h0))
node _T_710 = mux(_WIRE_2[19], UInt<1>(0h0), UInt<1>(0h0))
node _T_711 = or(_T_691, _T_692)
node _T_712 = or(_T_711, _T_693)
node _T_713 = or(_T_712, _T_694)
node _T_714 = or(_T_713, _T_695)
node _T_715 = or(_T_714, _T_696)
node _T_716 = or(_T_715, _T_697)
node _T_717 = or(_T_716, _T_698)
node _T_718 = or(_T_717, _T_699)
node _T_719 = or(_T_718, _T_700)
node _T_720 = or(_T_719, _T_701)
node _T_721 = or(_T_720, _T_702)
node _T_722 = or(_T_721, _T_703)
node _T_723 = or(_T_722, _T_704)
node _T_724 = or(_T_723, _T_705)
node _T_725 = or(_T_724, _T_706)
node _T_726 = or(_T_725, _T_707)
node _T_727 = or(_T_726, _T_708)
node _T_728 = or(_T_727, _T_709)
node _T_729 = or(_T_728, _T_710)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_729
node _T_730 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_731 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_732 = and(_T_730, _T_731)
node _T_733 = or(UInt<1>(0h0), _T_732)
node _T_734 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_735 = cvt(_T_734)
node _T_736 = and(_T_735, asSInt(UInt<14>(0h2000)))
node _T_737 = asSInt(_T_736)
node _T_738 = eq(_T_737, asSInt(UInt<1>(0h0)))
node _T_739 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_740 = cvt(_T_739)
node _T_741 = and(_T_740, asSInt(UInt<13>(0h1000)))
node _T_742 = asSInt(_T_741)
node _T_743 = eq(_T_742, asSInt(UInt<1>(0h0)))
node _T_744 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_745 = cvt(_T_744)
node _T_746 = and(_T_745, asSInt(UInt<17>(0h10000)))
node _T_747 = asSInt(_T_746)
node _T_748 = eq(_T_747, asSInt(UInt<1>(0h0)))
node _T_749 = xor(io.in.a.bits.address, UInt<18>(0h20000))
node _T_750 = cvt(_T_749)
node _T_751 = and(_T_750, asSInt(UInt<15>(0h4000)))
node _T_752 = asSInt(_T_751)
node _T_753 = eq(_T_752, asSInt(UInt<1>(0h0)))
node _T_754 = xor(io.in.a.bits.address, UInt<18>(0h24000))
node _T_755 = cvt(_T_754)
node _T_756 = and(_T_755, asSInt(UInt<13>(0h1000)))
node _T_757 = asSInt(_T_756)
node _T_758 = eq(_T_757, asSInt(UInt<1>(0h0)))
node _T_759 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_760 = cvt(_T_759)
node _T_761 = and(_T_760, asSInt(UInt<18>(0h2f000)))
node _T_762 = asSInt(_T_761)
node _T_763 = eq(_T_762, asSInt(UInt<1>(0h0)))
node _T_764 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_765 = cvt(_T_764)
node _T_766 = and(_T_765, asSInt(UInt<17>(0h10000)))
node _T_767 = asSInt(_T_766)
node _T_768 = eq(_T_767, asSInt(UInt<1>(0h0)))
node _T_769 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_770 = cvt(_T_769)
node _T_771 = and(_T_770, asSInt(UInt<13>(0h1000)))
node _T_772 = asSInt(_T_771)
node _T_773 = eq(_T_772, asSInt(UInt<1>(0h0)))
node _T_774 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_775 = cvt(_T_774)
node _T_776 = and(_T_775, asSInt(UInt<27>(0h4000000)))
node _T_777 = asSInt(_T_776)
node _T_778 = eq(_T_777, asSInt(UInt<1>(0h0)))
node _T_779 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_780 = cvt(_T_779)
node _T_781 = and(_T_780, asSInt(UInt<13>(0h1000)))
node _T_782 = asSInt(_T_781)
node _T_783 = eq(_T_782, asSInt(UInt<1>(0h0)))
node _T_784 = or(_T_738, _T_743)
node _T_785 = or(_T_784, _T_748)
node _T_786 = or(_T_785, _T_753)
node _T_787 = or(_T_786, _T_758)
node _T_788 = or(_T_787, _T_763)
node _T_789 = or(_T_788, _T_768)
node _T_790 = or(_T_789, _T_773)
node _T_791 = or(_T_790, _T_778)
node _T_792 = or(_T_791, _T_783)
node _T_793 = and(_T_733, _T_792)
node _T_794 = or(UInt<1>(0h0), _T_793)
node _T_795 = and(_WIRE_3, _T_794)
node _T_796 = asUInt(reset)
node _T_797 = eq(_T_796, UInt<1>(0h0))
when _T_797 :
node _T_798 = eq(_T_795, UInt<1>(0h0))
when _T_798 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_795, UInt<1>(0h1), "") : assert_11
node _T_799 = asUInt(reset)
node _T_800 = eq(_T_799, UInt<1>(0h0))
when _T_800 :
node _T_801 = eq(source_ok, UInt<1>(0h0))
when _T_801 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_802 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_803 = asUInt(reset)
node _T_804 = eq(_T_803, UInt<1>(0h0))
when _T_804 :
node _T_805 = eq(_T_802, UInt<1>(0h0))
when _T_805 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_802, UInt<1>(0h1), "") : assert_13
node _T_806 = asUInt(reset)
node _T_807 = eq(_T_806, UInt<1>(0h0))
when _T_807 :
node _T_808 = eq(is_aligned, UInt<1>(0h0))
when _T_808 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_809 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_810 = asUInt(reset)
node _T_811 = eq(_T_810, UInt<1>(0h0))
when _T_811 :
node _T_812 = eq(_T_809, UInt<1>(0h0))
when _T_812 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_809, UInt<1>(0h1), "") : assert_15
node _T_813 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_814 = asUInt(reset)
node _T_815 = eq(_T_814, UInt<1>(0h0))
when _T_815 :
node _T_816 = eq(_T_813, UInt<1>(0h0))
when _T_816 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_813, UInt<1>(0h1), "") : assert_16
node _T_817 = not(io.in.a.bits.mask)
node _T_818 = eq(_T_817, UInt<1>(0h0))
node _T_819 = asUInt(reset)
node _T_820 = eq(_T_819, UInt<1>(0h0))
when _T_820 :
node _T_821 = eq(_T_818, UInt<1>(0h0))
when _T_821 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_818, UInt<1>(0h1), "") : assert_17
node _T_822 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_823 = asUInt(reset)
node _T_824 = eq(_T_823, UInt<1>(0h0))
when _T_824 :
node _T_825 = eq(_T_822, UInt<1>(0h0))
when _T_825 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_822, UInt<1>(0h1), "") : assert_18
node _T_826 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_826 :
node _T_827 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_828 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_829 = and(_T_827, _T_828)
node _T_830 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_831 = shr(io.in.a.bits.source, 2)
node _T_832 = eq(_T_831, UInt<1>(0h0))
node _T_833 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_834 = and(_T_832, _T_833)
node _T_835 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_836 = and(_T_834, _T_835)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_837 = shr(io.in.a.bits.source, 2)
node _T_838 = eq(_T_837, UInt<1>(0h1))
node _T_839 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_840 = and(_T_838, _T_839)
node _T_841 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_842 = and(_T_840, _T_841)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0)
node _T_843 = shr(io.in.a.bits.source, 2)
node _T_844 = eq(_T_843, UInt<2>(0h2))
node _T_845 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_846 = and(_T_844, _T_845)
node _T_847 = leq(uncommonBits_22, UInt<2>(0h3))
node _T_848 = and(_T_846, _T_847)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0)
node _T_849 = shr(io.in.a.bits.source, 2)
node _T_850 = eq(_T_849, UInt<2>(0h3))
node _T_851 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_852 = and(_T_850, _T_851)
node _T_853 = leq(uncommonBits_23, UInt<2>(0h3))
node _T_854 = and(_T_852, _T_853)
node _T_855 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_856 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_857 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_858 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_859 = eq(io.in.a.bits.source, UInt<6>(0h2f))
node _T_860 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_861 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_862 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_863 = eq(io.in.a.bits.source, UInt<6>(0h2b))
node _T_864 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_865 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_866 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_867 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_868 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_869 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_870 = or(_T_830, _T_836)
node _T_871 = or(_T_870, _T_842)
node _T_872 = or(_T_871, _T_848)
node _T_873 = or(_T_872, _T_854)
node _T_874 = or(_T_873, _T_855)
node _T_875 = or(_T_874, _T_856)
node _T_876 = or(_T_875, _T_857)
node _T_877 = or(_T_876, _T_858)
node _T_878 = or(_T_877, _T_859)
node _T_879 = or(_T_878, _T_860)
node _T_880 = or(_T_879, _T_861)
node _T_881 = or(_T_880, _T_862)
node _T_882 = or(_T_881, _T_863)
node _T_883 = or(_T_882, _T_864)
node _T_884 = or(_T_883, _T_865)
node _T_885 = or(_T_884, _T_866)
node _T_886 = or(_T_885, _T_867)
node _T_887 = or(_T_886, _T_868)
node _T_888 = or(_T_887, _T_869)
node _T_889 = and(_T_829, _T_888)
node _T_890 = or(UInt<1>(0h0), _T_889)
node _T_891 = asUInt(reset)
node _T_892 = eq(_T_891, UInt<1>(0h0))
when _T_892 :
node _T_893 = eq(_T_890, UInt<1>(0h0))
when _T_893 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_890, UInt<1>(0h1), "") : assert_19
node _T_894 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_895 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_896 = and(_T_894, _T_895)
node _T_897 = or(UInt<1>(0h0), _T_896)
node _T_898 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_899 = cvt(_T_898)
node _T_900 = and(_T_899, asSInt(UInt<13>(0h1000)))
node _T_901 = asSInt(_T_900)
node _T_902 = eq(_T_901, asSInt(UInt<1>(0h0)))
node _T_903 = and(_T_897, _T_902)
node _T_904 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_905 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_906 = and(_T_904, _T_905)
node _T_907 = or(UInt<1>(0h0), _T_906)
node _T_908 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_909 = cvt(_T_908)
node _T_910 = and(_T_909, asSInt(UInt<14>(0h2000)))
node _T_911 = asSInt(_T_910)
node _T_912 = eq(_T_911, asSInt(UInt<1>(0h0)))
node _T_913 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_914 = cvt(_T_913)
node _T_915 = and(_T_914, asSInt(UInt<17>(0h10000)))
node _T_916 = asSInt(_T_915)
node _T_917 = eq(_T_916, asSInt(UInt<1>(0h0)))
node _T_918 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_919 = cvt(_T_918)
node _T_920 = and(_T_919, asSInt(UInt<18>(0h2f000)))
node _T_921 = asSInt(_T_920)
node _T_922 = eq(_T_921, asSInt(UInt<1>(0h0)))
node _T_923 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_924 = cvt(_T_923)
node _T_925 = and(_T_924, asSInt(UInt<17>(0h10000)))
node _T_926 = asSInt(_T_925)
node _T_927 = eq(_T_926, asSInt(UInt<1>(0h0)))
node _T_928 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_929 = cvt(_T_928)
node _T_930 = and(_T_929, asSInt(UInt<13>(0h1000)))
node _T_931 = asSInt(_T_930)
node _T_932 = eq(_T_931, asSInt(UInt<1>(0h0)))
node _T_933 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_934 = cvt(_T_933)
node _T_935 = and(_T_934, asSInt(UInt<27>(0h4000000)))
node _T_936 = asSInt(_T_935)
node _T_937 = eq(_T_936, asSInt(UInt<1>(0h0)))
node _T_938 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_939 = cvt(_T_938)
node _T_940 = and(_T_939, asSInt(UInt<13>(0h1000)))
node _T_941 = asSInt(_T_940)
node _T_942 = eq(_T_941, asSInt(UInt<1>(0h0)))
node _T_943 = or(_T_912, _T_917)
node _T_944 = or(_T_943, _T_922)
node _T_945 = or(_T_944, _T_927)
node _T_946 = or(_T_945, _T_932)
node _T_947 = or(_T_946, _T_937)
node _T_948 = or(_T_947, _T_942)
node _T_949 = and(_T_907, _T_948)
node _T_950 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_951 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_952 = and(_T_950, _T_951)
node _T_953 = or(UInt<1>(0h0), _T_952)
node _T_954 = xor(io.in.a.bits.address, UInt<18>(0h20000))
node _T_955 = cvt(_T_954)
node _T_956 = and(_T_955, asSInt(UInt<15>(0h4000)))
node _T_957 = asSInt(_T_956)
node _T_958 = eq(_T_957, asSInt(UInt<1>(0h0)))
node _T_959 = xor(io.in.a.bits.address, UInt<18>(0h24000))
node _T_960 = cvt(_T_959)
node _T_961 = and(_T_960, asSInt(UInt<13>(0h1000)))
node _T_962 = asSInt(_T_961)
node _T_963 = eq(_T_962, asSInt(UInt<1>(0h0)))
node _T_964 = or(_T_958, _T_963)
node _T_965 = and(_T_953, _T_964)
node _T_966 = or(UInt<1>(0h0), _T_903)
node _T_967 = or(_T_966, _T_949)
node _T_968 = or(_T_967, _T_965)
node _T_969 = asUInt(reset)
node _T_970 = eq(_T_969, UInt<1>(0h0))
when _T_970 :
node _T_971 = eq(_T_968, UInt<1>(0h0))
when _T_971 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_968, UInt<1>(0h1), "") : assert_20
node _T_972 = asUInt(reset)
node _T_973 = eq(_T_972, UInt<1>(0h0))
when _T_973 :
node _T_974 = eq(source_ok, UInt<1>(0h0))
when _T_974 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_975 = asUInt(reset)
node _T_976 = eq(_T_975, UInt<1>(0h0))
when _T_976 :
node _T_977 = eq(is_aligned, UInt<1>(0h0))
when _T_977 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_978 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_979 = asUInt(reset)
node _T_980 = eq(_T_979, UInt<1>(0h0))
when _T_980 :
node _T_981 = eq(_T_978, UInt<1>(0h0))
when _T_981 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_978, UInt<1>(0h1), "") : assert_23
node _T_982 = eq(io.in.a.bits.mask, mask)
node _T_983 = asUInt(reset)
node _T_984 = eq(_T_983, UInt<1>(0h0))
when _T_984 :
node _T_985 = eq(_T_982, UInt<1>(0h0))
when _T_985 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_982, UInt<1>(0h1), "") : assert_24
node _T_986 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_987 = asUInt(reset)
node _T_988 = eq(_T_987, UInt<1>(0h0))
when _T_988 :
node _T_989 = eq(_T_986, UInt<1>(0h0))
when _T_989 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_986, UInt<1>(0h1), "") : assert_25
node _T_990 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_990 :
node _T_991 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_992 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_993 = and(_T_991, _T_992)
node _T_994 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_995 = shr(io.in.a.bits.source, 2)
node _T_996 = eq(_T_995, UInt<1>(0h0))
node _T_997 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_998 = and(_T_996, _T_997)
node _T_999 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_1000 = and(_T_998, _T_999)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_1001 = shr(io.in.a.bits.source, 2)
node _T_1002 = eq(_T_1001, UInt<1>(0h1))
node _T_1003 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_1004 = and(_T_1002, _T_1003)
node _T_1005 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_1006 = and(_T_1004, _T_1005)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_1007 = shr(io.in.a.bits.source, 2)
node _T_1008 = eq(_T_1007, UInt<2>(0h2))
node _T_1009 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_1010 = and(_T_1008, _T_1009)
node _T_1011 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_1012 = and(_T_1010, _T_1011)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_1013 = shr(io.in.a.bits.source, 2)
node _T_1014 = eq(_T_1013, UInt<2>(0h3))
node _T_1015 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_1016 = and(_T_1014, _T_1015)
node _T_1017 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_1018 = and(_T_1016, _T_1017)
node _T_1019 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_1020 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_1021 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_1022 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_1023 = eq(io.in.a.bits.source, UInt<6>(0h2f))
node _T_1024 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_1025 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_1026 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_1027 = eq(io.in.a.bits.source, UInt<6>(0h2b))
node _T_1028 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_1029 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_1030 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_1031 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_1032 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_1033 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_1034 = or(_T_994, _T_1000)
node _T_1035 = or(_T_1034, _T_1006)
node _T_1036 = or(_T_1035, _T_1012)
node _T_1037 = or(_T_1036, _T_1018)
node _T_1038 = or(_T_1037, _T_1019)
node _T_1039 = or(_T_1038, _T_1020)
node _T_1040 = or(_T_1039, _T_1021)
node _T_1041 = or(_T_1040, _T_1022)
node _T_1042 = or(_T_1041, _T_1023)
node _T_1043 = or(_T_1042, _T_1024)
node _T_1044 = or(_T_1043, _T_1025)
node _T_1045 = or(_T_1044, _T_1026)
node _T_1046 = or(_T_1045, _T_1027)
node _T_1047 = or(_T_1046, _T_1028)
node _T_1048 = or(_T_1047, _T_1029)
node _T_1049 = or(_T_1048, _T_1030)
node _T_1050 = or(_T_1049, _T_1031)
node _T_1051 = or(_T_1050, _T_1032)
node _T_1052 = or(_T_1051, _T_1033)
node _T_1053 = and(_T_993, _T_1052)
node _T_1054 = or(UInt<1>(0h0), _T_1053)
node _T_1055 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1056 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1057 = and(_T_1055, _T_1056)
node _T_1058 = or(UInt<1>(0h0), _T_1057)
node _T_1059 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_1060 = cvt(_T_1059)
node _T_1061 = and(_T_1060, asSInt(UInt<13>(0h1000)))
node _T_1062 = asSInt(_T_1061)
node _T_1063 = eq(_T_1062, asSInt(UInt<1>(0h0)))
node _T_1064 = and(_T_1058, _T_1063)
node _T_1065 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1066 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_1067 = and(_T_1065, _T_1066)
node _T_1068 = or(UInt<1>(0h0), _T_1067)
node _T_1069 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1070 = cvt(_T_1069)
node _T_1071 = and(_T_1070, asSInt(UInt<14>(0h2000)))
node _T_1072 = asSInt(_T_1071)
node _T_1073 = eq(_T_1072, asSInt(UInt<1>(0h0)))
node _T_1074 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1075 = cvt(_T_1074)
node _T_1076 = and(_T_1075, asSInt(UInt<18>(0h2f000)))
node _T_1077 = asSInt(_T_1076)
node _T_1078 = eq(_T_1077, asSInt(UInt<1>(0h0)))
node _T_1079 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1080 = cvt(_T_1079)
node _T_1081 = and(_T_1080, asSInt(UInt<17>(0h10000)))
node _T_1082 = asSInt(_T_1081)
node _T_1083 = eq(_T_1082, asSInt(UInt<1>(0h0)))
node _T_1084 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1085 = cvt(_T_1084)
node _T_1086 = and(_T_1085, asSInt(UInt<13>(0h1000)))
node _T_1087 = asSInt(_T_1086)
node _T_1088 = eq(_T_1087, asSInt(UInt<1>(0h0)))
node _T_1089 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1090 = cvt(_T_1089)
node _T_1091 = and(_T_1090, asSInt(UInt<27>(0h4000000)))
node _T_1092 = asSInt(_T_1091)
node _T_1093 = eq(_T_1092, asSInt(UInt<1>(0h0)))
node _T_1094 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1095 = cvt(_T_1094)
node _T_1096 = and(_T_1095, asSInt(UInt<13>(0h1000)))
node _T_1097 = asSInt(_T_1096)
node _T_1098 = eq(_T_1097, asSInt(UInt<1>(0h0)))
node _T_1099 = or(_T_1073, _T_1078)
node _T_1100 = or(_T_1099, _T_1083)
node _T_1101 = or(_T_1100, _T_1088)
node _T_1102 = or(_T_1101, _T_1093)
node _T_1103 = or(_T_1102, _T_1098)
node _T_1104 = and(_T_1068, _T_1103)
node _T_1105 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1106 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1107 = cvt(_T_1106)
node _T_1108 = and(_T_1107, asSInt(UInt<17>(0h10000)))
node _T_1109 = asSInt(_T_1108)
node _T_1110 = eq(_T_1109, asSInt(UInt<1>(0h0)))
node _T_1111 = and(_T_1105, _T_1110)
node _T_1112 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1113 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_1114 = and(_T_1112, _T_1113)
node _T_1115 = or(UInt<1>(0h0), _T_1114)
node _T_1116 = xor(io.in.a.bits.address, UInt<18>(0h20000))
node _T_1117 = cvt(_T_1116)
node _T_1118 = and(_T_1117, asSInt(UInt<15>(0h4000)))
node _T_1119 = asSInt(_T_1118)
node _T_1120 = eq(_T_1119, asSInt(UInt<1>(0h0)))
node _T_1121 = xor(io.in.a.bits.address, UInt<18>(0h24000))
node _T_1122 = cvt(_T_1121)
node _T_1123 = and(_T_1122, asSInt(UInt<13>(0h1000)))
node _T_1124 = asSInt(_T_1123)
node _T_1125 = eq(_T_1124, asSInt(UInt<1>(0h0)))
node _T_1126 = or(_T_1120, _T_1125)
node _T_1127 = and(_T_1115, _T_1126)
node _T_1128 = or(UInt<1>(0h0), _T_1064)
node _T_1129 = or(_T_1128, _T_1104)
node _T_1130 = or(_T_1129, _T_1111)
node _T_1131 = or(_T_1130, _T_1127)
node _T_1132 = and(_T_1054, _T_1131)
node _T_1133 = asUInt(reset)
node _T_1134 = eq(_T_1133, UInt<1>(0h0))
when _T_1134 :
node _T_1135 = eq(_T_1132, UInt<1>(0h0))
when _T_1135 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_1132, UInt<1>(0h1), "") : assert_26
node _T_1136 = asUInt(reset)
node _T_1137 = eq(_T_1136, UInt<1>(0h0))
when _T_1137 :
node _T_1138 = eq(source_ok, UInt<1>(0h0))
when _T_1138 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_1139 = asUInt(reset)
node _T_1140 = eq(_T_1139, UInt<1>(0h0))
when _T_1140 :
node _T_1141 = eq(is_aligned, UInt<1>(0h0))
when _T_1141 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_1142 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_1143 = asUInt(reset)
node _T_1144 = eq(_T_1143, UInt<1>(0h0))
when _T_1144 :
node _T_1145 = eq(_T_1142, UInt<1>(0h0))
when _T_1145 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_1142, UInt<1>(0h1), "") : assert_29
node _T_1146 = eq(io.in.a.bits.mask, mask)
node _T_1147 = asUInt(reset)
node _T_1148 = eq(_T_1147, UInt<1>(0h0))
when _T_1148 :
node _T_1149 = eq(_T_1146, UInt<1>(0h0))
when _T_1149 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_1146, UInt<1>(0h1), "") : assert_30
node _T_1150 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_1150 :
node _T_1151 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1152 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1153 = and(_T_1151, _T_1152)
node _T_1154 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0)
node _T_1155 = shr(io.in.a.bits.source, 2)
node _T_1156 = eq(_T_1155, UInt<1>(0h0))
node _T_1157 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_1158 = and(_T_1156, _T_1157)
node _T_1159 = leq(uncommonBits_28, UInt<2>(0h3))
node _T_1160 = and(_T_1158, _T_1159)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0)
node _T_1161 = shr(io.in.a.bits.source, 2)
node _T_1162 = eq(_T_1161, UInt<1>(0h1))
node _T_1163 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_1164 = and(_T_1162, _T_1163)
node _T_1165 = leq(uncommonBits_29, UInt<2>(0h3))
node _T_1166 = and(_T_1164, _T_1165)
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_1167 = shr(io.in.a.bits.source, 2)
node _T_1168 = eq(_T_1167, UInt<2>(0h2))
node _T_1169 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_1170 = and(_T_1168, _T_1169)
node _T_1171 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_1172 = and(_T_1170, _T_1171)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_1173 = shr(io.in.a.bits.source, 2)
node _T_1174 = eq(_T_1173, UInt<2>(0h3))
node _T_1175 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_1176 = and(_T_1174, _T_1175)
node _T_1177 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_1178 = and(_T_1176, _T_1177)
node _T_1179 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_1180 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_1181 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_1182 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_1183 = eq(io.in.a.bits.source, UInt<6>(0h2f))
node _T_1184 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_1185 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_1186 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_1187 = eq(io.in.a.bits.source, UInt<6>(0h2b))
node _T_1188 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_1189 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_1190 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_1191 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_1192 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_1193 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_1194 = or(_T_1154, _T_1160)
node _T_1195 = or(_T_1194, _T_1166)
node _T_1196 = or(_T_1195, _T_1172)
node _T_1197 = or(_T_1196, _T_1178)
node _T_1198 = or(_T_1197, _T_1179)
node _T_1199 = or(_T_1198, _T_1180)
node _T_1200 = or(_T_1199, _T_1181)
node _T_1201 = or(_T_1200, _T_1182)
node _T_1202 = or(_T_1201, _T_1183)
node _T_1203 = or(_T_1202, _T_1184)
node _T_1204 = or(_T_1203, _T_1185)
node _T_1205 = or(_T_1204, _T_1186)
node _T_1206 = or(_T_1205, _T_1187)
node _T_1207 = or(_T_1206, _T_1188)
node _T_1208 = or(_T_1207, _T_1189)
node _T_1209 = or(_T_1208, _T_1190)
node _T_1210 = or(_T_1209, _T_1191)
node _T_1211 = or(_T_1210, _T_1192)
node _T_1212 = or(_T_1211, _T_1193)
node _T_1213 = and(_T_1153, _T_1212)
node _T_1214 = or(UInt<1>(0h0), _T_1213)
node _T_1215 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1216 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1217 = and(_T_1215, _T_1216)
node _T_1218 = or(UInt<1>(0h0), _T_1217)
node _T_1219 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_1220 = cvt(_T_1219)
node _T_1221 = and(_T_1220, asSInt(UInt<13>(0h1000)))
node _T_1222 = asSInt(_T_1221)
node _T_1223 = eq(_T_1222, asSInt(UInt<1>(0h0)))
node _T_1224 = and(_T_1218, _T_1223)
node _T_1225 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1226 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_1227 = and(_T_1225, _T_1226)
node _T_1228 = or(UInt<1>(0h0), _T_1227)
node _T_1229 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1230 = cvt(_T_1229)
node _T_1231 = and(_T_1230, asSInt(UInt<14>(0h2000)))
node _T_1232 = asSInt(_T_1231)
node _T_1233 = eq(_T_1232, asSInt(UInt<1>(0h0)))
node _T_1234 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1235 = cvt(_T_1234)
node _T_1236 = and(_T_1235, asSInt(UInt<18>(0h2f000)))
node _T_1237 = asSInt(_T_1236)
node _T_1238 = eq(_T_1237, asSInt(UInt<1>(0h0)))
node _T_1239 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1240 = cvt(_T_1239)
node _T_1241 = and(_T_1240, asSInt(UInt<17>(0h10000)))
node _T_1242 = asSInt(_T_1241)
node _T_1243 = eq(_T_1242, asSInt(UInt<1>(0h0)))
node _T_1244 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1245 = cvt(_T_1244)
node _T_1246 = and(_T_1245, asSInt(UInt<13>(0h1000)))
node _T_1247 = asSInt(_T_1246)
node _T_1248 = eq(_T_1247, asSInt(UInt<1>(0h0)))
node _T_1249 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1250 = cvt(_T_1249)
node _T_1251 = and(_T_1250, asSInt(UInt<27>(0h4000000)))
node _T_1252 = asSInt(_T_1251)
node _T_1253 = eq(_T_1252, asSInt(UInt<1>(0h0)))
node _T_1254 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1255 = cvt(_T_1254)
node _T_1256 = and(_T_1255, asSInt(UInt<13>(0h1000)))
node _T_1257 = asSInt(_T_1256)
node _T_1258 = eq(_T_1257, asSInt(UInt<1>(0h0)))
node _T_1259 = or(_T_1233, _T_1238)
node _T_1260 = or(_T_1259, _T_1243)
node _T_1261 = or(_T_1260, _T_1248)
node _T_1262 = or(_T_1261, _T_1253)
node _T_1263 = or(_T_1262, _T_1258)
node _T_1264 = and(_T_1228, _T_1263)
node _T_1265 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1266 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1267 = cvt(_T_1266)
node _T_1268 = and(_T_1267, asSInt(UInt<17>(0h10000)))
node _T_1269 = asSInt(_T_1268)
node _T_1270 = eq(_T_1269, asSInt(UInt<1>(0h0)))
node _T_1271 = and(_T_1265, _T_1270)
node _T_1272 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1273 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_1274 = and(_T_1272, _T_1273)
node _T_1275 = or(UInt<1>(0h0), _T_1274)
node _T_1276 = xor(io.in.a.bits.address, UInt<18>(0h20000))
node _T_1277 = cvt(_T_1276)
node _T_1278 = and(_T_1277, asSInt(UInt<15>(0h4000)))
node _T_1279 = asSInt(_T_1278)
node _T_1280 = eq(_T_1279, asSInt(UInt<1>(0h0)))
node _T_1281 = xor(io.in.a.bits.address, UInt<18>(0h24000))
node _T_1282 = cvt(_T_1281)
node _T_1283 = and(_T_1282, asSInt(UInt<13>(0h1000)))
node _T_1284 = asSInt(_T_1283)
node _T_1285 = eq(_T_1284, asSInt(UInt<1>(0h0)))
node _T_1286 = or(_T_1280, _T_1285)
node _T_1287 = and(_T_1275, _T_1286)
node _T_1288 = or(UInt<1>(0h0), _T_1224)
node _T_1289 = or(_T_1288, _T_1264)
node _T_1290 = or(_T_1289, _T_1271)
node _T_1291 = or(_T_1290, _T_1287)
node _T_1292 = and(_T_1214, _T_1291)
node _T_1293 = asUInt(reset)
node _T_1294 = eq(_T_1293, UInt<1>(0h0))
when _T_1294 :
node _T_1295 = eq(_T_1292, UInt<1>(0h0))
when _T_1295 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_1292, UInt<1>(0h1), "") : assert_31
node _T_1296 = asUInt(reset)
node _T_1297 = eq(_T_1296, UInt<1>(0h0))
when _T_1297 :
node _T_1298 = eq(source_ok, UInt<1>(0h0))
when _T_1298 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_1299 = asUInt(reset)
node _T_1300 = eq(_T_1299, UInt<1>(0h0))
when _T_1300 :
node _T_1301 = eq(is_aligned, UInt<1>(0h0))
when _T_1301 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_1302 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_1303 = asUInt(reset)
node _T_1304 = eq(_T_1303, UInt<1>(0h0))
when _T_1304 :
node _T_1305 = eq(_T_1302, UInt<1>(0h0))
when _T_1305 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_1302, UInt<1>(0h1), "") : assert_34
node _T_1306 = not(mask)
node _T_1307 = and(io.in.a.bits.mask, _T_1306)
node _T_1308 = eq(_T_1307, UInt<1>(0h0))
node _T_1309 = asUInt(reset)
node _T_1310 = eq(_T_1309, UInt<1>(0h0))
when _T_1310 :
node _T_1311 = eq(_T_1308, UInt<1>(0h0))
when _T_1311 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_1308, UInt<1>(0h1), "") : assert_35
node _T_1312 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_1312 :
node _T_1313 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1314 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1315 = and(_T_1313, _T_1314)
node _T_1316 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_1317 = shr(io.in.a.bits.source, 2)
node _T_1318 = eq(_T_1317, UInt<1>(0h0))
node _T_1319 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_1320 = and(_T_1318, _T_1319)
node _T_1321 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_1322 = and(_T_1320, _T_1321)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_1323 = shr(io.in.a.bits.source, 2)
node _T_1324 = eq(_T_1323, UInt<1>(0h1))
node _T_1325 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_1326 = and(_T_1324, _T_1325)
node _T_1327 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_1328 = and(_T_1326, _T_1327)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0)
node _T_1329 = shr(io.in.a.bits.source, 2)
node _T_1330 = eq(_T_1329, UInt<2>(0h2))
node _T_1331 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_1332 = and(_T_1330, _T_1331)
node _T_1333 = leq(uncommonBits_34, UInt<2>(0h3))
node _T_1334 = and(_T_1332, _T_1333)
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0)
node _T_1335 = shr(io.in.a.bits.source, 2)
node _T_1336 = eq(_T_1335, UInt<2>(0h3))
node _T_1337 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_1338 = and(_T_1336, _T_1337)
node _T_1339 = leq(uncommonBits_35, UInt<2>(0h3))
node _T_1340 = and(_T_1338, _T_1339)
node _T_1341 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_1342 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_1343 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_1344 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_1345 = eq(io.in.a.bits.source, UInt<6>(0h2f))
node _T_1346 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_1347 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_1348 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_1349 = eq(io.in.a.bits.source, UInt<6>(0h2b))
node _T_1350 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_1351 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_1352 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_1353 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_1354 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_1355 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_1356 = or(_T_1316, _T_1322)
node _T_1357 = or(_T_1356, _T_1328)
node _T_1358 = or(_T_1357, _T_1334)
node _T_1359 = or(_T_1358, _T_1340)
node _T_1360 = or(_T_1359, _T_1341)
node _T_1361 = or(_T_1360, _T_1342)
node _T_1362 = or(_T_1361, _T_1343)
node _T_1363 = or(_T_1362, _T_1344)
node _T_1364 = or(_T_1363, _T_1345)
node _T_1365 = or(_T_1364, _T_1346)
node _T_1366 = or(_T_1365, _T_1347)
node _T_1367 = or(_T_1366, _T_1348)
node _T_1368 = or(_T_1367, _T_1349)
node _T_1369 = or(_T_1368, _T_1350)
node _T_1370 = or(_T_1369, _T_1351)
node _T_1371 = or(_T_1370, _T_1352)
node _T_1372 = or(_T_1371, _T_1353)
node _T_1373 = or(_T_1372, _T_1354)
node _T_1374 = or(_T_1373, _T_1355)
node _T_1375 = and(_T_1315, _T_1374)
node _T_1376 = or(UInt<1>(0h0), _T_1375)
node _T_1377 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1378 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_1379 = and(_T_1377, _T_1378)
node _T_1380 = or(UInt<1>(0h0), _T_1379)
node _T_1381 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1382 = cvt(_T_1381)
node _T_1383 = and(_T_1382, asSInt(UInt<14>(0h2000)))
node _T_1384 = asSInt(_T_1383)
node _T_1385 = eq(_T_1384, asSInt(UInt<1>(0h0)))
node _T_1386 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_1387 = cvt(_T_1386)
node _T_1388 = and(_T_1387, asSInt(UInt<13>(0h1000)))
node _T_1389 = asSInt(_T_1388)
node _T_1390 = eq(_T_1389, asSInt(UInt<1>(0h0)))
node _T_1391 = xor(io.in.a.bits.address, UInt<18>(0h20000))
node _T_1392 = cvt(_T_1391)
node _T_1393 = and(_T_1392, asSInt(UInt<15>(0h4000)))
node _T_1394 = asSInt(_T_1393)
node _T_1395 = eq(_T_1394, asSInt(UInt<1>(0h0)))
node _T_1396 = xor(io.in.a.bits.address, UInt<18>(0h24000))
node _T_1397 = cvt(_T_1396)
node _T_1398 = and(_T_1397, asSInt(UInt<13>(0h1000)))
node _T_1399 = asSInt(_T_1398)
node _T_1400 = eq(_T_1399, asSInt(UInt<1>(0h0)))
node _T_1401 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1402 = cvt(_T_1401)
node _T_1403 = and(_T_1402, asSInt(UInt<18>(0h2f000)))
node _T_1404 = asSInt(_T_1403)
node _T_1405 = eq(_T_1404, asSInt(UInt<1>(0h0)))
node _T_1406 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1407 = cvt(_T_1406)
node _T_1408 = and(_T_1407, asSInt(UInt<17>(0h10000)))
node _T_1409 = asSInt(_T_1408)
node _T_1410 = eq(_T_1409, asSInt(UInt<1>(0h0)))
node _T_1411 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1412 = cvt(_T_1411)
node _T_1413 = and(_T_1412, asSInt(UInt<13>(0h1000)))
node _T_1414 = asSInt(_T_1413)
node _T_1415 = eq(_T_1414, asSInt(UInt<1>(0h0)))
node _T_1416 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1417 = cvt(_T_1416)
node _T_1418 = and(_T_1417, asSInt(UInt<27>(0h4000000)))
node _T_1419 = asSInt(_T_1418)
node _T_1420 = eq(_T_1419, asSInt(UInt<1>(0h0)))
node _T_1421 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1422 = cvt(_T_1421)
node _T_1423 = and(_T_1422, asSInt(UInt<13>(0h1000)))
node _T_1424 = asSInt(_T_1423)
node _T_1425 = eq(_T_1424, asSInt(UInt<1>(0h0)))
node _T_1426 = or(_T_1385, _T_1390)
node _T_1427 = or(_T_1426, _T_1395)
node _T_1428 = or(_T_1427, _T_1400)
node _T_1429 = or(_T_1428, _T_1405)
node _T_1430 = or(_T_1429, _T_1410)
node _T_1431 = or(_T_1430, _T_1415)
node _T_1432 = or(_T_1431, _T_1420)
node _T_1433 = or(_T_1432, _T_1425)
node _T_1434 = and(_T_1380, _T_1433)
node _T_1435 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1436 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1437 = cvt(_T_1436)
node _T_1438 = and(_T_1437, asSInt(UInt<17>(0h10000)))
node _T_1439 = asSInt(_T_1438)
node _T_1440 = eq(_T_1439, asSInt(UInt<1>(0h0)))
node _T_1441 = and(_T_1435, _T_1440)
node _T_1442 = or(UInt<1>(0h0), _T_1434)
node _T_1443 = or(_T_1442, _T_1441)
node _T_1444 = and(_T_1376, _T_1443)
node _T_1445 = asUInt(reset)
node _T_1446 = eq(_T_1445, UInt<1>(0h0))
when _T_1446 :
node _T_1447 = eq(_T_1444, UInt<1>(0h0))
when _T_1447 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_1444, UInt<1>(0h1), "") : assert_36
node _T_1448 = asUInt(reset)
node _T_1449 = eq(_T_1448, UInt<1>(0h0))
when _T_1449 :
node _T_1450 = eq(source_ok, UInt<1>(0h0))
when _T_1450 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_1451 = asUInt(reset)
node _T_1452 = eq(_T_1451, UInt<1>(0h0))
when _T_1452 :
node _T_1453 = eq(is_aligned, UInt<1>(0h0))
when _T_1453 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_1454 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_1455 = asUInt(reset)
node _T_1456 = eq(_T_1455, UInt<1>(0h0))
when _T_1456 :
node _T_1457 = eq(_T_1454, UInt<1>(0h0))
when _T_1457 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_1454, UInt<1>(0h1), "") : assert_39
node _T_1458 = eq(io.in.a.bits.mask, mask)
node _T_1459 = asUInt(reset)
node _T_1460 = eq(_T_1459, UInt<1>(0h0))
when _T_1460 :
node _T_1461 = eq(_T_1458, UInt<1>(0h0))
when _T_1461 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_1458, UInt<1>(0h1), "") : assert_40
node _T_1462 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_1462 :
node _T_1463 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1464 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1465 = and(_T_1463, _T_1464)
node _T_1466 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0)
node _T_1467 = shr(io.in.a.bits.source, 2)
node _T_1468 = eq(_T_1467, UInt<1>(0h0))
node _T_1469 = leq(UInt<1>(0h0), uncommonBits_36)
node _T_1470 = and(_T_1468, _T_1469)
node _T_1471 = leq(uncommonBits_36, UInt<2>(0h3))
node _T_1472 = and(_T_1470, _T_1471)
node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0)
node _T_1473 = shr(io.in.a.bits.source, 2)
node _T_1474 = eq(_T_1473, UInt<1>(0h1))
node _T_1475 = leq(UInt<1>(0h0), uncommonBits_37)
node _T_1476 = and(_T_1474, _T_1475)
node _T_1477 = leq(uncommonBits_37, UInt<2>(0h3))
node _T_1478 = and(_T_1476, _T_1477)
node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0)
node _T_1479 = shr(io.in.a.bits.source, 2)
node _T_1480 = eq(_T_1479, UInt<2>(0h2))
node _T_1481 = leq(UInt<1>(0h0), uncommonBits_38)
node _T_1482 = and(_T_1480, _T_1481)
node _T_1483 = leq(uncommonBits_38, UInt<2>(0h3))
node _T_1484 = and(_T_1482, _T_1483)
node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0)
node _T_1485 = shr(io.in.a.bits.source, 2)
node _T_1486 = eq(_T_1485, UInt<2>(0h3))
node _T_1487 = leq(UInt<1>(0h0), uncommonBits_39)
node _T_1488 = and(_T_1486, _T_1487)
node _T_1489 = leq(uncommonBits_39, UInt<2>(0h3))
node _T_1490 = and(_T_1488, _T_1489)
node _T_1491 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_1492 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_1493 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_1494 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_1495 = eq(io.in.a.bits.source, UInt<6>(0h2f))
node _T_1496 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_1497 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_1498 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_1499 = eq(io.in.a.bits.source, UInt<6>(0h2b))
node _T_1500 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_1501 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_1502 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_1503 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_1504 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_1505 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_1506 = or(_T_1466, _T_1472)
node _T_1507 = or(_T_1506, _T_1478)
node _T_1508 = or(_T_1507, _T_1484)
node _T_1509 = or(_T_1508, _T_1490)
node _T_1510 = or(_T_1509, _T_1491)
node _T_1511 = or(_T_1510, _T_1492)
node _T_1512 = or(_T_1511, _T_1493)
node _T_1513 = or(_T_1512, _T_1494)
node _T_1514 = or(_T_1513, _T_1495)
node _T_1515 = or(_T_1514, _T_1496)
node _T_1516 = or(_T_1515, _T_1497)
node _T_1517 = or(_T_1516, _T_1498)
node _T_1518 = or(_T_1517, _T_1499)
node _T_1519 = or(_T_1518, _T_1500)
node _T_1520 = or(_T_1519, _T_1501)
node _T_1521 = or(_T_1520, _T_1502)
node _T_1522 = or(_T_1521, _T_1503)
node _T_1523 = or(_T_1522, _T_1504)
node _T_1524 = or(_T_1523, _T_1505)
node _T_1525 = and(_T_1465, _T_1524)
node _T_1526 = or(UInt<1>(0h0), _T_1525)
node _T_1527 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1528 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_1529 = and(_T_1527, _T_1528)
node _T_1530 = or(UInt<1>(0h0), _T_1529)
node _T_1531 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1532 = cvt(_T_1531)
node _T_1533 = and(_T_1532, asSInt(UInt<14>(0h2000)))
node _T_1534 = asSInt(_T_1533)
node _T_1535 = eq(_T_1534, asSInt(UInt<1>(0h0)))
node _T_1536 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_1537 = cvt(_T_1536)
node _T_1538 = and(_T_1537, asSInt(UInt<13>(0h1000)))
node _T_1539 = asSInt(_T_1538)
node _T_1540 = eq(_T_1539, asSInt(UInt<1>(0h0)))
node _T_1541 = xor(io.in.a.bits.address, UInt<18>(0h20000))
node _T_1542 = cvt(_T_1541)
node _T_1543 = and(_T_1542, asSInt(UInt<15>(0h4000)))
node _T_1544 = asSInt(_T_1543)
node _T_1545 = eq(_T_1544, asSInt(UInt<1>(0h0)))
node _T_1546 = xor(io.in.a.bits.address, UInt<18>(0h24000))
node _T_1547 = cvt(_T_1546)
node _T_1548 = and(_T_1547, asSInt(UInt<13>(0h1000)))
node _T_1549 = asSInt(_T_1548)
node _T_1550 = eq(_T_1549, asSInt(UInt<1>(0h0)))
node _T_1551 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1552 = cvt(_T_1551)
node _T_1553 = and(_T_1552, asSInt(UInt<18>(0h2f000)))
node _T_1554 = asSInt(_T_1553)
node _T_1555 = eq(_T_1554, asSInt(UInt<1>(0h0)))
node _T_1556 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1557 = cvt(_T_1556)
node _T_1558 = and(_T_1557, asSInt(UInt<17>(0h10000)))
node _T_1559 = asSInt(_T_1558)
node _T_1560 = eq(_T_1559, asSInt(UInt<1>(0h0)))
node _T_1561 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1562 = cvt(_T_1561)
node _T_1563 = and(_T_1562, asSInt(UInt<13>(0h1000)))
node _T_1564 = asSInt(_T_1563)
node _T_1565 = eq(_T_1564, asSInt(UInt<1>(0h0)))
node _T_1566 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1567 = cvt(_T_1566)
node _T_1568 = and(_T_1567, asSInt(UInt<27>(0h4000000)))
node _T_1569 = asSInt(_T_1568)
node _T_1570 = eq(_T_1569, asSInt(UInt<1>(0h0)))
node _T_1571 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1572 = cvt(_T_1571)
node _T_1573 = and(_T_1572, asSInt(UInt<13>(0h1000)))
node _T_1574 = asSInt(_T_1573)
node _T_1575 = eq(_T_1574, asSInt(UInt<1>(0h0)))
node _T_1576 = or(_T_1535, _T_1540)
node _T_1577 = or(_T_1576, _T_1545)
node _T_1578 = or(_T_1577, _T_1550)
node _T_1579 = or(_T_1578, _T_1555)
node _T_1580 = or(_T_1579, _T_1560)
node _T_1581 = or(_T_1580, _T_1565)
node _T_1582 = or(_T_1581, _T_1570)
node _T_1583 = or(_T_1582, _T_1575)
node _T_1584 = and(_T_1530, _T_1583)
node _T_1585 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1586 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1587 = cvt(_T_1586)
node _T_1588 = and(_T_1587, asSInt(UInt<17>(0h10000)))
node _T_1589 = asSInt(_T_1588)
node _T_1590 = eq(_T_1589, asSInt(UInt<1>(0h0)))
node _T_1591 = and(_T_1585, _T_1590)
node _T_1592 = or(UInt<1>(0h0), _T_1584)
node _T_1593 = or(_T_1592, _T_1591)
node _T_1594 = and(_T_1526, _T_1593)
node _T_1595 = asUInt(reset)
node _T_1596 = eq(_T_1595, UInt<1>(0h0))
when _T_1596 :
node _T_1597 = eq(_T_1594, UInt<1>(0h0))
when _T_1597 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_1594, UInt<1>(0h1), "") : assert_41
node _T_1598 = asUInt(reset)
node _T_1599 = eq(_T_1598, UInt<1>(0h0))
when _T_1599 :
node _T_1600 = eq(source_ok, UInt<1>(0h0))
when _T_1600 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_1601 = asUInt(reset)
node _T_1602 = eq(_T_1601, UInt<1>(0h0))
when _T_1602 :
node _T_1603 = eq(is_aligned, UInt<1>(0h0))
when _T_1603 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_1604 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_1605 = asUInt(reset)
node _T_1606 = eq(_T_1605, UInt<1>(0h0))
when _T_1606 :
node _T_1607 = eq(_T_1604, UInt<1>(0h0))
when _T_1607 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_1604, UInt<1>(0h1), "") : assert_44
node _T_1608 = eq(io.in.a.bits.mask, mask)
node _T_1609 = asUInt(reset)
node _T_1610 = eq(_T_1609, UInt<1>(0h0))
when _T_1610 :
node _T_1611 = eq(_T_1608, UInt<1>(0h0))
when _T_1611 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_1608, UInt<1>(0h1), "") : assert_45
node _T_1612 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_1612 :
node _T_1613 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1614 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1615 = and(_T_1613, _T_1614)
node _T_1616 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0)
node _T_1617 = shr(io.in.a.bits.source, 2)
node _T_1618 = eq(_T_1617, UInt<1>(0h0))
node _T_1619 = leq(UInt<1>(0h0), uncommonBits_40)
node _T_1620 = and(_T_1618, _T_1619)
node _T_1621 = leq(uncommonBits_40, UInt<2>(0h3))
node _T_1622 = and(_T_1620, _T_1621)
node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0)
node _T_1623 = shr(io.in.a.bits.source, 2)
node _T_1624 = eq(_T_1623, UInt<1>(0h1))
node _T_1625 = leq(UInt<1>(0h0), uncommonBits_41)
node _T_1626 = and(_T_1624, _T_1625)
node _T_1627 = leq(uncommonBits_41, UInt<2>(0h3))
node _T_1628 = and(_T_1626, _T_1627)
node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0)
node _T_1629 = shr(io.in.a.bits.source, 2)
node _T_1630 = eq(_T_1629, UInt<2>(0h2))
node _T_1631 = leq(UInt<1>(0h0), uncommonBits_42)
node _T_1632 = and(_T_1630, _T_1631)
node _T_1633 = leq(uncommonBits_42, UInt<2>(0h3))
node _T_1634 = and(_T_1632, _T_1633)
node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0)
node _T_1635 = shr(io.in.a.bits.source, 2)
node _T_1636 = eq(_T_1635, UInt<2>(0h3))
node _T_1637 = leq(UInt<1>(0h0), uncommonBits_43)
node _T_1638 = and(_T_1636, _T_1637)
node _T_1639 = leq(uncommonBits_43, UInt<2>(0h3))
node _T_1640 = and(_T_1638, _T_1639)
node _T_1641 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_1642 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_1643 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_1644 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_1645 = eq(io.in.a.bits.source, UInt<6>(0h2f))
node _T_1646 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_1647 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_1648 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_1649 = eq(io.in.a.bits.source, UInt<6>(0h2b))
node _T_1650 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_1651 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_1652 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_1653 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_1654 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_1655 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_1656 = or(_T_1616, _T_1622)
node _T_1657 = or(_T_1656, _T_1628)
node _T_1658 = or(_T_1657, _T_1634)
node _T_1659 = or(_T_1658, _T_1640)
node _T_1660 = or(_T_1659, _T_1641)
node _T_1661 = or(_T_1660, _T_1642)
node _T_1662 = or(_T_1661, _T_1643)
node _T_1663 = or(_T_1662, _T_1644)
node _T_1664 = or(_T_1663, _T_1645)
node _T_1665 = or(_T_1664, _T_1646)
node _T_1666 = or(_T_1665, _T_1647)
node _T_1667 = or(_T_1666, _T_1648)
node _T_1668 = or(_T_1667, _T_1649)
node _T_1669 = or(_T_1668, _T_1650)
node _T_1670 = or(_T_1669, _T_1651)
node _T_1671 = or(_T_1670, _T_1652)
node _T_1672 = or(_T_1671, _T_1653)
node _T_1673 = or(_T_1672, _T_1654)
node _T_1674 = or(_T_1673, _T_1655)
node _T_1675 = and(_T_1615, _T_1674)
node _T_1676 = or(UInt<1>(0h0), _T_1675)
node _T_1677 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1678 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1679 = and(_T_1677, _T_1678)
node _T_1680 = or(UInt<1>(0h0), _T_1679)
node _T_1681 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_1682 = cvt(_T_1681)
node _T_1683 = and(_T_1682, asSInt(UInt<13>(0h1000)))
node _T_1684 = asSInt(_T_1683)
node _T_1685 = eq(_T_1684, asSInt(UInt<1>(0h0)))
node _T_1686 = and(_T_1680, _T_1685)
node _T_1687 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1688 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1689 = cvt(_T_1688)
node _T_1690 = and(_T_1689, asSInt(UInt<14>(0h2000)))
node _T_1691 = asSInt(_T_1690)
node _T_1692 = eq(_T_1691, asSInt(UInt<1>(0h0)))
node _T_1693 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1694 = cvt(_T_1693)
node _T_1695 = and(_T_1694, asSInt(UInt<17>(0h10000)))
node _T_1696 = asSInt(_T_1695)
node _T_1697 = eq(_T_1696, asSInt(UInt<1>(0h0)))
node _T_1698 = xor(io.in.a.bits.address, UInt<18>(0h20000))
node _T_1699 = cvt(_T_1698)
node _T_1700 = and(_T_1699, asSInt(UInt<15>(0h4000)))
node _T_1701 = asSInt(_T_1700)
node _T_1702 = eq(_T_1701, asSInt(UInt<1>(0h0)))
node _T_1703 = xor(io.in.a.bits.address, UInt<18>(0h24000))
node _T_1704 = cvt(_T_1703)
node _T_1705 = and(_T_1704, asSInt(UInt<13>(0h1000)))
node _T_1706 = asSInt(_T_1705)
node _T_1707 = eq(_T_1706, asSInt(UInt<1>(0h0)))
node _T_1708 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1709 = cvt(_T_1708)
node _T_1710 = and(_T_1709, asSInt(UInt<18>(0h2f000)))
node _T_1711 = asSInt(_T_1710)
node _T_1712 = eq(_T_1711, asSInt(UInt<1>(0h0)))
node _T_1713 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1714 = cvt(_T_1713)
node _T_1715 = and(_T_1714, asSInt(UInt<17>(0h10000)))
node _T_1716 = asSInt(_T_1715)
node _T_1717 = eq(_T_1716, asSInt(UInt<1>(0h0)))
node _T_1718 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1719 = cvt(_T_1718)
node _T_1720 = and(_T_1719, asSInt(UInt<13>(0h1000)))
node _T_1721 = asSInt(_T_1720)
node _T_1722 = eq(_T_1721, asSInt(UInt<1>(0h0)))
node _T_1723 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1724 = cvt(_T_1723)
node _T_1725 = and(_T_1724, asSInt(UInt<27>(0h4000000)))
node _T_1726 = asSInt(_T_1725)
node _T_1727 = eq(_T_1726, asSInt(UInt<1>(0h0)))
node _T_1728 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1729 = cvt(_T_1728)
node _T_1730 = and(_T_1729, asSInt(UInt<13>(0h1000)))
node _T_1731 = asSInt(_T_1730)
node _T_1732 = eq(_T_1731, asSInt(UInt<1>(0h0)))
node _T_1733 = or(_T_1692, _T_1697)
node _T_1734 = or(_T_1733, _T_1702)
node _T_1735 = or(_T_1734, _T_1707)
node _T_1736 = or(_T_1735, _T_1712)
node _T_1737 = or(_T_1736, _T_1717)
node _T_1738 = or(_T_1737, _T_1722)
node _T_1739 = or(_T_1738, _T_1727)
node _T_1740 = or(_T_1739, _T_1732)
node _T_1741 = and(_T_1687, _T_1740)
node _T_1742 = or(UInt<1>(0h0), _T_1686)
node _T_1743 = or(_T_1742, _T_1741)
node _T_1744 = and(_T_1676, _T_1743)
node _T_1745 = asUInt(reset)
node _T_1746 = eq(_T_1745, UInt<1>(0h0))
when _T_1746 :
node _T_1747 = eq(_T_1744, UInt<1>(0h0))
when _T_1747 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_1744, UInt<1>(0h1), "") : assert_46
node _T_1748 = asUInt(reset)
node _T_1749 = eq(_T_1748, UInt<1>(0h0))
when _T_1749 :
node _T_1750 = eq(source_ok, UInt<1>(0h0))
when _T_1750 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_1751 = asUInt(reset)
node _T_1752 = eq(_T_1751, UInt<1>(0h0))
when _T_1752 :
node _T_1753 = eq(is_aligned, UInt<1>(0h0))
when _T_1753 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_1754 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_1755 = asUInt(reset)
node _T_1756 = eq(_T_1755, UInt<1>(0h0))
when _T_1756 :
node _T_1757 = eq(_T_1754, UInt<1>(0h0))
when _T_1757 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_1754, UInt<1>(0h1), "") : assert_49
node _T_1758 = eq(io.in.a.bits.mask, mask)
node _T_1759 = asUInt(reset)
node _T_1760 = eq(_T_1759, UInt<1>(0h0))
when _T_1760 :
node _T_1761 = eq(_T_1758, UInt<1>(0h0))
when _T_1761 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_1758, UInt<1>(0h1), "") : assert_50
node _T_1762 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1763 = asUInt(reset)
node _T_1764 = eq(_T_1763, UInt<1>(0h0))
when _T_1764 :
node _T_1765 = eq(_T_1762, UInt<1>(0h0))
when _T_1765 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_1762, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_1766 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1767 = asUInt(reset)
node _T_1768 = eq(_T_1767, UInt<1>(0h0))
when _T_1768 :
node _T_1769 = eq(_T_1766, UInt<1>(0h0))
when _T_1769 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_1766, UInt<1>(0h1), "") : assert_52
node _source_ok_T_58 = eq(io.in.d.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0)
node _source_ok_T_59 = shr(io.in.d.bits.source, 2)
node _source_ok_T_60 = eq(_source_ok_T_59, UInt<1>(0h0))
node _source_ok_T_61 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_62 = and(_source_ok_T_60, _source_ok_T_61)
node _source_ok_T_63 = leq(source_ok_uncommonBits_4, UInt<2>(0h3))
node _source_ok_T_64 = and(_source_ok_T_62, _source_ok_T_63)
node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0)
node _source_ok_T_65 = shr(io.in.d.bits.source, 2)
node _source_ok_T_66 = eq(_source_ok_T_65, UInt<1>(0h1))
node _source_ok_T_67 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_68 = and(_source_ok_T_66, _source_ok_T_67)
node _source_ok_T_69 = leq(source_ok_uncommonBits_5, UInt<2>(0h3))
node _source_ok_T_70 = and(_source_ok_T_68, _source_ok_T_69)
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0)
node _source_ok_T_71 = shr(io.in.d.bits.source, 2)
node _source_ok_T_72 = eq(_source_ok_T_71, UInt<2>(0h2))
node _source_ok_T_73 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_74 = and(_source_ok_T_72, _source_ok_T_73)
node _source_ok_T_75 = leq(source_ok_uncommonBits_6, UInt<2>(0h3))
node _source_ok_T_76 = and(_source_ok_T_74, _source_ok_T_75)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_77 = shr(io.in.d.bits.source, 2)
node _source_ok_T_78 = eq(_source_ok_T_77, UInt<2>(0h3))
node _source_ok_T_79 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_80 = and(_source_ok_T_78, _source_ok_T_79)
node _source_ok_T_81 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_82 = and(_source_ok_T_80, _source_ok_T_81)
node _source_ok_T_83 = eq(io.in.d.bits.source, UInt<6>(0h24))
node _source_ok_T_84 = eq(io.in.d.bits.source, UInt<6>(0h25))
node _source_ok_T_85 = eq(io.in.d.bits.source, UInt<6>(0h26))
node _source_ok_T_86 = eq(io.in.d.bits.source, UInt<6>(0h2e))
node _source_ok_T_87 = eq(io.in.d.bits.source, UInt<6>(0h2f))
node _source_ok_T_88 = eq(io.in.d.bits.source, UInt<6>(0h2c))
node _source_ok_T_89 = eq(io.in.d.bits.source, UInt<6>(0h2d))
node _source_ok_T_90 = eq(io.in.d.bits.source, UInt<6>(0h2a))
node _source_ok_T_91 = eq(io.in.d.bits.source, UInt<6>(0h2b))
node _source_ok_T_92 = eq(io.in.d.bits.source, UInt<6>(0h28))
node _source_ok_T_93 = eq(io.in.d.bits.source, UInt<6>(0h29))
node _source_ok_T_94 = eq(io.in.d.bits.source, UInt<6>(0h22))
node _source_ok_T_95 = eq(io.in.d.bits.source, UInt<6>(0h20))
node _source_ok_T_96 = eq(io.in.d.bits.source, UInt<6>(0h21))
node _source_ok_T_97 = eq(io.in.d.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE_1 : UInt<1>[20]
connect _source_ok_WIRE_1[0], _source_ok_T_58
connect _source_ok_WIRE_1[1], _source_ok_T_64
connect _source_ok_WIRE_1[2], _source_ok_T_70
connect _source_ok_WIRE_1[3], _source_ok_T_76
connect _source_ok_WIRE_1[4], _source_ok_T_82
connect _source_ok_WIRE_1[5], _source_ok_T_83
connect _source_ok_WIRE_1[6], _source_ok_T_84
connect _source_ok_WIRE_1[7], _source_ok_T_85
connect _source_ok_WIRE_1[8], _source_ok_T_86
connect _source_ok_WIRE_1[9], _source_ok_T_87
connect _source_ok_WIRE_1[10], _source_ok_T_88
connect _source_ok_WIRE_1[11], _source_ok_T_89
connect _source_ok_WIRE_1[12], _source_ok_T_90
connect _source_ok_WIRE_1[13], _source_ok_T_91
connect _source_ok_WIRE_1[14], _source_ok_T_92
connect _source_ok_WIRE_1[15], _source_ok_T_93
connect _source_ok_WIRE_1[16], _source_ok_T_94
connect _source_ok_WIRE_1[17], _source_ok_T_95
connect _source_ok_WIRE_1[18], _source_ok_T_96
connect _source_ok_WIRE_1[19], _source_ok_T_97
node _source_ok_T_98 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_99 = or(_source_ok_T_98, _source_ok_WIRE_1[2])
node _source_ok_T_100 = or(_source_ok_T_99, _source_ok_WIRE_1[3])
node _source_ok_T_101 = or(_source_ok_T_100, _source_ok_WIRE_1[4])
node _source_ok_T_102 = or(_source_ok_T_101, _source_ok_WIRE_1[5])
node _source_ok_T_103 = or(_source_ok_T_102, _source_ok_WIRE_1[6])
node _source_ok_T_104 = or(_source_ok_T_103, _source_ok_WIRE_1[7])
node _source_ok_T_105 = or(_source_ok_T_104, _source_ok_WIRE_1[8])
node _source_ok_T_106 = or(_source_ok_T_105, _source_ok_WIRE_1[9])
node _source_ok_T_107 = or(_source_ok_T_106, _source_ok_WIRE_1[10])
node _source_ok_T_108 = or(_source_ok_T_107, _source_ok_WIRE_1[11])
node _source_ok_T_109 = or(_source_ok_T_108, _source_ok_WIRE_1[12])
node _source_ok_T_110 = or(_source_ok_T_109, _source_ok_WIRE_1[13])
node _source_ok_T_111 = or(_source_ok_T_110, _source_ok_WIRE_1[14])
node _source_ok_T_112 = or(_source_ok_T_111, _source_ok_WIRE_1[15])
node _source_ok_T_113 = or(_source_ok_T_112, _source_ok_WIRE_1[16])
node _source_ok_T_114 = or(_source_ok_T_113, _source_ok_WIRE_1[17])
node _source_ok_T_115 = or(_source_ok_T_114, _source_ok_WIRE_1[18])
node source_ok_1 = or(_source_ok_T_115, _source_ok_WIRE_1[19])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_1770 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1770 :
node _T_1771 = asUInt(reset)
node _T_1772 = eq(_T_1771, UInt<1>(0h0))
when _T_1772 :
node _T_1773 = eq(source_ok_1, UInt<1>(0h0))
when _T_1773 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_1774 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1775 = asUInt(reset)
node _T_1776 = eq(_T_1775, UInt<1>(0h0))
when _T_1776 :
node _T_1777 = eq(_T_1774, UInt<1>(0h0))
when _T_1777 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1774, UInt<1>(0h1), "") : assert_54
node _T_1778 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1779 = asUInt(reset)
node _T_1780 = eq(_T_1779, UInt<1>(0h0))
when _T_1780 :
node _T_1781 = eq(_T_1778, UInt<1>(0h0))
when _T_1781 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1778, UInt<1>(0h1), "") : assert_55
node _T_1782 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1783 = asUInt(reset)
node _T_1784 = eq(_T_1783, UInt<1>(0h0))
when _T_1784 :
node _T_1785 = eq(_T_1782, UInt<1>(0h0))
when _T_1785 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1782, UInt<1>(0h1), "") : assert_56
node _T_1786 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1787 = asUInt(reset)
node _T_1788 = eq(_T_1787, UInt<1>(0h0))
when _T_1788 :
node _T_1789 = eq(_T_1786, UInt<1>(0h0))
when _T_1789 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1786, UInt<1>(0h1), "") : assert_57
node _T_1790 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1790 :
node _T_1791 = asUInt(reset)
node _T_1792 = eq(_T_1791, UInt<1>(0h0))
when _T_1792 :
node _T_1793 = eq(source_ok_1, UInt<1>(0h0))
when _T_1793 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1794 = asUInt(reset)
node _T_1795 = eq(_T_1794, UInt<1>(0h0))
when _T_1795 :
node _T_1796 = eq(sink_ok, UInt<1>(0h0))
when _T_1796 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1797 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1798 = asUInt(reset)
node _T_1799 = eq(_T_1798, UInt<1>(0h0))
when _T_1799 :
node _T_1800 = eq(_T_1797, UInt<1>(0h0))
when _T_1800 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1797, UInt<1>(0h1), "") : assert_60
node _T_1801 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1802 = asUInt(reset)
node _T_1803 = eq(_T_1802, UInt<1>(0h0))
when _T_1803 :
node _T_1804 = eq(_T_1801, UInt<1>(0h0))
when _T_1804 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1801, UInt<1>(0h1), "") : assert_61
node _T_1805 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1806 = asUInt(reset)
node _T_1807 = eq(_T_1806, UInt<1>(0h0))
when _T_1807 :
node _T_1808 = eq(_T_1805, UInt<1>(0h0))
when _T_1808 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1805, UInt<1>(0h1), "") : assert_62
node _T_1809 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1810 = asUInt(reset)
node _T_1811 = eq(_T_1810, UInt<1>(0h0))
when _T_1811 :
node _T_1812 = eq(_T_1809, UInt<1>(0h0))
when _T_1812 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1809, UInt<1>(0h1), "") : assert_63
node _T_1813 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1814 = or(UInt<1>(0h1), _T_1813)
node _T_1815 = asUInt(reset)
node _T_1816 = eq(_T_1815, UInt<1>(0h0))
when _T_1816 :
node _T_1817 = eq(_T_1814, UInt<1>(0h0))
when _T_1817 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1814, UInt<1>(0h1), "") : assert_64
node _T_1818 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1818 :
node _T_1819 = asUInt(reset)
node _T_1820 = eq(_T_1819, UInt<1>(0h0))
when _T_1820 :
node _T_1821 = eq(source_ok_1, UInt<1>(0h0))
when _T_1821 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1822 = asUInt(reset)
node _T_1823 = eq(_T_1822, UInt<1>(0h0))
when _T_1823 :
node _T_1824 = eq(sink_ok, UInt<1>(0h0))
when _T_1824 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1825 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1826 = asUInt(reset)
node _T_1827 = eq(_T_1826, UInt<1>(0h0))
when _T_1827 :
node _T_1828 = eq(_T_1825, UInt<1>(0h0))
when _T_1828 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1825, UInt<1>(0h1), "") : assert_67
node _T_1829 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1830 = asUInt(reset)
node _T_1831 = eq(_T_1830, UInt<1>(0h0))
when _T_1831 :
node _T_1832 = eq(_T_1829, UInt<1>(0h0))
when _T_1832 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1829, UInt<1>(0h1), "") : assert_68
node _T_1833 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1834 = asUInt(reset)
node _T_1835 = eq(_T_1834, UInt<1>(0h0))
when _T_1835 :
node _T_1836 = eq(_T_1833, UInt<1>(0h0))
when _T_1836 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1833, UInt<1>(0h1), "") : assert_69
node _T_1837 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1838 = or(_T_1837, io.in.d.bits.corrupt)
node _T_1839 = asUInt(reset)
node _T_1840 = eq(_T_1839, UInt<1>(0h0))
when _T_1840 :
node _T_1841 = eq(_T_1838, UInt<1>(0h0))
when _T_1841 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1838, UInt<1>(0h1), "") : assert_70
node _T_1842 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1843 = or(UInt<1>(0h1), _T_1842)
node _T_1844 = asUInt(reset)
node _T_1845 = eq(_T_1844, UInt<1>(0h0))
when _T_1845 :
node _T_1846 = eq(_T_1843, UInt<1>(0h0))
when _T_1846 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1843, UInt<1>(0h1), "") : assert_71
node _T_1847 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1847 :
node _T_1848 = asUInt(reset)
node _T_1849 = eq(_T_1848, UInt<1>(0h0))
when _T_1849 :
node _T_1850 = eq(source_ok_1, UInt<1>(0h0))
when _T_1850 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1851 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1852 = asUInt(reset)
node _T_1853 = eq(_T_1852, UInt<1>(0h0))
when _T_1853 :
node _T_1854 = eq(_T_1851, UInt<1>(0h0))
when _T_1854 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1851, UInt<1>(0h1), "") : assert_73
node _T_1855 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1856 = asUInt(reset)
node _T_1857 = eq(_T_1856, UInt<1>(0h0))
when _T_1857 :
node _T_1858 = eq(_T_1855, UInt<1>(0h0))
when _T_1858 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1855, UInt<1>(0h1), "") : assert_74
node _T_1859 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1860 = or(UInt<1>(0h1), _T_1859)
node _T_1861 = asUInt(reset)
node _T_1862 = eq(_T_1861, UInt<1>(0h0))
when _T_1862 :
node _T_1863 = eq(_T_1860, UInt<1>(0h0))
when _T_1863 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1860, UInt<1>(0h1), "") : assert_75
node _T_1864 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1864 :
node _T_1865 = asUInt(reset)
node _T_1866 = eq(_T_1865, UInt<1>(0h0))
when _T_1866 :
node _T_1867 = eq(source_ok_1, UInt<1>(0h0))
when _T_1867 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1868 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1869 = asUInt(reset)
node _T_1870 = eq(_T_1869, UInt<1>(0h0))
when _T_1870 :
node _T_1871 = eq(_T_1868, UInt<1>(0h0))
when _T_1871 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1868, UInt<1>(0h1), "") : assert_77
node _T_1872 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1873 = or(_T_1872, io.in.d.bits.corrupt)
node _T_1874 = asUInt(reset)
node _T_1875 = eq(_T_1874, UInt<1>(0h0))
when _T_1875 :
node _T_1876 = eq(_T_1873, UInt<1>(0h0))
when _T_1876 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1873, UInt<1>(0h1), "") : assert_78
node _T_1877 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1878 = or(UInt<1>(0h1), _T_1877)
node _T_1879 = asUInt(reset)
node _T_1880 = eq(_T_1879, UInt<1>(0h0))
when _T_1880 :
node _T_1881 = eq(_T_1878, UInt<1>(0h0))
when _T_1881 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1878, UInt<1>(0h1), "") : assert_79
node _T_1882 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1882 :
node _T_1883 = asUInt(reset)
node _T_1884 = eq(_T_1883, UInt<1>(0h0))
when _T_1884 :
node _T_1885 = eq(source_ok_1, UInt<1>(0h0))
when _T_1885 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1886 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1887 = asUInt(reset)
node _T_1888 = eq(_T_1887, UInt<1>(0h0))
when _T_1888 :
node _T_1889 = eq(_T_1886, UInt<1>(0h0))
when _T_1889 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1886, UInt<1>(0h1), "") : assert_81
node _T_1890 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1891 = asUInt(reset)
node _T_1892 = eq(_T_1891, UInt<1>(0h0))
when _T_1892 :
node _T_1893 = eq(_T_1890, UInt<1>(0h0))
when _T_1893 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1890, UInt<1>(0h1), "") : assert_82
node _T_1894 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1895 = or(UInt<1>(0h1), _T_1894)
node _T_1896 = asUInt(reset)
node _T_1897 = eq(_T_1896, UInt<1>(0h0))
when _T_1897 :
node _T_1898 = eq(_T_1895, UInt<1>(0h0))
when _T_1898 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1895, UInt<1>(0h1), "") : assert_83
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.mask, UInt<8>(0h0)
connect _WIRE_4.bits.address, UInt<29>(0h0)
connect _WIRE_4.bits.source, UInt<7>(0h0)
connect _WIRE_4.bits.size, UInt<4>(0h0)
connect _WIRE_4.bits.param, UInt<2>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1899 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1900 = asUInt(reset)
node _T_1901 = eq(_T_1900, UInt<1>(0h0))
when _T_1901 :
node _T_1902 = eq(_T_1899, UInt<1>(0h0))
when _T_1902 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1899, UInt<1>(0h1), "") : assert_84
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<29>(0h0)
connect _WIRE_6.bits.source, UInt<7>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1903 = eq(_WIRE_7.valid, UInt<1>(0h0))
node _T_1904 = asUInt(reset)
node _T_1905 = eq(_T_1904, UInt<1>(0h0))
when _T_1905 :
node _T_1906 = eq(_T_1903, UInt<1>(0h0))
when _T_1906 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1903, UInt<1>(0h1), "") : assert_85
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_8.bits.sink, UInt<1>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1907 = eq(_WIRE_9.valid, UInt<1>(0h0))
node _T_1908 = asUInt(reset)
node _T_1909 = eq(_T_1908, UInt<1>(0h0))
when _T_1909 :
node _T_1910 = eq(_T_1907, UInt<1>(0h0))
when _T_1910 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1907, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1911 = eq(a_first, UInt<1>(0h0))
node _T_1912 = and(io.in.a.valid, _T_1911)
when _T_1912 :
node _T_1913 = eq(io.in.a.bits.opcode, opcode)
node _T_1914 = asUInt(reset)
node _T_1915 = eq(_T_1914, UInt<1>(0h0))
when _T_1915 :
node _T_1916 = eq(_T_1913, UInt<1>(0h0))
when _T_1916 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1913, UInt<1>(0h1), "") : assert_87
node _T_1917 = eq(io.in.a.bits.param, param)
node _T_1918 = asUInt(reset)
node _T_1919 = eq(_T_1918, UInt<1>(0h0))
when _T_1919 :
node _T_1920 = eq(_T_1917, UInt<1>(0h0))
when _T_1920 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1917, UInt<1>(0h1), "") : assert_88
node _T_1921 = eq(io.in.a.bits.size, size)
node _T_1922 = asUInt(reset)
node _T_1923 = eq(_T_1922, UInt<1>(0h0))
when _T_1923 :
node _T_1924 = eq(_T_1921, UInt<1>(0h0))
when _T_1924 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1921, UInt<1>(0h1), "") : assert_89
node _T_1925 = eq(io.in.a.bits.source, source)
node _T_1926 = asUInt(reset)
node _T_1927 = eq(_T_1926, UInt<1>(0h0))
when _T_1927 :
node _T_1928 = eq(_T_1925, UInt<1>(0h0))
when _T_1928 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1925, UInt<1>(0h1), "") : assert_90
node _T_1929 = eq(io.in.a.bits.address, address)
node _T_1930 = asUInt(reset)
node _T_1931 = eq(_T_1930, UInt<1>(0h0))
when _T_1931 :
node _T_1932 = eq(_T_1929, UInt<1>(0h0))
when _T_1932 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1929, UInt<1>(0h1), "") : assert_91
node _T_1933 = and(io.in.a.ready, io.in.a.valid)
node _T_1934 = and(_T_1933, a_first)
when _T_1934 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1935 = eq(d_first, UInt<1>(0h0))
node _T_1936 = and(io.in.d.valid, _T_1935)
when _T_1936 :
node _T_1937 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1938 = asUInt(reset)
node _T_1939 = eq(_T_1938, UInt<1>(0h0))
when _T_1939 :
node _T_1940 = eq(_T_1937, UInt<1>(0h0))
when _T_1940 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1937, UInt<1>(0h1), "") : assert_92
node _T_1941 = eq(io.in.d.bits.param, param_1)
node _T_1942 = asUInt(reset)
node _T_1943 = eq(_T_1942, UInt<1>(0h0))
when _T_1943 :
node _T_1944 = eq(_T_1941, UInt<1>(0h0))
when _T_1944 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1941, UInt<1>(0h1), "") : assert_93
node _T_1945 = eq(io.in.d.bits.size, size_1)
node _T_1946 = asUInt(reset)
node _T_1947 = eq(_T_1946, UInt<1>(0h0))
when _T_1947 :
node _T_1948 = eq(_T_1945, UInt<1>(0h0))
when _T_1948 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1945, UInt<1>(0h1), "") : assert_94
node _T_1949 = eq(io.in.d.bits.source, source_1)
node _T_1950 = asUInt(reset)
node _T_1951 = eq(_T_1950, UInt<1>(0h0))
when _T_1951 :
node _T_1952 = eq(_T_1949, UInt<1>(0h0))
when _T_1952 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1949, UInt<1>(0h1), "") : assert_95
node _T_1953 = eq(io.in.d.bits.sink, sink)
node _T_1954 = asUInt(reset)
node _T_1955 = eq(_T_1954, UInt<1>(0h0))
when _T_1955 :
node _T_1956 = eq(_T_1953, UInt<1>(0h0))
when _T_1956 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1953, UInt<1>(0h1), "") : assert_96
node _T_1957 = eq(io.in.d.bits.denied, denied)
node _T_1958 = asUInt(reset)
node _T_1959 = eq(_T_1958, UInt<1>(0h0))
when _T_1959 :
node _T_1960 = eq(_T_1957, UInt<1>(0h0))
when _T_1960 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1957, UInt<1>(0h1), "") : assert_97
node _T_1961 = and(io.in.d.ready, io.in.d.valid)
node _T_1962 = and(_T_1961, d_first)
when _T_1962 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes : UInt<520>, clock, reset, UInt<520>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<65>
connect a_set, UInt<65>(0h0)
wire a_set_wo_ready : UInt<65>
connect a_set_wo_ready, UInt<65>(0h0)
wire a_opcodes_set : UInt<260>
connect a_opcodes_set, UInt<260>(0h0)
wire a_sizes_set : UInt<520>
connect a_sizes_set, UInt<520>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<8>
connect a_size_lookup, UInt<8>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<5>
connect a_sizes_set_interm, UInt<5>(0h0)
node _T_1963 = and(io.in.a.valid, a_first_1)
node _T_1964 = and(_T_1963, UInt<1>(0h1))
when _T_1964 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1965 = and(io.in.a.ready, io.in.a.valid)
node _T_1966 = and(_T_1965, a_first_1)
node _T_1967 = and(_T_1966, UInt<1>(0h1))
when _T_1967 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1968 = dshr(inflight, io.in.a.bits.source)
node _T_1969 = bits(_T_1968, 0, 0)
node _T_1970 = eq(_T_1969, UInt<1>(0h0))
node _T_1971 = asUInt(reset)
node _T_1972 = eq(_T_1971, UInt<1>(0h0))
when _T_1972 :
node _T_1973 = eq(_T_1970, UInt<1>(0h0))
when _T_1973 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1970, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<65>
connect d_clr, UInt<65>(0h0)
wire d_clr_wo_ready : UInt<65>
connect d_clr_wo_ready, UInt<65>(0h0)
wire d_opcodes_clr : UInt<260>
connect d_opcodes_clr, UInt<260>(0h0)
wire d_sizes_clr : UInt<520>
connect d_sizes_clr, UInt<520>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1974 = and(io.in.d.valid, d_first_1)
node _T_1975 = and(_T_1974, UInt<1>(0h1))
node _T_1976 = eq(d_release_ack, UInt<1>(0h0))
node _T_1977 = and(_T_1975, _T_1976)
when _T_1977 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1978 = and(io.in.d.ready, io.in.d.valid)
node _T_1979 = and(_T_1978, d_first_1)
node _T_1980 = and(_T_1979, UInt<1>(0h1))
node _T_1981 = eq(d_release_ack, UInt<1>(0h0))
node _T_1982 = and(_T_1980, _T_1981)
when _T_1982 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1983 = and(io.in.d.valid, d_first_1)
node _T_1984 = and(_T_1983, UInt<1>(0h1))
node _T_1985 = eq(d_release_ack, UInt<1>(0h0))
node _T_1986 = and(_T_1984, _T_1985)
when _T_1986 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1987 = dshr(inflight, io.in.d.bits.source)
node _T_1988 = bits(_T_1987, 0, 0)
node _T_1989 = or(_T_1988, same_cycle_resp)
node _T_1990 = asUInt(reset)
node _T_1991 = eq(_T_1990, UInt<1>(0h0))
when _T_1991 :
node _T_1992 = eq(_T_1989, UInt<1>(0h0))
when _T_1992 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1989, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1993 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1994 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1995 = or(_T_1993, _T_1994)
node _T_1996 = asUInt(reset)
node _T_1997 = eq(_T_1996, UInt<1>(0h0))
when _T_1997 :
node _T_1998 = eq(_T_1995, UInt<1>(0h0))
when _T_1998 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1995, UInt<1>(0h1), "") : assert_100
node _T_1999 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_2000 = asUInt(reset)
node _T_2001 = eq(_T_2000, UInt<1>(0h0))
when _T_2001 :
node _T_2002 = eq(_T_1999, UInt<1>(0h0))
when _T_2002 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1999, UInt<1>(0h1), "") : assert_101
else :
node _T_2003 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_2004 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_2005 = or(_T_2003, _T_2004)
node _T_2006 = asUInt(reset)
node _T_2007 = eq(_T_2006, UInt<1>(0h0))
when _T_2007 :
node _T_2008 = eq(_T_2005, UInt<1>(0h0))
when _T_2008 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_2005, UInt<1>(0h1), "") : assert_102
node _T_2009 = eq(io.in.d.bits.size, a_size_lookup)
node _T_2010 = asUInt(reset)
node _T_2011 = eq(_T_2010, UInt<1>(0h0))
when _T_2011 :
node _T_2012 = eq(_T_2009, UInt<1>(0h0))
when _T_2012 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_2009, UInt<1>(0h1), "") : assert_103
node _T_2013 = and(io.in.d.valid, d_first_1)
node _T_2014 = and(_T_2013, a_first_1)
node _T_2015 = and(_T_2014, io.in.a.valid)
node _T_2016 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_2017 = and(_T_2015, _T_2016)
node _T_2018 = eq(d_release_ack, UInt<1>(0h0))
node _T_2019 = and(_T_2017, _T_2018)
when _T_2019 :
node _T_2020 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_2021 = or(_T_2020, io.in.a.ready)
node _T_2022 = asUInt(reset)
node _T_2023 = eq(_T_2022, UInt<1>(0h0))
when _T_2023 :
node _T_2024 = eq(_T_2021, UInt<1>(0h0))
when _T_2024 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_2021, UInt<1>(0h1), "") : assert_104
node _T_2025 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_2026 = orr(a_set_wo_ready)
node _T_2027 = eq(_T_2026, UInt<1>(0h0))
node _T_2028 = or(_T_2025, _T_2027)
node _T_2029 = asUInt(reset)
node _T_2030 = eq(_T_2029, UInt<1>(0h0))
when _T_2030 :
node _T_2031 = eq(_T_2028, UInt<1>(0h0))
when _T_2031 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_2028, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_56
node _T_2032 = orr(inflight)
node _T_2033 = eq(_T_2032, UInt<1>(0h0))
node _T_2034 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_2035 = or(_T_2033, _T_2034)
node _T_2036 = lt(watchdog, plusarg_reader.out)
node _T_2037 = or(_T_2035, _T_2036)
node _T_2038 = asUInt(reset)
node _T_2039 = eq(_T_2038, UInt<1>(0h0))
when _T_2039 :
node _T_2040 = eq(_T_2037, UInt<1>(0h0))
when _T_2040 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_2037, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_2041 = and(io.in.a.ready, io.in.a.valid)
node _T_2042 = and(io.in.d.ready, io.in.d.valid)
node _T_2043 = or(_T_2041, _T_2042)
when _T_2043 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes_1 : UInt<520>, clock, reset, UInt<520>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<29>(0h0)
connect _c_first_WIRE.bits.source, UInt<7>(0h0)
connect _c_first_WIRE.bits.size, UInt<4>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<29>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<65>
connect c_set, UInt<65>(0h0)
wire c_set_wo_ready : UInt<65>
connect c_set_wo_ready, UInt<65>(0h0)
wire c_opcodes_set : UInt<260>
connect c_opcodes_set, UInt<260>(0h0)
wire c_sizes_set : UInt<520>
connect c_sizes_set, UInt<520>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<8>
connect c_size_lookup, UInt<8>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<5>
connect c_sizes_set_interm, UInt<5>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<29>(0h0)
connect _WIRE_10.bits.source, UInt<7>(0h0)
connect _WIRE_10.bits.size, UInt<4>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_2044 = and(_WIRE_11.valid, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<29>(0h0)
connect _WIRE_12.bits.source, UInt<7>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_2045 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_2046 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_2047 = and(_T_2045, _T_2046)
node _T_2048 = and(_T_2044, _T_2047)
when _T_2048 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<29>(0h0)
connect _WIRE_14.bits.source, UInt<7>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_2049 = and(_WIRE_15.ready, _WIRE_15.valid)
node _T_2050 = and(_T_2049, c_first)
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<29>(0h0)
connect _WIRE_16.bits.source, UInt<7>(0h0)
connect _WIRE_16.bits.size, UInt<4>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_2051 = bits(_WIRE_17.bits.opcode, 2, 2)
node _T_2052 = bits(_WIRE_17.bits.opcode, 1, 1)
node _T_2053 = and(_T_2051, _T_2052)
node _T_2054 = and(_T_2050, _T_2053)
when _T_2054 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<29>(0h0)
connect _WIRE_18.bits.source, UInt<7>(0h0)
connect _WIRE_18.bits.size, UInt<4>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_2055 = dshr(inflight_1, _WIRE_19.bits.source)
node _T_2056 = bits(_T_2055, 0, 0)
node _T_2057 = eq(_T_2056, UInt<1>(0h0))
node _T_2058 = asUInt(reset)
node _T_2059 = eq(_T_2058, UInt<1>(0h0))
when _T_2059 :
node _T_2060 = eq(_T_2057, UInt<1>(0h0))
when _T_2060 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_2057, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<65>
connect d_clr_1, UInt<65>(0h0)
wire d_clr_wo_ready_1 : UInt<65>
connect d_clr_wo_ready_1, UInt<65>(0h0)
wire d_opcodes_clr_1 : UInt<260>
connect d_opcodes_clr_1, UInt<260>(0h0)
wire d_sizes_clr_1 : UInt<520>
connect d_sizes_clr_1, UInt<520>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_2061 = and(io.in.d.valid, d_first_2)
node _T_2062 = and(_T_2061, UInt<1>(0h1))
node _T_2063 = and(_T_2062, d_release_ack_1)
when _T_2063 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_2064 = and(io.in.d.ready, io.in.d.valid)
node _T_2065 = and(_T_2064, d_first_2)
node _T_2066 = and(_T_2065, UInt<1>(0h1))
node _T_2067 = and(_T_2066, d_release_ack_1)
when _T_2067 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_2068 = and(io.in.d.valid, d_first_2)
node _T_2069 = and(_T_2068, UInt<1>(0h1))
node _T_2070 = and(_T_2069, d_release_ack_1)
when _T_2070 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_2071 = dshr(inflight_1, io.in.d.bits.source)
node _T_2072 = bits(_T_2071, 0, 0)
node _T_2073 = or(_T_2072, same_cycle_resp_1)
node _T_2074 = asUInt(reset)
node _T_2075 = eq(_T_2074, UInt<1>(0h0))
when _T_2075 :
node _T_2076 = eq(_T_2073, UInt<1>(0h0))
when _T_2076 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_2073, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<29>(0h0)
connect _WIRE_20.bits.source, UInt<7>(0h0)
connect _WIRE_20.bits.size, UInt<4>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_2077 = eq(io.in.d.bits.size, _WIRE_21.bits.size)
node _T_2078 = asUInt(reset)
node _T_2079 = eq(_T_2078, UInt<1>(0h0))
when _T_2079 :
node _T_2080 = eq(_T_2077, UInt<1>(0h0))
when _T_2080 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_2077, UInt<1>(0h1), "") : assert_109
else :
node _T_2081 = eq(io.in.d.bits.size, c_size_lookup)
node _T_2082 = asUInt(reset)
node _T_2083 = eq(_T_2082, UInt<1>(0h0))
when _T_2083 :
node _T_2084 = eq(_T_2081, UInt<1>(0h0))
when _T_2084 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_2081, UInt<1>(0h1), "") : assert_110
node _T_2085 = and(io.in.d.valid, d_first_2)
node _T_2086 = and(_T_2085, c_first)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<29>(0h0)
connect _WIRE_22.bits.source, UInt<7>(0h0)
connect _WIRE_22.bits.size, UInt<4>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_2087 = and(_T_2086, _WIRE_23.valid)
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<29>(0h0)
connect _WIRE_24.bits.source, UInt<7>(0h0)
connect _WIRE_24.bits.size, UInt<4>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_2088 = eq(_WIRE_25.bits.source, io.in.d.bits.source)
node _T_2089 = and(_T_2087, _T_2088)
node _T_2090 = and(_T_2089, d_release_ack_1)
node _T_2091 = eq(c_probe_ack, UInt<1>(0h0))
node _T_2092 = and(_T_2090, _T_2091)
when _T_2092 :
node _T_2093 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<64>(0h0)
connect _WIRE_26.bits.address, UInt<29>(0h0)
connect _WIRE_26.bits.source, UInt<7>(0h0)
connect _WIRE_26.bits.size, UInt<4>(0h0)
connect _WIRE_26.bits.param, UInt<3>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
node _T_2094 = or(_T_2093, _WIRE_27.ready)
node _T_2095 = asUInt(reset)
node _T_2096 = eq(_T_2095, UInt<1>(0h0))
when _T_2096 :
node _T_2097 = eq(_T_2094, UInt<1>(0h0))
when _T_2097 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_2094, UInt<1>(0h1), "") : assert_111
node _T_2098 = orr(c_set_wo_ready)
when _T_2098 :
node _T_2099 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_2100 = asUInt(reset)
node _T_2101 = eq(_T_2100, UInt<1>(0h0))
when _T_2101 :
node _T_2102 = eq(_T_2099, UInt<1>(0h0))
when _T_2102 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_2099, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_57
node _T_2103 = orr(inflight_1)
node _T_2104 = eq(_T_2103, UInt<1>(0h0))
node _T_2105 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_2106 = or(_T_2104, _T_2105)
node _T_2107 = lt(watchdog_1, plusarg_reader_1.out)
node _T_2108 = or(_T_2106, _T_2107)
node _T_2109 = asUInt(reset)
node _T_2110 = eq(_T_2109, UInt<1>(0h0))
when _T_2110 :
node _T_2111 = eq(_T_2108, UInt<1>(0h0))
when _T_2111 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_2108, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<64>(0h0)
connect _WIRE_28.bits.address, UInt<29>(0h0)
connect _WIRE_28.bits.source, UInt<7>(0h0)
connect _WIRE_28.bits.size, UInt<4>(0h0)
connect _WIRE_28.bits.param, UInt<3>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
node _T_2112 = and(_WIRE_29.ready, _WIRE_29.valid)
node _T_2113 = and(io.in.d.ready, io.in.d.valid)
node _T_2114 = or(_T_2112, _T_2113)
when _T_2114 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_28( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27]
wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_61 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_63 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_67 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_69 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_73 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_75 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_79 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:57:20]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28]
wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [1027:0] _c_sizes_set_T_1 = 1028'h0; // @[Monitor.scala:768:52]
wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79]
wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77]
wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35]
wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35]
wire [519:0] c_sizes_set = 520'h0; // @[Monitor.scala:741:34]
wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34]
wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34]
wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h24; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31]
wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h25; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31]
wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h26; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31]
wire _source_ok_T_28 = io_in_a_bits_source_0 == 7'h2E; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_8 = _source_ok_T_28; // @[Parameters.scala:1138:31]
wire _source_ok_T_29 = io_in_a_bits_source_0 == 7'h2F; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_9 = _source_ok_T_29; // @[Parameters.scala:1138:31]
wire _source_ok_T_30 = io_in_a_bits_source_0 == 7'h2C; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_10 = _source_ok_T_30; // @[Parameters.scala:1138:31]
wire _source_ok_T_31 = io_in_a_bits_source_0 == 7'h2D; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_11 = _source_ok_T_31; // @[Parameters.scala:1138:31]
wire _source_ok_T_32 = io_in_a_bits_source_0 == 7'h2A; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_12 = _source_ok_T_32; // @[Parameters.scala:1138:31]
wire _source_ok_T_33 = io_in_a_bits_source_0 == 7'h2B; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_13 = _source_ok_T_33; // @[Parameters.scala:1138:31]
wire _source_ok_T_34 = io_in_a_bits_source_0 == 7'h28; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_14 = _source_ok_T_34; // @[Parameters.scala:1138:31]
wire _source_ok_T_35 = io_in_a_bits_source_0 == 7'h29; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_15 = _source_ok_T_35; // @[Parameters.scala:1138:31]
wire _source_ok_T_36 = io_in_a_bits_source_0 == 7'h22; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_16 = _source_ok_T_36; // @[Parameters.scala:1138:31]
wire _source_ok_T_37 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_17 = _source_ok_T_37; // @[Parameters.scala:1138:31]
wire _source_ok_T_38 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_18 = _source_ok_T_38; // @[Parameters.scala:1138:31]
wire _source_ok_T_39 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_19 = _source_ok_T_39; // @[Parameters.scala:1138:31]
wire _source_ok_T_40 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_41 = _source_ok_T_40 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_42 = _source_ok_T_41 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_43 = _source_ok_T_42 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_44 = _source_ok_T_43 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_45 = _source_ok_T_44 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_46 = _source_ok_T_45 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_47 = _source_ok_T_46 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_48 = _source_ok_T_47 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_49 = _source_ok_T_48 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_50 = _source_ok_T_49 | _source_ok_WIRE_11; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_51 = _source_ok_T_50 | _source_ok_WIRE_12; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_52 = _source_ok_T_51 | _source_ok_WIRE_13; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_53 = _source_ok_T_52 | _source_ok_WIRE_14; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_54 = _source_ok_T_53 | _source_ok_WIRE_15; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_55 = _source_ok_T_54 | _source_ok_WIRE_16; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_56 = _source_ok_T_55 | _source_ok_WIRE_17; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_57 = _source_ok_T_56 | _source_ok_WIRE_18; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_57 | _source_ok_WIRE_19; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [28:0] _is_aligned_T = {17'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_58 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_58; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_59 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_65 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_71 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_77 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_60 = _source_ok_T_59 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_62 = _source_ok_T_60; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_64 = _source_ok_T_62; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_64; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_66 = _source_ok_T_65 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_68 = _source_ok_T_66; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_70 = _source_ok_T_68; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_70; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_72 = _source_ok_T_71 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_74 = _source_ok_T_72; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_76 = _source_ok_T_74; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_76; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_78 = _source_ok_T_77 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_80 = _source_ok_T_78; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_82; // @[Parameters.scala:1138:31]
wire _source_ok_T_83 = io_in_d_bits_source_0 == 7'h24; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_5 = _source_ok_T_83; // @[Parameters.scala:1138:31]
wire _source_ok_T_84 = io_in_d_bits_source_0 == 7'h25; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_6 = _source_ok_T_84; // @[Parameters.scala:1138:31]
wire _source_ok_T_85 = io_in_d_bits_source_0 == 7'h26; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_7 = _source_ok_T_85; // @[Parameters.scala:1138:31]
wire _source_ok_T_86 = io_in_d_bits_source_0 == 7'h2E; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_8 = _source_ok_T_86; // @[Parameters.scala:1138:31]
wire _source_ok_T_87 = io_in_d_bits_source_0 == 7'h2F; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_9 = _source_ok_T_87; // @[Parameters.scala:1138:31]
wire _source_ok_T_88 = io_in_d_bits_source_0 == 7'h2C; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_10 = _source_ok_T_88; // @[Parameters.scala:1138:31]
wire _source_ok_T_89 = io_in_d_bits_source_0 == 7'h2D; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_11 = _source_ok_T_89; // @[Parameters.scala:1138:31]
wire _source_ok_T_90 = io_in_d_bits_source_0 == 7'h2A; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_12 = _source_ok_T_90; // @[Parameters.scala:1138:31]
wire _source_ok_T_91 = io_in_d_bits_source_0 == 7'h2B; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_13 = _source_ok_T_91; // @[Parameters.scala:1138:31]
wire _source_ok_T_92 = io_in_d_bits_source_0 == 7'h28; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_14 = _source_ok_T_92; // @[Parameters.scala:1138:31]
wire _source_ok_T_93 = io_in_d_bits_source_0 == 7'h29; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_15 = _source_ok_T_93; // @[Parameters.scala:1138:31]
wire _source_ok_T_94 = io_in_d_bits_source_0 == 7'h22; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_16 = _source_ok_T_94; // @[Parameters.scala:1138:31]
wire _source_ok_T_95 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_17 = _source_ok_T_95; // @[Parameters.scala:1138:31]
wire _source_ok_T_96 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_18 = _source_ok_T_96; // @[Parameters.scala:1138:31]
wire _source_ok_T_97 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_19 = _source_ok_T_97; // @[Parameters.scala:1138:31]
wire _source_ok_T_98 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_99 = _source_ok_T_98 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_100 = _source_ok_T_99 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_101 = _source_ok_T_100 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_102 = _source_ok_T_101 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_103 = _source_ok_T_102 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_104 = _source_ok_T_103 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_105 = _source_ok_T_104 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_106 = _source_ok_T_105 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_107 = _source_ok_T_106 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_108 = _source_ok_T_107 | _source_ok_WIRE_1_11; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_109 = _source_ok_T_108 | _source_ok_WIRE_1_12; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_110 = _source_ok_T_109 | _source_ok_WIRE_1_13; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_111 = _source_ok_T_110 | _source_ok_WIRE_1_14; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_112 = _source_ok_T_111 | _source_ok_WIRE_1_15; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_113 = _source_ok_T_112 | _source_ok_WIRE_1_16; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_114 = _source_ok_T_113 | _source_ok_WIRE_1_17; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_115 = _source_ok_T_114 | _source_ok_WIRE_1_18; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_115 | _source_ok_WIRE_1_19; // @[Parameters.scala:1138:31, :1139:46]
wire _T_2041 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_2041; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_2041; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [6:0] source; // @[Monitor.scala:390:22]
reg [28:0] address; // @[Monitor.scala:391:22]
wire _T_2114 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_2114; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_2114; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_2114; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [6:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [64:0] inflight; // @[Monitor.scala:614:27]
reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [519:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [64:0] a_set; // @[Monitor.scala:626:34]
wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [519:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [9:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [519:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [519:0] _a_size_lookup_T_6 = {512'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}]
wire [519:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[519:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [127:0] _GEN_3 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35]
wire [127:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1967 = _T_2041 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1967 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1967 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1967 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [9:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1967 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [9:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [1027:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1967 ? _a_sizes_set_T_1[519:0] : 520'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [64:0] d_clr; // @[Monitor.scala:664:34]
wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [519:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_2013 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_2013 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1982 = _T_2114 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1982 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1982 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [1038:0] _d_sizes_clr_T_5 = 1039'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1982 ? _d_sizes_clr_T_5[519:0] : 520'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [519:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [519:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [519:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [64:0] inflight_1; // @[Monitor.scala:726:35]
wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [519:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [519:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [519:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [519:0] _c_size_lookup_T_6 = {512'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}]
wire [519:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[519:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [64:0] d_clr_1; // @[Monitor.scala:774:34]
wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [519:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_2085 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_2085 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_2067 = _T_2114 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_2067 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_2067 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [1038:0] _d_sizes_clr_T_11 = 1039'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_2067 ? _d_sizes_clr_T_11[519:0] : 520'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113]
wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [519:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [519:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module BranchPredictor :
input clock : Clock
input reset : Reset
output io : { flip f0_req : { valid : UInt<1>, bits : { pc : UInt<40>, ghist : { old_history : UInt<64>, current_saw_branch_not_taken : UInt<1>, new_saw_branch_not_taken : UInt<1>, new_saw_branch_taken : UInt<1>, ras_idx : UInt<5>}}}, resp : { f1 : { pc : UInt<40>, preds : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], meta : UInt<120>[1], lhist : UInt<1>[1]}, f2 : { pc : UInt<40>, preds : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], meta : UInt<120>[1], lhist : UInt<1>[1]}, f3 : { pc : UInt<40>, preds : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], meta : UInt<120>[1], lhist : UInt<1>[1]}}, flip f3_fire : UInt<1>, flip update : { valid : UInt<1>, bits : { is_mispredict_update : UInt<1>, is_repair_update : UInt<1>, btb_mispredicts : UInt<4>, pc : UInt<40>, br_mask : UInt<4>, cfi_idx : { valid : UInt<1>, bits : UInt<2>}, cfi_taken : UInt<1>, cfi_mispredicted : UInt<1>, cfi_is_br : UInt<1>, cfi_is_jal : UInt<1>, cfi_is_jalr : UInt<1>, ghist : { old_history : UInt<64>, current_saw_branch_not_taken : UInt<1>, new_saw_branch_not_taken : UInt<1>, new_saw_branch_taken : UInt<1>, ras_idx : UInt<5>}, lhist : UInt<1>[1], target : UInt<40>, meta : UInt<120>[1]}}}
inst banked_predictors_0 of ComposedBranchPredictorBank
connect banked_predictors_0.clock, clock
connect banked_predictors_0.reset, reset
inst banked_lhist_providers_0 of NullLocalBranchPredictorBank
connect banked_lhist_providers_0.clock, clock
connect banked_lhist_providers_0.reset, reset
connect banked_lhist_providers_0.io.f0_valid, io.f0_req.valid
node _banked_lhist_providers_0_io_f0_pc_T = not(io.f0_req.bits.pc)
node _banked_lhist_providers_0_io_f0_pc_T_1 = or(_banked_lhist_providers_0_io_f0_pc_T, UInt<3>(0h7))
node _banked_lhist_providers_0_io_f0_pc_T_2 = not(_banked_lhist_providers_0_io_f0_pc_T_1)
connect banked_lhist_providers_0.io.f0_pc, _banked_lhist_providers_0_io_f0_pc_T_2
connect banked_predictors_0.io.f0_valid, io.f0_req.valid
node _banked_predictors_0_io_f0_pc_T = not(io.f0_req.bits.pc)
node _banked_predictors_0_io_f0_pc_T_1 = or(_banked_predictors_0_io_f0_pc_T, UInt<3>(0h7))
node _banked_predictors_0_io_f0_pc_T_2 = not(_banked_predictors_0_io_f0_pc_T_1)
connect banked_predictors_0.io.f0_pc, _banked_predictors_0_io_f0_pc_T_2
node banked_predictors_0_io_f0_mask_idx = bits(io.f0_req.bits.pc, 2, 1)
node _banked_predictors_0_io_f0_mask_T = dshl(UInt<4>(0hf), banked_predictors_0_io_f0_mask_idx)
connect banked_predictors_0.io.f0_mask, _banked_predictors_0_io_f0_mask_T
reg banked_predictors_0_io_f1_ghist_REG : UInt, clock
connect banked_predictors_0_io_f1_ghist_REG, io.f0_req.bits.ghist.old_history
connect banked_predictors_0.io.f1_ghist, banked_predictors_0_io_f1_ghist_REG
connect banked_predictors_0.io.f1_lhist, banked_lhist_providers_0.io.f1_lhist
wire _banked_predictors_0_io_resp_in_0_WIRE : { f1 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f2 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f3 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4]}
connect _banked_predictors_0_io_resp_in_0_WIRE.f3[0].predicted_pc.bits, UInt<40>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f3[0].predicted_pc.valid, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f3[0].is_jal, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f3[0].is_br, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f3[0].taken, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f3[1].predicted_pc.bits, UInt<40>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f3[1].predicted_pc.valid, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f3[1].is_jal, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f3[1].is_br, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f3[1].taken, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f3[2].predicted_pc.bits, UInt<40>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f3[2].predicted_pc.valid, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f3[2].is_jal, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f3[2].is_br, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f3[2].taken, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f3[3].predicted_pc.bits, UInt<40>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f3[3].predicted_pc.valid, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f3[3].is_jal, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f3[3].is_br, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f3[3].taken, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f2[0].predicted_pc.bits, UInt<40>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f2[0].predicted_pc.valid, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f2[0].is_jal, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f2[0].is_br, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f2[0].taken, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f2[1].predicted_pc.bits, UInt<40>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f2[1].predicted_pc.valid, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f2[1].is_jal, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f2[1].is_br, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f2[1].taken, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f2[2].predicted_pc.bits, UInt<40>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f2[2].predicted_pc.valid, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f2[2].is_jal, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f2[2].is_br, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f2[2].taken, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f2[3].predicted_pc.bits, UInt<40>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f2[3].predicted_pc.valid, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f2[3].is_jal, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f2[3].is_br, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f2[3].taken, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f1[0].predicted_pc.bits, UInt<40>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f1[0].predicted_pc.valid, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f1[0].is_jal, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f1[0].is_br, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f1[0].taken, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f1[1].predicted_pc.bits, UInt<40>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f1[1].predicted_pc.valid, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f1[1].is_jal, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f1[1].is_br, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f1[1].taken, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f1[2].predicted_pc.bits, UInt<40>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f1[2].predicted_pc.valid, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f1[2].is_jal, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f1[2].is_br, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f1[2].taken, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f1[3].predicted_pc.bits, UInt<40>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f1[3].predicted_pc.valid, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f1[3].is_jal, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f1[3].is_br, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f1[3].taken, UInt<1>(0h0)
connect banked_predictors_0.io.resp_in[0].f3[0].predicted_pc.bits, _banked_predictors_0_io_resp_in_0_WIRE.f3[0].predicted_pc.bits
connect banked_predictors_0.io.resp_in[0].f3[0].predicted_pc.valid, _banked_predictors_0_io_resp_in_0_WIRE.f3[0].predicted_pc.valid
connect banked_predictors_0.io.resp_in[0].f3[0].is_jal, _banked_predictors_0_io_resp_in_0_WIRE.f3[0].is_jal
connect banked_predictors_0.io.resp_in[0].f3[0].is_br, _banked_predictors_0_io_resp_in_0_WIRE.f3[0].is_br
connect banked_predictors_0.io.resp_in[0].f3[0].taken, _banked_predictors_0_io_resp_in_0_WIRE.f3[0].taken
connect banked_predictors_0.io.resp_in[0].f3[1].predicted_pc.bits, _banked_predictors_0_io_resp_in_0_WIRE.f3[1].predicted_pc.bits
connect banked_predictors_0.io.resp_in[0].f3[1].predicted_pc.valid, _banked_predictors_0_io_resp_in_0_WIRE.f3[1].predicted_pc.valid
connect banked_predictors_0.io.resp_in[0].f3[1].is_jal, _banked_predictors_0_io_resp_in_0_WIRE.f3[1].is_jal
connect banked_predictors_0.io.resp_in[0].f3[1].is_br, _banked_predictors_0_io_resp_in_0_WIRE.f3[1].is_br
connect banked_predictors_0.io.resp_in[0].f3[1].taken, _banked_predictors_0_io_resp_in_0_WIRE.f3[1].taken
connect banked_predictors_0.io.resp_in[0].f3[2].predicted_pc.bits, _banked_predictors_0_io_resp_in_0_WIRE.f3[2].predicted_pc.bits
connect banked_predictors_0.io.resp_in[0].f3[2].predicted_pc.valid, _banked_predictors_0_io_resp_in_0_WIRE.f3[2].predicted_pc.valid
connect banked_predictors_0.io.resp_in[0].f3[2].is_jal, _banked_predictors_0_io_resp_in_0_WIRE.f3[2].is_jal
connect banked_predictors_0.io.resp_in[0].f3[2].is_br, _banked_predictors_0_io_resp_in_0_WIRE.f3[2].is_br
connect banked_predictors_0.io.resp_in[0].f3[2].taken, _banked_predictors_0_io_resp_in_0_WIRE.f3[2].taken
connect banked_predictors_0.io.resp_in[0].f3[3].predicted_pc.bits, _banked_predictors_0_io_resp_in_0_WIRE.f3[3].predicted_pc.bits
connect banked_predictors_0.io.resp_in[0].f3[3].predicted_pc.valid, _banked_predictors_0_io_resp_in_0_WIRE.f3[3].predicted_pc.valid
connect banked_predictors_0.io.resp_in[0].f3[3].is_jal, _banked_predictors_0_io_resp_in_0_WIRE.f3[3].is_jal
connect banked_predictors_0.io.resp_in[0].f3[3].is_br, _banked_predictors_0_io_resp_in_0_WIRE.f3[3].is_br
connect banked_predictors_0.io.resp_in[0].f3[3].taken, _banked_predictors_0_io_resp_in_0_WIRE.f3[3].taken
connect banked_predictors_0.io.resp_in[0].f2[0].predicted_pc.bits, _banked_predictors_0_io_resp_in_0_WIRE.f2[0].predicted_pc.bits
connect banked_predictors_0.io.resp_in[0].f2[0].predicted_pc.valid, _banked_predictors_0_io_resp_in_0_WIRE.f2[0].predicted_pc.valid
connect banked_predictors_0.io.resp_in[0].f2[0].is_jal, _banked_predictors_0_io_resp_in_0_WIRE.f2[0].is_jal
connect banked_predictors_0.io.resp_in[0].f2[0].is_br, _banked_predictors_0_io_resp_in_0_WIRE.f2[0].is_br
connect banked_predictors_0.io.resp_in[0].f2[0].taken, _banked_predictors_0_io_resp_in_0_WIRE.f2[0].taken
connect banked_predictors_0.io.resp_in[0].f2[1].predicted_pc.bits, _banked_predictors_0_io_resp_in_0_WIRE.f2[1].predicted_pc.bits
connect banked_predictors_0.io.resp_in[0].f2[1].predicted_pc.valid, _banked_predictors_0_io_resp_in_0_WIRE.f2[1].predicted_pc.valid
connect banked_predictors_0.io.resp_in[0].f2[1].is_jal, _banked_predictors_0_io_resp_in_0_WIRE.f2[1].is_jal
connect banked_predictors_0.io.resp_in[0].f2[1].is_br, _banked_predictors_0_io_resp_in_0_WIRE.f2[1].is_br
connect banked_predictors_0.io.resp_in[0].f2[1].taken, _banked_predictors_0_io_resp_in_0_WIRE.f2[1].taken
connect banked_predictors_0.io.resp_in[0].f2[2].predicted_pc.bits, _banked_predictors_0_io_resp_in_0_WIRE.f2[2].predicted_pc.bits
connect banked_predictors_0.io.resp_in[0].f2[2].predicted_pc.valid, _banked_predictors_0_io_resp_in_0_WIRE.f2[2].predicted_pc.valid
connect banked_predictors_0.io.resp_in[0].f2[2].is_jal, _banked_predictors_0_io_resp_in_0_WIRE.f2[2].is_jal
connect banked_predictors_0.io.resp_in[0].f2[2].is_br, _banked_predictors_0_io_resp_in_0_WIRE.f2[2].is_br
connect banked_predictors_0.io.resp_in[0].f2[2].taken, _banked_predictors_0_io_resp_in_0_WIRE.f2[2].taken
connect banked_predictors_0.io.resp_in[0].f2[3].predicted_pc.bits, _banked_predictors_0_io_resp_in_0_WIRE.f2[3].predicted_pc.bits
connect banked_predictors_0.io.resp_in[0].f2[3].predicted_pc.valid, _banked_predictors_0_io_resp_in_0_WIRE.f2[3].predicted_pc.valid
connect banked_predictors_0.io.resp_in[0].f2[3].is_jal, _banked_predictors_0_io_resp_in_0_WIRE.f2[3].is_jal
connect banked_predictors_0.io.resp_in[0].f2[3].is_br, _banked_predictors_0_io_resp_in_0_WIRE.f2[3].is_br
connect banked_predictors_0.io.resp_in[0].f2[3].taken, _banked_predictors_0_io_resp_in_0_WIRE.f2[3].taken
connect banked_predictors_0.io.resp_in[0].f1[0].predicted_pc.bits, _banked_predictors_0_io_resp_in_0_WIRE.f1[0].predicted_pc.bits
connect banked_predictors_0.io.resp_in[0].f1[0].predicted_pc.valid, _banked_predictors_0_io_resp_in_0_WIRE.f1[0].predicted_pc.valid
connect banked_predictors_0.io.resp_in[0].f1[0].is_jal, _banked_predictors_0_io_resp_in_0_WIRE.f1[0].is_jal
connect banked_predictors_0.io.resp_in[0].f1[0].is_br, _banked_predictors_0_io_resp_in_0_WIRE.f1[0].is_br
connect banked_predictors_0.io.resp_in[0].f1[0].taken, _banked_predictors_0_io_resp_in_0_WIRE.f1[0].taken
connect banked_predictors_0.io.resp_in[0].f1[1].predicted_pc.bits, _banked_predictors_0_io_resp_in_0_WIRE.f1[1].predicted_pc.bits
connect banked_predictors_0.io.resp_in[0].f1[1].predicted_pc.valid, _banked_predictors_0_io_resp_in_0_WIRE.f1[1].predicted_pc.valid
connect banked_predictors_0.io.resp_in[0].f1[1].is_jal, _banked_predictors_0_io_resp_in_0_WIRE.f1[1].is_jal
connect banked_predictors_0.io.resp_in[0].f1[1].is_br, _banked_predictors_0_io_resp_in_0_WIRE.f1[1].is_br
connect banked_predictors_0.io.resp_in[0].f1[1].taken, _banked_predictors_0_io_resp_in_0_WIRE.f1[1].taken
connect banked_predictors_0.io.resp_in[0].f1[2].predicted_pc.bits, _banked_predictors_0_io_resp_in_0_WIRE.f1[2].predicted_pc.bits
connect banked_predictors_0.io.resp_in[0].f1[2].predicted_pc.valid, _banked_predictors_0_io_resp_in_0_WIRE.f1[2].predicted_pc.valid
connect banked_predictors_0.io.resp_in[0].f1[2].is_jal, _banked_predictors_0_io_resp_in_0_WIRE.f1[2].is_jal
connect banked_predictors_0.io.resp_in[0].f1[2].is_br, _banked_predictors_0_io_resp_in_0_WIRE.f1[2].is_br
connect banked_predictors_0.io.resp_in[0].f1[2].taken, _banked_predictors_0_io_resp_in_0_WIRE.f1[2].taken
connect banked_predictors_0.io.resp_in[0].f1[3].predicted_pc.bits, _banked_predictors_0_io_resp_in_0_WIRE.f1[3].predicted_pc.bits
connect banked_predictors_0.io.resp_in[0].f1[3].predicted_pc.valid, _banked_predictors_0_io_resp_in_0_WIRE.f1[3].predicted_pc.valid
connect banked_predictors_0.io.resp_in[0].f1[3].is_jal, _banked_predictors_0_io_resp_in_0_WIRE.f1[3].is_jal
connect banked_predictors_0.io.resp_in[0].f1[3].is_br, _banked_predictors_0_io_resp_in_0_WIRE.f1[3].is_br
connect banked_predictors_0.io.resp_in[0].f1[3].taken, _banked_predictors_0_io_resp_in_0_WIRE.f1[3].taken
node _banked_lhist_providers_0_io_f3_taken_br_T = and(banked_predictors_0.io.resp.f3[0].is_br, banked_predictors_0.io.resp.f3[0].predicted_pc.valid)
node _banked_lhist_providers_0_io_f3_taken_br_T_1 = and(_banked_lhist_providers_0_io_f3_taken_br_T, banked_predictors_0.io.resp.f3[0].taken)
node _banked_lhist_providers_0_io_f3_taken_br_T_2 = and(banked_predictors_0.io.resp.f3[1].is_br, banked_predictors_0.io.resp.f3[1].predicted_pc.valid)
node _banked_lhist_providers_0_io_f3_taken_br_T_3 = and(_banked_lhist_providers_0_io_f3_taken_br_T_2, banked_predictors_0.io.resp.f3[1].taken)
node _banked_lhist_providers_0_io_f3_taken_br_T_4 = and(banked_predictors_0.io.resp.f3[2].is_br, banked_predictors_0.io.resp.f3[2].predicted_pc.valid)
node _banked_lhist_providers_0_io_f3_taken_br_T_5 = and(_banked_lhist_providers_0_io_f3_taken_br_T_4, banked_predictors_0.io.resp.f3[2].taken)
node _banked_lhist_providers_0_io_f3_taken_br_T_6 = and(banked_predictors_0.io.resp.f3[3].is_br, banked_predictors_0.io.resp.f3[3].predicted_pc.valid)
node _banked_lhist_providers_0_io_f3_taken_br_T_7 = and(_banked_lhist_providers_0_io_f3_taken_br_T_6, banked_predictors_0.io.resp.f3[3].taken)
node _banked_lhist_providers_0_io_f3_taken_br_T_8 = or(_banked_lhist_providers_0_io_f3_taken_br_T_1, _banked_lhist_providers_0_io_f3_taken_br_T_3)
node _banked_lhist_providers_0_io_f3_taken_br_T_9 = or(_banked_lhist_providers_0_io_f3_taken_br_T_8, _banked_lhist_providers_0_io_f3_taken_br_T_5)
node _banked_lhist_providers_0_io_f3_taken_br_T_10 = or(_banked_lhist_providers_0_io_f3_taken_br_T_9, _banked_lhist_providers_0_io_f3_taken_br_T_7)
connect banked_lhist_providers_0.io.f3_taken_br, _banked_lhist_providers_0_io_f3_taken_br_T_10
connect io.resp.f1.preds, banked_predictors_0.io.resp.f1
connect io.resp.f2.preds, banked_predictors_0.io.resp.f2
connect io.resp.f3.preds, banked_predictors_0.io.resp.f3
connect io.resp.f3.meta[0], banked_predictors_0.io.f3_meta
connect io.resp.f3.lhist[0], banked_lhist_providers_0.io.f3_lhist
connect banked_predictors_0.io.f3_fire, io.f3_fire
connect banked_lhist_providers_0.io.f3_fire, io.f3_fire
reg io_resp_f1_pc_REG : UInt, clock
connect io_resp_f1_pc_REG, io.f0_req.bits.pc
connect io.resp.f1.pc, io_resp_f1_pc_REG
reg io_resp_f2_pc_REG : UInt, clock
connect io_resp_f2_pc_REG, io.resp.f1.pc
connect io.resp.f2.pc, io_resp_f2_pc_REG
reg io_resp_f3_pc_REG : UInt, clock
connect io_resp_f3_pc_REG, io.resp.f2.pc
connect io.resp.f3.pc, io_resp_f3_pc_REG
invalidate io.resp.f1.meta[0]
invalidate io.resp.f2.meta[0]
invalidate io.resp.f1.lhist[0]
invalidate io.resp.f2.lhist[0]
connect banked_predictors_0.io.update.bits.is_mispredict_update, io.update.bits.is_mispredict_update
connect banked_predictors_0.io.update.bits.is_repair_update, io.update.bits.is_repair_update
connect banked_predictors_0.io.update.bits.meta, io.update.bits.meta[0]
connect banked_predictors_0.io.update.bits.lhist, io.update.bits.lhist[0]
connect banked_predictors_0.io.update.bits.cfi_idx.bits, io.update.bits.cfi_idx.bits
connect banked_predictors_0.io.update.bits.cfi_taken, io.update.bits.cfi_taken
connect banked_predictors_0.io.update.bits.cfi_mispredicted, io.update.bits.cfi_mispredicted
connect banked_predictors_0.io.update.bits.cfi_is_br, io.update.bits.cfi_is_br
connect banked_predictors_0.io.update.bits.cfi_is_jal, io.update.bits.cfi_is_jal
connect banked_predictors_0.io.update.bits.cfi_is_jalr, io.update.bits.cfi_is_jalr
connect banked_predictors_0.io.update.bits.target, io.update.bits.target
connect banked_lhist_providers_0.io.update.mispredict, io.update.bits.is_mispredict_update
connect banked_lhist_providers_0.io.update.repair, io.update.bits.is_repair_update
connect banked_lhist_providers_0.io.update.lhist, io.update.bits.lhist[0]
connect banked_predictors_0.io.update.valid, io.update.valid
node _banked_predictors_0_io_update_bits_pc_T = not(io.update.bits.pc)
node _banked_predictors_0_io_update_bits_pc_T_1 = or(_banked_predictors_0_io_update_bits_pc_T, UInt<3>(0h7))
node _banked_predictors_0_io_update_bits_pc_T_2 = not(_banked_predictors_0_io_update_bits_pc_T_1)
connect banked_predictors_0.io.update.bits.pc, _banked_predictors_0_io_update_bits_pc_T_2
connect banked_predictors_0.io.update.bits.br_mask, io.update.bits.br_mask
connect banked_predictors_0.io.update.bits.btb_mispredicts, io.update.bits.btb_mispredicts
connect banked_predictors_0.io.update.bits.cfi_idx.valid, io.update.bits.cfi_idx.valid
connect banked_predictors_0.io.update.bits.ghist, io.update.bits.ghist.old_history
node _banked_lhist_providers_0_io_update_valid_T = neq(io.update.bits.br_mask, UInt<1>(0h0))
node _banked_lhist_providers_0_io_update_valid_T_1 = and(io.update.valid, _banked_lhist_providers_0_io_update_valid_T)
connect banked_lhist_providers_0.io.update.valid, _banked_lhist_providers_0_io_update_valid_T_1
node _banked_lhist_providers_0_io_update_pc_T = not(io.update.bits.pc)
node _banked_lhist_providers_0_io_update_pc_T_1 = or(_banked_lhist_providers_0_io_update_pc_T, UInt<3>(0h7))
node _banked_lhist_providers_0_io_update_pc_T_2 = not(_banked_lhist_providers_0_io_update_pc_T_1)
connect banked_lhist_providers_0.io.update.pc, _banked_lhist_providers_0_io_update_pc_T_2
when io.update.valid :
node _T = and(io.update.bits.cfi_is_br, io.update.bits.cfi_idx.valid)
when _T :
node _T_1 = dshr(io.update.bits.br_mask, io.update.bits.cfi_idx.bits)
node _T_2 = bits(_T_1, 0, 0)
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
node _T_5 = eq(_T_2, UInt<1>(0h0))
when _T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at predictor.scala:468 assert(io.update.bits.br_mask(io.update.bits.cfi_idx.bits))\n") : printf
assert(clock, _T_2, UInt<1>(0h1), "") : assert | module BranchPredictor( // @[predictor.scala:194:7]
input clock, // @[predictor.scala:194:7]
input reset, // @[predictor.scala:194:7]
input io_f0_req_valid, // @[predictor.scala:197:14]
input [39:0] io_f0_req_bits_pc, // @[predictor.scala:197:14]
input [63:0] io_f0_req_bits_ghist_old_history, // @[predictor.scala:197:14]
input io_f0_req_bits_ghist_current_saw_branch_not_taken, // @[predictor.scala:197:14]
input io_f0_req_bits_ghist_new_saw_branch_not_taken, // @[predictor.scala:197:14]
input io_f0_req_bits_ghist_new_saw_branch_taken, // @[predictor.scala:197:14]
input [4:0] io_f0_req_bits_ghist_ras_idx, // @[predictor.scala:197:14]
output io_resp_f1_preds_0_taken, // @[predictor.scala:197:14]
output io_resp_f1_preds_0_is_br, // @[predictor.scala:197:14]
output io_resp_f1_preds_0_is_jal, // @[predictor.scala:197:14]
output io_resp_f1_preds_0_predicted_pc_valid, // @[predictor.scala:197:14]
output [39:0] io_resp_f1_preds_0_predicted_pc_bits, // @[predictor.scala:197:14]
output io_resp_f1_preds_1_taken, // @[predictor.scala:197:14]
output io_resp_f1_preds_1_is_br, // @[predictor.scala:197:14]
output io_resp_f1_preds_1_is_jal, // @[predictor.scala:197:14]
output io_resp_f1_preds_1_predicted_pc_valid, // @[predictor.scala:197:14]
output [39:0] io_resp_f1_preds_1_predicted_pc_bits, // @[predictor.scala:197:14]
output io_resp_f1_preds_2_taken, // @[predictor.scala:197:14]
output io_resp_f1_preds_2_is_br, // @[predictor.scala:197:14]
output io_resp_f1_preds_2_is_jal, // @[predictor.scala:197:14]
output io_resp_f1_preds_2_predicted_pc_valid, // @[predictor.scala:197:14]
output [39:0] io_resp_f1_preds_2_predicted_pc_bits, // @[predictor.scala:197:14]
output io_resp_f1_preds_3_taken, // @[predictor.scala:197:14]
output io_resp_f1_preds_3_is_br, // @[predictor.scala:197:14]
output io_resp_f1_preds_3_is_jal, // @[predictor.scala:197:14]
output io_resp_f1_preds_3_predicted_pc_valid, // @[predictor.scala:197:14]
output [39:0] io_resp_f1_preds_3_predicted_pc_bits, // @[predictor.scala:197:14]
output [39:0] io_resp_f2_pc, // @[predictor.scala:197:14]
output io_resp_f2_preds_0_taken, // @[predictor.scala:197:14]
output io_resp_f2_preds_0_is_br, // @[predictor.scala:197:14]
output io_resp_f2_preds_0_is_jal, // @[predictor.scala:197:14]
output io_resp_f2_preds_0_predicted_pc_valid, // @[predictor.scala:197:14]
output [39:0] io_resp_f2_preds_0_predicted_pc_bits, // @[predictor.scala:197:14]
output io_resp_f2_preds_1_taken, // @[predictor.scala:197:14]
output io_resp_f2_preds_1_is_br, // @[predictor.scala:197:14]
output io_resp_f2_preds_1_is_jal, // @[predictor.scala:197:14]
output io_resp_f2_preds_1_predicted_pc_valid, // @[predictor.scala:197:14]
output [39:0] io_resp_f2_preds_1_predicted_pc_bits, // @[predictor.scala:197:14]
output io_resp_f2_preds_2_taken, // @[predictor.scala:197:14]
output io_resp_f2_preds_2_is_br, // @[predictor.scala:197:14]
output io_resp_f2_preds_2_is_jal, // @[predictor.scala:197:14]
output io_resp_f2_preds_2_predicted_pc_valid, // @[predictor.scala:197:14]
output [39:0] io_resp_f2_preds_2_predicted_pc_bits, // @[predictor.scala:197:14]
output io_resp_f2_preds_3_taken, // @[predictor.scala:197:14]
output io_resp_f2_preds_3_is_br, // @[predictor.scala:197:14]
output io_resp_f2_preds_3_is_jal, // @[predictor.scala:197:14]
output io_resp_f2_preds_3_predicted_pc_valid, // @[predictor.scala:197:14]
output [39:0] io_resp_f2_preds_3_predicted_pc_bits, // @[predictor.scala:197:14]
output [39:0] io_resp_f3_pc, // @[predictor.scala:197:14]
output io_resp_f3_preds_0_taken, // @[predictor.scala:197:14]
output io_resp_f3_preds_0_is_br, // @[predictor.scala:197:14]
output io_resp_f3_preds_0_is_jal, // @[predictor.scala:197:14]
output io_resp_f3_preds_0_predicted_pc_valid, // @[predictor.scala:197:14]
output [39:0] io_resp_f3_preds_0_predicted_pc_bits, // @[predictor.scala:197:14]
output io_resp_f3_preds_1_taken, // @[predictor.scala:197:14]
output io_resp_f3_preds_1_is_br, // @[predictor.scala:197:14]
output io_resp_f3_preds_1_is_jal, // @[predictor.scala:197:14]
output io_resp_f3_preds_1_predicted_pc_valid, // @[predictor.scala:197:14]
output [39:0] io_resp_f3_preds_1_predicted_pc_bits, // @[predictor.scala:197:14]
output io_resp_f3_preds_2_taken, // @[predictor.scala:197:14]
output io_resp_f3_preds_2_is_br, // @[predictor.scala:197:14]
output io_resp_f3_preds_2_is_jal, // @[predictor.scala:197:14]
output io_resp_f3_preds_2_predicted_pc_valid, // @[predictor.scala:197:14]
output [39:0] io_resp_f3_preds_2_predicted_pc_bits, // @[predictor.scala:197:14]
output io_resp_f3_preds_3_taken, // @[predictor.scala:197:14]
output io_resp_f3_preds_3_is_br, // @[predictor.scala:197:14]
output io_resp_f3_preds_3_is_jal, // @[predictor.scala:197:14]
output io_resp_f3_preds_3_predicted_pc_valid, // @[predictor.scala:197:14]
output [39:0] io_resp_f3_preds_3_predicted_pc_bits, // @[predictor.scala:197:14]
output [119:0] io_resp_f3_meta_0, // @[predictor.scala:197:14]
input io_f3_fire, // @[predictor.scala:197:14]
input io_update_valid, // @[predictor.scala:197:14]
input io_update_bits_is_mispredict_update, // @[predictor.scala:197:14]
input io_update_bits_is_repair_update, // @[predictor.scala:197:14]
input [3:0] io_update_bits_btb_mispredicts, // @[predictor.scala:197:14]
input [39:0] io_update_bits_pc, // @[predictor.scala:197:14]
input [3:0] io_update_bits_br_mask, // @[predictor.scala:197:14]
input io_update_bits_cfi_idx_valid, // @[predictor.scala:197:14]
input [1:0] io_update_bits_cfi_idx_bits, // @[predictor.scala:197:14]
input io_update_bits_cfi_taken, // @[predictor.scala:197:14]
input io_update_bits_cfi_mispredicted, // @[predictor.scala:197:14]
input io_update_bits_cfi_is_br, // @[predictor.scala:197:14]
input io_update_bits_cfi_is_jal, // @[predictor.scala:197:14]
input io_update_bits_cfi_is_jalr, // @[predictor.scala:197:14]
input [63:0] io_update_bits_ghist_old_history, // @[predictor.scala:197:14]
input io_update_bits_ghist_current_saw_branch_not_taken, // @[predictor.scala:197:14]
input io_update_bits_ghist_new_saw_branch_not_taken, // @[predictor.scala:197:14]
input io_update_bits_ghist_new_saw_branch_taken, // @[predictor.scala:197:14]
input [4:0] io_update_bits_ghist_ras_idx, // @[predictor.scala:197:14]
input io_update_bits_lhist_0, // @[predictor.scala:197:14]
input [39:0] io_update_bits_target, // @[predictor.scala:197:14]
input [119:0] io_update_bits_meta_0 // @[predictor.scala:197:14]
);
wire _banked_predictors_0_io_resp_f3_0_taken; // @[predictor.scala:218:19]
wire _banked_predictors_0_io_resp_f3_0_is_br; // @[predictor.scala:218:19]
wire _banked_predictors_0_io_resp_f3_0_predicted_pc_valid; // @[predictor.scala:218:19]
wire _banked_predictors_0_io_resp_f3_1_taken; // @[predictor.scala:218:19]
wire _banked_predictors_0_io_resp_f3_1_is_br; // @[predictor.scala:218:19]
wire _banked_predictors_0_io_resp_f3_1_predicted_pc_valid; // @[predictor.scala:218:19]
wire _banked_predictors_0_io_resp_f3_2_taken; // @[predictor.scala:218:19]
wire _banked_predictors_0_io_resp_f3_2_is_br; // @[predictor.scala:218:19]
wire _banked_predictors_0_io_resp_f3_2_predicted_pc_valid; // @[predictor.scala:218:19]
wire _banked_predictors_0_io_resp_f3_3_taken; // @[predictor.scala:218:19]
wire _banked_predictors_0_io_resp_f3_3_is_br; // @[predictor.scala:218:19]
wire _banked_predictors_0_io_resp_f3_3_predicted_pc_valid; // @[predictor.scala:218:19]
wire io_f0_req_valid_0 = io_f0_req_valid; // @[predictor.scala:194:7]
wire [39:0] io_f0_req_bits_pc_0 = io_f0_req_bits_pc; // @[predictor.scala:194:7]
wire [63:0] io_f0_req_bits_ghist_old_history_0 = io_f0_req_bits_ghist_old_history; // @[predictor.scala:194:7]
wire io_f0_req_bits_ghist_current_saw_branch_not_taken_0 = io_f0_req_bits_ghist_current_saw_branch_not_taken; // @[predictor.scala:194:7]
wire io_f0_req_bits_ghist_new_saw_branch_not_taken_0 = io_f0_req_bits_ghist_new_saw_branch_not_taken; // @[predictor.scala:194:7]
wire io_f0_req_bits_ghist_new_saw_branch_taken_0 = io_f0_req_bits_ghist_new_saw_branch_taken; // @[predictor.scala:194:7]
wire [4:0] io_f0_req_bits_ghist_ras_idx_0 = io_f0_req_bits_ghist_ras_idx; // @[predictor.scala:194:7]
wire io_f3_fire_0 = io_f3_fire; // @[predictor.scala:194:7]
wire io_update_valid_0 = io_update_valid; // @[predictor.scala:194:7]
wire io_update_bits_is_mispredict_update_0 = io_update_bits_is_mispredict_update; // @[predictor.scala:194:7]
wire io_update_bits_is_repair_update_0 = io_update_bits_is_repair_update; // @[predictor.scala:194:7]
wire [3:0] io_update_bits_btb_mispredicts_0 = io_update_bits_btb_mispredicts; // @[predictor.scala:194:7]
wire [39:0] io_update_bits_pc_0 = io_update_bits_pc; // @[predictor.scala:194:7]
wire [3:0] io_update_bits_br_mask_0 = io_update_bits_br_mask; // @[predictor.scala:194:7]
wire io_update_bits_cfi_idx_valid_0 = io_update_bits_cfi_idx_valid; // @[predictor.scala:194:7]
wire [1:0] io_update_bits_cfi_idx_bits_0 = io_update_bits_cfi_idx_bits; // @[predictor.scala:194:7]
wire io_update_bits_cfi_taken_0 = io_update_bits_cfi_taken; // @[predictor.scala:194:7]
wire io_update_bits_cfi_mispredicted_0 = io_update_bits_cfi_mispredicted; // @[predictor.scala:194:7]
wire io_update_bits_cfi_is_br_0 = io_update_bits_cfi_is_br; // @[predictor.scala:194:7]
wire io_update_bits_cfi_is_jal_0 = io_update_bits_cfi_is_jal; // @[predictor.scala:194:7]
wire io_update_bits_cfi_is_jalr_0 = io_update_bits_cfi_is_jalr; // @[predictor.scala:194:7]
wire [63:0] io_update_bits_ghist_old_history_0 = io_update_bits_ghist_old_history; // @[predictor.scala:194:7]
wire io_update_bits_ghist_current_saw_branch_not_taken_0 = io_update_bits_ghist_current_saw_branch_not_taken; // @[predictor.scala:194:7]
wire io_update_bits_ghist_new_saw_branch_not_taken_0 = io_update_bits_ghist_new_saw_branch_not_taken; // @[predictor.scala:194:7]
wire io_update_bits_ghist_new_saw_branch_taken_0 = io_update_bits_ghist_new_saw_branch_taken; // @[predictor.scala:194:7]
wire [4:0] io_update_bits_ghist_ras_idx_0 = io_update_bits_ghist_ras_idx; // @[predictor.scala:194:7]
wire io_update_bits_lhist_0_0 = io_update_bits_lhist_0; // @[predictor.scala:194:7]
wire [39:0] io_update_bits_target_0 = io_update_bits_target; // @[predictor.scala:194:7]
wire [119:0] io_update_bits_meta_0_0 = io_update_bits_meta_0; // @[predictor.scala:194:7]
wire [119:0] io_resp_f1_meta_0 = 120'h0; // @[predictor.scala:194:7]
wire [119:0] io_resp_f2_meta_0 = 120'h0; // @[predictor.scala:194:7]
wire io_resp_f1_lhist_0 = 1'h0; // @[predictor.scala:194:7]
wire io_resp_f2_lhist_0 = 1'h0; // @[predictor.scala:194:7]
wire io_resp_f3_lhist_0 = 1'h0; // @[predictor.scala:194:7]
wire _banked_predictors_0_io_resp_in_0_WIRE_f1_0_taken = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f1_0_is_br = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f1_0_is_jal = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f1_0_predicted_pc_valid = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f1_1_taken = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f1_1_is_br = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f1_1_is_jal = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f1_1_predicted_pc_valid = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f1_2_taken = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f1_2_is_br = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f1_2_is_jal = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f1_2_predicted_pc_valid = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f1_3_taken = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f1_3_is_br = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f1_3_is_jal = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f1_3_predicted_pc_valid = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f2_0_taken = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f2_0_is_br = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f2_0_is_jal = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f2_0_predicted_pc_valid = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f2_1_taken = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f2_1_is_br = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f2_1_is_jal = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f2_1_predicted_pc_valid = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f2_2_taken = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f2_2_is_br = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f2_2_is_jal = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f2_2_predicted_pc_valid = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f2_3_taken = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f2_3_is_br = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f2_3_is_jal = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f2_3_predicted_pc_valid = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f3_0_taken = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f3_0_is_br = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f3_0_is_jal = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f3_0_predicted_pc_valid = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f3_1_taken = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f3_1_is_br = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f3_1_is_jal = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f3_1_predicted_pc_valid = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f3_2_taken = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f3_2_is_br = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f3_2_is_jal = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f3_2_predicted_pc_valid = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f3_3_taken = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f3_3_is_br = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f3_3_is_jal = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f3_3_predicted_pc_valid = 1'h0; // @[predictor.scala:242:67]
wire [39:0] _banked_predictors_0_io_resp_in_0_WIRE_f1_0_predicted_pc_bits = 40'h0; // @[predictor.scala:242:67]
wire [39:0] _banked_predictors_0_io_resp_in_0_WIRE_f1_1_predicted_pc_bits = 40'h0; // @[predictor.scala:242:67]
wire [39:0] _banked_predictors_0_io_resp_in_0_WIRE_f1_2_predicted_pc_bits = 40'h0; // @[predictor.scala:242:67]
wire [39:0] _banked_predictors_0_io_resp_in_0_WIRE_f1_3_predicted_pc_bits = 40'h0; // @[predictor.scala:242:67]
wire [39:0] _banked_predictors_0_io_resp_in_0_WIRE_f2_0_predicted_pc_bits = 40'h0; // @[predictor.scala:242:67]
wire [39:0] _banked_predictors_0_io_resp_in_0_WIRE_f2_1_predicted_pc_bits = 40'h0; // @[predictor.scala:242:67]
wire [39:0] _banked_predictors_0_io_resp_in_0_WIRE_f2_2_predicted_pc_bits = 40'h0; // @[predictor.scala:242:67]
wire [39:0] _banked_predictors_0_io_resp_in_0_WIRE_f2_3_predicted_pc_bits = 40'h0; // @[predictor.scala:242:67]
wire [39:0] _banked_predictors_0_io_resp_in_0_WIRE_f3_0_predicted_pc_bits = 40'h0; // @[predictor.scala:242:67]
wire [39:0] _banked_predictors_0_io_resp_in_0_WIRE_f3_1_predicted_pc_bits = 40'h0; // @[predictor.scala:242:67]
wire [39:0] _banked_predictors_0_io_resp_in_0_WIRE_f3_2_predicted_pc_bits = 40'h0; // @[predictor.scala:242:67]
wire [39:0] _banked_predictors_0_io_resp_in_0_WIRE_f3_3_predicted_pc_bits = 40'h0; // @[predictor.scala:242:67]
wire io_resp_f1_preds_0_predicted_pc_valid_0; // @[predictor.scala:194:7]
wire [39:0] io_resp_f1_preds_0_predicted_pc_bits_0; // @[predictor.scala:194:7]
wire io_resp_f1_preds_0_taken_0; // @[predictor.scala:194:7]
wire io_resp_f1_preds_0_is_br_0; // @[predictor.scala:194:7]
wire io_resp_f1_preds_0_is_jal_0; // @[predictor.scala:194:7]
wire io_resp_f1_preds_1_predicted_pc_valid_0; // @[predictor.scala:194:7]
wire [39:0] io_resp_f1_preds_1_predicted_pc_bits_0; // @[predictor.scala:194:7]
wire io_resp_f1_preds_1_taken_0; // @[predictor.scala:194:7]
wire io_resp_f1_preds_1_is_br_0; // @[predictor.scala:194:7]
wire io_resp_f1_preds_1_is_jal_0; // @[predictor.scala:194:7]
wire io_resp_f1_preds_2_predicted_pc_valid_0; // @[predictor.scala:194:7]
wire [39:0] io_resp_f1_preds_2_predicted_pc_bits_0; // @[predictor.scala:194:7]
wire io_resp_f1_preds_2_taken_0; // @[predictor.scala:194:7]
wire io_resp_f1_preds_2_is_br_0; // @[predictor.scala:194:7]
wire io_resp_f1_preds_2_is_jal_0; // @[predictor.scala:194:7]
wire io_resp_f1_preds_3_predicted_pc_valid_0; // @[predictor.scala:194:7]
wire [39:0] io_resp_f1_preds_3_predicted_pc_bits_0; // @[predictor.scala:194:7]
wire io_resp_f1_preds_3_taken_0; // @[predictor.scala:194:7]
wire io_resp_f1_preds_3_is_br_0; // @[predictor.scala:194:7]
wire io_resp_f1_preds_3_is_jal_0; // @[predictor.scala:194:7]
wire [39:0] io_resp_f1_pc; // @[predictor.scala:194:7]
wire io_resp_f2_preds_0_predicted_pc_valid_0; // @[predictor.scala:194:7]
wire [39:0] io_resp_f2_preds_0_predicted_pc_bits_0; // @[predictor.scala:194:7]
wire io_resp_f2_preds_0_taken_0; // @[predictor.scala:194:7]
wire io_resp_f2_preds_0_is_br_0; // @[predictor.scala:194:7]
wire io_resp_f2_preds_0_is_jal_0; // @[predictor.scala:194:7]
wire io_resp_f2_preds_1_predicted_pc_valid_0; // @[predictor.scala:194:7]
wire [39:0] io_resp_f2_preds_1_predicted_pc_bits_0; // @[predictor.scala:194:7]
wire io_resp_f2_preds_1_taken_0; // @[predictor.scala:194:7]
wire io_resp_f2_preds_1_is_br_0; // @[predictor.scala:194:7]
wire io_resp_f2_preds_1_is_jal_0; // @[predictor.scala:194:7]
wire io_resp_f2_preds_2_predicted_pc_valid_0; // @[predictor.scala:194:7]
wire [39:0] io_resp_f2_preds_2_predicted_pc_bits_0; // @[predictor.scala:194:7]
wire io_resp_f2_preds_2_taken_0; // @[predictor.scala:194:7]
wire io_resp_f2_preds_2_is_br_0; // @[predictor.scala:194:7]
wire io_resp_f2_preds_2_is_jal_0; // @[predictor.scala:194:7]
wire io_resp_f2_preds_3_predicted_pc_valid_0; // @[predictor.scala:194:7]
wire [39:0] io_resp_f2_preds_3_predicted_pc_bits_0; // @[predictor.scala:194:7]
wire io_resp_f2_preds_3_taken_0; // @[predictor.scala:194:7]
wire io_resp_f2_preds_3_is_br_0; // @[predictor.scala:194:7]
wire io_resp_f2_preds_3_is_jal_0; // @[predictor.scala:194:7]
wire [39:0] io_resp_f2_pc_0; // @[predictor.scala:194:7]
wire io_resp_f3_preds_0_predicted_pc_valid_0; // @[predictor.scala:194:7]
wire [39:0] io_resp_f3_preds_0_predicted_pc_bits_0; // @[predictor.scala:194:7]
wire io_resp_f3_preds_0_taken_0; // @[predictor.scala:194:7]
wire io_resp_f3_preds_0_is_br_0; // @[predictor.scala:194:7]
wire io_resp_f3_preds_0_is_jal_0; // @[predictor.scala:194:7]
wire io_resp_f3_preds_1_predicted_pc_valid_0; // @[predictor.scala:194:7]
wire [39:0] io_resp_f3_preds_1_predicted_pc_bits_0; // @[predictor.scala:194:7]
wire io_resp_f3_preds_1_taken_0; // @[predictor.scala:194:7]
wire io_resp_f3_preds_1_is_br_0; // @[predictor.scala:194:7]
wire io_resp_f3_preds_1_is_jal_0; // @[predictor.scala:194:7]
wire io_resp_f3_preds_2_predicted_pc_valid_0; // @[predictor.scala:194:7]
wire [39:0] io_resp_f3_preds_2_predicted_pc_bits_0; // @[predictor.scala:194:7]
wire io_resp_f3_preds_2_taken_0; // @[predictor.scala:194:7]
wire io_resp_f3_preds_2_is_br_0; // @[predictor.scala:194:7]
wire io_resp_f3_preds_2_is_jal_0; // @[predictor.scala:194:7]
wire io_resp_f3_preds_3_predicted_pc_valid_0; // @[predictor.scala:194:7]
wire [39:0] io_resp_f3_preds_3_predicted_pc_bits_0; // @[predictor.scala:194:7]
wire io_resp_f3_preds_3_taken_0; // @[predictor.scala:194:7]
wire io_resp_f3_preds_3_is_br_0; // @[predictor.scala:194:7]
wire io_resp_f3_preds_3_is_jal_0; // @[predictor.scala:194:7]
wire [119:0] io_resp_f3_meta_0_0; // @[predictor.scala:194:7]
wire [39:0] io_resp_f3_pc_0; // @[predictor.scala:194:7]
wire [39:0] _banked_lhist_providers_0_io_f0_pc_T = ~io_f0_req_bits_pc_0; // @[frontend.scala:160:33]
wire [39:0] _banked_lhist_providers_0_io_f0_pc_T_1 = {_banked_lhist_providers_0_io_f0_pc_T[39:3], 3'h7}; // @[frontend.scala:160:{33,39}]
wire [39:0] _banked_lhist_providers_0_io_f0_pc_T_2 = ~_banked_lhist_providers_0_io_f0_pc_T_1; // @[frontend.scala:160:{31,39}]
wire [39:0] _banked_predictors_0_io_f0_pc_T = ~io_f0_req_bits_pc_0; // @[frontend.scala:160:33]
wire [39:0] _banked_predictors_0_io_f0_pc_T_1 = {_banked_predictors_0_io_f0_pc_T[39:3], 3'h7}; // @[frontend.scala:160:{33,39}]
wire [39:0] _banked_predictors_0_io_f0_pc_T_2 = ~_banked_predictors_0_io_f0_pc_T_1; // @[frontend.scala:160:{31,39}]
wire [1:0] banked_predictors_0_io_f0_mask_idx = io_f0_req_bits_pc_0[2:1]; // @[package.scala:163:13]
wire [6:0] _banked_predictors_0_io_f0_mask_T = 7'hF << banked_predictors_0_io_f0_mask_idx; // @[package.scala:163:13]
reg [63:0] banked_predictors_0_io_f1_ghist_REG; // @[predictor.scala:239:48]
wire _banked_lhist_providers_0_io_f3_taken_br_T = _banked_predictors_0_io_resp_f3_0_is_br & _banked_predictors_0_io_resp_f3_0_predicted_pc_valid; // @[predictor.scala:218:19, :293:15]
wire _banked_lhist_providers_0_io_f3_taken_br_T_1 = _banked_lhist_providers_0_io_f3_taken_br_T & _banked_predictors_0_io_resp_f3_0_taken; // @[predictor.scala:218:19, :293:{15,39}]
wire _banked_lhist_providers_0_io_f3_taken_br_T_2 = _banked_predictors_0_io_resp_f3_1_is_br & _banked_predictors_0_io_resp_f3_1_predicted_pc_valid; // @[predictor.scala:218:19, :293:15]
wire _banked_lhist_providers_0_io_f3_taken_br_T_3 = _banked_lhist_providers_0_io_f3_taken_br_T_2 & _banked_predictors_0_io_resp_f3_1_taken; // @[predictor.scala:218:19, :293:{15,39}]
wire _banked_lhist_providers_0_io_f3_taken_br_T_4 = _banked_predictors_0_io_resp_f3_2_is_br & _banked_predictors_0_io_resp_f3_2_predicted_pc_valid; // @[predictor.scala:218:19, :293:15]
wire _banked_lhist_providers_0_io_f3_taken_br_T_5 = _banked_lhist_providers_0_io_f3_taken_br_T_4 & _banked_predictors_0_io_resp_f3_2_taken; // @[predictor.scala:218:19, :293:{15,39}]
wire _banked_lhist_providers_0_io_f3_taken_br_T_6 = _banked_predictors_0_io_resp_f3_3_is_br & _banked_predictors_0_io_resp_f3_3_predicted_pc_valid; // @[predictor.scala:218:19, :293:15]
wire _banked_lhist_providers_0_io_f3_taken_br_T_7 = _banked_lhist_providers_0_io_f3_taken_br_T_6 & _banked_predictors_0_io_resp_f3_3_taken; // @[predictor.scala:218:19, :293:{15,39}]
wire _banked_lhist_providers_0_io_f3_taken_br_T_8 = _banked_lhist_providers_0_io_f3_taken_br_T_1 | _banked_lhist_providers_0_io_f3_taken_br_T_3; // @[predictor.scala:293:39, :294:15]
wire _banked_lhist_providers_0_io_f3_taken_br_T_9 = _banked_lhist_providers_0_io_f3_taken_br_T_8 | _banked_lhist_providers_0_io_f3_taken_br_T_5; // @[predictor.scala:293:39, :294:15]
wire _banked_lhist_providers_0_io_f3_taken_br_T_10 = _banked_lhist_providers_0_io_f3_taken_br_T_9 | _banked_lhist_providers_0_io_f3_taken_br_T_7; // @[predictor.scala:293:39, :294:15]
reg [39:0] io_resp_f1_pc_REG; // @[predictor.scala:362:27]
assign io_resp_f1_pc = io_resp_f1_pc_REG; // @[predictor.scala:194:7, :362:27]
reg [39:0] io_resp_f2_pc_REG; // @[predictor.scala:363:27]
assign io_resp_f2_pc_0 = io_resp_f2_pc_REG; // @[predictor.scala:194:7, :363:27]
reg [39:0] io_resp_f3_pc_REG; // @[predictor.scala:364:27]
assign io_resp_f3_pc_0 = io_resp_f3_pc_REG; // @[predictor.scala:194:7, :364:27]
wire [39:0] _banked_predictors_0_io_update_bits_pc_T = ~io_update_bits_pc_0; // @[frontend.scala:160:33]
wire [39:0] _banked_predictors_0_io_update_bits_pc_T_1 = {_banked_predictors_0_io_update_bits_pc_T[39:3], 3'h7}; // @[frontend.scala:160:{33,39}]
wire [39:0] _banked_predictors_0_io_update_bits_pc_T_2 = ~_banked_predictors_0_io_update_bits_pc_T_1; // @[frontend.scala:160:{31,39}]
wire _banked_lhist_providers_0_io_update_valid_T = |io_update_bits_br_mask_0; // @[predictor.scala:194:7, :401:92]
wire _banked_lhist_providers_0_io_update_valid_T_1 = io_update_valid_0 & _banked_lhist_providers_0_io_update_valid_T; // @[predictor.scala:194:7, :401:{66,92}]
wire [39:0] _banked_lhist_providers_0_io_update_pc_T = ~io_update_bits_pc_0; // @[frontend.scala:160:33]
wire [39:0] _banked_lhist_providers_0_io_update_pc_T_1 = {_banked_lhist_providers_0_io_update_pc_T[39:3], 3'h7}; // @[frontend.scala:160:{33,39}]
wire [39:0] _banked_lhist_providers_0_io_update_pc_T_2 = ~_banked_lhist_providers_0_io_update_pc_T_1; // @[frontend.scala:160:{31,39}] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_49 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_source_valid_1 of AsyncResetSynchronizerShiftReg_w1_d3_i0_59
connect io_out_source_valid_1.clock, clock
connect io_out_source_valid_1.reset, reset
connect io_out_source_valid_1.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_source_valid_1.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_49( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_59 io_out_source_valid_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module IngressUnit_53 :
input clock : Clock
input reset : Reset
output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<0>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}}}, flip vcalloc_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}}, flip out_credit_available : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}[1], debug : { va_stall : UInt<0>, sa_stall : UInt<0>}, flip block : UInt<1>, flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}
inst route_buffer of Queue2_Flit_106
connect route_buffer.clock, clock
connect route_buffer.reset, reset
inst route_q of Queue2_RouteComputerResp_53
connect route_q.clock, clock
connect route_q.reset, reset
node _T = eq(UInt<1>(0h1), io.in.bits.egress_id)
node _T_1 = eq(_T, UInt<1>(0h0))
node _T_2 = and(io.in.valid, _T_1)
node _T_3 = eq(_T_2, UInt<1>(0h0))
node _T_4 = asUInt(reset)
node _T_5 = eq(_T_4, UInt<1>(0h0))
when _T_5 :
node _T_6 = eq(_T_3, UInt<1>(0h0))
when _T_6 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:30 assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))\n") : printf
assert(clock, _T_3, UInt<1>(0h1), "") : assert
connect route_buffer.io.enq.bits.head, io.in.bits.head
connect route_buffer.io.enq.bits.tail, io.in.bits.tail
connect route_buffer.io.enq.bits.flow.ingress_node, UInt<3>(0h7)
connect route_buffer.io.enq.bits.flow.ingress_node_id, UInt<1>(0h1)
connect route_buffer.io.enq.bits.flow.vnet_id, UInt<1>(0h1)
node _route_buffer_io_enq_bits_flow_egress_node_T = eq(UInt<1>(0h1), io.in.bits.egress_id)
connect route_buffer.io.enq.bits.flow.egress_node, UInt<1>(0h0)
node _route_buffer_io_enq_bits_flow_egress_node_id_T = eq(UInt<1>(0h1), io.in.bits.egress_id)
connect route_buffer.io.enq.bits.flow.egress_node_id, UInt<1>(0h1)
connect route_buffer.io.enq.bits.payload, io.in.bits.payload
invalidate route_buffer.io.enq.bits.virt_channel_id
connect io.router_req.bits.src_virt_id, UInt<1>(0h0)
connect io.router_req.bits.flow.egress_node_id, route_buffer.io.enq.bits.flow.egress_node_id
connect io.router_req.bits.flow.egress_node, route_buffer.io.enq.bits.flow.egress_node
connect io.router_req.bits.flow.ingress_node_id, route_buffer.io.enq.bits.flow.ingress_node_id
connect io.router_req.bits.flow.ingress_node, route_buffer.io.enq.bits.flow.ingress_node
connect io.router_req.bits.flow.vnet_id, route_buffer.io.enq.bits.flow.vnet_id
node at_dest = eq(route_buffer.io.enq.bits.flow.egress_node, UInt<3>(0h7))
node _route_buffer_io_enq_valid_T = eq(io.in.bits.head, UInt<1>(0h0))
node _route_buffer_io_enq_valid_T_1 = or(io.router_req.ready, _route_buffer_io_enq_valid_T)
node _route_buffer_io_enq_valid_T_2 = or(_route_buffer_io_enq_valid_T_1, at_dest)
node _route_buffer_io_enq_valid_T_3 = and(io.in.valid, _route_buffer_io_enq_valid_T_2)
connect route_buffer.io.enq.valid, _route_buffer_io_enq_valid_T_3
node _io_router_req_valid_T = and(io.in.valid, route_buffer.io.enq.ready)
node _io_router_req_valid_T_1 = and(_io_router_req_valid_T, io.in.bits.head)
node _io_router_req_valid_T_2 = eq(at_dest, UInt<1>(0h0))
node _io_router_req_valid_T_3 = and(_io_router_req_valid_T_1, _io_router_req_valid_T_2)
connect io.router_req.valid, _io_router_req_valid_T_3
node _io_in_ready_T = eq(io.in.bits.head, UInt<1>(0h0))
node _io_in_ready_T_1 = or(io.router_req.ready, _io_in_ready_T)
node _io_in_ready_T_2 = or(_io_in_ready_T_1, at_dest)
node _io_in_ready_T_3 = and(route_buffer.io.enq.ready, _io_in_ready_T_2)
connect io.in.ready, _io_in_ready_T_3
node _route_q_io_enq_valid_T = and(io.router_req.ready, io.router_req.valid)
connect route_q.io.enq.valid, _route_q_io_enq_valid_T
connect route_q.io.enq.bits.vc_sel.`0`[0], io.router_resp.vc_sel.`0`[0]
connect route_q.io.enq.bits.vc_sel.`0`[1], io.router_resp.vc_sel.`0`[1]
connect route_q.io.enq.bits.vc_sel.`0`[2], io.router_resp.vc_sel.`0`[2]
connect route_q.io.enq.bits.vc_sel.`0`[3], io.router_resp.vc_sel.`0`[3]
connect route_q.io.enq.bits.vc_sel.`0`[4], io.router_resp.vc_sel.`0`[4]
connect route_q.io.enq.bits.vc_sel.`1`[0], io.router_resp.vc_sel.`1`[0]
connect route_q.io.enq.bits.vc_sel.`2`[0], io.router_resp.vc_sel.`2`[0]
connect route_q.io.enq.bits.vc_sel.`3`[0], io.router_resp.vc_sel.`3`[0]
node _T_7 = and(io.in.ready, io.in.valid)
node _T_8 = and(_T_7, io.in.bits.head)
node _T_9 = and(_T_8, at_dest)
when _T_9 :
connect route_q.io.enq.valid, UInt<1>(0h1)
connect route_q.io.enq.bits.vc_sel.`0`[0], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[1], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[2], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[3], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[4], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`3`[0], UInt<1>(0h0)
node _T_10 = eq(UInt<5>(0h14), io.in.bits.egress_id)
when _T_10 :
connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h1)
node _T_11 = eq(UInt<5>(0h15), io.in.bits.egress_id)
when _T_11 :
connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h1)
node _T_12 = eq(UInt<5>(0h16), io.in.bits.egress_id)
when _T_12 :
connect route_q.io.enq.bits.vc_sel.`3`[0], UInt<1>(0h1)
node _T_13 = eq(route_q.io.enq.ready, UInt<1>(0h0))
node _T_14 = and(route_q.io.enq.valid, _T_13)
node _T_15 = eq(_T_14, UInt<1>(0h0))
node _T_16 = asUInt(reset)
node _T_17 = eq(_T_16, UInt<1>(0h0))
when _T_17 :
node _T_18 = eq(_T_15, UInt<1>(0h0))
when _T_18 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:73 assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))\n") : printf_1
assert(clock, _T_15, UInt<1>(0h1), "") : assert_1
inst vcalloc_buffer of Queue2_Flit_107
connect vcalloc_buffer.clock, clock
connect vcalloc_buffer.reset, reset
inst vcalloc_q of Queue1_VCAllocResp_53
connect vcalloc_q.clock, clock
connect vcalloc_q.reset, reset
connect vcalloc_buffer.io.enq.bits.virt_channel_id, route_buffer.io.deq.bits.virt_channel_id
connect vcalloc_buffer.io.enq.bits.flow.egress_node_id, route_buffer.io.deq.bits.flow.egress_node_id
connect vcalloc_buffer.io.enq.bits.flow.egress_node, route_buffer.io.deq.bits.flow.egress_node
connect vcalloc_buffer.io.enq.bits.flow.ingress_node_id, route_buffer.io.deq.bits.flow.ingress_node_id
connect vcalloc_buffer.io.enq.bits.flow.ingress_node, route_buffer.io.deq.bits.flow.ingress_node
connect vcalloc_buffer.io.enq.bits.flow.vnet_id, route_buffer.io.deq.bits.flow.vnet_id
connect vcalloc_buffer.io.enq.bits.payload, route_buffer.io.deq.bits.payload
connect vcalloc_buffer.io.enq.bits.tail, route_buffer.io.deq.bits.tail
connect vcalloc_buffer.io.enq.bits.head, route_buffer.io.deq.bits.head
connect io.vcalloc_req.bits.vc_sel.`0`, route_q.io.deq.bits.vc_sel.`0`
connect io.vcalloc_req.bits.vc_sel.`1`, route_q.io.deq.bits.vc_sel.`1`
connect io.vcalloc_req.bits.vc_sel.`2`, route_q.io.deq.bits.vc_sel.`2`
connect io.vcalloc_req.bits.vc_sel.`3`, route_q.io.deq.bits.vc_sel.`3`
connect io.vcalloc_req.bits.flow, route_buffer.io.deq.bits.flow
connect io.vcalloc_req.bits.in_vc, UInt<1>(0h0)
node _vcalloc_buffer_io_enq_valid_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _vcalloc_buffer_io_enq_valid_T_1 = or(route_q.io.deq.valid, _vcalloc_buffer_io_enq_valid_T)
node _vcalloc_buffer_io_enq_valid_T_2 = and(route_buffer.io.deq.valid, _vcalloc_buffer_io_enq_valid_T_1)
node _vcalloc_buffer_io_enq_valid_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _vcalloc_buffer_io_enq_valid_T_4 = or(io.vcalloc_req.ready, _vcalloc_buffer_io_enq_valid_T_3)
node _vcalloc_buffer_io_enq_valid_T_5 = and(_vcalloc_buffer_io_enq_valid_T_2, _vcalloc_buffer_io_enq_valid_T_4)
connect vcalloc_buffer.io.enq.valid, _vcalloc_buffer_io_enq_valid_T_5
node _io_vcalloc_req_valid_T = and(route_buffer.io.deq.valid, route_q.io.deq.valid)
node _io_vcalloc_req_valid_T_1 = and(_io_vcalloc_req_valid_T, route_buffer.io.deq.bits.head)
node _io_vcalloc_req_valid_T_2 = and(_io_vcalloc_req_valid_T_1, vcalloc_buffer.io.enq.ready)
node _io_vcalloc_req_valid_T_3 = and(_io_vcalloc_req_valid_T_2, vcalloc_q.io.enq.ready)
connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_3
node _route_buffer_io_deq_ready_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _route_buffer_io_deq_ready_T_1 = or(route_q.io.deq.valid, _route_buffer_io_deq_ready_T)
node _route_buffer_io_deq_ready_T_2 = and(vcalloc_buffer.io.enq.ready, _route_buffer_io_deq_ready_T_1)
node _route_buffer_io_deq_ready_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _route_buffer_io_deq_ready_T_4 = or(io.vcalloc_req.ready, _route_buffer_io_deq_ready_T_3)
node _route_buffer_io_deq_ready_T_5 = and(_route_buffer_io_deq_ready_T_2, _route_buffer_io_deq_ready_T_4)
node _route_buffer_io_deq_ready_T_6 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _route_buffer_io_deq_ready_T_7 = or(vcalloc_q.io.enq.ready, _route_buffer_io_deq_ready_T_6)
node _route_buffer_io_deq_ready_T_8 = and(_route_buffer_io_deq_ready_T_5, _route_buffer_io_deq_ready_T_7)
connect route_buffer.io.deq.ready, _route_buffer_io_deq_ready_T_8
node _route_q_io_deq_ready_T = and(route_buffer.io.deq.ready, route_buffer.io.deq.valid)
node _route_q_io_deq_ready_T_1 = and(_route_q_io_deq_ready_T, route_buffer.io.deq.bits.tail)
connect route_q.io.deq.ready, _route_q_io_deq_ready_T_1
node _vcalloc_q_io_enq_valid_T = and(io.vcalloc_req.ready, io.vcalloc_req.valid)
connect vcalloc_q.io.enq.valid, _vcalloc_q_io_enq_valid_T
connect vcalloc_q.io.enq.bits.vc_sel.`0`[0], io.vcalloc_resp.vc_sel.`0`[0]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[1], io.vcalloc_resp.vc_sel.`0`[1]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[2], io.vcalloc_resp.vc_sel.`0`[2]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[3], io.vcalloc_resp.vc_sel.`0`[3]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[4], io.vcalloc_resp.vc_sel.`0`[4]
connect vcalloc_q.io.enq.bits.vc_sel.`1`[0], io.vcalloc_resp.vc_sel.`1`[0]
connect vcalloc_q.io.enq.bits.vc_sel.`2`[0], io.vcalloc_resp.vc_sel.`2`[0]
connect vcalloc_q.io.enq.bits.vc_sel.`3`[0], io.vcalloc_resp.vc_sel.`3`[0]
node _T_19 = eq(vcalloc_q.io.enq.ready, UInt<1>(0h0))
node _T_20 = and(vcalloc_q.io.enq.valid, _T_19)
node _T_21 = eq(_T_20, UInt<1>(0h0))
node _T_22 = asUInt(reset)
node _T_23 = eq(_T_22, UInt<1>(0h0))
when _T_23 :
node _T_24 = eq(_T_21, UInt<1>(0h0))
when _T_24 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:102 assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))\n") : printf_2
assert(clock, _T_21, UInt<1>(0h1), "") : assert_2
connect io.salloc_req[0].bits.vc_sel.`0`, vcalloc_q.io.deq.bits.vc_sel.`0`
connect io.salloc_req[0].bits.vc_sel.`1`, vcalloc_q.io.deq.bits.vc_sel.`1`
connect io.salloc_req[0].bits.vc_sel.`2`, vcalloc_q.io.deq.bits.vc_sel.`2`
connect io.salloc_req[0].bits.vc_sel.`3`, vcalloc_q.io.deq.bits.vc_sel.`3`
connect io.salloc_req[0].bits.tail, vcalloc_buffer.io.deq.bits.tail
node c_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0])
node c_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[4], vcalloc_q.io.deq.bits.vc_sel.`0`[3])
node c_hi = cat(c_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[2])
node _c_T = cat(c_hi, c_lo)
node c_lo_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`1`[0], _c_T)
node c_hi_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`3`[0], vcalloc_q.io.deq.bits.vc_sel.`2`[0])
node _c_T_1 = cat(c_hi_1, c_lo_1)
node c_lo_2 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node c_hi_hi_1 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3])
node c_hi_2 = cat(c_hi_hi_1, io.out_credit_available.`0`[2])
node _c_T_2 = cat(c_hi_2, c_lo_2)
node c_lo_3 = cat(io.out_credit_available.`1`[0], _c_T_2)
node c_hi_3 = cat(io.out_credit_available.`3`[0], io.out_credit_available.`2`[0])
node _c_T_3 = cat(c_hi_3, c_lo_3)
node _c_T_4 = and(_c_T_1, _c_T_3)
node c = neq(_c_T_4, UInt<1>(0h0))
node _io_salloc_req_0_valid_T = and(vcalloc_buffer.io.deq.valid, vcalloc_q.io.deq.valid)
node _io_salloc_req_0_valid_T_1 = and(_io_salloc_req_0_valid_T, c)
node _io_salloc_req_0_valid_T_2 = eq(io.block, UInt<1>(0h0))
node _io_salloc_req_0_valid_T_3 = and(_io_salloc_req_0_valid_T_1, _io_salloc_req_0_valid_T_2)
connect io.salloc_req[0].valid, _io_salloc_req_0_valid_T_3
node _vcalloc_buffer_io_deq_ready_T = and(io.salloc_req[0].ready, vcalloc_q.io.deq.valid)
node _vcalloc_buffer_io_deq_ready_T_1 = and(_vcalloc_buffer_io_deq_ready_T, c)
node _vcalloc_buffer_io_deq_ready_T_2 = eq(io.block, UInt<1>(0h0))
node _vcalloc_buffer_io_deq_ready_T_3 = and(_vcalloc_buffer_io_deq_ready_T_1, _vcalloc_buffer_io_deq_ready_T_2)
connect vcalloc_buffer.io.deq.ready, _vcalloc_buffer_io_deq_ready_T_3
node _vcalloc_q_io_deq_ready_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid)
node _vcalloc_q_io_deq_ready_T_1 = and(vcalloc_buffer.io.deq.bits.tail, _vcalloc_q_io_deq_ready_T)
connect vcalloc_q.io.deq.ready, _vcalloc_q_io_deq_ready_T_1
reg out_bundle : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}, clock
connect io.out[0], out_bundle
node _out_bundle_valid_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid)
connect out_bundle.valid, _out_bundle_valid_T
connect out_bundle.bits.flit, vcalloc_buffer.io.deq.bits
connect out_bundle.bits.flit.virt_channel_id, UInt<1>(0h0)
node _out_channel_oh_T = or(vcalloc_q.io.deq.bits.vc_sel.`0`[0], vcalloc_q.io.deq.bits.vc_sel.`0`[1])
node _out_channel_oh_T_1 = or(_out_channel_oh_T, vcalloc_q.io.deq.bits.vc_sel.`0`[2])
node _out_channel_oh_T_2 = or(_out_channel_oh_T_1, vcalloc_q.io.deq.bits.vc_sel.`0`[3])
node out_channel_oh_0 = or(_out_channel_oh_T_2, vcalloc_q.io.deq.bits.vc_sel.`0`[4])
node out_bundle_bits_out_virt_channel_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0])
node out_bundle_bits_out_virt_channel_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[4], vcalloc_q.io.deq.bits.vc_sel.`0`[3])
node out_bundle_bits_out_virt_channel_hi = cat(out_bundle_bits_out_virt_channel_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[2])
node _out_bundle_bits_out_virt_channel_T = cat(out_bundle_bits_out_virt_channel_hi, out_bundle_bits_out_virt_channel_lo)
node out_bundle_bits_out_virt_channel_hi_1 = bits(_out_bundle_bits_out_virt_channel_T, 4, 4)
node out_bundle_bits_out_virt_channel_lo_1 = bits(_out_bundle_bits_out_virt_channel_T, 3, 0)
node _out_bundle_bits_out_virt_channel_T_1 = orr(out_bundle_bits_out_virt_channel_hi_1)
node _out_bundle_bits_out_virt_channel_T_2 = or(out_bundle_bits_out_virt_channel_hi_1, out_bundle_bits_out_virt_channel_lo_1)
node out_bundle_bits_out_virt_channel_hi_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 3, 2)
node out_bundle_bits_out_virt_channel_lo_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 1, 0)
node _out_bundle_bits_out_virt_channel_T_3 = orr(out_bundle_bits_out_virt_channel_hi_2)
node _out_bundle_bits_out_virt_channel_T_4 = or(out_bundle_bits_out_virt_channel_hi_2, out_bundle_bits_out_virt_channel_lo_2)
node _out_bundle_bits_out_virt_channel_T_5 = bits(_out_bundle_bits_out_virt_channel_T_4, 1, 1)
node _out_bundle_bits_out_virt_channel_T_6 = cat(_out_bundle_bits_out_virt_channel_T_3, _out_bundle_bits_out_virt_channel_T_5)
node _out_bundle_bits_out_virt_channel_T_7 = cat(_out_bundle_bits_out_virt_channel_T_1, _out_bundle_bits_out_virt_channel_T_6)
node _out_bundle_bits_out_virt_channel_T_8 = mux(out_channel_oh_0, _out_bundle_bits_out_virt_channel_T_7, UInt<1>(0h0))
node _out_bundle_bits_out_virt_channel_T_9 = mux(vcalloc_q.io.deq.bits.vc_sel.`1`[0], UInt<1>(0h0), UInt<1>(0h0))
node _out_bundle_bits_out_virt_channel_T_10 = mux(vcalloc_q.io.deq.bits.vc_sel.`2`[0], UInt<1>(0h0), UInt<1>(0h0))
node _out_bundle_bits_out_virt_channel_T_11 = mux(vcalloc_q.io.deq.bits.vc_sel.`3`[0], UInt<1>(0h0), UInt<1>(0h0))
node _out_bundle_bits_out_virt_channel_T_12 = or(_out_bundle_bits_out_virt_channel_T_8, _out_bundle_bits_out_virt_channel_T_9)
node _out_bundle_bits_out_virt_channel_T_13 = or(_out_bundle_bits_out_virt_channel_T_12, _out_bundle_bits_out_virt_channel_T_10)
node _out_bundle_bits_out_virt_channel_T_14 = or(_out_bundle_bits_out_virt_channel_T_13, _out_bundle_bits_out_virt_channel_T_11)
wire _out_bundle_bits_out_virt_channel_WIRE : UInt<3>
connect _out_bundle_bits_out_virt_channel_WIRE, _out_bundle_bits_out_virt_channel_T_14
connect out_bundle.bits.out_virt_channel, _out_bundle_bits_out_virt_channel_WIRE
node _io_debug_va_stall_T = eq(io.vcalloc_req.ready, UInt<1>(0h0))
node _io_debug_va_stall_T_1 = and(io.vcalloc_req.valid, _io_debug_va_stall_T)
connect io.debug.va_stall, _io_debug_va_stall_T_1
node _io_debug_sa_stall_T = eq(io.salloc_req[0].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_1 = and(io.salloc_req[0].valid, _io_debug_sa_stall_T)
connect io.debug.sa_stall, _io_debug_sa_stall_T_1 | module IngressUnit_53( // @[IngressUnit.scala:11:7]
input clock, // @[IngressUnit.scala:11:7]
input reset, // @[IngressUnit.scala:11:7]
input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_3_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_3_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_2_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_3, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_4, // @[IngressUnit.scala:24:14]
input io_out_credit_available_3_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_2_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_1_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_1, // @[IngressUnit.scala:24:14]
input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_3_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14]
output io_out_0_valid, // @[IngressUnit.scala:24:14]
output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14]
output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14]
output [72:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14]
output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14]
output [4:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14]
output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14]
output [4:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14]
output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14]
output [2:0] io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14]
output io_in_ready, // @[IngressUnit.scala:24:14]
input io_in_valid, // @[IngressUnit.scala:24:14]
input io_in_bits_head, // @[IngressUnit.scala:24:14]
input io_in_bits_tail, // @[IngressUnit.scala:24:14]
input [72:0] io_in_bits_payload // @[IngressUnit.scala:24:14]
);
wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_3_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_2_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_2; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_3; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_4; // @[IngressUnit.scala:76:25]
wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_bits_head; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30]
wire [72:0] _vcalloc_buffer_io_deq_bits_payload; // @[IngressUnit.scala:75:30]
wire [2:0] _vcalloc_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:75:30]
wire [4:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:75:30]
wire [1:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:75:30]
wire [4:0] _vcalloc_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:75:30]
wire [1:0] _vcalloc_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:75:30]
wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23]
wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23]
wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28]
wire [72:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28]
wire [2:0] _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28]
wire [4:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28]
wire [1:0] _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28]
wire [4:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28]
wire [1:0] _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28]
wire [2:0] _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28]
wire io_router_req_valid = io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head; // @[IngressUnit.scala:26:28, :58:{38,67}]
wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}]
wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid | ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready | ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready | ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29]
wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35] |
Generate the Verilog code corresponding to this FIRRTL code module TLAFromNoC_5 :
input clock : Clock
input reset : Reset
output io : { protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}
wire protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
regreset is_const : UInt<1>, clock, reset, UInt<1>(0h1)
reg const_reg : UInt<46>, clock
node const = mux(io.flit.bits.head, io.flit.bits.payload, const_reg)
node _io_flit_ready_T = eq(io.flit.bits.tail, UInt<1>(0h0))
node _io_flit_ready_T_1 = and(is_const, _io_flit_ready_T)
node _io_flit_ready_T_2 = or(_io_flit_ready_T_1, protocol.ready)
connect io.flit.ready, _io_flit_ready_T_2
node _protocol_valid_T = eq(is_const, UInt<1>(0h0))
node _protocol_valid_T_1 = or(_protocol_valid_T, io.flit.bits.tail)
node _protocol_valid_T_2 = and(_protocol_valid_T_1, io.flit.valid)
connect protocol.valid, _protocol_valid_T_2
wire _protocol_bits_echo_WIRE : { }
wire _protocol_bits_echo_WIRE_1 : UInt<0>
connect _protocol_bits_echo_WIRE_1, const
connect protocol.bits.echo, _protocol_bits_echo_WIRE
node _T = shr(const, 0)
wire _protocol_bits_user_WIRE : { }
wire _protocol_bits_user_WIRE_1 : UInt<0>
connect _protocol_bits_user_WIRE_1, _T
connect protocol.bits.user, _protocol_bits_user_WIRE
node _T_1 = shr(_T, 0)
wire _protocol_bits_address_WIRE : UInt<29>
connect _protocol_bits_address_WIRE, _T_1
connect protocol.bits.address, _protocol_bits_address_WIRE
node _T_2 = shr(_T_1, 29)
wire _protocol_bits_source_WIRE : UInt<7>
connect _protocol_bits_source_WIRE, _T_2
connect protocol.bits.source, _protocol_bits_source_WIRE
node _T_3 = shr(_T_2, 7)
wire _protocol_bits_size_WIRE : UInt<4>
connect _protocol_bits_size_WIRE, _T_3
connect protocol.bits.size, _protocol_bits_size_WIRE
node _T_4 = shr(_T_3, 4)
wire _protocol_bits_param_WIRE : UInt<3>
connect _protocol_bits_param_WIRE, _T_4
connect protocol.bits.param, _protocol_bits_param_WIRE
node _T_5 = shr(_T_4, 3)
wire _protocol_bits_opcode_WIRE : UInt<3>
connect _protocol_bits_opcode_WIRE, _T_5
connect protocol.bits.opcode, _protocol_bits_opcode_WIRE
node _T_6 = shr(_T_5, 3)
wire _protocol_bits_corrupt_WIRE : UInt<1>
connect _protocol_bits_corrupt_WIRE, io.flit.bits.payload
connect protocol.bits.corrupt, _protocol_bits_corrupt_WIRE
node _T_7 = shr(io.flit.bits.payload, 1)
wire _protocol_bits_data_WIRE : UInt<64>
connect _protocol_bits_data_WIRE, _T_7
connect protocol.bits.data, _protocol_bits_data_WIRE
node _T_8 = shr(_T_7, 64)
wire _protocol_bits_mask_WIRE : UInt<8>
connect _protocol_bits_mask_WIRE, _T_8
connect protocol.bits.mask, _protocol_bits_mask_WIRE
node _T_9 = shr(_T_8, 8)
node _T_10 = and(io.flit.ready, io.flit.valid)
node _T_11 = and(_T_10, io.flit.bits.head)
when _T_11 :
connect is_const, UInt<1>(0h0)
connect const_reg, io.flit.bits.payload
node _T_12 = and(io.flit.ready, io.flit.valid)
node _T_13 = and(_T_12, io.flit.bits.tail)
when _T_13 :
connect is_const, UInt<1>(0h1)
connect io.protocol, protocol
when io.flit.bits.head :
node _io_protocol_bits_mask_T = not(UInt<8>(0h0))
connect io.protocol.bits.mask, _io_protocol_bits_mask_T | module TLAFromNoC_5( // @[TilelinkAdapters.scala:128:7]
input clock, // @[TilelinkAdapters.scala:128:7]
input reset, // @[TilelinkAdapters.scala:128:7]
input io_protocol_ready, // @[TilelinkAdapters.scala:56:14]
output io_protocol_valid, // @[TilelinkAdapters.scala:56:14]
output [2:0] io_protocol_bits_opcode, // @[TilelinkAdapters.scala:56:14]
output [2:0] io_protocol_bits_param, // @[TilelinkAdapters.scala:56:14]
output [3:0] io_protocol_bits_size, // @[TilelinkAdapters.scala:56:14]
output [6:0] io_protocol_bits_source, // @[TilelinkAdapters.scala:56:14]
output [28:0] io_protocol_bits_address, // @[TilelinkAdapters.scala:56:14]
output [7:0] io_protocol_bits_mask, // @[TilelinkAdapters.scala:56:14]
output [63:0] io_protocol_bits_data, // @[TilelinkAdapters.scala:56:14]
output io_protocol_bits_corrupt, // @[TilelinkAdapters.scala:56:14]
output io_flit_ready, // @[TilelinkAdapters.scala:56:14]
input io_flit_valid, // @[TilelinkAdapters.scala:56:14]
input io_flit_bits_head, // @[TilelinkAdapters.scala:56:14]
input io_flit_bits_tail, // @[TilelinkAdapters.scala:56:14]
input [72:0] io_flit_bits_payload // @[TilelinkAdapters.scala:56:14]
);
reg is_const; // @[TilelinkAdapters.scala:68:25]
reg [45:0] const_reg; // @[TilelinkAdapters.scala:69:22]
wire [45:0] const_0 = io_flit_bits_head ? io_flit_bits_payload[45:0] : const_reg; // @[TilelinkAdapters.scala:56:14, :69:22, :70:18]
wire io_flit_ready_0 = is_const & ~io_flit_bits_tail | io_protocol_ready; // @[TilelinkAdapters.scala:68:25, :71:{30,33,53}]
wire _GEN = io_flit_ready_0 & io_flit_valid; // @[Decoupled.scala:51:35]
wire _GEN_0 = _GEN & io_flit_bits_head; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[TilelinkAdapters.scala:128:7]
if (reset) // @[TilelinkAdapters.scala:128:7]
is_const <= 1'h1; // @[TilelinkAdapters.scala:68:25, :128:7]
else // @[TilelinkAdapters.scala:128:7]
is_const <= _GEN & io_flit_bits_tail | ~_GEN_0 & is_const; // @[Decoupled.scala:51:35]
if (_GEN_0) // @[TilelinkAdapters.scala:84:22]
const_reg <= io_flit_bits_payload[45:0]; // @[TilelinkAdapters.scala:56:14, :69:22]
always @(posedge) |
Generate the Verilog code corresponding to this FIRRTL code module MulRecFN_18 :
output io : { flip a : UInt<33>, flip b : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
inst mulRawFN of MulRawFN_18
node mulRawFN_io_a_exp = bits(io.a, 31, 23)
node _mulRawFN_io_a_isZero_T = bits(mulRawFN_io_a_exp, 8, 6)
node mulRawFN_io_a_isZero = eq(_mulRawFN_io_a_isZero_T, UInt<1>(0h0))
node _mulRawFN_io_a_isSpecial_T = bits(mulRawFN_io_a_exp, 8, 7)
node mulRawFN_io_a_isSpecial = eq(_mulRawFN_io_a_isSpecial_T, UInt<2>(0h3))
wire mulRawFN_io_a_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _mulRawFN_io_a_out_isNaN_T = bits(mulRawFN_io_a_exp, 6, 6)
node _mulRawFN_io_a_out_isNaN_T_1 = and(mulRawFN_io_a_isSpecial, _mulRawFN_io_a_out_isNaN_T)
connect mulRawFN_io_a_out.isNaN, _mulRawFN_io_a_out_isNaN_T_1
node _mulRawFN_io_a_out_isInf_T = bits(mulRawFN_io_a_exp, 6, 6)
node _mulRawFN_io_a_out_isInf_T_1 = eq(_mulRawFN_io_a_out_isInf_T, UInt<1>(0h0))
node _mulRawFN_io_a_out_isInf_T_2 = and(mulRawFN_io_a_isSpecial, _mulRawFN_io_a_out_isInf_T_1)
connect mulRawFN_io_a_out.isInf, _mulRawFN_io_a_out_isInf_T_2
connect mulRawFN_io_a_out.isZero, mulRawFN_io_a_isZero
node _mulRawFN_io_a_out_sign_T = bits(io.a, 32, 32)
connect mulRawFN_io_a_out.sign, _mulRawFN_io_a_out_sign_T
node _mulRawFN_io_a_out_sExp_T = cvt(mulRawFN_io_a_exp)
connect mulRawFN_io_a_out.sExp, _mulRawFN_io_a_out_sExp_T
node _mulRawFN_io_a_out_sig_T = eq(mulRawFN_io_a_isZero, UInt<1>(0h0))
node _mulRawFN_io_a_out_sig_T_1 = cat(UInt<1>(0h0), _mulRawFN_io_a_out_sig_T)
node _mulRawFN_io_a_out_sig_T_2 = bits(io.a, 22, 0)
node _mulRawFN_io_a_out_sig_T_3 = cat(_mulRawFN_io_a_out_sig_T_1, _mulRawFN_io_a_out_sig_T_2)
connect mulRawFN_io_a_out.sig, _mulRawFN_io_a_out_sig_T_3
connect mulRawFN.io.a.sig, mulRawFN_io_a_out.sig
connect mulRawFN.io.a.sExp, mulRawFN_io_a_out.sExp
connect mulRawFN.io.a.sign, mulRawFN_io_a_out.sign
connect mulRawFN.io.a.isZero, mulRawFN_io_a_out.isZero
connect mulRawFN.io.a.isInf, mulRawFN_io_a_out.isInf
connect mulRawFN.io.a.isNaN, mulRawFN_io_a_out.isNaN
node mulRawFN_io_b_exp = bits(io.b, 31, 23)
node _mulRawFN_io_b_isZero_T = bits(mulRawFN_io_b_exp, 8, 6)
node mulRawFN_io_b_isZero = eq(_mulRawFN_io_b_isZero_T, UInt<1>(0h0))
node _mulRawFN_io_b_isSpecial_T = bits(mulRawFN_io_b_exp, 8, 7)
node mulRawFN_io_b_isSpecial = eq(_mulRawFN_io_b_isSpecial_T, UInt<2>(0h3))
wire mulRawFN_io_b_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _mulRawFN_io_b_out_isNaN_T = bits(mulRawFN_io_b_exp, 6, 6)
node _mulRawFN_io_b_out_isNaN_T_1 = and(mulRawFN_io_b_isSpecial, _mulRawFN_io_b_out_isNaN_T)
connect mulRawFN_io_b_out.isNaN, _mulRawFN_io_b_out_isNaN_T_1
node _mulRawFN_io_b_out_isInf_T = bits(mulRawFN_io_b_exp, 6, 6)
node _mulRawFN_io_b_out_isInf_T_1 = eq(_mulRawFN_io_b_out_isInf_T, UInt<1>(0h0))
node _mulRawFN_io_b_out_isInf_T_2 = and(mulRawFN_io_b_isSpecial, _mulRawFN_io_b_out_isInf_T_1)
connect mulRawFN_io_b_out.isInf, _mulRawFN_io_b_out_isInf_T_2
connect mulRawFN_io_b_out.isZero, mulRawFN_io_b_isZero
node _mulRawFN_io_b_out_sign_T = bits(io.b, 32, 32)
connect mulRawFN_io_b_out.sign, _mulRawFN_io_b_out_sign_T
node _mulRawFN_io_b_out_sExp_T = cvt(mulRawFN_io_b_exp)
connect mulRawFN_io_b_out.sExp, _mulRawFN_io_b_out_sExp_T
node _mulRawFN_io_b_out_sig_T = eq(mulRawFN_io_b_isZero, UInt<1>(0h0))
node _mulRawFN_io_b_out_sig_T_1 = cat(UInt<1>(0h0), _mulRawFN_io_b_out_sig_T)
node _mulRawFN_io_b_out_sig_T_2 = bits(io.b, 22, 0)
node _mulRawFN_io_b_out_sig_T_3 = cat(_mulRawFN_io_b_out_sig_T_1, _mulRawFN_io_b_out_sig_T_2)
connect mulRawFN_io_b_out.sig, _mulRawFN_io_b_out_sig_T_3
connect mulRawFN.io.b.sig, mulRawFN_io_b_out.sig
connect mulRawFN.io.b.sExp, mulRawFN_io_b_out.sExp
connect mulRawFN.io.b.sign, mulRawFN_io_b_out.sign
connect mulRawFN.io.b.isZero, mulRawFN_io_b_out.isZero
connect mulRawFN.io.b.isInf, mulRawFN_io_b_out.isInf
connect mulRawFN.io.b.isNaN, mulRawFN_io_b_out.isNaN
inst roundRawFNToRecFN of RoundRawFNToRecFN_e8_s24_59
connect roundRawFNToRecFN.io.invalidExc, mulRawFN.io.invalidExc
connect roundRawFNToRecFN.io.infiniteExc, UInt<1>(0h0)
connect roundRawFNToRecFN.io.in.sig, mulRawFN.io.rawOut.sig
connect roundRawFNToRecFN.io.in.sExp, mulRawFN.io.rawOut.sExp
connect roundRawFNToRecFN.io.in.sign, mulRawFN.io.rawOut.sign
connect roundRawFNToRecFN.io.in.isZero, mulRawFN.io.rawOut.isZero
connect roundRawFNToRecFN.io.in.isInf, mulRawFN.io.rawOut.isInf
connect roundRawFNToRecFN.io.in.isNaN, mulRawFN.io.rawOut.isNaN
connect roundRawFNToRecFN.io.roundingMode, io.roundingMode
connect roundRawFNToRecFN.io.detectTininess, io.detectTininess
connect io.out, roundRawFNToRecFN.io.out
connect io.exceptionFlags, roundRawFNToRecFN.io.exceptionFlags | module MulRecFN_18( // @[MulRecFN.scala:100:7]
input [32:0] io_a, // @[MulRecFN.scala:102:16]
input [32:0] io_b, // @[MulRecFN.scala:102:16]
output [32:0] io_out // @[MulRecFN.scala:102:16]
);
wire _mulRawFN_io_invalidExc; // @[MulRecFN.scala:113:26]
wire _mulRawFN_io_rawOut_isNaN; // @[MulRecFN.scala:113:26]
wire _mulRawFN_io_rawOut_isInf; // @[MulRecFN.scala:113:26]
wire _mulRawFN_io_rawOut_isZero; // @[MulRecFN.scala:113:26]
wire _mulRawFN_io_rawOut_sign; // @[MulRecFN.scala:113:26]
wire [9:0] _mulRawFN_io_rawOut_sExp; // @[MulRecFN.scala:113:26]
wire [26:0] _mulRawFN_io_rawOut_sig; // @[MulRecFN.scala:113:26]
wire [32:0] io_a_0 = io_a; // @[MulRecFN.scala:100:7]
wire [32:0] io_b_0 = io_b; // @[MulRecFN.scala:100:7]
wire io_detectTininess = 1'h1; // @[MulRecFN.scala:100:7, :102:16, :121:15]
wire [2:0] io_roundingMode = 3'h0; // @[MulRecFN.scala:100:7, :102:16, :121:15]
wire [32:0] io_out_0; // @[MulRecFN.scala:100:7]
wire [4:0] io_exceptionFlags; // @[MulRecFN.scala:100:7]
wire [8:0] mulRawFN_io_a_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _mulRawFN_io_a_isZero_T = mulRawFN_io_a_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire mulRawFN_io_a_isZero = _mulRawFN_io_a_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire mulRawFN_io_a_out_isZero = mulRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _mulRawFN_io_a_isSpecial_T = mulRawFN_io_a_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire mulRawFN_io_a_isSpecial = &_mulRawFN_io_a_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _mulRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _mulRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _mulRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _mulRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _mulRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire mulRawFN_io_a_out_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire mulRawFN_io_a_out_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire mulRawFN_io_a_out_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] mulRawFN_io_a_out_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] mulRawFN_io_a_out_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _mulRawFN_io_a_out_isNaN_T = mulRawFN_io_a_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _mulRawFN_io_a_out_isInf_T = mulRawFN_io_a_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _mulRawFN_io_a_out_isNaN_T_1 = mulRawFN_io_a_isSpecial & _mulRawFN_io_a_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign mulRawFN_io_a_out_isNaN = _mulRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _mulRawFN_io_a_out_isInf_T_1 = ~_mulRawFN_io_a_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _mulRawFN_io_a_out_isInf_T_2 = mulRawFN_io_a_isSpecial & _mulRawFN_io_a_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign mulRawFN_io_a_out_isInf = _mulRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _mulRawFN_io_a_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign mulRawFN_io_a_out_sign = _mulRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _mulRawFN_io_a_out_sExp_T = {1'h0, mulRawFN_io_a_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign mulRawFN_io_a_out_sExp = _mulRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _mulRawFN_io_a_out_sig_T = ~mulRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _mulRawFN_io_a_out_sig_T_1 = {1'h0, _mulRawFN_io_a_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _mulRawFN_io_a_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _mulRawFN_io_a_out_sig_T_3 = {_mulRawFN_io_a_out_sig_T_1, _mulRawFN_io_a_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign mulRawFN_io_a_out_sig = _mulRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [8:0] mulRawFN_io_b_exp = io_b_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _mulRawFN_io_b_isZero_T = mulRawFN_io_b_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire mulRawFN_io_b_isZero = _mulRawFN_io_b_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire mulRawFN_io_b_out_isZero = mulRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _mulRawFN_io_b_isSpecial_T = mulRawFN_io_b_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire mulRawFN_io_b_isSpecial = &_mulRawFN_io_b_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _mulRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _mulRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _mulRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _mulRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _mulRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire mulRawFN_io_b_out_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire mulRawFN_io_b_out_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire mulRawFN_io_b_out_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] mulRawFN_io_b_out_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] mulRawFN_io_b_out_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _mulRawFN_io_b_out_isNaN_T = mulRawFN_io_b_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _mulRawFN_io_b_out_isInf_T = mulRawFN_io_b_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _mulRawFN_io_b_out_isNaN_T_1 = mulRawFN_io_b_isSpecial & _mulRawFN_io_b_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign mulRawFN_io_b_out_isNaN = _mulRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _mulRawFN_io_b_out_isInf_T_1 = ~_mulRawFN_io_b_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _mulRawFN_io_b_out_isInf_T_2 = mulRawFN_io_b_isSpecial & _mulRawFN_io_b_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign mulRawFN_io_b_out_isInf = _mulRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _mulRawFN_io_b_out_sign_T = io_b_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign mulRawFN_io_b_out_sign = _mulRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _mulRawFN_io_b_out_sExp_T = {1'h0, mulRawFN_io_b_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign mulRawFN_io_b_out_sExp = _mulRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _mulRawFN_io_b_out_sig_T = ~mulRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _mulRawFN_io_b_out_sig_T_1 = {1'h0, _mulRawFN_io_b_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _mulRawFN_io_b_out_sig_T_2 = io_b_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _mulRawFN_io_b_out_sig_T_3 = {_mulRawFN_io_b_out_sig_T_1, _mulRawFN_io_b_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign mulRawFN_io_b_out_sig = _mulRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
MulRawFN_18 mulRawFN ( // @[MulRecFN.scala:113:26]
.io_a_isNaN (mulRawFN_io_a_out_isNaN), // @[rawFloatFromRecFN.scala:55:23]
.io_a_isInf (mulRawFN_io_a_out_isInf), // @[rawFloatFromRecFN.scala:55:23]
.io_a_isZero (mulRawFN_io_a_out_isZero), // @[rawFloatFromRecFN.scala:55:23]
.io_a_sign (mulRawFN_io_a_out_sign), // @[rawFloatFromRecFN.scala:55:23]
.io_a_sExp (mulRawFN_io_a_out_sExp), // @[rawFloatFromRecFN.scala:55:23]
.io_a_sig (mulRawFN_io_a_out_sig), // @[rawFloatFromRecFN.scala:55:23]
.io_b_isNaN (mulRawFN_io_b_out_isNaN), // @[rawFloatFromRecFN.scala:55:23]
.io_b_isInf (mulRawFN_io_b_out_isInf), // @[rawFloatFromRecFN.scala:55:23]
.io_b_isZero (mulRawFN_io_b_out_isZero), // @[rawFloatFromRecFN.scala:55:23]
.io_b_sign (mulRawFN_io_b_out_sign), // @[rawFloatFromRecFN.scala:55:23]
.io_b_sExp (mulRawFN_io_b_out_sExp), // @[rawFloatFromRecFN.scala:55:23]
.io_b_sig (mulRawFN_io_b_out_sig), // @[rawFloatFromRecFN.scala:55:23]
.io_invalidExc (_mulRawFN_io_invalidExc),
.io_rawOut_isNaN (_mulRawFN_io_rawOut_isNaN),
.io_rawOut_isInf (_mulRawFN_io_rawOut_isInf),
.io_rawOut_isZero (_mulRawFN_io_rawOut_isZero),
.io_rawOut_sign (_mulRawFN_io_rawOut_sign),
.io_rawOut_sExp (_mulRawFN_io_rawOut_sExp),
.io_rawOut_sig (_mulRawFN_io_rawOut_sig)
); // @[MulRecFN.scala:113:26]
RoundRawFNToRecFN_e8_s24_59 roundRawFNToRecFN ( // @[MulRecFN.scala:121:15]
.io_invalidExc (_mulRawFN_io_invalidExc), // @[MulRecFN.scala:113:26]
.io_in_isNaN (_mulRawFN_io_rawOut_isNaN), // @[MulRecFN.scala:113:26]
.io_in_isInf (_mulRawFN_io_rawOut_isInf), // @[MulRecFN.scala:113:26]
.io_in_isZero (_mulRawFN_io_rawOut_isZero), // @[MulRecFN.scala:113:26]
.io_in_sign (_mulRawFN_io_rawOut_sign), // @[MulRecFN.scala:113:26]
.io_in_sExp (_mulRawFN_io_rawOut_sExp), // @[MulRecFN.scala:113:26]
.io_in_sig (_mulRawFN_io_rawOut_sig), // @[MulRecFN.scala:113:26]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags)
); // @[MulRecFN.scala:121:15]
assign io_out = io_out_0; // @[MulRecFN.scala:100:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_11 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<13>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<13>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<13>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 12, 0)
node _source_ok_T = shr(io.in.a.bits.source, 13)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<13>(0h100f))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T_5
node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<13>(0h0))
node uncommonBits = bits(_uncommonBits_T, 12, 0)
node _T_4 = shr(io.in.a.bits.source, 13)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<13>(0h100f))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_16, UInt<1>(0h1), "") : assert_1
node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_20 :
node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_23 = and(_T_21, _T_22)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<13>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 12, 0)
node _T_24 = shr(io.in.a.bits.source, 13)
node _T_25 = eq(_T_24, UInt<1>(0h0))
node _T_26 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_27 = and(_T_25, _T_26)
node _T_28 = leq(uncommonBits_1, UInt<13>(0h100f))
node _T_29 = and(_T_27, _T_28)
node _T_30 = and(_T_23, _T_29)
node _T_31 = or(UInt<1>(0h0), _T_30)
node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_33 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_34 = cvt(_T_33)
node _T_35 = and(_T_34, asSInt(UInt<13>(0h1000)))
node _T_36 = asSInt(_T_35)
node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0)))
node _T_38 = and(_T_32, _T_37)
node _T_39 = or(UInt<1>(0h0), _T_38)
node _T_40 = and(_T_31, _T_39)
node _T_41 = asUInt(reset)
node _T_42 = eq(_T_41, UInt<1>(0h0))
when _T_42 :
node _T_43 = eq(_T_40, UInt<1>(0h0))
when _T_43 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_40, UInt<1>(0h1), "") : assert_2
node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_46 = and(_T_44, _T_45)
node _T_47 = or(UInt<1>(0h0), _T_46)
node _T_48 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_49 = cvt(_T_48)
node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000)))
node _T_51 = asSInt(_T_50)
node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0)))
node _T_53 = and(_T_47, _T_52)
node _T_54 = or(UInt<1>(0h0), _T_53)
node _T_55 = and(UInt<1>(0h0), _T_54)
node _T_56 = asUInt(reset)
node _T_57 = eq(_T_56, UInt<1>(0h0))
when _T_57 :
node _T_58 = eq(_T_55, UInt<1>(0h0))
when _T_58 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_55, UInt<1>(0h1), "") : assert_3
node _T_59 = asUInt(reset)
node _T_60 = eq(_T_59, UInt<1>(0h0))
when _T_60 :
node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_61 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_63 = asUInt(reset)
node _T_64 = eq(_T_63, UInt<1>(0h0))
when _T_64 :
node _T_65 = eq(_T_62, UInt<1>(0h0))
when _T_65 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_62, UInt<1>(0h1), "") : assert_5
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(is_aligned, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_70 = asUInt(reset)
node _T_71 = eq(_T_70, UInt<1>(0h0))
when _T_71 :
node _T_72 = eq(_T_69, UInt<1>(0h0))
when _T_72 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_69, UInt<1>(0h1), "") : assert_7
node _T_73 = not(io.in.a.bits.mask)
node _T_74 = eq(_T_73, UInt<1>(0h0))
node _T_75 = asUInt(reset)
node _T_76 = eq(_T_75, UInt<1>(0h0))
when _T_76 :
node _T_77 = eq(_T_74, UInt<1>(0h0))
when _T_77 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_74, UInt<1>(0h1), "") : assert_8
node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_79 = asUInt(reset)
node _T_80 = eq(_T_79, UInt<1>(0h0))
when _T_80 :
node _T_81 = eq(_T_78, UInt<1>(0h0))
when _T_81 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_78, UInt<1>(0h1), "") : assert_9
node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_82 :
node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_85 = and(_T_83, _T_84)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<13>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 12, 0)
node _T_86 = shr(io.in.a.bits.source, 13)
node _T_87 = eq(_T_86, UInt<1>(0h0))
node _T_88 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_89 = and(_T_87, _T_88)
node _T_90 = leq(uncommonBits_2, UInt<13>(0h100f))
node _T_91 = and(_T_89, _T_90)
node _T_92 = and(_T_85, _T_91)
node _T_93 = or(UInt<1>(0h0), _T_92)
node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_95 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_96 = cvt(_T_95)
node _T_97 = and(_T_96, asSInt(UInt<13>(0h1000)))
node _T_98 = asSInt(_T_97)
node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = and(_T_94, _T_99)
node _T_101 = or(UInt<1>(0h0), _T_100)
node _T_102 = and(_T_93, _T_101)
node _T_103 = asUInt(reset)
node _T_104 = eq(_T_103, UInt<1>(0h0))
when _T_104 :
node _T_105 = eq(_T_102, UInt<1>(0h0))
when _T_105 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_102, UInt<1>(0h1), "") : assert_10
node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_108 = and(_T_106, _T_107)
node _T_109 = or(UInt<1>(0h0), _T_108)
node _T_110 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_111 = cvt(_T_110)
node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000)))
node _T_113 = asSInt(_T_112)
node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0)))
node _T_115 = and(_T_109, _T_114)
node _T_116 = or(UInt<1>(0h0), _T_115)
node _T_117 = and(UInt<1>(0h0), _T_116)
node _T_118 = asUInt(reset)
node _T_119 = eq(_T_118, UInt<1>(0h0))
when _T_119 :
node _T_120 = eq(_T_117, UInt<1>(0h0))
when _T_120 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_117, UInt<1>(0h1), "") : assert_11
node _T_121 = asUInt(reset)
node _T_122 = eq(_T_121, UInt<1>(0h0))
when _T_122 :
node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_125 = asUInt(reset)
node _T_126 = eq(_T_125, UInt<1>(0h0))
when _T_126 :
node _T_127 = eq(_T_124, UInt<1>(0h0))
when _T_127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_124, UInt<1>(0h1), "") : assert_13
node _T_128 = asUInt(reset)
node _T_129 = eq(_T_128, UInt<1>(0h0))
when _T_129 :
node _T_130 = eq(is_aligned, UInt<1>(0h0))
when _T_130 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_132 = asUInt(reset)
node _T_133 = eq(_T_132, UInt<1>(0h0))
when _T_133 :
node _T_134 = eq(_T_131, UInt<1>(0h0))
when _T_134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_131, UInt<1>(0h1), "") : assert_15
node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_136 = asUInt(reset)
node _T_137 = eq(_T_136, UInt<1>(0h0))
when _T_137 :
node _T_138 = eq(_T_135, UInt<1>(0h0))
when _T_138 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_135, UInt<1>(0h1), "") : assert_16
node _T_139 = not(io.in.a.bits.mask)
node _T_140 = eq(_T_139, UInt<1>(0h0))
node _T_141 = asUInt(reset)
node _T_142 = eq(_T_141, UInt<1>(0h0))
when _T_142 :
node _T_143 = eq(_T_140, UInt<1>(0h0))
when _T_143 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_140, UInt<1>(0h1), "") : assert_17
node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_145 = asUInt(reset)
node _T_146 = eq(_T_145, UInt<1>(0h0))
when _T_146 :
node _T_147 = eq(_T_144, UInt<1>(0h0))
when _T_147 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_144, UInt<1>(0h1), "") : assert_18
node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_148 :
node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_151 = and(_T_149, _T_150)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<13>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 12, 0)
node _T_152 = shr(io.in.a.bits.source, 13)
node _T_153 = eq(_T_152, UInt<1>(0h0))
node _T_154 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_155 = and(_T_153, _T_154)
node _T_156 = leq(uncommonBits_3, UInt<13>(0h100f))
node _T_157 = and(_T_155, _T_156)
node _T_158 = and(_T_151, _T_157)
node _T_159 = or(UInt<1>(0h0), _T_158)
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(_T_159, UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_159, UInt<1>(0h1), "") : assert_19
node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_165 = and(_T_163, _T_164)
node _T_166 = or(UInt<1>(0h0), _T_165)
node _T_167 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_168 = cvt(_T_167)
node _T_169 = and(_T_168, asSInt(UInt<13>(0h1000)))
node _T_170 = asSInt(_T_169)
node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0)))
node _T_172 = and(_T_166, _T_171)
node _T_173 = or(UInt<1>(0h0), _T_172)
node _T_174 = asUInt(reset)
node _T_175 = eq(_T_174, UInt<1>(0h0))
when _T_175 :
node _T_176 = eq(_T_173, UInt<1>(0h0))
when _T_176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_173, UInt<1>(0h1), "") : assert_20
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_180 = asUInt(reset)
node _T_181 = eq(_T_180, UInt<1>(0h0))
when _T_181 :
node _T_182 = eq(is_aligned, UInt<1>(0h0))
when _T_182 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_183, UInt<1>(0h1), "") : assert_23
node _T_187 = eq(io.in.a.bits.mask, mask)
node _T_188 = asUInt(reset)
node _T_189 = eq(_T_188, UInt<1>(0h0))
when _T_189 :
node _T_190 = eq(_T_187, UInt<1>(0h0))
when _T_190 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_187, UInt<1>(0h1), "") : assert_24
node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_192 = asUInt(reset)
node _T_193 = eq(_T_192, UInt<1>(0h0))
when _T_193 :
node _T_194 = eq(_T_191, UInt<1>(0h0))
when _T_194 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_191, UInt<1>(0h1), "") : assert_25
node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_195 :
node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_198 = and(_T_196, _T_197)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<13>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 12, 0)
node _T_199 = shr(io.in.a.bits.source, 13)
node _T_200 = eq(_T_199, UInt<1>(0h0))
node _T_201 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_202 = and(_T_200, _T_201)
node _T_203 = leq(uncommonBits_4, UInt<13>(0h100f))
node _T_204 = and(_T_202, _T_203)
node _T_205 = and(_T_198, _T_204)
node _T_206 = or(UInt<1>(0h0), _T_205)
node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_209 = and(_T_207, _T_208)
node _T_210 = or(UInt<1>(0h0), _T_209)
node _T_211 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_212 = cvt(_T_211)
node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000)))
node _T_214 = asSInt(_T_213)
node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0)))
node _T_216 = and(_T_210, _T_215)
node _T_217 = or(UInt<1>(0h0), _T_216)
node _T_218 = and(_T_206, _T_217)
node _T_219 = asUInt(reset)
node _T_220 = eq(_T_219, UInt<1>(0h0))
when _T_220 :
node _T_221 = eq(_T_218, UInt<1>(0h0))
when _T_221 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_218, UInt<1>(0h1), "") : assert_26
node _T_222 = asUInt(reset)
node _T_223 = eq(_T_222, UInt<1>(0h0))
when _T_223 :
node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_225 = asUInt(reset)
node _T_226 = eq(_T_225, UInt<1>(0h0))
when _T_226 :
node _T_227 = eq(is_aligned, UInt<1>(0h0))
when _T_227 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_229 = asUInt(reset)
node _T_230 = eq(_T_229, UInt<1>(0h0))
when _T_230 :
node _T_231 = eq(_T_228, UInt<1>(0h0))
when _T_231 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_228, UInt<1>(0h1), "") : assert_29
node _T_232 = eq(io.in.a.bits.mask, mask)
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_232, UInt<1>(0h1), "") : assert_30
node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_236 :
node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_239 = and(_T_237, _T_238)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<13>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 12, 0)
node _T_240 = shr(io.in.a.bits.source, 13)
node _T_241 = eq(_T_240, UInt<1>(0h0))
node _T_242 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_243 = and(_T_241, _T_242)
node _T_244 = leq(uncommonBits_5, UInt<13>(0h100f))
node _T_245 = and(_T_243, _T_244)
node _T_246 = and(_T_239, _T_245)
node _T_247 = or(UInt<1>(0h0), _T_246)
node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_250 = and(_T_248, _T_249)
node _T_251 = or(UInt<1>(0h0), _T_250)
node _T_252 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_253 = cvt(_T_252)
node _T_254 = and(_T_253, asSInt(UInt<13>(0h1000)))
node _T_255 = asSInt(_T_254)
node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0)))
node _T_257 = and(_T_251, _T_256)
node _T_258 = or(UInt<1>(0h0), _T_257)
node _T_259 = and(_T_247, _T_258)
node _T_260 = asUInt(reset)
node _T_261 = eq(_T_260, UInt<1>(0h0))
when _T_261 :
node _T_262 = eq(_T_259, UInt<1>(0h0))
when _T_262 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_259, UInt<1>(0h1), "") : assert_31
node _T_263 = asUInt(reset)
node _T_264 = eq(_T_263, UInt<1>(0h0))
when _T_264 :
node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_265 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_266 = asUInt(reset)
node _T_267 = eq(_T_266, UInt<1>(0h0))
when _T_267 :
node _T_268 = eq(is_aligned, UInt<1>(0h0))
when _T_268 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_270 = asUInt(reset)
node _T_271 = eq(_T_270, UInt<1>(0h0))
when _T_271 :
node _T_272 = eq(_T_269, UInt<1>(0h0))
when _T_272 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_269, UInt<1>(0h1), "") : assert_34
node _T_273 = not(mask)
node _T_274 = and(io.in.a.bits.mask, _T_273)
node _T_275 = eq(_T_274, UInt<1>(0h0))
node _T_276 = asUInt(reset)
node _T_277 = eq(_T_276, UInt<1>(0h0))
when _T_277 :
node _T_278 = eq(_T_275, UInt<1>(0h0))
when _T_278 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_275, UInt<1>(0h1), "") : assert_35
node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_279 :
node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_282 = and(_T_280, _T_281)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<13>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 12, 0)
node _T_283 = shr(io.in.a.bits.source, 13)
node _T_284 = eq(_T_283, UInt<1>(0h0))
node _T_285 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_286 = and(_T_284, _T_285)
node _T_287 = leq(uncommonBits_6, UInt<13>(0h100f))
node _T_288 = and(_T_286, _T_287)
node _T_289 = and(_T_282, _T_288)
node _T_290 = or(UInt<1>(0h0), _T_289)
node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_292 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_293 = cvt(_T_292)
node _T_294 = and(_T_293, asSInt(UInt<13>(0h1000)))
node _T_295 = asSInt(_T_294)
node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0)))
node _T_297 = and(_T_291, _T_296)
node _T_298 = or(UInt<1>(0h0), _T_297)
node _T_299 = and(_T_290, _T_298)
node _T_300 = asUInt(reset)
node _T_301 = eq(_T_300, UInt<1>(0h0))
when _T_301 :
node _T_302 = eq(_T_299, UInt<1>(0h0))
when _T_302 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_299, UInt<1>(0h1), "") : assert_36
node _T_303 = asUInt(reset)
node _T_304 = eq(_T_303, UInt<1>(0h0))
when _T_304 :
node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_305 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_306 = asUInt(reset)
node _T_307 = eq(_T_306, UInt<1>(0h0))
when _T_307 :
node _T_308 = eq(is_aligned, UInt<1>(0h0))
when _T_308 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_310 = asUInt(reset)
node _T_311 = eq(_T_310, UInt<1>(0h0))
when _T_311 :
node _T_312 = eq(_T_309, UInt<1>(0h0))
when _T_312 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_309, UInt<1>(0h1), "") : assert_39
node _T_313 = eq(io.in.a.bits.mask, mask)
node _T_314 = asUInt(reset)
node _T_315 = eq(_T_314, UInt<1>(0h0))
when _T_315 :
node _T_316 = eq(_T_313, UInt<1>(0h0))
when _T_316 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_313, UInt<1>(0h1), "") : assert_40
node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_317 :
node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_320 = and(_T_318, _T_319)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<13>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 12, 0)
node _T_321 = shr(io.in.a.bits.source, 13)
node _T_322 = eq(_T_321, UInt<1>(0h0))
node _T_323 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_324 = and(_T_322, _T_323)
node _T_325 = leq(uncommonBits_7, UInt<13>(0h100f))
node _T_326 = and(_T_324, _T_325)
node _T_327 = and(_T_320, _T_326)
node _T_328 = or(UInt<1>(0h0), _T_327)
node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_330 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_331 = cvt(_T_330)
node _T_332 = and(_T_331, asSInt(UInt<13>(0h1000)))
node _T_333 = asSInt(_T_332)
node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0)))
node _T_335 = and(_T_329, _T_334)
node _T_336 = or(UInt<1>(0h0), _T_335)
node _T_337 = and(_T_328, _T_336)
node _T_338 = asUInt(reset)
node _T_339 = eq(_T_338, UInt<1>(0h0))
when _T_339 :
node _T_340 = eq(_T_337, UInt<1>(0h0))
when _T_340 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_337, UInt<1>(0h1), "") : assert_41
node _T_341 = asUInt(reset)
node _T_342 = eq(_T_341, UInt<1>(0h0))
when _T_342 :
node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_343 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_344 = asUInt(reset)
node _T_345 = eq(_T_344, UInt<1>(0h0))
when _T_345 :
node _T_346 = eq(is_aligned, UInt<1>(0h0))
when _T_346 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_348 = asUInt(reset)
node _T_349 = eq(_T_348, UInt<1>(0h0))
when _T_349 :
node _T_350 = eq(_T_347, UInt<1>(0h0))
when _T_350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_347, UInt<1>(0h1), "") : assert_44
node _T_351 = eq(io.in.a.bits.mask, mask)
node _T_352 = asUInt(reset)
node _T_353 = eq(_T_352, UInt<1>(0h0))
when _T_353 :
node _T_354 = eq(_T_351, UInt<1>(0h0))
when _T_354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_351, UInt<1>(0h1), "") : assert_45
node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_355 :
node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_358 = and(_T_356, _T_357)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<13>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 12, 0)
node _T_359 = shr(io.in.a.bits.source, 13)
node _T_360 = eq(_T_359, UInt<1>(0h0))
node _T_361 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_362 = and(_T_360, _T_361)
node _T_363 = leq(uncommonBits_8, UInt<13>(0h100f))
node _T_364 = and(_T_362, _T_363)
node _T_365 = and(_T_358, _T_364)
node _T_366 = or(UInt<1>(0h0), _T_365)
node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_368 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_369 = cvt(_T_368)
node _T_370 = and(_T_369, asSInt(UInt<13>(0h1000)))
node _T_371 = asSInt(_T_370)
node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0)))
node _T_373 = and(_T_367, _T_372)
node _T_374 = or(UInt<1>(0h0), _T_373)
node _T_375 = and(_T_366, _T_374)
node _T_376 = asUInt(reset)
node _T_377 = eq(_T_376, UInt<1>(0h0))
when _T_377 :
node _T_378 = eq(_T_375, UInt<1>(0h0))
when _T_378 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_375, UInt<1>(0h1), "") : assert_46
node _T_379 = asUInt(reset)
node _T_380 = eq(_T_379, UInt<1>(0h0))
when _T_380 :
node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_381 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_382 = asUInt(reset)
node _T_383 = eq(_T_382, UInt<1>(0h0))
when _T_383 :
node _T_384 = eq(is_aligned, UInt<1>(0h0))
when _T_384 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_386 = asUInt(reset)
node _T_387 = eq(_T_386, UInt<1>(0h0))
when _T_387 :
node _T_388 = eq(_T_385, UInt<1>(0h0))
when _T_388 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_385, UInt<1>(0h1), "") : assert_49
node _T_389 = eq(io.in.a.bits.mask, mask)
node _T_390 = asUInt(reset)
node _T_391 = eq(_T_390, UInt<1>(0h0))
when _T_391 :
node _T_392 = eq(_T_389, UInt<1>(0h0))
when _T_392 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_389, UInt<1>(0h1), "") : assert_50
node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_394 = asUInt(reset)
node _T_395 = eq(_T_394, UInt<1>(0h0))
when _T_395 :
node _T_396 = eq(_T_393, UInt<1>(0h0))
when _T_396 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_393, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(_T_397, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_397, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<13>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 12, 0)
node _source_ok_T_6 = shr(io.in.d.bits.source, 13)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<13>(0h100f))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_11
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_401 :
node _T_402 = asUInt(reset)
node _T_403 = eq(_T_402, UInt<1>(0h0))
when _T_403 :
node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_404 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_406 = asUInt(reset)
node _T_407 = eq(_T_406, UInt<1>(0h0))
when _T_407 :
node _T_408 = eq(_T_405, UInt<1>(0h0))
when _T_408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_405, UInt<1>(0h1), "") : assert_54
node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_410 = asUInt(reset)
node _T_411 = eq(_T_410, UInt<1>(0h0))
when _T_411 :
node _T_412 = eq(_T_409, UInt<1>(0h0))
when _T_412 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_409, UInt<1>(0h1), "") : assert_55
node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_414 = asUInt(reset)
node _T_415 = eq(_T_414, UInt<1>(0h0))
when _T_415 :
node _T_416 = eq(_T_413, UInt<1>(0h0))
when _T_416 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_413, UInt<1>(0h1), "") : assert_56
node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_418 = asUInt(reset)
node _T_419 = eq(_T_418, UInt<1>(0h0))
when _T_419 :
node _T_420 = eq(_T_417, UInt<1>(0h0))
when _T_420 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_417, UInt<1>(0h1), "") : assert_57
node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_421 :
node _T_422 = asUInt(reset)
node _T_423 = eq(_T_422, UInt<1>(0h0))
when _T_423 :
node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_424 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_425 = asUInt(reset)
node _T_426 = eq(_T_425, UInt<1>(0h0))
when _T_426 :
node _T_427 = eq(sink_ok, UInt<1>(0h0))
when _T_427 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_429 = asUInt(reset)
node _T_430 = eq(_T_429, UInt<1>(0h0))
when _T_430 :
node _T_431 = eq(_T_428, UInt<1>(0h0))
when _T_431 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_428, UInt<1>(0h1), "") : assert_60
node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_433 = asUInt(reset)
node _T_434 = eq(_T_433, UInt<1>(0h0))
when _T_434 :
node _T_435 = eq(_T_432, UInt<1>(0h0))
when _T_435 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_432, UInt<1>(0h1), "") : assert_61
node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_437 = asUInt(reset)
node _T_438 = eq(_T_437, UInt<1>(0h0))
when _T_438 :
node _T_439 = eq(_T_436, UInt<1>(0h0))
when _T_439 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_436, UInt<1>(0h1), "") : assert_62
node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_441 = asUInt(reset)
node _T_442 = eq(_T_441, UInt<1>(0h0))
when _T_442 :
node _T_443 = eq(_T_440, UInt<1>(0h0))
when _T_443 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_440, UInt<1>(0h1), "") : assert_63
node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_445 = or(UInt<1>(0h0), _T_444)
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_445, UInt<1>(0h1), "") : assert_64
node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_449 :
node _T_450 = asUInt(reset)
node _T_451 = eq(_T_450, UInt<1>(0h0))
when _T_451 :
node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_452 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(sink_ok, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_457 = asUInt(reset)
node _T_458 = eq(_T_457, UInt<1>(0h0))
when _T_458 :
node _T_459 = eq(_T_456, UInt<1>(0h0))
when _T_459 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_456, UInt<1>(0h1), "") : assert_67
node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_461 = asUInt(reset)
node _T_462 = eq(_T_461, UInt<1>(0h0))
when _T_462 :
node _T_463 = eq(_T_460, UInt<1>(0h0))
when _T_463 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_460, UInt<1>(0h1), "") : assert_68
node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_465 = asUInt(reset)
node _T_466 = eq(_T_465, UInt<1>(0h0))
when _T_466 :
node _T_467 = eq(_T_464, UInt<1>(0h0))
when _T_467 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_464, UInt<1>(0h1), "") : assert_69
node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_469 = or(_T_468, io.in.d.bits.corrupt)
node _T_470 = asUInt(reset)
node _T_471 = eq(_T_470, UInt<1>(0h0))
when _T_471 :
node _T_472 = eq(_T_469, UInt<1>(0h0))
when _T_472 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_469, UInt<1>(0h1), "") : assert_70
node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_474 = or(UInt<1>(0h0), _T_473)
node _T_475 = asUInt(reset)
node _T_476 = eq(_T_475, UInt<1>(0h0))
when _T_476 :
node _T_477 = eq(_T_474, UInt<1>(0h0))
when _T_477 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_474, UInt<1>(0h1), "") : assert_71
node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_478 :
node _T_479 = asUInt(reset)
node _T_480 = eq(_T_479, UInt<1>(0h0))
when _T_480 :
node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_481 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_483 = asUInt(reset)
node _T_484 = eq(_T_483, UInt<1>(0h0))
when _T_484 :
node _T_485 = eq(_T_482, UInt<1>(0h0))
when _T_485 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_482, UInt<1>(0h1), "") : assert_73
node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_487 = asUInt(reset)
node _T_488 = eq(_T_487, UInt<1>(0h0))
when _T_488 :
node _T_489 = eq(_T_486, UInt<1>(0h0))
when _T_489 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_486, UInt<1>(0h1), "") : assert_74
node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_491 = or(UInt<1>(0h0), _T_490)
node _T_492 = asUInt(reset)
node _T_493 = eq(_T_492, UInt<1>(0h0))
when _T_493 :
node _T_494 = eq(_T_491, UInt<1>(0h0))
when _T_494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_491, UInt<1>(0h1), "") : assert_75
node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_495 :
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_500 = asUInt(reset)
node _T_501 = eq(_T_500, UInt<1>(0h0))
when _T_501 :
node _T_502 = eq(_T_499, UInt<1>(0h0))
when _T_502 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_499, UInt<1>(0h1), "") : assert_77
node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_504 = or(_T_503, io.in.d.bits.corrupt)
node _T_505 = asUInt(reset)
node _T_506 = eq(_T_505, UInt<1>(0h0))
when _T_506 :
node _T_507 = eq(_T_504, UInt<1>(0h0))
when _T_507 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_504, UInt<1>(0h1), "") : assert_78
node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_509 = or(UInt<1>(0h0), _T_508)
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_T_509, UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_509, UInt<1>(0h1), "") : assert_79
node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_513 :
node _T_514 = asUInt(reset)
node _T_515 = eq(_T_514, UInt<1>(0h0))
when _T_515 :
node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_516 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_518 = asUInt(reset)
node _T_519 = eq(_T_518, UInt<1>(0h0))
when _T_519 :
node _T_520 = eq(_T_517, UInt<1>(0h0))
when _T_520 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_517, UInt<1>(0h1), "") : assert_81
node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_522 = asUInt(reset)
node _T_523 = eq(_T_522, UInt<1>(0h0))
when _T_523 :
node _T_524 = eq(_T_521, UInt<1>(0h0))
when _T_524 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_521, UInt<1>(0h1), "") : assert_82
node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_526 = or(UInt<1>(0h0), _T_525)
node _T_527 = asUInt(reset)
node _T_528 = eq(_T_527, UInt<1>(0h0))
when _T_528 :
node _T_529 = eq(_T_526, UInt<1>(0h0))
when _T_529 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_526, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<13>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<13>(0h0)
connect _WIRE.bits.source, UInt<13>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<13>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_531 = asUInt(reset)
node _T_532 = eq(_T_531, UInt<1>(0h0))
when _T_532 :
node _T_533 = eq(_T_530, UInt<1>(0h0))
when _T_533 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_530, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<13>(0h0)
connect _WIRE_2.bits.source, UInt<13>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_535 = asUInt(reset)
node _T_536 = eq(_T_535, UInt<1>(0h0))
when _T_536 :
node _T_537 = eq(_T_534, UInt<1>(0h0))
when _T_537 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_534, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_539 = asUInt(reset)
node _T_540 = eq(_T_539, UInt<1>(0h0))
when _T_540 :
node _T_541 = eq(_T_538, UInt<1>(0h0))
when _T_541 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_538, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_542 = eq(a_first, UInt<1>(0h0))
node _T_543 = and(io.in.a.valid, _T_542)
when _T_543 :
node _T_544 = eq(io.in.a.bits.opcode, opcode)
node _T_545 = asUInt(reset)
node _T_546 = eq(_T_545, UInt<1>(0h0))
when _T_546 :
node _T_547 = eq(_T_544, UInt<1>(0h0))
when _T_547 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_544, UInt<1>(0h1), "") : assert_87
node _T_548 = eq(io.in.a.bits.param, param)
node _T_549 = asUInt(reset)
node _T_550 = eq(_T_549, UInt<1>(0h0))
when _T_550 :
node _T_551 = eq(_T_548, UInt<1>(0h0))
when _T_551 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_548, UInt<1>(0h1), "") : assert_88
node _T_552 = eq(io.in.a.bits.size, size)
node _T_553 = asUInt(reset)
node _T_554 = eq(_T_553, UInt<1>(0h0))
when _T_554 :
node _T_555 = eq(_T_552, UInt<1>(0h0))
when _T_555 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_552, UInt<1>(0h1), "") : assert_89
node _T_556 = eq(io.in.a.bits.source, source)
node _T_557 = asUInt(reset)
node _T_558 = eq(_T_557, UInt<1>(0h0))
when _T_558 :
node _T_559 = eq(_T_556, UInt<1>(0h0))
when _T_559 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_556, UInt<1>(0h1), "") : assert_90
node _T_560 = eq(io.in.a.bits.address, address)
node _T_561 = asUInt(reset)
node _T_562 = eq(_T_561, UInt<1>(0h0))
when _T_562 :
node _T_563 = eq(_T_560, UInt<1>(0h0))
when _T_563 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_560, UInt<1>(0h1), "") : assert_91
node _T_564 = and(io.in.a.ready, io.in.a.valid)
node _T_565 = and(_T_564, a_first)
when _T_565 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_566 = eq(d_first, UInt<1>(0h0))
node _T_567 = and(io.in.d.valid, _T_566)
when _T_567 :
node _T_568 = eq(io.in.d.bits.opcode, opcode_1)
node _T_569 = asUInt(reset)
node _T_570 = eq(_T_569, UInt<1>(0h0))
when _T_570 :
node _T_571 = eq(_T_568, UInt<1>(0h0))
when _T_571 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_568, UInt<1>(0h1), "") : assert_92
node _T_572 = eq(io.in.d.bits.param, param_1)
node _T_573 = asUInt(reset)
node _T_574 = eq(_T_573, UInt<1>(0h0))
when _T_574 :
node _T_575 = eq(_T_572, UInt<1>(0h0))
when _T_575 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_572, UInt<1>(0h1), "") : assert_93
node _T_576 = eq(io.in.d.bits.size, size_1)
node _T_577 = asUInt(reset)
node _T_578 = eq(_T_577, UInt<1>(0h0))
when _T_578 :
node _T_579 = eq(_T_576, UInt<1>(0h0))
when _T_579 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_576, UInt<1>(0h1), "") : assert_94
node _T_580 = eq(io.in.d.bits.source, source_1)
node _T_581 = asUInt(reset)
node _T_582 = eq(_T_581, UInt<1>(0h0))
when _T_582 :
node _T_583 = eq(_T_580, UInt<1>(0h0))
when _T_583 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_580, UInt<1>(0h1), "") : assert_95
node _T_584 = eq(io.in.d.bits.sink, sink)
node _T_585 = asUInt(reset)
node _T_586 = eq(_T_585, UInt<1>(0h0))
when _T_586 :
node _T_587 = eq(_T_584, UInt<1>(0h0))
when _T_587 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_584, UInt<1>(0h1), "") : assert_96
node _T_588 = eq(io.in.d.bits.denied, denied)
node _T_589 = asUInt(reset)
node _T_590 = eq(_T_589, UInt<1>(0h0))
when _T_590 :
node _T_591 = eq(_T_588, UInt<1>(0h0))
when _T_591 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_588, UInt<1>(0h1), "") : assert_97
node _T_592 = and(io.in.d.ready, io.in.d.valid)
node _T_593 = and(_T_592, d_first)
when _T_593 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<4112>, clock, reset, UInt<4112>(0h0)
regreset inflight_opcodes : UInt<16448>, clock, reset, UInt<16448>(0h0)
regreset inflight_sizes : UInt<16448>, clock, reset, UInt<16448>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<4112>
connect a_set, UInt<4112>(0h0)
wire a_set_wo_ready : UInt<4112>
connect a_set_wo_ready, UInt<4112>(0h0)
wire a_opcodes_set : UInt<16448>
connect a_opcodes_set, UInt<16448>(0h0)
wire a_sizes_set : UInt<16448>
connect a_sizes_set, UInt<16448>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<3>
connect a_sizes_set_interm, UInt<3>(0h0)
node _T_594 = and(io.in.a.valid, a_first_1)
node _T_595 = and(_T_594, UInt<1>(0h1))
when _T_595 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_596 = and(io.in.a.ready, io.in.a.valid)
node _T_597 = and(_T_596, a_first_1)
node _T_598 = and(_T_597, UInt<1>(0h1))
when _T_598 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_599 = dshr(inflight, io.in.a.bits.source)
node _T_600 = bits(_T_599, 0, 0)
node _T_601 = eq(_T_600, UInt<1>(0h0))
node _T_602 = asUInt(reset)
node _T_603 = eq(_T_602, UInt<1>(0h0))
when _T_603 :
node _T_604 = eq(_T_601, UInt<1>(0h0))
when _T_604 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_601, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<4112>
connect d_clr, UInt<4112>(0h0)
wire d_clr_wo_ready : UInt<4112>
connect d_clr_wo_ready, UInt<4112>(0h0)
wire d_opcodes_clr : UInt<16448>
connect d_opcodes_clr, UInt<16448>(0h0)
wire d_sizes_clr : UInt<16448>
connect d_sizes_clr, UInt<16448>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_605 = and(io.in.d.valid, d_first_1)
node _T_606 = and(_T_605, UInt<1>(0h1))
node _T_607 = eq(d_release_ack, UInt<1>(0h0))
node _T_608 = and(_T_606, _T_607)
when _T_608 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_609 = and(io.in.d.ready, io.in.d.valid)
node _T_610 = and(_T_609, d_first_1)
node _T_611 = and(_T_610, UInt<1>(0h1))
node _T_612 = eq(d_release_ack, UInt<1>(0h0))
node _T_613 = and(_T_611, _T_612)
when _T_613 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_614 = and(io.in.d.valid, d_first_1)
node _T_615 = and(_T_614, UInt<1>(0h1))
node _T_616 = eq(d_release_ack, UInt<1>(0h0))
node _T_617 = and(_T_615, _T_616)
when _T_617 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_618 = dshr(inflight, io.in.d.bits.source)
node _T_619 = bits(_T_618, 0, 0)
node _T_620 = or(_T_619, same_cycle_resp)
node _T_621 = asUInt(reset)
node _T_622 = eq(_T_621, UInt<1>(0h0))
when _T_622 :
node _T_623 = eq(_T_620, UInt<1>(0h0))
when _T_623 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_620, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_626 = or(_T_624, _T_625)
node _T_627 = asUInt(reset)
node _T_628 = eq(_T_627, UInt<1>(0h0))
when _T_628 :
node _T_629 = eq(_T_626, UInt<1>(0h0))
when _T_629 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_626, UInt<1>(0h1), "") : assert_100
node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_631 = asUInt(reset)
node _T_632 = eq(_T_631, UInt<1>(0h0))
when _T_632 :
node _T_633 = eq(_T_630, UInt<1>(0h0))
when _T_633 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_630, UInt<1>(0h1), "") : assert_101
else :
node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_636 = or(_T_634, _T_635)
node _T_637 = asUInt(reset)
node _T_638 = eq(_T_637, UInt<1>(0h0))
when _T_638 :
node _T_639 = eq(_T_636, UInt<1>(0h0))
when _T_639 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_636, UInt<1>(0h1), "") : assert_102
node _T_640 = eq(io.in.d.bits.size, a_size_lookup)
node _T_641 = asUInt(reset)
node _T_642 = eq(_T_641, UInt<1>(0h0))
when _T_642 :
node _T_643 = eq(_T_640, UInt<1>(0h0))
when _T_643 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_640, UInt<1>(0h1), "") : assert_103
node _T_644 = and(io.in.d.valid, d_first_1)
node _T_645 = and(_T_644, a_first_1)
node _T_646 = and(_T_645, io.in.a.valid)
node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_648 = and(_T_646, _T_647)
node _T_649 = eq(d_release_ack, UInt<1>(0h0))
node _T_650 = and(_T_648, _T_649)
when _T_650 :
node _T_651 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_652 = or(_T_651, io.in.a.ready)
node _T_653 = asUInt(reset)
node _T_654 = eq(_T_653, UInt<1>(0h0))
when _T_654 :
node _T_655 = eq(_T_652, UInt<1>(0h0))
when _T_655 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_652, UInt<1>(0h1), "") : assert_104
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_22
node _T_656 = orr(inflight)
node _T_657 = eq(_T_656, UInt<1>(0h0))
node _T_658 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_659 = or(_T_657, _T_658)
node _T_660 = lt(watchdog, plusarg_reader.out)
node _T_661 = or(_T_659, _T_660)
node _T_662 = asUInt(reset)
node _T_663 = eq(_T_662, UInt<1>(0h0))
when _T_663 :
node _T_664 = eq(_T_661, UInt<1>(0h0))
when _T_664 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_661, UInt<1>(0h1), "") : assert_105
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_665 = and(io.in.a.ready, io.in.a.valid)
node _T_666 = and(io.in.d.ready, io.in.d.valid)
node _T_667 = or(_T_665, _T_666)
when _T_667 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<4112>, clock, reset, UInt<4112>(0h0)
regreset inflight_opcodes_1 : UInt<16448>, clock, reset, UInt<16448>(0h0)
regreset inflight_sizes_1 : UInt<16448>, clock, reset, UInt<16448>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<13>(0h0)
connect _c_first_WIRE.bits.source, UInt<13>(0h0)
connect _c_first_WIRE.bits.size, UInt<2>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<13>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<13>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<4112>
connect c_set, UInt<4112>(0h0)
wire c_set_wo_ready : UInt<4112>
connect c_set_wo_ready, UInt<4112>(0h0)
wire c_opcodes_set : UInt<16448>
connect c_opcodes_set, UInt<16448>(0h0)
wire c_sizes_set : UInt<16448>
connect c_sizes_set, UInt<16448>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<3>
connect c_sizes_set_interm, UInt<3>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<13>(0h0)
connect _WIRE_6.bits.source, UInt<13>(0h0)
connect _WIRE_6.bits.size, UInt<2>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_668 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<13>(0h0)
connect _WIRE_8.bits.source, UInt<13>(0h0)
connect _WIRE_8.bits.size, UInt<2>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_669 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_670 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_671 = and(_T_669, _T_670)
node _T_672 = and(_T_668, _T_671)
when _T_672 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<13>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<13>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<13>(0h0)
connect _WIRE_10.bits.source, UInt<13>(0h0)
connect _WIRE_10.bits.size, UInt<2>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_673 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_674 = and(_T_673, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<13>(0h0)
connect _WIRE_12.bits.source, UInt<13>(0h0)
connect _WIRE_12.bits.size, UInt<2>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_675 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_676 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_677 = and(_T_675, _T_676)
node _T_678 = and(_T_674, _T_677)
when _T_678 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<13>(0h0)
connect _c_set_WIRE.bits.source, UInt<13>(0h0)
connect _c_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<13>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<13>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<13>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<13>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<13>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<13>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<13>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<13>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<13>(0h0)
connect _WIRE_14.bits.source, UInt<13>(0h0)
connect _WIRE_14.bits.size, UInt<2>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_679 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_680 = bits(_T_679, 0, 0)
node _T_681 = eq(_T_680, UInt<1>(0h0))
node _T_682 = asUInt(reset)
node _T_683 = eq(_T_682, UInt<1>(0h0))
when _T_683 :
node _T_684 = eq(_T_681, UInt<1>(0h0))
when _T_684 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_681, UInt<1>(0h1), "") : assert_106
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<13>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<13>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<13>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<13>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<4112>
connect d_clr_1, UInt<4112>(0h0)
wire d_clr_wo_ready_1 : UInt<4112>
connect d_clr_wo_ready_1, UInt<4112>(0h0)
wire d_opcodes_clr_1 : UInt<16448>
connect d_opcodes_clr_1, UInt<16448>(0h0)
wire d_sizes_clr_1 : UInt<16448>
connect d_sizes_clr_1, UInt<16448>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_685 = and(io.in.d.valid, d_first_2)
node _T_686 = and(_T_685, UInt<1>(0h1))
node _T_687 = and(_T_686, d_release_ack_1)
when _T_687 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_688 = and(io.in.d.ready, io.in.d.valid)
node _T_689 = and(_T_688, d_first_2)
node _T_690 = and(_T_689, UInt<1>(0h1))
node _T_691 = and(_T_690, d_release_ack_1)
when _T_691 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_692 = and(io.in.d.valid, d_first_2)
node _T_693 = and(_T_692, UInt<1>(0h1))
node _T_694 = and(_T_693, d_release_ack_1)
when _T_694 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<13>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<13>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<13>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<13>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<13>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<13>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_695 = dshr(inflight_1, io.in.d.bits.source)
node _T_696 = bits(_T_695, 0, 0)
node _T_697 = or(_T_696, same_cycle_resp_1)
node _T_698 = asUInt(reset)
node _T_699 = eq(_T_698, UInt<1>(0h0))
when _T_699 :
node _T_700 = eq(_T_697, UInt<1>(0h0))
when _T_700 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107
assert(clock, _T_697, UInt<1>(0h1), "") : assert_107
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<13>(0h0)
connect _WIRE_16.bits.source, UInt<13>(0h0)
connect _WIRE_16.bits.size, UInt<2>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_701 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_702 = asUInt(reset)
node _T_703 = eq(_T_702, UInt<1>(0h0))
when _T_703 :
node _T_704 = eq(_T_701, UInt<1>(0h0))
when _T_704 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_701, UInt<1>(0h1), "") : assert_108
else :
node _T_705 = eq(io.in.d.bits.size, c_size_lookup)
node _T_706 = asUInt(reset)
node _T_707 = eq(_T_706, UInt<1>(0h0))
when _T_707 :
node _T_708 = eq(_T_705, UInt<1>(0h0))
when _T_708 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_705, UInt<1>(0h1), "") : assert_109
node _T_709 = and(io.in.d.valid, d_first_2)
node _T_710 = and(_T_709, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<13>(0h0)
connect _WIRE_18.bits.source, UInt<13>(0h0)
connect _WIRE_18.bits.size, UInt<2>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_711 = and(_T_710, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<13>(0h0)
connect _WIRE_20.bits.source, UInt<13>(0h0)
connect _WIRE_20.bits.size, UInt<2>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_712 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_713 = and(_T_711, _T_712)
node _T_714 = and(_T_713, d_release_ack_1)
node _T_715 = eq(c_probe_ack, UInt<1>(0h0))
node _T_716 = and(_T_714, _T_715)
when _T_716 :
node _T_717 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<13>(0h0)
connect _WIRE_22.bits.source, UInt<13>(0h0)
connect _WIRE_22.bits.size, UInt<2>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_718 = or(_T_717, _WIRE_23.ready)
node _T_719 = asUInt(reset)
node _T_720 = eq(_T_719, UInt<1>(0h0))
when _T_720 :
node _T_721 = eq(_T_718, UInt<1>(0h0))
when _T_721 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_718, UInt<1>(0h1), "") : assert_110
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_23
node _T_722 = orr(inflight_1)
node _T_723 = eq(_T_722, UInt<1>(0h0))
node _T_724 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_725 = or(_T_723, _T_724)
node _T_726 = lt(watchdog_1, plusarg_reader_1.out)
node _T_727 = or(_T_725, _T_726)
node _T_728 = asUInt(reset)
node _T_729 = eq(_T_728, UInt<1>(0h0))
when _T_729 :
node _T_730 = eq(_T_727, UInt<1>(0h0))
when _T_730 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_727, UInt<1>(0h1), "") : assert_111
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<13>(0h0)
connect _WIRE_24.bits.source, UInt<13>(0h0)
connect _WIRE_24.bits.size, UInt<2>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_731 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_732 = and(io.in.d.ready, io.in.d.valid)
node _T_733 = or(_T_731, _T_732)
when _T_733 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_11( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [12:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [12:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [12:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [12:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [12:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [12:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10]
wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count = 1'h0; // @[Edges.scala:234:25]
wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27]
wire c_first_count = 1'h0; // @[Edges.scala:234:25]
wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21]
wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67]
wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last = 1'h1; // @[Edges.scala:232:33]
wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33]
wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [12:0] _c_first_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _c_first_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _c_first_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _c_first_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _c_first_WIRE_2_bits_source = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _c_first_WIRE_2_bits_address = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _c_first_WIRE_3_bits_source = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _c_first_WIRE_3_bits_address = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _c_set_wo_ready_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _c_set_wo_ready_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _c_set_wo_ready_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _c_set_wo_ready_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _c_set_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _c_set_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _c_set_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _c_set_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _c_opcodes_set_interm_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _c_opcodes_set_interm_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _c_opcodes_set_interm_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _c_opcodes_set_interm_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _c_sizes_set_interm_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _c_sizes_set_interm_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _c_sizes_set_interm_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _c_sizes_set_interm_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _c_opcodes_set_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _c_opcodes_set_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _c_opcodes_set_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _c_opcodes_set_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _c_sizes_set_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _c_sizes_set_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _c_sizes_set_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _c_sizes_set_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _c_probe_ack_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _c_probe_ack_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _c_probe_ack_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _c_probe_ack_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _c_probe_ack_WIRE_2_bits_source = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _c_probe_ack_WIRE_2_bits_address = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _c_probe_ack_WIRE_3_bits_source = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _c_probe_ack_WIRE_3_bits_address = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _same_cycle_resp_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _same_cycle_resp_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _same_cycle_resp_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _same_cycle_resp_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _same_cycle_resp_WIRE_2_bits_source = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _same_cycle_resp_WIRE_2_bits_address = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _same_cycle_resp_WIRE_3_bits_source = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _same_cycle_resp_WIRE_3_bits_address = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _same_cycle_resp_WIRE_4_bits_source = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _same_cycle_resp_WIRE_4_bits_address = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _same_cycle_resp_WIRE_5_bits_source = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _same_cycle_resp_WIRE_5_bits_address = 13'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46]
wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [65537:0] _c_sizes_set_T_1 = 65538'h0; // @[Monitor.scala:768:52]
wire [15:0] _c_opcodes_set_T = 16'h0; // @[Monitor.scala:767:79]
wire [15:0] _c_sizes_set_T = 16'h0; // @[Monitor.scala:768:77]
wire [65538:0] _c_opcodes_set_T_1 = 65539'h0; // @[Monitor.scala:767:54]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [8191:0] _c_set_wo_ready_T = 8192'h1; // @[OneHot.scala:58:35]
wire [8191:0] _c_set_T = 8192'h1; // @[OneHot.scala:58:35]
wire [16447:0] c_opcodes_set = 16448'h0; // @[Monitor.scala:740:34]
wire [16447:0] c_sizes_set = 16448'h0; // @[Monitor.scala:741:34]
wire [4111:0] c_set = 4112'h0; // @[Monitor.scala:738:34]
wire [4111:0] c_set_wo_ready = 4112'h0; // @[Monitor.scala:739:34]
wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76]
wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [12:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [12:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [12:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [12:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [12:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [12:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [12:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [12:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [12:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [12:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [12:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [12:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_4 = source_ok_uncommonBits < 13'h1010; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [12:0] _is_aligned_T = {10'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 13'h0; // @[Edges.scala:21:{16,24}]
wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [12:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [12:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire [12:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}]
wire [12:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}]
wire [12:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}]
wire [12:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}]
wire [12:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}]
wire [12:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}]
wire [12:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}]
wire [12:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_10 = source_ok_uncommonBits_1 < 13'h1010; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31]
wire _T_665 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_665; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_665; // @[Decoupled.scala:51:35]
wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
reg a_first_counter; // @[Edges.scala:229:27]
wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28]
wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [1:0] size; // @[Monitor.scala:389:22]
reg [12:0] source; // @[Monitor.scala:390:22]
reg [12:0] address; // @[Monitor.scala:391:22]
wire _T_733 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_733; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_733; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_733; // @[Decoupled.scala:51:35]
wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35]
wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
reg d_first_counter; // @[Edges.scala:229:27]
wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28]
wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg [12:0] source_1; // @[Monitor.scala:541:22]
reg [4111:0] inflight; // @[Monitor.scala:614:27]
reg [16447:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [16447:0] inflight_sizes; // @[Monitor.scala:618:33]
wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
reg a_first_counter_1; // @[Edges.scala:229:27]
wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire [4111:0] a_set; // @[Monitor.scala:626:34]
wire [4111:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [16447:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [16447:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [15:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [15:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [15:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [15:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [15:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [15:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [15:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [15:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [15:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [16447:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [16447:0] _a_opcode_lookup_T_6 = {16444'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [16447:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[16447:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [16447:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [16447:0] _a_size_lookup_T_6 = {16444'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [16447:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[16447:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [8191:0] _GEN_2 = 8192'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [8191:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [8191:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[4111:0] : 4112'h0; // @[OneHot.scala:58:35]
wire _T_598 = _T_665 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_598 ? _a_set_T[4111:0] : 4112'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [15:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [15:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [15:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [65538:0] _a_opcodes_set_T_1 = {65535'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[16447:0] : 16448'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [65537:0] _a_sizes_set_T_1 = {65535'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[16447:0] : 16448'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [4111:0] d_clr; // @[Monitor.scala:664:34]
wire [4111:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [16447:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [16447:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [8191:0] _GEN_5 = 8192'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [8191:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [8191:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [8191:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [8191:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[4111:0] : 4112'h0; // @[OneHot.scala:58:35]
wire _T_613 = _T_733 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_613 ? _d_clr_T[4111:0] : 4112'h0; // @[OneHot.scala:58:35]
wire [65550:0] _d_opcodes_clr_T_5 = 65551'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[16447:0] : 16448'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [65550:0] _d_sizes_clr_T_5 = 65551'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[16447:0] : 16448'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [4111:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [4111:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [4111:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [16447:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [16447:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [16447:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [16447:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [16447:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [16447:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [4111:0] inflight_1; // @[Monitor.scala:726:35]
wire [4111:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [16447:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [16447:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [16447:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [16447:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
reg d_first_counter_2; // @[Edges.scala:229:27]
wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28]
wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [16447:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [16447:0] _c_opcode_lookup_T_6 = {16444'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [16447:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[16447:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [16447:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [16447:0] _c_size_lookup_T_6 = {16444'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [16447:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[16447:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [4111:0] d_clr_1; // @[Monitor.scala:774:34]
wire [4111:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [16447:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [16447:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_709 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_709 & d_release_ack_1 ? _d_clr_wo_ready_T_1[4111:0] : 4112'h0; // @[OneHot.scala:58:35]
wire _T_691 = _T_733 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_691 ? _d_clr_T_1[4111:0] : 4112'h0; // @[OneHot.scala:58:35]
wire [65550:0] _d_opcodes_clr_T_11 = 65551'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_691 ? _d_opcodes_clr_T_11[16447:0] : 16448'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [65550:0] _d_sizes_clr_T_11 = 65551'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_691 ? _d_sizes_clr_T_11[16447:0] : 16448'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 13'h0; // @[Monitor.scala:36:7, :795:113]
wire [4111:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [4111:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [16447:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [16447:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [16447:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [16447:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_365 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_365( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module ClockSinkDomain_6 :
output auto : { flip rerocc_tile_ctrl_ctrl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, rerocc_tile_buffer_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, flip rerocc_tile_re_ro_cc_in : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}}, flip rerocc_tile_rerocc_manager_id_sink_in : UInt<7>, flip clock_in : { clock : Clock, reset : Reset}}
output clock : Clock
output reset : Reset
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset
inst rerocc_tile of ReRoCCManagerTile_4
connect rerocc_tile.clock, childClock
connect rerocc_tile.reset, childReset
wire clockNodeIn : { clock : Clock, reset : Reset}
invalidate clockNodeIn.reset
invalidate clockNodeIn.clock
connect clockNodeIn, auto.clock_in
connect rerocc_tile.auto.rerocc_manager_id_sink_in, auto.rerocc_tile_rerocc_manager_id_sink_in
connect rerocc_tile.auto.re_ro_cc_in, auto.rerocc_tile_re_ro_cc_in
connect auto.rerocc_tile_buffer_out.e.bits, rerocc_tile.auto.buffer_out.e.bits
connect auto.rerocc_tile_buffer_out.e.valid, rerocc_tile.auto.buffer_out.e.valid
connect rerocc_tile.auto.buffer_out.e.ready, auto.rerocc_tile_buffer_out.e.ready
connect rerocc_tile.auto.buffer_out.d, auto.rerocc_tile_buffer_out.d
connect auto.rerocc_tile_buffer_out.c.bits, rerocc_tile.auto.buffer_out.c.bits
connect auto.rerocc_tile_buffer_out.c.valid, rerocc_tile.auto.buffer_out.c.valid
connect rerocc_tile.auto.buffer_out.c.ready, auto.rerocc_tile_buffer_out.c.ready
connect rerocc_tile.auto.buffer_out.b, auto.rerocc_tile_buffer_out.b
connect auto.rerocc_tile_buffer_out.a.bits, rerocc_tile.auto.buffer_out.a.bits
connect auto.rerocc_tile_buffer_out.a.valid, rerocc_tile.auto.buffer_out.a.valid
connect rerocc_tile.auto.buffer_out.a.ready, auto.rerocc_tile_buffer_out.a.ready
connect rerocc_tile.auto.ctrl_ctrl_in, auto.rerocc_tile_ctrl_ctrl_in
connect childClock, clockNodeIn.clock
connect childReset, clockNodeIn.reset
connect clock, clockNodeIn.clock
connect reset, clockNodeIn.reset | module ClockSinkDomain_6( // @[ClockDomain.scala:14:9]
output auto_rerocc_tile_ctrl_ctrl_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_rerocc_tile_ctrl_ctrl_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [11:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_rerocc_tile_ctrl_ctrl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_rerocc_tile_ctrl_ctrl_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_rerocc_tile_ctrl_ctrl_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_rerocc_tile_ctrl_ctrl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_rerocc_tile_ctrl_ctrl_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_rerocc_tile_ctrl_ctrl_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_rerocc_tile_ctrl_ctrl_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_rerocc_tile_buffer_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_rerocc_tile_buffer_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_rerocc_tile_buffer_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_rerocc_tile_buffer_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_rerocc_tile_buffer_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_rerocc_tile_buffer_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_rerocc_tile_buffer_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_rerocc_tile_buffer_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_rerocc_tile_buffer_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_rerocc_tile_buffer_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_rerocc_tile_buffer_out_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_rerocc_tile_buffer_out_b_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_rerocc_tile_buffer_out_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_rerocc_tile_buffer_out_b_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_rerocc_tile_buffer_out_b_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_rerocc_tile_buffer_out_b_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_rerocc_tile_buffer_out_b_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_rerocc_tile_buffer_out_b_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_rerocc_tile_buffer_out_b_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_rerocc_tile_buffer_out_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_rerocc_tile_buffer_out_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_rerocc_tile_buffer_out_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_rerocc_tile_buffer_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_rerocc_tile_buffer_out_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_rerocc_tile_buffer_out_c_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_rerocc_tile_buffer_out_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_rerocc_tile_buffer_out_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_rerocc_tile_buffer_out_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_rerocc_tile_buffer_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_rerocc_tile_buffer_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_rerocc_tile_buffer_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_rerocc_tile_buffer_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_rerocc_tile_buffer_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_rerocc_tile_buffer_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_rerocc_tile_buffer_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_rerocc_tile_buffer_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_rerocc_tile_buffer_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_rerocc_tile_buffer_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_rerocc_tile_buffer_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_rerocc_tile_buffer_out_e_ready, // @[LazyModuleImp.scala:107:25]
output auto_rerocc_tile_buffer_out_e_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_rerocc_tile_buffer_out_e_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_rerocc_tile_re_ro_cc_in_req_ready, // @[LazyModuleImp.scala:107:25]
input auto_rerocc_tile_re_ro_cc_in_req_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_rerocc_tile_re_ro_cc_in_req_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_rerocc_tile_re_ro_cc_in_req_bits_client_id, // @[LazyModuleImp.scala:107:25]
input auto_rerocc_tile_re_ro_cc_in_req_bits_manager_id, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_rerocc_tile_re_ro_cc_in_req_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_rerocc_tile_re_ro_cc_in_resp_ready, // @[LazyModuleImp.scala:107:25]
output auto_rerocc_tile_re_ro_cc_in_resp_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_rerocc_tile_re_ro_cc_in_resp_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_rerocc_tile_re_ro_cc_in_resp_bits_client_id, // @[LazyModuleImp.scala:107:25]
output auto_rerocc_tile_re_ro_cc_in_resp_bits_manager_id, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_rerocc_tile_re_ro_cc_in_resp_bits_data, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_rerocc_tile_rerocc_manager_id_sink_in, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_reset // @[LazyModuleImp.scala:107:25]
);
wire auto_rerocc_tile_ctrl_ctrl_in_a_valid_0 = auto_rerocc_tile_ctrl_ctrl_in_a_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_opcode_0 = auto_rerocc_tile_ctrl_ctrl_in_a_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_param_0 = auto_rerocc_tile_ctrl_ctrl_in_a_bits_param; // @[ClockDomain.scala:14:9]
wire [2:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_size_0 = auto_rerocc_tile_ctrl_ctrl_in_a_bits_size; // @[ClockDomain.scala:14:9]
wire [6:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_source_0 = auto_rerocc_tile_ctrl_ctrl_in_a_bits_source; // @[ClockDomain.scala:14:9]
wire [11:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_address_0 = auto_rerocc_tile_ctrl_ctrl_in_a_bits_address; // @[ClockDomain.scala:14:9]
wire [7:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_mask_0 = auto_rerocc_tile_ctrl_ctrl_in_a_bits_mask; // @[ClockDomain.scala:14:9]
wire [63:0] auto_rerocc_tile_ctrl_ctrl_in_a_bits_data_0 = auto_rerocc_tile_ctrl_ctrl_in_a_bits_data; // @[ClockDomain.scala:14:9]
wire auto_rerocc_tile_ctrl_ctrl_in_a_bits_corrupt_0 = auto_rerocc_tile_ctrl_ctrl_in_a_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_rerocc_tile_ctrl_ctrl_in_d_ready_0 = auto_rerocc_tile_ctrl_ctrl_in_d_ready; // @[ClockDomain.scala:14:9]
wire auto_rerocc_tile_buffer_out_a_ready_0 = auto_rerocc_tile_buffer_out_a_ready; // @[ClockDomain.scala:14:9]
wire auto_rerocc_tile_buffer_out_b_valid_0 = auto_rerocc_tile_buffer_out_b_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_rerocc_tile_buffer_out_b_bits_opcode_0 = auto_rerocc_tile_buffer_out_b_bits_opcode; // @[ClockDomain.scala:14:9]
wire [1:0] auto_rerocc_tile_buffer_out_b_bits_param_0 = auto_rerocc_tile_buffer_out_b_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] auto_rerocc_tile_buffer_out_b_bits_size_0 = auto_rerocc_tile_buffer_out_b_bits_size; // @[ClockDomain.scala:14:9]
wire [1:0] auto_rerocc_tile_buffer_out_b_bits_source_0 = auto_rerocc_tile_buffer_out_b_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] auto_rerocc_tile_buffer_out_b_bits_address_0 = auto_rerocc_tile_buffer_out_b_bits_address; // @[ClockDomain.scala:14:9]
wire [7:0] auto_rerocc_tile_buffer_out_b_bits_mask_0 = auto_rerocc_tile_buffer_out_b_bits_mask; // @[ClockDomain.scala:14:9]
wire [63:0] auto_rerocc_tile_buffer_out_b_bits_data_0 = auto_rerocc_tile_buffer_out_b_bits_data; // @[ClockDomain.scala:14:9]
wire auto_rerocc_tile_buffer_out_b_bits_corrupt_0 = auto_rerocc_tile_buffer_out_b_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_rerocc_tile_buffer_out_c_ready_0 = auto_rerocc_tile_buffer_out_c_ready; // @[ClockDomain.scala:14:9]
wire auto_rerocc_tile_buffer_out_d_valid_0 = auto_rerocc_tile_buffer_out_d_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_rerocc_tile_buffer_out_d_bits_opcode_0 = auto_rerocc_tile_buffer_out_d_bits_opcode; // @[ClockDomain.scala:14:9]
wire [1:0] auto_rerocc_tile_buffer_out_d_bits_param_0 = auto_rerocc_tile_buffer_out_d_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] auto_rerocc_tile_buffer_out_d_bits_size_0 = auto_rerocc_tile_buffer_out_d_bits_size; // @[ClockDomain.scala:14:9]
wire [1:0] auto_rerocc_tile_buffer_out_d_bits_source_0 = auto_rerocc_tile_buffer_out_d_bits_source; // @[ClockDomain.scala:14:9]
wire [2:0] auto_rerocc_tile_buffer_out_d_bits_sink_0 = auto_rerocc_tile_buffer_out_d_bits_sink; // @[ClockDomain.scala:14:9]
wire auto_rerocc_tile_buffer_out_d_bits_denied_0 = auto_rerocc_tile_buffer_out_d_bits_denied; // @[ClockDomain.scala:14:9]
wire [63:0] auto_rerocc_tile_buffer_out_d_bits_data_0 = auto_rerocc_tile_buffer_out_d_bits_data; // @[ClockDomain.scala:14:9]
wire auto_rerocc_tile_buffer_out_d_bits_corrupt_0 = auto_rerocc_tile_buffer_out_d_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_rerocc_tile_buffer_out_e_ready_0 = auto_rerocc_tile_buffer_out_e_ready; // @[ClockDomain.scala:14:9]
wire auto_rerocc_tile_re_ro_cc_in_req_valid_0 = auto_rerocc_tile_re_ro_cc_in_req_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_rerocc_tile_re_ro_cc_in_req_bits_opcode_0 = auto_rerocc_tile_re_ro_cc_in_req_bits_opcode; // @[ClockDomain.scala:14:9]
wire [3:0] auto_rerocc_tile_re_ro_cc_in_req_bits_client_id_0 = auto_rerocc_tile_re_ro_cc_in_req_bits_client_id; // @[ClockDomain.scala:14:9]
wire auto_rerocc_tile_re_ro_cc_in_req_bits_manager_id_0 = auto_rerocc_tile_re_ro_cc_in_req_bits_manager_id; // @[ClockDomain.scala:14:9]
wire [63:0] auto_rerocc_tile_re_ro_cc_in_req_bits_data_0 = auto_rerocc_tile_re_ro_cc_in_req_bits_data; // @[ClockDomain.scala:14:9]
wire auto_rerocc_tile_re_ro_cc_in_resp_ready_0 = auto_rerocc_tile_re_ro_cc_in_resp_ready; // @[ClockDomain.scala:14:9]
wire [6:0] auto_rerocc_tile_rerocc_manager_id_sink_in_0 = auto_rerocc_tile_rerocc_manager_id_sink_in; // @[ClockDomain.scala:14:9]
wire auto_clock_in_clock_0 = auto_clock_in_clock; // @[ClockDomain.scala:14:9]
wire auto_clock_in_reset_0 = auto_clock_in_reset; // @[ClockDomain.scala:14:9]
wire [1:0] auto_rerocc_tile_ctrl_ctrl_in_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9]
wire auto_rerocc_tile_ctrl_ctrl_in_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_rerocc_tile_ctrl_ctrl_in_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_rerocc_tile_ctrl_ctrl_in_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire clockNodeIn_clock = auto_clock_in_clock_0; // @[ClockDomain.scala:14:9]
wire clockNodeIn_reset = auto_clock_in_reset_0; // @[ClockDomain.scala:14:9]
wire auto_rerocc_tile_ctrl_ctrl_in_a_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_rerocc_tile_ctrl_ctrl_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_rerocc_tile_ctrl_ctrl_in_d_bits_size_0; // @[ClockDomain.scala:14:9]
wire [6:0] auto_rerocc_tile_ctrl_ctrl_in_d_bits_source_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_rerocc_tile_ctrl_ctrl_in_d_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_rerocc_tile_ctrl_ctrl_in_d_valid_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_rerocc_tile_buffer_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_rerocc_tile_buffer_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
wire [3:0] auto_rerocc_tile_buffer_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_rerocc_tile_buffer_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
wire [31:0] auto_rerocc_tile_buffer_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
wire [7:0] auto_rerocc_tile_buffer_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_rerocc_tile_buffer_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_rerocc_tile_buffer_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_rerocc_tile_buffer_out_a_valid_0; // @[ClockDomain.scala:14:9]
wire auto_rerocc_tile_buffer_out_b_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_rerocc_tile_buffer_out_c_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_rerocc_tile_buffer_out_c_bits_param_0; // @[ClockDomain.scala:14:9]
wire [3:0] auto_rerocc_tile_buffer_out_c_bits_size_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_rerocc_tile_buffer_out_c_bits_source_0; // @[ClockDomain.scala:14:9]
wire [31:0] auto_rerocc_tile_buffer_out_c_bits_address_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_rerocc_tile_buffer_out_c_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_rerocc_tile_buffer_out_c_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_rerocc_tile_buffer_out_c_valid_0; // @[ClockDomain.scala:14:9]
wire auto_rerocc_tile_buffer_out_d_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_rerocc_tile_buffer_out_e_bits_sink_0; // @[ClockDomain.scala:14:9]
wire auto_rerocc_tile_buffer_out_e_valid_0; // @[ClockDomain.scala:14:9]
wire auto_rerocc_tile_re_ro_cc_in_req_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_rerocc_tile_re_ro_cc_in_resp_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [3:0] auto_rerocc_tile_re_ro_cc_in_resp_bits_client_id_0; // @[ClockDomain.scala:14:9]
wire auto_rerocc_tile_re_ro_cc_in_resp_bits_manager_id_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_rerocc_tile_re_ro_cc_in_resp_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_rerocc_tile_re_ro_cc_in_resp_valid_0; // @[ClockDomain.scala:14:9]
wire childClock; // @[LazyModuleImp.scala:155:31]
wire childReset; // @[LazyModuleImp.scala:158:31]
assign childClock = clockNodeIn_clock; // @[MixedNode.scala:551:17]
assign childReset = clockNodeIn_reset; // @[MixedNode.scala:551:17]
ReRoCCManagerTile_4 rerocc_tile ( // @[Integration.scala:45:54]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_ctrl_ctrl_in_a_ready (auto_rerocc_tile_ctrl_ctrl_in_a_ready_0),
.auto_ctrl_ctrl_in_a_valid (auto_rerocc_tile_ctrl_ctrl_in_a_valid_0), // @[ClockDomain.scala:14:9]
.auto_ctrl_ctrl_in_a_bits_opcode (auto_rerocc_tile_ctrl_ctrl_in_a_bits_opcode_0), // @[ClockDomain.scala:14:9]
.auto_ctrl_ctrl_in_a_bits_param (auto_rerocc_tile_ctrl_ctrl_in_a_bits_param_0), // @[ClockDomain.scala:14:9]
.auto_ctrl_ctrl_in_a_bits_size (auto_rerocc_tile_ctrl_ctrl_in_a_bits_size_0), // @[ClockDomain.scala:14:9]
.auto_ctrl_ctrl_in_a_bits_source (auto_rerocc_tile_ctrl_ctrl_in_a_bits_source_0), // @[ClockDomain.scala:14:9]
.auto_ctrl_ctrl_in_a_bits_address (auto_rerocc_tile_ctrl_ctrl_in_a_bits_address_0), // @[ClockDomain.scala:14:9]
.auto_ctrl_ctrl_in_a_bits_mask (auto_rerocc_tile_ctrl_ctrl_in_a_bits_mask_0), // @[ClockDomain.scala:14:9]
.auto_ctrl_ctrl_in_a_bits_data (auto_rerocc_tile_ctrl_ctrl_in_a_bits_data_0), // @[ClockDomain.scala:14:9]
.auto_ctrl_ctrl_in_a_bits_corrupt (auto_rerocc_tile_ctrl_ctrl_in_a_bits_corrupt_0), // @[ClockDomain.scala:14:9]
.auto_ctrl_ctrl_in_d_ready (auto_rerocc_tile_ctrl_ctrl_in_d_ready_0), // @[ClockDomain.scala:14:9]
.auto_ctrl_ctrl_in_d_valid (auto_rerocc_tile_ctrl_ctrl_in_d_valid_0),
.auto_ctrl_ctrl_in_d_bits_opcode (auto_rerocc_tile_ctrl_ctrl_in_d_bits_opcode_0),
.auto_ctrl_ctrl_in_d_bits_size (auto_rerocc_tile_ctrl_ctrl_in_d_bits_size_0),
.auto_ctrl_ctrl_in_d_bits_source (auto_rerocc_tile_ctrl_ctrl_in_d_bits_source_0),
.auto_ctrl_ctrl_in_d_bits_data (auto_rerocc_tile_ctrl_ctrl_in_d_bits_data_0),
.auto_buffer_out_a_ready (auto_rerocc_tile_buffer_out_a_ready_0), // @[ClockDomain.scala:14:9]
.auto_buffer_out_a_valid (auto_rerocc_tile_buffer_out_a_valid_0),
.auto_buffer_out_a_bits_opcode (auto_rerocc_tile_buffer_out_a_bits_opcode_0),
.auto_buffer_out_a_bits_param (auto_rerocc_tile_buffer_out_a_bits_param_0),
.auto_buffer_out_a_bits_size (auto_rerocc_tile_buffer_out_a_bits_size_0),
.auto_buffer_out_a_bits_source (auto_rerocc_tile_buffer_out_a_bits_source_0),
.auto_buffer_out_a_bits_address (auto_rerocc_tile_buffer_out_a_bits_address_0),
.auto_buffer_out_a_bits_mask (auto_rerocc_tile_buffer_out_a_bits_mask_0),
.auto_buffer_out_a_bits_data (auto_rerocc_tile_buffer_out_a_bits_data_0),
.auto_buffer_out_a_bits_corrupt (auto_rerocc_tile_buffer_out_a_bits_corrupt_0),
.auto_buffer_out_b_ready (auto_rerocc_tile_buffer_out_b_ready_0),
.auto_buffer_out_b_valid (auto_rerocc_tile_buffer_out_b_valid_0), // @[ClockDomain.scala:14:9]
.auto_buffer_out_b_bits_opcode (auto_rerocc_tile_buffer_out_b_bits_opcode_0), // @[ClockDomain.scala:14:9]
.auto_buffer_out_b_bits_param (auto_rerocc_tile_buffer_out_b_bits_param_0), // @[ClockDomain.scala:14:9]
.auto_buffer_out_b_bits_size (auto_rerocc_tile_buffer_out_b_bits_size_0), // @[ClockDomain.scala:14:9]
.auto_buffer_out_b_bits_source (auto_rerocc_tile_buffer_out_b_bits_source_0), // @[ClockDomain.scala:14:9]
.auto_buffer_out_b_bits_address (auto_rerocc_tile_buffer_out_b_bits_address_0), // @[ClockDomain.scala:14:9]
.auto_buffer_out_b_bits_mask (auto_rerocc_tile_buffer_out_b_bits_mask_0), // @[ClockDomain.scala:14:9]
.auto_buffer_out_b_bits_data (auto_rerocc_tile_buffer_out_b_bits_data_0), // @[ClockDomain.scala:14:9]
.auto_buffer_out_b_bits_corrupt (auto_rerocc_tile_buffer_out_b_bits_corrupt_0), // @[ClockDomain.scala:14:9]
.auto_buffer_out_c_ready (auto_rerocc_tile_buffer_out_c_ready_0), // @[ClockDomain.scala:14:9]
.auto_buffer_out_c_valid (auto_rerocc_tile_buffer_out_c_valid_0),
.auto_buffer_out_c_bits_opcode (auto_rerocc_tile_buffer_out_c_bits_opcode_0),
.auto_buffer_out_c_bits_param (auto_rerocc_tile_buffer_out_c_bits_param_0),
.auto_buffer_out_c_bits_size (auto_rerocc_tile_buffer_out_c_bits_size_0),
.auto_buffer_out_c_bits_source (auto_rerocc_tile_buffer_out_c_bits_source_0),
.auto_buffer_out_c_bits_address (auto_rerocc_tile_buffer_out_c_bits_address_0),
.auto_buffer_out_c_bits_data (auto_rerocc_tile_buffer_out_c_bits_data_0),
.auto_buffer_out_c_bits_corrupt (auto_rerocc_tile_buffer_out_c_bits_corrupt_0),
.auto_buffer_out_d_ready (auto_rerocc_tile_buffer_out_d_ready_0),
.auto_buffer_out_d_valid (auto_rerocc_tile_buffer_out_d_valid_0), // @[ClockDomain.scala:14:9]
.auto_buffer_out_d_bits_opcode (auto_rerocc_tile_buffer_out_d_bits_opcode_0), // @[ClockDomain.scala:14:9]
.auto_buffer_out_d_bits_param (auto_rerocc_tile_buffer_out_d_bits_param_0), // @[ClockDomain.scala:14:9]
.auto_buffer_out_d_bits_size (auto_rerocc_tile_buffer_out_d_bits_size_0), // @[ClockDomain.scala:14:9]
.auto_buffer_out_d_bits_source (auto_rerocc_tile_buffer_out_d_bits_source_0), // @[ClockDomain.scala:14:9]
.auto_buffer_out_d_bits_sink (auto_rerocc_tile_buffer_out_d_bits_sink_0), // @[ClockDomain.scala:14:9]
.auto_buffer_out_d_bits_denied (auto_rerocc_tile_buffer_out_d_bits_denied_0), // @[ClockDomain.scala:14:9]
.auto_buffer_out_d_bits_data (auto_rerocc_tile_buffer_out_d_bits_data_0), // @[ClockDomain.scala:14:9]
.auto_buffer_out_d_bits_corrupt (auto_rerocc_tile_buffer_out_d_bits_corrupt_0), // @[ClockDomain.scala:14:9]
.auto_buffer_out_e_ready (auto_rerocc_tile_buffer_out_e_ready_0), // @[ClockDomain.scala:14:9]
.auto_buffer_out_e_valid (auto_rerocc_tile_buffer_out_e_valid_0),
.auto_buffer_out_e_bits_sink (auto_rerocc_tile_buffer_out_e_bits_sink_0),
.auto_re_ro_cc_in_req_ready (auto_rerocc_tile_re_ro_cc_in_req_ready_0),
.auto_re_ro_cc_in_req_valid (auto_rerocc_tile_re_ro_cc_in_req_valid_0), // @[ClockDomain.scala:14:9]
.auto_re_ro_cc_in_req_bits_opcode (auto_rerocc_tile_re_ro_cc_in_req_bits_opcode_0), // @[ClockDomain.scala:14:9]
.auto_re_ro_cc_in_req_bits_client_id (auto_rerocc_tile_re_ro_cc_in_req_bits_client_id_0), // @[ClockDomain.scala:14:9]
.auto_re_ro_cc_in_req_bits_manager_id (auto_rerocc_tile_re_ro_cc_in_req_bits_manager_id_0), // @[ClockDomain.scala:14:9]
.auto_re_ro_cc_in_req_bits_data (auto_rerocc_tile_re_ro_cc_in_req_bits_data_0), // @[ClockDomain.scala:14:9]
.auto_re_ro_cc_in_resp_ready (auto_rerocc_tile_re_ro_cc_in_resp_ready_0), // @[ClockDomain.scala:14:9]
.auto_re_ro_cc_in_resp_valid (auto_rerocc_tile_re_ro_cc_in_resp_valid_0),
.auto_re_ro_cc_in_resp_bits_opcode (auto_rerocc_tile_re_ro_cc_in_resp_bits_opcode_0),
.auto_re_ro_cc_in_resp_bits_client_id (auto_rerocc_tile_re_ro_cc_in_resp_bits_client_id_0),
.auto_re_ro_cc_in_resp_bits_manager_id (auto_rerocc_tile_re_ro_cc_in_resp_bits_manager_id_0),
.auto_re_ro_cc_in_resp_bits_data (auto_rerocc_tile_re_ro_cc_in_resp_bits_data_0),
.auto_rerocc_manager_id_sink_in (auto_rerocc_tile_rerocc_manager_id_sink_in_0) // @[ClockDomain.scala:14:9]
); // @[Integration.scala:45:54]
assign auto_rerocc_tile_ctrl_ctrl_in_a_ready = auto_rerocc_tile_ctrl_ctrl_in_a_ready_0; // @[ClockDomain.scala:14:9]
assign auto_rerocc_tile_ctrl_ctrl_in_d_valid = auto_rerocc_tile_ctrl_ctrl_in_d_valid_0; // @[ClockDomain.scala:14:9]
assign auto_rerocc_tile_ctrl_ctrl_in_d_bits_opcode = auto_rerocc_tile_ctrl_ctrl_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_rerocc_tile_ctrl_ctrl_in_d_bits_size = auto_rerocc_tile_ctrl_ctrl_in_d_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_rerocc_tile_ctrl_ctrl_in_d_bits_source = auto_rerocc_tile_ctrl_ctrl_in_d_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_rerocc_tile_ctrl_ctrl_in_d_bits_data = auto_rerocc_tile_ctrl_ctrl_in_d_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_rerocc_tile_buffer_out_a_valid = auto_rerocc_tile_buffer_out_a_valid_0; // @[ClockDomain.scala:14:9]
assign auto_rerocc_tile_buffer_out_a_bits_opcode = auto_rerocc_tile_buffer_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_rerocc_tile_buffer_out_a_bits_param = auto_rerocc_tile_buffer_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_rerocc_tile_buffer_out_a_bits_size = auto_rerocc_tile_buffer_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_rerocc_tile_buffer_out_a_bits_source = auto_rerocc_tile_buffer_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_rerocc_tile_buffer_out_a_bits_address = auto_rerocc_tile_buffer_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
assign auto_rerocc_tile_buffer_out_a_bits_mask = auto_rerocc_tile_buffer_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
assign auto_rerocc_tile_buffer_out_a_bits_data = auto_rerocc_tile_buffer_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_rerocc_tile_buffer_out_a_bits_corrupt = auto_rerocc_tile_buffer_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
assign auto_rerocc_tile_buffer_out_b_ready = auto_rerocc_tile_buffer_out_b_ready_0; // @[ClockDomain.scala:14:9]
assign auto_rerocc_tile_buffer_out_c_valid = auto_rerocc_tile_buffer_out_c_valid_0; // @[ClockDomain.scala:14:9]
assign auto_rerocc_tile_buffer_out_c_bits_opcode = auto_rerocc_tile_buffer_out_c_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_rerocc_tile_buffer_out_c_bits_param = auto_rerocc_tile_buffer_out_c_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_rerocc_tile_buffer_out_c_bits_size = auto_rerocc_tile_buffer_out_c_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_rerocc_tile_buffer_out_c_bits_source = auto_rerocc_tile_buffer_out_c_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_rerocc_tile_buffer_out_c_bits_address = auto_rerocc_tile_buffer_out_c_bits_address_0; // @[ClockDomain.scala:14:9]
assign auto_rerocc_tile_buffer_out_c_bits_data = auto_rerocc_tile_buffer_out_c_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_rerocc_tile_buffer_out_c_bits_corrupt = auto_rerocc_tile_buffer_out_c_bits_corrupt_0; // @[ClockDomain.scala:14:9]
assign auto_rerocc_tile_buffer_out_d_ready = auto_rerocc_tile_buffer_out_d_ready_0; // @[ClockDomain.scala:14:9]
assign auto_rerocc_tile_buffer_out_e_valid = auto_rerocc_tile_buffer_out_e_valid_0; // @[ClockDomain.scala:14:9]
assign auto_rerocc_tile_buffer_out_e_bits_sink = auto_rerocc_tile_buffer_out_e_bits_sink_0; // @[ClockDomain.scala:14:9]
assign auto_rerocc_tile_re_ro_cc_in_req_ready = auto_rerocc_tile_re_ro_cc_in_req_ready_0; // @[ClockDomain.scala:14:9]
assign auto_rerocc_tile_re_ro_cc_in_resp_valid = auto_rerocc_tile_re_ro_cc_in_resp_valid_0; // @[ClockDomain.scala:14:9]
assign auto_rerocc_tile_re_ro_cc_in_resp_bits_opcode = auto_rerocc_tile_re_ro_cc_in_resp_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_rerocc_tile_re_ro_cc_in_resp_bits_client_id = auto_rerocc_tile_re_ro_cc_in_resp_bits_client_id_0; // @[ClockDomain.scala:14:9]
assign auto_rerocc_tile_re_ro_cc_in_resp_bits_manager_id = auto_rerocc_tile_re_ro_cc_in_resp_bits_manager_id_0; // @[ClockDomain.scala:14:9]
assign auto_rerocc_tile_re_ro_cc_in_resp_bits_data = auto_rerocc_tile_re_ro_cc_in_resp_bits_data_0; // @[ClockDomain.scala:14:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_105 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_source_valid_1 of AsyncResetSynchronizerShiftReg_w1_d3_i0_122
connect io_out_source_valid_1.clock, clock
connect io_out_source_valid_1.reset, reset
connect io_out_source_valid_1.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_source_valid_1.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_105( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_122 io_out_source_valid_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module Repeater_TLBundleA_a32d256s5k3z4u_5 :
input clock : Clock
input reset : Reset
output io : { flip repeat : UInt<1>, full : UInt<1>, flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}}
regreset full : UInt<1>, clock, reset, UInt<1>(0h0)
reg saved : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}, clock
node _io_deq_valid_T = or(io.enq.valid, full)
connect io.deq.valid, _io_deq_valid_T
node _io_enq_ready_T = eq(full, UInt<1>(0h0))
node _io_enq_ready_T_1 = and(io.deq.ready, _io_enq_ready_T)
connect io.enq.ready, _io_enq_ready_T_1
node _io_deq_bits_T = mux(full, saved, io.enq.bits)
connect io.deq.bits, _io_deq_bits_T
connect io.full, full
node _T = and(io.enq.ready, io.enq.valid)
node _T_1 = and(_T, io.repeat)
when _T_1 :
connect full, UInt<1>(0h1)
connect saved, io.enq.bits
node _T_2 = and(io.deq.ready, io.deq.valid)
node _T_3 = eq(io.repeat, UInt<1>(0h0))
node _T_4 = and(_T_2, _T_3)
when _T_4 :
connect full, UInt<1>(0h0) | module Repeater_TLBundleA_a32d256s5k3z4u_5( // @[Repeater.scala:10:7]
input clock, // @[Repeater.scala:10:7]
input reset, // @[Repeater.scala:10:7]
input io_repeat, // @[Repeater.scala:13:14]
output io_enq_ready, // @[Repeater.scala:13:14]
input io_enq_valid, // @[Repeater.scala:13:14]
input [2:0] io_enq_bits_opcode, // @[Repeater.scala:13:14]
input [2:0] io_enq_bits_param, // @[Repeater.scala:13:14]
input [3:0] io_enq_bits_size, // @[Repeater.scala:13:14]
input [4:0] io_enq_bits_source, // @[Repeater.scala:13:14]
input [31:0] io_enq_bits_address, // @[Repeater.scala:13:14]
input [31:0] io_enq_bits_mask, // @[Repeater.scala:13:14]
input [255:0] io_enq_bits_data, // @[Repeater.scala:13:14]
input io_enq_bits_corrupt, // @[Repeater.scala:13:14]
input io_deq_ready, // @[Repeater.scala:13:14]
output io_deq_valid, // @[Repeater.scala:13:14]
output [2:0] io_deq_bits_opcode, // @[Repeater.scala:13:14]
output [2:0] io_deq_bits_param, // @[Repeater.scala:13:14]
output [3:0] io_deq_bits_size, // @[Repeater.scala:13:14]
output [4:0] io_deq_bits_source, // @[Repeater.scala:13:14]
output [31:0] io_deq_bits_address, // @[Repeater.scala:13:14]
output [31:0] io_deq_bits_mask, // @[Repeater.scala:13:14]
output [255:0] io_deq_bits_data, // @[Repeater.scala:13:14]
output io_deq_bits_corrupt // @[Repeater.scala:13:14]
);
wire io_repeat_0 = io_repeat; // @[Repeater.scala:10:7]
wire io_enq_valid_0 = io_enq_valid; // @[Repeater.scala:10:7]
wire [2:0] io_enq_bits_opcode_0 = io_enq_bits_opcode; // @[Repeater.scala:10:7]
wire [2:0] io_enq_bits_param_0 = io_enq_bits_param; // @[Repeater.scala:10:7]
wire [3:0] io_enq_bits_size_0 = io_enq_bits_size; // @[Repeater.scala:10:7]
wire [4:0] io_enq_bits_source_0 = io_enq_bits_source; // @[Repeater.scala:10:7]
wire [31:0] io_enq_bits_address_0 = io_enq_bits_address; // @[Repeater.scala:10:7]
wire [31:0] io_enq_bits_mask_0 = io_enq_bits_mask; // @[Repeater.scala:10:7]
wire [255:0] io_enq_bits_data_0 = io_enq_bits_data; // @[Repeater.scala:10:7]
wire io_enq_bits_corrupt_0 = io_enq_bits_corrupt; // @[Repeater.scala:10:7]
wire io_deq_ready_0 = io_deq_ready; // @[Repeater.scala:10:7]
wire _io_enq_ready_T_1; // @[Repeater.scala:25:32]
wire _io_deq_valid_T; // @[Repeater.scala:24:32]
wire [2:0] _io_deq_bits_T_opcode; // @[Repeater.scala:26:21]
wire [2:0] _io_deq_bits_T_param; // @[Repeater.scala:26:21]
wire [3:0] _io_deq_bits_T_size; // @[Repeater.scala:26:21]
wire [4:0] _io_deq_bits_T_source; // @[Repeater.scala:26:21]
wire [31:0] _io_deq_bits_T_address; // @[Repeater.scala:26:21]
wire [31:0] _io_deq_bits_T_mask; // @[Repeater.scala:26:21]
wire [255:0] _io_deq_bits_T_data; // @[Repeater.scala:26:21]
wire _io_deq_bits_T_corrupt; // @[Repeater.scala:26:21]
wire io_enq_ready_0; // @[Repeater.scala:10:7]
wire [2:0] io_deq_bits_opcode_0; // @[Repeater.scala:10:7]
wire [2:0] io_deq_bits_param_0; // @[Repeater.scala:10:7]
wire [3:0] io_deq_bits_size_0; // @[Repeater.scala:10:7]
wire [4:0] io_deq_bits_source_0; // @[Repeater.scala:10:7]
wire [31:0] io_deq_bits_address_0; // @[Repeater.scala:10:7]
wire [31:0] io_deq_bits_mask_0; // @[Repeater.scala:10:7]
wire [255:0] io_deq_bits_data_0; // @[Repeater.scala:10:7]
wire io_deq_bits_corrupt_0; // @[Repeater.scala:10:7]
wire io_deq_valid_0; // @[Repeater.scala:10:7]
wire io_full; // @[Repeater.scala:10:7]
reg full; // @[Repeater.scala:20:21]
assign io_full = full; // @[Repeater.scala:10:7, :20:21]
reg [2:0] saved_opcode; // @[Repeater.scala:21:18]
reg [2:0] saved_param; // @[Repeater.scala:21:18]
reg [3:0] saved_size; // @[Repeater.scala:21:18]
reg [4:0] saved_source; // @[Repeater.scala:21:18]
reg [31:0] saved_address; // @[Repeater.scala:21:18]
reg [31:0] saved_mask; // @[Repeater.scala:21:18]
reg [255:0] saved_data; // @[Repeater.scala:21:18]
reg saved_corrupt; // @[Repeater.scala:21:18]
assign _io_deq_valid_T = io_enq_valid_0 | full; // @[Repeater.scala:10:7, :20:21, :24:32]
assign io_deq_valid_0 = _io_deq_valid_T; // @[Repeater.scala:10:7, :24:32]
wire _io_enq_ready_T = ~full; // @[Repeater.scala:20:21, :25:35]
assign _io_enq_ready_T_1 = io_deq_ready_0 & _io_enq_ready_T; // @[Repeater.scala:10:7, :25:{32,35}]
assign io_enq_ready_0 = _io_enq_ready_T_1; // @[Repeater.scala:10:7, :25:32]
assign _io_deq_bits_T_opcode = full ? saved_opcode : io_enq_bits_opcode_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_param = full ? saved_param : io_enq_bits_param_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_size = full ? saved_size : io_enq_bits_size_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_source = full ? saved_source : io_enq_bits_source_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_address = full ? saved_address : io_enq_bits_address_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_mask = full ? saved_mask : io_enq_bits_mask_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_data = full ? saved_data : io_enq_bits_data_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_corrupt = full ? saved_corrupt : io_enq_bits_corrupt_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign io_deq_bits_opcode_0 = _io_deq_bits_T_opcode; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_param_0 = _io_deq_bits_T_param; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_size_0 = _io_deq_bits_T_size; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_source_0 = _io_deq_bits_T_source; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_address_0 = _io_deq_bits_T_address; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_mask_0 = _io_deq_bits_T_mask; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_data_0 = _io_deq_bits_T_data; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_corrupt_0 = _io_deq_bits_T_corrupt; // @[Repeater.scala:10:7, :26:21]
wire _T_1 = io_enq_ready_0 & io_enq_valid_0 & io_repeat_0; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[Repeater.scala:10:7]
if (reset) // @[Repeater.scala:10:7]
full <= 1'h0; // @[Repeater.scala:20:21]
else // @[Repeater.scala:10:7]
full <= ~(io_deq_ready_0 & io_deq_valid_0 & ~io_repeat_0) & (_T_1 | full); // @[Decoupled.scala:51:35]
if (_T_1) begin // @[Decoupled.scala:51:35]
saved_opcode <= io_enq_bits_opcode_0; // @[Repeater.scala:10:7, :21:18]
saved_param <= io_enq_bits_param_0; // @[Repeater.scala:10:7, :21:18]
saved_size <= io_enq_bits_size_0; // @[Repeater.scala:10:7, :21:18]
saved_source <= io_enq_bits_source_0; // @[Repeater.scala:10:7, :21:18]
saved_address <= io_enq_bits_address_0; // @[Repeater.scala:10:7, :21:18]
saved_mask <= io_enq_bits_mask_0; // @[Repeater.scala:10:7, :21:18]
saved_data <= io_enq_bits_data_0; // @[Repeater.scala:10:7, :21:18]
saved_corrupt <= io_enq_bits_corrupt_0; // @[Repeater.scala:10:7, :21:18]
end
always @(posedge)
assign io_enq_ready = io_enq_ready_0; // @[Repeater.scala:10:7]
assign io_deq_valid = io_deq_valid_0; // @[Repeater.scala:10:7]
assign io_deq_bits_opcode = io_deq_bits_opcode_0; // @[Repeater.scala:10:7]
assign io_deq_bits_param = io_deq_bits_param_0; // @[Repeater.scala:10:7]
assign io_deq_bits_size = io_deq_bits_size_0; // @[Repeater.scala:10:7]
assign io_deq_bits_source = io_deq_bits_source_0; // @[Repeater.scala:10:7]
assign io_deq_bits_address = io_deq_bits_address_0; // @[Repeater.scala:10:7]
assign io_deq_bits_mask = io_deq_bits_mask_0; // @[Repeater.scala:10:7]
assign io_deq_bits_data = io_deq_bits_data_0; // @[Repeater.scala:10:7]
assign io_deq_bits_corrupt = io_deq_bits_corrupt_0; // @[Repeater.scala:10:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_132 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_sink_valid_0 of AsyncResetSynchronizerShiftReg_w1_d3_i0_146
connect io_out_sink_valid_0.clock, clock
connect io_out_sink_valid_0.reset, reset
connect io_out_sink_valid_0.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_sink_valid_0.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_132( // @[AsyncQueue.scala:58:7]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in = 1'h1; // @[ShiftReg.scala:45:23]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_146 io_out_sink_valid_0 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_56 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 3, 0)
node _source_ok_T = shr(io.in.a.bits.source, 4)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<4>(0h9))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T_5
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits = bits(_uncommonBits_T, 3, 0)
node _T_4 = shr(io.in.a.bits.source, 4)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<4>(0h9))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_16, UInt<1>(0h1), "") : assert_1
node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_20 :
node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_23 = and(_T_21, _T_22)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 3, 0)
node _T_24 = shr(io.in.a.bits.source, 4)
node _T_25 = eq(_T_24, UInt<1>(0h0))
node _T_26 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_27 = and(_T_25, _T_26)
node _T_28 = leq(uncommonBits_1, UInt<4>(0h9))
node _T_29 = and(_T_27, _T_28)
node _T_30 = and(_T_23, _T_29)
node _T_31 = or(UInt<1>(0h0), _T_30)
node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_33 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_34 = cvt(_T_33)
node _T_35 = and(_T_34, asSInt(UInt<17>(0h100c0)))
node _T_36 = asSInt(_T_35)
node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0)))
node _T_38 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_39 = cvt(_T_38)
node _T_40 = and(_T_39, asSInt(UInt<29>(0h100000c0)))
node _T_41 = asSInt(_T_40)
node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0)))
node _T_43 = or(_T_37, _T_42)
node _T_44 = and(_T_32, _T_43)
node _T_45 = or(UInt<1>(0h0), _T_44)
node _T_46 = and(_T_31, _T_45)
node _T_47 = asUInt(reset)
node _T_48 = eq(_T_47, UInt<1>(0h0))
when _T_48 :
node _T_49 = eq(_T_46, UInt<1>(0h0))
when _T_49 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_46, UInt<1>(0h1), "") : assert_2
node _T_50 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_51 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_52 = and(_T_50, _T_51)
node _T_53 = or(UInt<1>(0h0), _T_52)
node _T_54 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_55 = cvt(_T_54)
node _T_56 = and(_T_55, asSInt(UInt<17>(0h100c0)))
node _T_57 = asSInt(_T_56)
node _T_58 = eq(_T_57, asSInt(UInt<1>(0h0)))
node _T_59 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_60 = cvt(_T_59)
node _T_61 = and(_T_60, asSInt(UInt<29>(0h100000c0)))
node _T_62 = asSInt(_T_61)
node _T_63 = eq(_T_62, asSInt(UInt<1>(0h0)))
node _T_64 = or(_T_58, _T_63)
node _T_65 = and(_T_53, _T_64)
node _T_66 = or(UInt<1>(0h0), _T_65)
node _T_67 = and(UInt<1>(0h0), _T_66)
node _T_68 = asUInt(reset)
node _T_69 = eq(_T_68, UInt<1>(0h0))
when _T_69 :
node _T_70 = eq(_T_67, UInt<1>(0h0))
when _T_70 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_67, UInt<1>(0h1), "") : assert_3
node _T_71 = asUInt(reset)
node _T_72 = eq(_T_71, UInt<1>(0h0))
when _T_72 :
node _T_73 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_73 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_74 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_75 = asUInt(reset)
node _T_76 = eq(_T_75, UInt<1>(0h0))
when _T_76 :
node _T_77 = eq(_T_74, UInt<1>(0h0))
when _T_77 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_74, UInt<1>(0h1), "") : assert_5
node _T_78 = asUInt(reset)
node _T_79 = eq(_T_78, UInt<1>(0h0))
when _T_79 :
node _T_80 = eq(is_aligned, UInt<1>(0h0))
when _T_80 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_81 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_82 = asUInt(reset)
node _T_83 = eq(_T_82, UInt<1>(0h0))
when _T_83 :
node _T_84 = eq(_T_81, UInt<1>(0h0))
when _T_84 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_81, UInt<1>(0h1), "") : assert_7
node _T_85 = not(io.in.a.bits.mask)
node _T_86 = eq(_T_85, UInt<1>(0h0))
node _T_87 = asUInt(reset)
node _T_88 = eq(_T_87, UInt<1>(0h0))
when _T_88 :
node _T_89 = eq(_T_86, UInt<1>(0h0))
when _T_89 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_86, UInt<1>(0h1), "") : assert_8
node _T_90 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_91 = asUInt(reset)
node _T_92 = eq(_T_91, UInt<1>(0h0))
when _T_92 :
node _T_93 = eq(_T_90, UInt<1>(0h0))
when _T_93 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_90, UInt<1>(0h1), "") : assert_9
node _T_94 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_94 :
node _T_95 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_96 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_97 = and(_T_95, _T_96)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 3, 0)
node _T_98 = shr(io.in.a.bits.source, 4)
node _T_99 = eq(_T_98, UInt<1>(0h0))
node _T_100 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_101 = and(_T_99, _T_100)
node _T_102 = leq(uncommonBits_2, UInt<4>(0h9))
node _T_103 = and(_T_101, _T_102)
node _T_104 = and(_T_97, _T_103)
node _T_105 = or(UInt<1>(0h0), _T_104)
node _T_106 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_107 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_108 = cvt(_T_107)
node _T_109 = and(_T_108, asSInt(UInt<17>(0h100c0)))
node _T_110 = asSInt(_T_109)
node _T_111 = eq(_T_110, asSInt(UInt<1>(0h0)))
node _T_112 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_113 = cvt(_T_112)
node _T_114 = and(_T_113, asSInt(UInt<29>(0h100000c0)))
node _T_115 = asSInt(_T_114)
node _T_116 = eq(_T_115, asSInt(UInt<1>(0h0)))
node _T_117 = or(_T_111, _T_116)
node _T_118 = and(_T_106, _T_117)
node _T_119 = or(UInt<1>(0h0), _T_118)
node _T_120 = and(_T_105, _T_119)
node _T_121 = asUInt(reset)
node _T_122 = eq(_T_121, UInt<1>(0h0))
when _T_122 :
node _T_123 = eq(_T_120, UInt<1>(0h0))
when _T_123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_120, UInt<1>(0h1), "") : assert_10
node _T_124 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_125 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_126 = and(_T_124, _T_125)
node _T_127 = or(UInt<1>(0h0), _T_126)
node _T_128 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_129 = cvt(_T_128)
node _T_130 = and(_T_129, asSInt(UInt<17>(0h100c0)))
node _T_131 = asSInt(_T_130)
node _T_132 = eq(_T_131, asSInt(UInt<1>(0h0)))
node _T_133 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_134 = cvt(_T_133)
node _T_135 = and(_T_134, asSInt(UInt<29>(0h100000c0)))
node _T_136 = asSInt(_T_135)
node _T_137 = eq(_T_136, asSInt(UInt<1>(0h0)))
node _T_138 = or(_T_132, _T_137)
node _T_139 = and(_T_127, _T_138)
node _T_140 = or(UInt<1>(0h0), _T_139)
node _T_141 = and(UInt<1>(0h0), _T_140)
node _T_142 = asUInt(reset)
node _T_143 = eq(_T_142, UInt<1>(0h0))
when _T_143 :
node _T_144 = eq(_T_141, UInt<1>(0h0))
when _T_144 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_141, UInt<1>(0h1), "") : assert_11
node _T_145 = asUInt(reset)
node _T_146 = eq(_T_145, UInt<1>(0h0))
when _T_146 :
node _T_147 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_147 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_148 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_149 = asUInt(reset)
node _T_150 = eq(_T_149, UInt<1>(0h0))
when _T_150 :
node _T_151 = eq(_T_148, UInt<1>(0h0))
when _T_151 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_148, UInt<1>(0h1), "") : assert_13
node _T_152 = asUInt(reset)
node _T_153 = eq(_T_152, UInt<1>(0h0))
when _T_153 :
node _T_154 = eq(is_aligned, UInt<1>(0h0))
when _T_154 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_155 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_156 = asUInt(reset)
node _T_157 = eq(_T_156, UInt<1>(0h0))
when _T_157 :
node _T_158 = eq(_T_155, UInt<1>(0h0))
when _T_158 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_155, UInt<1>(0h1), "") : assert_15
node _T_159 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(_T_159, UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_159, UInt<1>(0h1), "") : assert_16
node _T_163 = not(io.in.a.bits.mask)
node _T_164 = eq(_T_163, UInt<1>(0h0))
node _T_165 = asUInt(reset)
node _T_166 = eq(_T_165, UInt<1>(0h0))
when _T_166 :
node _T_167 = eq(_T_164, UInt<1>(0h0))
when _T_167 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_164, UInt<1>(0h1), "") : assert_17
node _T_168 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_169 = asUInt(reset)
node _T_170 = eq(_T_169, UInt<1>(0h0))
when _T_170 :
node _T_171 = eq(_T_168, UInt<1>(0h0))
when _T_171 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_168, UInt<1>(0h1), "") : assert_18
node _T_172 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_172 :
node _T_173 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_174 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_175 = and(_T_173, _T_174)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 3, 0)
node _T_176 = shr(io.in.a.bits.source, 4)
node _T_177 = eq(_T_176, UInt<1>(0h0))
node _T_178 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_179 = and(_T_177, _T_178)
node _T_180 = leq(uncommonBits_3, UInt<4>(0h9))
node _T_181 = and(_T_179, _T_180)
node _T_182 = and(_T_175, _T_181)
node _T_183 = or(UInt<1>(0h0), _T_182)
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_183, UInt<1>(0h1), "") : assert_19
node _T_187 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_188 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_189 = and(_T_187, _T_188)
node _T_190 = or(UInt<1>(0h0), _T_189)
node _T_191 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_192 = cvt(_T_191)
node _T_193 = and(_T_192, asSInt(UInt<17>(0h100c0)))
node _T_194 = asSInt(_T_193)
node _T_195 = eq(_T_194, asSInt(UInt<1>(0h0)))
node _T_196 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_197 = cvt(_T_196)
node _T_198 = and(_T_197, asSInt(UInt<29>(0h100000c0)))
node _T_199 = asSInt(_T_198)
node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0)))
node _T_201 = or(_T_195, _T_200)
node _T_202 = and(_T_190, _T_201)
node _T_203 = or(UInt<1>(0h0), _T_202)
node _T_204 = asUInt(reset)
node _T_205 = eq(_T_204, UInt<1>(0h0))
when _T_205 :
node _T_206 = eq(_T_203, UInt<1>(0h0))
when _T_206 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_203, UInt<1>(0h1), "") : assert_20
node _T_207 = asUInt(reset)
node _T_208 = eq(_T_207, UInt<1>(0h0))
when _T_208 :
node _T_209 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_209 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_210 = asUInt(reset)
node _T_211 = eq(_T_210, UInt<1>(0h0))
when _T_211 :
node _T_212 = eq(is_aligned, UInt<1>(0h0))
when _T_212 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_213 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_214 = asUInt(reset)
node _T_215 = eq(_T_214, UInt<1>(0h0))
when _T_215 :
node _T_216 = eq(_T_213, UInt<1>(0h0))
when _T_216 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_213, UInt<1>(0h1), "") : assert_23
node _T_217 = eq(io.in.a.bits.mask, mask)
node _T_218 = asUInt(reset)
node _T_219 = eq(_T_218, UInt<1>(0h0))
when _T_219 :
node _T_220 = eq(_T_217, UInt<1>(0h0))
when _T_220 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_217, UInt<1>(0h1), "") : assert_24
node _T_221 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_222 = asUInt(reset)
node _T_223 = eq(_T_222, UInt<1>(0h0))
when _T_223 :
node _T_224 = eq(_T_221, UInt<1>(0h0))
when _T_224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_221, UInt<1>(0h1), "") : assert_25
node _T_225 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_225 :
node _T_226 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_227 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_228 = and(_T_226, _T_227)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 3, 0)
node _T_229 = shr(io.in.a.bits.source, 4)
node _T_230 = eq(_T_229, UInt<1>(0h0))
node _T_231 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_232 = and(_T_230, _T_231)
node _T_233 = leq(uncommonBits_4, UInt<4>(0h9))
node _T_234 = and(_T_232, _T_233)
node _T_235 = and(_T_228, _T_234)
node _T_236 = or(UInt<1>(0h0), _T_235)
node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_238 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_239 = and(_T_237, _T_238)
node _T_240 = or(UInt<1>(0h0), _T_239)
node _T_241 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_242 = cvt(_T_241)
node _T_243 = and(_T_242, asSInt(UInt<17>(0h100c0)))
node _T_244 = asSInt(_T_243)
node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0)))
node _T_246 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_247 = cvt(_T_246)
node _T_248 = and(_T_247, asSInt(UInt<29>(0h100000c0)))
node _T_249 = asSInt(_T_248)
node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0)))
node _T_251 = or(_T_245, _T_250)
node _T_252 = and(_T_240, _T_251)
node _T_253 = or(UInt<1>(0h0), _T_252)
node _T_254 = and(_T_236, _T_253)
node _T_255 = asUInt(reset)
node _T_256 = eq(_T_255, UInt<1>(0h0))
when _T_256 :
node _T_257 = eq(_T_254, UInt<1>(0h0))
when _T_257 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_254, UInt<1>(0h1), "") : assert_26
node _T_258 = asUInt(reset)
node _T_259 = eq(_T_258, UInt<1>(0h0))
when _T_259 :
node _T_260 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_260 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_261 = asUInt(reset)
node _T_262 = eq(_T_261, UInt<1>(0h0))
when _T_262 :
node _T_263 = eq(is_aligned, UInt<1>(0h0))
when _T_263 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_264 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_265 = asUInt(reset)
node _T_266 = eq(_T_265, UInt<1>(0h0))
when _T_266 :
node _T_267 = eq(_T_264, UInt<1>(0h0))
when _T_267 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_264, UInt<1>(0h1), "") : assert_29
node _T_268 = eq(io.in.a.bits.mask, mask)
node _T_269 = asUInt(reset)
node _T_270 = eq(_T_269, UInt<1>(0h0))
when _T_270 :
node _T_271 = eq(_T_268, UInt<1>(0h0))
when _T_271 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_268, UInt<1>(0h1), "") : assert_30
node _T_272 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_272 :
node _T_273 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_274 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_275 = and(_T_273, _T_274)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 3, 0)
node _T_276 = shr(io.in.a.bits.source, 4)
node _T_277 = eq(_T_276, UInt<1>(0h0))
node _T_278 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_279 = and(_T_277, _T_278)
node _T_280 = leq(uncommonBits_5, UInt<4>(0h9))
node _T_281 = and(_T_279, _T_280)
node _T_282 = and(_T_275, _T_281)
node _T_283 = or(UInt<1>(0h0), _T_282)
node _T_284 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_285 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_286 = and(_T_284, _T_285)
node _T_287 = or(UInt<1>(0h0), _T_286)
node _T_288 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_289 = cvt(_T_288)
node _T_290 = and(_T_289, asSInt(UInt<17>(0h100c0)))
node _T_291 = asSInt(_T_290)
node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0)))
node _T_293 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_294 = cvt(_T_293)
node _T_295 = and(_T_294, asSInt(UInt<29>(0h100000c0)))
node _T_296 = asSInt(_T_295)
node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0)))
node _T_298 = or(_T_292, _T_297)
node _T_299 = and(_T_287, _T_298)
node _T_300 = or(UInt<1>(0h0), _T_299)
node _T_301 = and(_T_283, _T_300)
node _T_302 = asUInt(reset)
node _T_303 = eq(_T_302, UInt<1>(0h0))
when _T_303 :
node _T_304 = eq(_T_301, UInt<1>(0h0))
when _T_304 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_301, UInt<1>(0h1), "") : assert_31
node _T_305 = asUInt(reset)
node _T_306 = eq(_T_305, UInt<1>(0h0))
when _T_306 :
node _T_307 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_307 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_308 = asUInt(reset)
node _T_309 = eq(_T_308, UInt<1>(0h0))
when _T_309 :
node _T_310 = eq(is_aligned, UInt<1>(0h0))
when _T_310 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_311 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_312 = asUInt(reset)
node _T_313 = eq(_T_312, UInt<1>(0h0))
when _T_313 :
node _T_314 = eq(_T_311, UInt<1>(0h0))
when _T_314 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_311, UInt<1>(0h1), "") : assert_34
node _T_315 = not(mask)
node _T_316 = and(io.in.a.bits.mask, _T_315)
node _T_317 = eq(_T_316, UInt<1>(0h0))
node _T_318 = asUInt(reset)
node _T_319 = eq(_T_318, UInt<1>(0h0))
when _T_319 :
node _T_320 = eq(_T_317, UInt<1>(0h0))
when _T_320 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_317, UInt<1>(0h1), "") : assert_35
node _T_321 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_321 :
node _T_322 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_323 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_324 = and(_T_322, _T_323)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 3, 0)
node _T_325 = shr(io.in.a.bits.source, 4)
node _T_326 = eq(_T_325, UInt<1>(0h0))
node _T_327 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_328 = and(_T_326, _T_327)
node _T_329 = leq(uncommonBits_6, UInt<4>(0h9))
node _T_330 = and(_T_328, _T_329)
node _T_331 = and(_T_324, _T_330)
node _T_332 = or(UInt<1>(0h0), _T_331)
node _T_333 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_334 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_335 = cvt(_T_334)
node _T_336 = and(_T_335, asSInt(UInt<17>(0h100c0)))
node _T_337 = asSInt(_T_336)
node _T_338 = eq(_T_337, asSInt(UInt<1>(0h0)))
node _T_339 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_340 = cvt(_T_339)
node _T_341 = and(_T_340, asSInt(UInt<29>(0h100000c0)))
node _T_342 = asSInt(_T_341)
node _T_343 = eq(_T_342, asSInt(UInt<1>(0h0)))
node _T_344 = or(_T_338, _T_343)
node _T_345 = and(_T_333, _T_344)
node _T_346 = or(UInt<1>(0h0), _T_345)
node _T_347 = and(_T_332, _T_346)
node _T_348 = asUInt(reset)
node _T_349 = eq(_T_348, UInt<1>(0h0))
when _T_349 :
node _T_350 = eq(_T_347, UInt<1>(0h0))
when _T_350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_347, UInt<1>(0h1), "") : assert_36
node _T_351 = asUInt(reset)
node _T_352 = eq(_T_351, UInt<1>(0h0))
when _T_352 :
node _T_353 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_353 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_354 = asUInt(reset)
node _T_355 = eq(_T_354, UInt<1>(0h0))
when _T_355 :
node _T_356 = eq(is_aligned, UInt<1>(0h0))
when _T_356 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_357 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_358 = asUInt(reset)
node _T_359 = eq(_T_358, UInt<1>(0h0))
when _T_359 :
node _T_360 = eq(_T_357, UInt<1>(0h0))
when _T_360 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_357, UInt<1>(0h1), "") : assert_39
node _T_361 = eq(io.in.a.bits.mask, mask)
node _T_362 = asUInt(reset)
node _T_363 = eq(_T_362, UInt<1>(0h0))
when _T_363 :
node _T_364 = eq(_T_361, UInt<1>(0h0))
when _T_364 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_361, UInt<1>(0h1), "") : assert_40
node _T_365 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_365 :
node _T_366 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_367 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_368 = and(_T_366, _T_367)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 3, 0)
node _T_369 = shr(io.in.a.bits.source, 4)
node _T_370 = eq(_T_369, UInt<1>(0h0))
node _T_371 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_372 = and(_T_370, _T_371)
node _T_373 = leq(uncommonBits_7, UInt<4>(0h9))
node _T_374 = and(_T_372, _T_373)
node _T_375 = and(_T_368, _T_374)
node _T_376 = or(UInt<1>(0h0), _T_375)
node _T_377 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_378 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_379 = cvt(_T_378)
node _T_380 = and(_T_379, asSInt(UInt<17>(0h100c0)))
node _T_381 = asSInt(_T_380)
node _T_382 = eq(_T_381, asSInt(UInt<1>(0h0)))
node _T_383 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_384 = cvt(_T_383)
node _T_385 = and(_T_384, asSInt(UInt<29>(0h100000c0)))
node _T_386 = asSInt(_T_385)
node _T_387 = eq(_T_386, asSInt(UInt<1>(0h0)))
node _T_388 = or(_T_382, _T_387)
node _T_389 = and(_T_377, _T_388)
node _T_390 = or(UInt<1>(0h0), _T_389)
node _T_391 = and(_T_376, _T_390)
node _T_392 = asUInt(reset)
node _T_393 = eq(_T_392, UInt<1>(0h0))
when _T_393 :
node _T_394 = eq(_T_391, UInt<1>(0h0))
when _T_394 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_391, UInt<1>(0h1), "") : assert_41
node _T_395 = asUInt(reset)
node _T_396 = eq(_T_395, UInt<1>(0h0))
when _T_396 :
node _T_397 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_397 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(is_aligned, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_401 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_402 = asUInt(reset)
node _T_403 = eq(_T_402, UInt<1>(0h0))
when _T_403 :
node _T_404 = eq(_T_401, UInt<1>(0h0))
when _T_404 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_401, UInt<1>(0h1), "") : assert_44
node _T_405 = eq(io.in.a.bits.mask, mask)
node _T_406 = asUInt(reset)
node _T_407 = eq(_T_406, UInt<1>(0h0))
when _T_407 :
node _T_408 = eq(_T_405, UInt<1>(0h0))
when _T_408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_405, UInt<1>(0h1), "") : assert_45
node _T_409 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_409 :
node _T_410 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_411 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_412 = and(_T_410, _T_411)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 3, 0)
node _T_413 = shr(io.in.a.bits.source, 4)
node _T_414 = eq(_T_413, UInt<1>(0h0))
node _T_415 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_416 = and(_T_414, _T_415)
node _T_417 = leq(uncommonBits_8, UInt<4>(0h9))
node _T_418 = and(_T_416, _T_417)
node _T_419 = and(_T_412, _T_418)
node _T_420 = or(UInt<1>(0h0), _T_419)
node _T_421 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_422 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_423 = cvt(_T_422)
node _T_424 = and(_T_423, asSInt(UInt<17>(0h100c0)))
node _T_425 = asSInt(_T_424)
node _T_426 = eq(_T_425, asSInt(UInt<1>(0h0)))
node _T_427 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_428 = cvt(_T_427)
node _T_429 = and(_T_428, asSInt(UInt<29>(0h100000c0)))
node _T_430 = asSInt(_T_429)
node _T_431 = eq(_T_430, asSInt(UInt<1>(0h0)))
node _T_432 = or(_T_426, _T_431)
node _T_433 = and(_T_421, _T_432)
node _T_434 = or(UInt<1>(0h0), _T_433)
node _T_435 = and(_T_420, _T_434)
node _T_436 = asUInt(reset)
node _T_437 = eq(_T_436, UInt<1>(0h0))
when _T_437 :
node _T_438 = eq(_T_435, UInt<1>(0h0))
when _T_438 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_435, UInt<1>(0h1), "") : assert_46
node _T_439 = asUInt(reset)
node _T_440 = eq(_T_439, UInt<1>(0h0))
when _T_440 :
node _T_441 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_441 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_442 = asUInt(reset)
node _T_443 = eq(_T_442, UInt<1>(0h0))
when _T_443 :
node _T_444 = eq(is_aligned, UInt<1>(0h0))
when _T_444 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_445 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_445, UInt<1>(0h1), "") : assert_49
node _T_449 = eq(io.in.a.bits.mask, mask)
node _T_450 = asUInt(reset)
node _T_451 = eq(_T_450, UInt<1>(0h0))
when _T_451 :
node _T_452 = eq(_T_449, UInt<1>(0h0))
when _T_452 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_449, UInt<1>(0h1), "") : assert_50
node _T_453 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_454 = asUInt(reset)
node _T_455 = eq(_T_454, UInt<1>(0h0))
when _T_455 :
node _T_456 = eq(_T_453, UInt<1>(0h0))
when _T_456 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_453, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_457 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_458 = asUInt(reset)
node _T_459 = eq(_T_458, UInt<1>(0h0))
when _T_459 :
node _T_460 = eq(_T_457, UInt<1>(0h0))
when _T_460 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_457, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 3, 0)
node _source_ok_T_6 = shr(io.in.d.bits.source, 4)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<4>(0h9))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_11
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_461 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_461 :
node _T_462 = asUInt(reset)
node _T_463 = eq(_T_462, UInt<1>(0h0))
when _T_463 :
node _T_464 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_464 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_465 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_466 = asUInt(reset)
node _T_467 = eq(_T_466, UInt<1>(0h0))
when _T_467 :
node _T_468 = eq(_T_465, UInt<1>(0h0))
when _T_468 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_465, UInt<1>(0h1), "") : assert_54
node _T_469 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_470 = asUInt(reset)
node _T_471 = eq(_T_470, UInt<1>(0h0))
when _T_471 :
node _T_472 = eq(_T_469, UInt<1>(0h0))
when _T_472 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_469, UInt<1>(0h1), "") : assert_55
node _T_473 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_474 = asUInt(reset)
node _T_475 = eq(_T_474, UInt<1>(0h0))
when _T_475 :
node _T_476 = eq(_T_473, UInt<1>(0h0))
when _T_476 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_473, UInt<1>(0h1), "") : assert_56
node _T_477 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_478 = asUInt(reset)
node _T_479 = eq(_T_478, UInt<1>(0h0))
when _T_479 :
node _T_480 = eq(_T_477, UInt<1>(0h0))
when _T_480 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_477, UInt<1>(0h1), "") : assert_57
node _T_481 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_481 :
node _T_482 = asUInt(reset)
node _T_483 = eq(_T_482, UInt<1>(0h0))
when _T_483 :
node _T_484 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_484 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_485 = asUInt(reset)
node _T_486 = eq(_T_485, UInt<1>(0h0))
when _T_486 :
node _T_487 = eq(sink_ok, UInt<1>(0h0))
when _T_487 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_488 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_489 = asUInt(reset)
node _T_490 = eq(_T_489, UInt<1>(0h0))
when _T_490 :
node _T_491 = eq(_T_488, UInt<1>(0h0))
when _T_491 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_488, UInt<1>(0h1), "") : assert_60
node _T_492 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_493 = asUInt(reset)
node _T_494 = eq(_T_493, UInt<1>(0h0))
when _T_494 :
node _T_495 = eq(_T_492, UInt<1>(0h0))
when _T_495 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_492, UInt<1>(0h1), "") : assert_61
node _T_496 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_497 = asUInt(reset)
node _T_498 = eq(_T_497, UInt<1>(0h0))
when _T_498 :
node _T_499 = eq(_T_496, UInt<1>(0h0))
when _T_499 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_496, UInt<1>(0h1), "") : assert_62
node _T_500 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_501 = asUInt(reset)
node _T_502 = eq(_T_501, UInt<1>(0h0))
when _T_502 :
node _T_503 = eq(_T_500, UInt<1>(0h0))
when _T_503 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_500, UInt<1>(0h1), "") : assert_63
node _T_504 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_505 = or(UInt<1>(0h1), _T_504)
node _T_506 = asUInt(reset)
node _T_507 = eq(_T_506, UInt<1>(0h0))
when _T_507 :
node _T_508 = eq(_T_505, UInt<1>(0h0))
when _T_508 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_505, UInt<1>(0h1), "") : assert_64
node _T_509 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_509 :
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_513 = asUInt(reset)
node _T_514 = eq(_T_513, UInt<1>(0h0))
when _T_514 :
node _T_515 = eq(sink_ok, UInt<1>(0h0))
when _T_515 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_516 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_517 = asUInt(reset)
node _T_518 = eq(_T_517, UInt<1>(0h0))
when _T_518 :
node _T_519 = eq(_T_516, UInt<1>(0h0))
when _T_519 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_516, UInt<1>(0h1), "") : assert_67
node _T_520 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_521 = asUInt(reset)
node _T_522 = eq(_T_521, UInt<1>(0h0))
when _T_522 :
node _T_523 = eq(_T_520, UInt<1>(0h0))
when _T_523 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_520, UInt<1>(0h1), "") : assert_68
node _T_524 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_525 = asUInt(reset)
node _T_526 = eq(_T_525, UInt<1>(0h0))
when _T_526 :
node _T_527 = eq(_T_524, UInt<1>(0h0))
when _T_527 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_524, UInt<1>(0h1), "") : assert_69
node _T_528 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_529 = or(_T_528, io.in.d.bits.corrupt)
node _T_530 = asUInt(reset)
node _T_531 = eq(_T_530, UInt<1>(0h0))
when _T_531 :
node _T_532 = eq(_T_529, UInt<1>(0h0))
when _T_532 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_529, UInt<1>(0h1), "") : assert_70
node _T_533 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_534 = or(UInt<1>(0h1), _T_533)
node _T_535 = asUInt(reset)
node _T_536 = eq(_T_535, UInt<1>(0h0))
when _T_536 :
node _T_537 = eq(_T_534, UInt<1>(0h0))
when _T_537 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_534, UInt<1>(0h1), "") : assert_71
node _T_538 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_538 :
node _T_539 = asUInt(reset)
node _T_540 = eq(_T_539, UInt<1>(0h0))
when _T_540 :
node _T_541 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_541 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_542 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_543 = asUInt(reset)
node _T_544 = eq(_T_543, UInt<1>(0h0))
when _T_544 :
node _T_545 = eq(_T_542, UInt<1>(0h0))
when _T_545 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_542, UInt<1>(0h1), "") : assert_73
node _T_546 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_547 = asUInt(reset)
node _T_548 = eq(_T_547, UInt<1>(0h0))
when _T_548 :
node _T_549 = eq(_T_546, UInt<1>(0h0))
when _T_549 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_546, UInt<1>(0h1), "") : assert_74
node _T_550 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_551 = or(UInt<1>(0h1), _T_550)
node _T_552 = asUInt(reset)
node _T_553 = eq(_T_552, UInt<1>(0h0))
when _T_553 :
node _T_554 = eq(_T_551, UInt<1>(0h0))
when _T_554 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_551, UInt<1>(0h1), "") : assert_75
node _T_555 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_555 :
node _T_556 = asUInt(reset)
node _T_557 = eq(_T_556, UInt<1>(0h0))
when _T_557 :
node _T_558 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_558 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_559 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_560 = asUInt(reset)
node _T_561 = eq(_T_560, UInt<1>(0h0))
when _T_561 :
node _T_562 = eq(_T_559, UInt<1>(0h0))
when _T_562 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_559, UInt<1>(0h1), "") : assert_77
node _T_563 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_564 = or(_T_563, io.in.d.bits.corrupt)
node _T_565 = asUInt(reset)
node _T_566 = eq(_T_565, UInt<1>(0h0))
when _T_566 :
node _T_567 = eq(_T_564, UInt<1>(0h0))
when _T_567 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_564, UInt<1>(0h1), "") : assert_78
node _T_568 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_569 = or(UInt<1>(0h1), _T_568)
node _T_570 = asUInt(reset)
node _T_571 = eq(_T_570, UInt<1>(0h0))
when _T_571 :
node _T_572 = eq(_T_569, UInt<1>(0h0))
when _T_572 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_569, UInt<1>(0h1), "") : assert_79
node _T_573 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_573 :
node _T_574 = asUInt(reset)
node _T_575 = eq(_T_574, UInt<1>(0h0))
when _T_575 :
node _T_576 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_576 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_577 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_578 = asUInt(reset)
node _T_579 = eq(_T_578, UInt<1>(0h0))
when _T_579 :
node _T_580 = eq(_T_577, UInt<1>(0h0))
when _T_580 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_577, UInt<1>(0h1), "") : assert_81
node _T_581 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_582 = asUInt(reset)
node _T_583 = eq(_T_582, UInt<1>(0h0))
when _T_583 :
node _T_584 = eq(_T_581, UInt<1>(0h0))
when _T_584 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_581, UInt<1>(0h1), "") : assert_82
node _T_585 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_586 = or(UInt<1>(0h1), _T_585)
node _T_587 = asUInt(reset)
node _T_588 = eq(_T_587, UInt<1>(0h0))
when _T_588 :
node _T_589 = eq(_T_586, UInt<1>(0h0))
when _T_589 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_586, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<4>(0h0)
connect _WIRE.bits.size, UInt<3>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_590 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_591 = asUInt(reset)
node _T_592 = eq(_T_591, UInt<1>(0h0))
when _T_592 :
node _T_593 = eq(_T_590, UInt<1>(0h0))
when _T_593 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_590, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<4>(0h0)
connect _WIRE_2.bits.size, UInt<3>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_594 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_595 = asUInt(reset)
node _T_596 = eq(_T_595, UInt<1>(0h0))
when _T_596 :
node _T_597 = eq(_T_594, UInt<1>(0h0))
when _T_597 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_594, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_598 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_599 = asUInt(reset)
node _T_600 = eq(_T_599, UInt<1>(0h0))
when _T_600 :
node _T_601 = eq(_T_598, UInt<1>(0h0))
when _T_601 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_598, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_602 = eq(a_first, UInt<1>(0h0))
node _T_603 = and(io.in.a.valid, _T_602)
when _T_603 :
node _T_604 = eq(io.in.a.bits.opcode, opcode)
node _T_605 = asUInt(reset)
node _T_606 = eq(_T_605, UInt<1>(0h0))
when _T_606 :
node _T_607 = eq(_T_604, UInt<1>(0h0))
when _T_607 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_604, UInt<1>(0h1), "") : assert_87
node _T_608 = eq(io.in.a.bits.param, param)
node _T_609 = asUInt(reset)
node _T_610 = eq(_T_609, UInt<1>(0h0))
when _T_610 :
node _T_611 = eq(_T_608, UInt<1>(0h0))
when _T_611 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_608, UInt<1>(0h1), "") : assert_88
node _T_612 = eq(io.in.a.bits.size, size)
node _T_613 = asUInt(reset)
node _T_614 = eq(_T_613, UInt<1>(0h0))
when _T_614 :
node _T_615 = eq(_T_612, UInt<1>(0h0))
when _T_615 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_612, UInt<1>(0h1), "") : assert_89
node _T_616 = eq(io.in.a.bits.source, source)
node _T_617 = asUInt(reset)
node _T_618 = eq(_T_617, UInt<1>(0h0))
when _T_618 :
node _T_619 = eq(_T_616, UInt<1>(0h0))
when _T_619 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_616, UInt<1>(0h1), "") : assert_90
node _T_620 = eq(io.in.a.bits.address, address)
node _T_621 = asUInt(reset)
node _T_622 = eq(_T_621, UInt<1>(0h0))
when _T_622 :
node _T_623 = eq(_T_620, UInt<1>(0h0))
when _T_623 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_620, UInt<1>(0h1), "") : assert_91
node _T_624 = and(io.in.a.ready, io.in.a.valid)
node _T_625 = and(_T_624, a_first)
when _T_625 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_626 = eq(d_first, UInt<1>(0h0))
node _T_627 = and(io.in.d.valid, _T_626)
when _T_627 :
node _T_628 = eq(io.in.d.bits.opcode, opcode_1)
node _T_629 = asUInt(reset)
node _T_630 = eq(_T_629, UInt<1>(0h0))
when _T_630 :
node _T_631 = eq(_T_628, UInt<1>(0h0))
when _T_631 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_628, UInt<1>(0h1), "") : assert_92
node _T_632 = eq(io.in.d.bits.param, param_1)
node _T_633 = asUInt(reset)
node _T_634 = eq(_T_633, UInt<1>(0h0))
when _T_634 :
node _T_635 = eq(_T_632, UInt<1>(0h0))
when _T_635 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_632, UInt<1>(0h1), "") : assert_93
node _T_636 = eq(io.in.d.bits.size, size_1)
node _T_637 = asUInt(reset)
node _T_638 = eq(_T_637, UInt<1>(0h0))
when _T_638 :
node _T_639 = eq(_T_636, UInt<1>(0h0))
when _T_639 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_636, UInt<1>(0h1), "") : assert_94
node _T_640 = eq(io.in.d.bits.source, source_1)
node _T_641 = asUInt(reset)
node _T_642 = eq(_T_641, UInt<1>(0h0))
when _T_642 :
node _T_643 = eq(_T_640, UInt<1>(0h0))
when _T_643 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_640, UInt<1>(0h1), "") : assert_95
node _T_644 = eq(io.in.d.bits.sink, sink)
node _T_645 = asUInt(reset)
node _T_646 = eq(_T_645, UInt<1>(0h0))
when _T_646 :
node _T_647 = eq(_T_644, UInt<1>(0h0))
when _T_647 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_644, UInt<1>(0h1), "") : assert_96
node _T_648 = eq(io.in.d.bits.denied, denied)
node _T_649 = asUInt(reset)
node _T_650 = eq(_T_649, UInt<1>(0h0))
when _T_650 :
node _T_651 = eq(_T_648, UInt<1>(0h0))
when _T_651 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_648, UInt<1>(0h1), "") : assert_97
node _T_652 = and(io.in.d.ready, io.in.d.valid)
node _T_653 = and(_T_652, d_first)
when _T_653 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<10>, clock, reset, UInt<10>(0h0)
regreset inflight_opcodes : UInt<40>, clock, reset, UInt<40>(0h0)
regreset inflight_sizes : UInt<40>, clock, reset, UInt<40>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<10>
connect a_set, UInt<10>(0h0)
wire a_set_wo_ready : UInt<10>
connect a_set_wo_ready, UInt<10>(0h0)
wire a_opcodes_set : UInt<40>
connect a_opcodes_set, UInt<40>(0h0)
wire a_sizes_set : UInt<40>
connect a_sizes_set, UInt<40>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_654 = and(io.in.a.valid, a_first_1)
node _T_655 = and(_T_654, UInt<1>(0h1))
when _T_655 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_656 = and(io.in.a.ready, io.in.a.valid)
node _T_657 = and(_T_656, a_first_1)
node _T_658 = and(_T_657, UInt<1>(0h1))
when _T_658 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_659 = dshr(inflight, io.in.a.bits.source)
node _T_660 = bits(_T_659, 0, 0)
node _T_661 = eq(_T_660, UInt<1>(0h0))
node _T_662 = asUInt(reset)
node _T_663 = eq(_T_662, UInt<1>(0h0))
when _T_663 :
node _T_664 = eq(_T_661, UInt<1>(0h0))
when _T_664 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_661, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<10>
connect d_clr, UInt<10>(0h0)
wire d_clr_wo_ready : UInt<10>
connect d_clr_wo_ready, UInt<10>(0h0)
wire d_opcodes_clr : UInt<40>
connect d_opcodes_clr, UInt<40>(0h0)
wire d_sizes_clr : UInt<40>
connect d_sizes_clr, UInt<40>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_665 = and(io.in.d.valid, d_first_1)
node _T_666 = and(_T_665, UInt<1>(0h1))
node _T_667 = eq(d_release_ack, UInt<1>(0h0))
node _T_668 = and(_T_666, _T_667)
when _T_668 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_669 = and(io.in.d.ready, io.in.d.valid)
node _T_670 = and(_T_669, d_first_1)
node _T_671 = and(_T_670, UInt<1>(0h1))
node _T_672 = eq(d_release_ack, UInt<1>(0h0))
node _T_673 = and(_T_671, _T_672)
when _T_673 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_674 = and(io.in.d.valid, d_first_1)
node _T_675 = and(_T_674, UInt<1>(0h1))
node _T_676 = eq(d_release_ack, UInt<1>(0h0))
node _T_677 = and(_T_675, _T_676)
when _T_677 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_678 = dshr(inflight, io.in.d.bits.source)
node _T_679 = bits(_T_678, 0, 0)
node _T_680 = or(_T_679, same_cycle_resp)
node _T_681 = asUInt(reset)
node _T_682 = eq(_T_681, UInt<1>(0h0))
when _T_682 :
node _T_683 = eq(_T_680, UInt<1>(0h0))
when _T_683 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_680, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_684 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_685 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_686 = or(_T_684, _T_685)
node _T_687 = asUInt(reset)
node _T_688 = eq(_T_687, UInt<1>(0h0))
when _T_688 :
node _T_689 = eq(_T_686, UInt<1>(0h0))
when _T_689 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_686, UInt<1>(0h1), "") : assert_100
node _T_690 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_691 = asUInt(reset)
node _T_692 = eq(_T_691, UInt<1>(0h0))
when _T_692 :
node _T_693 = eq(_T_690, UInt<1>(0h0))
when _T_693 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_690, UInt<1>(0h1), "") : assert_101
else :
node _T_694 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_695 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_696 = or(_T_694, _T_695)
node _T_697 = asUInt(reset)
node _T_698 = eq(_T_697, UInt<1>(0h0))
when _T_698 :
node _T_699 = eq(_T_696, UInt<1>(0h0))
when _T_699 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_696, UInt<1>(0h1), "") : assert_102
node _T_700 = eq(io.in.d.bits.size, a_size_lookup)
node _T_701 = asUInt(reset)
node _T_702 = eq(_T_701, UInt<1>(0h0))
when _T_702 :
node _T_703 = eq(_T_700, UInt<1>(0h0))
when _T_703 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_700, UInt<1>(0h1), "") : assert_103
node _T_704 = and(io.in.d.valid, d_first_1)
node _T_705 = and(_T_704, a_first_1)
node _T_706 = and(_T_705, io.in.a.valid)
node _T_707 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_708 = and(_T_706, _T_707)
node _T_709 = eq(d_release_ack, UInt<1>(0h0))
node _T_710 = and(_T_708, _T_709)
when _T_710 :
node _T_711 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_712 = or(_T_711, io.in.a.ready)
node _T_713 = asUInt(reset)
node _T_714 = eq(_T_713, UInt<1>(0h0))
when _T_714 :
node _T_715 = eq(_T_712, UInt<1>(0h0))
when _T_715 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_712, UInt<1>(0h1), "") : assert_104
node _T_716 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_717 = orr(a_set_wo_ready)
node _T_718 = eq(_T_717, UInt<1>(0h0))
node _T_719 = or(_T_716, _T_718)
node _T_720 = asUInt(reset)
node _T_721 = eq(_T_720, UInt<1>(0h0))
when _T_721 :
node _T_722 = eq(_T_719, UInt<1>(0h0))
when _T_722 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_719, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_138
node _T_723 = orr(inflight)
node _T_724 = eq(_T_723, UInt<1>(0h0))
node _T_725 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_726 = or(_T_724, _T_725)
node _T_727 = lt(watchdog, plusarg_reader.out)
node _T_728 = or(_T_726, _T_727)
node _T_729 = asUInt(reset)
node _T_730 = eq(_T_729, UInt<1>(0h0))
when _T_730 :
node _T_731 = eq(_T_728, UInt<1>(0h0))
when _T_731 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_728, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_732 = and(io.in.a.ready, io.in.a.valid)
node _T_733 = and(io.in.d.ready, io.in.d.valid)
node _T_734 = or(_T_732, _T_733)
when _T_734 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<10>, clock, reset, UInt<10>(0h0)
regreset inflight_opcodes_1 : UInt<40>, clock, reset, UInt<40>(0h0)
regreset inflight_sizes_1 : UInt<40>, clock, reset, UInt<40>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<32>(0h0)
connect _c_first_WIRE.bits.source, UInt<4>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<10>
connect c_set, UInt<10>(0h0)
wire c_set_wo_ready : UInt<10>
connect c_set_wo_ready, UInt<10>(0h0)
wire c_opcodes_set : UInt<40>
connect c_opcodes_set, UInt<40>(0h0)
wire c_sizes_set : UInt<40>
connect c_sizes_set, UInt<40>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<4>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_735 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<4>(0h0)
connect _WIRE_8.bits.size, UInt<3>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_736 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_737 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_738 = and(_T_736, _T_737)
node _T_739 = and(_T_735, _T_738)
when _T_739 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<32>(0h0)
connect _WIRE_10.bits.source, UInt<4>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_740 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_741 = and(_T_740, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<32>(0h0)
connect _WIRE_12.bits.source, UInt<4>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_742 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_743 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_744 = and(_T_742, _T_743)
node _T_745 = and(_T_741, _T_744)
when _T_745 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<32>(0h0)
connect _WIRE_14.bits.source, UInt<4>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_746 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_747 = bits(_T_746, 0, 0)
node _T_748 = eq(_T_747, UInt<1>(0h0))
node _T_749 = asUInt(reset)
node _T_750 = eq(_T_749, UInt<1>(0h0))
when _T_750 :
node _T_751 = eq(_T_748, UInt<1>(0h0))
when _T_751 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_748, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<10>
connect d_clr_1, UInt<10>(0h0)
wire d_clr_wo_ready_1 : UInt<10>
connect d_clr_wo_ready_1, UInt<10>(0h0)
wire d_opcodes_clr_1 : UInt<40>
connect d_opcodes_clr_1, UInt<40>(0h0)
wire d_sizes_clr_1 : UInt<40>
connect d_sizes_clr_1, UInt<40>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_752 = and(io.in.d.valid, d_first_2)
node _T_753 = and(_T_752, UInt<1>(0h1))
node _T_754 = and(_T_753, d_release_ack_1)
when _T_754 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_755 = and(io.in.d.ready, io.in.d.valid)
node _T_756 = and(_T_755, d_first_2)
node _T_757 = and(_T_756, UInt<1>(0h1))
node _T_758 = and(_T_757, d_release_ack_1)
when _T_758 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_759 = and(io.in.d.valid, d_first_2)
node _T_760 = and(_T_759, UInt<1>(0h1))
node _T_761 = and(_T_760, d_release_ack_1)
when _T_761 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_762 = dshr(inflight_1, io.in.d.bits.source)
node _T_763 = bits(_T_762, 0, 0)
node _T_764 = or(_T_763, same_cycle_resp_1)
node _T_765 = asUInt(reset)
node _T_766 = eq(_T_765, UInt<1>(0h0))
when _T_766 :
node _T_767 = eq(_T_764, UInt<1>(0h0))
when _T_767 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_764, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<32>(0h0)
connect _WIRE_16.bits.source, UInt<4>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_768 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_769 = asUInt(reset)
node _T_770 = eq(_T_769, UInt<1>(0h0))
when _T_770 :
node _T_771 = eq(_T_768, UInt<1>(0h0))
when _T_771 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_768, UInt<1>(0h1), "") : assert_109
else :
node _T_772 = eq(io.in.d.bits.size, c_size_lookup)
node _T_773 = asUInt(reset)
node _T_774 = eq(_T_773, UInt<1>(0h0))
when _T_774 :
node _T_775 = eq(_T_772, UInt<1>(0h0))
when _T_775 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_772, UInt<1>(0h1), "") : assert_110
node _T_776 = and(io.in.d.valid, d_first_2)
node _T_777 = and(_T_776, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<32>(0h0)
connect _WIRE_18.bits.source, UInt<4>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_778 = and(_T_777, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<32>(0h0)
connect _WIRE_20.bits.source, UInt<4>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_779 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_780 = and(_T_778, _T_779)
node _T_781 = and(_T_780, d_release_ack_1)
node _T_782 = eq(c_probe_ack, UInt<1>(0h0))
node _T_783 = and(_T_781, _T_782)
when _T_783 :
node _T_784 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<32>(0h0)
connect _WIRE_22.bits.source, UInt<4>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_785 = or(_T_784, _WIRE_23.ready)
node _T_786 = asUInt(reset)
node _T_787 = eq(_T_786, UInt<1>(0h0))
when _T_787 :
node _T_788 = eq(_T_785, UInt<1>(0h0))
when _T_788 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_785, UInt<1>(0h1), "") : assert_111
node _T_789 = orr(c_set_wo_ready)
when _T_789 :
node _T_790 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_791 = asUInt(reset)
node _T_792 = eq(_T_791, UInt<1>(0h0))
when _T_792 :
node _T_793 = eq(_T_790, UInt<1>(0h0))
when _T_793 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_790, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_139
node _T_794 = orr(inflight_1)
node _T_795 = eq(_T_794, UInt<1>(0h0))
node _T_796 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_797 = or(_T_795, _T_796)
node _T_798 = lt(watchdog_1, plusarg_reader_1.out)
node _T_799 = or(_T_797, _T_798)
node _T_800 = asUInt(reset)
node _T_801 = eq(_T_800, UInt<1>(0h0))
when _T_801 :
node _T_802 = eq(_T_799, UInt<1>(0h0))
when _T_802 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_799, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<32>(0h0)
connect _WIRE_24.bits.source, UInt<4>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_803 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_804 = and(io.in.d.ready, io.in.d.valid)
node _T_805 = or(_T_803, _T_804)
when _T_805 :
connect watchdog_1, UInt<1>(0h0)
extmodule plusarg_reader_140 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_141 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLMonitor_56( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71]
wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [3:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [3:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [9:0] inflight; // @[Monitor.scala:614:27]
reg [39:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [39:0] inflight_sizes; // @[Monitor.scala:618:33]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire [15:0] _GEN_0 = {12'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35]
wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
wire [15:0] _GEN_3 = {12'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [9:0] inflight_1; // @[Monitor.scala:726:35]
reg [39:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_135 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_135( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module DivUnit_1 :
input clock : Clock
input reset : Reset
output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, rs1_data : UInt<64>, rs2_data : UInt<64>, rs3_data : UInt<64>, pred_data : UInt<1>, kill : UInt<1>}}, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, predicated : UInt<1>, data : UInt<64>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}, addr : UInt<40>, mxcpt : { valid : UInt<1>, bits : UInt<25>}, sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}}}, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, bypass : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<64>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}}[0]}
connect io.resp.valid, UInt<1>(0h0)
invalidate io.resp.bits.sfence.bits.hg
invalidate io.resp.bits.sfence.bits.hv
invalidate io.resp.bits.sfence.bits.asid
invalidate io.resp.bits.sfence.bits.addr
invalidate io.resp.bits.sfence.bits.rs2
invalidate io.resp.bits.sfence.bits.rs1
invalidate io.resp.bits.sfence.valid
invalidate io.resp.bits.mxcpt.bits
invalidate io.resp.bits.mxcpt.valid
invalidate io.resp.bits.addr
invalidate io.resp.bits.fflags.bits.flags
invalidate io.resp.bits.fflags.bits.uop.debug_tsrc
invalidate io.resp.bits.fflags.bits.uop.debug_fsrc
invalidate io.resp.bits.fflags.bits.uop.bp_xcpt_if
invalidate io.resp.bits.fflags.bits.uop.bp_debug_if
invalidate io.resp.bits.fflags.bits.uop.xcpt_ma_if
invalidate io.resp.bits.fflags.bits.uop.xcpt_ae_if
invalidate io.resp.bits.fflags.bits.uop.xcpt_pf_if
invalidate io.resp.bits.fflags.bits.uop.fp_single
invalidate io.resp.bits.fflags.bits.uop.fp_val
invalidate io.resp.bits.fflags.bits.uop.frs3_en
invalidate io.resp.bits.fflags.bits.uop.lrs2_rtype
invalidate io.resp.bits.fflags.bits.uop.lrs1_rtype
invalidate io.resp.bits.fflags.bits.uop.dst_rtype
invalidate io.resp.bits.fflags.bits.uop.ldst_val
invalidate io.resp.bits.fflags.bits.uop.lrs3
invalidate io.resp.bits.fflags.bits.uop.lrs2
invalidate io.resp.bits.fflags.bits.uop.lrs1
invalidate io.resp.bits.fflags.bits.uop.ldst
invalidate io.resp.bits.fflags.bits.uop.ldst_is_rs1
invalidate io.resp.bits.fflags.bits.uop.flush_on_commit
invalidate io.resp.bits.fflags.bits.uop.is_unique
invalidate io.resp.bits.fflags.bits.uop.is_sys_pc2epc
invalidate io.resp.bits.fflags.bits.uop.uses_stq
invalidate io.resp.bits.fflags.bits.uop.uses_ldq
invalidate io.resp.bits.fflags.bits.uop.is_amo
invalidate io.resp.bits.fflags.bits.uop.is_fencei
invalidate io.resp.bits.fflags.bits.uop.is_fence
invalidate io.resp.bits.fflags.bits.uop.mem_signed
invalidate io.resp.bits.fflags.bits.uop.mem_size
invalidate io.resp.bits.fflags.bits.uop.mem_cmd
invalidate io.resp.bits.fflags.bits.uop.bypassable
invalidate io.resp.bits.fflags.bits.uop.exc_cause
invalidate io.resp.bits.fflags.bits.uop.exception
invalidate io.resp.bits.fflags.bits.uop.stale_pdst
invalidate io.resp.bits.fflags.bits.uop.ppred_busy
invalidate io.resp.bits.fflags.bits.uop.prs3_busy
invalidate io.resp.bits.fflags.bits.uop.prs2_busy
invalidate io.resp.bits.fflags.bits.uop.prs1_busy
invalidate io.resp.bits.fflags.bits.uop.ppred
invalidate io.resp.bits.fflags.bits.uop.prs3
invalidate io.resp.bits.fflags.bits.uop.prs2
invalidate io.resp.bits.fflags.bits.uop.prs1
invalidate io.resp.bits.fflags.bits.uop.pdst
invalidate io.resp.bits.fflags.bits.uop.rxq_idx
invalidate io.resp.bits.fflags.bits.uop.stq_idx
invalidate io.resp.bits.fflags.bits.uop.ldq_idx
invalidate io.resp.bits.fflags.bits.uop.rob_idx
invalidate io.resp.bits.fflags.bits.uop.csr_addr
invalidate io.resp.bits.fflags.bits.uop.imm_packed
invalidate io.resp.bits.fflags.bits.uop.taken
invalidate io.resp.bits.fflags.bits.uop.pc_lob
invalidate io.resp.bits.fflags.bits.uop.edge_inst
invalidate io.resp.bits.fflags.bits.uop.ftq_idx
invalidate io.resp.bits.fflags.bits.uop.br_tag
invalidate io.resp.bits.fflags.bits.uop.br_mask
invalidate io.resp.bits.fflags.bits.uop.is_sfb
invalidate io.resp.bits.fflags.bits.uop.is_jal
invalidate io.resp.bits.fflags.bits.uop.is_jalr
invalidate io.resp.bits.fflags.bits.uop.is_br
invalidate io.resp.bits.fflags.bits.uop.iw_p2_poisoned
invalidate io.resp.bits.fflags.bits.uop.iw_p1_poisoned
invalidate io.resp.bits.fflags.bits.uop.iw_state
invalidate io.resp.bits.fflags.bits.uop.ctrl.is_std
invalidate io.resp.bits.fflags.bits.uop.ctrl.is_sta
invalidate io.resp.bits.fflags.bits.uop.ctrl.is_load
invalidate io.resp.bits.fflags.bits.uop.ctrl.csr_cmd
invalidate io.resp.bits.fflags.bits.uop.ctrl.fcn_dw
invalidate io.resp.bits.fflags.bits.uop.ctrl.op_fcn
invalidate io.resp.bits.fflags.bits.uop.ctrl.imm_sel
invalidate io.resp.bits.fflags.bits.uop.ctrl.op2_sel
invalidate io.resp.bits.fflags.bits.uop.ctrl.op1_sel
invalidate io.resp.bits.fflags.bits.uop.ctrl.br_type
invalidate io.resp.bits.fflags.bits.uop.fu_code
invalidate io.resp.bits.fflags.bits.uop.iq_type
invalidate io.resp.bits.fflags.bits.uop.debug_pc
invalidate io.resp.bits.fflags.bits.uop.is_rvc
invalidate io.resp.bits.fflags.bits.uop.debug_inst
invalidate io.resp.bits.fflags.bits.uop.inst
invalidate io.resp.bits.fflags.bits.uop.uopc
invalidate io.resp.bits.fflags.valid
invalidate io.resp.bits.data
invalidate io.resp.bits.predicated
invalidate io.resp.bits.uop.debug_tsrc
invalidate io.resp.bits.uop.debug_fsrc
invalidate io.resp.bits.uop.bp_xcpt_if
invalidate io.resp.bits.uop.bp_debug_if
invalidate io.resp.bits.uop.xcpt_ma_if
invalidate io.resp.bits.uop.xcpt_ae_if
invalidate io.resp.bits.uop.xcpt_pf_if
invalidate io.resp.bits.uop.fp_single
invalidate io.resp.bits.uop.fp_val
invalidate io.resp.bits.uop.frs3_en
invalidate io.resp.bits.uop.lrs2_rtype
invalidate io.resp.bits.uop.lrs1_rtype
invalidate io.resp.bits.uop.dst_rtype
invalidate io.resp.bits.uop.ldst_val
invalidate io.resp.bits.uop.lrs3
invalidate io.resp.bits.uop.lrs2
invalidate io.resp.bits.uop.lrs1
invalidate io.resp.bits.uop.ldst
invalidate io.resp.bits.uop.ldst_is_rs1
invalidate io.resp.bits.uop.flush_on_commit
invalidate io.resp.bits.uop.is_unique
invalidate io.resp.bits.uop.is_sys_pc2epc
invalidate io.resp.bits.uop.uses_stq
invalidate io.resp.bits.uop.uses_ldq
invalidate io.resp.bits.uop.is_amo
invalidate io.resp.bits.uop.is_fencei
invalidate io.resp.bits.uop.is_fence
invalidate io.resp.bits.uop.mem_signed
invalidate io.resp.bits.uop.mem_size
invalidate io.resp.bits.uop.mem_cmd
invalidate io.resp.bits.uop.bypassable
invalidate io.resp.bits.uop.exc_cause
invalidate io.resp.bits.uop.exception
invalidate io.resp.bits.uop.stale_pdst
invalidate io.resp.bits.uop.ppred_busy
invalidate io.resp.bits.uop.prs3_busy
invalidate io.resp.bits.uop.prs2_busy
invalidate io.resp.bits.uop.prs1_busy
invalidate io.resp.bits.uop.ppred
invalidate io.resp.bits.uop.prs3
invalidate io.resp.bits.uop.prs2
invalidate io.resp.bits.uop.prs1
invalidate io.resp.bits.uop.pdst
invalidate io.resp.bits.uop.rxq_idx
invalidate io.resp.bits.uop.stq_idx
invalidate io.resp.bits.uop.ldq_idx
invalidate io.resp.bits.uop.rob_idx
invalidate io.resp.bits.uop.csr_addr
invalidate io.resp.bits.uop.imm_packed
invalidate io.resp.bits.uop.taken
invalidate io.resp.bits.uop.pc_lob
invalidate io.resp.bits.uop.edge_inst
invalidate io.resp.bits.uop.ftq_idx
invalidate io.resp.bits.uop.br_tag
invalidate io.resp.bits.uop.br_mask
invalidate io.resp.bits.uop.is_sfb
invalidate io.resp.bits.uop.is_jal
invalidate io.resp.bits.uop.is_jalr
invalidate io.resp.bits.uop.is_br
invalidate io.resp.bits.uop.iw_p2_poisoned
invalidate io.resp.bits.uop.iw_p1_poisoned
invalidate io.resp.bits.uop.iw_state
invalidate io.resp.bits.uop.ctrl.is_std
invalidate io.resp.bits.uop.ctrl.is_sta
invalidate io.resp.bits.uop.ctrl.is_load
invalidate io.resp.bits.uop.ctrl.csr_cmd
invalidate io.resp.bits.uop.ctrl.fcn_dw
invalidate io.resp.bits.uop.ctrl.op_fcn
invalidate io.resp.bits.uop.ctrl.imm_sel
invalidate io.resp.bits.uop.ctrl.op2_sel
invalidate io.resp.bits.uop.ctrl.op1_sel
invalidate io.resp.bits.uop.ctrl.br_type
invalidate io.resp.bits.uop.fu_code
invalidate io.resp.bits.uop.iq_type
invalidate io.resp.bits.uop.debug_pc
invalidate io.resp.bits.uop.is_rvc
invalidate io.resp.bits.uop.debug_inst
invalidate io.resp.bits.uop.inst
invalidate io.resp.bits.uop.uopc
reg r_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock
wire do_kill : UInt<1>
connect do_kill, io.req.bits.kill
node _T = and(io.req.ready, io.req.valid)
when _T :
node _do_kill_T = and(io.brupdate.b1.mispredict_mask, io.req.bits.uop.br_mask)
node _do_kill_T_1 = neq(_do_kill_T, UInt<1>(0h0))
node _do_kill_T_2 = or(_do_kill_T_1, io.req.bits.kill)
connect do_kill, _do_kill_T_2
connect r_uop, io.req.bits.uop
node _r_uop_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _r_uop_br_mask_T_1 = and(io.req.bits.uop.br_mask, _r_uop_br_mask_T)
connect r_uop.br_mask, _r_uop_br_mask_T_1
else :
node _do_kill_T_3 = and(io.brupdate.b1.mispredict_mask, r_uop.br_mask)
node _do_kill_T_4 = neq(_do_kill_T_3, UInt<1>(0h0))
node _do_kill_T_5 = or(_do_kill_T_4, io.req.bits.kill)
connect do_kill, _do_kill_T_5
node _r_uop_br_mask_T_2 = not(io.brupdate.b1.resolve_mask)
node _r_uop_br_mask_T_3 = and(r_uop.br_mask, _r_uop_br_mask_T_2)
connect r_uop.br_mask, _r_uop_br_mask_T_3
connect io.resp.bits.uop, r_uop
inst div of MulDiv_3
connect div.clock, clock
connect div.reset, reset
node _div_io_req_valid_T = eq(do_kill, UInt<1>(0h0))
node _div_io_req_valid_T_1 = and(io.req.valid, _div_io_req_valid_T)
connect div.io.req.valid, _div_io_req_valid_T_1
connect div.io.req.bits.dw, io.req.bits.uop.ctrl.fcn_dw
connect div.io.req.bits.fn, io.req.bits.uop.ctrl.op_fcn
connect div.io.req.bits.in1, io.req.bits.rs1_data
connect div.io.req.bits.in2, io.req.bits.rs2_data
invalidate div.io.req.bits.tag
connect io.req.ready, div.io.req.ready
connect div.io.kill, do_kill
node _io_resp_valid_T = eq(do_kill, UInt<1>(0h0))
node _io_resp_valid_T_1 = and(div.io.resp.valid, _io_resp_valid_T)
connect io.resp.valid, _io_resp_valid_T_1
connect div.io.resp.ready, io.resp.ready
connect io.resp.bits.data, div.io.resp.bits.data | module DivUnit_1( // @[functional-unit.scala:676:7]
input clock, // @[functional-unit.scala:676:7]
input reset, // @[functional-unit.scala:676:7]
output io_req_ready, // @[functional-unit.scala:168:14]
input io_req_valid, // @[functional-unit.scala:168:14]
input [6:0] io_req_bits_uop_uopc, // @[functional-unit.scala:168:14]
input [31:0] io_req_bits_uop_inst, // @[functional-unit.scala:168:14]
input [31:0] io_req_bits_uop_debug_inst, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_rvc, // @[functional-unit.scala:168:14]
input [39:0] io_req_bits_uop_debug_pc, // @[functional-unit.scala:168:14]
input [2:0] io_req_bits_uop_iq_type, // @[functional-unit.scala:168:14]
input [9:0] io_req_bits_uop_fu_code, // @[functional-unit.scala:168:14]
input [3:0] io_req_bits_uop_ctrl_br_type, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14]
input [2:0] io_req_bits_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14]
input [2:0] io_req_bits_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14]
input [4:0] io_req_bits_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14]
input io_req_bits_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14]
input [2:0] io_req_bits_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14]
input io_req_bits_uop_ctrl_is_load, // @[functional-unit.scala:168:14]
input io_req_bits_uop_ctrl_is_sta, // @[functional-unit.scala:168:14]
input io_req_bits_uop_ctrl_is_std, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_iw_state, // @[functional-unit.scala:168:14]
input io_req_bits_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14]
input io_req_bits_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_br, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_jalr, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_jal, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_sfb, // @[functional-unit.scala:168:14]
input [15:0] io_req_bits_uop_br_mask, // @[functional-unit.scala:168:14]
input [3:0] io_req_bits_uop_br_tag, // @[functional-unit.scala:168:14]
input [4:0] io_req_bits_uop_ftq_idx, // @[functional-unit.scala:168:14]
input io_req_bits_uop_edge_inst, // @[functional-unit.scala:168:14]
input [5:0] io_req_bits_uop_pc_lob, // @[functional-unit.scala:168:14]
input io_req_bits_uop_taken, // @[functional-unit.scala:168:14]
input [19:0] io_req_bits_uop_imm_packed, // @[functional-unit.scala:168:14]
input [11:0] io_req_bits_uop_csr_addr, // @[functional-unit.scala:168:14]
input [6:0] io_req_bits_uop_rob_idx, // @[functional-unit.scala:168:14]
input [4:0] io_req_bits_uop_ldq_idx, // @[functional-unit.scala:168:14]
input [4:0] io_req_bits_uop_stq_idx, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_rxq_idx, // @[functional-unit.scala:168:14]
input [6:0] io_req_bits_uop_pdst, // @[functional-unit.scala:168:14]
input [6:0] io_req_bits_uop_prs1, // @[functional-unit.scala:168:14]
input [6:0] io_req_bits_uop_prs2, // @[functional-unit.scala:168:14]
input [6:0] io_req_bits_uop_prs3, // @[functional-unit.scala:168:14]
input [4:0] io_req_bits_uop_ppred, // @[functional-unit.scala:168:14]
input io_req_bits_uop_prs1_busy, // @[functional-unit.scala:168:14]
input io_req_bits_uop_prs2_busy, // @[functional-unit.scala:168:14]
input io_req_bits_uop_prs3_busy, // @[functional-unit.scala:168:14]
input io_req_bits_uop_ppred_busy, // @[functional-unit.scala:168:14]
input [6:0] io_req_bits_uop_stale_pdst, // @[functional-unit.scala:168:14]
input io_req_bits_uop_exception, // @[functional-unit.scala:168:14]
input [63:0] io_req_bits_uop_exc_cause, // @[functional-unit.scala:168:14]
input io_req_bits_uop_bypassable, // @[functional-unit.scala:168:14]
input [4:0] io_req_bits_uop_mem_cmd, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_mem_size, // @[functional-unit.scala:168:14]
input io_req_bits_uop_mem_signed, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_fence, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_fencei, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_amo, // @[functional-unit.scala:168:14]
input io_req_bits_uop_uses_ldq, // @[functional-unit.scala:168:14]
input io_req_bits_uop_uses_stq, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_unique, // @[functional-unit.scala:168:14]
input io_req_bits_uop_flush_on_commit, // @[functional-unit.scala:168:14]
input io_req_bits_uop_ldst_is_rs1, // @[functional-unit.scala:168:14]
input [5:0] io_req_bits_uop_ldst, // @[functional-unit.scala:168:14]
input [5:0] io_req_bits_uop_lrs1, // @[functional-unit.scala:168:14]
input [5:0] io_req_bits_uop_lrs2, // @[functional-unit.scala:168:14]
input [5:0] io_req_bits_uop_lrs3, // @[functional-unit.scala:168:14]
input io_req_bits_uop_ldst_val, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_dst_rtype, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_lrs1_rtype, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_lrs2_rtype, // @[functional-unit.scala:168:14]
input io_req_bits_uop_frs3_en, // @[functional-unit.scala:168:14]
input io_req_bits_uop_fp_val, // @[functional-unit.scala:168:14]
input io_req_bits_uop_fp_single, // @[functional-unit.scala:168:14]
input io_req_bits_uop_xcpt_pf_if, // @[functional-unit.scala:168:14]
input io_req_bits_uop_xcpt_ae_if, // @[functional-unit.scala:168:14]
input io_req_bits_uop_xcpt_ma_if, // @[functional-unit.scala:168:14]
input io_req_bits_uop_bp_debug_if, // @[functional-unit.scala:168:14]
input io_req_bits_uop_bp_xcpt_if, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_debug_fsrc, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_debug_tsrc, // @[functional-unit.scala:168:14]
input [63:0] io_req_bits_rs1_data, // @[functional-unit.scala:168:14]
input [63:0] io_req_bits_rs2_data, // @[functional-unit.scala:168:14]
input io_req_bits_kill, // @[functional-unit.scala:168:14]
input io_resp_ready, // @[functional-unit.scala:168:14]
output io_resp_valid, // @[functional-unit.scala:168:14]
output [6:0] io_resp_bits_uop_uopc, // @[functional-unit.scala:168:14]
output [31:0] io_resp_bits_uop_inst, // @[functional-unit.scala:168:14]
output [31:0] io_resp_bits_uop_debug_inst, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_rvc, // @[functional-unit.scala:168:14]
output [39:0] io_resp_bits_uop_debug_pc, // @[functional-unit.scala:168:14]
output [2:0] io_resp_bits_uop_iq_type, // @[functional-unit.scala:168:14]
output [9:0] io_resp_bits_uop_fu_code, // @[functional-unit.scala:168:14]
output [3:0] io_resp_bits_uop_ctrl_br_type, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14]
output [2:0] io_resp_bits_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14]
output [2:0] io_resp_bits_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14]
output [4:0] io_resp_bits_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14]
output [2:0] io_resp_bits_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_ctrl_is_load, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_ctrl_is_sta, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_ctrl_is_std, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_iw_state, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_br, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_jalr, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_jal, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_sfb, // @[functional-unit.scala:168:14]
output [15:0] io_resp_bits_uop_br_mask, // @[functional-unit.scala:168:14]
output [3:0] io_resp_bits_uop_br_tag, // @[functional-unit.scala:168:14]
output [4:0] io_resp_bits_uop_ftq_idx, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_edge_inst, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_uop_pc_lob, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_taken, // @[functional-unit.scala:168:14]
output [19:0] io_resp_bits_uop_imm_packed, // @[functional-unit.scala:168:14]
output [11:0] io_resp_bits_uop_csr_addr, // @[functional-unit.scala:168:14]
output [6:0] io_resp_bits_uop_rob_idx, // @[functional-unit.scala:168:14]
output [4:0] io_resp_bits_uop_ldq_idx, // @[functional-unit.scala:168:14]
output [4:0] io_resp_bits_uop_stq_idx, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_rxq_idx, // @[functional-unit.scala:168:14]
output [6:0] io_resp_bits_uop_pdst, // @[functional-unit.scala:168:14]
output [6:0] io_resp_bits_uop_prs1, // @[functional-unit.scala:168:14]
output [6:0] io_resp_bits_uop_prs2, // @[functional-unit.scala:168:14]
output [6:0] io_resp_bits_uop_prs3, // @[functional-unit.scala:168:14]
output [4:0] io_resp_bits_uop_ppred, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_prs1_busy, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_prs2_busy, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_prs3_busy, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_ppred_busy, // @[functional-unit.scala:168:14]
output [6:0] io_resp_bits_uop_stale_pdst, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_exception, // @[functional-unit.scala:168:14]
output [63:0] io_resp_bits_uop_exc_cause, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_bypassable, // @[functional-unit.scala:168:14]
output [4:0] io_resp_bits_uop_mem_cmd, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_mem_size, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_mem_signed, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_fence, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_fencei, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_amo, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_uses_ldq, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_uses_stq, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_unique, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_flush_on_commit, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_ldst_is_rs1, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_uop_ldst, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_uop_lrs1, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_uop_lrs2, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_uop_lrs3, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_ldst_val, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_dst_rtype, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_lrs1_rtype, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_lrs2_rtype, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_frs3_en, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_fp_val, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_fp_single, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_xcpt_pf_if, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_xcpt_ae_if, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_xcpt_ma_if, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_bp_debug_if, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_bp_xcpt_if, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_debug_fsrc, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_debug_tsrc, // @[functional-unit.scala:168:14]
output [63:0] io_resp_bits_data, // @[functional-unit.scala:168:14]
input [15:0] io_brupdate_b1_resolve_mask, // @[functional-unit.scala:168:14]
input [15:0] io_brupdate_b1_mispredict_mask, // @[functional-unit.scala:168:14]
input [6:0] io_brupdate_b2_uop_uopc, // @[functional-unit.scala:168:14]
input [31:0] io_brupdate_b2_uop_inst, // @[functional-unit.scala:168:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_rvc, // @[functional-unit.scala:168:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[functional-unit.scala:168:14]
input [2:0] io_brupdate_b2_uop_iq_type, // @[functional-unit.scala:168:14]
input [9:0] io_brupdate_b2_uop_fu_code, // @[functional-unit.scala:168:14]
input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14]
input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14]
input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14]
input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14]
input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_ctrl_is_load, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_ctrl_is_sta, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_ctrl_is_std, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_iw_state, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_br, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_jalr, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_jal, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_sfb, // @[functional-unit.scala:168:14]
input [15:0] io_brupdate_b2_uop_br_mask, // @[functional-unit.scala:168:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[functional-unit.scala:168:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_edge_inst, // @[functional-unit.scala:168:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_taken, // @[functional-unit.scala:168:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[functional-unit.scala:168:14]
input [11:0] io_brupdate_b2_uop_csr_addr, // @[functional-unit.scala:168:14]
input [6:0] io_brupdate_b2_uop_rob_idx, // @[functional-unit.scala:168:14]
input [4:0] io_brupdate_b2_uop_ldq_idx, // @[functional-unit.scala:168:14]
input [4:0] io_brupdate_b2_uop_stq_idx, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[functional-unit.scala:168:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[functional-unit.scala:168:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[functional-unit.scala:168:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[functional-unit.scala:168:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[functional-unit.scala:168:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_prs1_busy, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_prs2_busy, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_prs3_busy, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_ppred_busy, // @[functional-unit.scala:168:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_exception, // @[functional-unit.scala:168:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_bypassable, // @[functional-unit.scala:168:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_mem_signed, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_fence, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_fencei, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_amo, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_uses_ldq, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_uses_stq, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_unique, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_flush_on_commit, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[functional-unit.scala:168:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[functional-unit.scala:168:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[functional-unit.scala:168:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[functional-unit.scala:168:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_ldst_val, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_frs3_en, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_fp_val, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_fp_single, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_bp_debug_if, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[functional-unit.scala:168:14]
input io_brupdate_b2_valid, // @[functional-unit.scala:168:14]
input io_brupdate_b2_mispredict, // @[functional-unit.scala:168:14]
input io_brupdate_b2_taken, // @[functional-unit.scala:168:14]
input [2:0] io_brupdate_b2_cfi_type, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_pc_sel, // @[functional-unit.scala:168:14]
input [39:0] io_brupdate_b2_jalr_target, // @[functional-unit.scala:168:14]
input [20:0] io_brupdate_b2_target_offset // @[functional-unit.scala:168:14]
);
wire _div_io_resp_valid; // @[functional-unit.scala:682:19]
wire io_req_valid_0 = io_req_valid; // @[functional-unit.scala:676:7]
wire [6:0] io_req_bits_uop_uopc_0 = io_req_bits_uop_uopc; // @[functional-unit.scala:676:7]
wire [31:0] io_req_bits_uop_inst_0 = io_req_bits_uop_inst; // @[functional-unit.scala:676:7]
wire [31:0] io_req_bits_uop_debug_inst_0 = io_req_bits_uop_debug_inst; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_is_rvc_0 = io_req_bits_uop_is_rvc; // @[functional-unit.scala:676:7]
wire [39:0] io_req_bits_uop_debug_pc_0 = io_req_bits_uop_debug_pc; // @[functional-unit.scala:676:7]
wire [2:0] io_req_bits_uop_iq_type_0 = io_req_bits_uop_iq_type; // @[functional-unit.scala:676:7]
wire [9:0] io_req_bits_uop_fu_code_0 = io_req_bits_uop_fu_code; // @[functional-unit.scala:676:7]
wire [3:0] io_req_bits_uop_ctrl_br_type_0 = io_req_bits_uop_ctrl_br_type; // @[functional-unit.scala:676:7]
wire [1:0] io_req_bits_uop_ctrl_op1_sel_0 = io_req_bits_uop_ctrl_op1_sel; // @[functional-unit.scala:676:7]
wire [2:0] io_req_bits_uop_ctrl_op2_sel_0 = io_req_bits_uop_ctrl_op2_sel; // @[functional-unit.scala:676:7]
wire [2:0] io_req_bits_uop_ctrl_imm_sel_0 = io_req_bits_uop_ctrl_imm_sel; // @[functional-unit.scala:676:7]
wire [4:0] io_req_bits_uop_ctrl_op_fcn_0 = io_req_bits_uop_ctrl_op_fcn; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_ctrl_fcn_dw_0 = io_req_bits_uop_ctrl_fcn_dw; // @[functional-unit.scala:676:7]
wire [2:0] io_req_bits_uop_ctrl_csr_cmd_0 = io_req_bits_uop_ctrl_csr_cmd; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_ctrl_is_load_0 = io_req_bits_uop_ctrl_is_load; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_ctrl_is_sta_0 = io_req_bits_uop_ctrl_is_sta; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_ctrl_is_std_0 = io_req_bits_uop_ctrl_is_std; // @[functional-unit.scala:676:7]
wire [1:0] io_req_bits_uop_iw_state_0 = io_req_bits_uop_iw_state; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_iw_p1_poisoned_0 = io_req_bits_uop_iw_p1_poisoned; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_iw_p2_poisoned_0 = io_req_bits_uop_iw_p2_poisoned; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_is_br_0 = io_req_bits_uop_is_br; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_is_jalr_0 = io_req_bits_uop_is_jalr; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_is_jal_0 = io_req_bits_uop_is_jal; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_is_sfb_0 = io_req_bits_uop_is_sfb; // @[functional-unit.scala:676:7]
wire [15:0] io_req_bits_uop_br_mask_0 = io_req_bits_uop_br_mask; // @[functional-unit.scala:676:7]
wire [3:0] io_req_bits_uop_br_tag_0 = io_req_bits_uop_br_tag; // @[functional-unit.scala:676:7]
wire [4:0] io_req_bits_uop_ftq_idx_0 = io_req_bits_uop_ftq_idx; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_edge_inst_0 = io_req_bits_uop_edge_inst; // @[functional-unit.scala:676:7]
wire [5:0] io_req_bits_uop_pc_lob_0 = io_req_bits_uop_pc_lob; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_taken_0 = io_req_bits_uop_taken; // @[functional-unit.scala:676:7]
wire [19:0] io_req_bits_uop_imm_packed_0 = io_req_bits_uop_imm_packed; // @[functional-unit.scala:676:7]
wire [11:0] io_req_bits_uop_csr_addr_0 = io_req_bits_uop_csr_addr; // @[functional-unit.scala:676:7]
wire [6:0] io_req_bits_uop_rob_idx_0 = io_req_bits_uop_rob_idx; // @[functional-unit.scala:676:7]
wire [4:0] io_req_bits_uop_ldq_idx_0 = io_req_bits_uop_ldq_idx; // @[functional-unit.scala:676:7]
wire [4:0] io_req_bits_uop_stq_idx_0 = io_req_bits_uop_stq_idx; // @[functional-unit.scala:676:7]
wire [1:0] io_req_bits_uop_rxq_idx_0 = io_req_bits_uop_rxq_idx; // @[functional-unit.scala:676:7]
wire [6:0] io_req_bits_uop_pdst_0 = io_req_bits_uop_pdst; // @[functional-unit.scala:676:7]
wire [6:0] io_req_bits_uop_prs1_0 = io_req_bits_uop_prs1; // @[functional-unit.scala:676:7]
wire [6:0] io_req_bits_uop_prs2_0 = io_req_bits_uop_prs2; // @[functional-unit.scala:676:7]
wire [6:0] io_req_bits_uop_prs3_0 = io_req_bits_uop_prs3; // @[functional-unit.scala:676:7]
wire [4:0] io_req_bits_uop_ppred_0 = io_req_bits_uop_ppred; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_prs1_busy_0 = io_req_bits_uop_prs1_busy; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_prs2_busy_0 = io_req_bits_uop_prs2_busy; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_prs3_busy_0 = io_req_bits_uop_prs3_busy; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_ppred_busy_0 = io_req_bits_uop_ppred_busy; // @[functional-unit.scala:676:7]
wire [6:0] io_req_bits_uop_stale_pdst_0 = io_req_bits_uop_stale_pdst; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_exception_0 = io_req_bits_uop_exception; // @[functional-unit.scala:676:7]
wire [63:0] io_req_bits_uop_exc_cause_0 = io_req_bits_uop_exc_cause; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_bypassable_0 = io_req_bits_uop_bypassable; // @[functional-unit.scala:676:7]
wire [4:0] io_req_bits_uop_mem_cmd_0 = io_req_bits_uop_mem_cmd; // @[functional-unit.scala:676:7]
wire [1:0] io_req_bits_uop_mem_size_0 = io_req_bits_uop_mem_size; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_mem_signed_0 = io_req_bits_uop_mem_signed; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_is_fence_0 = io_req_bits_uop_is_fence; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_is_fencei_0 = io_req_bits_uop_is_fencei; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_is_amo_0 = io_req_bits_uop_is_amo; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_uses_ldq_0 = io_req_bits_uop_uses_ldq; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_uses_stq_0 = io_req_bits_uop_uses_stq; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_is_sys_pc2epc_0 = io_req_bits_uop_is_sys_pc2epc; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_is_unique_0 = io_req_bits_uop_is_unique; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_flush_on_commit_0 = io_req_bits_uop_flush_on_commit; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_ldst_is_rs1_0 = io_req_bits_uop_ldst_is_rs1; // @[functional-unit.scala:676:7]
wire [5:0] io_req_bits_uop_ldst_0 = io_req_bits_uop_ldst; // @[functional-unit.scala:676:7]
wire [5:0] io_req_bits_uop_lrs1_0 = io_req_bits_uop_lrs1; // @[functional-unit.scala:676:7]
wire [5:0] io_req_bits_uop_lrs2_0 = io_req_bits_uop_lrs2; // @[functional-unit.scala:676:7]
wire [5:0] io_req_bits_uop_lrs3_0 = io_req_bits_uop_lrs3; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_ldst_val_0 = io_req_bits_uop_ldst_val; // @[functional-unit.scala:676:7]
wire [1:0] io_req_bits_uop_dst_rtype_0 = io_req_bits_uop_dst_rtype; // @[functional-unit.scala:676:7]
wire [1:0] io_req_bits_uop_lrs1_rtype_0 = io_req_bits_uop_lrs1_rtype; // @[functional-unit.scala:676:7]
wire [1:0] io_req_bits_uop_lrs2_rtype_0 = io_req_bits_uop_lrs2_rtype; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_frs3_en_0 = io_req_bits_uop_frs3_en; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_fp_val_0 = io_req_bits_uop_fp_val; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_fp_single_0 = io_req_bits_uop_fp_single; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_xcpt_pf_if_0 = io_req_bits_uop_xcpt_pf_if; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_xcpt_ae_if_0 = io_req_bits_uop_xcpt_ae_if; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_xcpt_ma_if_0 = io_req_bits_uop_xcpt_ma_if; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_bp_debug_if_0 = io_req_bits_uop_bp_debug_if; // @[functional-unit.scala:676:7]
wire io_req_bits_uop_bp_xcpt_if_0 = io_req_bits_uop_bp_xcpt_if; // @[functional-unit.scala:676:7]
wire [1:0] io_req_bits_uop_debug_fsrc_0 = io_req_bits_uop_debug_fsrc; // @[functional-unit.scala:676:7]
wire [1:0] io_req_bits_uop_debug_tsrc_0 = io_req_bits_uop_debug_tsrc; // @[functional-unit.scala:676:7]
wire [63:0] io_req_bits_rs1_data_0 = io_req_bits_rs1_data; // @[functional-unit.scala:676:7]
wire [63:0] io_req_bits_rs2_data_0 = io_req_bits_rs2_data; // @[functional-unit.scala:676:7]
wire io_req_bits_kill_0 = io_req_bits_kill; // @[functional-unit.scala:676:7]
wire io_resp_ready_0 = io_resp_ready; // @[functional-unit.scala:676:7]
wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[functional-unit.scala:676:7]
wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[functional-unit.scala:676:7]
wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[functional-unit.scala:676:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[functional-unit.scala:676:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[functional-unit.scala:676:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[functional-unit.scala:676:7]
wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[functional-unit.scala:676:7]
wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[functional-unit.scala:676:7]
wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[functional-unit.scala:676:7]
wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[functional-unit.scala:676:7]
wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[functional-unit.scala:676:7]
wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[functional-unit.scala:676:7]
wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[functional-unit.scala:676:7]
wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[functional-unit.scala:676:7]
wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[functional-unit.scala:676:7]
wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[functional-unit.scala:676:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[functional-unit.scala:676:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[functional-unit.scala:676:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[functional-unit.scala:676:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[functional-unit.scala:676:7]
wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[functional-unit.scala:676:7]
wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[functional-unit.scala:676:7]
wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[functional-unit.scala:676:7]
wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[functional-unit.scala:676:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[functional-unit.scala:676:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[functional-unit.scala:676:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[functional-unit.scala:676:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[functional-unit.scala:676:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[functional-unit.scala:676:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[functional-unit.scala:676:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[functional-unit.scala:676:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[functional-unit.scala:676:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[functional-unit.scala:676:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[functional-unit.scala:676:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[functional-unit.scala:676:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[functional-unit.scala:676:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[functional-unit.scala:676:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[functional-unit.scala:676:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[functional-unit.scala:676:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[functional-unit.scala:676:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[functional-unit.scala:676:7]
wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[functional-unit.scala:676:7]
wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[functional-unit.scala:676:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[functional-unit.scala:676:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[functional-unit.scala:676:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[functional-unit.scala:676:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[functional-unit.scala:676:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[functional-unit.scala:676:7]
wire [38:0] io_resp_bits_sfence_bits_addr = 39'h0; // @[functional-unit.scala:676:7]
wire [24:0] io_resp_bits_mxcpt_bits = 25'h0; // @[functional-unit.scala:676:7]
wire [11:0] io_resp_bits_fflags_bits_uop_csr_addr = 12'h0; // @[functional-unit.scala:676:7]
wire [19:0] io_resp_bits_fflags_bits_uop_imm_packed = 20'h0; // @[functional-unit.scala:676:7]
wire [5:0] io_resp_bits_fflags_bits_uop_pc_lob = 6'h0; // @[functional-unit.scala:676:7]
wire [5:0] io_resp_bits_fflags_bits_uop_ldst = 6'h0; // @[functional-unit.scala:676:7]
wire [5:0] io_resp_bits_fflags_bits_uop_lrs1 = 6'h0; // @[functional-unit.scala:676:7]
wire [5:0] io_resp_bits_fflags_bits_uop_lrs2 = 6'h0; // @[functional-unit.scala:676:7]
wire [5:0] io_resp_bits_fflags_bits_uop_lrs3 = 6'h0; // @[functional-unit.scala:676:7]
wire [15:0] io_resp_bits_fflags_bits_uop_br_mask = 16'h0; // @[functional-unit.scala:676:7]
wire [4:0] io_resp_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[functional-unit.scala:676:7]
wire [4:0] io_resp_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[functional-unit.scala:676:7]
wire [4:0] io_resp_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[functional-unit.scala:676:7]
wire [4:0] io_resp_bits_fflags_bits_uop_stq_idx = 5'h0; // @[functional-unit.scala:676:7]
wire [4:0] io_resp_bits_fflags_bits_uop_ppred = 5'h0; // @[functional-unit.scala:676:7]
wire [4:0] io_resp_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[functional-unit.scala:676:7]
wire [4:0] io_resp_bits_fflags_bits_flags = 5'h0; // @[functional-unit.scala:676:7]
wire [1:0] io_resp_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[functional-unit.scala:676:7]
wire [1:0] io_resp_bits_fflags_bits_uop_iw_state = 2'h0; // @[functional-unit.scala:676:7]
wire [1:0] io_resp_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[functional-unit.scala:676:7]
wire [1:0] io_resp_bits_fflags_bits_uop_mem_size = 2'h0; // @[functional-unit.scala:676:7]
wire [1:0] io_resp_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[functional-unit.scala:676:7]
wire [1:0] io_resp_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[functional-unit.scala:676:7]
wire [1:0] io_resp_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[functional-unit.scala:676:7]
wire [1:0] io_resp_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[functional-unit.scala:676:7]
wire [1:0] io_resp_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[functional-unit.scala:676:7]
wire [3:0] io_resp_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[functional-unit.scala:676:7]
wire [3:0] io_resp_bits_fflags_bits_uop_br_tag = 4'h0; // @[functional-unit.scala:676:7]
wire [9:0] io_resp_bits_fflags_bits_uop_fu_code = 10'h0; // @[functional-unit.scala:676:7]
wire [2:0] io_resp_bits_fflags_bits_uop_iq_type = 3'h0; // @[functional-unit.scala:676:7]
wire [2:0] io_resp_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[functional-unit.scala:676:7]
wire [2:0] io_resp_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[functional-unit.scala:676:7]
wire [2:0] io_resp_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[functional-unit.scala:676:7]
wire [39:0] io_resp_bits_fflags_bits_uop_debug_pc = 40'h0; // @[functional-unit.scala:676:7]
wire [39:0] io_resp_bits_addr = 40'h0; // @[functional-unit.scala:676:7]
wire [31:0] io_resp_bits_fflags_bits_uop_inst = 32'h0; // @[functional-unit.scala:676:7]
wire [31:0] io_resp_bits_fflags_bits_uop_debug_inst = 32'h0; // @[functional-unit.scala:676:7]
wire [6:0] io_resp_bits_fflags_bits_uop_uopc = 7'h0; // @[functional-unit.scala:676:7]
wire [6:0] io_resp_bits_fflags_bits_uop_rob_idx = 7'h0; // @[functional-unit.scala:676:7]
wire [6:0] io_resp_bits_fflags_bits_uop_pdst = 7'h0; // @[functional-unit.scala:676:7]
wire [6:0] io_resp_bits_fflags_bits_uop_prs1 = 7'h0; // @[functional-unit.scala:676:7]
wire [6:0] io_resp_bits_fflags_bits_uop_prs2 = 7'h0; // @[functional-unit.scala:676:7]
wire [6:0] io_resp_bits_fflags_bits_uop_prs3 = 7'h0; // @[functional-unit.scala:676:7]
wire [6:0] io_resp_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[functional-unit.scala:676:7]
wire io_req_bits_pred_data = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_predicated = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_valid = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_is_rvc = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_is_br = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_is_jalr = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_is_jal = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_is_sfb = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_edge_inst = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_taken = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_exception = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_bypassable = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_mem_signed = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_is_fence = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_is_fencei = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_is_amo = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_uses_stq = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_is_unique = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_ldst_val = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_frs3_en = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_fp_val = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_fp_single = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_mxcpt_valid = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_sfence_valid = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_sfence_bits_rs1 = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_sfence_bits_rs2 = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_sfence_bits_asid = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_sfence_bits_hv = 1'h0; // @[functional-unit.scala:676:7]
wire io_resp_bits_sfence_bits_hg = 1'h0; // @[functional-unit.scala:676:7]
wire [63:0] io_req_bits_rs3_data = 64'h0; // @[functional-unit.scala:676:7]
wire [63:0] io_resp_bits_fflags_bits_uop_exc_cause = 64'h0; // @[functional-unit.scala:676:7]
wire _io_resp_valid_T_1; // @[functional-unit.scala:697:44]
wire io_req_ready_0; // @[functional-unit.scala:676:7]
wire [3:0] io_resp_bits_uop_ctrl_br_type_0; // @[functional-unit.scala:676:7]
wire [1:0] io_resp_bits_uop_ctrl_op1_sel_0; // @[functional-unit.scala:676:7]
wire [2:0] io_resp_bits_uop_ctrl_op2_sel_0; // @[functional-unit.scala:676:7]
wire [2:0] io_resp_bits_uop_ctrl_imm_sel_0; // @[functional-unit.scala:676:7]
wire [4:0] io_resp_bits_uop_ctrl_op_fcn_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_ctrl_fcn_dw_0; // @[functional-unit.scala:676:7]
wire [2:0] io_resp_bits_uop_ctrl_csr_cmd_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_ctrl_is_load_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_ctrl_is_sta_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_ctrl_is_std_0; // @[functional-unit.scala:676:7]
wire [6:0] io_resp_bits_uop_uopc_0; // @[functional-unit.scala:676:7]
wire [31:0] io_resp_bits_uop_inst_0; // @[functional-unit.scala:676:7]
wire [31:0] io_resp_bits_uop_debug_inst_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_is_rvc_0; // @[functional-unit.scala:676:7]
wire [39:0] io_resp_bits_uop_debug_pc_0; // @[functional-unit.scala:676:7]
wire [2:0] io_resp_bits_uop_iq_type_0; // @[functional-unit.scala:676:7]
wire [9:0] io_resp_bits_uop_fu_code_0; // @[functional-unit.scala:676:7]
wire [1:0] io_resp_bits_uop_iw_state_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_iw_p1_poisoned_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_iw_p2_poisoned_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_is_br_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_is_jalr_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_is_jal_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_is_sfb_0; // @[functional-unit.scala:676:7]
wire [15:0] io_resp_bits_uop_br_mask_0; // @[functional-unit.scala:676:7]
wire [3:0] io_resp_bits_uop_br_tag_0; // @[functional-unit.scala:676:7]
wire [4:0] io_resp_bits_uop_ftq_idx_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_edge_inst_0; // @[functional-unit.scala:676:7]
wire [5:0] io_resp_bits_uop_pc_lob_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_taken_0; // @[functional-unit.scala:676:7]
wire [19:0] io_resp_bits_uop_imm_packed_0; // @[functional-unit.scala:676:7]
wire [11:0] io_resp_bits_uop_csr_addr_0; // @[functional-unit.scala:676:7]
wire [6:0] io_resp_bits_uop_rob_idx_0; // @[functional-unit.scala:676:7]
wire [4:0] io_resp_bits_uop_ldq_idx_0; // @[functional-unit.scala:676:7]
wire [4:0] io_resp_bits_uop_stq_idx_0; // @[functional-unit.scala:676:7]
wire [1:0] io_resp_bits_uop_rxq_idx_0; // @[functional-unit.scala:676:7]
wire [6:0] io_resp_bits_uop_pdst_0; // @[functional-unit.scala:676:7]
wire [6:0] io_resp_bits_uop_prs1_0; // @[functional-unit.scala:676:7]
wire [6:0] io_resp_bits_uop_prs2_0; // @[functional-unit.scala:676:7]
wire [6:0] io_resp_bits_uop_prs3_0; // @[functional-unit.scala:676:7]
wire [4:0] io_resp_bits_uop_ppred_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_prs1_busy_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_prs2_busy_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_prs3_busy_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_ppred_busy_0; // @[functional-unit.scala:676:7]
wire [6:0] io_resp_bits_uop_stale_pdst_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_exception_0; // @[functional-unit.scala:676:7]
wire [63:0] io_resp_bits_uop_exc_cause_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_bypassable_0; // @[functional-unit.scala:676:7]
wire [4:0] io_resp_bits_uop_mem_cmd_0; // @[functional-unit.scala:676:7]
wire [1:0] io_resp_bits_uop_mem_size_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_mem_signed_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_is_fence_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_is_fencei_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_is_amo_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_uses_ldq_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_uses_stq_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_is_unique_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_flush_on_commit_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:676:7]
wire [5:0] io_resp_bits_uop_ldst_0; // @[functional-unit.scala:676:7]
wire [5:0] io_resp_bits_uop_lrs1_0; // @[functional-unit.scala:676:7]
wire [5:0] io_resp_bits_uop_lrs2_0; // @[functional-unit.scala:676:7]
wire [5:0] io_resp_bits_uop_lrs3_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_ldst_val_0; // @[functional-unit.scala:676:7]
wire [1:0] io_resp_bits_uop_dst_rtype_0; // @[functional-unit.scala:676:7]
wire [1:0] io_resp_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:676:7]
wire [1:0] io_resp_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_frs3_en_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_fp_val_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_fp_single_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_bp_debug_if_0; // @[functional-unit.scala:676:7]
wire io_resp_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:676:7]
wire [1:0] io_resp_bits_uop_debug_fsrc_0; // @[functional-unit.scala:676:7]
wire [1:0] io_resp_bits_uop_debug_tsrc_0; // @[functional-unit.scala:676:7]
wire [63:0] io_resp_bits_data_0; // @[functional-unit.scala:676:7]
wire io_resp_valid_0; // @[functional-unit.scala:676:7]
reg [6:0] r_uop_uopc; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_uopc_0 = r_uop_uopc; // @[functional-unit.scala:652:18, :676:7]
reg [31:0] r_uop_inst; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_inst_0 = r_uop_inst; // @[functional-unit.scala:652:18, :676:7]
reg [31:0] r_uop_debug_inst; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_debug_inst_0 = r_uop_debug_inst; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_is_rvc; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_is_rvc_0 = r_uop_is_rvc; // @[functional-unit.scala:652:18, :676:7]
reg [39:0] r_uop_debug_pc; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_debug_pc_0 = r_uop_debug_pc; // @[functional-unit.scala:652:18, :676:7]
reg [2:0] r_uop_iq_type; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_iq_type_0 = r_uop_iq_type; // @[functional-unit.scala:652:18, :676:7]
reg [9:0] r_uop_fu_code; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_fu_code_0 = r_uop_fu_code; // @[functional-unit.scala:652:18, :676:7]
reg [3:0] r_uop_ctrl_br_type; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_ctrl_br_type_0 = r_uop_ctrl_br_type; // @[functional-unit.scala:652:18, :676:7]
reg [1:0] r_uop_ctrl_op1_sel; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_ctrl_op1_sel_0 = r_uop_ctrl_op1_sel; // @[functional-unit.scala:652:18, :676:7]
reg [2:0] r_uop_ctrl_op2_sel; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_ctrl_op2_sel_0 = r_uop_ctrl_op2_sel; // @[functional-unit.scala:652:18, :676:7]
reg [2:0] r_uop_ctrl_imm_sel; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_ctrl_imm_sel_0 = r_uop_ctrl_imm_sel; // @[functional-unit.scala:652:18, :676:7]
reg [4:0] r_uop_ctrl_op_fcn; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_ctrl_op_fcn_0 = r_uop_ctrl_op_fcn; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_ctrl_fcn_dw; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_ctrl_fcn_dw_0 = r_uop_ctrl_fcn_dw; // @[functional-unit.scala:652:18, :676:7]
reg [2:0] r_uop_ctrl_csr_cmd; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_ctrl_csr_cmd_0 = r_uop_ctrl_csr_cmd; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_ctrl_is_load; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_ctrl_is_load_0 = r_uop_ctrl_is_load; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_ctrl_is_sta; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_ctrl_is_sta_0 = r_uop_ctrl_is_sta; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_ctrl_is_std; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_ctrl_is_std_0 = r_uop_ctrl_is_std; // @[functional-unit.scala:652:18, :676:7]
reg [1:0] r_uop_iw_state; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_iw_state_0 = r_uop_iw_state; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_iw_p1_poisoned; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_iw_p1_poisoned_0 = r_uop_iw_p1_poisoned; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_iw_p2_poisoned; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_iw_p2_poisoned_0 = r_uop_iw_p2_poisoned; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_is_br; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_is_br_0 = r_uop_is_br; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_is_jalr; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_is_jalr_0 = r_uop_is_jalr; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_is_jal; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_is_jal_0 = r_uop_is_jal; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_is_sfb; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_is_sfb_0 = r_uop_is_sfb; // @[functional-unit.scala:652:18, :676:7]
reg [15:0] r_uop_br_mask; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_br_mask_0 = r_uop_br_mask; // @[functional-unit.scala:652:18, :676:7]
reg [3:0] r_uop_br_tag; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_br_tag_0 = r_uop_br_tag; // @[functional-unit.scala:652:18, :676:7]
reg [4:0] r_uop_ftq_idx; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_ftq_idx_0 = r_uop_ftq_idx; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_edge_inst; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_edge_inst_0 = r_uop_edge_inst; // @[functional-unit.scala:652:18, :676:7]
reg [5:0] r_uop_pc_lob; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_pc_lob_0 = r_uop_pc_lob; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_taken; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_taken_0 = r_uop_taken; // @[functional-unit.scala:652:18, :676:7]
reg [19:0] r_uop_imm_packed; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_imm_packed_0 = r_uop_imm_packed; // @[functional-unit.scala:652:18, :676:7]
reg [11:0] r_uop_csr_addr; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_csr_addr_0 = r_uop_csr_addr; // @[functional-unit.scala:652:18, :676:7]
reg [6:0] r_uop_rob_idx; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_rob_idx_0 = r_uop_rob_idx; // @[functional-unit.scala:652:18, :676:7]
reg [4:0] r_uop_ldq_idx; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_ldq_idx_0 = r_uop_ldq_idx; // @[functional-unit.scala:652:18, :676:7]
reg [4:0] r_uop_stq_idx; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_stq_idx_0 = r_uop_stq_idx; // @[functional-unit.scala:652:18, :676:7]
reg [1:0] r_uop_rxq_idx; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_rxq_idx_0 = r_uop_rxq_idx; // @[functional-unit.scala:652:18, :676:7]
reg [6:0] r_uop_pdst; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_pdst_0 = r_uop_pdst; // @[functional-unit.scala:652:18, :676:7]
reg [6:0] r_uop_prs1; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_prs1_0 = r_uop_prs1; // @[functional-unit.scala:652:18, :676:7]
reg [6:0] r_uop_prs2; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_prs2_0 = r_uop_prs2; // @[functional-unit.scala:652:18, :676:7]
reg [6:0] r_uop_prs3; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_prs3_0 = r_uop_prs3; // @[functional-unit.scala:652:18, :676:7]
reg [4:0] r_uop_ppred; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_ppred_0 = r_uop_ppred; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_prs1_busy; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_prs1_busy_0 = r_uop_prs1_busy; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_prs2_busy; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_prs2_busy_0 = r_uop_prs2_busy; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_prs3_busy; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_prs3_busy_0 = r_uop_prs3_busy; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_ppred_busy; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_ppred_busy_0 = r_uop_ppred_busy; // @[functional-unit.scala:652:18, :676:7]
reg [6:0] r_uop_stale_pdst; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_stale_pdst_0 = r_uop_stale_pdst; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_exception; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_exception_0 = r_uop_exception; // @[functional-unit.scala:652:18, :676:7]
reg [63:0] r_uop_exc_cause; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_exc_cause_0 = r_uop_exc_cause; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_bypassable; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_bypassable_0 = r_uop_bypassable; // @[functional-unit.scala:652:18, :676:7]
reg [4:0] r_uop_mem_cmd; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_mem_cmd_0 = r_uop_mem_cmd; // @[functional-unit.scala:652:18, :676:7]
reg [1:0] r_uop_mem_size; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_mem_size_0 = r_uop_mem_size; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_mem_signed; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_mem_signed_0 = r_uop_mem_signed; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_is_fence; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_is_fence_0 = r_uop_is_fence; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_is_fencei; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_is_fencei_0 = r_uop_is_fencei; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_is_amo; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_is_amo_0 = r_uop_is_amo; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_uses_ldq; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_uses_ldq_0 = r_uop_uses_ldq; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_uses_stq; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_uses_stq_0 = r_uop_uses_stq; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_is_sys_pc2epc; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_is_sys_pc2epc_0 = r_uop_is_sys_pc2epc; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_is_unique; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_is_unique_0 = r_uop_is_unique; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_flush_on_commit; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_flush_on_commit_0 = r_uop_flush_on_commit; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_ldst_is_rs1; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_ldst_is_rs1_0 = r_uop_ldst_is_rs1; // @[functional-unit.scala:652:18, :676:7]
reg [5:0] r_uop_ldst; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_ldst_0 = r_uop_ldst; // @[functional-unit.scala:652:18, :676:7]
reg [5:0] r_uop_lrs1; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_lrs1_0 = r_uop_lrs1; // @[functional-unit.scala:652:18, :676:7]
reg [5:0] r_uop_lrs2; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_lrs2_0 = r_uop_lrs2; // @[functional-unit.scala:652:18, :676:7]
reg [5:0] r_uop_lrs3; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_lrs3_0 = r_uop_lrs3; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_ldst_val; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_ldst_val_0 = r_uop_ldst_val; // @[functional-unit.scala:652:18, :676:7]
reg [1:0] r_uop_dst_rtype; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_dst_rtype_0 = r_uop_dst_rtype; // @[functional-unit.scala:652:18, :676:7]
reg [1:0] r_uop_lrs1_rtype; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_lrs1_rtype_0 = r_uop_lrs1_rtype; // @[functional-unit.scala:652:18, :676:7]
reg [1:0] r_uop_lrs2_rtype; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_lrs2_rtype_0 = r_uop_lrs2_rtype; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_frs3_en; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_frs3_en_0 = r_uop_frs3_en; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_fp_val; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_fp_val_0 = r_uop_fp_val; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_fp_single; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_fp_single_0 = r_uop_fp_single; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_xcpt_pf_if; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_xcpt_pf_if_0 = r_uop_xcpt_pf_if; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_xcpt_ae_if; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_xcpt_ae_if_0 = r_uop_xcpt_ae_if; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_xcpt_ma_if; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_xcpt_ma_if_0 = r_uop_xcpt_ma_if; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_bp_debug_if; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_bp_debug_if_0 = r_uop_bp_debug_if; // @[functional-unit.scala:652:18, :676:7]
reg r_uop_bp_xcpt_if; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_bp_xcpt_if_0 = r_uop_bp_xcpt_if; // @[functional-unit.scala:652:18, :676:7]
reg [1:0] r_uop_debug_fsrc; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_debug_fsrc_0 = r_uop_debug_fsrc; // @[functional-unit.scala:652:18, :676:7]
reg [1:0] r_uop_debug_tsrc; // @[functional-unit.scala:652:18]
assign io_resp_bits_uop_debug_tsrc_0 = r_uop_debug_tsrc; // @[functional-unit.scala:652:18, :676:7]
wire do_kill; // @[functional-unit.scala:654:21]
wire _T = io_req_ready_0 & io_req_valid_0; // @[Decoupled.scala:51:35]
wire [15:0] _do_kill_T = io_brupdate_b1_mispredict_mask_0 & io_req_bits_uop_br_mask_0; // @[util.scala:118:51]
wire _do_kill_T_1 = |_do_kill_T; // @[util.scala:118:{51,59}]
wire _do_kill_T_2 = _do_kill_T_1 | io_req_bits_kill_0; // @[util.scala:118:59]
wire [15:0] _r_uop_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27]
wire [15:0] _r_uop_br_mask_T_1 = io_req_bits_uop_br_mask_0 & _r_uop_br_mask_T; // @[util.scala:85:{25,27}]
wire [15:0] _do_kill_T_3 = io_brupdate_b1_mispredict_mask_0 & r_uop_br_mask; // @[util.scala:118:51]
wire _do_kill_T_4 = |_do_kill_T_3; // @[util.scala:118:{51,59}]
wire _do_kill_T_5 = _do_kill_T_4 | io_req_bits_kill_0; // @[util.scala:118:59]
assign do_kill = _T ? _do_kill_T_2 : _do_kill_T_5; // @[Decoupled.scala:51:35]
wire [15:0] _r_uop_br_mask_T_2 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27]
wire [15:0] _r_uop_br_mask_T_3 = r_uop_br_mask & _r_uop_br_mask_T_2; // @[util.scala:85:{25,27}]
wire _div_io_req_valid_T = ~do_kill; // @[functional-unit.scala:654:21, :685:42]
wire _div_io_req_valid_T_1 = io_req_valid_0 & _div_io_req_valid_T; // @[functional-unit.scala:676:7, :685:{39,42}]
wire _io_resp_valid_T = ~do_kill; // @[functional-unit.scala:654:21, :685:42, :697:47]
assign _io_resp_valid_T_1 = _div_io_resp_valid & _io_resp_valid_T; // @[functional-unit.scala:682:19, :697:{44,47}]
assign io_resp_valid_0 = _io_resp_valid_T_1; // @[functional-unit.scala:676:7, :697:44]
always @(posedge clock) begin // @[functional-unit.scala:676:7]
if (_T) begin // @[Decoupled.scala:51:35]
r_uop_uopc <= io_req_bits_uop_uopc_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_inst <= io_req_bits_uop_inst_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_debug_inst <= io_req_bits_uop_debug_inst_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_is_rvc <= io_req_bits_uop_is_rvc_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_debug_pc <= io_req_bits_uop_debug_pc_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_iq_type <= io_req_bits_uop_iq_type_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_fu_code <= io_req_bits_uop_fu_code_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_ctrl_br_type <= io_req_bits_uop_ctrl_br_type_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_ctrl_op1_sel <= io_req_bits_uop_ctrl_op1_sel_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_ctrl_op2_sel <= io_req_bits_uop_ctrl_op2_sel_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_ctrl_imm_sel <= io_req_bits_uop_ctrl_imm_sel_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_ctrl_op_fcn <= io_req_bits_uop_ctrl_op_fcn_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_ctrl_fcn_dw <= io_req_bits_uop_ctrl_fcn_dw_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_ctrl_csr_cmd <= io_req_bits_uop_ctrl_csr_cmd_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_ctrl_is_load <= io_req_bits_uop_ctrl_is_load_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_ctrl_is_sta <= io_req_bits_uop_ctrl_is_sta_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_ctrl_is_std <= io_req_bits_uop_ctrl_is_std_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_iw_state <= io_req_bits_uop_iw_state_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_iw_p1_poisoned <= io_req_bits_uop_iw_p1_poisoned_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_iw_p2_poisoned <= io_req_bits_uop_iw_p2_poisoned_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_is_br <= io_req_bits_uop_is_br_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_is_jalr <= io_req_bits_uop_is_jalr_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_is_jal <= io_req_bits_uop_is_jal_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_is_sfb <= io_req_bits_uop_is_sfb_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_br_tag <= io_req_bits_uop_br_tag_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_ftq_idx <= io_req_bits_uop_ftq_idx_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_edge_inst <= io_req_bits_uop_edge_inst_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_pc_lob <= io_req_bits_uop_pc_lob_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_taken <= io_req_bits_uop_taken_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_imm_packed <= io_req_bits_uop_imm_packed_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_csr_addr <= io_req_bits_uop_csr_addr_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_rob_idx <= io_req_bits_uop_rob_idx_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_ldq_idx <= io_req_bits_uop_ldq_idx_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_stq_idx <= io_req_bits_uop_stq_idx_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_rxq_idx <= io_req_bits_uop_rxq_idx_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_pdst <= io_req_bits_uop_pdst_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_prs1 <= io_req_bits_uop_prs1_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_prs2 <= io_req_bits_uop_prs2_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_prs3 <= io_req_bits_uop_prs3_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_ppred <= io_req_bits_uop_ppred_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_prs1_busy <= io_req_bits_uop_prs1_busy_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_prs2_busy <= io_req_bits_uop_prs2_busy_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_prs3_busy <= io_req_bits_uop_prs3_busy_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_ppred_busy <= io_req_bits_uop_ppred_busy_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_stale_pdst <= io_req_bits_uop_stale_pdst_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_exception <= io_req_bits_uop_exception_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_exc_cause <= io_req_bits_uop_exc_cause_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_bypassable <= io_req_bits_uop_bypassable_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_mem_cmd <= io_req_bits_uop_mem_cmd_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_mem_size <= io_req_bits_uop_mem_size_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_mem_signed <= io_req_bits_uop_mem_signed_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_is_fence <= io_req_bits_uop_is_fence_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_is_fencei <= io_req_bits_uop_is_fencei_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_is_amo <= io_req_bits_uop_is_amo_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_uses_ldq <= io_req_bits_uop_uses_ldq_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_uses_stq <= io_req_bits_uop_uses_stq_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_is_sys_pc2epc <= io_req_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_is_unique <= io_req_bits_uop_is_unique_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_flush_on_commit <= io_req_bits_uop_flush_on_commit_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_ldst_is_rs1 <= io_req_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_ldst <= io_req_bits_uop_ldst_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_lrs1 <= io_req_bits_uop_lrs1_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_lrs2 <= io_req_bits_uop_lrs2_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_lrs3 <= io_req_bits_uop_lrs3_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_ldst_val <= io_req_bits_uop_ldst_val_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_dst_rtype <= io_req_bits_uop_dst_rtype_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_lrs1_rtype <= io_req_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_lrs2_rtype <= io_req_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_frs3_en <= io_req_bits_uop_frs3_en_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_fp_val <= io_req_bits_uop_fp_val_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_fp_single <= io_req_bits_uop_fp_single_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_xcpt_pf_if <= io_req_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_xcpt_ae_if <= io_req_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_xcpt_ma_if <= io_req_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_bp_debug_if <= io_req_bits_uop_bp_debug_if_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_bp_xcpt_if <= io_req_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_debug_fsrc <= io_req_bits_uop_debug_fsrc_0; // @[functional-unit.scala:652:18, :676:7]
r_uop_debug_tsrc <= io_req_bits_uop_debug_tsrc_0; // @[functional-unit.scala:652:18, :676:7]
end
r_uop_br_mask <= _T ? _r_uop_br_mask_T_1 : _r_uop_br_mask_T_3; // @[Decoupled.scala:51:35]
always @(posedge)
MulDiv_3 div ( // @[functional-unit.scala:682:19]
.clock (clock),
.reset (reset),
.io_req_ready (io_req_ready_0),
.io_req_valid (_div_io_req_valid_T_1), // @[functional-unit.scala:685:39]
.io_req_bits_fn (io_req_bits_uop_ctrl_op_fcn_0), // @[functional-unit.scala:676:7]
.io_req_bits_dw (io_req_bits_uop_ctrl_fcn_dw_0), // @[functional-unit.scala:676:7]
.io_req_bits_in1 (io_req_bits_rs1_data_0), // @[functional-unit.scala:676:7]
.io_req_bits_in2 (io_req_bits_rs2_data_0), // @[functional-unit.scala:676:7]
.io_kill (do_kill), // @[functional-unit.scala:654:21]
.io_resp_ready (io_resp_ready_0), // @[functional-unit.scala:676:7]
.io_resp_valid (_div_io_resp_valid),
.io_resp_bits_data (io_resp_bits_data_0)
); // @[functional-unit.scala:682:19]
assign io_req_ready = io_req_ready_0; // @[functional-unit.scala:676:7]
assign io_resp_valid = io_resp_valid_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_uopc = io_resp_bits_uop_uopc_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_inst = io_resp_bits_uop_inst_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_debug_inst = io_resp_bits_uop_debug_inst_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_is_rvc = io_resp_bits_uop_is_rvc_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_debug_pc = io_resp_bits_uop_debug_pc_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_iq_type = io_resp_bits_uop_iq_type_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_fu_code = io_resp_bits_uop_fu_code_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_ctrl_br_type = io_resp_bits_uop_ctrl_br_type_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_ctrl_op1_sel = io_resp_bits_uop_ctrl_op1_sel_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_ctrl_op2_sel = io_resp_bits_uop_ctrl_op2_sel_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_ctrl_imm_sel = io_resp_bits_uop_ctrl_imm_sel_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_ctrl_op_fcn = io_resp_bits_uop_ctrl_op_fcn_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_ctrl_fcn_dw = io_resp_bits_uop_ctrl_fcn_dw_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_ctrl_csr_cmd = io_resp_bits_uop_ctrl_csr_cmd_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_ctrl_is_load = io_resp_bits_uop_ctrl_is_load_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_ctrl_is_sta = io_resp_bits_uop_ctrl_is_sta_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_ctrl_is_std = io_resp_bits_uop_ctrl_is_std_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_iw_state = io_resp_bits_uop_iw_state_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_iw_p1_poisoned = io_resp_bits_uop_iw_p1_poisoned_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_iw_p2_poisoned = io_resp_bits_uop_iw_p2_poisoned_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_is_br = io_resp_bits_uop_is_br_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_is_jalr = io_resp_bits_uop_is_jalr_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_is_jal = io_resp_bits_uop_is_jal_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_is_sfb = io_resp_bits_uop_is_sfb_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_br_mask = io_resp_bits_uop_br_mask_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_br_tag = io_resp_bits_uop_br_tag_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_ftq_idx = io_resp_bits_uop_ftq_idx_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_edge_inst = io_resp_bits_uop_edge_inst_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_pc_lob = io_resp_bits_uop_pc_lob_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_taken = io_resp_bits_uop_taken_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_imm_packed = io_resp_bits_uop_imm_packed_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_csr_addr = io_resp_bits_uop_csr_addr_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_rob_idx = io_resp_bits_uop_rob_idx_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_ldq_idx = io_resp_bits_uop_ldq_idx_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_stq_idx = io_resp_bits_uop_stq_idx_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_rxq_idx = io_resp_bits_uop_rxq_idx_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_pdst = io_resp_bits_uop_pdst_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_prs1 = io_resp_bits_uop_prs1_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_prs2 = io_resp_bits_uop_prs2_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_prs3 = io_resp_bits_uop_prs3_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_ppred = io_resp_bits_uop_ppred_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_prs1_busy = io_resp_bits_uop_prs1_busy_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_prs2_busy = io_resp_bits_uop_prs2_busy_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_prs3_busy = io_resp_bits_uop_prs3_busy_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_ppred_busy = io_resp_bits_uop_ppred_busy_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_stale_pdst = io_resp_bits_uop_stale_pdst_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_exception = io_resp_bits_uop_exception_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_exc_cause = io_resp_bits_uop_exc_cause_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_bypassable = io_resp_bits_uop_bypassable_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_mem_cmd = io_resp_bits_uop_mem_cmd_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_mem_size = io_resp_bits_uop_mem_size_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_mem_signed = io_resp_bits_uop_mem_signed_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_is_fence = io_resp_bits_uop_is_fence_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_is_fencei = io_resp_bits_uop_is_fencei_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_is_amo = io_resp_bits_uop_is_amo_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_uses_ldq = io_resp_bits_uop_uses_ldq_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_uses_stq = io_resp_bits_uop_uses_stq_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_is_sys_pc2epc = io_resp_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_is_unique = io_resp_bits_uop_is_unique_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_flush_on_commit = io_resp_bits_uop_flush_on_commit_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_ldst_is_rs1 = io_resp_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_ldst = io_resp_bits_uop_ldst_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_lrs1 = io_resp_bits_uop_lrs1_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_lrs2 = io_resp_bits_uop_lrs2_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_lrs3 = io_resp_bits_uop_lrs3_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_ldst_val = io_resp_bits_uop_ldst_val_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_dst_rtype = io_resp_bits_uop_dst_rtype_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_lrs1_rtype = io_resp_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_lrs2_rtype = io_resp_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_frs3_en = io_resp_bits_uop_frs3_en_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_fp_val = io_resp_bits_uop_fp_val_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_fp_single = io_resp_bits_uop_fp_single_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_xcpt_pf_if = io_resp_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_xcpt_ae_if = io_resp_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_xcpt_ma_if = io_resp_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_bp_debug_if = io_resp_bits_uop_bp_debug_if_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_bp_xcpt_if = io_resp_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_debug_fsrc = io_resp_bits_uop_debug_fsrc_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_uop_debug_tsrc = io_resp_bits_uop_debug_tsrc_0; // @[functional-unit.scala:676:7]
assign io_resp_bits_data = io_resp_bits_data_0; // @[functional-unit.scala:676:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module ReRoCCBuffer_5 :
input clock : Clock
input reset : Reset
output auto : { flip in : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}}, out : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}}}
wire nodeIn : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}}
invalidate nodeIn.resp.bits.data
invalidate nodeIn.resp.bits.manager_id
invalidate nodeIn.resp.bits.client_id
invalidate nodeIn.resp.bits.opcode
invalidate nodeIn.resp.valid
invalidate nodeIn.resp.ready
invalidate nodeIn.req.bits.data
invalidate nodeIn.req.bits.manager_id
invalidate nodeIn.req.bits.client_id
invalidate nodeIn.req.bits.opcode
invalidate nodeIn.req.valid
invalidate nodeIn.req.ready
wire nodeOut : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}}
invalidate nodeOut.resp.bits.data
invalidate nodeOut.resp.bits.manager_id
invalidate nodeOut.resp.bits.client_id
invalidate nodeOut.resp.bits.opcode
invalidate nodeOut.resp.valid
invalidate nodeOut.resp.ready
invalidate nodeOut.req.bits.data
invalidate nodeOut.req.bits.manager_id
invalidate nodeOut.req.bits.client_id
invalidate nodeOut.req.bits.opcode
invalidate nodeOut.req.valid
invalidate nodeOut.req.ready
connect auto.out, nodeOut
connect nodeIn, auto.in
inst nodeOut_req_q of Queue2_ReRoCCMsgBundle_15
connect nodeOut_req_q.clock, clock
connect nodeOut_req_q.reset, reset
connect nodeOut_req_q.io.enq.valid, nodeIn.req.valid
connect nodeOut_req_q.io.enq.bits.data, nodeIn.req.bits.data
connect nodeOut_req_q.io.enq.bits.manager_id, nodeIn.req.bits.manager_id
connect nodeOut_req_q.io.enq.bits.client_id, nodeIn.req.bits.client_id
connect nodeOut_req_q.io.enq.bits.opcode, nodeIn.req.bits.opcode
connect nodeIn.req.ready, nodeOut_req_q.io.enq.ready
connect nodeOut.req.bits, nodeOut_req_q.io.deq.bits
connect nodeOut.req.valid, nodeOut_req_q.io.deq.valid
connect nodeOut_req_q.io.deq.ready, nodeOut.req.ready
inst nodeIn_resp_q of Queue2_ReRoCCMsgBundle_16
connect nodeIn_resp_q.clock, clock
connect nodeIn_resp_q.reset, reset
connect nodeIn_resp_q.io.enq.valid, nodeOut.resp.valid
connect nodeIn_resp_q.io.enq.bits.data, nodeOut.resp.bits.data
connect nodeIn_resp_q.io.enq.bits.manager_id, nodeOut.resp.bits.manager_id
connect nodeIn_resp_q.io.enq.bits.client_id, nodeOut.resp.bits.client_id
connect nodeIn_resp_q.io.enq.bits.opcode, nodeOut.resp.bits.opcode
connect nodeOut.resp.ready, nodeIn_resp_q.io.enq.ready
connect nodeIn.resp.bits, nodeIn_resp_q.io.deq.bits
connect nodeIn.resp.valid, nodeIn_resp_q.io.deq.valid
connect nodeIn_resp_q.io.deq.ready, nodeIn.resp.ready
extmodule plusarg_reader_169 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_170 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module ReRoCCBuffer_5( // @[Protocol.scala:124:25]
input clock, // @[Protocol.scala:124:25]
input reset, // @[Protocol.scala:124:25]
output auto_in_req_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_req_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_req_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_req_bits_client_id, // @[LazyModuleImp.scala:107:25]
input auto_in_req_bits_manager_id, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_req_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_resp_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_resp_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_resp_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_resp_bits_client_id, // @[LazyModuleImp.scala:107:25]
output auto_in_resp_bits_manager_id, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_resp_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_req_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_req_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_req_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_req_bits_client_id, // @[LazyModuleImp.scala:107:25]
output auto_out_req_bits_manager_id, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_req_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_resp_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_resp_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_resp_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_resp_bits_client_id, // @[LazyModuleImp.scala:107:25]
input auto_out_resp_bits_manager_id, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_resp_bits_data // @[LazyModuleImp.scala:107:25]
);
wire auto_in_req_valid_0 = auto_in_req_valid; // @[Protocol.scala:124:25]
wire [2:0] auto_in_req_bits_opcode_0 = auto_in_req_bits_opcode; // @[Protocol.scala:124:25]
wire [3:0] auto_in_req_bits_client_id_0 = auto_in_req_bits_client_id; // @[Protocol.scala:124:25]
wire auto_in_req_bits_manager_id_0 = auto_in_req_bits_manager_id; // @[Protocol.scala:124:25]
wire [63:0] auto_in_req_bits_data_0 = auto_in_req_bits_data; // @[Protocol.scala:124:25]
wire auto_in_resp_ready_0 = auto_in_resp_ready; // @[Protocol.scala:124:25]
wire auto_out_req_ready_0 = auto_out_req_ready; // @[Protocol.scala:124:25]
wire auto_out_resp_valid_0 = auto_out_resp_valid; // @[Protocol.scala:124:25]
wire [2:0] auto_out_resp_bits_opcode_0 = auto_out_resp_bits_opcode; // @[Protocol.scala:124:25]
wire [3:0] auto_out_resp_bits_client_id_0 = auto_out_resp_bits_client_id; // @[Protocol.scala:124:25]
wire auto_out_resp_bits_manager_id_0 = auto_out_resp_bits_manager_id; // @[Protocol.scala:124:25]
wire [63:0] auto_out_resp_bits_data_0 = auto_out_resp_bits_data; // @[Protocol.scala:124:25]
wire nodeIn_req_ready; // @[MixedNode.scala:551:17]
wire nodeIn_req_valid = auto_in_req_valid_0; // @[Protocol.scala:124:25]
wire [2:0] nodeIn_req_bits_opcode = auto_in_req_bits_opcode_0; // @[Protocol.scala:124:25]
wire [3:0] nodeIn_req_bits_client_id = auto_in_req_bits_client_id_0; // @[Protocol.scala:124:25]
wire nodeIn_req_bits_manager_id = auto_in_req_bits_manager_id_0; // @[Protocol.scala:124:25]
wire [63:0] nodeIn_req_bits_data = auto_in_req_bits_data_0; // @[Protocol.scala:124:25]
wire nodeIn_resp_ready = auto_in_resp_ready_0; // @[Protocol.scala:124:25]
wire nodeIn_resp_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_resp_bits_opcode; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_resp_bits_client_id; // @[MixedNode.scala:551:17]
wire nodeIn_resp_bits_manager_id; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_resp_bits_data; // @[MixedNode.scala:551:17]
wire nodeOut_req_ready = auto_out_req_ready_0; // @[Protocol.scala:124:25]
wire nodeOut_req_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_req_bits_opcode; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_req_bits_client_id; // @[MixedNode.scala:542:17]
wire nodeOut_req_bits_manager_id; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_req_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_resp_ready; // @[MixedNode.scala:542:17]
wire nodeOut_resp_valid = auto_out_resp_valid_0; // @[Protocol.scala:124:25]
wire [2:0] nodeOut_resp_bits_opcode = auto_out_resp_bits_opcode_0; // @[Protocol.scala:124:25]
wire [3:0] nodeOut_resp_bits_client_id = auto_out_resp_bits_client_id_0; // @[Protocol.scala:124:25]
wire nodeOut_resp_bits_manager_id = auto_out_resp_bits_manager_id_0; // @[Protocol.scala:124:25]
wire [63:0] nodeOut_resp_bits_data = auto_out_resp_bits_data_0; // @[Protocol.scala:124:25]
wire auto_in_req_ready_0; // @[Protocol.scala:124:25]
wire [2:0] auto_in_resp_bits_opcode_0; // @[Protocol.scala:124:25]
wire [3:0] auto_in_resp_bits_client_id_0; // @[Protocol.scala:124:25]
wire auto_in_resp_bits_manager_id_0; // @[Protocol.scala:124:25]
wire [63:0] auto_in_resp_bits_data_0; // @[Protocol.scala:124:25]
wire auto_in_resp_valid_0; // @[Protocol.scala:124:25]
wire [2:0] auto_out_req_bits_opcode_0; // @[Protocol.scala:124:25]
wire [3:0] auto_out_req_bits_client_id_0; // @[Protocol.scala:124:25]
wire auto_out_req_bits_manager_id_0; // @[Protocol.scala:124:25]
wire [63:0] auto_out_req_bits_data_0; // @[Protocol.scala:124:25]
wire auto_out_req_valid_0; // @[Protocol.scala:124:25]
wire auto_out_resp_ready_0; // @[Protocol.scala:124:25]
assign auto_in_req_ready_0 = nodeIn_req_ready; // @[Protocol.scala:124:25]
assign auto_in_resp_valid_0 = nodeIn_resp_valid; // @[Protocol.scala:124:25]
assign auto_in_resp_bits_opcode_0 = nodeIn_resp_bits_opcode; // @[Protocol.scala:124:25]
assign auto_in_resp_bits_client_id_0 = nodeIn_resp_bits_client_id; // @[Protocol.scala:124:25]
assign auto_in_resp_bits_manager_id_0 = nodeIn_resp_bits_manager_id; // @[Protocol.scala:124:25]
assign auto_in_resp_bits_data_0 = nodeIn_resp_bits_data; // @[Protocol.scala:124:25]
assign auto_out_req_valid_0 = nodeOut_req_valid; // @[Protocol.scala:124:25]
assign auto_out_req_bits_opcode_0 = nodeOut_req_bits_opcode; // @[Protocol.scala:124:25]
assign auto_out_req_bits_client_id_0 = nodeOut_req_bits_client_id; // @[Protocol.scala:124:25]
assign auto_out_req_bits_manager_id_0 = nodeOut_req_bits_manager_id; // @[Protocol.scala:124:25]
assign auto_out_req_bits_data_0 = nodeOut_req_bits_data; // @[Protocol.scala:124:25]
assign auto_out_resp_ready_0 = nodeOut_resp_ready; // @[Protocol.scala:124:25]
Queue2_ReRoCCMsgBundle_15 nodeOut_req_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_req_ready),
.io_enq_valid (nodeIn_req_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (nodeIn_req_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_client_id (nodeIn_req_bits_client_id), // @[MixedNode.scala:551:17]
.io_enq_bits_manager_id (nodeIn_req_bits_manager_id), // @[MixedNode.scala:551:17]
.io_enq_bits_data (nodeIn_req_bits_data), // @[MixedNode.scala:551:17]
.io_deq_ready (nodeOut_req_ready), // @[MixedNode.scala:542:17]
.io_deq_valid (nodeOut_req_valid),
.io_deq_bits_opcode (nodeOut_req_bits_opcode),
.io_deq_bits_client_id (nodeOut_req_bits_client_id),
.io_deq_bits_manager_id (nodeOut_req_bits_manager_id),
.io_deq_bits_data (nodeOut_req_bits_data)
); // @[Decoupled.scala:362:21]
Queue2_ReRoCCMsgBundle_16 nodeIn_resp_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeOut_resp_ready),
.io_enq_valid (nodeOut_resp_valid), // @[MixedNode.scala:542:17]
.io_enq_bits_opcode (nodeOut_resp_bits_opcode), // @[MixedNode.scala:542:17]
.io_enq_bits_client_id (nodeOut_resp_bits_client_id), // @[MixedNode.scala:542:17]
.io_enq_bits_manager_id (nodeOut_resp_bits_manager_id), // @[MixedNode.scala:542:17]
.io_enq_bits_data (nodeOut_resp_bits_data), // @[MixedNode.scala:542:17]
.io_deq_ready (nodeIn_resp_ready), // @[MixedNode.scala:551:17]
.io_deq_valid (nodeIn_resp_valid),
.io_deq_bits_opcode (nodeIn_resp_bits_opcode),
.io_deq_bits_client_id (nodeIn_resp_bits_client_id),
.io_deq_bits_manager_id (nodeIn_resp_bits_manager_id),
.io_deq_bits_data (nodeIn_resp_bits_data)
); // @[Decoupled.scala:362:21]
assign auto_in_req_ready = auto_in_req_ready_0; // @[Protocol.scala:124:25]
assign auto_in_resp_valid = auto_in_resp_valid_0; // @[Protocol.scala:124:25]
assign auto_in_resp_bits_opcode = auto_in_resp_bits_opcode_0; // @[Protocol.scala:124:25]
assign auto_in_resp_bits_client_id = auto_in_resp_bits_client_id_0; // @[Protocol.scala:124:25]
assign auto_in_resp_bits_manager_id = auto_in_resp_bits_manager_id_0; // @[Protocol.scala:124:25]
assign auto_in_resp_bits_data = auto_in_resp_bits_data_0; // @[Protocol.scala:124:25]
assign auto_out_req_valid = auto_out_req_valid_0; // @[Protocol.scala:124:25]
assign auto_out_req_bits_opcode = auto_out_req_bits_opcode_0; // @[Protocol.scala:124:25]
assign auto_out_req_bits_client_id = auto_out_req_bits_client_id_0; // @[Protocol.scala:124:25]
assign auto_out_req_bits_manager_id = auto_out_req_bits_manager_id_0; // @[Protocol.scala:124:25]
assign auto_out_req_bits_data = auto_out_req_bits_data_0; // @[Protocol.scala:124:25]
assign auto_out_resp_ready = auto_out_resp_ready_0; // @[Protocol.scala:124:25]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PE_389 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>}
inst mac_unit of MacUnit_133
connect mac_unit.clock, clock
connect mac_unit.reset, reset
reg c1 : SInt<8>, clock
reg c2 : SInt<8>, clock
connect io.out_a, io.in_a
connect io.out_control.dataflow, io.in_control.dataflow
connect io.out_control.propagate, io.in_control.propagate
connect io.out_control.shift, io.in_control.shift
connect io.out_id, io.in_id
connect io.out_last, io.in_last
connect io.out_valid, io.in_valid
connect mac_unit.io.in_a, io.in_a
reg last_s : UInt<1>, clock
when io.in_valid :
connect last_s, io.in_control.propagate
node flip = neq(last_s, io.in_control.propagate)
node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0))
connect io.bad_dataflow, UInt<1>(0h0)
node _T = eq(io.in_control.dataflow, UInt<1>(0h0))
node _T_1 = and(UInt<1>(0h0), _T)
node _T_2 = or(UInt<1>(0h0), _T_1)
when _T_2 :
node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_3 :
node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1)
node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2)
node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0)
node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4)
node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_1 = asUInt(c1)
node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1)
node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3)
node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1))
node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1)
node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6)
node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7)
node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0))
node _io_out_c_ones_digit_T = dshr(c1, shift_offset)
node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0)
node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit)
node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T)
node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0)
node _io_out_c_T = dshr(c1, shift_offset)
node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1)
node _io_out_c_T_3 = tail(_io_out_c_T_2, 1)
node _io_out_c_T_4 = asSInt(_io_out_c_T_3)
node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4)
node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7)
node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0)
node _io_out_c_T_10 = asSInt(_io_out_c_T_9)
connect io.out_c, _io_out_c_T_10
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE : SInt<8>
node _mac_unit_io_in_b_T = asUInt(io.in_b)
node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T)
connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE
connect mac_unit.io.in_c, c2
connect c2, mac_unit.io.out_d
node _c1_T = bits(io.in_d, 7, 0)
node _c1_T_1 = asSInt(_c1_T)
connect c1, _c1_T_1
else :
node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1)
node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7)
node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0)
node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9)
node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_10 = asUInt(c2)
node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1)
node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12)
node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1))
node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1)
node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15)
node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16)
node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0))
node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset)
node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0)
node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1)
node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2)
node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0)
node _io_out_c_T_11 = dshr(c2, shift_offset)
node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12)
node _io_out_c_T_14 = tail(_io_out_c_T_13, 1)
node _io_out_c_T_15 = asSInt(_io_out_c_T_14)
node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15)
node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18)
node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0)
node _io_out_c_T_21 = asSInt(_io_out_c_T_20)
connect io.out_c, _io_out_c_T_21
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE_1 : SInt<8>
node _mac_unit_io_in_b_T_2 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2)
connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1
connect mac_unit.io.in_c, c1
connect c1, mac_unit.io.out_d
node _c2_T = bits(io.in_d, 7, 0)
node _c2_T_1 = asSInt(_c2_T)
connect c2, _c2_T_1
else :
node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1))
node _T_5 = and(UInt<1>(0h0), _T_4)
node _T_6 = or(UInt<1>(0h1), _T_5)
when _T_6 :
node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_7 :
connect io.out_c, c1
wire _mac_unit_io_in_b_WIRE_2 : SInt<8>
node _mac_unit_io_in_b_T_4 = asUInt(c2)
node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4)
connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c1, io.in_d
else :
connect io.out_c, c2
wire _mac_unit_io_in_b_WIRE_3 : SInt<8>
node _mac_unit_io_in_b_T_6 = asUInt(c1)
node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6)
connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c2, io.in_d
else :
connect io.bad_dataflow, UInt<1>(0h1)
invalidate io.out_c
invalidate io.out_b
wire _mac_unit_io_in_b_WIRE_4 : SInt<8>
node _mac_unit_io_in_b_T_8 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8)
connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4
connect mac_unit.io.in_c, c2
node _T_8 = eq(io.in_valid, UInt<1>(0h0))
when _T_8 :
connect c1, c1
connect c2, c2
invalidate mac_unit.io.in_b
invalidate mac_unit.io.in_c | module PE_389( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid // @[PE.scala:35:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7]
wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60]
wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [7:0] c1; // @[PE.scala:70:15]
wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [7:0] c2; // @[PE.scala:71:15]
wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25]
wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}]
wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16]
wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8]
c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15]
if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8]
c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15]
if (io_in_valid_0) // @[PE.scala:31:7]
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
always @(posedge)
MacUnit_133 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_b_0), // @[PE.scala:31:7]
.io_out_d (io_out_b_0)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PE_5 :
input clock : Clock
input reset : Reset
output io : { flip inR : SInt<8>, flip inD : SInt<8>, outL : SInt<8>, outU : SInt<8>, flip dir : UInt<1>, flip en : UInt<1>}
node _reg_T = eq(io.dir, UInt<1>(0h0))
node _reg_T_1 = mux(_reg_T, io.inR, io.inD)
reg reg : SInt<8>, clock
when io.en :
connect reg, _reg_T_1
connect io.outU, reg
connect io.outL, reg | module PE_5( // @[Transposer.scala:100:9]
input clock, // @[Transposer.scala:100:9]
input reset, // @[Transposer.scala:100:9]
input [7:0] io_inR, // @[Transposer.scala:101:16]
input [7:0] io_inD, // @[Transposer.scala:101:16]
output [7:0] io_outL, // @[Transposer.scala:101:16]
output [7:0] io_outU, // @[Transposer.scala:101:16]
input io_dir, // @[Transposer.scala:101:16]
input io_en // @[Transposer.scala:101:16]
);
wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9]
wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9]
wire io_dir_0 = io_dir; // @[Transposer.scala:100:9]
wire io_en_0 = io_en; // @[Transposer.scala:100:9]
wire [7:0] io_outL_0; // @[Transposer.scala:100:9]
wire [7:0] io_outU_0; // @[Transposer.scala:100:9]
wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36]
wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}]
reg [7:0] reg_0; // @[Transposer.scala:110:24]
assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
always @(posedge clock) begin // @[Transposer.scala:100:9]
if (io_en_0) // @[Transposer.scala:100:9]
reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}]
always @(posedge)
assign io_outL = io_outL_0; // @[Transposer.scala:100:9]
assign io_outU = io_outU_0; // @[Transposer.scala:100:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_15 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<4>, q : UInt<4>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_154
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
node _output_T_2 = asAsyncReset(reset)
node _output_T_3 = bits(io.d, 1, 1)
inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_155
connect output_chain_1.clock, clock
connect output_chain_1.reset, _output_T_2
connect output_chain_1.io.d, _output_T_3
wire output_1 : UInt<1>
connect output_1, output_chain_1.io.q
node _output_T_4 = asAsyncReset(reset)
node _output_T_5 = bits(io.d, 2, 2)
inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_156
connect output_chain_2.clock, clock
connect output_chain_2.reset, _output_T_4
connect output_chain_2.io.d, _output_T_5
wire output_2 : UInt<1>
connect output_2, output_chain_2.io.q
node _output_T_6 = asAsyncReset(reset)
node _output_T_7 = bits(io.d, 3, 3)
inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_157
connect output_chain_3.clock, clock
connect output_chain_3.reset, _output_T_6
connect output_chain_3.io.d, _output_T_7
wire output_3 : UInt<1>
connect output_3, output_chain_3.io.q
node io_q_lo = cat(output_1, output_0)
node io_q_hi = cat(output_3, output_2)
node _io_q_T = cat(io_q_hi, io_q_lo)
connect io.q, _io_q_T | module AsyncResetSynchronizerShiftReg_w4_d3_i0_15( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input [3:0] io_d, // @[ShiftReg.scala:36:14]
output [3:0] io_q // @[ShiftReg.scala:36:14]
);
wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21]
wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14]
wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7]
wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_1; // @[ShiftReg.scala:48:24]
wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_2; // @[ShiftReg.scala:48:24]
wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_3; // @[ShiftReg.scala:48:24]
wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14]
wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14]
assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14]
assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_154 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_155 output_chain_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_2), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_3), // @[SynchronizerReg.scala:87:41]
.io_q (output_1)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_156 output_chain_2 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_4), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_5), // @[SynchronizerReg.scala:87:41]
.io_q (output_2)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_157 output_chain_3 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_6), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_7), // @[SynchronizerReg.scala:87:41]
.io_q (output_3)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_106 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h3d))
node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<6>(0h39))
node _source_ok_T_30 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _source_ok_T_33 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _source_ok_T_34 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _source_ok_T_35 = eq(io.in.a.bits.source, UInt<6>(0h31))
node _source_ok_T_36 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _source_ok_T_37 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _source_ok_T_38 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _source_ok_T_39 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _source_ok_T_40 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _source_ok_T_41 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _source_ok_T_42 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _source_ok_T_43 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _source_ok_T_44 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _source_ok_T_45 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _source_ok_T_46 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _source_ok_T_47 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _source_ok_T_48 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _source_ok_T_49 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE : UInt<1>[30]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_25
connect _source_ok_WIRE[6], _source_ok_T_26
connect _source_ok_WIRE[7], _source_ok_T_27
connect _source_ok_WIRE[8], _source_ok_T_28
connect _source_ok_WIRE[9], _source_ok_T_29
connect _source_ok_WIRE[10], _source_ok_T_30
connect _source_ok_WIRE[11], _source_ok_T_31
connect _source_ok_WIRE[12], _source_ok_T_32
connect _source_ok_WIRE[13], _source_ok_T_33
connect _source_ok_WIRE[14], _source_ok_T_34
connect _source_ok_WIRE[15], _source_ok_T_35
connect _source_ok_WIRE[16], _source_ok_T_36
connect _source_ok_WIRE[17], _source_ok_T_37
connect _source_ok_WIRE[18], _source_ok_T_38
connect _source_ok_WIRE[19], _source_ok_T_39
connect _source_ok_WIRE[20], _source_ok_T_40
connect _source_ok_WIRE[21], _source_ok_T_41
connect _source_ok_WIRE[22], _source_ok_T_42
connect _source_ok_WIRE[23], _source_ok_T_43
connect _source_ok_WIRE[24], _source_ok_T_44
connect _source_ok_WIRE[25], _source_ok_T_45
connect _source_ok_WIRE[26], _source_ok_T_46
connect _source_ok_WIRE[27], _source_ok_T_47
connect _source_ok_WIRE[28], _source_ok_T_48
connect _source_ok_WIRE[29], _source_ok_T_49
node _source_ok_T_50 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_51 = or(_source_ok_T_50, _source_ok_WIRE[2])
node _source_ok_T_52 = or(_source_ok_T_51, _source_ok_WIRE[3])
node _source_ok_T_53 = or(_source_ok_T_52, _source_ok_WIRE[4])
node _source_ok_T_54 = or(_source_ok_T_53, _source_ok_WIRE[5])
node _source_ok_T_55 = or(_source_ok_T_54, _source_ok_WIRE[6])
node _source_ok_T_56 = or(_source_ok_T_55, _source_ok_WIRE[7])
node _source_ok_T_57 = or(_source_ok_T_56, _source_ok_WIRE[8])
node _source_ok_T_58 = or(_source_ok_T_57, _source_ok_WIRE[9])
node _source_ok_T_59 = or(_source_ok_T_58, _source_ok_WIRE[10])
node _source_ok_T_60 = or(_source_ok_T_59, _source_ok_WIRE[11])
node _source_ok_T_61 = or(_source_ok_T_60, _source_ok_WIRE[12])
node _source_ok_T_62 = or(_source_ok_T_61, _source_ok_WIRE[13])
node _source_ok_T_63 = or(_source_ok_T_62, _source_ok_WIRE[14])
node _source_ok_T_64 = or(_source_ok_T_63, _source_ok_WIRE[15])
node _source_ok_T_65 = or(_source_ok_T_64, _source_ok_WIRE[16])
node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE[17])
node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE[18])
node _source_ok_T_68 = or(_source_ok_T_67, _source_ok_WIRE[19])
node _source_ok_T_69 = or(_source_ok_T_68, _source_ok_WIRE[20])
node _source_ok_T_70 = or(_source_ok_T_69, _source_ok_WIRE[21])
node _source_ok_T_71 = or(_source_ok_T_70, _source_ok_WIRE[22])
node _source_ok_T_72 = or(_source_ok_T_71, _source_ok_WIRE[23])
node _source_ok_T_73 = or(_source_ok_T_72, _source_ok_WIRE[24])
node _source_ok_T_74 = or(_source_ok_T_73, _source_ok_WIRE[25])
node _source_ok_T_75 = or(_source_ok_T_74, _source_ok_WIRE[26])
node _source_ok_T_76 = or(_source_ok_T_75, _source_ok_WIRE[27])
node _source_ok_T_77 = or(_source_ok_T_76, _source_ok_WIRE[28])
node source_ok = or(_source_ok_T_77, _source_ok_WIRE[29])
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<1>(0h0))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<1>(0h1))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<2>(0h2))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<2>(0h3))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_67 = cvt(_T_66)
node _T_68 = and(_T_67, asSInt(UInt<1>(0h0)))
node _T_69 = asSInt(_T_68)
node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0)))
node _T_71 = or(_T_65, _T_70)
node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h3d))
node _T_73 = eq(_T_72, UInt<1>(0h0))
node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_75 = cvt(_T_74)
node _T_76 = and(_T_75, asSInt(UInt<1>(0h0)))
node _T_77 = asSInt(_T_76)
node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0)))
node _T_79 = or(_T_73, _T_78)
node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_81 = eq(_T_80, UInt<1>(0h0))
node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_83 = cvt(_T_82)
node _T_84 = and(_T_83, asSInt(UInt<1>(0h0)))
node _T_85 = asSInt(_T_84)
node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0)))
node _T_87 = or(_T_81, _T_86)
node _T_88 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_89 = eq(_T_88, UInt<1>(0h0))
node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_91 = cvt(_T_90)
node _T_92 = and(_T_91, asSInt(UInt<1>(0h0)))
node _T_93 = asSInt(_T_92)
node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0)))
node _T_95 = or(_T_89, _T_94)
node _T_96 = eq(io.in.a.bits.source, UInt<6>(0h39))
node _T_97 = eq(_T_96, UInt<1>(0h0))
node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_99 = cvt(_T_98)
node _T_100 = and(_T_99, asSInt(UInt<1>(0h0)))
node _T_101 = asSInt(_T_100)
node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0)))
node _T_103 = or(_T_97, _T_102)
node _T_104 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_105 = eq(_T_104, UInt<1>(0h0))
node _T_106 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_107 = cvt(_T_106)
node _T_108 = and(_T_107, asSInt(UInt<1>(0h0)))
node _T_109 = asSInt(_T_108)
node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0)))
node _T_111 = or(_T_105, _T_110)
node _T_112 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_113 = eq(_T_112, UInt<1>(0h0))
node _T_114 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_115 = cvt(_T_114)
node _T_116 = and(_T_115, asSInt(UInt<1>(0h0)))
node _T_117 = asSInt(_T_116)
node _T_118 = eq(_T_117, asSInt(UInt<1>(0h0)))
node _T_119 = or(_T_113, _T_118)
node _T_120 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_121 = eq(_T_120, UInt<1>(0h0))
node _T_122 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_123 = cvt(_T_122)
node _T_124 = and(_T_123, asSInt(UInt<1>(0h0)))
node _T_125 = asSInt(_T_124)
node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0)))
node _T_127 = or(_T_121, _T_126)
node _T_128 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_129 = eq(_T_128, UInt<1>(0h0))
node _T_130 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_131 = cvt(_T_130)
node _T_132 = and(_T_131, asSInt(UInt<1>(0h0)))
node _T_133 = asSInt(_T_132)
node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0)))
node _T_135 = or(_T_129, _T_134)
node _T_136 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_137 = eq(_T_136, UInt<1>(0h0))
node _T_138 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_139 = cvt(_T_138)
node _T_140 = and(_T_139, asSInt(UInt<1>(0h0)))
node _T_141 = asSInt(_T_140)
node _T_142 = eq(_T_141, asSInt(UInt<1>(0h0)))
node _T_143 = or(_T_137, _T_142)
node _T_144 = eq(io.in.a.bits.source, UInt<6>(0h31))
node _T_145 = eq(_T_144, UInt<1>(0h0))
node _T_146 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_147 = cvt(_T_146)
node _T_148 = and(_T_147, asSInt(UInt<1>(0h0)))
node _T_149 = asSInt(_T_148)
node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0)))
node _T_151 = or(_T_145, _T_150)
node _T_152 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_153 = eq(_T_152, UInt<1>(0h0))
node _T_154 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_155 = cvt(_T_154)
node _T_156 = and(_T_155, asSInt(UInt<1>(0h0)))
node _T_157 = asSInt(_T_156)
node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0)))
node _T_159 = or(_T_153, _T_158)
node _T_160 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_161 = eq(_T_160, UInt<1>(0h0))
node _T_162 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_163 = cvt(_T_162)
node _T_164 = and(_T_163, asSInt(UInt<1>(0h0)))
node _T_165 = asSInt(_T_164)
node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0)))
node _T_167 = or(_T_161, _T_166)
node _T_168 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_169 = eq(_T_168, UInt<1>(0h0))
node _T_170 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_171 = cvt(_T_170)
node _T_172 = and(_T_171, asSInt(UInt<1>(0h0)))
node _T_173 = asSInt(_T_172)
node _T_174 = eq(_T_173, asSInt(UInt<1>(0h0)))
node _T_175 = or(_T_169, _T_174)
node _T_176 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_177 = eq(_T_176, UInt<1>(0h0))
node _T_178 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_179 = cvt(_T_178)
node _T_180 = and(_T_179, asSInt(UInt<1>(0h0)))
node _T_181 = asSInt(_T_180)
node _T_182 = eq(_T_181, asSInt(UInt<1>(0h0)))
node _T_183 = or(_T_177, _T_182)
node _T_184 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_185 = eq(_T_184, UInt<1>(0h0))
node _T_186 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_187 = cvt(_T_186)
node _T_188 = and(_T_187, asSInt(UInt<1>(0h0)))
node _T_189 = asSInt(_T_188)
node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0)))
node _T_191 = or(_T_185, _T_190)
node _T_192 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_193 = eq(_T_192, UInt<1>(0h0))
node _T_194 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_195 = cvt(_T_194)
node _T_196 = and(_T_195, asSInt(UInt<1>(0h0)))
node _T_197 = asSInt(_T_196)
node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0)))
node _T_199 = or(_T_193, _T_198)
node _T_200 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_201 = eq(_T_200, UInt<1>(0h0))
node _T_202 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_203 = cvt(_T_202)
node _T_204 = and(_T_203, asSInt(UInt<1>(0h0)))
node _T_205 = asSInt(_T_204)
node _T_206 = eq(_T_205, asSInt(UInt<1>(0h0)))
node _T_207 = or(_T_201, _T_206)
node _T_208 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_209 = eq(_T_208, UInt<1>(0h0))
node _T_210 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_211 = cvt(_T_210)
node _T_212 = and(_T_211, asSInt(UInt<1>(0h0)))
node _T_213 = asSInt(_T_212)
node _T_214 = eq(_T_213, asSInt(UInt<1>(0h0)))
node _T_215 = or(_T_209, _T_214)
node _T_216 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_217 = eq(_T_216, UInt<1>(0h0))
node _T_218 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_219 = cvt(_T_218)
node _T_220 = and(_T_219, asSInt(UInt<1>(0h0)))
node _T_221 = asSInt(_T_220)
node _T_222 = eq(_T_221, asSInt(UInt<1>(0h0)))
node _T_223 = or(_T_217, _T_222)
node _T_224 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_225 = eq(_T_224, UInt<1>(0h0))
node _T_226 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_227 = cvt(_T_226)
node _T_228 = and(_T_227, asSInt(UInt<1>(0h0)))
node _T_229 = asSInt(_T_228)
node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0)))
node _T_231 = or(_T_225, _T_230)
node _T_232 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_233 = eq(_T_232, UInt<1>(0h0))
node _T_234 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_235 = cvt(_T_234)
node _T_236 = and(_T_235, asSInt(UInt<1>(0h0)))
node _T_237 = asSInt(_T_236)
node _T_238 = eq(_T_237, asSInt(UInt<1>(0h0)))
node _T_239 = or(_T_233, _T_238)
node _T_240 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_241 = eq(_T_240, UInt<1>(0h0))
node _T_242 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_243 = cvt(_T_242)
node _T_244 = and(_T_243, asSInt(UInt<1>(0h0)))
node _T_245 = asSInt(_T_244)
node _T_246 = eq(_T_245, asSInt(UInt<1>(0h0)))
node _T_247 = or(_T_241, _T_246)
node _T_248 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_249 = eq(_T_248, UInt<1>(0h0))
node _T_250 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_251 = cvt(_T_250)
node _T_252 = and(_T_251, asSInt(UInt<1>(0h0)))
node _T_253 = asSInt(_T_252)
node _T_254 = eq(_T_253, asSInt(UInt<1>(0h0)))
node _T_255 = or(_T_249, _T_254)
node _T_256 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_257 = eq(_T_256, UInt<1>(0h0))
node _T_258 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_259 = cvt(_T_258)
node _T_260 = and(_T_259, asSInt(UInt<1>(0h0)))
node _T_261 = asSInt(_T_260)
node _T_262 = eq(_T_261, asSInt(UInt<1>(0h0)))
node _T_263 = or(_T_257, _T_262)
node _T_264 = and(_T_11, _T_24)
node _T_265 = and(_T_264, _T_37)
node _T_266 = and(_T_265, _T_50)
node _T_267 = and(_T_266, _T_63)
node _T_268 = and(_T_267, _T_71)
node _T_269 = and(_T_268, _T_79)
node _T_270 = and(_T_269, _T_87)
node _T_271 = and(_T_270, _T_95)
node _T_272 = and(_T_271, _T_103)
node _T_273 = and(_T_272, _T_111)
node _T_274 = and(_T_273, _T_119)
node _T_275 = and(_T_274, _T_127)
node _T_276 = and(_T_275, _T_135)
node _T_277 = and(_T_276, _T_143)
node _T_278 = and(_T_277, _T_151)
node _T_279 = and(_T_278, _T_159)
node _T_280 = and(_T_279, _T_167)
node _T_281 = and(_T_280, _T_175)
node _T_282 = and(_T_281, _T_183)
node _T_283 = and(_T_282, _T_191)
node _T_284 = and(_T_283, _T_199)
node _T_285 = and(_T_284, _T_207)
node _T_286 = and(_T_285, _T_215)
node _T_287 = and(_T_286, _T_223)
node _T_288 = and(_T_287, _T_231)
node _T_289 = and(_T_288, _T_239)
node _T_290 = and(_T_289, _T_247)
node _T_291 = and(_T_290, _T_255)
node _T_292 = and(_T_291, _T_263)
node _T_293 = asUInt(reset)
node _T_294 = eq(_T_293, UInt<1>(0h0))
when _T_294 :
node _T_295 = eq(_T_292, UInt<1>(0h0))
when _T_295 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_292, UInt<1>(0h1), "") : assert_1
node _T_296 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_296 :
node _T_297 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_298 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_299 = and(_T_297, _T_298)
node _T_300 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0)
node _T_301 = shr(io.in.a.bits.source, 2)
node _T_302 = eq(_T_301, UInt<1>(0h0))
node _T_303 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_304 = and(_T_302, _T_303)
node _T_305 = leq(uncommonBits_4, UInt<2>(0h3))
node _T_306 = and(_T_304, _T_305)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0)
node _T_307 = shr(io.in.a.bits.source, 2)
node _T_308 = eq(_T_307, UInt<1>(0h1))
node _T_309 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_310 = and(_T_308, _T_309)
node _T_311 = leq(uncommonBits_5, UInt<2>(0h3))
node _T_312 = and(_T_310, _T_311)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_313 = shr(io.in.a.bits.source, 2)
node _T_314 = eq(_T_313, UInt<2>(0h2))
node _T_315 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_316 = and(_T_314, _T_315)
node _T_317 = leq(uncommonBits_6, UInt<2>(0h3))
node _T_318 = and(_T_316, _T_317)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_319 = shr(io.in.a.bits.source, 2)
node _T_320 = eq(_T_319, UInt<2>(0h3))
node _T_321 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_322 = and(_T_320, _T_321)
node _T_323 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_324 = and(_T_322, _T_323)
node _T_325 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_326 = eq(io.in.a.bits.source, UInt<6>(0h3d))
node _T_327 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_328 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_329 = eq(io.in.a.bits.source, UInt<6>(0h39))
node _T_330 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_331 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_332 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_333 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_334 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_335 = eq(io.in.a.bits.source, UInt<6>(0h31))
node _T_336 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_337 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_338 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_339 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_340 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_341 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_342 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_343 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_344 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_345 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_346 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_347 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_348 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_349 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_350 = or(_T_300, _T_306)
node _T_351 = or(_T_350, _T_312)
node _T_352 = or(_T_351, _T_318)
node _T_353 = or(_T_352, _T_324)
node _T_354 = or(_T_353, _T_325)
node _T_355 = or(_T_354, _T_326)
node _T_356 = or(_T_355, _T_327)
node _T_357 = or(_T_356, _T_328)
node _T_358 = or(_T_357, _T_329)
node _T_359 = or(_T_358, _T_330)
node _T_360 = or(_T_359, _T_331)
node _T_361 = or(_T_360, _T_332)
node _T_362 = or(_T_361, _T_333)
node _T_363 = or(_T_362, _T_334)
node _T_364 = or(_T_363, _T_335)
node _T_365 = or(_T_364, _T_336)
node _T_366 = or(_T_365, _T_337)
node _T_367 = or(_T_366, _T_338)
node _T_368 = or(_T_367, _T_339)
node _T_369 = or(_T_368, _T_340)
node _T_370 = or(_T_369, _T_341)
node _T_371 = or(_T_370, _T_342)
node _T_372 = or(_T_371, _T_343)
node _T_373 = or(_T_372, _T_344)
node _T_374 = or(_T_373, _T_345)
node _T_375 = or(_T_374, _T_346)
node _T_376 = or(_T_375, _T_347)
node _T_377 = or(_T_376, _T_348)
node _T_378 = or(_T_377, _T_349)
node _T_379 = and(_T_299, _T_378)
node _T_380 = or(UInt<1>(0h0), _T_379)
node _T_381 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_382 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_383 = cvt(_T_382)
node _T_384 = and(_T_383, asSInt(UInt<13>(0h1000)))
node _T_385 = asSInt(_T_384)
node _T_386 = eq(_T_385, asSInt(UInt<1>(0h0)))
node _T_387 = and(_T_381, _T_386)
node _T_388 = or(UInt<1>(0h0), _T_387)
node _T_389 = and(_T_380, _T_388)
node _T_390 = asUInt(reset)
node _T_391 = eq(_T_390, UInt<1>(0h0))
when _T_391 :
node _T_392 = eq(_T_389, UInt<1>(0h0))
when _T_392 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_389, UInt<1>(0h1), "") : assert_2
node _T_393 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_394 = shr(io.in.a.bits.source, 2)
node _T_395 = eq(_T_394, UInt<1>(0h0))
node _T_396 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_397 = and(_T_395, _T_396)
node _T_398 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_399 = and(_T_397, _T_398)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_400 = shr(io.in.a.bits.source, 2)
node _T_401 = eq(_T_400, UInt<1>(0h1))
node _T_402 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_403 = and(_T_401, _T_402)
node _T_404 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_405 = and(_T_403, _T_404)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0)
node _T_406 = shr(io.in.a.bits.source, 2)
node _T_407 = eq(_T_406, UInt<2>(0h2))
node _T_408 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_409 = and(_T_407, _T_408)
node _T_410 = leq(uncommonBits_10, UInt<2>(0h3))
node _T_411 = and(_T_409, _T_410)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0)
node _T_412 = shr(io.in.a.bits.source, 2)
node _T_413 = eq(_T_412, UInt<2>(0h3))
node _T_414 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_415 = and(_T_413, _T_414)
node _T_416 = leq(uncommonBits_11, UInt<2>(0h3))
node _T_417 = and(_T_415, _T_416)
node _T_418 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_419 = eq(io.in.a.bits.source, UInt<6>(0h3d))
node _T_420 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_421 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_422 = eq(io.in.a.bits.source, UInt<6>(0h39))
node _T_423 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_424 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_425 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_426 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_427 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_428 = eq(io.in.a.bits.source, UInt<6>(0h31))
node _T_429 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_430 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_431 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_432 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_433 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_434 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_435 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_436 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_437 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_438 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_439 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_440 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_441 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_442 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _WIRE : UInt<1>[30]
connect _WIRE[0], _T_393
connect _WIRE[1], _T_399
connect _WIRE[2], _T_405
connect _WIRE[3], _T_411
connect _WIRE[4], _T_417
connect _WIRE[5], _T_418
connect _WIRE[6], _T_419
connect _WIRE[7], _T_420
connect _WIRE[8], _T_421
connect _WIRE[9], _T_422
connect _WIRE[10], _T_423
connect _WIRE[11], _T_424
connect _WIRE[12], _T_425
connect _WIRE[13], _T_426
connect _WIRE[14], _T_427
connect _WIRE[15], _T_428
connect _WIRE[16], _T_429
connect _WIRE[17], _T_430
connect _WIRE[18], _T_431
connect _WIRE[19], _T_432
connect _WIRE[20], _T_433
connect _WIRE[21], _T_434
connect _WIRE[22], _T_435
connect _WIRE[23], _T_436
connect _WIRE[24], _T_437
connect _WIRE[25], _T_438
connect _WIRE[26], _T_439
connect _WIRE[27], _T_440
connect _WIRE[28], _T_441
connect _WIRE[29], _T_442
node _T_443 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_444 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_445 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_446 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_447 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_448 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_449 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_450 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_451 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_452 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_453 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_454 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_455 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_456 = mux(_WIRE[5], _T_443, UInt<1>(0h0))
node _T_457 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_458 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_459 = mux(_WIRE[8], _T_444, UInt<1>(0h0))
node _T_460 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_461 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_462 = mux(_WIRE[11], _T_445, UInt<1>(0h0))
node _T_463 = mux(_WIRE[12], UInt<1>(0h0), UInt<1>(0h0))
node _T_464 = mux(_WIRE[13], UInt<1>(0h0), UInt<1>(0h0))
node _T_465 = mux(_WIRE[14], _T_446, UInt<1>(0h0))
node _T_466 = mux(_WIRE[15], UInt<1>(0h0), UInt<1>(0h0))
node _T_467 = mux(_WIRE[16], UInt<1>(0h0), UInt<1>(0h0))
node _T_468 = mux(_WIRE[17], _T_447, UInt<1>(0h0))
node _T_469 = mux(_WIRE[18], UInt<1>(0h0), UInt<1>(0h0))
node _T_470 = mux(_WIRE[19], UInt<1>(0h0), UInt<1>(0h0))
node _T_471 = mux(_WIRE[20], _T_448, UInt<1>(0h0))
node _T_472 = mux(_WIRE[21], UInt<1>(0h0), UInt<1>(0h0))
node _T_473 = mux(_WIRE[22], UInt<1>(0h0), UInt<1>(0h0))
node _T_474 = mux(_WIRE[23], _T_449, UInt<1>(0h0))
node _T_475 = mux(_WIRE[24], UInt<1>(0h0), UInt<1>(0h0))
node _T_476 = mux(_WIRE[25], UInt<1>(0h0), UInt<1>(0h0))
node _T_477 = mux(_WIRE[26], _T_450, UInt<1>(0h0))
node _T_478 = mux(_WIRE[27], UInt<1>(0h0), UInt<1>(0h0))
node _T_479 = mux(_WIRE[28], UInt<1>(0h0), UInt<1>(0h0))
node _T_480 = mux(_WIRE[29], UInt<1>(0h0), UInt<1>(0h0))
node _T_481 = or(_T_451, _T_452)
node _T_482 = or(_T_481, _T_453)
node _T_483 = or(_T_482, _T_454)
node _T_484 = or(_T_483, _T_455)
node _T_485 = or(_T_484, _T_456)
node _T_486 = or(_T_485, _T_457)
node _T_487 = or(_T_486, _T_458)
node _T_488 = or(_T_487, _T_459)
node _T_489 = or(_T_488, _T_460)
node _T_490 = or(_T_489, _T_461)
node _T_491 = or(_T_490, _T_462)
node _T_492 = or(_T_491, _T_463)
node _T_493 = or(_T_492, _T_464)
node _T_494 = or(_T_493, _T_465)
node _T_495 = or(_T_494, _T_466)
node _T_496 = or(_T_495, _T_467)
node _T_497 = or(_T_496, _T_468)
node _T_498 = or(_T_497, _T_469)
node _T_499 = or(_T_498, _T_470)
node _T_500 = or(_T_499, _T_471)
node _T_501 = or(_T_500, _T_472)
node _T_502 = or(_T_501, _T_473)
node _T_503 = or(_T_502, _T_474)
node _T_504 = or(_T_503, _T_475)
node _T_505 = or(_T_504, _T_476)
node _T_506 = or(_T_505, _T_477)
node _T_507 = or(_T_506, _T_478)
node _T_508 = or(_T_507, _T_479)
node _T_509 = or(_T_508, _T_480)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_509
node _T_510 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_511 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_512 = and(_T_510, _T_511)
node _T_513 = or(UInt<1>(0h0), _T_512)
node _T_514 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_515 = cvt(_T_514)
node _T_516 = and(_T_515, asSInt(UInt<13>(0h1000)))
node _T_517 = asSInt(_T_516)
node _T_518 = eq(_T_517, asSInt(UInt<1>(0h0)))
node _T_519 = and(_T_513, _T_518)
node _T_520 = or(UInt<1>(0h0), _T_519)
node _T_521 = and(_WIRE_1, _T_520)
node _T_522 = asUInt(reset)
node _T_523 = eq(_T_522, UInt<1>(0h0))
when _T_523 :
node _T_524 = eq(_T_521, UInt<1>(0h0))
when _T_524 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_521, UInt<1>(0h1), "") : assert_3
node _T_525 = asUInt(reset)
node _T_526 = eq(_T_525, UInt<1>(0h0))
when _T_526 :
node _T_527 = eq(source_ok, UInt<1>(0h0))
when _T_527 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_528 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_529 = asUInt(reset)
node _T_530 = eq(_T_529, UInt<1>(0h0))
when _T_530 :
node _T_531 = eq(_T_528, UInt<1>(0h0))
when _T_531 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_528, UInt<1>(0h1), "") : assert_5
node _T_532 = asUInt(reset)
node _T_533 = eq(_T_532, UInt<1>(0h0))
when _T_533 :
node _T_534 = eq(is_aligned, UInt<1>(0h0))
when _T_534 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_535 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_536 = asUInt(reset)
node _T_537 = eq(_T_536, UInt<1>(0h0))
when _T_537 :
node _T_538 = eq(_T_535, UInt<1>(0h0))
when _T_538 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_535, UInt<1>(0h1), "") : assert_7
node _T_539 = not(io.in.a.bits.mask)
node _T_540 = eq(_T_539, UInt<1>(0h0))
node _T_541 = asUInt(reset)
node _T_542 = eq(_T_541, UInt<1>(0h0))
when _T_542 :
node _T_543 = eq(_T_540, UInt<1>(0h0))
when _T_543 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_540, UInt<1>(0h1), "") : assert_8
node _T_544 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_545 = asUInt(reset)
node _T_546 = eq(_T_545, UInt<1>(0h0))
when _T_546 :
node _T_547 = eq(_T_544, UInt<1>(0h0))
when _T_547 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_544, UInt<1>(0h1), "") : assert_9
node _T_548 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_548 :
node _T_549 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_550 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_551 = and(_T_549, _T_550)
node _T_552 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_553 = shr(io.in.a.bits.source, 2)
node _T_554 = eq(_T_553, UInt<1>(0h0))
node _T_555 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_556 = and(_T_554, _T_555)
node _T_557 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_558 = and(_T_556, _T_557)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_559 = shr(io.in.a.bits.source, 2)
node _T_560 = eq(_T_559, UInt<1>(0h1))
node _T_561 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_562 = and(_T_560, _T_561)
node _T_563 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_564 = and(_T_562, _T_563)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_565 = shr(io.in.a.bits.source, 2)
node _T_566 = eq(_T_565, UInt<2>(0h2))
node _T_567 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_568 = and(_T_566, _T_567)
node _T_569 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_570 = and(_T_568, _T_569)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_571 = shr(io.in.a.bits.source, 2)
node _T_572 = eq(_T_571, UInt<2>(0h3))
node _T_573 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_574 = and(_T_572, _T_573)
node _T_575 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_576 = and(_T_574, _T_575)
node _T_577 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_578 = eq(io.in.a.bits.source, UInt<6>(0h3d))
node _T_579 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_580 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_581 = eq(io.in.a.bits.source, UInt<6>(0h39))
node _T_582 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_583 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_584 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_585 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_586 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_587 = eq(io.in.a.bits.source, UInt<6>(0h31))
node _T_588 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_589 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_590 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_591 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_592 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_593 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_594 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_595 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_596 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_597 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_598 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_599 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_600 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_601 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_602 = or(_T_552, _T_558)
node _T_603 = or(_T_602, _T_564)
node _T_604 = or(_T_603, _T_570)
node _T_605 = or(_T_604, _T_576)
node _T_606 = or(_T_605, _T_577)
node _T_607 = or(_T_606, _T_578)
node _T_608 = or(_T_607, _T_579)
node _T_609 = or(_T_608, _T_580)
node _T_610 = or(_T_609, _T_581)
node _T_611 = or(_T_610, _T_582)
node _T_612 = or(_T_611, _T_583)
node _T_613 = or(_T_612, _T_584)
node _T_614 = or(_T_613, _T_585)
node _T_615 = or(_T_614, _T_586)
node _T_616 = or(_T_615, _T_587)
node _T_617 = or(_T_616, _T_588)
node _T_618 = or(_T_617, _T_589)
node _T_619 = or(_T_618, _T_590)
node _T_620 = or(_T_619, _T_591)
node _T_621 = or(_T_620, _T_592)
node _T_622 = or(_T_621, _T_593)
node _T_623 = or(_T_622, _T_594)
node _T_624 = or(_T_623, _T_595)
node _T_625 = or(_T_624, _T_596)
node _T_626 = or(_T_625, _T_597)
node _T_627 = or(_T_626, _T_598)
node _T_628 = or(_T_627, _T_599)
node _T_629 = or(_T_628, _T_600)
node _T_630 = or(_T_629, _T_601)
node _T_631 = and(_T_551, _T_630)
node _T_632 = or(UInt<1>(0h0), _T_631)
node _T_633 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_634 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_635 = cvt(_T_634)
node _T_636 = and(_T_635, asSInt(UInt<13>(0h1000)))
node _T_637 = asSInt(_T_636)
node _T_638 = eq(_T_637, asSInt(UInt<1>(0h0)))
node _T_639 = and(_T_633, _T_638)
node _T_640 = or(UInt<1>(0h0), _T_639)
node _T_641 = and(_T_632, _T_640)
node _T_642 = asUInt(reset)
node _T_643 = eq(_T_642, UInt<1>(0h0))
when _T_643 :
node _T_644 = eq(_T_641, UInt<1>(0h0))
when _T_644 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_641, UInt<1>(0h1), "") : assert_10
node _T_645 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0)
node _T_646 = shr(io.in.a.bits.source, 2)
node _T_647 = eq(_T_646, UInt<1>(0h0))
node _T_648 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_649 = and(_T_647, _T_648)
node _T_650 = leq(uncommonBits_16, UInt<2>(0h3))
node _T_651 = and(_T_649, _T_650)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0)
node _T_652 = shr(io.in.a.bits.source, 2)
node _T_653 = eq(_T_652, UInt<1>(0h1))
node _T_654 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_655 = and(_T_653, _T_654)
node _T_656 = leq(uncommonBits_17, UInt<2>(0h3))
node _T_657 = and(_T_655, _T_656)
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0)
node _T_658 = shr(io.in.a.bits.source, 2)
node _T_659 = eq(_T_658, UInt<2>(0h2))
node _T_660 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_661 = and(_T_659, _T_660)
node _T_662 = leq(uncommonBits_18, UInt<2>(0h3))
node _T_663 = and(_T_661, _T_662)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0)
node _T_664 = shr(io.in.a.bits.source, 2)
node _T_665 = eq(_T_664, UInt<2>(0h3))
node _T_666 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_667 = and(_T_665, _T_666)
node _T_668 = leq(uncommonBits_19, UInt<2>(0h3))
node _T_669 = and(_T_667, _T_668)
node _T_670 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_671 = eq(io.in.a.bits.source, UInt<6>(0h3d))
node _T_672 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_673 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_674 = eq(io.in.a.bits.source, UInt<6>(0h39))
node _T_675 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_676 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_677 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_678 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_679 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_680 = eq(io.in.a.bits.source, UInt<6>(0h31))
node _T_681 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_682 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_683 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_684 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_685 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_686 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_687 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_688 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_689 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_690 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_691 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_692 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_693 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_694 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _WIRE_2 : UInt<1>[30]
connect _WIRE_2[0], _T_645
connect _WIRE_2[1], _T_651
connect _WIRE_2[2], _T_657
connect _WIRE_2[3], _T_663
connect _WIRE_2[4], _T_669
connect _WIRE_2[5], _T_670
connect _WIRE_2[6], _T_671
connect _WIRE_2[7], _T_672
connect _WIRE_2[8], _T_673
connect _WIRE_2[9], _T_674
connect _WIRE_2[10], _T_675
connect _WIRE_2[11], _T_676
connect _WIRE_2[12], _T_677
connect _WIRE_2[13], _T_678
connect _WIRE_2[14], _T_679
connect _WIRE_2[15], _T_680
connect _WIRE_2[16], _T_681
connect _WIRE_2[17], _T_682
connect _WIRE_2[18], _T_683
connect _WIRE_2[19], _T_684
connect _WIRE_2[20], _T_685
connect _WIRE_2[21], _T_686
connect _WIRE_2[22], _T_687
connect _WIRE_2[23], _T_688
connect _WIRE_2[24], _T_689
connect _WIRE_2[25], _T_690
connect _WIRE_2[26], _T_691
connect _WIRE_2[27], _T_692
connect _WIRE_2[28], _T_693
connect _WIRE_2[29], _T_694
node _T_695 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_696 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_697 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_698 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_699 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_700 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_701 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_702 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_703 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_704 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_705 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_706 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_707 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_708 = mux(_WIRE_2[5], _T_695, UInt<1>(0h0))
node _T_709 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_710 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_711 = mux(_WIRE_2[8], _T_696, UInt<1>(0h0))
node _T_712 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_713 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_714 = mux(_WIRE_2[11], _T_697, UInt<1>(0h0))
node _T_715 = mux(_WIRE_2[12], UInt<1>(0h0), UInt<1>(0h0))
node _T_716 = mux(_WIRE_2[13], UInt<1>(0h0), UInt<1>(0h0))
node _T_717 = mux(_WIRE_2[14], _T_698, UInt<1>(0h0))
node _T_718 = mux(_WIRE_2[15], UInt<1>(0h0), UInt<1>(0h0))
node _T_719 = mux(_WIRE_2[16], UInt<1>(0h0), UInt<1>(0h0))
node _T_720 = mux(_WIRE_2[17], _T_699, UInt<1>(0h0))
node _T_721 = mux(_WIRE_2[18], UInt<1>(0h0), UInt<1>(0h0))
node _T_722 = mux(_WIRE_2[19], UInt<1>(0h0), UInt<1>(0h0))
node _T_723 = mux(_WIRE_2[20], _T_700, UInt<1>(0h0))
node _T_724 = mux(_WIRE_2[21], UInt<1>(0h0), UInt<1>(0h0))
node _T_725 = mux(_WIRE_2[22], UInt<1>(0h0), UInt<1>(0h0))
node _T_726 = mux(_WIRE_2[23], _T_701, UInt<1>(0h0))
node _T_727 = mux(_WIRE_2[24], UInt<1>(0h0), UInt<1>(0h0))
node _T_728 = mux(_WIRE_2[25], UInt<1>(0h0), UInt<1>(0h0))
node _T_729 = mux(_WIRE_2[26], _T_702, UInt<1>(0h0))
node _T_730 = mux(_WIRE_2[27], UInt<1>(0h0), UInt<1>(0h0))
node _T_731 = mux(_WIRE_2[28], UInt<1>(0h0), UInt<1>(0h0))
node _T_732 = mux(_WIRE_2[29], UInt<1>(0h0), UInt<1>(0h0))
node _T_733 = or(_T_703, _T_704)
node _T_734 = or(_T_733, _T_705)
node _T_735 = or(_T_734, _T_706)
node _T_736 = or(_T_735, _T_707)
node _T_737 = or(_T_736, _T_708)
node _T_738 = or(_T_737, _T_709)
node _T_739 = or(_T_738, _T_710)
node _T_740 = or(_T_739, _T_711)
node _T_741 = or(_T_740, _T_712)
node _T_742 = or(_T_741, _T_713)
node _T_743 = or(_T_742, _T_714)
node _T_744 = or(_T_743, _T_715)
node _T_745 = or(_T_744, _T_716)
node _T_746 = or(_T_745, _T_717)
node _T_747 = or(_T_746, _T_718)
node _T_748 = or(_T_747, _T_719)
node _T_749 = or(_T_748, _T_720)
node _T_750 = or(_T_749, _T_721)
node _T_751 = or(_T_750, _T_722)
node _T_752 = or(_T_751, _T_723)
node _T_753 = or(_T_752, _T_724)
node _T_754 = or(_T_753, _T_725)
node _T_755 = or(_T_754, _T_726)
node _T_756 = or(_T_755, _T_727)
node _T_757 = or(_T_756, _T_728)
node _T_758 = or(_T_757, _T_729)
node _T_759 = or(_T_758, _T_730)
node _T_760 = or(_T_759, _T_731)
node _T_761 = or(_T_760, _T_732)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_761
node _T_762 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_763 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_764 = and(_T_762, _T_763)
node _T_765 = or(UInt<1>(0h0), _T_764)
node _T_766 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_767 = cvt(_T_766)
node _T_768 = and(_T_767, asSInt(UInt<13>(0h1000)))
node _T_769 = asSInt(_T_768)
node _T_770 = eq(_T_769, asSInt(UInt<1>(0h0)))
node _T_771 = and(_T_765, _T_770)
node _T_772 = or(UInt<1>(0h0), _T_771)
node _T_773 = and(_WIRE_3, _T_772)
node _T_774 = asUInt(reset)
node _T_775 = eq(_T_774, UInt<1>(0h0))
when _T_775 :
node _T_776 = eq(_T_773, UInt<1>(0h0))
when _T_776 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_773, UInt<1>(0h1), "") : assert_11
node _T_777 = asUInt(reset)
node _T_778 = eq(_T_777, UInt<1>(0h0))
when _T_778 :
node _T_779 = eq(source_ok, UInt<1>(0h0))
when _T_779 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_780 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_781 = asUInt(reset)
node _T_782 = eq(_T_781, UInt<1>(0h0))
when _T_782 :
node _T_783 = eq(_T_780, UInt<1>(0h0))
when _T_783 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_780, UInt<1>(0h1), "") : assert_13
node _T_784 = asUInt(reset)
node _T_785 = eq(_T_784, UInt<1>(0h0))
when _T_785 :
node _T_786 = eq(is_aligned, UInt<1>(0h0))
when _T_786 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_787 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_788 = asUInt(reset)
node _T_789 = eq(_T_788, UInt<1>(0h0))
when _T_789 :
node _T_790 = eq(_T_787, UInt<1>(0h0))
when _T_790 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_787, UInt<1>(0h1), "") : assert_15
node _T_791 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_792 = asUInt(reset)
node _T_793 = eq(_T_792, UInt<1>(0h0))
when _T_793 :
node _T_794 = eq(_T_791, UInt<1>(0h0))
when _T_794 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_791, UInt<1>(0h1), "") : assert_16
node _T_795 = not(io.in.a.bits.mask)
node _T_796 = eq(_T_795, UInt<1>(0h0))
node _T_797 = asUInt(reset)
node _T_798 = eq(_T_797, UInt<1>(0h0))
when _T_798 :
node _T_799 = eq(_T_796, UInt<1>(0h0))
when _T_799 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_796, UInt<1>(0h1), "") : assert_17
node _T_800 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_801 = asUInt(reset)
node _T_802 = eq(_T_801, UInt<1>(0h0))
when _T_802 :
node _T_803 = eq(_T_800, UInt<1>(0h0))
when _T_803 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_800, UInt<1>(0h1), "") : assert_18
node _T_804 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_804 :
node _T_805 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_806 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_807 = and(_T_805, _T_806)
node _T_808 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_809 = shr(io.in.a.bits.source, 2)
node _T_810 = eq(_T_809, UInt<1>(0h0))
node _T_811 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_812 = and(_T_810, _T_811)
node _T_813 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_814 = and(_T_812, _T_813)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_815 = shr(io.in.a.bits.source, 2)
node _T_816 = eq(_T_815, UInt<1>(0h1))
node _T_817 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_818 = and(_T_816, _T_817)
node _T_819 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_820 = and(_T_818, _T_819)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0)
node _T_821 = shr(io.in.a.bits.source, 2)
node _T_822 = eq(_T_821, UInt<2>(0h2))
node _T_823 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_824 = and(_T_822, _T_823)
node _T_825 = leq(uncommonBits_22, UInt<2>(0h3))
node _T_826 = and(_T_824, _T_825)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0)
node _T_827 = shr(io.in.a.bits.source, 2)
node _T_828 = eq(_T_827, UInt<2>(0h3))
node _T_829 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_830 = and(_T_828, _T_829)
node _T_831 = leq(uncommonBits_23, UInt<2>(0h3))
node _T_832 = and(_T_830, _T_831)
node _T_833 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_834 = eq(io.in.a.bits.source, UInt<6>(0h3d))
node _T_835 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_836 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_837 = eq(io.in.a.bits.source, UInt<6>(0h39))
node _T_838 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_839 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_840 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_841 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_842 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_843 = eq(io.in.a.bits.source, UInt<6>(0h31))
node _T_844 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_845 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_846 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_847 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_848 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_849 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_850 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_851 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_852 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_853 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_854 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_855 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_856 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_857 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_858 = or(_T_808, _T_814)
node _T_859 = or(_T_858, _T_820)
node _T_860 = or(_T_859, _T_826)
node _T_861 = or(_T_860, _T_832)
node _T_862 = or(_T_861, _T_833)
node _T_863 = or(_T_862, _T_834)
node _T_864 = or(_T_863, _T_835)
node _T_865 = or(_T_864, _T_836)
node _T_866 = or(_T_865, _T_837)
node _T_867 = or(_T_866, _T_838)
node _T_868 = or(_T_867, _T_839)
node _T_869 = or(_T_868, _T_840)
node _T_870 = or(_T_869, _T_841)
node _T_871 = or(_T_870, _T_842)
node _T_872 = or(_T_871, _T_843)
node _T_873 = or(_T_872, _T_844)
node _T_874 = or(_T_873, _T_845)
node _T_875 = or(_T_874, _T_846)
node _T_876 = or(_T_875, _T_847)
node _T_877 = or(_T_876, _T_848)
node _T_878 = or(_T_877, _T_849)
node _T_879 = or(_T_878, _T_850)
node _T_880 = or(_T_879, _T_851)
node _T_881 = or(_T_880, _T_852)
node _T_882 = or(_T_881, _T_853)
node _T_883 = or(_T_882, _T_854)
node _T_884 = or(_T_883, _T_855)
node _T_885 = or(_T_884, _T_856)
node _T_886 = or(_T_885, _T_857)
node _T_887 = and(_T_807, _T_886)
node _T_888 = or(UInt<1>(0h0), _T_887)
node _T_889 = asUInt(reset)
node _T_890 = eq(_T_889, UInt<1>(0h0))
when _T_890 :
node _T_891 = eq(_T_888, UInt<1>(0h0))
when _T_891 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_888, UInt<1>(0h1), "") : assert_19
node _T_892 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_893 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_894 = and(_T_892, _T_893)
node _T_895 = or(UInt<1>(0h0), _T_894)
node _T_896 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_897 = cvt(_T_896)
node _T_898 = and(_T_897, asSInt(UInt<13>(0h1000)))
node _T_899 = asSInt(_T_898)
node _T_900 = eq(_T_899, asSInt(UInt<1>(0h0)))
node _T_901 = and(_T_895, _T_900)
node _T_902 = or(UInt<1>(0h0), _T_901)
node _T_903 = asUInt(reset)
node _T_904 = eq(_T_903, UInt<1>(0h0))
when _T_904 :
node _T_905 = eq(_T_902, UInt<1>(0h0))
when _T_905 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_902, UInt<1>(0h1), "") : assert_20
node _T_906 = asUInt(reset)
node _T_907 = eq(_T_906, UInt<1>(0h0))
when _T_907 :
node _T_908 = eq(source_ok, UInt<1>(0h0))
when _T_908 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_909 = asUInt(reset)
node _T_910 = eq(_T_909, UInt<1>(0h0))
when _T_910 :
node _T_911 = eq(is_aligned, UInt<1>(0h0))
when _T_911 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_912 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_913 = asUInt(reset)
node _T_914 = eq(_T_913, UInt<1>(0h0))
when _T_914 :
node _T_915 = eq(_T_912, UInt<1>(0h0))
when _T_915 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_912, UInt<1>(0h1), "") : assert_23
node _T_916 = eq(io.in.a.bits.mask, mask)
node _T_917 = asUInt(reset)
node _T_918 = eq(_T_917, UInt<1>(0h0))
when _T_918 :
node _T_919 = eq(_T_916, UInt<1>(0h0))
when _T_919 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_916, UInt<1>(0h1), "") : assert_24
node _T_920 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_921 = asUInt(reset)
node _T_922 = eq(_T_921, UInt<1>(0h0))
when _T_922 :
node _T_923 = eq(_T_920, UInt<1>(0h0))
when _T_923 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_920, UInt<1>(0h1), "") : assert_25
node _T_924 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_924 :
node _T_925 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_926 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_927 = and(_T_925, _T_926)
node _T_928 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_929 = shr(io.in.a.bits.source, 2)
node _T_930 = eq(_T_929, UInt<1>(0h0))
node _T_931 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_932 = and(_T_930, _T_931)
node _T_933 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_934 = and(_T_932, _T_933)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_935 = shr(io.in.a.bits.source, 2)
node _T_936 = eq(_T_935, UInt<1>(0h1))
node _T_937 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_938 = and(_T_936, _T_937)
node _T_939 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_940 = and(_T_938, _T_939)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_941 = shr(io.in.a.bits.source, 2)
node _T_942 = eq(_T_941, UInt<2>(0h2))
node _T_943 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_944 = and(_T_942, _T_943)
node _T_945 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_946 = and(_T_944, _T_945)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_947 = shr(io.in.a.bits.source, 2)
node _T_948 = eq(_T_947, UInt<2>(0h3))
node _T_949 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_950 = and(_T_948, _T_949)
node _T_951 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_952 = and(_T_950, _T_951)
node _T_953 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_954 = eq(io.in.a.bits.source, UInt<6>(0h3d))
node _T_955 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_956 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_957 = eq(io.in.a.bits.source, UInt<6>(0h39))
node _T_958 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_959 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_960 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_961 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_962 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_963 = eq(io.in.a.bits.source, UInt<6>(0h31))
node _T_964 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_965 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_966 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_967 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_968 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_969 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_970 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_971 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_972 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_973 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_974 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_975 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_976 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_977 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_978 = or(_T_928, _T_934)
node _T_979 = or(_T_978, _T_940)
node _T_980 = or(_T_979, _T_946)
node _T_981 = or(_T_980, _T_952)
node _T_982 = or(_T_981, _T_953)
node _T_983 = or(_T_982, _T_954)
node _T_984 = or(_T_983, _T_955)
node _T_985 = or(_T_984, _T_956)
node _T_986 = or(_T_985, _T_957)
node _T_987 = or(_T_986, _T_958)
node _T_988 = or(_T_987, _T_959)
node _T_989 = or(_T_988, _T_960)
node _T_990 = or(_T_989, _T_961)
node _T_991 = or(_T_990, _T_962)
node _T_992 = or(_T_991, _T_963)
node _T_993 = or(_T_992, _T_964)
node _T_994 = or(_T_993, _T_965)
node _T_995 = or(_T_994, _T_966)
node _T_996 = or(_T_995, _T_967)
node _T_997 = or(_T_996, _T_968)
node _T_998 = or(_T_997, _T_969)
node _T_999 = or(_T_998, _T_970)
node _T_1000 = or(_T_999, _T_971)
node _T_1001 = or(_T_1000, _T_972)
node _T_1002 = or(_T_1001, _T_973)
node _T_1003 = or(_T_1002, _T_974)
node _T_1004 = or(_T_1003, _T_975)
node _T_1005 = or(_T_1004, _T_976)
node _T_1006 = or(_T_1005, _T_977)
node _T_1007 = and(_T_927, _T_1006)
node _T_1008 = or(UInt<1>(0h0), _T_1007)
node _T_1009 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1010 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_1011 = and(_T_1009, _T_1010)
node _T_1012 = or(UInt<1>(0h0), _T_1011)
node _T_1013 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1014 = cvt(_T_1013)
node _T_1015 = and(_T_1014, asSInt(UInt<13>(0h1000)))
node _T_1016 = asSInt(_T_1015)
node _T_1017 = eq(_T_1016, asSInt(UInt<1>(0h0)))
node _T_1018 = and(_T_1012, _T_1017)
node _T_1019 = or(UInt<1>(0h0), _T_1018)
node _T_1020 = and(_T_1008, _T_1019)
node _T_1021 = asUInt(reset)
node _T_1022 = eq(_T_1021, UInt<1>(0h0))
when _T_1022 :
node _T_1023 = eq(_T_1020, UInt<1>(0h0))
when _T_1023 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_1020, UInt<1>(0h1), "") : assert_26
node _T_1024 = asUInt(reset)
node _T_1025 = eq(_T_1024, UInt<1>(0h0))
when _T_1025 :
node _T_1026 = eq(source_ok, UInt<1>(0h0))
when _T_1026 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_1027 = asUInt(reset)
node _T_1028 = eq(_T_1027, UInt<1>(0h0))
when _T_1028 :
node _T_1029 = eq(is_aligned, UInt<1>(0h0))
when _T_1029 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_1030 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_1031 = asUInt(reset)
node _T_1032 = eq(_T_1031, UInt<1>(0h0))
when _T_1032 :
node _T_1033 = eq(_T_1030, UInt<1>(0h0))
when _T_1033 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_1030, UInt<1>(0h1), "") : assert_29
node _T_1034 = eq(io.in.a.bits.mask, mask)
node _T_1035 = asUInt(reset)
node _T_1036 = eq(_T_1035, UInt<1>(0h0))
when _T_1036 :
node _T_1037 = eq(_T_1034, UInt<1>(0h0))
when _T_1037 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_1034, UInt<1>(0h1), "") : assert_30
node _T_1038 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_1038 :
node _T_1039 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1040 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1041 = and(_T_1039, _T_1040)
node _T_1042 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0)
node _T_1043 = shr(io.in.a.bits.source, 2)
node _T_1044 = eq(_T_1043, UInt<1>(0h0))
node _T_1045 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_1046 = and(_T_1044, _T_1045)
node _T_1047 = leq(uncommonBits_28, UInt<2>(0h3))
node _T_1048 = and(_T_1046, _T_1047)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0)
node _T_1049 = shr(io.in.a.bits.source, 2)
node _T_1050 = eq(_T_1049, UInt<1>(0h1))
node _T_1051 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_1052 = and(_T_1050, _T_1051)
node _T_1053 = leq(uncommonBits_29, UInt<2>(0h3))
node _T_1054 = and(_T_1052, _T_1053)
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_1055 = shr(io.in.a.bits.source, 2)
node _T_1056 = eq(_T_1055, UInt<2>(0h2))
node _T_1057 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_1058 = and(_T_1056, _T_1057)
node _T_1059 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_1060 = and(_T_1058, _T_1059)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_1061 = shr(io.in.a.bits.source, 2)
node _T_1062 = eq(_T_1061, UInt<2>(0h3))
node _T_1063 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_1064 = and(_T_1062, _T_1063)
node _T_1065 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_1066 = and(_T_1064, _T_1065)
node _T_1067 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_1068 = eq(io.in.a.bits.source, UInt<6>(0h3d))
node _T_1069 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_1070 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_1071 = eq(io.in.a.bits.source, UInt<6>(0h39))
node _T_1072 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_1073 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_1074 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_1075 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_1076 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_1077 = eq(io.in.a.bits.source, UInt<6>(0h31))
node _T_1078 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_1079 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_1080 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_1081 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_1082 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_1083 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_1084 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_1085 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_1086 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_1087 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_1088 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_1089 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_1090 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_1091 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_1092 = or(_T_1042, _T_1048)
node _T_1093 = or(_T_1092, _T_1054)
node _T_1094 = or(_T_1093, _T_1060)
node _T_1095 = or(_T_1094, _T_1066)
node _T_1096 = or(_T_1095, _T_1067)
node _T_1097 = or(_T_1096, _T_1068)
node _T_1098 = or(_T_1097, _T_1069)
node _T_1099 = or(_T_1098, _T_1070)
node _T_1100 = or(_T_1099, _T_1071)
node _T_1101 = or(_T_1100, _T_1072)
node _T_1102 = or(_T_1101, _T_1073)
node _T_1103 = or(_T_1102, _T_1074)
node _T_1104 = or(_T_1103, _T_1075)
node _T_1105 = or(_T_1104, _T_1076)
node _T_1106 = or(_T_1105, _T_1077)
node _T_1107 = or(_T_1106, _T_1078)
node _T_1108 = or(_T_1107, _T_1079)
node _T_1109 = or(_T_1108, _T_1080)
node _T_1110 = or(_T_1109, _T_1081)
node _T_1111 = or(_T_1110, _T_1082)
node _T_1112 = or(_T_1111, _T_1083)
node _T_1113 = or(_T_1112, _T_1084)
node _T_1114 = or(_T_1113, _T_1085)
node _T_1115 = or(_T_1114, _T_1086)
node _T_1116 = or(_T_1115, _T_1087)
node _T_1117 = or(_T_1116, _T_1088)
node _T_1118 = or(_T_1117, _T_1089)
node _T_1119 = or(_T_1118, _T_1090)
node _T_1120 = or(_T_1119, _T_1091)
node _T_1121 = and(_T_1041, _T_1120)
node _T_1122 = or(UInt<1>(0h0), _T_1121)
node _T_1123 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1124 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_1125 = and(_T_1123, _T_1124)
node _T_1126 = or(UInt<1>(0h0), _T_1125)
node _T_1127 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1128 = cvt(_T_1127)
node _T_1129 = and(_T_1128, asSInt(UInt<13>(0h1000)))
node _T_1130 = asSInt(_T_1129)
node _T_1131 = eq(_T_1130, asSInt(UInt<1>(0h0)))
node _T_1132 = and(_T_1126, _T_1131)
node _T_1133 = or(UInt<1>(0h0), _T_1132)
node _T_1134 = and(_T_1122, _T_1133)
node _T_1135 = asUInt(reset)
node _T_1136 = eq(_T_1135, UInt<1>(0h0))
when _T_1136 :
node _T_1137 = eq(_T_1134, UInt<1>(0h0))
when _T_1137 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_1134, UInt<1>(0h1), "") : assert_31
node _T_1138 = asUInt(reset)
node _T_1139 = eq(_T_1138, UInt<1>(0h0))
when _T_1139 :
node _T_1140 = eq(source_ok, UInt<1>(0h0))
when _T_1140 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_1141 = asUInt(reset)
node _T_1142 = eq(_T_1141, UInt<1>(0h0))
when _T_1142 :
node _T_1143 = eq(is_aligned, UInt<1>(0h0))
when _T_1143 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_1144 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_1145 = asUInt(reset)
node _T_1146 = eq(_T_1145, UInt<1>(0h0))
when _T_1146 :
node _T_1147 = eq(_T_1144, UInt<1>(0h0))
when _T_1147 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_1144, UInt<1>(0h1), "") : assert_34
node _T_1148 = not(mask)
node _T_1149 = and(io.in.a.bits.mask, _T_1148)
node _T_1150 = eq(_T_1149, UInt<1>(0h0))
node _T_1151 = asUInt(reset)
node _T_1152 = eq(_T_1151, UInt<1>(0h0))
when _T_1152 :
node _T_1153 = eq(_T_1150, UInt<1>(0h0))
when _T_1153 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_1150, UInt<1>(0h1), "") : assert_35
node _T_1154 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_1154 :
node _T_1155 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1156 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1157 = and(_T_1155, _T_1156)
node _T_1158 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_1159 = shr(io.in.a.bits.source, 2)
node _T_1160 = eq(_T_1159, UInt<1>(0h0))
node _T_1161 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_1162 = and(_T_1160, _T_1161)
node _T_1163 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_1164 = and(_T_1162, _T_1163)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_1165 = shr(io.in.a.bits.source, 2)
node _T_1166 = eq(_T_1165, UInt<1>(0h1))
node _T_1167 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_1168 = and(_T_1166, _T_1167)
node _T_1169 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_1170 = and(_T_1168, _T_1169)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0)
node _T_1171 = shr(io.in.a.bits.source, 2)
node _T_1172 = eq(_T_1171, UInt<2>(0h2))
node _T_1173 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_1174 = and(_T_1172, _T_1173)
node _T_1175 = leq(uncommonBits_34, UInt<2>(0h3))
node _T_1176 = and(_T_1174, _T_1175)
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0)
node _T_1177 = shr(io.in.a.bits.source, 2)
node _T_1178 = eq(_T_1177, UInt<2>(0h3))
node _T_1179 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_1180 = and(_T_1178, _T_1179)
node _T_1181 = leq(uncommonBits_35, UInt<2>(0h3))
node _T_1182 = and(_T_1180, _T_1181)
node _T_1183 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_1184 = eq(io.in.a.bits.source, UInt<6>(0h3d))
node _T_1185 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_1186 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_1187 = eq(io.in.a.bits.source, UInt<6>(0h39))
node _T_1188 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_1189 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_1190 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_1191 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_1192 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_1193 = eq(io.in.a.bits.source, UInt<6>(0h31))
node _T_1194 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_1195 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_1196 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_1197 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_1198 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_1199 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_1200 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_1201 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_1202 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_1203 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_1204 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_1205 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_1206 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_1207 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_1208 = or(_T_1158, _T_1164)
node _T_1209 = or(_T_1208, _T_1170)
node _T_1210 = or(_T_1209, _T_1176)
node _T_1211 = or(_T_1210, _T_1182)
node _T_1212 = or(_T_1211, _T_1183)
node _T_1213 = or(_T_1212, _T_1184)
node _T_1214 = or(_T_1213, _T_1185)
node _T_1215 = or(_T_1214, _T_1186)
node _T_1216 = or(_T_1215, _T_1187)
node _T_1217 = or(_T_1216, _T_1188)
node _T_1218 = or(_T_1217, _T_1189)
node _T_1219 = or(_T_1218, _T_1190)
node _T_1220 = or(_T_1219, _T_1191)
node _T_1221 = or(_T_1220, _T_1192)
node _T_1222 = or(_T_1221, _T_1193)
node _T_1223 = or(_T_1222, _T_1194)
node _T_1224 = or(_T_1223, _T_1195)
node _T_1225 = or(_T_1224, _T_1196)
node _T_1226 = or(_T_1225, _T_1197)
node _T_1227 = or(_T_1226, _T_1198)
node _T_1228 = or(_T_1227, _T_1199)
node _T_1229 = or(_T_1228, _T_1200)
node _T_1230 = or(_T_1229, _T_1201)
node _T_1231 = or(_T_1230, _T_1202)
node _T_1232 = or(_T_1231, _T_1203)
node _T_1233 = or(_T_1232, _T_1204)
node _T_1234 = or(_T_1233, _T_1205)
node _T_1235 = or(_T_1234, _T_1206)
node _T_1236 = or(_T_1235, _T_1207)
node _T_1237 = and(_T_1157, _T_1236)
node _T_1238 = or(UInt<1>(0h0), _T_1237)
node _T_1239 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1240 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1241 = cvt(_T_1240)
node _T_1242 = and(_T_1241, asSInt(UInt<13>(0h1000)))
node _T_1243 = asSInt(_T_1242)
node _T_1244 = eq(_T_1243, asSInt(UInt<1>(0h0)))
node _T_1245 = and(_T_1239, _T_1244)
node _T_1246 = or(UInt<1>(0h0), _T_1245)
node _T_1247 = and(_T_1238, _T_1246)
node _T_1248 = asUInt(reset)
node _T_1249 = eq(_T_1248, UInt<1>(0h0))
when _T_1249 :
node _T_1250 = eq(_T_1247, UInt<1>(0h0))
when _T_1250 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_1247, UInt<1>(0h1), "") : assert_36
node _T_1251 = asUInt(reset)
node _T_1252 = eq(_T_1251, UInt<1>(0h0))
when _T_1252 :
node _T_1253 = eq(source_ok, UInt<1>(0h0))
when _T_1253 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_1254 = asUInt(reset)
node _T_1255 = eq(_T_1254, UInt<1>(0h0))
when _T_1255 :
node _T_1256 = eq(is_aligned, UInt<1>(0h0))
when _T_1256 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_1257 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_1258 = asUInt(reset)
node _T_1259 = eq(_T_1258, UInt<1>(0h0))
when _T_1259 :
node _T_1260 = eq(_T_1257, UInt<1>(0h0))
when _T_1260 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_1257, UInt<1>(0h1), "") : assert_39
node _T_1261 = eq(io.in.a.bits.mask, mask)
node _T_1262 = asUInt(reset)
node _T_1263 = eq(_T_1262, UInt<1>(0h0))
when _T_1263 :
node _T_1264 = eq(_T_1261, UInt<1>(0h0))
when _T_1264 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_1261, UInt<1>(0h1), "") : assert_40
node _T_1265 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_1265 :
node _T_1266 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1267 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1268 = and(_T_1266, _T_1267)
node _T_1269 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0)
node _T_1270 = shr(io.in.a.bits.source, 2)
node _T_1271 = eq(_T_1270, UInt<1>(0h0))
node _T_1272 = leq(UInt<1>(0h0), uncommonBits_36)
node _T_1273 = and(_T_1271, _T_1272)
node _T_1274 = leq(uncommonBits_36, UInt<2>(0h3))
node _T_1275 = and(_T_1273, _T_1274)
node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0)
node _T_1276 = shr(io.in.a.bits.source, 2)
node _T_1277 = eq(_T_1276, UInt<1>(0h1))
node _T_1278 = leq(UInt<1>(0h0), uncommonBits_37)
node _T_1279 = and(_T_1277, _T_1278)
node _T_1280 = leq(uncommonBits_37, UInt<2>(0h3))
node _T_1281 = and(_T_1279, _T_1280)
node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0)
node _T_1282 = shr(io.in.a.bits.source, 2)
node _T_1283 = eq(_T_1282, UInt<2>(0h2))
node _T_1284 = leq(UInt<1>(0h0), uncommonBits_38)
node _T_1285 = and(_T_1283, _T_1284)
node _T_1286 = leq(uncommonBits_38, UInt<2>(0h3))
node _T_1287 = and(_T_1285, _T_1286)
node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0)
node _T_1288 = shr(io.in.a.bits.source, 2)
node _T_1289 = eq(_T_1288, UInt<2>(0h3))
node _T_1290 = leq(UInt<1>(0h0), uncommonBits_39)
node _T_1291 = and(_T_1289, _T_1290)
node _T_1292 = leq(uncommonBits_39, UInt<2>(0h3))
node _T_1293 = and(_T_1291, _T_1292)
node _T_1294 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_1295 = eq(io.in.a.bits.source, UInt<6>(0h3d))
node _T_1296 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_1297 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_1298 = eq(io.in.a.bits.source, UInt<6>(0h39))
node _T_1299 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_1300 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_1301 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_1302 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_1303 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_1304 = eq(io.in.a.bits.source, UInt<6>(0h31))
node _T_1305 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_1306 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_1307 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_1308 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_1309 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_1310 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_1311 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_1312 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_1313 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_1314 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_1315 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_1316 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_1317 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_1318 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_1319 = or(_T_1269, _T_1275)
node _T_1320 = or(_T_1319, _T_1281)
node _T_1321 = or(_T_1320, _T_1287)
node _T_1322 = or(_T_1321, _T_1293)
node _T_1323 = or(_T_1322, _T_1294)
node _T_1324 = or(_T_1323, _T_1295)
node _T_1325 = or(_T_1324, _T_1296)
node _T_1326 = or(_T_1325, _T_1297)
node _T_1327 = or(_T_1326, _T_1298)
node _T_1328 = or(_T_1327, _T_1299)
node _T_1329 = or(_T_1328, _T_1300)
node _T_1330 = or(_T_1329, _T_1301)
node _T_1331 = or(_T_1330, _T_1302)
node _T_1332 = or(_T_1331, _T_1303)
node _T_1333 = or(_T_1332, _T_1304)
node _T_1334 = or(_T_1333, _T_1305)
node _T_1335 = or(_T_1334, _T_1306)
node _T_1336 = or(_T_1335, _T_1307)
node _T_1337 = or(_T_1336, _T_1308)
node _T_1338 = or(_T_1337, _T_1309)
node _T_1339 = or(_T_1338, _T_1310)
node _T_1340 = or(_T_1339, _T_1311)
node _T_1341 = or(_T_1340, _T_1312)
node _T_1342 = or(_T_1341, _T_1313)
node _T_1343 = or(_T_1342, _T_1314)
node _T_1344 = or(_T_1343, _T_1315)
node _T_1345 = or(_T_1344, _T_1316)
node _T_1346 = or(_T_1345, _T_1317)
node _T_1347 = or(_T_1346, _T_1318)
node _T_1348 = and(_T_1268, _T_1347)
node _T_1349 = or(UInt<1>(0h0), _T_1348)
node _T_1350 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1351 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1352 = cvt(_T_1351)
node _T_1353 = and(_T_1352, asSInt(UInt<13>(0h1000)))
node _T_1354 = asSInt(_T_1353)
node _T_1355 = eq(_T_1354, asSInt(UInt<1>(0h0)))
node _T_1356 = and(_T_1350, _T_1355)
node _T_1357 = or(UInt<1>(0h0), _T_1356)
node _T_1358 = and(_T_1349, _T_1357)
node _T_1359 = asUInt(reset)
node _T_1360 = eq(_T_1359, UInt<1>(0h0))
when _T_1360 :
node _T_1361 = eq(_T_1358, UInt<1>(0h0))
when _T_1361 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_1358, UInt<1>(0h1), "") : assert_41
node _T_1362 = asUInt(reset)
node _T_1363 = eq(_T_1362, UInt<1>(0h0))
when _T_1363 :
node _T_1364 = eq(source_ok, UInt<1>(0h0))
when _T_1364 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_1365 = asUInt(reset)
node _T_1366 = eq(_T_1365, UInt<1>(0h0))
when _T_1366 :
node _T_1367 = eq(is_aligned, UInt<1>(0h0))
when _T_1367 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_1368 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_1369 = asUInt(reset)
node _T_1370 = eq(_T_1369, UInt<1>(0h0))
when _T_1370 :
node _T_1371 = eq(_T_1368, UInt<1>(0h0))
when _T_1371 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_1368, UInt<1>(0h1), "") : assert_44
node _T_1372 = eq(io.in.a.bits.mask, mask)
node _T_1373 = asUInt(reset)
node _T_1374 = eq(_T_1373, UInt<1>(0h0))
when _T_1374 :
node _T_1375 = eq(_T_1372, UInt<1>(0h0))
when _T_1375 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_1372, UInt<1>(0h1), "") : assert_45
node _T_1376 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_1376 :
node _T_1377 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1378 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1379 = and(_T_1377, _T_1378)
node _T_1380 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0)
node _T_1381 = shr(io.in.a.bits.source, 2)
node _T_1382 = eq(_T_1381, UInt<1>(0h0))
node _T_1383 = leq(UInt<1>(0h0), uncommonBits_40)
node _T_1384 = and(_T_1382, _T_1383)
node _T_1385 = leq(uncommonBits_40, UInt<2>(0h3))
node _T_1386 = and(_T_1384, _T_1385)
node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0)
node _T_1387 = shr(io.in.a.bits.source, 2)
node _T_1388 = eq(_T_1387, UInt<1>(0h1))
node _T_1389 = leq(UInt<1>(0h0), uncommonBits_41)
node _T_1390 = and(_T_1388, _T_1389)
node _T_1391 = leq(uncommonBits_41, UInt<2>(0h3))
node _T_1392 = and(_T_1390, _T_1391)
node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0)
node _T_1393 = shr(io.in.a.bits.source, 2)
node _T_1394 = eq(_T_1393, UInt<2>(0h2))
node _T_1395 = leq(UInt<1>(0h0), uncommonBits_42)
node _T_1396 = and(_T_1394, _T_1395)
node _T_1397 = leq(uncommonBits_42, UInt<2>(0h3))
node _T_1398 = and(_T_1396, _T_1397)
node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0)
node _T_1399 = shr(io.in.a.bits.source, 2)
node _T_1400 = eq(_T_1399, UInt<2>(0h3))
node _T_1401 = leq(UInt<1>(0h0), uncommonBits_43)
node _T_1402 = and(_T_1400, _T_1401)
node _T_1403 = leq(uncommonBits_43, UInt<2>(0h3))
node _T_1404 = and(_T_1402, _T_1403)
node _T_1405 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_1406 = eq(io.in.a.bits.source, UInt<6>(0h3d))
node _T_1407 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_1408 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_1409 = eq(io.in.a.bits.source, UInt<6>(0h39))
node _T_1410 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_1411 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_1412 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_1413 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_1414 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_1415 = eq(io.in.a.bits.source, UInt<6>(0h31))
node _T_1416 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_1417 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_1418 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_1419 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_1420 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_1421 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_1422 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_1423 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_1424 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_1425 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_1426 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_1427 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_1428 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_1429 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_1430 = or(_T_1380, _T_1386)
node _T_1431 = or(_T_1430, _T_1392)
node _T_1432 = or(_T_1431, _T_1398)
node _T_1433 = or(_T_1432, _T_1404)
node _T_1434 = or(_T_1433, _T_1405)
node _T_1435 = or(_T_1434, _T_1406)
node _T_1436 = or(_T_1435, _T_1407)
node _T_1437 = or(_T_1436, _T_1408)
node _T_1438 = or(_T_1437, _T_1409)
node _T_1439 = or(_T_1438, _T_1410)
node _T_1440 = or(_T_1439, _T_1411)
node _T_1441 = or(_T_1440, _T_1412)
node _T_1442 = or(_T_1441, _T_1413)
node _T_1443 = or(_T_1442, _T_1414)
node _T_1444 = or(_T_1443, _T_1415)
node _T_1445 = or(_T_1444, _T_1416)
node _T_1446 = or(_T_1445, _T_1417)
node _T_1447 = or(_T_1446, _T_1418)
node _T_1448 = or(_T_1447, _T_1419)
node _T_1449 = or(_T_1448, _T_1420)
node _T_1450 = or(_T_1449, _T_1421)
node _T_1451 = or(_T_1450, _T_1422)
node _T_1452 = or(_T_1451, _T_1423)
node _T_1453 = or(_T_1452, _T_1424)
node _T_1454 = or(_T_1453, _T_1425)
node _T_1455 = or(_T_1454, _T_1426)
node _T_1456 = or(_T_1455, _T_1427)
node _T_1457 = or(_T_1456, _T_1428)
node _T_1458 = or(_T_1457, _T_1429)
node _T_1459 = and(_T_1379, _T_1458)
node _T_1460 = or(UInt<1>(0h0), _T_1459)
node _T_1461 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1462 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1463 = cvt(_T_1462)
node _T_1464 = and(_T_1463, asSInt(UInt<13>(0h1000)))
node _T_1465 = asSInt(_T_1464)
node _T_1466 = eq(_T_1465, asSInt(UInt<1>(0h0)))
node _T_1467 = and(_T_1461, _T_1466)
node _T_1468 = or(UInt<1>(0h0), _T_1467)
node _T_1469 = and(_T_1460, _T_1468)
node _T_1470 = asUInt(reset)
node _T_1471 = eq(_T_1470, UInt<1>(0h0))
when _T_1471 :
node _T_1472 = eq(_T_1469, UInt<1>(0h0))
when _T_1472 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_1469, UInt<1>(0h1), "") : assert_46
node _T_1473 = asUInt(reset)
node _T_1474 = eq(_T_1473, UInt<1>(0h0))
when _T_1474 :
node _T_1475 = eq(source_ok, UInt<1>(0h0))
when _T_1475 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_1476 = asUInt(reset)
node _T_1477 = eq(_T_1476, UInt<1>(0h0))
when _T_1477 :
node _T_1478 = eq(is_aligned, UInt<1>(0h0))
when _T_1478 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_1479 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_1480 = asUInt(reset)
node _T_1481 = eq(_T_1480, UInt<1>(0h0))
when _T_1481 :
node _T_1482 = eq(_T_1479, UInt<1>(0h0))
when _T_1482 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_1479, UInt<1>(0h1), "") : assert_49
node _T_1483 = eq(io.in.a.bits.mask, mask)
node _T_1484 = asUInt(reset)
node _T_1485 = eq(_T_1484, UInt<1>(0h0))
when _T_1485 :
node _T_1486 = eq(_T_1483, UInt<1>(0h0))
when _T_1486 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_1483, UInt<1>(0h1), "") : assert_50
node _T_1487 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1488 = asUInt(reset)
node _T_1489 = eq(_T_1488, UInt<1>(0h0))
when _T_1489 :
node _T_1490 = eq(_T_1487, UInt<1>(0h0))
when _T_1490 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_1487, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_1491 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1492 = asUInt(reset)
node _T_1493 = eq(_T_1492, UInt<1>(0h0))
when _T_1493 :
node _T_1494 = eq(_T_1491, UInt<1>(0h0))
when _T_1494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_1491, UInt<1>(0h1), "") : assert_52
node _source_ok_T_78 = eq(io.in.d.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0)
node _source_ok_T_79 = shr(io.in.d.bits.source, 2)
node _source_ok_T_80 = eq(_source_ok_T_79, UInt<1>(0h0))
node _source_ok_T_81 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_82 = and(_source_ok_T_80, _source_ok_T_81)
node _source_ok_T_83 = leq(source_ok_uncommonBits_4, UInt<2>(0h3))
node _source_ok_T_84 = and(_source_ok_T_82, _source_ok_T_83)
node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0)
node _source_ok_T_85 = shr(io.in.d.bits.source, 2)
node _source_ok_T_86 = eq(_source_ok_T_85, UInt<1>(0h1))
node _source_ok_T_87 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_88 = and(_source_ok_T_86, _source_ok_T_87)
node _source_ok_T_89 = leq(source_ok_uncommonBits_5, UInt<2>(0h3))
node _source_ok_T_90 = and(_source_ok_T_88, _source_ok_T_89)
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0)
node _source_ok_T_91 = shr(io.in.d.bits.source, 2)
node _source_ok_T_92 = eq(_source_ok_T_91, UInt<2>(0h2))
node _source_ok_T_93 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_94 = and(_source_ok_T_92, _source_ok_T_93)
node _source_ok_T_95 = leq(source_ok_uncommonBits_6, UInt<2>(0h3))
node _source_ok_T_96 = and(_source_ok_T_94, _source_ok_T_95)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_97 = shr(io.in.d.bits.source, 2)
node _source_ok_T_98 = eq(_source_ok_T_97, UInt<2>(0h3))
node _source_ok_T_99 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_100 = and(_source_ok_T_98, _source_ok_T_99)
node _source_ok_T_101 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_102 = and(_source_ok_T_100, _source_ok_T_101)
node _source_ok_T_103 = eq(io.in.d.bits.source, UInt<6>(0h3c))
node _source_ok_T_104 = eq(io.in.d.bits.source, UInt<6>(0h3d))
node _source_ok_T_105 = eq(io.in.d.bits.source, UInt<6>(0h3e))
node _source_ok_T_106 = eq(io.in.d.bits.source, UInt<6>(0h38))
node _source_ok_T_107 = eq(io.in.d.bits.source, UInt<6>(0h39))
node _source_ok_T_108 = eq(io.in.d.bits.source, UInt<6>(0h3a))
node _source_ok_T_109 = eq(io.in.d.bits.source, UInt<6>(0h34))
node _source_ok_T_110 = eq(io.in.d.bits.source, UInt<6>(0h35))
node _source_ok_T_111 = eq(io.in.d.bits.source, UInt<6>(0h36))
node _source_ok_T_112 = eq(io.in.d.bits.source, UInt<6>(0h30))
node _source_ok_T_113 = eq(io.in.d.bits.source, UInt<6>(0h31))
node _source_ok_T_114 = eq(io.in.d.bits.source, UInt<6>(0h32))
node _source_ok_T_115 = eq(io.in.d.bits.source, UInt<6>(0h2c))
node _source_ok_T_116 = eq(io.in.d.bits.source, UInt<6>(0h2d))
node _source_ok_T_117 = eq(io.in.d.bits.source, UInt<6>(0h2e))
node _source_ok_T_118 = eq(io.in.d.bits.source, UInt<6>(0h28))
node _source_ok_T_119 = eq(io.in.d.bits.source, UInt<6>(0h29))
node _source_ok_T_120 = eq(io.in.d.bits.source, UInt<6>(0h2a))
node _source_ok_T_121 = eq(io.in.d.bits.source, UInt<6>(0h24))
node _source_ok_T_122 = eq(io.in.d.bits.source, UInt<6>(0h25))
node _source_ok_T_123 = eq(io.in.d.bits.source, UInt<6>(0h26))
node _source_ok_T_124 = eq(io.in.d.bits.source, UInt<6>(0h20))
node _source_ok_T_125 = eq(io.in.d.bits.source, UInt<6>(0h21))
node _source_ok_T_126 = eq(io.in.d.bits.source, UInt<6>(0h22))
node _source_ok_T_127 = eq(io.in.d.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE_1 : UInt<1>[30]
connect _source_ok_WIRE_1[0], _source_ok_T_78
connect _source_ok_WIRE_1[1], _source_ok_T_84
connect _source_ok_WIRE_1[2], _source_ok_T_90
connect _source_ok_WIRE_1[3], _source_ok_T_96
connect _source_ok_WIRE_1[4], _source_ok_T_102
connect _source_ok_WIRE_1[5], _source_ok_T_103
connect _source_ok_WIRE_1[6], _source_ok_T_104
connect _source_ok_WIRE_1[7], _source_ok_T_105
connect _source_ok_WIRE_1[8], _source_ok_T_106
connect _source_ok_WIRE_1[9], _source_ok_T_107
connect _source_ok_WIRE_1[10], _source_ok_T_108
connect _source_ok_WIRE_1[11], _source_ok_T_109
connect _source_ok_WIRE_1[12], _source_ok_T_110
connect _source_ok_WIRE_1[13], _source_ok_T_111
connect _source_ok_WIRE_1[14], _source_ok_T_112
connect _source_ok_WIRE_1[15], _source_ok_T_113
connect _source_ok_WIRE_1[16], _source_ok_T_114
connect _source_ok_WIRE_1[17], _source_ok_T_115
connect _source_ok_WIRE_1[18], _source_ok_T_116
connect _source_ok_WIRE_1[19], _source_ok_T_117
connect _source_ok_WIRE_1[20], _source_ok_T_118
connect _source_ok_WIRE_1[21], _source_ok_T_119
connect _source_ok_WIRE_1[22], _source_ok_T_120
connect _source_ok_WIRE_1[23], _source_ok_T_121
connect _source_ok_WIRE_1[24], _source_ok_T_122
connect _source_ok_WIRE_1[25], _source_ok_T_123
connect _source_ok_WIRE_1[26], _source_ok_T_124
connect _source_ok_WIRE_1[27], _source_ok_T_125
connect _source_ok_WIRE_1[28], _source_ok_T_126
connect _source_ok_WIRE_1[29], _source_ok_T_127
node _source_ok_T_128 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_129 = or(_source_ok_T_128, _source_ok_WIRE_1[2])
node _source_ok_T_130 = or(_source_ok_T_129, _source_ok_WIRE_1[3])
node _source_ok_T_131 = or(_source_ok_T_130, _source_ok_WIRE_1[4])
node _source_ok_T_132 = or(_source_ok_T_131, _source_ok_WIRE_1[5])
node _source_ok_T_133 = or(_source_ok_T_132, _source_ok_WIRE_1[6])
node _source_ok_T_134 = or(_source_ok_T_133, _source_ok_WIRE_1[7])
node _source_ok_T_135 = or(_source_ok_T_134, _source_ok_WIRE_1[8])
node _source_ok_T_136 = or(_source_ok_T_135, _source_ok_WIRE_1[9])
node _source_ok_T_137 = or(_source_ok_T_136, _source_ok_WIRE_1[10])
node _source_ok_T_138 = or(_source_ok_T_137, _source_ok_WIRE_1[11])
node _source_ok_T_139 = or(_source_ok_T_138, _source_ok_WIRE_1[12])
node _source_ok_T_140 = or(_source_ok_T_139, _source_ok_WIRE_1[13])
node _source_ok_T_141 = or(_source_ok_T_140, _source_ok_WIRE_1[14])
node _source_ok_T_142 = or(_source_ok_T_141, _source_ok_WIRE_1[15])
node _source_ok_T_143 = or(_source_ok_T_142, _source_ok_WIRE_1[16])
node _source_ok_T_144 = or(_source_ok_T_143, _source_ok_WIRE_1[17])
node _source_ok_T_145 = or(_source_ok_T_144, _source_ok_WIRE_1[18])
node _source_ok_T_146 = or(_source_ok_T_145, _source_ok_WIRE_1[19])
node _source_ok_T_147 = or(_source_ok_T_146, _source_ok_WIRE_1[20])
node _source_ok_T_148 = or(_source_ok_T_147, _source_ok_WIRE_1[21])
node _source_ok_T_149 = or(_source_ok_T_148, _source_ok_WIRE_1[22])
node _source_ok_T_150 = or(_source_ok_T_149, _source_ok_WIRE_1[23])
node _source_ok_T_151 = or(_source_ok_T_150, _source_ok_WIRE_1[24])
node _source_ok_T_152 = or(_source_ok_T_151, _source_ok_WIRE_1[25])
node _source_ok_T_153 = or(_source_ok_T_152, _source_ok_WIRE_1[26])
node _source_ok_T_154 = or(_source_ok_T_153, _source_ok_WIRE_1[27])
node _source_ok_T_155 = or(_source_ok_T_154, _source_ok_WIRE_1[28])
node source_ok_1 = or(_source_ok_T_155, _source_ok_WIRE_1[29])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_1495 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1495 :
node _T_1496 = asUInt(reset)
node _T_1497 = eq(_T_1496, UInt<1>(0h0))
when _T_1497 :
node _T_1498 = eq(source_ok_1, UInt<1>(0h0))
when _T_1498 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_1499 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1500 = asUInt(reset)
node _T_1501 = eq(_T_1500, UInt<1>(0h0))
when _T_1501 :
node _T_1502 = eq(_T_1499, UInt<1>(0h0))
when _T_1502 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1499, UInt<1>(0h1), "") : assert_54
node _T_1503 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1504 = asUInt(reset)
node _T_1505 = eq(_T_1504, UInt<1>(0h0))
when _T_1505 :
node _T_1506 = eq(_T_1503, UInt<1>(0h0))
when _T_1506 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1503, UInt<1>(0h1), "") : assert_55
node _T_1507 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1508 = asUInt(reset)
node _T_1509 = eq(_T_1508, UInt<1>(0h0))
when _T_1509 :
node _T_1510 = eq(_T_1507, UInt<1>(0h0))
when _T_1510 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1507, UInt<1>(0h1), "") : assert_56
node _T_1511 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1512 = asUInt(reset)
node _T_1513 = eq(_T_1512, UInt<1>(0h0))
when _T_1513 :
node _T_1514 = eq(_T_1511, UInt<1>(0h0))
when _T_1514 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1511, UInt<1>(0h1), "") : assert_57
node _T_1515 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1515 :
node _T_1516 = asUInt(reset)
node _T_1517 = eq(_T_1516, UInt<1>(0h0))
when _T_1517 :
node _T_1518 = eq(source_ok_1, UInt<1>(0h0))
when _T_1518 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1519 = asUInt(reset)
node _T_1520 = eq(_T_1519, UInt<1>(0h0))
when _T_1520 :
node _T_1521 = eq(sink_ok, UInt<1>(0h0))
when _T_1521 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1522 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1523 = asUInt(reset)
node _T_1524 = eq(_T_1523, UInt<1>(0h0))
when _T_1524 :
node _T_1525 = eq(_T_1522, UInt<1>(0h0))
when _T_1525 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1522, UInt<1>(0h1), "") : assert_60
node _T_1526 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1527 = asUInt(reset)
node _T_1528 = eq(_T_1527, UInt<1>(0h0))
when _T_1528 :
node _T_1529 = eq(_T_1526, UInt<1>(0h0))
when _T_1529 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1526, UInt<1>(0h1), "") : assert_61
node _T_1530 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1531 = asUInt(reset)
node _T_1532 = eq(_T_1531, UInt<1>(0h0))
when _T_1532 :
node _T_1533 = eq(_T_1530, UInt<1>(0h0))
when _T_1533 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1530, UInt<1>(0h1), "") : assert_62
node _T_1534 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1535 = asUInt(reset)
node _T_1536 = eq(_T_1535, UInt<1>(0h0))
when _T_1536 :
node _T_1537 = eq(_T_1534, UInt<1>(0h0))
when _T_1537 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1534, UInt<1>(0h1), "") : assert_63
node _T_1538 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1539 = or(UInt<1>(0h0), _T_1538)
node _T_1540 = asUInt(reset)
node _T_1541 = eq(_T_1540, UInt<1>(0h0))
when _T_1541 :
node _T_1542 = eq(_T_1539, UInt<1>(0h0))
when _T_1542 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1539, UInt<1>(0h1), "") : assert_64
node _T_1543 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1543 :
node _T_1544 = asUInt(reset)
node _T_1545 = eq(_T_1544, UInt<1>(0h0))
when _T_1545 :
node _T_1546 = eq(source_ok_1, UInt<1>(0h0))
when _T_1546 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1547 = asUInt(reset)
node _T_1548 = eq(_T_1547, UInt<1>(0h0))
when _T_1548 :
node _T_1549 = eq(sink_ok, UInt<1>(0h0))
when _T_1549 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1550 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1551 = asUInt(reset)
node _T_1552 = eq(_T_1551, UInt<1>(0h0))
when _T_1552 :
node _T_1553 = eq(_T_1550, UInt<1>(0h0))
when _T_1553 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1550, UInt<1>(0h1), "") : assert_67
node _T_1554 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1555 = asUInt(reset)
node _T_1556 = eq(_T_1555, UInt<1>(0h0))
when _T_1556 :
node _T_1557 = eq(_T_1554, UInt<1>(0h0))
when _T_1557 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1554, UInt<1>(0h1), "") : assert_68
node _T_1558 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1559 = asUInt(reset)
node _T_1560 = eq(_T_1559, UInt<1>(0h0))
when _T_1560 :
node _T_1561 = eq(_T_1558, UInt<1>(0h0))
when _T_1561 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1558, UInt<1>(0h1), "") : assert_69
node _T_1562 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1563 = or(_T_1562, io.in.d.bits.corrupt)
node _T_1564 = asUInt(reset)
node _T_1565 = eq(_T_1564, UInt<1>(0h0))
when _T_1565 :
node _T_1566 = eq(_T_1563, UInt<1>(0h0))
when _T_1566 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1563, UInt<1>(0h1), "") : assert_70
node _T_1567 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1568 = or(UInt<1>(0h0), _T_1567)
node _T_1569 = asUInt(reset)
node _T_1570 = eq(_T_1569, UInt<1>(0h0))
when _T_1570 :
node _T_1571 = eq(_T_1568, UInt<1>(0h0))
when _T_1571 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1568, UInt<1>(0h1), "") : assert_71
node _T_1572 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1572 :
node _T_1573 = asUInt(reset)
node _T_1574 = eq(_T_1573, UInt<1>(0h0))
when _T_1574 :
node _T_1575 = eq(source_ok_1, UInt<1>(0h0))
when _T_1575 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1576 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1577 = asUInt(reset)
node _T_1578 = eq(_T_1577, UInt<1>(0h0))
when _T_1578 :
node _T_1579 = eq(_T_1576, UInt<1>(0h0))
when _T_1579 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1576, UInt<1>(0h1), "") : assert_73
node _T_1580 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1581 = asUInt(reset)
node _T_1582 = eq(_T_1581, UInt<1>(0h0))
when _T_1582 :
node _T_1583 = eq(_T_1580, UInt<1>(0h0))
when _T_1583 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1580, UInt<1>(0h1), "") : assert_74
node _T_1584 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1585 = or(UInt<1>(0h0), _T_1584)
node _T_1586 = asUInt(reset)
node _T_1587 = eq(_T_1586, UInt<1>(0h0))
when _T_1587 :
node _T_1588 = eq(_T_1585, UInt<1>(0h0))
when _T_1588 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1585, UInt<1>(0h1), "") : assert_75
node _T_1589 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1589 :
node _T_1590 = asUInt(reset)
node _T_1591 = eq(_T_1590, UInt<1>(0h0))
when _T_1591 :
node _T_1592 = eq(source_ok_1, UInt<1>(0h0))
when _T_1592 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1593 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1594 = asUInt(reset)
node _T_1595 = eq(_T_1594, UInt<1>(0h0))
when _T_1595 :
node _T_1596 = eq(_T_1593, UInt<1>(0h0))
when _T_1596 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1593, UInt<1>(0h1), "") : assert_77
node _T_1597 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1598 = or(_T_1597, io.in.d.bits.corrupt)
node _T_1599 = asUInt(reset)
node _T_1600 = eq(_T_1599, UInt<1>(0h0))
when _T_1600 :
node _T_1601 = eq(_T_1598, UInt<1>(0h0))
when _T_1601 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1598, UInt<1>(0h1), "") : assert_78
node _T_1602 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1603 = or(UInt<1>(0h0), _T_1602)
node _T_1604 = asUInt(reset)
node _T_1605 = eq(_T_1604, UInt<1>(0h0))
when _T_1605 :
node _T_1606 = eq(_T_1603, UInt<1>(0h0))
when _T_1606 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1603, UInt<1>(0h1), "") : assert_79
node _T_1607 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1607 :
node _T_1608 = asUInt(reset)
node _T_1609 = eq(_T_1608, UInt<1>(0h0))
when _T_1609 :
node _T_1610 = eq(source_ok_1, UInt<1>(0h0))
when _T_1610 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1611 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1612 = asUInt(reset)
node _T_1613 = eq(_T_1612, UInt<1>(0h0))
when _T_1613 :
node _T_1614 = eq(_T_1611, UInt<1>(0h0))
when _T_1614 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1611, UInt<1>(0h1), "") : assert_81
node _T_1615 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1616 = asUInt(reset)
node _T_1617 = eq(_T_1616, UInt<1>(0h0))
when _T_1617 :
node _T_1618 = eq(_T_1615, UInt<1>(0h0))
when _T_1618 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1615, UInt<1>(0h1), "") : assert_82
node _T_1619 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1620 = or(UInt<1>(0h0), _T_1619)
node _T_1621 = asUInt(reset)
node _T_1622 = eq(_T_1621, UInt<1>(0h0))
when _T_1622 :
node _T_1623 = eq(_T_1620, UInt<1>(0h0))
when _T_1623 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1620, UInt<1>(0h1), "") : assert_83
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.mask, UInt<8>(0h0)
connect _WIRE_4.bits.address, UInt<21>(0h0)
connect _WIRE_4.bits.source, UInt<7>(0h0)
connect _WIRE_4.bits.size, UInt<3>(0h0)
connect _WIRE_4.bits.param, UInt<2>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1624 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1625 = asUInt(reset)
node _T_1626 = eq(_T_1625, UInt<1>(0h0))
when _T_1626 :
node _T_1627 = eq(_T_1624, UInt<1>(0h0))
when _T_1627 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1624, UInt<1>(0h1), "") : assert_84
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<21>(0h0)
connect _WIRE_6.bits.source, UInt<7>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1628 = eq(_WIRE_7.valid, UInt<1>(0h0))
node _T_1629 = asUInt(reset)
node _T_1630 = eq(_T_1629, UInt<1>(0h0))
when _T_1630 :
node _T_1631 = eq(_T_1628, UInt<1>(0h0))
when _T_1631 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1628, UInt<1>(0h1), "") : assert_85
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_8.bits.sink, UInt<1>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1632 = eq(_WIRE_9.valid, UInt<1>(0h0))
node _T_1633 = asUInt(reset)
node _T_1634 = eq(_T_1633, UInt<1>(0h0))
when _T_1634 :
node _T_1635 = eq(_T_1632, UInt<1>(0h0))
when _T_1635 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1632, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1636 = eq(a_first, UInt<1>(0h0))
node _T_1637 = and(io.in.a.valid, _T_1636)
when _T_1637 :
node _T_1638 = eq(io.in.a.bits.opcode, opcode)
node _T_1639 = asUInt(reset)
node _T_1640 = eq(_T_1639, UInt<1>(0h0))
when _T_1640 :
node _T_1641 = eq(_T_1638, UInt<1>(0h0))
when _T_1641 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1638, UInt<1>(0h1), "") : assert_87
node _T_1642 = eq(io.in.a.bits.param, param)
node _T_1643 = asUInt(reset)
node _T_1644 = eq(_T_1643, UInt<1>(0h0))
when _T_1644 :
node _T_1645 = eq(_T_1642, UInt<1>(0h0))
when _T_1645 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1642, UInt<1>(0h1), "") : assert_88
node _T_1646 = eq(io.in.a.bits.size, size)
node _T_1647 = asUInt(reset)
node _T_1648 = eq(_T_1647, UInt<1>(0h0))
when _T_1648 :
node _T_1649 = eq(_T_1646, UInt<1>(0h0))
when _T_1649 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1646, UInt<1>(0h1), "") : assert_89
node _T_1650 = eq(io.in.a.bits.source, source)
node _T_1651 = asUInt(reset)
node _T_1652 = eq(_T_1651, UInt<1>(0h0))
when _T_1652 :
node _T_1653 = eq(_T_1650, UInt<1>(0h0))
when _T_1653 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1650, UInt<1>(0h1), "") : assert_90
node _T_1654 = eq(io.in.a.bits.address, address)
node _T_1655 = asUInt(reset)
node _T_1656 = eq(_T_1655, UInt<1>(0h0))
when _T_1656 :
node _T_1657 = eq(_T_1654, UInt<1>(0h0))
when _T_1657 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1654, UInt<1>(0h1), "") : assert_91
node _T_1658 = and(io.in.a.ready, io.in.a.valid)
node _T_1659 = and(_T_1658, a_first)
when _T_1659 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1660 = eq(d_first, UInt<1>(0h0))
node _T_1661 = and(io.in.d.valid, _T_1660)
when _T_1661 :
node _T_1662 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1663 = asUInt(reset)
node _T_1664 = eq(_T_1663, UInt<1>(0h0))
when _T_1664 :
node _T_1665 = eq(_T_1662, UInt<1>(0h0))
when _T_1665 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1662, UInt<1>(0h1), "") : assert_92
node _T_1666 = eq(io.in.d.bits.param, param_1)
node _T_1667 = asUInt(reset)
node _T_1668 = eq(_T_1667, UInt<1>(0h0))
when _T_1668 :
node _T_1669 = eq(_T_1666, UInt<1>(0h0))
when _T_1669 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1666, UInt<1>(0h1), "") : assert_93
node _T_1670 = eq(io.in.d.bits.size, size_1)
node _T_1671 = asUInt(reset)
node _T_1672 = eq(_T_1671, UInt<1>(0h0))
when _T_1672 :
node _T_1673 = eq(_T_1670, UInt<1>(0h0))
when _T_1673 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1670, UInt<1>(0h1), "") : assert_94
node _T_1674 = eq(io.in.d.bits.source, source_1)
node _T_1675 = asUInt(reset)
node _T_1676 = eq(_T_1675, UInt<1>(0h0))
when _T_1676 :
node _T_1677 = eq(_T_1674, UInt<1>(0h0))
when _T_1677 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1674, UInt<1>(0h1), "") : assert_95
node _T_1678 = eq(io.in.d.bits.sink, sink)
node _T_1679 = asUInt(reset)
node _T_1680 = eq(_T_1679, UInt<1>(0h0))
when _T_1680 :
node _T_1681 = eq(_T_1678, UInt<1>(0h0))
when _T_1681 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1678, UInt<1>(0h1), "") : assert_96
node _T_1682 = eq(io.in.d.bits.denied, denied)
node _T_1683 = asUInt(reset)
node _T_1684 = eq(_T_1683, UInt<1>(0h0))
when _T_1684 :
node _T_1685 = eq(_T_1682, UInt<1>(0h0))
when _T_1685 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1682, UInt<1>(0h1), "") : assert_97
node _T_1686 = and(io.in.d.ready, io.in.d.valid)
node _T_1687 = and(_T_1686, d_first)
when _T_1687 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<65>
connect a_set, UInt<65>(0h0)
wire a_set_wo_ready : UInt<65>
connect a_set_wo_ready, UInt<65>(0h0)
wire a_opcodes_set : UInt<260>
connect a_opcodes_set, UInt<260>(0h0)
wire a_sizes_set : UInt<260>
connect a_sizes_set, UInt<260>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_1688 = and(io.in.a.valid, a_first_1)
node _T_1689 = and(_T_1688, UInt<1>(0h1))
when _T_1689 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1690 = and(io.in.a.ready, io.in.a.valid)
node _T_1691 = and(_T_1690, a_first_1)
node _T_1692 = and(_T_1691, UInt<1>(0h1))
when _T_1692 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1693 = dshr(inflight, io.in.a.bits.source)
node _T_1694 = bits(_T_1693, 0, 0)
node _T_1695 = eq(_T_1694, UInt<1>(0h0))
node _T_1696 = asUInt(reset)
node _T_1697 = eq(_T_1696, UInt<1>(0h0))
when _T_1697 :
node _T_1698 = eq(_T_1695, UInt<1>(0h0))
when _T_1698 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1695, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<65>
connect d_clr, UInt<65>(0h0)
wire d_clr_wo_ready : UInt<65>
connect d_clr_wo_ready, UInt<65>(0h0)
wire d_opcodes_clr : UInt<260>
connect d_opcodes_clr, UInt<260>(0h0)
wire d_sizes_clr : UInt<260>
connect d_sizes_clr, UInt<260>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1699 = and(io.in.d.valid, d_first_1)
node _T_1700 = and(_T_1699, UInt<1>(0h1))
node _T_1701 = eq(d_release_ack, UInt<1>(0h0))
node _T_1702 = and(_T_1700, _T_1701)
when _T_1702 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1703 = and(io.in.d.ready, io.in.d.valid)
node _T_1704 = and(_T_1703, d_first_1)
node _T_1705 = and(_T_1704, UInt<1>(0h1))
node _T_1706 = eq(d_release_ack, UInt<1>(0h0))
node _T_1707 = and(_T_1705, _T_1706)
when _T_1707 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1708 = and(io.in.d.valid, d_first_1)
node _T_1709 = and(_T_1708, UInt<1>(0h1))
node _T_1710 = eq(d_release_ack, UInt<1>(0h0))
node _T_1711 = and(_T_1709, _T_1710)
when _T_1711 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1712 = dshr(inflight, io.in.d.bits.source)
node _T_1713 = bits(_T_1712, 0, 0)
node _T_1714 = or(_T_1713, same_cycle_resp)
node _T_1715 = asUInt(reset)
node _T_1716 = eq(_T_1715, UInt<1>(0h0))
when _T_1716 :
node _T_1717 = eq(_T_1714, UInt<1>(0h0))
when _T_1717 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1714, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1718 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1719 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1720 = or(_T_1718, _T_1719)
node _T_1721 = asUInt(reset)
node _T_1722 = eq(_T_1721, UInt<1>(0h0))
when _T_1722 :
node _T_1723 = eq(_T_1720, UInt<1>(0h0))
when _T_1723 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1720, UInt<1>(0h1), "") : assert_100
node _T_1724 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1725 = asUInt(reset)
node _T_1726 = eq(_T_1725, UInt<1>(0h0))
when _T_1726 :
node _T_1727 = eq(_T_1724, UInt<1>(0h0))
when _T_1727 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1724, UInt<1>(0h1), "") : assert_101
else :
node _T_1728 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1729 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1730 = or(_T_1728, _T_1729)
node _T_1731 = asUInt(reset)
node _T_1732 = eq(_T_1731, UInt<1>(0h0))
when _T_1732 :
node _T_1733 = eq(_T_1730, UInt<1>(0h0))
when _T_1733 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1730, UInt<1>(0h1), "") : assert_102
node _T_1734 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1735 = asUInt(reset)
node _T_1736 = eq(_T_1735, UInt<1>(0h0))
when _T_1736 :
node _T_1737 = eq(_T_1734, UInt<1>(0h0))
when _T_1737 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1734, UInt<1>(0h1), "") : assert_103
node _T_1738 = and(io.in.d.valid, d_first_1)
node _T_1739 = and(_T_1738, a_first_1)
node _T_1740 = and(_T_1739, io.in.a.valid)
node _T_1741 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1742 = and(_T_1740, _T_1741)
node _T_1743 = eq(d_release_ack, UInt<1>(0h0))
node _T_1744 = and(_T_1742, _T_1743)
when _T_1744 :
node _T_1745 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1746 = or(_T_1745, io.in.a.ready)
node _T_1747 = asUInt(reset)
node _T_1748 = eq(_T_1747, UInt<1>(0h0))
when _T_1748 :
node _T_1749 = eq(_T_1746, UInt<1>(0h0))
when _T_1749 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1746, UInt<1>(0h1), "") : assert_104
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_285
node _T_1750 = orr(inflight)
node _T_1751 = eq(_T_1750, UInt<1>(0h0))
node _T_1752 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1753 = or(_T_1751, _T_1752)
node _T_1754 = lt(watchdog, plusarg_reader.out)
node _T_1755 = or(_T_1753, _T_1754)
node _T_1756 = asUInt(reset)
node _T_1757 = eq(_T_1756, UInt<1>(0h0))
when _T_1757 :
node _T_1758 = eq(_T_1755, UInt<1>(0h0))
when _T_1758 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_1755, UInt<1>(0h1), "") : assert_105
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1759 = and(io.in.a.ready, io.in.a.valid)
node _T_1760 = and(io.in.d.ready, io.in.d.valid)
node _T_1761 = or(_T_1759, _T_1760)
when _T_1761 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<21>(0h0)
connect _c_first_WIRE.bits.source, UInt<7>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<21>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<65>
connect c_set, UInt<65>(0h0)
wire c_set_wo_ready : UInt<65>
connect c_set_wo_ready, UInt<65>(0h0)
wire c_opcodes_set : UInt<260>
connect c_opcodes_set, UInt<260>(0h0)
wire c_sizes_set : UInt<260>
connect c_sizes_set, UInt<260>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<21>(0h0)
connect _WIRE_10.bits.source, UInt<7>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1762 = and(_WIRE_11.valid, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<21>(0h0)
connect _WIRE_12.bits.source, UInt<7>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1763 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1764 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1765 = and(_T_1763, _T_1764)
node _T_1766 = and(_T_1762, _T_1765)
when _T_1766 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<21>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<21>(0h0)
connect _WIRE_14.bits.source, UInt<7>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1767 = and(_WIRE_15.ready, _WIRE_15.valid)
node _T_1768 = and(_T_1767, c_first)
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<21>(0h0)
connect _WIRE_16.bits.source, UInt<7>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1769 = bits(_WIRE_17.bits.opcode, 2, 2)
node _T_1770 = bits(_WIRE_17.bits.opcode, 1, 1)
node _T_1771 = and(_T_1769, _T_1770)
node _T_1772 = and(_T_1768, _T_1771)
when _T_1772 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<21>(0h0)
connect _c_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<21>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<21>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<21>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<21>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<21>(0h0)
connect _WIRE_18.bits.source, UInt<7>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1773 = dshr(inflight_1, _WIRE_19.bits.source)
node _T_1774 = bits(_T_1773, 0, 0)
node _T_1775 = eq(_T_1774, UInt<1>(0h0))
node _T_1776 = asUInt(reset)
node _T_1777 = eq(_T_1776, UInt<1>(0h0))
when _T_1777 :
node _T_1778 = eq(_T_1775, UInt<1>(0h0))
when _T_1778 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1775, UInt<1>(0h1), "") : assert_106
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<21>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<21>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<65>
connect d_clr_1, UInt<65>(0h0)
wire d_clr_wo_ready_1 : UInt<65>
connect d_clr_wo_ready_1, UInt<65>(0h0)
wire d_opcodes_clr_1 : UInt<260>
connect d_opcodes_clr_1, UInt<260>(0h0)
wire d_sizes_clr_1 : UInt<260>
connect d_sizes_clr_1, UInt<260>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1779 = and(io.in.d.valid, d_first_2)
node _T_1780 = and(_T_1779, UInt<1>(0h1))
node _T_1781 = and(_T_1780, d_release_ack_1)
when _T_1781 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1782 = and(io.in.d.ready, io.in.d.valid)
node _T_1783 = and(_T_1782, d_first_2)
node _T_1784 = and(_T_1783, UInt<1>(0h1))
node _T_1785 = and(_T_1784, d_release_ack_1)
when _T_1785 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1786 = and(io.in.d.valid, d_first_2)
node _T_1787 = and(_T_1786, UInt<1>(0h1))
node _T_1788 = and(_T_1787, d_release_ack_1)
when _T_1788 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<21>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<21>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<21>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1789 = dshr(inflight_1, io.in.d.bits.source)
node _T_1790 = bits(_T_1789, 0, 0)
node _T_1791 = or(_T_1790, same_cycle_resp_1)
node _T_1792 = asUInt(reset)
node _T_1793 = eq(_T_1792, UInt<1>(0h0))
when _T_1793 :
node _T_1794 = eq(_T_1791, UInt<1>(0h0))
when _T_1794 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107
assert(clock, _T_1791, UInt<1>(0h1), "") : assert_107
when same_cycle_resp_1 :
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<21>(0h0)
connect _WIRE_20.bits.source, UInt<7>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1795 = eq(io.in.d.bits.size, _WIRE_21.bits.size)
node _T_1796 = asUInt(reset)
node _T_1797 = eq(_T_1796, UInt<1>(0h0))
when _T_1797 :
node _T_1798 = eq(_T_1795, UInt<1>(0h0))
when _T_1798 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1795, UInt<1>(0h1), "") : assert_108
else :
node _T_1799 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1800 = asUInt(reset)
node _T_1801 = eq(_T_1800, UInt<1>(0h0))
when _T_1801 :
node _T_1802 = eq(_T_1799, UInt<1>(0h0))
when _T_1802 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1799, UInt<1>(0h1), "") : assert_109
node _T_1803 = and(io.in.d.valid, d_first_2)
node _T_1804 = and(_T_1803, c_first)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<21>(0h0)
connect _WIRE_22.bits.source, UInt<7>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1805 = and(_T_1804, _WIRE_23.valid)
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<21>(0h0)
connect _WIRE_24.bits.source, UInt<7>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1806 = eq(_WIRE_25.bits.source, io.in.d.bits.source)
node _T_1807 = and(_T_1805, _T_1806)
node _T_1808 = and(_T_1807, d_release_ack_1)
node _T_1809 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1810 = and(_T_1808, _T_1809)
when _T_1810 :
node _T_1811 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<64>(0h0)
connect _WIRE_26.bits.address, UInt<21>(0h0)
connect _WIRE_26.bits.source, UInt<7>(0h0)
connect _WIRE_26.bits.size, UInt<3>(0h0)
connect _WIRE_26.bits.param, UInt<3>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
node _T_1812 = or(_T_1811, _WIRE_27.ready)
node _T_1813 = asUInt(reset)
node _T_1814 = eq(_T_1813, UInt<1>(0h0))
when _T_1814 :
node _T_1815 = eq(_T_1812, UInt<1>(0h0))
when _T_1815 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1812, UInt<1>(0h1), "") : assert_110
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_286
node _T_1816 = orr(inflight_1)
node _T_1817 = eq(_T_1816, UInt<1>(0h0))
node _T_1818 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1819 = or(_T_1817, _T_1818)
node _T_1820 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1821 = or(_T_1819, _T_1820)
node _T_1822 = asUInt(reset)
node _T_1823 = eq(_T_1822, UInt<1>(0h0))
when _T_1823 :
node _T_1824 = eq(_T_1821, UInt<1>(0h0))
when _T_1824 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_1821, UInt<1>(0h1), "") : assert_111
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<64>(0h0)
connect _WIRE_28.bits.address, UInt<21>(0h0)
connect _WIRE_28.bits.source, UInt<7>(0h0)
connect _WIRE_28.bits.size, UInt<3>(0h0)
connect _WIRE_28.bits.param, UInt<3>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
node _T_1825 = and(_WIRE_29.ready, _WIRE_29.valid)
node _T_1826 = and(io.in.d.ready, io.in.d.valid)
node _T_1827 = or(_T_1825, _T_1826)
when _T_1827 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_106( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_d_bits_source // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71]
wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [6:0] source; // @[Monitor.scala:390:22]
reg [20:0] address; // @[Monitor.scala:391:22]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [6:0] source_1; // @[Monitor.scala:541:22]
reg [64:0] inflight; // @[Monitor.scala:614:27]
reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [259:0] inflight_sizes; // @[Monitor.scala:618:33]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _GEN_0 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_1 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [64:0] inflight_1; // @[Monitor.scala:726:35]
reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module ClockCrossingReg_w55 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<55>, q : UInt<55>, flip en : UInt<1>}
reg cdc_reg : UInt<55>, clock
when io.en :
connect cdc_reg, io.d
connect io.q, cdc_reg | module ClockCrossingReg_w55( // @[SynchronizerReg.scala:191:7]
input clock, // @[SynchronizerReg.scala:191:7]
input [54:0] io_d, // @[SynchronizerReg.scala:195:14]
output [54:0] io_q, // @[SynchronizerReg.scala:195:14]
input io_en // @[SynchronizerReg.scala:195:14]
);
reg [54:0] cdc_reg; // @[SynchronizerReg.scala:201:76]
always @(posedge clock) begin // @[SynchronizerReg.scala:191:7]
if (io_en) // @[SynchronizerReg.scala:195:14]
cdc_reg <= io_d; // @[SynchronizerReg.scala:201:76]
always @(posedge) |
Generate the Verilog code corresponding to this FIRRTL code module BootROMClockSinkDomain :
output auto : { flip bootrom_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip clock_in : { clock : Clock, reset : Reset}}
output clock : Clock
output reset : Reset
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset
inst bootrom of TLROM
connect bootrom.clock, childClock
connect bootrom.reset, childReset
wire clockNodeIn : { clock : Clock, reset : Reset}
invalidate clockNodeIn.reset
invalidate clockNodeIn.clock
connect clockNodeIn, auto.clock_in
connect bootrom.auto.in, auto.bootrom_in
connect childClock, clockNodeIn.clock
connect childReset, clockNodeIn.reset
connect clock, clockNodeIn.clock
connect reset, clockNodeIn.reset | module BootROMClockSinkDomain( // @[ClockDomain.scala:14:9]
output auto_bootrom_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_bootrom_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_bootrom_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_bootrom_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_bootrom_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [10:0] auto_bootrom_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [16:0] auto_bootrom_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_bootrom_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_bootrom_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_bootrom_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_bootrom_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_bootrom_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_bootrom_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [10:0] auto_bootrom_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_bootrom_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_reset // @[LazyModuleImp.scala:107:25]
);
wire auto_bootrom_in_a_valid_0 = auto_bootrom_in_a_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_bootrom_in_a_bits_opcode_0 = auto_bootrom_in_a_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] auto_bootrom_in_a_bits_param_0 = auto_bootrom_in_a_bits_param; // @[ClockDomain.scala:14:9]
wire [1:0] auto_bootrom_in_a_bits_size_0 = auto_bootrom_in_a_bits_size; // @[ClockDomain.scala:14:9]
wire [10:0] auto_bootrom_in_a_bits_source_0 = auto_bootrom_in_a_bits_source; // @[ClockDomain.scala:14:9]
wire [16:0] auto_bootrom_in_a_bits_address_0 = auto_bootrom_in_a_bits_address; // @[ClockDomain.scala:14:9]
wire [7:0] auto_bootrom_in_a_bits_mask_0 = auto_bootrom_in_a_bits_mask; // @[ClockDomain.scala:14:9]
wire [63:0] auto_bootrom_in_a_bits_data_0 = auto_bootrom_in_a_bits_data; // @[ClockDomain.scala:14:9]
wire auto_bootrom_in_a_bits_corrupt_0 = auto_bootrom_in_a_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_bootrom_in_d_ready_0 = auto_bootrom_in_d_ready; // @[ClockDomain.scala:14:9]
wire auto_clock_in_clock_0 = auto_clock_in_clock; // @[ClockDomain.scala:14:9]
wire auto_clock_in_reset_0 = auto_clock_in_reset; // @[ClockDomain.scala:14:9]
wire [2:0] auto_bootrom_in_d_bits_opcode = 3'h1; // @[ClockDomain.scala:14:9]
wire [1:0] auto_bootrom_in_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9]
wire auto_bootrom_in_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_bootrom_in_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_bootrom_in_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire clockNodeIn_clock = auto_clock_in_clock_0; // @[ClockDomain.scala:14:9]
wire clockNodeIn_reset = auto_clock_in_reset_0; // @[ClockDomain.scala:14:9]
wire auto_bootrom_in_a_ready_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_bootrom_in_d_bits_size_0; // @[ClockDomain.scala:14:9]
wire [10:0] auto_bootrom_in_d_bits_source_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_bootrom_in_d_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_bootrom_in_d_valid_0; // @[ClockDomain.scala:14:9]
wire childClock; // @[LazyModuleImp.scala:155:31]
wire childReset; // @[LazyModuleImp.scala:158:31]
assign childClock = clockNodeIn_clock; // @[MixedNode.scala:551:17]
assign childReset = clockNodeIn_reset; // @[MixedNode.scala:551:17]
TLROM bootrom ( // @[BootROM.scala:86:17]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_in_a_ready (auto_bootrom_in_a_ready_0),
.auto_in_a_valid (auto_bootrom_in_a_valid_0), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_opcode (auto_bootrom_in_a_bits_opcode_0), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_param (auto_bootrom_in_a_bits_param_0), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_size (auto_bootrom_in_a_bits_size_0), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_source (auto_bootrom_in_a_bits_source_0), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_address (auto_bootrom_in_a_bits_address_0), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_mask (auto_bootrom_in_a_bits_mask_0), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_data (auto_bootrom_in_a_bits_data_0), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_corrupt (auto_bootrom_in_a_bits_corrupt_0), // @[ClockDomain.scala:14:9]
.auto_in_d_ready (auto_bootrom_in_d_ready_0), // @[ClockDomain.scala:14:9]
.auto_in_d_valid (auto_bootrom_in_d_valid_0),
.auto_in_d_bits_size (auto_bootrom_in_d_bits_size_0),
.auto_in_d_bits_source (auto_bootrom_in_d_bits_source_0),
.auto_in_d_bits_data (auto_bootrom_in_d_bits_data_0)
); // @[BootROM.scala:86:17]
assign auto_bootrom_in_a_ready = auto_bootrom_in_a_ready_0; // @[ClockDomain.scala:14:9]
assign auto_bootrom_in_d_valid = auto_bootrom_in_d_valid_0; // @[ClockDomain.scala:14:9]
assign auto_bootrom_in_d_bits_size = auto_bootrom_in_d_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_bootrom_in_d_bits_source = auto_bootrom_in_d_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_bootrom_in_d_bits_data = auto_bootrom_in_d_bits_data_0; // @[ClockDomain.scala:14:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module SystemBus :
output auto : { flip coupler_from_rockettile_tl_master_clock_xing_in_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}, flip coupler_from_rockettile_tl_master_clock_xing_in_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}, coupler_to_bus_named_coh_widget_anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}, flip coupler_from_bus_named_fbus_bus_xing_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, coupler_to_bus_named_cbus_bus_xing_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, fixedClockNode_anon_out_2 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_1 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_0 : { clock : Clock, reset : Reset}, flip sbus_clock_groups_in : { member : { sbus_1 : { clock : Clock, reset : Reset}, sbus_0 : { clock : Clock, reset : Reset}}}, sbus_clock_groups_out : { member : { coh_0 : { clock : Clock, reset : Reset}}}}
output clock : Clock
output reset : Reset
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset
inst sbus_clock_groups of ClockGroupAggregator_sbus
inst clockGroup of ClockGroup
inst fixedClockNode of FixedClockBroadcast_4
inst broadcast of BundleBridgeNexus_NoOutput
inst system_bus_xbar of TLXbar_sbus_i3_o2_a32d128s7k4z4c
connect system_bus_xbar.clock, childClock
connect system_bus_xbar.reset, childReset
inst fixer of TLFIFOFixer
connect fixer.clock, childClock
connect fixer.reset, childReset
inst coupler_to_bus_named_cbus of TLInterconnectCoupler_sbus_to_bus_named_cbus
connect coupler_to_bus_named_cbus.clock, childClock
connect coupler_to_bus_named_cbus.reset, childReset
inst coupler_from_bus_named_fbus of TLInterconnectCoupler_sbus_from_bus_named_fbus
connect coupler_from_bus_named_fbus.clock, childClock
connect coupler_from_bus_named_fbus.reset, childReset
inst coupler_to_bus_named_coh of TLInterconnectCoupler_sbus_to_bus_named_coh
connect coupler_to_bus_named_coh.clock, childClock
connect coupler_to_bus_named_coh.reset, childReset
inst coupler_from_rockettile of TLInterconnectCoupler_sbus_from_rockettile
connect coupler_from_rockettile.clock, childClock
connect coupler_from_rockettile.reset, childReset
wire clockSinkNodeIn : { clock : Clock, reset : Reset}
invalidate clockSinkNodeIn.reset
invalidate clockSinkNodeIn.clock
connect clockGroup.auto.in, sbus_clock_groups.auto.out_0
connect fixedClockNode.auto.anon_in, clockGroup.auto.out
connect clockSinkNodeIn, fixedClockNode.auto.anon_out_0
connect coupler_to_bus_named_cbus.auto.widget_anon_in, system_bus_xbar.auto.anon_out_0
connect coupler_to_bus_named_coh.auto.widget_anon_in, system_bus_xbar.auto.anon_out_1
connect system_bus_xbar.auto.anon_in_0, fixer.auto.anon_out_0
connect system_bus_xbar.auto.anon_in_1, fixer.auto.anon_out_1
connect system_bus_xbar.auto.anon_in_2, fixer.auto.anon_out_2
connect fixer.auto.anon_in_0, coupler_from_bus_named_fbus.auto.widget_anon_out
connect fixer.auto.anon_in_1, coupler_from_rockettile.auto.tl_out_0
connect fixer.auto.anon_in_2, coupler_from_rockettile.auto.tl_out_1
connect auto.sbus_clock_groups_out, sbus_clock_groups.auto.out_1
connect sbus_clock_groups.auto.in, auto.sbus_clock_groups_in
connect auto.fixedClockNode_anon_out_0, fixedClockNode.auto.anon_out_1
connect auto.fixedClockNode_anon_out_1, fixedClockNode.auto.anon_out_2
connect auto.fixedClockNode_anon_out_2, fixedClockNode.auto.anon_out_3
connect coupler_to_bus_named_cbus.auto.bus_xing_out.d, auto.coupler_to_bus_named_cbus_bus_xing_out.d
connect auto.coupler_to_bus_named_cbus_bus_xing_out.a.bits, coupler_to_bus_named_cbus.auto.bus_xing_out.a.bits
connect auto.coupler_to_bus_named_cbus_bus_xing_out.a.valid, coupler_to_bus_named_cbus.auto.bus_xing_out.a.valid
connect coupler_to_bus_named_cbus.auto.bus_xing_out.a.ready, auto.coupler_to_bus_named_cbus_bus_xing_out.a.ready
connect coupler_from_bus_named_fbus.auto.bus_xing_in, auto.coupler_from_bus_named_fbus_bus_xing_in
connect auto.coupler_to_bus_named_coh_widget_anon_out.e.bits, coupler_to_bus_named_coh.auto.widget_anon_out.e.bits
connect auto.coupler_to_bus_named_coh_widget_anon_out.e.valid, coupler_to_bus_named_coh.auto.widget_anon_out.e.valid
connect coupler_to_bus_named_coh.auto.widget_anon_out.e.ready, auto.coupler_to_bus_named_coh_widget_anon_out.e.ready
connect coupler_to_bus_named_coh.auto.widget_anon_out.d, auto.coupler_to_bus_named_coh_widget_anon_out.d
connect auto.coupler_to_bus_named_coh_widget_anon_out.c.bits, coupler_to_bus_named_coh.auto.widget_anon_out.c.bits
connect auto.coupler_to_bus_named_coh_widget_anon_out.c.valid, coupler_to_bus_named_coh.auto.widget_anon_out.c.valid
connect coupler_to_bus_named_coh.auto.widget_anon_out.c.ready, auto.coupler_to_bus_named_coh_widget_anon_out.c.ready
connect coupler_to_bus_named_coh.auto.widget_anon_out.b, auto.coupler_to_bus_named_coh_widget_anon_out.b
connect auto.coupler_to_bus_named_coh_widget_anon_out.a.bits, coupler_to_bus_named_coh.auto.widget_anon_out.a.bits
connect auto.coupler_to_bus_named_coh_widget_anon_out.a.valid, coupler_to_bus_named_coh.auto.widget_anon_out.a.valid
connect coupler_to_bus_named_coh.auto.widget_anon_out.a.ready, auto.coupler_to_bus_named_coh_widget_anon_out.a.ready
connect coupler_from_rockettile.auto.tl_master_clock_xing_in_0, auto.coupler_from_rockettile_tl_master_clock_xing_in_0
connect coupler_from_rockettile.auto.tl_master_clock_xing_in_1, auto.coupler_from_rockettile_tl_master_clock_xing_in_1
connect childClock, clockSinkNodeIn.clock
connect childReset, clockSinkNodeIn.reset
connect clock, clockSinkNodeIn.clock
connect reset, clockSinkNodeIn.reset | module SystemBus( // @[ClockDomain.scala:14:9]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [15:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_valid, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_param, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_address, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_valid, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [15:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_coh_widget_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [15:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_coh_widget_anon_out_b_valid, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_b_bits_param, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_b_bits_address, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_coh_widget_anon_out_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_coh_widget_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_coh_widget_anon_out_e_valid, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_coupler_to_bus_named_coh_widget_anon_out_e_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_bus_named_fbus_bus_xing_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_bus_named_fbus_bus_xing_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_cbus_bus_xing_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [28:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_cbus_bus_xing_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_2_clock, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_2_reset, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_1_clock, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_1_reset, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_0_clock, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_0_reset, // @[LazyModuleImp.scala:107:25]
input auto_sbus_clock_groups_in_member_sbus_1_clock, // @[LazyModuleImp.scala:107:25]
input auto_sbus_clock_groups_in_member_sbus_1_reset, // @[LazyModuleImp.scala:107:25]
input auto_sbus_clock_groups_in_member_sbus_0_clock, // @[LazyModuleImp.scala:107:25]
input auto_sbus_clock_groups_in_member_sbus_0_reset, // @[LazyModuleImp.scala:107:25]
output auto_sbus_clock_groups_out_member_coh_0_clock, // @[LazyModuleImp.scala:107:25]
output auto_sbus_clock_groups_out_member_coh_0_reset // @[LazyModuleImp.scala:107:25]
);
wire coupler_to_bus_named_coh_auto_widget_anon_in_e_valid; // @[LazyModuleImp.scala:138:7]
wire [3:0] coupler_to_bus_named_coh_auto_widget_anon_in_e_bits_sink; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_coh_auto_widget_anon_in_d_ready; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_coh_auto_widget_anon_in_c_valid; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_coh_auto_widget_anon_in_c_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_in_c_bits_data; // @[LazyModuleImp.scala:138:7]
wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_in_c_bits_address; // @[LazyModuleImp.scala:138:7]
wire [6:0] coupler_to_bus_named_coh_auto_widget_anon_in_c_bits_source; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_c_bits_size; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_c_bits_param; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_c_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_coh_auto_widget_anon_in_b_ready; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_coh_auto_widget_anon_in_a_valid; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_data; // @[LazyModuleImp.scala:138:7]
wire [15:0] coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_mask; // @[LazyModuleImp.scala:138:7]
wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_address; // @[LazyModuleImp.scala:138:7]
wire [6:0] coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_source; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_size; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_param; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire fixer_auto_anon_out_0_d_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_0_d_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire [127:0] fixer_auto_anon_out_0_d_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_0_d_bits_denied; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_out_0_d_bits_sink; // @[FIFOFixer.scala:50:9]
wire [4:0] fixer_auto_anon_out_0_d_bits_source; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_out_0_d_bits_size; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_out_0_d_bits_param; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_0_d_bits_opcode; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_0_a_ready; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_1_d_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_1_d_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire [127:0] fixer_auto_anon_out_1_d_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_1_d_bits_denied; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_out_1_d_bits_sink; // @[FIFOFixer.scala:50:9]
wire [4:0] fixer_auto_anon_out_1_d_bits_source; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_out_1_d_bits_size; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_out_1_d_bits_param; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_1_d_bits_opcode; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_1_a_ready; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_2_d_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_2_d_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire [127:0] fixer_auto_anon_out_2_d_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_2_d_bits_denied; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_out_2_d_bits_sink; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_out_2_d_bits_source; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_out_2_d_bits_size; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_out_2_d_bits_param; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_2_d_bits_opcode; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_2_c_ready; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_2_b_valid; // @[FIFOFixer.scala:50:9]
wire [31:0] fixer_auto_anon_out_2_b_bits_address; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_out_2_b_bits_param; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_2_a_ready; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_0_d_ready; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_0_a_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_0_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire [127:0] fixer_auto_anon_in_0_a_bits_data; // @[FIFOFixer.scala:50:9]
wire [15:0] fixer_auto_anon_in_0_a_bits_mask; // @[FIFOFixer.scala:50:9]
wire [31:0] fixer_auto_anon_in_0_a_bits_address; // @[FIFOFixer.scala:50:9]
wire [4:0] fixer_auto_anon_in_0_a_bits_source; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_in_0_a_bits_size; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_0_a_bits_param; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_0_a_bits_opcode; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_1_d_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_1_d_ready; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_1_d_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire [127:0] fixer_auto_anon_in_1_d_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_1_d_bits_denied; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_in_1_d_bits_sink; // @[FIFOFixer.scala:50:9]
wire [4:0] fixer_auto_anon_in_1_d_bits_source; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_in_1_d_bits_size; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_in_1_d_bits_param; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_1_d_bits_opcode; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_1_a_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_1_a_ready; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_1_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire [127:0] fixer_auto_anon_in_1_a_bits_data; // @[FIFOFixer.scala:50:9]
wire [15:0] fixer_auto_anon_in_1_a_bits_mask; // @[FIFOFixer.scala:50:9]
wire [31:0] fixer_auto_anon_in_1_a_bits_address; // @[FIFOFixer.scala:50:9]
wire [4:0] fixer_auto_anon_in_1_a_bits_source; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_in_1_a_bits_size; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_1_a_bits_param; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_1_a_bits_opcode; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_2_e_valid; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_in_2_e_bits_sink; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_2_d_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_2_d_ready; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_2_d_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire [127:0] fixer_auto_anon_in_2_d_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_2_d_bits_denied; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_in_2_d_bits_sink; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_in_2_d_bits_source; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_in_2_d_bits_size; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_in_2_d_bits_param; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_2_d_bits_opcode; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_2_c_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_2_c_ready; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_2_c_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire [127:0] fixer_auto_anon_in_2_c_bits_data; // @[FIFOFixer.scala:50:9]
wire [31:0] fixer_auto_anon_in_2_c_bits_address; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_in_2_c_bits_source; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_in_2_c_bits_size; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_2_c_bits_param; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_2_c_bits_opcode; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_2_b_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_2_b_ready; // @[FIFOFixer.scala:50:9]
wire [31:0] fixer_auto_anon_in_2_b_bits_address; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_in_2_b_bits_param; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_2_a_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_2_a_ready; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_2_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire [127:0] fixer_auto_anon_in_2_a_bits_data; // @[FIFOFixer.scala:50:9]
wire [15:0] fixer_auto_anon_in_2_a_bits_mask; // @[FIFOFixer.scala:50:9]
wire [31:0] fixer_auto_anon_in_2_a_bits_address; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_in_2_a_bits_source; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_in_2_a_bits_size; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_2_a_bits_param; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_2_a_bits_opcode; // @[FIFOFixer.scala:50:9]
wire sbus_clock_groups_auto_out_0_member_sbus_0_reset; // @[ClockGroup.scala:53:9]
wire sbus_clock_groups_auto_out_0_member_sbus_0_clock; // @[ClockGroup.scala:53:9]
wire _coupler_to_bus_named_cbus_auto_widget_anon_in_a_ready; // @[LazyScope.scala:98:27]
wire _coupler_to_bus_named_cbus_auto_widget_anon_in_d_valid; // @[LazyScope.scala:98:27]
wire [2:0] _coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_opcode; // @[LazyScope.scala:98:27]
wire [1:0] _coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_param; // @[LazyScope.scala:98:27]
wire [3:0] _coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_size; // @[LazyScope.scala:98:27]
wire [6:0] _coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_source; // @[LazyScope.scala:98:27]
wire _coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_sink; // @[LazyScope.scala:98:27]
wire _coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_denied; // @[LazyScope.scala:98:27]
wire [127:0] _coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_data; // @[LazyScope.scala:98:27]
wire _coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_corrupt; // @[LazyScope.scala:98:27]
wire _system_bus_xbar_auto_anon_out_0_a_valid; // @[SystemBus.scala:47:43]
wire [2:0] _system_bus_xbar_auto_anon_out_0_a_bits_opcode; // @[SystemBus.scala:47:43]
wire [2:0] _system_bus_xbar_auto_anon_out_0_a_bits_param; // @[SystemBus.scala:47:43]
wire [3:0] _system_bus_xbar_auto_anon_out_0_a_bits_size; // @[SystemBus.scala:47:43]
wire [6:0] _system_bus_xbar_auto_anon_out_0_a_bits_source; // @[SystemBus.scala:47:43]
wire [28:0] _system_bus_xbar_auto_anon_out_0_a_bits_address; // @[SystemBus.scala:47:43]
wire [15:0] _system_bus_xbar_auto_anon_out_0_a_bits_mask; // @[SystemBus.scala:47:43]
wire [127:0] _system_bus_xbar_auto_anon_out_0_a_bits_data; // @[SystemBus.scala:47:43]
wire _system_bus_xbar_auto_anon_out_0_a_bits_corrupt; // @[SystemBus.scala:47:43]
wire _system_bus_xbar_auto_anon_out_0_d_ready; // @[SystemBus.scala:47:43]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_valid_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_opcode_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_param_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_size_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_size; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_source_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_address_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_address; // @[ClockDomain.scala:14:9]
wire [15:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_mask_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_mask; // @[ClockDomain.scala:14:9]
wire [127:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_data_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_data; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_corrupt_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_ready_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_ready; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_valid_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_opcode_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_param_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_size_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_size; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_source_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_address_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_address; // @[ClockDomain.scala:14:9]
wire [127:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_data_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_data; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_corrupt_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_ready_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_ready; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_valid_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_valid; // @[ClockDomain.scala:14:9]
wire [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_bits_sink_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_bits_sink; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_valid_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_opcode_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_param_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_size_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_size; // @[ClockDomain.scala:14:9]
wire [4:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_source_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_address_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_address; // @[ClockDomain.scala:14:9]
wire [15:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_mask_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_mask; // @[ClockDomain.scala:14:9]
wire [127:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_data_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_data; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_corrupt_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_ready_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_ready; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_coh_widget_anon_out_a_ready_0 = auto_coupler_to_bus_named_coh_widget_anon_out_a_ready; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_coh_widget_anon_out_b_valid_0 = auto_coupler_to_bus_named_coh_widget_anon_out_b_valid; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_b_bits_param_0 = auto_coupler_to_bus_named_coh_widget_anon_out_b_bits_param; // @[ClockDomain.scala:14:9]
wire [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_b_bits_address_0 = auto_coupler_to_bus_named_coh_widget_anon_out_b_bits_address; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_coh_widget_anon_out_c_ready_0 = auto_coupler_to_bus_named_coh_widget_anon_out_c_ready; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_coh_widget_anon_out_d_valid_0 = auto_coupler_to_bus_named_coh_widget_anon_out_d_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_opcode_0 = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_opcode; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_param_0 = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_param; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_size_0 = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_size; // @[ClockDomain.scala:14:9]
wire [6:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_source_0 = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_source; // @[ClockDomain.scala:14:9]
wire [3:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_sink_0 = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_sink; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_denied_0 = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_denied; // @[ClockDomain.scala:14:9]
wire [127:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_data_0 = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_data; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_corrupt_0 = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_bus_named_fbus_bus_xing_in_a_valid_0 = auto_coupler_from_bus_named_fbus_bus_xing_in_a_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_opcode_0 = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_param_0 = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_size_0 = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_size; // @[ClockDomain.scala:14:9]
wire [4:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_source_0 = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_address_0 = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_address; // @[ClockDomain.scala:14:9]
wire [7:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_mask_0 = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_mask; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_data_0 = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_data; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_corrupt_0 = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_bus_named_fbus_bus_xing_in_d_ready_0 = auto_coupler_from_bus_named_fbus_bus_xing_in_d_ready; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_cbus_bus_xing_out_a_ready_0 = auto_coupler_to_bus_named_cbus_bus_xing_out_a_ready; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_cbus_bus_xing_out_d_valid_0 = auto_coupler_to_bus_named_cbus_bus_xing_out_d_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_opcode_0 = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_opcode; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_param_0 = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_size_0 = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_size; // @[ClockDomain.scala:14:9]
wire [6:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_source_0 = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_source; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_sink_0 = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_sink; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_denied_0 = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_denied; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_data_0 = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_data; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_corrupt_0 = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_sbus_clock_groups_in_member_sbus_1_clock_0 = auto_sbus_clock_groups_in_member_sbus_1_clock; // @[ClockDomain.scala:14:9]
wire auto_sbus_clock_groups_in_member_sbus_1_reset_0 = auto_sbus_clock_groups_in_member_sbus_1_reset; // @[ClockDomain.scala:14:9]
wire auto_sbus_clock_groups_in_member_sbus_0_clock_0 = auto_sbus_clock_groups_in_member_sbus_0_clock; // @[ClockDomain.scala:14:9]
wire auto_sbus_clock_groups_in_member_sbus_0_reset_0 = auto_sbus_clock_groups_in_member_sbus_0_reset; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_opcode = 3'h6; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_b_bits_opcode = 3'h6; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_b_bits_size = 3'h6; // @[ClockDomain.scala:14:9]
wire [2:0] fixer_auto_anon_in_2_b_bits_opcode = 3'h6; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_2_b_bits_opcode = 3'h6; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_x1_anonOut_1_b_bits_opcode = 3'h6; // @[MixedNode.scala:542:17]
wire [2:0] fixer_x1_anonIn_1_b_bits_opcode = 3'h6; // @[MixedNode.scala:551:17]
wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_b_bits_opcode = 3'h6; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_b_bits_size = 3'h6; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_b_bits_opcode = 3'h6; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_b_bits_size = 3'h6; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_b_bits_opcode = 3'h6; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_b_bits_size = 3'h6; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_b_bits_opcode = 3'h6; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_b_bits_size = 3'h6; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_anonOut_b_bits_opcode = 3'h6; // @[MixedNode.scala:542:17]
wire [2:0] coupler_to_bus_named_coh_widget_anonOut_b_bits_size = 3'h6; // @[MixedNode.scala:542:17]
wire [2:0] coupler_to_bus_named_coh_widget_anonIn_b_bits_opcode = 3'h6; // @[MixedNode.scala:551:17]
wire [2:0] coupler_to_bus_named_coh_widget_anonIn_b_bits_size = 3'h6; // @[MixedNode.scala:551:17]
wire [2:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_1_b_bits_opcode = 3'h6; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_from_rockettile_auto_tl_out_1_b_bits_opcode = 3'h6; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_from_rockettile_x1_tlOut_b_bits_opcode = 3'h6; // @[MixedNode.scala:542:17]
wire [2:0] coupler_from_rockettile_x1_tlIn_b_bits_opcode = 3'h6; // @[MixedNode.scala:551:17]
wire [2:0] coupler_from_rockettile_x1_no_bufferOut_b_bits_opcode = 3'h6; // @[MixedNode.scala:542:17]
wire [2:0] coupler_from_rockettile_x1_no_bufferIn_b_bits_opcode = 3'h6; // @[MixedNode.scala:551:17]
wire [2:0] coupler_from_rockettile_x1_tlMasterClockXingOut_b_bits_opcode = 3'h6; // @[MixedNode.scala:542:17]
wire [2:0] coupler_from_rockettile_x1_tlMasterClockXingIn_b_bits_opcode = 3'h6; // @[MixedNode.scala:551:17]
wire [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_size = 4'h6; // @[ClockDomain.scala:14:9]
wire [3:0] fixer_auto_anon_in_2_b_bits_size = 4'h6; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_out_2_b_bits_size = 4'h6; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_x1_anonOut_1_b_bits_size = 4'h6; // @[MixedNode.scala:542:17]
wire [3:0] fixer_x1_anonIn_1_b_bits_size = 4'h6; // @[MixedNode.scala:551:17]
wire [3:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_1_b_bits_size = 4'h6; // @[LazyModuleImp.scala:138:7]
wire [3:0] coupler_from_rockettile_auto_tl_out_1_b_bits_size = 4'h6; // @[LazyModuleImp.scala:138:7]
wire [3:0] coupler_from_rockettile_x1_tlOut_b_bits_size = 4'h6; // @[MixedNode.scala:542:17]
wire [3:0] coupler_from_rockettile_x1_tlIn_b_bits_size = 4'h6; // @[MixedNode.scala:551:17]
wire [3:0] coupler_from_rockettile_x1_no_bufferOut_b_bits_size = 4'h6; // @[MixedNode.scala:542:17]
wire [3:0] coupler_from_rockettile_x1_no_bufferIn_b_bits_size = 4'h6; // @[MixedNode.scala:551:17]
wire [3:0] coupler_from_rockettile_x1_tlMasterClockXingOut_b_bits_size = 4'h6; // @[MixedNode.scala:542:17]
wire [3:0] coupler_from_rockettile_x1_tlMasterClockXingIn_b_bits_size = 4'h6; // @[MixedNode.scala:551:17]
wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_source = 2'h0; // @[ClockDomain.scala:14:9]
wire [1:0] fixer_auto_anon_in_2_b_bits_source = 2'h0; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_out_2_b_bits_source = 2'h0; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_x1_anonOut_1_b_bits_source = 2'h0; // @[MixedNode.scala:542:17]
wire [1:0] fixer_x1_anonIn_1_b_bits_source = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_1_b_bits_source = 2'h0; // @[LazyModuleImp.scala:138:7]
wire [1:0] coupler_from_rockettile_auto_tl_out_1_b_bits_source = 2'h0; // @[LazyModuleImp.scala:138:7]
wire [1:0] coupler_from_rockettile_x1_tlOut_b_bits_source = 2'h0; // @[MixedNode.scala:542:17]
wire [1:0] coupler_from_rockettile_x1_tlIn_b_bits_source = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] coupler_from_rockettile_x1_no_bufferOut_b_bits_source = 2'h0; // @[MixedNode.scala:542:17]
wire [1:0] coupler_from_rockettile_x1_no_bufferIn_b_bits_source = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] coupler_from_rockettile_x1_tlMasterClockXingOut_b_bits_source = 2'h0; // @[MixedNode.scala:542:17]
wire [1:0] coupler_from_rockettile_x1_tlMasterClockXingIn_b_bits_source = 2'h0; // @[MixedNode.scala:551:17]
wire [15:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_mask = 16'hFFFF; // @[ClockDomain.scala:14:9]
wire [15:0] auto_coupler_to_bus_named_coh_widget_anon_out_b_bits_mask = 16'hFFFF; // @[ClockDomain.scala:14:9]
wire [15:0] fixer_auto_anon_in_2_b_bits_mask = 16'hFFFF; // @[FIFOFixer.scala:50:9]
wire [15:0] fixer_auto_anon_out_2_b_bits_mask = 16'hFFFF; // @[FIFOFixer.scala:50:9]
wire [15:0] fixer_x1_anonOut_1_b_bits_mask = 16'hFFFF; // @[MixedNode.scala:542:17]
wire [15:0] fixer_x1_anonIn_1_b_bits_mask = 16'hFFFF; // @[MixedNode.scala:551:17]
wire [15:0] coupler_to_bus_named_coh_auto_widget_anon_in_b_bits_mask = 16'hFFFF; // @[LazyModuleImp.scala:138:7]
wire [15:0] coupler_to_bus_named_coh_auto_widget_anon_out_b_bits_mask = 16'hFFFF; // @[LazyModuleImp.scala:138:7]
wire [15:0] coupler_to_bus_named_coh_widget_auto_anon_in_b_bits_mask = 16'hFFFF; // @[WidthWidget.scala:27:9]
wire [15:0] coupler_to_bus_named_coh_widget_auto_anon_out_b_bits_mask = 16'hFFFF; // @[WidthWidget.scala:27:9]
wire [15:0] coupler_to_bus_named_coh_widget_anonOut_b_bits_mask = 16'hFFFF; // @[MixedNode.scala:542:17]
wire [15:0] coupler_to_bus_named_coh_widget_anonIn_b_bits_mask = 16'hFFFF; // @[MixedNode.scala:551:17]
wire [15:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_1_b_bits_mask = 16'hFFFF; // @[LazyModuleImp.scala:138:7]
wire [15:0] coupler_from_rockettile_auto_tl_out_1_b_bits_mask = 16'hFFFF; // @[LazyModuleImp.scala:138:7]
wire [15:0] coupler_from_rockettile_x1_tlOut_b_bits_mask = 16'hFFFF; // @[MixedNode.scala:542:17]
wire [15:0] coupler_from_rockettile_x1_tlIn_b_bits_mask = 16'hFFFF; // @[MixedNode.scala:551:17]
wire [15:0] coupler_from_rockettile_x1_no_bufferOut_b_bits_mask = 16'hFFFF; // @[MixedNode.scala:542:17]
wire [15:0] coupler_from_rockettile_x1_no_bufferIn_b_bits_mask = 16'hFFFF; // @[MixedNode.scala:551:17]
wire [15:0] coupler_from_rockettile_x1_tlMasterClockXingOut_b_bits_mask = 16'hFFFF; // @[MixedNode.scala:542:17]
wire [15:0] coupler_from_rockettile_x1_tlMasterClockXingIn_b_bits_mask = 16'hFFFF; // @[MixedNode.scala:551:17]
wire [127:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_data = 128'h0; // @[ClockDomain.scala:14:9]
wire [127:0] auto_coupler_to_bus_named_coh_widget_anon_out_b_bits_data = 128'h0; // @[ClockDomain.scala:14:9]
wire [127:0] fixer_auto_anon_in_2_b_bits_data = 128'h0; // @[FIFOFixer.scala:50:9]
wire [127:0] fixer_auto_anon_out_2_b_bits_data = 128'h0; // @[FIFOFixer.scala:50:9]
wire [127:0] fixer_x1_anonOut_1_b_bits_data = 128'h0; // @[MixedNode.scala:542:17]
wire [127:0] fixer_x1_anonIn_1_b_bits_data = 128'h0; // @[MixedNode.scala:551:17]
wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_in_b_bits_data = 128'h0; // @[LazyModuleImp.scala:138:7]
wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_out_b_bits_data = 128'h0; // @[LazyModuleImp.scala:138:7]
wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_in_b_bits_data = 128'h0; // @[WidthWidget.scala:27:9]
wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_out_b_bits_data = 128'h0; // @[WidthWidget.scala:27:9]
wire [127:0] coupler_to_bus_named_coh_widget_anonOut_b_bits_data = 128'h0; // @[MixedNode.scala:542:17]
wire [127:0] coupler_to_bus_named_coh_widget_anonIn_b_bits_data = 128'h0; // @[MixedNode.scala:551:17]
wire [127:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_1_b_bits_data = 128'h0; // @[LazyModuleImp.scala:138:7]
wire [127:0] coupler_from_rockettile_auto_tl_out_1_b_bits_data = 128'h0; // @[LazyModuleImp.scala:138:7]
wire [127:0] coupler_from_rockettile_x1_tlOut_b_bits_data = 128'h0; // @[MixedNode.scala:542:17]
wire [127:0] coupler_from_rockettile_x1_tlIn_b_bits_data = 128'h0; // @[MixedNode.scala:551:17]
wire [127:0] coupler_from_rockettile_x1_no_bufferOut_b_bits_data = 128'h0; // @[MixedNode.scala:542:17]
wire [127:0] coupler_from_rockettile_x1_no_bufferIn_b_bits_data = 128'h0; // @[MixedNode.scala:551:17]
wire [127:0] coupler_from_rockettile_x1_tlMasterClockXingOut_b_bits_data = 128'h0; // @[MixedNode.scala:542:17]
wire [127:0] coupler_from_rockettile_x1_tlMasterClockXingIn_b_bits_data = 128'h0; // @[MixedNode.scala:551:17]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_coh_widget_anon_out_b_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire sbus_clock_groups_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire sbus_clock_groups_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire sbus_clock_groups__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire clockGroup_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire clockGroup_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire clockGroup__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire broadcast_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire broadcast_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire broadcast__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire fixer_auto_anon_in_2_b_bits_corrupt = 1'h0; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_2_b_bits_corrupt = 1'h0; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonOut_1_b_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire fixer_x1_anonIn_1_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire fixer__a_notFIFO_T_28 = 1'h0; // @[Mux.scala:30:73]
wire fixer_a_noDomain = 1'h0; // @[FIFOFixer.scala:63:29]
wire fixer__flight_WIRE_0 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_1 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_2 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_3 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_4 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_5 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_6 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_7 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_8 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_9 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_10 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_11 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_12 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_13 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_14 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_15 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_16 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__a_notFIFO_T_59 = 1'h0; // @[Mux.scala:30:73]
wire fixer_a_noDomain_1 = 1'h0; // @[FIFOFixer.scala:63:29]
wire fixer__flight_WIRE_1_0 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_1_1 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_1_2 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_1_3 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_1_4 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_1_5 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_1_6 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_1_7 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_1_8 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_1_9 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_1_10 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_1_11 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_1_12 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_1_13 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_1_14 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_1_15 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_1_16 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_1_17 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_1_18 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_1_19 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_1_20 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_1_21 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_1_22 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_1_23 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_1_24 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_1_25 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_1_26 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_1_27 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_1_28 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_1_29 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_1_30 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_1_31 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__a_notFIFO_T_90 = 1'h0; // @[Mux.scala:30:73]
wire fixer_a_noDomain_2 = 1'h0; // @[FIFOFixer.scala:63:29]
wire fixer__flight_WIRE_2_0 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_2_1 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_2_2 = 1'h0; // @[FIFOFixer.scala:79:35]
wire coupler_to_bus_named_coh_auto_widget_anon_in_b_bits_corrupt = 1'h0; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_coh_auto_widget_anon_out_b_bits_corrupt = 1'h0; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_coh_widget_auto_anon_in_b_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_auto_anon_out_b_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonOut_b_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire coupler_to_bus_named_coh_widget_anonIn_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_auto_tl_master_clock_xing_in_1_b_bits_corrupt = 1'h0; // @[LazyModuleImp.scala:138:7]
wire coupler_from_rockettile_auto_tl_out_1_b_bits_corrupt = 1'h0; // @[LazyModuleImp.scala:138:7]
wire coupler_from_rockettile_x1_tlOut_b_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_x1_tlIn_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_x1_no_bufferOut_b_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_x1_no_bufferIn_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_x1_tlMasterClockXingOut_b_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_x1_tlMasterClockXingIn_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_ready = 1'h1; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_coh_widget_anon_out_e_ready = 1'h1; // @[ClockDomain.scala:14:9]
wire fixer_auto_anon_in_2_e_ready = 1'h1; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_2_e_ready = 1'h1; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonOut_1_e_ready = 1'h1; // @[MixedNode.scala:542:17]
wire fixer_x1_anonIn_1_e_ready = 1'h1; // @[MixedNode.scala:551:17]
wire fixer__a_id_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire fixer__anonOut_a_valid_T = 1'h1; // @[FIFOFixer.scala:95:50]
wire fixer__anonOut_a_valid_T_1 = 1'h1; // @[FIFOFixer.scala:95:47]
wire fixer__anonIn_a_ready_T = 1'h1; // @[FIFOFixer.scala:96:50]
wire fixer__anonIn_a_ready_T_1 = 1'h1; // @[FIFOFixer.scala:96:47]
wire fixer__a_id_T_9 = 1'h1; // @[Parameters.scala:137:59]
wire fixer__anonOut_a_valid_T_3 = 1'h1; // @[FIFOFixer.scala:95:50]
wire fixer__anonOut_a_valid_T_4 = 1'h1; // @[FIFOFixer.scala:95:47]
wire fixer__anonIn_a_ready_T_3 = 1'h1; // @[FIFOFixer.scala:96:50]
wire fixer__anonIn_a_ready_T_4 = 1'h1; // @[FIFOFixer.scala:96:47]
wire fixer__a_id_T_14 = 1'h1; // @[Parameters.scala:137:59]
wire fixer__anonOut_a_valid_T_6 = 1'h1; // @[FIFOFixer.scala:95:50]
wire fixer__anonOut_a_valid_T_7 = 1'h1; // @[FIFOFixer.scala:95:47]
wire fixer__anonIn_a_ready_T_6 = 1'h1; // @[FIFOFixer.scala:96:50]
wire fixer__anonIn_a_ready_T_7 = 1'h1; // @[FIFOFixer.scala:96:47]
wire coupler_to_bus_named_coh_auto_widget_anon_in_e_ready = 1'h1; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_coh_auto_widget_anon_out_e_ready = 1'h1; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_coh_widget_auto_anon_in_e_ready = 1'h1; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_auto_anon_out_e_ready = 1'h1; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonOut_e_ready = 1'h1; // @[MixedNode.scala:542:17]
wire coupler_to_bus_named_coh_widget_anonIn_e_ready = 1'h1; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_auto_tl_master_clock_xing_in_1_e_ready = 1'h1; // @[LazyModuleImp.scala:138:7]
wire coupler_from_rockettile_auto_tl_out_1_e_ready = 1'h1; // @[LazyModuleImp.scala:138:7]
wire coupler_from_rockettile_x1_tlOut_e_ready = 1'h1; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_x1_tlIn_e_ready = 1'h1; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_x1_no_bufferOut_e_ready = 1'h1; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_x1_no_bufferIn_e_ready = 1'h1; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_x1_tlMasterClockXingOut_e_ready = 1'h1; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_x1_tlMasterClockXingIn_e_ready = 1'h1; // @[MixedNode.scala:551:17]
wire [6:0] auto_coupler_to_bus_named_coh_widget_anon_out_b_bits_source = 7'h40; // @[ClockDomain.scala:14:9]
wire [6:0] coupler_to_bus_named_coh_auto_widget_anon_in_b_bits_source = 7'h40; // @[LazyModuleImp.scala:138:7]
wire [6:0] coupler_to_bus_named_coh_auto_widget_anon_out_b_bits_source = 7'h40; // @[LazyModuleImp.scala:138:7]
wire [6:0] coupler_to_bus_named_coh_widget_auto_anon_in_b_bits_source = 7'h40; // @[WidthWidget.scala:27:9]
wire [6:0] coupler_to_bus_named_coh_widget_auto_anon_out_b_bits_source = 7'h40; // @[WidthWidget.scala:27:9]
wire [6:0] coupler_to_bus_named_coh_widget_anonOut_b_bits_source = 7'h40; // @[MixedNode.scala:542:17]
wire [6:0] coupler_to_bus_named_coh_widget_anonIn_b_bits_source = 7'h40; // @[MixedNode.scala:551:17]
wire [2:0] fixer__allIDs_FIFOed_T_2 = 3'h7; // @[FIFOFixer.scala:127:48]
wire [31:0] fixer__allIDs_FIFOed_T_1 = 32'hFFFFFFFF; // @[FIFOFixer.scala:127:48]
wire [16:0] fixer__allIDs_FIFOed_T = 17'h1FFFF; // @[FIFOFixer.scala:127:48]
wire [32:0] fixer__a_id_T_2 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] fixer__a_id_T_3 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] fixer__a_id_T_7 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] fixer__a_id_T_8 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] fixer__a_id_T_12 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] fixer__a_id_T_13 = 33'h0; // @[Parameters.scala:137:46]
wire coupler_from_rockettile_auto_tl_master_clock_xing_in_1_a_ready; // @[LazyModuleImp.scala:138:7]
wire coupler_from_rockettile_auto_tl_master_clock_xing_in_1_a_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_valid_0; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_1_a_bits_opcode = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_1_a_bits_param = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_param_0; // @[ClockDomain.scala:14:9]
wire [3:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_1_a_bits_size = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_size_0; // @[ClockDomain.scala:14:9]
wire [1:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_1_a_bits_source = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_source_0; // @[ClockDomain.scala:14:9]
wire [31:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_1_a_bits_address = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_address_0; // @[ClockDomain.scala:14:9]
wire [15:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_1_a_bits_mask = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_mask_0; // @[ClockDomain.scala:14:9]
wire [127:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_1_a_bits_data = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_data_0; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_auto_tl_master_clock_xing_in_1_a_bits_corrupt = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_auto_tl_master_clock_xing_in_1_b_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_ready_0; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_auto_tl_master_clock_xing_in_1_b_valid; // @[LazyModuleImp.scala:138:7]
wire [1:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_1_b_bits_param; // @[LazyModuleImp.scala:138:7]
wire [31:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_1_b_bits_address; // @[LazyModuleImp.scala:138:7]
wire coupler_from_rockettile_auto_tl_master_clock_xing_in_1_c_ready; // @[LazyModuleImp.scala:138:7]
wire coupler_from_rockettile_auto_tl_master_clock_xing_in_1_c_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_valid_0; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_1_c_bits_opcode = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_1_c_bits_param = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_param_0; // @[ClockDomain.scala:14:9]
wire [3:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_1_c_bits_size = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_size_0; // @[ClockDomain.scala:14:9]
wire [1:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_1_c_bits_source = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_source_0; // @[ClockDomain.scala:14:9]
wire [31:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_1_c_bits_address = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_address_0; // @[ClockDomain.scala:14:9]
wire [127:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_1_c_bits_data = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_data_0; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_auto_tl_master_clock_xing_in_1_c_bits_corrupt = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_auto_tl_master_clock_xing_in_1_d_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_ready_0; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_auto_tl_master_clock_xing_in_1_d_valid; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_1_d_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [1:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_1_d_bits_param; // @[LazyModuleImp.scala:138:7]
wire [3:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_1_d_bits_size; // @[LazyModuleImp.scala:138:7]
wire [1:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_1_d_bits_source; // @[LazyModuleImp.scala:138:7]
wire [3:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_1_d_bits_sink; // @[LazyModuleImp.scala:138:7]
wire coupler_from_rockettile_auto_tl_master_clock_xing_in_1_d_bits_denied; // @[LazyModuleImp.scala:138:7]
wire [127:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_1_d_bits_data; // @[LazyModuleImp.scala:138:7]
wire coupler_from_rockettile_auto_tl_master_clock_xing_in_1_d_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire coupler_from_rockettile_auto_tl_master_clock_xing_in_1_e_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_valid_0; // @[ClockDomain.scala:14:9]
wire [3:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_1_e_bits_sink = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_bits_sink_0; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_auto_tl_master_clock_xing_in_0_a_ready; // @[LazyModuleImp.scala:138:7]
wire coupler_from_rockettile_auto_tl_master_clock_xing_in_0_a_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_valid_0; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_0_a_bits_opcode = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_0_a_bits_param = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_param_0; // @[ClockDomain.scala:14:9]
wire [3:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_0_a_bits_size = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_size_0; // @[ClockDomain.scala:14:9]
wire [4:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_0_a_bits_source = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_source_0; // @[ClockDomain.scala:14:9]
wire [31:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_0_a_bits_address = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_address_0; // @[ClockDomain.scala:14:9]
wire [15:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_0_a_bits_mask = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_mask_0; // @[ClockDomain.scala:14:9]
wire [127:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_0_a_bits_data = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_data_0; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_auto_tl_master_clock_xing_in_0_a_bits_corrupt = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_auto_tl_master_clock_xing_in_0_d_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_ready_0; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_auto_tl_master_clock_xing_in_0_d_valid; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_0_d_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [1:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_0_d_bits_param; // @[LazyModuleImp.scala:138:7]
wire [3:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_0_d_bits_size; // @[LazyModuleImp.scala:138:7]
wire [4:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_0_d_bits_source; // @[LazyModuleImp.scala:138:7]
wire [3:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_0_d_bits_sink; // @[LazyModuleImp.scala:138:7]
wire coupler_from_rockettile_auto_tl_master_clock_xing_in_0_d_bits_denied; // @[LazyModuleImp.scala:138:7]
wire [127:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_0_d_bits_data; // @[LazyModuleImp.scala:138:7]
wire coupler_from_rockettile_auto_tl_master_clock_xing_in_0_d_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_coh_auto_widget_anon_out_a_ready = auto_coupler_to_bus_named_coh_widget_anon_out_a_ready_0; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_coh_auto_widget_anon_out_a_valid; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_param; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_size; // @[LazyModuleImp.scala:138:7]
wire [6:0] coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_source; // @[LazyModuleImp.scala:138:7]
wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_address; // @[LazyModuleImp.scala:138:7]
wire [15:0] coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_mask; // @[LazyModuleImp.scala:138:7]
wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_data; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_coh_auto_widget_anon_out_b_ready; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_coh_auto_widget_anon_out_b_valid = auto_coupler_to_bus_named_coh_widget_anon_out_b_valid_0; // @[ClockDomain.scala:14:9]
wire [1:0] coupler_to_bus_named_coh_auto_widget_anon_out_b_bits_param = auto_coupler_to_bus_named_coh_widget_anon_out_b_bits_param_0; // @[ClockDomain.scala:14:9]
wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_out_b_bits_address = auto_coupler_to_bus_named_coh_widget_anon_out_b_bits_address_0; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_coh_auto_widget_anon_out_c_ready = auto_coupler_to_bus_named_coh_widget_anon_out_c_ready_0; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_coh_auto_widget_anon_out_c_valid; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_c_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_c_bits_param; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_c_bits_size; // @[LazyModuleImp.scala:138:7]
wire [6:0] coupler_to_bus_named_coh_auto_widget_anon_out_c_bits_source; // @[LazyModuleImp.scala:138:7]
wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_out_c_bits_address; // @[LazyModuleImp.scala:138:7]
wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_out_c_bits_data; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_coh_auto_widget_anon_out_c_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_coh_auto_widget_anon_out_d_ready; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_coh_auto_widget_anon_out_d_valid = auto_coupler_to_bus_named_coh_widget_anon_out_d_valid_0; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_opcode = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [1:0] coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_param = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_param_0; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_size = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_size_0; // @[ClockDomain.scala:14:9]
wire [6:0] coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_source = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_source_0; // @[ClockDomain.scala:14:9]
wire [3:0] coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_sink = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_sink_0; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_denied = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_denied_0; // @[ClockDomain.scala:14:9]
wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_data = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_data_0; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_corrupt = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_coh_auto_widget_anon_out_e_valid; // @[LazyModuleImp.scala:138:7]
wire [3:0] coupler_to_bus_named_coh_auto_widget_anon_out_e_bits_sink; // @[LazyModuleImp.scala:138:7]
wire sbus_clock_groups_auto_in_member_sbus_1_clock = auto_sbus_clock_groups_in_member_sbus_1_clock_0; // @[ClockGroup.scala:53:9]
wire sbus_clock_groups_auto_in_member_sbus_1_reset = auto_sbus_clock_groups_in_member_sbus_1_reset_0; // @[ClockGroup.scala:53:9]
wire sbus_clock_groups_auto_in_member_sbus_0_clock = auto_sbus_clock_groups_in_member_sbus_0_clock_0; // @[ClockGroup.scala:53:9]
wire sbus_clock_groups_auto_in_member_sbus_0_reset = auto_sbus_clock_groups_in_member_sbus_0_reset_0; // @[ClockGroup.scala:53:9]
wire sbus_clock_groups_auto_out_1_member_coh_0_clock; // @[ClockGroup.scala:53:9]
wire sbus_clock_groups_auto_out_1_member_coh_0_reset; // @[ClockGroup.scala:53:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_ready_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_param_0; // @[ClockDomain.scala:14:9]
wire [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_address_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_valid_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_param_0; // @[ClockDomain.scala:14:9]
wire [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_size_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_source_0; // @[ClockDomain.scala:14:9]
wire [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_sink_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_denied_0; // @[ClockDomain.scala:14:9]
wire [127:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_valid_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_param_0; // @[ClockDomain.scala:14:9]
wire [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_size_0; // @[ClockDomain.scala:14:9]
wire [4:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_source_0; // @[ClockDomain.scala:14:9]
wire [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_sink_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_denied_0; // @[ClockDomain.scala:14:9]
wire [127:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_valid_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
wire [6:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
wire [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
wire [15:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
wire [127:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_coh_widget_anon_out_a_valid_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_coh_widget_anon_out_b_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_param_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_size_0; // @[ClockDomain.scala:14:9]
wire [6:0] auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_source_0; // @[ClockDomain.scala:14:9]
wire [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_address_0; // @[ClockDomain.scala:14:9]
wire [127:0] auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_coh_widget_anon_out_c_valid_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_coh_widget_anon_out_d_ready_0; // @[ClockDomain.scala:14:9]
wire [3:0] auto_coupler_to_bus_named_coh_widget_anon_out_e_bits_sink_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_coh_widget_anon_out_e_valid_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param_0; // @[ClockDomain.scala:14:9]
wire [3:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size_0; // @[ClockDomain.scala:14:9]
wire [4:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source_0; // @[ClockDomain.scala:14:9]
wire [3:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
wire [3:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
wire [6:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
wire [28:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
wire [7:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready_0; // @[ClockDomain.scala:14:9]
wire auto_fixedClockNode_anon_out_2_clock_0; // @[ClockDomain.scala:14:9]
wire auto_fixedClockNode_anon_out_2_reset_0; // @[ClockDomain.scala:14:9]
wire auto_fixedClockNode_anon_out_1_clock_0; // @[ClockDomain.scala:14:9]
wire auto_fixedClockNode_anon_out_1_reset_0; // @[ClockDomain.scala:14:9]
wire auto_fixedClockNode_anon_out_0_clock_0; // @[ClockDomain.scala:14:9]
wire auto_fixedClockNode_anon_out_0_reset_0; // @[ClockDomain.scala:14:9]
wire auto_sbus_clock_groups_out_member_coh_0_clock_0; // @[ClockDomain.scala:14:9]
wire auto_sbus_clock_groups_out_member_coh_0_reset_0; // @[ClockDomain.scala:14:9]
wire clockSinkNodeIn_clock; // @[MixedNode.scala:551:17]
wire clockSinkNodeIn_reset; // @[MixedNode.scala:551:17]
wire childClock; // @[LazyModuleImp.scala:155:31]
wire childReset; // @[LazyModuleImp.scala:158:31]
wire sbus_clock_groups_nodeIn_member_sbus_1_clock = sbus_clock_groups_auto_in_member_sbus_1_clock; // @[ClockGroup.scala:53:9]
wire sbus_clock_groups_nodeIn_member_sbus_1_reset = sbus_clock_groups_auto_in_member_sbus_1_reset; // @[ClockGroup.scala:53:9]
wire sbus_clock_groups_nodeIn_member_sbus_0_clock = sbus_clock_groups_auto_in_member_sbus_0_clock; // @[ClockGroup.scala:53:9]
wire sbus_clock_groups_nodeIn_member_sbus_0_reset = sbus_clock_groups_auto_in_member_sbus_0_reset; // @[ClockGroup.scala:53:9]
wire sbus_clock_groups_x1_nodeOut_member_coh_0_clock; // @[MixedNode.scala:542:17]
assign auto_sbus_clock_groups_out_member_coh_0_clock_0 = sbus_clock_groups_auto_out_1_member_coh_0_clock; // @[ClockGroup.scala:53:9]
wire sbus_clock_groups_x1_nodeOut_member_coh_0_reset; // @[MixedNode.scala:542:17]
assign auto_sbus_clock_groups_out_member_coh_0_reset_0 = sbus_clock_groups_auto_out_1_member_coh_0_reset; // @[ClockGroup.scala:53:9]
wire sbus_clock_groups_nodeOut_member_sbus_0_clock; // @[MixedNode.scala:542:17]
wire sbus_clock_groups_nodeOut_member_sbus_0_reset; // @[MixedNode.scala:542:17]
wire clockGroup_auto_in_member_sbus_0_clock = sbus_clock_groups_auto_out_0_member_sbus_0_clock; // @[ClockGroup.scala:24:9, :53:9]
wire clockGroup_auto_in_member_sbus_0_reset = sbus_clock_groups_auto_out_0_member_sbus_0_reset; // @[ClockGroup.scala:24:9, :53:9]
assign sbus_clock_groups_x1_nodeOut_member_coh_0_clock = sbus_clock_groups_nodeIn_member_sbus_1_clock; // @[MixedNode.scala:542:17, :551:17]
assign sbus_clock_groups_x1_nodeOut_member_coh_0_reset = sbus_clock_groups_nodeIn_member_sbus_1_reset; // @[MixedNode.scala:542:17, :551:17]
assign sbus_clock_groups_nodeOut_member_sbus_0_clock = sbus_clock_groups_nodeIn_member_sbus_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign sbus_clock_groups_nodeOut_member_sbus_0_reset = sbus_clock_groups_nodeIn_member_sbus_0_reset; // @[MixedNode.scala:542:17, :551:17]
assign sbus_clock_groups_auto_out_0_member_sbus_0_clock = sbus_clock_groups_nodeOut_member_sbus_0_clock; // @[ClockGroup.scala:53:9]
assign sbus_clock_groups_auto_out_0_member_sbus_0_reset = sbus_clock_groups_nodeOut_member_sbus_0_reset; // @[ClockGroup.scala:53:9]
assign sbus_clock_groups_auto_out_1_member_coh_0_clock = sbus_clock_groups_x1_nodeOut_member_coh_0_clock; // @[ClockGroup.scala:53:9]
assign sbus_clock_groups_auto_out_1_member_coh_0_reset = sbus_clock_groups_x1_nodeOut_member_coh_0_reset; // @[ClockGroup.scala:53:9]
wire clockGroup_nodeIn_member_sbus_0_clock = clockGroup_auto_in_member_sbus_0_clock; // @[ClockGroup.scala:24:9]
wire clockGroup_nodeOut_clock; // @[MixedNode.scala:542:17]
wire clockGroup_nodeIn_member_sbus_0_reset = clockGroup_auto_in_member_sbus_0_reset; // @[ClockGroup.scala:24:9]
wire clockGroup_nodeOut_reset; // @[MixedNode.scala:542:17]
wire clockGroup_auto_out_clock; // @[ClockGroup.scala:24:9]
wire clockGroup_auto_out_reset; // @[ClockGroup.scala:24:9]
assign clockGroup_auto_out_clock = clockGroup_nodeOut_clock; // @[ClockGroup.scala:24:9]
assign clockGroup_auto_out_reset = clockGroup_nodeOut_reset; // @[ClockGroup.scala:24:9]
assign clockGroup_nodeOut_clock = clockGroup_nodeIn_member_sbus_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign clockGroup_nodeOut_reset = clockGroup_nodeIn_member_sbus_0_reset; // @[MixedNode.scala:542:17, :551:17]
wire fixer_x1_anonIn_1_a_ready; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_auto_tl_out_1_a_ready = fixer_auto_anon_in_2_a_ready; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_auto_tl_out_1_a_valid; // @[LazyModuleImp.scala:138:7]
wire fixer_x1_anonIn_1_a_valid = fixer_auto_anon_in_2_a_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] coupler_from_rockettile_auto_tl_out_1_a_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [2:0] fixer_x1_anonIn_1_a_bits_opcode = fixer_auto_anon_in_2_a_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [2:0] coupler_from_rockettile_auto_tl_out_1_a_bits_param; // @[LazyModuleImp.scala:138:7]
wire [2:0] fixer_x1_anonIn_1_a_bits_param = fixer_auto_anon_in_2_a_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] coupler_from_rockettile_auto_tl_out_1_a_bits_size; // @[LazyModuleImp.scala:138:7]
wire [3:0] fixer_x1_anonIn_1_a_bits_size = fixer_auto_anon_in_2_a_bits_size; // @[FIFOFixer.scala:50:9]
wire [1:0] coupler_from_rockettile_auto_tl_out_1_a_bits_source; // @[LazyModuleImp.scala:138:7]
wire [1:0] fixer_x1_anonIn_1_a_bits_source = fixer_auto_anon_in_2_a_bits_source; // @[FIFOFixer.scala:50:9]
wire [31:0] coupler_from_rockettile_auto_tl_out_1_a_bits_address; // @[LazyModuleImp.scala:138:7]
wire [31:0] fixer_x1_anonIn_1_a_bits_address = fixer_auto_anon_in_2_a_bits_address; // @[FIFOFixer.scala:50:9]
wire [15:0] coupler_from_rockettile_auto_tl_out_1_a_bits_mask; // @[LazyModuleImp.scala:138:7]
wire [15:0] fixer_x1_anonIn_1_a_bits_mask = fixer_auto_anon_in_2_a_bits_mask; // @[FIFOFixer.scala:50:9]
wire [127:0] coupler_from_rockettile_auto_tl_out_1_a_bits_data; // @[LazyModuleImp.scala:138:7]
wire [127:0] fixer_x1_anonIn_1_a_bits_data = fixer_auto_anon_in_2_a_bits_data; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_auto_tl_out_1_a_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire fixer_x1_anonIn_1_a_bits_corrupt = fixer_auto_anon_in_2_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_auto_tl_out_1_b_ready; // @[LazyModuleImp.scala:138:7]
wire fixer_x1_anonIn_1_b_ready = fixer_auto_anon_in_2_b_ready; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonIn_1_b_valid; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_auto_tl_out_1_b_valid = fixer_auto_anon_in_2_b_valid; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_x1_anonIn_1_b_bits_param; // @[MixedNode.scala:551:17]
wire [1:0] coupler_from_rockettile_auto_tl_out_1_b_bits_param = fixer_auto_anon_in_2_b_bits_param; // @[FIFOFixer.scala:50:9]
wire [31:0] fixer_x1_anonIn_1_b_bits_address; // @[MixedNode.scala:551:17]
wire [31:0] coupler_from_rockettile_auto_tl_out_1_b_bits_address = fixer_auto_anon_in_2_b_bits_address; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonIn_1_c_ready; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_auto_tl_out_1_c_ready = fixer_auto_anon_in_2_c_ready; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_auto_tl_out_1_c_valid; // @[LazyModuleImp.scala:138:7]
wire fixer_x1_anonIn_1_c_valid = fixer_auto_anon_in_2_c_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] coupler_from_rockettile_auto_tl_out_1_c_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [2:0] fixer_x1_anonIn_1_c_bits_opcode = fixer_auto_anon_in_2_c_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [2:0] coupler_from_rockettile_auto_tl_out_1_c_bits_param; // @[LazyModuleImp.scala:138:7]
wire [2:0] fixer_x1_anonIn_1_c_bits_param = fixer_auto_anon_in_2_c_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] coupler_from_rockettile_auto_tl_out_1_c_bits_size; // @[LazyModuleImp.scala:138:7]
wire [3:0] fixer_x1_anonIn_1_c_bits_size = fixer_auto_anon_in_2_c_bits_size; // @[FIFOFixer.scala:50:9]
wire [1:0] coupler_from_rockettile_auto_tl_out_1_c_bits_source; // @[LazyModuleImp.scala:138:7]
wire [1:0] fixer_x1_anonIn_1_c_bits_source = fixer_auto_anon_in_2_c_bits_source; // @[FIFOFixer.scala:50:9]
wire [31:0] coupler_from_rockettile_auto_tl_out_1_c_bits_address; // @[LazyModuleImp.scala:138:7]
wire [31:0] fixer_x1_anonIn_1_c_bits_address = fixer_auto_anon_in_2_c_bits_address; // @[FIFOFixer.scala:50:9]
wire [127:0] coupler_from_rockettile_auto_tl_out_1_c_bits_data; // @[LazyModuleImp.scala:138:7]
wire [127:0] fixer_x1_anonIn_1_c_bits_data = fixer_auto_anon_in_2_c_bits_data; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_auto_tl_out_1_c_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire fixer_x1_anonIn_1_c_bits_corrupt = fixer_auto_anon_in_2_c_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_auto_tl_out_1_d_ready; // @[LazyModuleImp.scala:138:7]
wire fixer_x1_anonIn_1_d_ready = fixer_auto_anon_in_2_d_ready; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonIn_1_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] fixer_x1_anonIn_1_d_bits_opcode; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_auto_tl_out_1_d_valid = fixer_auto_anon_in_2_d_valid; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_x1_anonIn_1_d_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] coupler_from_rockettile_auto_tl_out_1_d_bits_opcode = fixer_auto_anon_in_2_d_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_x1_anonIn_1_d_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] coupler_from_rockettile_auto_tl_out_1_d_bits_param = fixer_auto_anon_in_2_d_bits_param; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_x1_anonIn_1_d_bits_source; // @[MixedNode.scala:551:17]
wire [3:0] coupler_from_rockettile_auto_tl_out_1_d_bits_size = fixer_auto_anon_in_2_d_bits_size; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_x1_anonIn_1_d_bits_sink; // @[MixedNode.scala:551:17]
wire [1:0] coupler_from_rockettile_auto_tl_out_1_d_bits_source = fixer_auto_anon_in_2_d_bits_source; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonIn_1_d_bits_denied; // @[MixedNode.scala:551:17]
wire [3:0] coupler_from_rockettile_auto_tl_out_1_d_bits_sink = fixer_auto_anon_in_2_d_bits_sink; // @[FIFOFixer.scala:50:9]
wire [127:0] fixer_x1_anonIn_1_d_bits_data; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_auto_tl_out_1_d_bits_denied = fixer_auto_anon_in_2_d_bits_denied; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonIn_1_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire [127:0] coupler_from_rockettile_auto_tl_out_1_d_bits_data = fixer_auto_anon_in_2_d_bits_data; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_auto_tl_out_1_d_bits_corrupt = fixer_auto_anon_in_2_d_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_auto_tl_out_1_e_valid; // @[LazyModuleImp.scala:138:7]
wire fixer_x1_anonIn_1_e_valid = fixer_auto_anon_in_2_e_valid; // @[FIFOFixer.scala:50:9]
wire [3:0] coupler_from_rockettile_auto_tl_out_1_e_bits_sink; // @[LazyModuleImp.scala:138:7]
wire fixer_x1_anonIn_a_ready; // @[MixedNode.scala:551:17]
wire [3:0] fixer_x1_anonIn_1_e_bits_sink = fixer_auto_anon_in_2_e_bits_sink; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_auto_tl_out_0_a_ready = fixer_auto_anon_in_1_a_ready; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_auto_tl_out_0_a_valid; // @[LazyModuleImp.scala:138:7]
wire fixer_x1_anonIn_a_valid = fixer_auto_anon_in_1_a_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] coupler_from_rockettile_auto_tl_out_0_a_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [2:0] fixer_x1_anonIn_a_bits_opcode = fixer_auto_anon_in_1_a_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [2:0] coupler_from_rockettile_auto_tl_out_0_a_bits_param; // @[LazyModuleImp.scala:138:7]
wire [2:0] fixer_x1_anonIn_a_bits_param = fixer_auto_anon_in_1_a_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] coupler_from_rockettile_auto_tl_out_0_a_bits_size; // @[LazyModuleImp.scala:138:7]
wire [3:0] fixer_x1_anonIn_a_bits_size = fixer_auto_anon_in_1_a_bits_size; // @[FIFOFixer.scala:50:9]
wire [4:0] coupler_from_rockettile_auto_tl_out_0_a_bits_source; // @[LazyModuleImp.scala:138:7]
wire [4:0] fixer_x1_anonIn_a_bits_source = fixer_auto_anon_in_1_a_bits_source; // @[FIFOFixer.scala:50:9]
wire [31:0] coupler_from_rockettile_auto_tl_out_0_a_bits_address; // @[LazyModuleImp.scala:138:7]
wire [31:0] fixer_x1_anonIn_a_bits_address = fixer_auto_anon_in_1_a_bits_address; // @[FIFOFixer.scala:50:9]
wire [15:0] coupler_from_rockettile_auto_tl_out_0_a_bits_mask; // @[LazyModuleImp.scala:138:7]
wire [15:0] fixer_x1_anonIn_a_bits_mask = fixer_auto_anon_in_1_a_bits_mask; // @[FIFOFixer.scala:50:9]
wire [127:0] coupler_from_rockettile_auto_tl_out_0_a_bits_data; // @[LazyModuleImp.scala:138:7]
wire [127:0] fixer_x1_anonIn_a_bits_data = fixer_auto_anon_in_1_a_bits_data; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_auto_tl_out_0_a_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire fixer_x1_anonIn_a_bits_corrupt = fixer_auto_anon_in_1_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_auto_tl_out_0_d_ready; // @[LazyModuleImp.scala:138:7]
wire fixer_x1_anonIn_d_ready = fixer_auto_anon_in_1_d_ready; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] fixer_x1_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_auto_tl_out_0_d_valid = fixer_auto_anon_in_1_d_valid; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_x1_anonIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] coupler_from_rockettile_auto_tl_out_0_d_bits_opcode = fixer_auto_anon_in_1_d_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_x1_anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] coupler_from_rockettile_auto_tl_out_0_d_bits_param = fixer_auto_anon_in_1_d_bits_param; // @[FIFOFixer.scala:50:9]
wire [4:0] fixer_x1_anonIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [3:0] coupler_from_rockettile_auto_tl_out_0_d_bits_size = fixer_auto_anon_in_1_d_bits_size; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_x1_anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire [4:0] coupler_from_rockettile_auto_tl_out_0_d_bits_source = fixer_auto_anon_in_1_d_bits_source; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [3:0] coupler_from_rockettile_auto_tl_out_0_d_bits_sink = fixer_auto_anon_in_1_d_bits_sink; // @[FIFOFixer.scala:50:9]
wire [127:0] fixer_x1_anonIn_d_bits_data; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_auto_tl_out_0_d_bits_denied = fixer_auto_anon_in_1_d_bits_denied; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire [127:0] coupler_from_rockettile_auto_tl_out_0_d_bits_data = fixer_auto_anon_in_1_d_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_anonIn_a_ready; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_auto_tl_out_0_d_bits_corrupt = fixer_auto_anon_in_1_d_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire fixer_anonIn_a_valid = fixer_auto_anon_in_0_a_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_anonIn_a_bits_opcode = fixer_auto_anon_in_0_a_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_anonIn_a_bits_param = fixer_auto_anon_in_0_a_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_anonIn_a_bits_size = fixer_auto_anon_in_0_a_bits_size; // @[FIFOFixer.scala:50:9]
wire [4:0] fixer_anonIn_a_bits_source = fixer_auto_anon_in_0_a_bits_source; // @[FIFOFixer.scala:50:9]
wire [31:0] fixer_anonIn_a_bits_address = fixer_auto_anon_in_0_a_bits_address; // @[FIFOFixer.scala:50:9]
wire [15:0] fixer_anonIn_a_bits_mask = fixer_auto_anon_in_0_a_bits_mask; // @[FIFOFixer.scala:50:9]
wire [127:0] fixer_anonIn_a_bits_data = fixer_auto_anon_in_0_a_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_anonIn_a_bits_corrupt = fixer_auto_anon_in_0_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire fixer_anonIn_d_ready = fixer_auto_anon_in_0_d_ready; // @[FIFOFixer.scala:50:9]
wire fixer_anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] fixer_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] fixer_anonIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] fixer_anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [4:0] fixer_anonIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [3:0] fixer_anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire fixer_anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [127:0] fixer_anonIn_d_bits_data; // @[MixedNode.scala:551:17]
wire fixer_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire fixer_x1_anonOut_1_a_ready = fixer_auto_anon_out_2_a_ready; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonOut_1_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] fixer_x1_anonOut_1_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] fixer_x1_anonOut_1_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] fixer_x1_anonOut_1_a_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] fixer_x1_anonOut_1_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] fixer_x1_anonOut_1_a_bits_address; // @[MixedNode.scala:542:17]
wire [15:0] fixer_x1_anonOut_1_a_bits_mask; // @[MixedNode.scala:542:17]
wire [127:0] fixer_x1_anonOut_1_a_bits_data; // @[MixedNode.scala:542:17]
wire fixer_x1_anonOut_1_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire fixer_x1_anonOut_1_b_ready; // @[MixedNode.scala:542:17]
wire fixer_x1_anonOut_1_b_valid = fixer_auto_anon_out_2_b_valid; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_x1_anonOut_1_b_bits_param = fixer_auto_anon_out_2_b_bits_param; // @[FIFOFixer.scala:50:9]
wire [31:0] fixer_x1_anonOut_1_b_bits_address = fixer_auto_anon_out_2_b_bits_address; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonOut_1_c_ready = fixer_auto_anon_out_2_c_ready; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonOut_1_c_valid; // @[MixedNode.scala:542:17]
wire [2:0] fixer_x1_anonOut_1_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] fixer_x1_anonOut_1_c_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] fixer_x1_anonOut_1_c_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] fixer_x1_anonOut_1_c_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] fixer_x1_anonOut_1_c_bits_address; // @[MixedNode.scala:542:17]
wire [127:0] fixer_x1_anonOut_1_c_bits_data; // @[MixedNode.scala:542:17]
wire fixer_x1_anonOut_1_c_bits_corrupt; // @[MixedNode.scala:542:17]
wire fixer_x1_anonOut_1_d_ready; // @[MixedNode.scala:542:17]
wire fixer_x1_anonOut_1_d_valid = fixer_auto_anon_out_2_d_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_x1_anonOut_1_d_bits_opcode = fixer_auto_anon_out_2_d_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_x1_anonOut_1_d_bits_param = fixer_auto_anon_out_2_d_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_x1_anonOut_1_d_bits_size = fixer_auto_anon_out_2_d_bits_size; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_x1_anonOut_1_d_bits_source = fixer_auto_anon_out_2_d_bits_source; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_x1_anonOut_1_d_bits_sink = fixer_auto_anon_out_2_d_bits_sink; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonOut_1_d_bits_denied = fixer_auto_anon_out_2_d_bits_denied; // @[FIFOFixer.scala:50:9]
wire [127:0] fixer_x1_anonOut_1_d_bits_data = fixer_auto_anon_out_2_d_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonOut_1_d_bits_corrupt = fixer_auto_anon_out_2_d_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonOut_1_e_valid; // @[MixedNode.scala:542:17]
wire [3:0] fixer_x1_anonOut_1_e_bits_sink; // @[MixedNode.scala:542:17]
wire fixer_x1_anonOut_a_ready = fixer_auto_anon_out_1_a_ready; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] fixer_x1_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] fixer_x1_anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] fixer_x1_anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [4:0] fixer_x1_anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] fixer_x1_anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [15:0] fixer_x1_anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [127:0] fixer_x1_anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire fixer_x1_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire fixer_x1_anonOut_d_ready; // @[MixedNode.scala:542:17]
wire fixer_x1_anonOut_d_valid = fixer_auto_anon_out_1_d_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_x1_anonOut_d_bits_opcode = fixer_auto_anon_out_1_d_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_x1_anonOut_d_bits_param = fixer_auto_anon_out_1_d_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_x1_anonOut_d_bits_size = fixer_auto_anon_out_1_d_bits_size; // @[FIFOFixer.scala:50:9]
wire [4:0] fixer_x1_anonOut_d_bits_source = fixer_auto_anon_out_1_d_bits_source; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_x1_anonOut_d_bits_sink = fixer_auto_anon_out_1_d_bits_sink; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonOut_d_bits_denied = fixer_auto_anon_out_1_d_bits_denied; // @[FIFOFixer.scala:50:9]
wire [127:0] fixer_x1_anonOut_d_bits_data = fixer_auto_anon_out_1_d_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonOut_d_bits_corrupt = fixer_auto_anon_out_1_d_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire fixer_anonOut_a_ready = fixer_auto_anon_out_0_a_ready; // @[FIFOFixer.scala:50:9]
wire fixer_anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] fixer_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] fixer_anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] fixer_anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [4:0] fixer_anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] fixer_anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [15:0] fixer_anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [127:0] fixer_anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire fixer_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire fixer_anonOut_d_ready; // @[MixedNode.scala:542:17]
wire fixer_anonOut_d_valid = fixer_auto_anon_out_0_d_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_anonOut_d_bits_opcode = fixer_auto_anon_out_0_d_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_anonOut_d_bits_param = fixer_auto_anon_out_0_d_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_anonOut_d_bits_size = fixer_auto_anon_out_0_d_bits_size; // @[FIFOFixer.scala:50:9]
wire [4:0] fixer_anonOut_d_bits_source = fixer_auto_anon_out_0_d_bits_source; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_anonOut_d_bits_sink = fixer_auto_anon_out_0_d_bits_sink; // @[FIFOFixer.scala:50:9]
wire fixer_anonOut_d_bits_denied = fixer_auto_anon_out_0_d_bits_denied; // @[FIFOFixer.scala:50:9]
wire [127:0] fixer_anonOut_d_bits_data = fixer_auto_anon_out_0_d_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_anonOut_d_bits_corrupt = fixer_auto_anon_out_0_d_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_0_a_ready; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_0_d_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_in_0_d_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_in_0_d_bits_size; // @[FIFOFixer.scala:50:9]
wire [4:0] fixer_auto_anon_in_0_d_bits_source; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_in_0_d_bits_sink; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_0_d_bits_denied; // @[FIFOFixer.scala:50:9]
wire [127:0] fixer_auto_anon_in_0_d_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_0_d_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_0_d_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_2_a_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_2_a_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_out_2_a_bits_size; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_out_2_a_bits_source; // @[FIFOFixer.scala:50:9]
wire [31:0] fixer_auto_anon_out_2_a_bits_address; // @[FIFOFixer.scala:50:9]
wire [15:0] fixer_auto_anon_out_2_a_bits_mask; // @[FIFOFixer.scala:50:9]
wire [127:0] fixer_auto_anon_out_2_a_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_2_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_2_a_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_2_b_ready; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_2_c_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_2_c_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_out_2_c_bits_size; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_out_2_c_bits_source; // @[FIFOFixer.scala:50:9]
wire [31:0] fixer_auto_anon_out_2_c_bits_address; // @[FIFOFixer.scala:50:9]
wire [127:0] fixer_auto_anon_out_2_c_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_2_c_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_2_c_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_2_d_ready; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_out_2_e_bits_sink; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_2_e_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_1_a_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_1_a_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_out_1_a_bits_size; // @[FIFOFixer.scala:50:9]
wire [4:0] fixer_auto_anon_out_1_a_bits_source; // @[FIFOFixer.scala:50:9]
wire [31:0] fixer_auto_anon_out_1_a_bits_address; // @[FIFOFixer.scala:50:9]
wire [15:0] fixer_auto_anon_out_1_a_bits_mask; // @[FIFOFixer.scala:50:9]
wire [127:0] fixer_auto_anon_out_1_a_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_1_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_1_a_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_1_d_ready; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_0_a_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_0_a_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_out_0_a_bits_size; // @[FIFOFixer.scala:50:9]
wire [4:0] fixer_auto_anon_out_0_a_bits_source; // @[FIFOFixer.scala:50:9]
wire [31:0] fixer_auto_anon_out_0_a_bits_address; // @[FIFOFixer.scala:50:9]
wire [15:0] fixer_auto_anon_out_0_a_bits_mask; // @[FIFOFixer.scala:50:9]
wire [127:0] fixer_auto_anon_out_0_a_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_0_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_0_a_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_0_d_ready; // @[FIFOFixer.scala:50:9]
wire fixer__anonOut_a_valid_T_2; // @[FIFOFixer.scala:95:33]
wire fixer__anonIn_a_ready_T_2 = fixer_anonOut_a_ready; // @[FIFOFixer.scala:96:33]
assign fixer_auto_anon_out_0_a_valid = fixer_anonOut_a_valid; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_0_a_bits_opcode = fixer_anonOut_a_bits_opcode; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_0_a_bits_param = fixer_anonOut_a_bits_param; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_0_a_bits_size = fixer_anonOut_a_bits_size; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_0_a_bits_source = fixer_anonOut_a_bits_source; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_0_a_bits_address = fixer_anonOut_a_bits_address; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_0_a_bits_mask = fixer_anonOut_a_bits_mask; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_0_a_bits_data = fixer_anonOut_a_bits_data; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_0_a_bits_corrupt = fixer_anonOut_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_0_d_ready = fixer_anonOut_d_ready; // @[FIFOFixer.scala:50:9]
assign fixer_anonIn_d_valid = fixer_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_d_bits_opcode = fixer_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_d_bits_param = fixer_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_d_bits_size = fixer_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_d_bits_source = fixer_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_d_bits_sink = fixer_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_d_bits_denied = fixer_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_d_bits_data = fixer_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_d_bits_corrupt = fixer_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire fixer__anonOut_a_valid_T_5; // @[FIFOFixer.scala:95:33]
wire fixer__anonIn_a_ready_T_5 = fixer_x1_anonOut_a_ready; // @[FIFOFixer.scala:96:33]
assign fixer_auto_anon_out_1_a_valid = fixer_x1_anonOut_a_valid; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_1_a_bits_opcode = fixer_x1_anonOut_a_bits_opcode; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_1_a_bits_param = fixer_x1_anonOut_a_bits_param; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_1_a_bits_size = fixer_x1_anonOut_a_bits_size; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_1_a_bits_source = fixer_x1_anonOut_a_bits_source; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_1_a_bits_address = fixer_x1_anonOut_a_bits_address; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_1_a_bits_mask = fixer_x1_anonOut_a_bits_mask; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_1_a_bits_data = fixer_x1_anonOut_a_bits_data; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_1_a_bits_corrupt = fixer_x1_anonOut_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_1_d_ready = fixer_x1_anonOut_d_ready; // @[FIFOFixer.scala:50:9]
assign fixer_x1_anonIn_d_valid = fixer_x1_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_d_bits_opcode = fixer_x1_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_d_bits_param = fixer_x1_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_d_bits_size = fixer_x1_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_d_bits_source = fixer_x1_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_d_bits_sink = fixer_x1_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_d_bits_denied = fixer_x1_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_d_bits_data = fixer_x1_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_d_bits_corrupt = fixer_x1_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire fixer__anonOut_a_valid_T_8; // @[FIFOFixer.scala:95:33]
wire fixer__anonIn_a_ready_T_8 = fixer_x1_anonOut_1_a_ready; // @[FIFOFixer.scala:96:33]
assign fixer_auto_anon_out_2_a_valid = fixer_x1_anonOut_1_a_valid; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_2_a_bits_opcode = fixer_x1_anonOut_1_a_bits_opcode; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_2_a_bits_param = fixer_x1_anonOut_1_a_bits_param; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_2_a_bits_size = fixer_x1_anonOut_1_a_bits_size; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_2_a_bits_source = fixer_x1_anonOut_1_a_bits_source; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_2_a_bits_address = fixer_x1_anonOut_1_a_bits_address; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_2_a_bits_mask = fixer_x1_anonOut_1_a_bits_mask; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_2_a_bits_data = fixer_x1_anonOut_1_a_bits_data; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_2_a_bits_corrupt = fixer_x1_anonOut_1_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_2_b_ready = fixer_x1_anonOut_1_b_ready; // @[FIFOFixer.scala:50:9]
assign fixer_x1_anonIn_1_b_valid = fixer_x1_anonOut_1_b_valid; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_1_b_bits_param = fixer_x1_anonOut_1_b_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_1_b_bits_address = fixer_x1_anonOut_1_b_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_1_c_ready = fixer_x1_anonOut_1_c_ready; // @[MixedNode.scala:542:17, :551:17]
assign fixer_auto_anon_out_2_c_valid = fixer_x1_anonOut_1_c_valid; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_2_c_bits_opcode = fixer_x1_anonOut_1_c_bits_opcode; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_2_c_bits_param = fixer_x1_anonOut_1_c_bits_param; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_2_c_bits_size = fixer_x1_anonOut_1_c_bits_size; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_2_c_bits_source = fixer_x1_anonOut_1_c_bits_source; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_2_c_bits_address = fixer_x1_anonOut_1_c_bits_address; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_2_c_bits_data = fixer_x1_anonOut_1_c_bits_data; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_2_c_bits_corrupt = fixer_x1_anonOut_1_c_bits_corrupt; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_2_d_ready = fixer_x1_anonOut_1_d_ready; // @[FIFOFixer.scala:50:9]
assign fixer_x1_anonIn_1_d_valid = fixer_x1_anonOut_1_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_1_d_bits_opcode = fixer_x1_anonOut_1_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_1_d_bits_param = fixer_x1_anonOut_1_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_1_d_bits_size = fixer_x1_anonOut_1_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_1_d_bits_source = fixer_x1_anonOut_1_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_1_d_bits_sink = fixer_x1_anonOut_1_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_1_d_bits_denied = fixer_x1_anonOut_1_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_1_d_bits_data = fixer_x1_anonOut_1_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_1_d_bits_corrupt = fixer_x1_anonOut_1_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign fixer_auto_anon_out_2_e_valid = fixer_x1_anonOut_1_e_valid; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_2_e_bits_sink = fixer_x1_anonOut_1_e_bits_sink; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_0_a_ready = fixer_anonIn_a_ready; // @[FIFOFixer.scala:50:9]
assign fixer__anonOut_a_valid_T_2 = fixer_anonIn_a_valid; // @[FIFOFixer.scala:95:33]
assign fixer_anonOut_a_bits_opcode = fixer_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_a_bits_param = fixer_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_a_bits_size = fixer_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_a_bits_source = fixer_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_a_bits_address = fixer_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] fixer__a_notFIFO_T = fixer_anonIn_a_bits_address; // @[Parameters.scala:137:31]
wire [31:0] fixer__a_id_T = fixer_anonIn_a_bits_address; // @[Parameters.scala:137:31]
assign fixer_anonOut_a_bits_mask = fixer_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_a_bits_data = fixer_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_a_bits_corrupt = fixer_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_d_ready = fixer_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign fixer_auto_anon_in_0_d_valid = fixer_anonIn_d_valid; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_0_d_bits_opcode = fixer_anonIn_d_bits_opcode; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_0_d_bits_param = fixer_anonIn_d_bits_param; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_0_d_bits_size = fixer_anonIn_d_bits_size; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_0_d_bits_source = fixer_anonIn_d_bits_source; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_0_d_bits_sink = fixer_anonIn_d_bits_sink; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_0_d_bits_denied = fixer_anonIn_d_bits_denied; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_0_d_bits_data = fixer_anonIn_d_bits_data; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_0_d_bits_corrupt = fixer_anonIn_d_bits_corrupt; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_1_a_ready = fixer_x1_anonIn_a_ready; // @[FIFOFixer.scala:50:9]
assign fixer__anonOut_a_valid_T_5 = fixer_x1_anonIn_a_valid; // @[FIFOFixer.scala:95:33]
assign fixer_x1_anonOut_a_bits_opcode = fixer_x1_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_a_bits_param = fixer_x1_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_a_bits_size = fixer_x1_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_a_bits_source = fixer_x1_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_a_bits_address = fixer_x1_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] fixer__a_notFIFO_T_31 = fixer_x1_anonIn_a_bits_address; // @[Parameters.scala:137:31]
wire [31:0] fixer__a_id_T_5 = fixer_x1_anonIn_a_bits_address; // @[Parameters.scala:137:31]
assign fixer_x1_anonOut_a_bits_mask = fixer_x1_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_a_bits_data = fixer_x1_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_a_bits_corrupt = fixer_x1_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_d_ready = fixer_x1_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign fixer_auto_anon_in_1_d_valid = fixer_x1_anonIn_d_valid; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_1_d_bits_opcode = fixer_x1_anonIn_d_bits_opcode; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_1_d_bits_param = fixer_x1_anonIn_d_bits_param; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_1_d_bits_size = fixer_x1_anonIn_d_bits_size; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_1_d_bits_source = fixer_x1_anonIn_d_bits_source; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_1_d_bits_sink = fixer_x1_anonIn_d_bits_sink; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_1_d_bits_denied = fixer_x1_anonIn_d_bits_denied; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_1_d_bits_data = fixer_x1_anonIn_d_bits_data; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_1_d_bits_corrupt = fixer_x1_anonIn_d_bits_corrupt; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_2_a_ready = fixer_x1_anonIn_1_a_ready; // @[FIFOFixer.scala:50:9]
assign fixer__anonOut_a_valid_T_8 = fixer_x1_anonIn_1_a_valid; // @[FIFOFixer.scala:95:33]
assign fixer_x1_anonOut_1_a_bits_opcode = fixer_x1_anonIn_1_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_1_a_bits_param = fixer_x1_anonIn_1_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_1_a_bits_size = fixer_x1_anonIn_1_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_1_a_bits_source = fixer_x1_anonIn_1_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_1_a_bits_address = fixer_x1_anonIn_1_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] fixer__a_notFIFO_T_62 = fixer_x1_anonIn_1_a_bits_address; // @[Parameters.scala:137:31]
wire [31:0] fixer__a_id_T_10 = fixer_x1_anonIn_1_a_bits_address; // @[Parameters.scala:137:31]
assign fixer_x1_anonOut_1_a_bits_mask = fixer_x1_anonIn_1_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_1_a_bits_data = fixer_x1_anonIn_1_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_1_a_bits_corrupt = fixer_x1_anonIn_1_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_1_b_ready = fixer_x1_anonIn_1_b_ready; // @[MixedNode.scala:542:17, :551:17]
assign fixer_auto_anon_in_2_b_valid = fixer_x1_anonIn_1_b_valid; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_2_b_bits_param = fixer_x1_anonIn_1_b_bits_param; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_2_b_bits_address = fixer_x1_anonIn_1_b_bits_address; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_2_c_ready = fixer_x1_anonIn_1_c_ready; // @[FIFOFixer.scala:50:9]
assign fixer_x1_anonOut_1_c_valid = fixer_x1_anonIn_1_c_valid; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_1_c_bits_opcode = fixer_x1_anonIn_1_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_1_c_bits_param = fixer_x1_anonIn_1_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_1_c_bits_size = fixer_x1_anonIn_1_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_1_c_bits_source = fixer_x1_anonIn_1_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_1_c_bits_address = fixer_x1_anonIn_1_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_1_c_bits_data = fixer_x1_anonIn_1_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_1_c_bits_corrupt = fixer_x1_anonIn_1_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_1_d_ready = fixer_x1_anonIn_1_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign fixer_auto_anon_in_2_d_valid = fixer_x1_anonIn_1_d_valid; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_2_d_bits_opcode = fixer_x1_anonIn_1_d_bits_opcode; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_2_d_bits_param = fixer_x1_anonIn_1_d_bits_param; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_2_d_bits_size = fixer_x1_anonIn_1_d_bits_size; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_2_d_bits_source = fixer_x1_anonIn_1_d_bits_source; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_2_d_bits_sink = fixer_x1_anonIn_1_d_bits_sink; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_2_d_bits_denied = fixer_x1_anonIn_1_d_bits_denied; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_2_d_bits_data = fixer_x1_anonIn_1_d_bits_data; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_2_d_bits_corrupt = fixer_x1_anonIn_1_d_bits_corrupt; // @[FIFOFixer.scala:50:9]
assign fixer_x1_anonOut_1_e_valid = fixer_x1_anonIn_1_e_valid; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_1_e_bits_sink = fixer_x1_anonIn_1_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire [32:0] fixer__a_notFIFO_T_1 = {1'h0, fixer__a_notFIFO_T}; // @[Parameters.scala:137:{31,41}]
wire [32:0] fixer__a_notFIFO_T_2 = fixer__a_notFIFO_T_1 & 33'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] fixer__a_notFIFO_T_3 = fixer__a_notFIFO_T_2; // @[Parameters.scala:137:46]
wire fixer__a_notFIFO_T_4 = fixer__a_notFIFO_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] fixer__a_notFIFO_T_5 = {fixer_anonIn_a_bits_address[31:17], fixer_anonIn_a_bits_address[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31]
wire [32:0] fixer__a_notFIFO_T_6 = {1'h0, fixer__a_notFIFO_T_5}; // @[Parameters.scala:137:{31,41}]
wire [32:0] fixer__a_notFIFO_T_7 = fixer__a_notFIFO_T_6 & 33'h8C011000; // @[Parameters.scala:137:{41,46}]
wire [32:0] fixer__a_notFIFO_T_8 = fixer__a_notFIFO_T_7; // @[Parameters.scala:137:46]
wire fixer__a_notFIFO_T_9 = fixer__a_notFIFO_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] fixer__a_notFIFO_T_10 = {fixer_anonIn_a_bits_address[31:28], fixer_anonIn_a_bits_address[27:0] ^ 28'hC000000}; // @[Parameters.scala:137:31]
wire [32:0] fixer__a_notFIFO_T_11 = {1'h0, fixer__a_notFIFO_T_10}; // @[Parameters.scala:137:{31,41}]
wire [32:0] fixer__a_notFIFO_T_12 = fixer__a_notFIFO_T_11 & 33'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] fixer__a_notFIFO_T_13 = fixer__a_notFIFO_T_12; // @[Parameters.scala:137:46]
wire fixer__a_notFIFO_T_14 = fixer__a_notFIFO_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire fixer__a_notFIFO_T_15 = fixer__a_notFIFO_T_4 | fixer__a_notFIFO_T_9; // @[Parameters.scala:629:89]
wire fixer__a_notFIFO_T_16 = fixer__a_notFIFO_T_15 | fixer__a_notFIFO_T_14; // @[Parameters.scala:629:89]
wire [31:0] fixer__a_notFIFO_T_17 = {fixer_anonIn_a_bits_address[31:28], fixer_anonIn_a_bits_address[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31]
wire [32:0] fixer__a_notFIFO_T_18 = {1'h0, fixer__a_notFIFO_T_17}; // @[Parameters.scala:137:{31,41}]
wire [32:0] fixer__a_notFIFO_T_19 = fixer__a_notFIFO_T_18 & 33'h8C010000; // @[Parameters.scala:137:{41,46}]
wire [32:0] fixer__a_notFIFO_T_20 = fixer__a_notFIFO_T_19; // @[Parameters.scala:137:46]
wire fixer__a_notFIFO_T_21 = fixer__a_notFIFO_T_20 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] fixer__a_notFIFO_T_22 = fixer_anonIn_a_bits_address ^ 32'h80000000; // @[Parameters.scala:137:31]
wire [32:0] fixer__a_notFIFO_T_23 = {1'h0, fixer__a_notFIFO_T_22}; // @[Parameters.scala:137:{31,41}]
wire [32:0] fixer__a_notFIFO_T_24 = fixer__a_notFIFO_T_23 & 33'h80000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] fixer__a_notFIFO_T_25 = fixer__a_notFIFO_T_24; // @[Parameters.scala:137:46]
wire fixer__a_notFIFO_T_26 = fixer__a_notFIFO_T_25 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire fixer__a_notFIFO_T_27 = fixer__a_notFIFO_T_21 | fixer__a_notFIFO_T_26; // @[Parameters.scala:629:89]
wire fixer__a_notFIFO_T_29 = fixer__a_notFIFO_T_27; // @[Mux.scala:30:73]
wire fixer__a_notFIFO_T_30 = fixer__a_notFIFO_T_29; // @[Mux.scala:30:73]
wire fixer_a_notFIFO = fixer__a_notFIFO_T_30; // @[Mux.scala:30:73]
wire [32:0] fixer__a_id_T_1 = {1'h0, fixer__a_id_T}; // @[Parameters.scala:137:{31,41}]
wire fixer__a_first_T = fixer_anonIn_a_ready & fixer_anonIn_a_valid; // @[Decoupled.scala:51:35]
wire [26:0] fixer__a_first_beats1_decode_T = 27'hFFF << fixer_anonIn_a_bits_size; // @[package.scala:243:71]
wire [11:0] fixer__a_first_beats1_decode_T_1 = fixer__a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] fixer__a_first_beats1_decode_T_2 = ~fixer__a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [7:0] fixer_a_first_beats1_decode = fixer__a_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46]
wire fixer__a_first_beats1_opdata_T = fixer_anonIn_a_bits_opcode[2]; // @[Edges.scala:92:37]
wire fixer_a_first_beats1_opdata = ~fixer__a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [7:0] fixer_a_first_beats1 = fixer_a_first_beats1_opdata ? fixer_a_first_beats1_decode : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [7:0] fixer_a_first_counter; // @[Edges.scala:229:27]
wire [8:0] fixer__a_first_counter1_T = {1'h0, fixer_a_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28]
wire [7:0] fixer_a_first_counter1 = fixer__a_first_counter1_T[7:0]; // @[Edges.scala:230:28]
wire fixer_a_first = fixer_a_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25]
wire fixer__a_first_last_T = fixer_a_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25]
wire fixer__a_first_last_T_1 = fixer_a_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43]
wire fixer_a_first_last = fixer__a_first_last_T | fixer__a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire fixer_a_first_done = fixer_a_first_last & fixer__a_first_T; // @[Decoupled.scala:51:35]
wire [7:0] fixer__a_first_count_T = ~fixer_a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [7:0] fixer_a_first_count = fixer_a_first_beats1 & fixer__a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [7:0] fixer__a_first_counter_T = fixer_a_first ? fixer_a_first_beats1 : fixer_a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire fixer__d_first_T = fixer_anonOut_d_ready & fixer_anonOut_d_valid; // @[Decoupled.scala:51:35]
wire [26:0] fixer__d_first_beats1_decode_T = 27'hFFF << fixer_anonOut_d_bits_size; // @[package.scala:243:71]
wire [11:0] fixer__d_first_beats1_decode_T_1 = fixer__d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] fixer__d_first_beats1_decode_T_2 = ~fixer__d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [7:0] fixer_d_first_beats1_decode = fixer__d_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46]
wire fixer_d_first_beats1_opdata = fixer_anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36]
wire [7:0] fixer_d_first_beats1 = fixer_d_first_beats1_opdata ? fixer_d_first_beats1_decode : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [7:0] fixer_d_first_counter; // @[Edges.scala:229:27]
wire [8:0] fixer__d_first_counter1_T = {1'h0, fixer_d_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28]
wire [7:0] fixer_d_first_counter1 = fixer__d_first_counter1_T[7:0]; // @[Edges.scala:230:28]
wire fixer_d_first_first = fixer_d_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25]
wire fixer__d_first_last_T = fixer_d_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25]
wire fixer__d_first_last_T_1 = fixer_d_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43]
wire fixer_d_first_last = fixer__d_first_last_T | fixer__d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire fixer_d_first_done = fixer_d_first_last & fixer__d_first_T; // @[Decoupled.scala:51:35]
wire [7:0] fixer__d_first_count_T = ~fixer_d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [7:0] fixer_d_first_count = fixer_d_first_beats1 & fixer__d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [7:0] fixer__d_first_counter_T = fixer_d_first_first ? fixer_d_first_beats1 : fixer_d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire fixer__d_first_T_1 = fixer_anonOut_d_bits_opcode != 3'h6; // @[FIFOFixer.scala:75:63]
wire fixer_d_first = fixer_d_first_first & fixer__d_first_T_1; // @[FIFOFixer.scala:75:{42,63}]
reg fixer_flight_0; // @[FIFOFixer.scala:79:27]
reg fixer_flight_1; // @[FIFOFixer.scala:79:27]
reg fixer_flight_2; // @[FIFOFixer.scala:79:27]
reg fixer_flight_3; // @[FIFOFixer.scala:79:27]
reg fixer_flight_4; // @[FIFOFixer.scala:79:27]
reg fixer_flight_5; // @[FIFOFixer.scala:79:27]
reg fixer_flight_6; // @[FIFOFixer.scala:79:27]
reg fixer_flight_7; // @[FIFOFixer.scala:79:27]
reg fixer_flight_8; // @[FIFOFixer.scala:79:27]
reg fixer_flight_9; // @[FIFOFixer.scala:79:27]
reg fixer_flight_10; // @[FIFOFixer.scala:79:27]
reg fixer_flight_11; // @[FIFOFixer.scala:79:27]
reg fixer_flight_12; // @[FIFOFixer.scala:79:27]
reg fixer_flight_13; // @[FIFOFixer.scala:79:27]
reg fixer_flight_14; // @[FIFOFixer.scala:79:27]
reg fixer_flight_15; // @[FIFOFixer.scala:79:27]
reg fixer_flight_16; // @[FIFOFixer.scala:79:27]
wire fixer__flight_T = ~fixer_a_notFIFO; // @[Mux.scala:30:73]
wire fixer__T_2 = fixer_anonIn_d_ready & fixer_anonIn_d_valid; // @[Decoupled.scala:51:35]
assign fixer_anonOut_a_valid = fixer__anonOut_a_valid_T_2; // @[FIFOFixer.scala:95:33]
assign fixer_anonIn_a_ready = fixer__anonIn_a_ready_T_2; // @[FIFOFixer.scala:96:33]
reg [16:0] fixer_SourceIdFIFOed; // @[FIFOFixer.scala:115:35]
wire [16:0] fixer_SourceIdSet; // @[FIFOFixer.scala:116:36]
wire [16:0] fixer_SourceIdClear; // @[FIFOFixer.scala:117:38]
wire [31:0] fixer__SourceIdSet_T = 32'h1 << fixer_anonIn_a_bits_source; // @[OneHot.scala:58:35]
assign fixer_SourceIdSet = fixer_a_first & fixer__a_first_T & ~fixer_a_notFIFO ? fixer__SourceIdSet_T[16:0] : 17'h0; // @[OneHot.scala:58:35]
wire [31:0] fixer__SourceIdClear_T = 32'h1 << fixer_anonIn_d_bits_source; // @[OneHot.scala:58:35]
assign fixer_SourceIdClear = fixer_d_first & fixer__T_2 ? fixer__SourceIdClear_T[16:0] : 17'h0; // @[OneHot.scala:58:35]
wire [16:0] fixer__SourceIdFIFOed_T = fixer_SourceIdFIFOed | fixer_SourceIdSet; // @[FIFOFixer.scala:115:35, :116:36, :126:40]
wire fixer_allIDs_FIFOed = &fixer_SourceIdFIFOed; // @[FIFOFixer.scala:115:35, :127:41]
wire [32:0] fixer__a_notFIFO_T_32 = {1'h0, fixer__a_notFIFO_T_31}; // @[Parameters.scala:137:{31,41}]
wire [32:0] fixer__a_notFIFO_T_33 = fixer__a_notFIFO_T_32 & 33'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] fixer__a_notFIFO_T_34 = fixer__a_notFIFO_T_33; // @[Parameters.scala:137:46]
wire fixer__a_notFIFO_T_35 = fixer__a_notFIFO_T_34 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] fixer__a_notFIFO_T_36 = {fixer_x1_anonIn_a_bits_address[31:17], fixer_x1_anonIn_a_bits_address[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31]
wire [32:0] fixer__a_notFIFO_T_37 = {1'h0, fixer__a_notFIFO_T_36}; // @[Parameters.scala:137:{31,41}]
wire [32:0] fixer__a_notFIFO_T_38 = fixer__a_notFIFO_T_37 & 33'h8C011000; // @[Parameters.scala:137:{41,46}]
wire [32:0] fixer__a_notFIFO_T_39 = fixer__a_notFIFO_T_38; // @[Parameters.scala:137:46]
wire fixer__a_notFIFO_T_40 = fixer__a_notFIFO_T_39 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] fixer__a_notFIFO_T_41 = {fixer_x1_anonIn_a_bits_address[31:28], fixer_x1_anonIn_a_bits_address[27:0] ^ 28'hC000000}; // @[Parameters.scala:137:31]
wire [32:0] fixer__a_notFIFO_T_42 = {1'h0, fixer__a_notFIFO_T_41}; // @[Parameters.scala:137:{31,41}]
wire [32:0] fixer__a_notFIFO_T_43 = fixer__a_notFIFO_T_42 & 33'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] fixer__a_notFIFO_T_44 = fixer__a_notFIFO_T_43; // @[Parameters.scala:137:46]
wire fixer__a_notFIFO_T_45 = fixer__a_notFIFO_T_44 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire fixer__a_notFIFO_T_46 = fixer__a_notFIFO_T_35 | fixer__a_notFIFO_T_40; // @[Parameters.scala:629:89]
wire fixer__a_notFIFO_T_47 = fixer__a_notFIFO_T_46 | fixer__a_notFIFO_T_45; // @[Parameters.scala:629:89]
wire [31:0] fixer__a_notFIFO_T_48 = {fixer_x1_anonIn_a_bits_address[31:28], fixer_x1_anonIn_a_bits_address[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31]
wire [32:0] fixer__a_notFIFO_T_49 = {1'h0, fixer__a_notFIFO_T_48}; // @[Parameters.scala:137:{31,41}]
wire [32:0] fixer__a_notFIFO_T_50 = fixer__a_notFIFO_T_49 & 33'h8C010000; // @[Parameters.scala:137:{41,46}]
wire [32:0] fixer__a_notFIFO_T_51 = fixer__a_notFIFO_T_50; // @[Parameters.scala:137:46]
wire fixer__a_notFIFO_T_52 = fixer__a_notFIFO_T_51 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] fixer__a_notFIFO_T_53 = fixer_x1_anonIn_a_bits_address ^ 32'h80000000; // @[Parameters.scala:137:31]
wire [32:0] fixer__a_notFIFO_T_54 = {1'h0, fixer__a_notFIFO_T_53}; // @[Parameters.scala:137:{31,41}]
wire [32:0] fixer__a_notFIFO_T_55 = fixer__a_notFIFO_T_54 & 33'h80000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] fixer__a_notFIFO_T_56 = fixer__a_notFIFO_T_55; // @[Parameters.scala:137:46]
wire fixer__a_notFIFO_T_57 = fixer__a_notFIFO_T_56 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire fixer__a_notFIFO_T_58 = fixer__a_notFIFO_T_52 | fixer__a_notFIFO_T_57; // @[Parameters.scala:629:89]
wire fixer__a_notFIFO_T_60 = fixer__a_notFIFO_T_58; // @[Mux.scala:30:73]
wire fixer__a_notFIFO_T_61 = fixer__a_notFIFO_T_60; // @[Mux.scala:30:73]
wire fixer_a_notFIFO_1 = fixer__a_notFIFO_T_61; // @[Mux.scala:30:73]
wire [32:0] fixer__a_id_T_6 = {1'h0, fixer__a_id_T_5}; // @[Parameters.scala:137:{31,41}]
wire fixer__a_first_T_1 = fixer_x1_anonIn_a_ready & fixer_x1_anonIn_a_valid; // @[Decoupled.scala:51:35]
wire [26:0] fixer__a_first_beats1_decode_T_3 = 27'hFFF << fixer_x1_anonIn_a_bits_size; // @[package.scala:243:71]
wire [11:0] fixer__a_first_beats1_decode_T_4 = fixer__a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] fixer__a_first_beats1_decode_T_5 = ~fixer__a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [7:0] fixer_a_first_beats1_decode_1 = fixer__a_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46]
wire fixer__a_first_beats1_opdata_T_1 = fixer_x1_anonIn_a_bits_opcode[2]; // @[Edges.scala:92:37]
wire fixer_a_first_beats1_opdata_1 = ~fixer__a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [7:0] fixer_a_first_beats1_1 = fixer_a_first_beats1_opdata_1 ? fixer_a_first_beats1_decode_1 : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [7:0] fixer_a_first_counter_1; // @[Edges.scala:229:27]
wire [8:0] fixer__a_first_counter1_T_1 = {1'h0, fixer_a_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28]
wire [7:0] fixer_a_first_counter1_1 = fixer__a_first_counter1_T_1[7:0]; // @[Edges.scala:230:28]
wire fixer_a_first_1 = fixer_a_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25]
wire fixer__a_first_last_T_2 = fixer_a_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25]
wire fixer__a_first_last_T_3 = fixer_a_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43]
wire fixer_a_first_last_1 = fixer__a_first_last_T_2 | fixer__a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire fixer_a_first_done_1 = fixer_a_first_last_1 & fixer__a_first_T_1; // @[Decoupled.scala:51:35]
wire [7:0] fixer__a_first_count_T_1 = ~fixer_a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [7:0] fixer_a_first_count_1 = fixer_a_first_beats1_1 & fixer__a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [7:0] fixer__a_first_counter_T_1 = fixer_a_first_1 ? fixer_a_first_beats1_1 : fixer_a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire fixer__d_first_T_2 = fixer_x1_anonOut_d_ready & fixer_x1_anonOut_d_valid; // @[Decoupled.scala:51:35]
wire [26:0] fixer__d_first_beats1_decode_T_3 = 27'hFFF << fixer_x1_anonOut_d_bits_size; // @[package.scala:243:71]
wire [11:0] fixer__d_first_beats1_decode_T_4 = fixer__d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] fixer__d_first_beats1_decode_T_5 = ~fixer__d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [7:0] fixer_d_first_beats1_decode_1 = fixer__d_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46]
wire fixer_d_first_beats1_opdata_1 = fixer_x1_anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36]
wire [7:0] fixer_d_first_beats1_1 = fixer_d_first_beats1_opdata_1 ? fixer_d_first_beats1_decode_1 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [7:0] fixer_d_first_counter_1; // @[Edges.scala:229:27]
wire [8:0] fixer__d_first_counter1_T_1 = {1'h0, fixer_d_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28]
wire [7:0] fixer_d_first_counter1_1 = fixer__d_first_counter1_T_1[7:0]; // @[Edges.scala:230:28]
wire fixer_d_first_first_1 = fixer_d_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25]
wire fixer__d_first_last_T_2 = fixer_d_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25]
wire fixer__d_first_last_T_3 = fixer_d_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43]
wire fixer_d_first_last_1 = fixer__d_first_last_T_2 | fixer__d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire fixer_d_first_done_1 = fixer_d_first_last_1 & fixer__d_first_T_2; // @[Decoupled.scala:51:35]
wire [7:0] fixer__d_first_count_T_1 = ~fixer_d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [7:0] fixer_d_first_count_1 = fixer_d_first_beats1_1 & fixer__d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [7:0] fixer__d_first_counter_T_1 = fixer_d_first_first_1 ? fixer_d_first_beats1_1 : fixer_d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire fixer__d_first_T_3 = fixer_x1_anonOut_d_bits_opcode != 3'h6; // @[FIFOFixer.scala:75:63]
wire fixer_d_first_1 = fixer_d_first_first_1 & fixer__d_first_T_3; // @[FIFOFixer.scala:75:{42,63}]
reg fixer_flight_1_0; // @[FIFOFixer.scala:79:27]
reg fixer_flight_1_1; // @[FIFOFixer.scala:79:27]
reg fixer_flight_1_2; // @[FIFOFixer.scala:79:27]
reg fixer_flight_1_3; // @[FIFOFixer.scala:79:27]
reg fixer_flight_1_4; // @[FIFOFixer.scala:79:27]
reg fixer_flight_1_5; // @[FIFOFixer.scala:79:27]
reg fixer_flight_1_6; // @[FIFOFixer.scala:79:27]
reg fixer_flight_1_7; // @[FIFOFixer.scala:79:27]
reg fixer_flight_1_8; // @[FIFOFixer.scala:79:27]
reg fixer_flight_1_9; // @[FIFOFixer.scala:79:27]
reg fixer_flight_1_10; // @[FIFOFixer.scala:79:27]
reg fixer_flight_1_11; // @[FIFOFixer.scala:79:27]
reg fixer_flight_1_12; // @[FIFOFixer.scala:79:27]
reg fixer_flight_1_13; // @[FIFOFixer.scala:79:27]
reg fixer_flight_1_14; // @[FIFOFixer.scala:79:27]
reg fixer_flight_1_15; // @[FIFOFixer.scala:79:27]
reg fixer_flight_1_16; // @[FIFOFixer.scala:79:27]
reg fixer_flight_1_17; // @[FIFOFixer.scala:79:27]
reg fixer_flight_1_18; // @[FIFOFixer.scala:79:27]
reg fixer_flight_1_19; // @[FIFOFixer.scala:79:27]
reg fixer_flight_1_20; // @[FIFOFixer.scala:79:27]
reg fixer_flight_1_21; // @[FIFOFixer.scala:79:27]
reg fixer_flight_1_22; // @[FIFOFixer.scala:79:27]
reg fixer_flight_1_23; // @[FIFOFixer.scala:79:27]
reg fixer_flight_1_24; // @[FIFOFixer.scala:79:27]
reg fixer_flight_1_25; // @[FIFOFixer.scala:79:27]
reg fixer_flight_1_26; // @[FIFOFixer.scala:79:27]
reg fixer_flight_1_27; // @[FIFOFixer.scala:79:27]
reg fixer_flight_1_28; // @[FIFOFixer.scala:79:27]
reg fixer_flight_1_29; // @[FIFOFixer.scala:79:27]
reg fixer_flight_1_30; // @[FIFOFixer.scala:79:27]
reg fixer_flight_1_31; // @[FIFOFixer.scala:79:27]
wire fixer__flight_T_1 = ~fixer_a_notFIFO_1; // @[Mux.scala:30:73]
wire fixer__T_32 = fixer_x1_anonIn_d_ready & fixer_x1_anonIn_d_valid; // @[Decoupled.scala:51:35]
assign fixer_x1_anonOut_a_valid = fixer__anonOut_a_valid_T_5; // @[FIFOFixer.scala:95:33]
assign fixer_x1_anonIn_a_ready = fixer__anonIn_a_ready_T_5; // @[FIFOFixer.scala:96:33]
reg [31:0] fixer_SourceIdFIFOed_1; // @[FIFOFixer.scala:115:35]
wire [31:0] fixer_SourceIdSet_1; // @[FIFOFixer.scala:116:36]
wire [31:0] fixer_SourceIdClear_1; // @[FIFOFixer.scala:117:38]
wire [31:0] fixer__SourceIdSet_T_1 = 32'h1 << fixer_x1_anonIn_a_bits_source; // @[OneHot.scala:58:35]
assign fixer_SourceIdSet_1 = fixer_a_first_1 & fixer__a_first_T_1 & ~fixer_a_notFIFO_1 ? fixer__SourceIdSet_T_1 : 32'h0; // @[OneHot.scala:58:35]
wire [31:0] fixer__SourceIdClear_T_1 = 32'h1 << fixer_x1_anonIn_d_bits_source; // @[OneHot.scala:58:35]
assign fixer_SourceIdClear_1 = fixer_d_first_1 & fixer__T_32 ? fixer__SourceIdClear_T_1 : 32'h0; // @[OneHot.scala:58:35]
wire [31:0] fixer__SourceIdFIFOed_T_1 = fixer_SourceIdFIFOed_1 | fixer_SourceIdSet_1; // @[FIFOFixer.scala:115:35, :116:36, :126:40]
wire fixer_allIDs_FIFOed_1 = &fixer_SourceIdFIFOed_1; // @[FIFOFixer.scala:115:35, :127:41]
wire [32:0] fixer__a_notFIFO_T_63 = {1'h0, fixer__a_notFIFO_T_62}; // @[Parameters.scala:137:{31,41}]
wire [32:0] fixer__a_notFIFO_T_64 = fixer__a_notFIFO_T_63 & 33'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] fixer__a_notFIFO_T_65 = fixer__a_notFIFO_T_64; // @[Parameters.scala:137:46]
wire fixer__a_notFIFO_T_66 = fixer__a_notFIFO_T_65 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] fixer__a_notFIFO_T_67 = {fixer_x1_anonIn_1_a_bits_address[31:17], fixer_x1_anonIn_1_a_bits_address[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31]
wire [32:0] fixer__a_notFIFO_T_68 = {1'h0, fixer__a_notFIFO_T_67}; // @[Parameters.scala:137:{31,41}]
wire [32:0] fixer__a_notFIFO_T_69 = fixer__a_notFIFO_T_68 & 33'h8C011000; // @[Parameters.scala:137:{41,46}]
wire [32:0] fixer__a_notFIFO_T_70 = fixer__a_notFIFO_T_69; // @[Parameters.scala:137:46]
wire fixer__a_notFIFO_T_71 = fixer__a_notFIFO_T_70 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] fixer__a_notFIFO_T_72 = {fixer_x1_anonIn_1_a_bits_address[31:28], fixer_x1_anonIn_1_a_bits_address[27:0] ^ 28'hC000000}; // @[Parameters.scala:137:31]
wire [32:0] fixer__a_notFIFO_T_73 = {1'h0, fixer__a_notFIFO_T_72}; // @[Parameters.scala:137:{31,41}]
wire [32:0] fixer__a_notFIFO_T_74 = fixer__a_notFIFO_T_73 & 33'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] fixer__a_notFIFO_T_75 = fixer__a_notFIFO_T_74; // @[Parameters.scala:137:46]
wire fixer__a_notFIFO_T_76 = fixer__a_notFIFO_T_75 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire fixer__a_notFIFO_T_77 = fixer__a_notFIFO_T_66 | fixer__a_notFIFO_T_71; // @[Parameters.scala:629:89]
wire fixer__a_notFIFO_T_78 = fixer__a_notFIFO_T_77 | fixer__a_notFIFO_T_76; // @[Parameters.scala:629:89]
wire [31:0] fixer__a_notFIFO_T_79 = {fixer_x1_anonIn_1_a_bits_address[31:28], fixer_x1_anonIn_1_a_bits_address[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31]
wire [32:0] fixer__a_notFIFO_T_80 = {1'h0, fixer__a_notFIFO_T_79}; // @[Parameters.scala:137:{31,41}]
wire [32:0] fixer__a_notFIFO_T_81 = fixer__a_notFIFO_T_80 & 33'h8C010000; // @[Parameters.scala:137:{41,46}]
wire [32:0] fixer__a_notFIFO_T_82 = fixer__a_notFIFO_T_81; // @[Parameters.scala:137:46]
wire fixer__a_notFIFO_T_83 = fixer__a_notFIFO_T_82 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] fixer__a_notFIFO_T_84 = fixer_x1_anonIn_1_a_bits_address ^ 32'h80000000; // @[Parameters.scala:137:31]
wire [32:0] fixer__a_notFIFO_T_85 = {1'h0, fixer__a_notFIFO_T_84}; // @[Parameters.scala:137:{31,41}]
wire [32:0] fixer__a_notFIFO_T_86 = fixer__a_notFIFO_T_85 & 33'h80000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] fixer__a_notFIFO_T_87 = fixer__a_notFIFO_T_86; // @[Parameters.scala:137:46]
wire fixer__a_notFIFO_T_88 = fixer__a_notFIFO_T_87 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire fixer__a_notFIFO_T_89 = fixer__a_notFIFO_T_83 | fixer__a_notFIFO_T_88; // @[Parameters.scala:629:89]
wire fixer__a_notFIFO_T_91 = fixer__a_notFIFO_T_89; // @[Mux.scala:30:73]
wire fixer__a_notFIFO_T_92 = fixer__a_notFIFO_T_91; // @[Mux.scala:30:73]
wire fixer_a_notFIFO_2 = fixer__a_notFIFO_T_92; // @[Mux.scala:30:73]
wire [32:0] fixer__a_id_T_11 = {1'h0, fixer__a_id_T_10}; // @[Parameters.scala:137:{31,41}]
wire fixer__a_first_T_2 = fixer_x1_anonIn_1_a_ready & fixer_x1_anonIn_1_a_valid; // @[Decoupled.scala:51:35]
wire [26:0] fixer__a_first_beats1_decode_T_6 = 27'hFFF << fixer_x1_anonIn_1_a_bits_size; // @[package.scala:243:71]
wire [11:0] fixer__a_first_beats1_decode_T_7 = fixer__a_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] fixer__a_first_beats1_decode_T_8 = ~fixer__a_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [7:0] fixer_a_first_beats1_decode_2 = fixer__a_first_beats1_decode_T_8[11:4]; // @[package.scala:243:46]
wire fixer__a_first_beats1_opdata_T_2 = fixer_x1_anonIn_1_a_bits_opcode[2]; // @[Edges.scala:92:37]
wire fixer_a_first_beats1_opdata_2 = ~fixer__a_first_beats1_opdata_T_2; // @[Edges.scala:92:{28,37}]
wire [7:0] fixer_a_first_beats1_2 = fixer_a_first_beats1_opdata_2 ? fixer_a_first_beats1_decode_2 : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [7:0] fixer_a_first_counter_2; // @[Edges.scala:229:27]
wire [8:0] fixer__a_first_counter1_T_2 = {1'h0, fixer_a_first_counter_2} - 9'h1; // @[Edges.scala:229:27, :230:28]
wire [7:0] fixer_a_first_counter1_2 = fixer__a_first_counter1_T_2[7:0]; // @[Edges.scala:230:28]
wire fixer_a_first_2 = fixer_a_first_counter_2 == 8'h0; // @[Edges.scala:229:27, :231:25]
wire fixer__a_first_last_T_4 = fixer_a_first_counter_2 == 8'h1; // @[Edges.scala:229:27, :232:25]
wire fixer__a_first_last_T_5 = fixer_a_first_beats1_2 == 8'h0; // @[Edges.scala:221:14, :232:43]
wire fixer_a_first_last_2 = fixer__a_first_last_T_4 | fixer__a_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire fixer_a_first_done_2 = fixer_a_first_last_2 & fixer__a_first_T_2; // @[Decoupled.scala:51:35]
wire [7:0] fixer__a_first_count_T_2 = ~fixer_a_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [7:0] fixer_a_first_count_2 = fixer_a_first_beats1_2 & fixer__a_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [7:0] fixer__a_first_counter_T_2 = fixer_a_first_2 ? fixer_a_first_beats1_2 : fixer_a_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire fixer__d_first_T_4 = fixer_x1_anonOut_1_d_ready & fixer_x1_anonOut_1_d_valid; // @[Decoupled.scala:51:35]
wire [26:0] fixer__d_first_beats1_decode_T_6 = 27'hFFF << fixer_x1_anonOut_1_d_bits_size; // @[package.scala:243:71]
wire [11:0] fixer__d_first_beats1_decode_T_7 = fixer__d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] fixer__d_first_beats1_decode_T_8 = ~fixer__d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [7:0] fixer_d_first_beats1_decode_2 = fixer__d_first_beats1_decode_T_8[11:4]; // @[package.scala:243:46]
wire fixer_d_first_beats1_opdata_2 = fixer_x1_anonOut_1_d_bits_opcode[0]; // @[Edges.scala:106:36]
wire [7:0] fixer_d_first_beats1_2 = fixer_d_first_beats1_opdata_2 ? fixer_d_first_beats1_decode_2 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [7:0] fixer_d_first_counter_2; // @[Edges.scala:229:27]
wire [8:0] fixer__d_first_counter1_T_2 = {1'h0, fixer_d_first_counter_2} - 9'h1; // @[Edges.scala:229:27, :230:28]
wire [7:0] fixer_d_first_counter1_2 = fixer__d_first_counter1_T_2[7:0]; // @[Edges.scala:230:28]
wire fixer_d_first_first_2 = fixer_d_first_counter_2 == 8'h0; // @[Edges.scala:229:27, :231:25]
wire fixer__d_first_last_T_4 = fixer_d_first_counter_2 == 8'h1; // @[Edges.scala:229:27, :232:25]
wire fixer__d_first_last_T_5 = fixer_d_first_beats1_2 == 8'h0; // @[Edges.scala:221:14, :232:43]
wire fixer_d_first_last_2 = fixer__d_first_last_T_4 | fixer__d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire fixer_d_first_done_2 = fixer_d_first_last_2 & fixer__d_first_T_4; // @[Decoupled.scala:51:35]
wire [7:0] fixer__d_first_count_T_2 = ~fixer_d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [7:0] fixer_d_first_count_2 = fixer_d_first_beats1_2 & fixer__d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [7:0] fixer__d_first_counter_T_2 = fixer_d_first_first_2 ? fixer_d_first_beats1_2 : fixer_d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire fixer__d_first_T_5 = fixer_x1_anonOut_1_d_bits_opcode != 3'h6; // @[FIFOFixer.scala:75:63]
wire fixer_d_first_2 = fixer_d_first_first_2 & fixer__d_first_T_5; // @[FIFOFixer.scala:75:{42,63}]
reg fixer_flight_2_0; // @[FIFOFixer.scala:79:27]
reg fixer_flight_2_1; // @[FIFOFixer.scala:79:27]
reg fixer_flight_2_2; // @[FIFOFixer.scala:79:27]
wire fixer__flight_T_2 = ~fixer_a_notFIFO_2; // @[Mux.scala:30:73]
wire fixer__T_77 = fixer_x1_anonIn_1_d_ready & fixer_x1_anonIn_1_d_valid; // @[Decoupled.scala:51:35]
assign fixer_x1_anonOut_1_a_valid = fixer__anonOut_a_valid_T_8; // @[FIFOFixer.scala:95:33]
assign fixer_x1_anonIn_1_a_ready = fixer__anonIn_a_ready_T_8; // @[FIFOFixer.scala:96:33]
reg [2:0] fixer_SourceIdFIFOed_2; // @[FIFOFixer.scala:115:35]
wire [2:0] fixer_SourceIdSet_2; // @[FIFOFixer.scala:116:36]
wire [2:0] fixer_SourceIdClear_2; // @[FIFOFixer.scala:117:38]
wire [3:0] fixer__SourceIdSet_T_2 = 4'h1 << fixer_x1_anonIn_1_a_bits_source; // @[OneHot.scala:58:35]
assign fixer_SourceIdSet_2 = fixer_a_first_2 & fixer__a_first_T_2 & ~fixer_a_notFIFO_2 ? fixer__SourceIdSet_T_2[2:0] : 3'h0; // @[OneHot.scala:58:35]
wire [3:0] fixer__SourceIdClear_T_2 = 4'h1 << fixer_x1_anonIn_1_d_bits_source; // @[OneHot.scala:58:35]
assign fixer_SourceIdClear_2 = fixer_d_first_2 & fixer__T_77 ? fixer__SourceIdClear_T_2[2:0] : 3'h0; // @[OneHot.scala:58:35]
wire [2:0] fixer__SourceIdFIFOed_T_2 = fixer_SourceIdFIFOed_2 | fixer_SourceIdSet_2; // @[FIFOFixer.scala:115:35, :116:36, :126:40]
wire fixer_allIDs_FIFOed_2 = &fixer_SourceIdFIFOed_2; // @[FIFOFixer.scala:115:35, :127:41]
wire coupler_to_bus_named_coh_widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_auto_anon_in_a_valid = coupler_to_bus_named_coh_auto_widget_anon_in_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_opcode = coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_param = coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_size = coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_size; // @[WidthWidget.scala:27:9]
wire [6:0] coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_source = coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_address = coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_address; // @[WidthWidget.scala:27:9]
wire [15:0] coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_mask = coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_data = coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_corrupt = coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_auto_anon_in_b_ready = coupler_to_bus_named_coh_auto_widget_anon_in_b_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_auto_anon_in_b_valid; // @[WidthWidget.scala:27:9]
wire [1:0] coupler_to_bus_named_coh_widget_auto_anon_in_b_bits_param; // @[WidthWidget.scala:27:9]
wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_in_b_bits_address; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_auto_anon_in_c_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_auto_anon_in_c_valid = coupler_to_bus_named_coh_auto_widget_anon_in_c_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_c_bits_opcode = coupler_to_bus_named_coh_auto_widget_anon_in_c_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_c_bits_param = coupler_to_bus_named_coh_auto_widget_anon_in_c_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_c_bits_size = coupler_to_bus_named_coh_auto_widget_anon_in_c_bits_size; // @[WidthWidget.scala:27:9]
wire [6:0] coupler_to_bus_named_coh_widget_auto_anon_in_c_bits_source = coupler_to_bus_named_coh_auto_widget_anon_in_c_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_in_c_bits_address = coupler_to_bus_named_coh_auto_widget_anon_in_c_bits_address; // @[WidthWidget.scala:27:9]
wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_in_c_bits_data = coupler_to_bus_named_coh_auto_widget_anon_in_c_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_auto_anon_in_c_bits_corrupt = coupler_to_bus_named_coh_auto_widget_anon_in_c_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_auto_anon_in_d_ready = coupler_to_bus_named_coh_auto_widget_anon_in_d_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9]
wire [6:0] coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9]
wire [3:0] coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_auto_anon_in_e_valid = coupler_to_bus_named_coh_auto_widget_anon_in_e_valid; // @[WidthWidget.scala:27:9]
wire [3:0] coupler_to_bus_named_coh_widget_auto_anon_in_e_bits_sink = coupler_to_bus_named_coh_auto_widget_anon_in_e_bits_sink; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_auto_anon_out_a_ready = coupler_to_bus_named_coh_auto_widget_anon_out_a_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_valid_0 = coupler_to_bus_named_coh_auto_widget_anon_out_a_valid; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_opcode_0 = coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_param_0 = coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_param; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_size_0 = coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_size; // @[ClockDomain.scala:14:9]
wire [6:0] coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_source_0 = coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_address_0 = coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_address; // @[ClockDomain.scala:14:9]
wire [15:0] coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_mask_0 = coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_mask; // @[ClockDomain.scala:14:9]
wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_data_0 = coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_data; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_corrupt; // @[WidthWidget.scala:27:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_corrupt_0 = coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_corrupt; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_coh_widget_auto_anon_out_b_ready; // @[WidthWidget.scala:27:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_b_ready_0 = coupler_to_bus_named_coh_auto_widget_anon_out_b_ready; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_coh_widget_auto_anon_out_b_valid = coupler_to_bus_named_coh_auto_widget_anon_out_b_valid; // @[WidthWidget.scala:27:9]
wire [1:0] coupler_to_bus_named_coh_widget_auto_anon_out_b_bits_param = coupler_to_bus_named_coh_auto_widget_anon_out_b_bits_param; // @[WidthWidget.scala:27:9]
wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_out_b_bits_address = coupler_to_bus_named_coh_auto_widget_anon_out_b_bits_address; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_auto_anon_out_c_ready = coupler_to_bus_named_coh_auto_widget_anon_out_c_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_auto_anon_out_c_valid; // @[WidthWidget.scala:27:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_c_valid_0 = coupler_to_bus_named_coh_auto_widget_anon_out_c_valid; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_c_bits_opcode; // @[WidthWidget.scala:27:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_opcode_0 = coupler_to_bus_named_coh_auto_widget_anon_out_c_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_c_bits_param; // @[WidthWidget.scala:27:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_param_0 = coupler_to_bus_named_coh_auto_widget_anon_out_c_bits_param; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_c_bits_size; // @[WidthWidget.scala:27:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_size_0 = coupler_to_bus_named_coh_auto_widget_anon_out_c_bits_size; // @[ClockDomain.scala:14:9]
wire [6:0] coupler_to_bus_named_coh_widget_auto_anon_out_c_bits_source; // @[WidthWidget.scala:27:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_source_0 = coupler_to_bus_named_coh_auto_widget_anon_out_c_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_out_c_bits_address; // @[WidthWidget.scala:27:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_address_0 = coupler_to_bus_named_coh_auto_widget_anon_out_c_bits_address; // @[ClockDomain.scala:14:9]
wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_out_c_bits_data; // @[WidthWidget.scala:27:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_data_0 = coupler_to_bus_named_coh_auto_widget_anon_out_c_bits_data; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_coh_widget_auto_anon_out_c_bits_corrupt; // @[WidthWidget.scala:27:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_corrupt_0 = coupler_to_bus_named_coh_auto_widget_anon_out_c_bits_corrupt; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_coh_widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_d_ready_0 = coupler_to_bus_named_coh_auto_widget_anon_out_d_ready; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_coh_widget_auto_anon_out_d_valid = coupler_to_bus_named_coh_auto_widget_anon_out_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_opcode = coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_param = coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_size = coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_size; // @[WidthWidget.scala:27:9]
wire [6:0] coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_source = coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_source; // @[WidthWidget.scala:27:9]
wire [3:0] coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_sink = coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_denied = coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [127:0] coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_data = coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_corrupt = coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_auto_anon_out_e_valid; // @[WidthWidget.scala:27:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_e_valid_0 = coupler_to_bus_named_coh_auto_widget_anon_out_e_valid; // @[ClockDomain.scala:14:9]
wire [3:0] coupler_to_bus_named_coh_widget_auto_anon_out_e_bits_sink; // @[WidthWidget.scala:27:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_e_bits_sink_0 = coupler_to_bus_named_coh_auto_widget_anon_out_e_bits_sink; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_coh_auto_widget_anon_in_a_ready; // @[LazyModuleImp.scala:138:7]
wire [1:0] coupler_to_bus_named_coh_auto_widget_anon_in_b_bits_param; // @[LazyModuleImp.scala:138:7]
wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_in_b_bits_address; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_coh_auto_widget_anon_in_b_valid; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_coh_auto_widget_anon_in_c_ready; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [1:0] coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_param; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_size; // @[LazyModuleImp.scala:138:7]
wire [6:0] coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_source; // @[LazyModuleImp.scala:138:7]
wire [3:0] coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_sink; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_denied; // @[LazyModuleImp.scala:138:7]
wire [127:0] coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_data; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_coh_auto_widget_anon_in_d_valid; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_coh_widget_anonIn_a_ready; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_coh_auto_widget_anon_in_a_ready = coupler_to_bus_named_coh_widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonIn_a_valid = coupler_to_bus_named_coh_widget_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_anonIn_a_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_anonIn_a_bits_param = coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_anonIn_a_bits_size = coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9]
wire [6:0] coupler_to_bus_named_coh_widget_anonIn_a_bits_source = coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] coupler_to_bus_named_coh_widget_anonIn_a_bits_address = coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9]
wire [15:0] coupler_to_bus_named_coh_widget_anonIn_a_bits_mask = coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [127:0] coupler_to_bus_named_coh_widget_anonIn_a_bits_data = coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonIn_a_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonIn_b_ready = coupler_to_bus_named_coh_widget_auto_anon_in_b_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonIn_b_valid; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_coh_auto_widget_anon_in_b_valid = coupler_to_bus_named_coh_widget_auto_anon_in_b_valid; // @[WidthWidget.scala:27:9]
wire [1:0] coupler_to_bus_named_coh_widget_anonIn_b_bits_param; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_coh_auto_widget_anon_in_b_bits_param = coupler_to_bus_named_coh_widget_auto_anon_in_b_bits_param; // @[WidthWidget.scala:27:9]
wire [31:0] coupler_to_bus_named_coh_widget_anonIn_b_bits_address; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_coh_auto_widget_anon_in_b_bits_address = coupler_to_bus_named_coh_widget_auto_anon_in_b_bits_address; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonIn_c_ready; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_coh_auto_widget_anon_in_c_ready = coupler_to_bus_named_coh_widget_auto_anon_in_c_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonIn_c_valid = coupler_to_bus_named_coh_widget_auto_anon_in_c_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_anonIn_c_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_in_c_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_anonIn_c_bits_param = coupler_to_bus_named_coh_widget_auto_anon_in_c_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_anonIn_c_bits_size = coupler_to_bus_named_coh_widget_auto_anon_in_c_bits_size; // @[WidthWidget.scala:27:9]
wire [6:0] coupler_to_bus_named_coh_widget_anonIn_c_bits_source = coupler_to_bus_named_coh_widget_auto_anon_in_c_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] coupler_to_bus_named_coh_widget_anonIn_c_bits_address = coupler_to_bus_named_coh_widget_auto_anon_in_c_bits_address; // @[WidthWidget.scala:27:9]
wire [127:0] coupler_to_bus_named_coh_widget_anonIn_c_bits_data = coupler_to_bus_named_coh_widget_auto_anon_in_c_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonIn_c_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_in_c_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonIn_d_ready = coupler_to_bus_named_coh_widget_auto_anon_in_d_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonIn_d_valid; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_coh_auto_widget_anon_in_d_valid = coupler_to_bus_named_coh_widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] coupler_to_bus_named_coh_widget_anonIn_d_bits_param; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_param = coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_anonIn_d_bits_size; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_size = coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9]
wire [6:0] coupler_to_bus_named_coh_widget_anonIn_d_bits_source; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_source = coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9]
wire [3:0] coupler_to_bus_named_coh_widget_anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_sink = coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_denied = coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [127:0] coupler_to_bus_named_coh_widget_anonIn_d_bits_data; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_data = coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonIn_e_valid = coupler_to_bus_named_coh_widget_auto_anon_in_e_valid; // @[WidthWidget.scala:27:9]
wire [3:0] coupler_to_bus_named_coh_widget_anonIn_e_bits_sink = coupler_to_bus_named_coh_widget_auto_anon_in_e_bits_sink; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonOut_a_ready = coupler_to_bus_named_coh_widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonOut_a_valid; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_coh_auto_widget_anon_out_a_valid = coupler_to_bus_named_coh_widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_anonOut_a_bits_param; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_param = coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_anonOut_a_bits_size; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_size = coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9]
wire [6:0] coupler_to_bus_named_coh_widget_anonOut_a_bits_source; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_source = coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] coupler_to_bus_named_coh_widget_anonOut_a_bits_address; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_address = coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9]
wire [15:0] coupler_to_bus_named_coh_widget_anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_mask = coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [127:0] coupler_to_bus_named_coh_widget_anonOut_a_bits_data; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_data = coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonOut_b_ready; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_coh_auto_widget_anon_out_b_ready = coupler_to_bus_named_coh_widget_auto_anon_out_b_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonOut_b_valid = coupler_to_bus_named_coh_widget_auto_anon_out_b_valid; // @[WidthWidget.scala:27:9]
wire [1:0] coupler_to_bus_named_coh_widget_anonOut_b_bits_param = coupler_to_bus_named_coh_widget_auto_anon_out_b_bits_param; // @[WidthWidget.scala:27:9]
wire [31:0] coupler_to_bus_named_coh_widget_anonOut_b_bits_address = coupler_to_bus_named_coh_widget_auto_anon_out_b_bits_address; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonOut_c_ready = coupler_to_bus_named_coh_widget_auto_anon_out_c_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonOut_c_valid; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_coh_auto_widget_anon_out_c_valid = coupler_to_bus_named_coh_widget_auto_anon_out_c_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_anonOut_c_bits_opcode; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_coh_auto_widget_anon_out_c_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_out_c_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_anonOut_c_bits_param; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_coh_auto_widget_anon_out_c_bits_param = coupler_to_bus_named_coh_widget_auto_anon_out_c_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_anonOut_c_bits_size; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_coh_auto_widget_anon_out_c_bits_size = coupler_to_bus_named_coh_widget_auto_anon_out_c_bits_size; // @[WidthWidget.scala:27:9]
wire [6:0] coupler_to_bus_named_coh_widget_anonOut_c_bits_source; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_coh_auto_widget_anon_out_c_bits_source = coupler_to_bus_named_coh_widget_auto_anon_out_c_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] coupler_to_bus_named_coh_widget_anonOut_c_bits_address; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_coh_auto_widget_anon_out_c_bits_address = coupler_to_bus_named_coh_widget_auto_anon_out_c_bits_address; // @[WidthWidget.scala:27:9]
wire [127:0] coupler_to_bus_named_coh_widget_anonOut_c_bits_data; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_coh_auto_widget_anon_out_c_bits_data = coupler_to_bus_named_coh_widget_auto_anon_out_c_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonOut_c_bits_corrupt; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_coh_auto_widget_anon_out_c_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_out_c_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonOut_d_ready; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_coh_auto_widget_anon_out_d_ready = coupler_to_bus_named_coh_widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonOut_d_valid = coupler_to_bus_named_coh_widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_anonOut_d_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] coupler_to_bus_named_coh_widget_anonOut_d_bits_param = coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_coh_widget_anonOut_d_bits_size = coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9]
wire [6:0] coupler_to_bus_named_coh_widget_anonOut_d_bits_source = coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9]
wire [3:0] coupler_to_bus_named_coh_widget_anonOut_d_bits_sink = coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonOut_d_bits_denied = coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [127:0] coupler_to_bus_named_coh_widget_anonOut_d_bits_data = coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonOut_d_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_coh_widget_anonOut_e_valid; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_coh_auto_widget_anon_out_e_valid = coupler_to_bus_named_coh_widget_auto_anon_out_e_valid; // @[WidthWidget.scala:27:9]
wire [3:0] coupler_to_bus_named_coh_widget_anonOut_e_bits_sink; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_coh_auto_widget_anon_out_e_bits_sink = coupler_to_bus_named_coh_widget_auto_anon_out_e_bits_sink; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_anonIn_a_ready = coupler_to_bus_named_coh_widget_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_auto_anon_out_a_valid = coupler_to_bus_named_coh_widget_anonOut_a_valid; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_opcode = coupler_to_bus_named_coh_widget_anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_param = coupler_to_bus_named_coh_widget_anonOut_a_bits_param; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_size = coupler_to_bus_named_coh_widget_anonOut_a_bits_size; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_source = coupler_to_bus_named_coh_widget_anonOut_a_bits_source; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_address = coupler_to_bus_named_coh_widget_anonOut_a_bits_address; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_mask = coupler_to_bus_named_coh_widget_anonOut_a_bits_mask; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_data = coupler_to_bus_named_coh_widget_anonOut_a_bits_data; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_corrupt = coupler_to_bus_named_coh_widget_anonOut_a_bits_corrupt; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_out_b_ready = coupler_to_bus_named_coh_widget_anonOut_b_ready; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_anonIn_b_valid = coupler_to_bus_named_coh_widget_anonOut_b_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonIn_b_bits_param = coupler_to_bus_named_coh_widget_anonOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonIn_b_bits_address = coupler_to_bus_named_coh_widget_anonOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonIn_c_ready = coupler_to_bus_named_coh_widget_anonOut_c_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_auto_anon_out_c_valid = coupler_to_bus_named_coh_widget_anonOut_c_valid; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_out_c_bits_opcode = coupler_to_bus_named_coh_widget_anonOut_c_bits_opcode; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_out_c_bits_param = coupler_to_bus_named_coh_widget_anonOut_c_bits_param; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_out_c_bits_size = coupler_to_bus_named_coh_widget_anonOut_c_bits_size; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_out_c_bits_source = coupler_to_bus_named_coh_widget_anonOut_c_bits_source; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_out_c_bits_address = coupler_to_bus_named_coh_widget_anonOut_c_bits_address; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_out_c_bits_data = coupler_to_bus_named_coh_widget_anonOut_c_bits_data; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_out_c_bits_corrupt = coupler_to_bus_named_coh_widget_anonOut_c_bits_corrupt; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_out_d_ready = coupler_to_bus_named_coh_widget_anonOut_d_ready; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_anonIn_d_valid = coupler_to_bus_named_coh_widget_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonIn_d_bits_opcode = coupler_to_bus_named_coh_widget_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonIn_d_bits_param = coupler_to_bus_named_coh_widget_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonIn_d_bits_size = coupler_to_bus_named_coh_widget_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonIn_d_bits_source = coupler_to_bus_named_coh_widget_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonIn_d_bits_sink = coupler_to_bus_named_coh_widget_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonIn_d_bits_denied = coupler_to_bus_named_coh_widget_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonIn_d_bits_data = coupler_to_bus_named_coh_widget_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonIn_d_bits_corrupt = coupler_to_bus_named_coh_widget_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_auto_anon_out_e_valid = coupler_to_bus_named_coh_widget_anonOut_e_valid; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_out_e_bits_sink = coupler_to_bus_named_coh_widget_anonOut_e_bits_sink; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_in_a_ready = coupler_to_bus_named_coh_widget_anonIn_a_ready; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_anonOut_a_valid = coupler_to_bus_named_coh_widget_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonOut_a_bits_opcode = coupler_to_bus_named_coh_widget_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonOut_a_bits_param = coupler_to_bus_named_coh_widget_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonOut_a_bits_size = coupler_to_bus_named_coh_widget_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonOut_a_bits_source = coupler_to_bus_named_coh_widget_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonOut_a_bits_address = coupler_to_bus_named_coh_widget_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonOut_a_bits_mask = coupler_to_bus_named_coh_widget_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonOut_a_bits_data = coupler_to_bus_named_coh_widget_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonOut_a_bits_corrupt = coupler_to_bus_named_coh_widget_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonOut_b_ready = coupler_to_bus_named_coh_widget_anonIn_b_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_auto_anon_in_b_valid = coupler_to_bus_named_coh_widget_anonIn_b_valid; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_in_b_bits_param = coupler_to_bus_named_coh_widget_anonIn_b_bits_param; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_in_b_bits_address = coupler_to_bus_named_coh_widget_anonIn_b_bits_address; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_in_c_ready = coupler_to_bus_named_coh_widget_anonIn_c_ready; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_anonOut_c_valid = coupler_to_bus_named_coh_widget_anonIn_c_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonOut_c_bits_opcode = coupler_to_bus_named_coh_widget_anonIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonOut_c_bits_param = coupler_to_bus_named_coh_widget_anonIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonOut_c_bits_size = coupler_to_bus_named_coh_widget_anonIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonOut_c_bits_source = coupler_to_bus_named_coh_widget_anonIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonOut_c_bits_address = coupler_to_bus_named_coh_widget_anonIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonOut_c_bits_data = coupler_to_bus_named_coh_widget_anonIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonOut_c_bits_corrupt = coupler_to_bus_named_coh_widget_anonIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonOut_d_ready = coupler_to_bus_named_coh_widget_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_auto_anon_in_d_valid = coupler_to_bus_named_coh_widget_anonIn_d_valid; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_opcode = coupler_to_bus_named_coh_widget_anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_param = coupler_to_bus_named_coh_widget_anonIn_d_bits_param; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_size = coupler_to_bus_named_coh_widget_anonIn_d_bits_size; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_source = coupler_to_bus_named_coh_widget_anonIn_d_bits_source; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_sink = coupler_to_bus_named_coh_widget_anonIn_d_bits_sink; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_denied = coupler_to_bus_named_coh_widget_anonIn_d_bits_denied; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_data = coupler_to_bus_named_coh_widget_anonIn_d_bits_data; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_corrupt = coupler_to_bus_named_coh_widget_anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_coh_widget_anonOut_e_valid = coupler_to_bus_named_coh_widget_anonIn_e_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_coh_widget_anonOut_e_bits_sink = coupler_to_bus_named_coh_widget_anonIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_x1_tlMasterClockXingIn_a_ready; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_ready_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_a_ready; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_x1_tlMasterClockXingIn_a_valid = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_a_valid; // @[MixedNode.scala:551:17]
wire [2:0] coupler_from_rockettile_x1_tlMasterClockXingIn_a_bits_opcode = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_a_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] coupler_from_rockettile_x1_tlMasterClockXingIn_a_bits_param = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_a_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] coupler_from_rockettile_x1_tlMasterClockXingIn_a_bits_size = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_a_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] coupler_from_rockettile_x1_tlMasterClockXingIn_a_bits_source = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_a_bits_source; // @[MixedNode.scala:551:17]
wire [31:0] coupler_from_rockettile_x1_tlMasterClockXingIn_a_bits_address = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_a_bits_address; // @[MixedNode.scala:551:17]
wire [15:0] coupler_from_rockettile_x1_tlMasterClockXingIn_a_bits_mask = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_a_bits_mask; // @[MixedNode.scala:551:17]
wire [127:0] coupler_from_rockettile_x1_tlMasterClockXingIn_a_bits_data = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_a_bits_data; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_x1_tlMasterClockXingIn_a_bits_corrupt = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_a_bits_corrupt; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_x1_tlMasterClockXingIn_b_ready = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_b_ready; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_x1_tlMasterClockXingIn_b_valid; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_valid_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_b_valid; // @[ClockDomain.scala:14:9]
wire [1:0] coupler_from_rockettile_x1_tlMasterClockXingIn_b_bits_param; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_param_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_b_bits_param; // @[ClockDomain.scala:14:9]
wire [31:0] coupler_from_rockettile_x1_tlMasterClockXingIn_b_bits_address; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_address_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_b_bits_address; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_x1_tlMasterClockXingIn_c_ready; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_ready_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_c_ready; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_x1_tlMasterClockXingIn_c_valid = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_c_valid; // @[MixedNode.scala:551:17]
wire [2:0] coupler_from_rockettile_x1_tlMasterClockXingIn_c_bits_opcode = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_c_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] coupler_from_rockettile_x1_tlMasterClockXingIn_c_bits_param = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_c_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] coupler_from_rockettile_x1_tlMasterClockXingIn_c_bits_size = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_c_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] coupler_from_rockettile_x1_tlMasterClockXingIn_c_bits_source = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_c_bits_source; // @[MixedNode.scala:551:17]
wire [31:0] coupler_from_rockettile_x1_tlMasterClockXingIn_c_bits_address = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_c_bits_address; // @[MixedNode.scala:551:17]
wire [127:0] coupler_from_rockettile_x1_tlMasterClockXingIn_c_bits_data = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_c_bits_data; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_x1_tlMasterClockXingIn_c_bits_corrupt = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_c_bits_corrupt; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_x1_tlMasterClockXingIn_d_ready = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_d_ready; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_x1_tlMasterClockXingIn_d_valid; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_valid_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_d_valid; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_from_rockettile_x1_tlMasterClockXingIn_d_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_opcode_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_d_bits_opcode; // @[ClockDomain.scala:14:9]
wire [1:0] coupler_from_rockettile_x1_tlMasterClockXingIn_d_bits_param; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_param_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_d_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] coupler_from_rockettile_x1_tlMasterClockXingIn_d_bits_size; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_size_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_d_bits_size; // @[ClockDomain.scala:14:9]
wire [1:0] coupler_from_rockettile_x1_tlMasterClockXingIn_d_bits_source; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_source_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_d_bits_source; // @[ClockDomain.scala:14:9]
wire [3:0] coupler_from_rockettile_x1_tlMasterClockXingIn_d_bits_sink; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_sink_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_d_bits_sink; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_x1_tlMasterClockXingIn_d_bits_denied; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_denied_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_d_bits_denied; // @[ClockDomain.scala:14:9]
wire [127:0] coupler_from_rockettile_x1_tlMasterClockXingIn_d_bits_data; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_data_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_d_bits_data; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_x1_tlMasterClockXingIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_corrupt_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_d_bits_corrupt; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_x1_tlMasterClockXingIn_e_valid = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_e_valid; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_tlMasterClockXingIn_a_ready; // @[MixedNode.scala:551:17]
wire [3:0] coupler_from_rockettile_x1_tlMasterClockXingIn_e_bits_sink = coupler_from_rockettile_auto_tl_master_clock_xing_in_1_e_bits_sink; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_ready_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_0_a_ready; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_tlMasterClockXingIn_a_valid = coupler_from_rockettile_auto_tl_master_clock_xing_in_0_a_valid; // @[MixedNode.scala:551:17]
wire [2:0] coupler_from_rockettile_tlMasterClockXingIn_a_bits_opcode = coupler_from_rockettile_auto_tl_master_clock_xing_in_0_a_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] coupler_from_rockettile_tlMasterClockXingIn_a_bits_param = coupler_from_rockettile_auto_tl_master_clock_xing_in_0_a_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] coupler_from_rockettile_tlMasterClockXingIn_a_bits_size = coupler_from_rockettile_auto_tl_master_clock_xing_in_0_a_bits_size; // @[MixedNode.scala:551:17]
wire [4:0] coupler_from_rockettile_tlMasterClockXingIn_a_bits_source = coupler_from_rockettile_auto_tl_master_clock_xing_in_0_a_bits_source; // @[MixedNode.scala:551:17]
wire [31:0] coupler_from_rockettile_tlMasterClockXingIn_a_bits_address = coupler_from_rockettile_auto_tl_master_clock_xing_in_0_a_bits_address; // @[MixedNode.scala:551:17]
wire [15:0] coupler_from_rockettile_tlMasterClockXingIn_a_bits_mask = coupler_from_rockettile_auto_tl_master_clock_xing_in_0_a_bits_mask; // @[MixedNode.scala:551:17]
wire [127:0] coupler_from_rockettile_tlMasterClockXingIn_a_bits_data = coupler_from_rockettile_auto_tl_master_clock_xing_in_0_a_bits_data; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_tlMasterClockXingIn_a_bits_corrupt = coupler_from_rockettile_auto_tl_master_clock_xing_in_0_a_bits_corrupt; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_tlMasterClockXingIn_d_ready = coupler_from_rockettile_auto_tl_master_clock_xing_in_0_d_ready; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_tlMasterClockXingIn_d_valid; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_valid_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_0_d_valid; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_from_rockettile_tlMasterClockXingIn_d_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_opcode_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_0_d_bits_opcode; // @[ClockDomain.scala:14:9]
wire [1:0] coupler_from_rockettile_tlMasterClockXingIn_d_bits_param; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_param_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_0_d_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] coupler_from_rockettile_tlMasterClockXingIn_d_bits_size; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_size_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_0_d_bits_size; // @[ClockDomain.scala:14:9]
wire [4:0] coupler_from_rockettile_tlMasterClockXingIn_d_bits_source; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_source_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_0_d_bits_source; // @[ClockDomain.scala:14:9]
wire [3:0] coupler_from_rockettile_tlMasterClockXingIn_d_bits_sink; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_sink_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_0_d_bits_sink; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_tlMasterClockXingIn_d_bits_denied; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_denied_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_0_d_bits_denied; // @[ClockDomain.scala:14:9]
wire [127:0] coupler_from_rockettile_tlMasterClockXingIn_d_bits_data; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_data_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_0_d_bits_data; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_tlMasterClockXingIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_corrupt_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_0_d_bits_corrupt; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_x1_tlOut_a_ready = coupler_from_rockettile_auto_tl_out_1_a_ready; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_x1_tlOut_a_valid; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_2_a_valid = coupler_from_rockettile_auto_tl_out_1_a_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] coupler_from_rockettile_x1_tlOut_a_bits_opcode; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_2_a_bits_opcode = coupler_from_rockettile_auto_tl_out_1_a_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [2:0] coupler_from_rockettile_x1_tlOut_a_bits_param; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_2_a_bits_param = coupler_from_rockettile_auto_tl_out_1_a_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] coupler_from_rockettile_x1_tlOut_a_bits_size; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_2_a_bits_size = coupler_from_rockettile_auto_tl_out_1_a_bits_size; // @[FIFOFixer.scala:50:9]
wire [1:0] coupler_from_rockettile_x1_tlOut_a_bits_source; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_2_a_bits_source = coupler_from_rockettile_auto_tl_out_1_a_bits_source; // @[FIFOFixer.scala:50:9]
wire [31:0] coupler_from_rockettile_x1_tlOut_a_bits_address; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_2_a_bits_address = coupler_from_rockettile_auto_tl_out_1_a_bits_address; // @[FIFOFixer.scala:50:9]
wire [15:0] coupler_from_rockettile_x1_tlOut_a_bits_mask; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_2_a_bits_mask = coupler_from_rockettile_auto_tl_out_1_a_bits_mask; // @[FIFOFixer.scala:50:9]
wire [127:0] coupler_from_rockettile_x1_tlOut_a_bits_data; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_2_a_bits_data = coupler_from_rockettile_auto_tl_out_1_a_bits_data; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_x1_tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_2_a_bits_corrupt = coupler_from_rockettile_auto_tl_out_1_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_x1_tlOut_b_ready; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_2_b_ready = coupler_from_rockettile_auto_tl_out_1_b_ready; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_x1_tlOut_b_valid = coupler_from_rockettile_auto_tl_out_1_b_valid; // @[MixedNode.scala:542:17]
wire [1:0] coupler_from_rockettile_x1_tlOut_b_bits_param = coupler_from_rockettile_auto_tl_out_1_b_bits_param; // @[MixedNode.scala:542:17]
wire [31:0] coupler_from_rockettile_x1_tlOut_b_bits_address = coupler_from_rockettile_auto_tl_out_1_b_bits_address; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_x1_tlOut_c_ready = coupler_from_rockettile_auto_tl_out_1_c_ready; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_x1_tlOut_c_valid; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_2_c_valid = coupler_from_rockettile_auto_tl_out_1_c_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] coupler_from_rockettile_x1_tlOut_c_bits_opcode; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_2_c_bits_opcode = coupler_from_rockettile_auto_tl_out_1_c_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [2:0] coupler_from_rockettile_x1_tlOut_c_bits_param; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_2_c_bits_param = coupler_from_rockettile_auto_tl_out_1_c_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] coupler_from_rockettile_x1_tlOut_c_bits_size; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_2_c_bits_size = coupler_from_rockettile_auto_tl_out_1_c_bits_size; // @[FIFOFixer.scala:50:9]
wire [1:0] coupler_from_rockettile_x1_tlOut_c_bits_source; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_2_c_bits_source = coupler_from_rockettile_auto_tl_out_1_c_bits_source; // @[FIFOFixer.scala:50:9]
wire [31:0] coupler_from_rockettile_x1_tlOut_c_bits_address; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_2_c_bits_address = coupler_from_rockettile_auto_tl_out_1_c_bits_address; // @[FIFOFixer.scala:50:9]
wire [127:0] coupler_from_rockettile_x1_tlOut_c_bits_data; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_2_c_bits_data = coupler_from_rockettile_auto_tl_out_1_c_bits_data; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_x1_tlOut_c_bits_corrupt; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_2_c_bits_corrupt = coupler_from_rockettile_auto_tl_out_1_c_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_x1_tlOut_d_ready; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_2_d_ready = coupler_from_rockettile_auto_tl_out_1_d_ready; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_x1_tlOut_d_valid = coupler_from_rockettile_auto_tl_out_1_d_valid; // @[MixedNode.scala:542:17]
wire [2:0] coupler_from_rockettile_x1_tlOut_d_bits_opcode = coupler_from_rockettile_auto_tl_out_1_d_bits_opcode; // @[MixedNode.scala:542:17]
wire [1:0] coupler_from_rockettile_x1_tlOut_d_bits_param = coupler_from_rockettile_auto_tl_out_1_d_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] coupler_from_rockettile_x1_tlOut_d_bits_size = coupler_from_rockettile_auto_tl_out_1_d_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] coupler_from_rockettile_x1_tlOut_d_bits_source = coupler_from_rockettile_auto_tl_out_1_d_bits_source; // @[MixedNode.scala:542:17]
wire [3:0] coupler_from_rockettile_x1_tlOut_d_bits_sink = coupler_from_rockettile_auto_tl_out_1_d_bits_sink; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_x1_tlOut_d_bits_denied = coupler_from_rockettile_auto_tl_out_1_d_bits_denied; // @[MixedNode.scala:542:17]
wire [127:0] coupler_from_rockettile_x1_tlOut_d_bits_data = coupler_from_rockettile_auto_tl_out_1_d_bits_data; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_x1_tlOut_d_bits_corrupt = coupler_from_rockettile_auto_tl_out_1_d_bits_corrupt; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_x1_tlOut_e_valid; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_2_e_valid = coupler_from_rockettile_auto_tl_out_1_e_valid; // @[FIFOFixer.scala:50:9]
wire [3:0] coupler_from_rockettile_x1_tlOut_e_bits_sink; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_2_e_bits_sink = coupler_from_rockettile_auto_tl_out_1_e_bits_sink; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_tlOut_a_ready = coupler_from_rockettile_auto_tl_out_0_a_ready; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_tlOut_a_valid; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_1_a_valid = coupler_from_rockettile_auto_tl_out_0_a_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] coupler_from_rockettile_tlOut_a_bits_opcode; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_1_a_bits_opcode = coupler_from_rockettile_auto_tl_out_0_a_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [2:0] coupler_from_rockettile_tlOut_a_bits_param; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_1_a_bits_param = coupler_from_rockettile_auto_tl_out_0_a_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] coupler_from_rockettile_tlOut_a_bits_size; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_1_a_bits_size = coupler_from_rockettile_auto_tl_out_0_a_bits_size; // @[FIFOFixer.scala:50:9]
wire [4:0] coupler_from_rockettile_tlOut_a_bits_source; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_1_a_bits_source = coupler_from_rockettile_auto_tl_out_0_a_bits_source; // @[FIFOFixer.scala:50:9]
wire [31:0] coupler_from_rockettile_tlOut_a_bits_address; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_1_a_bits_address = coupler_from_rockettile_auto_tl_out_0_a_bits_address; // @[FIFOFixer.scala:50:9]
wire [15:0] coupler_from_rockettile_tlOut_a_bits_mask; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_1_a_bits_mask = coupler_from_rockettile_auto_tl_out_0_a_bits_mask; // @[FIFOFixer.scala:50:9]
wire [127:0] coupler_from_rockettile_tlOut_a_bits_data; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_1_a_bits_data = coupler_from_rockettile_auto_tl_out_0_a_bits_data; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_1_a_bits_corrupt = coupler_from_rockettile_auto_tl_out_0_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_tlOut_d_ready; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_1_d_ready = coupler_from_rockettile_auto_tl_out_0_d_ready; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_tlOut_d_valid = coupler_from_rockettile_auto_tl_out_0_d_valid; // @[MixedNode.scala:542:17]
wire [2:0] coupler_from_rockettile_tlOut_d_bits_opcode = coupler_from_rockettile_auto_tl_out_0_d_bits_opcode; // @[MixedNode.scala:542:17]
wire [1:0] coupler_from_rockettile_tlOut_d_bits_param = coupler_from_rockettile_auto_tl_out_0_d_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] coupler_from_rockettile_tlOut_d_bits_size = coupler_from_rockettile_auto_tl_out_0_d_bits_size; // @[MixedNode.scala:542:17]
wire [4:0] coupler_from_rockettile_tlOut_d_bits_source = coupler_from_rockettile_auto_tl_out_0_d_bits_source; // @[MixedNode.scala:542:17]
wire [3:0] coupler_from_rockettile_tlOut_d_bits_sink = coupler_from_rockettile_auto_tl_out_0_d_bits_sink; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_tlOut_d_bits_denied = coupler_from_rockettile_auto_tl_out_0_d_bits_denied; // @[MixedNode.scala:542:17]
wire [127:0] coupler_from_rockettile_tlOut_d_bits_data = coupler_from_rockettile_auto_tl_out_0_d_bits_data; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_tlOut_d_bits_corrupt = coupler_from_rockettile_auto_tl_out_0_d_bits_corrupt; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_tlIn_a_ready = coupler_from_rockettile_tlOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_tlIn_a_valid; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_out_0_a_valid = coupler_from_rockettile_tlOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] coupler_from_rockettile_tlIn_a_bits_opcode; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_out_0_a_bits_opcode = coupler_from_rockettile_tlOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] coupler_from_rockettile_tlIn_a_bits_param; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_out_0_a_bits_param = coupler_from_rockettile_tlOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] coupler_from_rockettile_tlIn_a_bits_size; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_out_0_a_bits_size = coupler_from_rockettile_tlOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [4:0] coupler_from_rockettile_tlIn_a_bits_source; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_out_0_a_bits_source = coupler_from_rockettile_tlOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] coupler_from_rockettile_tlIn_a_bits_address; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_out_0_a_bits_address = coupler_from_rockettile_tlOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [15:0] coupler_from_rockettile_tlIn_a_bits_mask; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_out_0_a_bits_mask = coupler_from_rockettile_tlOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [127:0] coupler_from_rockettile_tlIn_a_bits_data; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_out_0_a_bits_data = coupler_from_rockettile_tlOut_a_bits_data; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_tlIn_a_bits_corrupt; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_out_0_a_bits_corrupt = coupler_from_rockettile_tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_tlIn_d_ready; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_out_0_d_ready = coupler_from_rockettile_tlOut_d_ready; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_tlIn_d_valid = coupler_from_rockettile_tlOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_tlIn_d_bits_opcode = coupler_from_rockettile_tlOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_tlIn_d_bits_param = coupler_from_rockettile_tlOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_tlIn_d_bits_size = coupler_from_rockettile_tlOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [4:0] coupler_from_rockettile_tlIn_d_bits_source = coupler_from_rockettile_tlOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_tlIn_d_bits_sink = coupler_from_rockettile_tlOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_tlIn_d_bits_denied = coupler_from_rockettile_tlOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [127:0] coupler_from_rockettile_tlIn_d_bits_data = coupler_from_rockettile_tlOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_tlIn_d_bits_corrupt = coupler_from_rockettile_tlOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_x1_tlIn_a_ready = coupler_from_rockettile_x1_tlOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_x1_tlIn_a_valid; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_out_1_a_valid = coupler_from_rockettile_x1_tlOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] coupler_from_rockettile_x1_tlIn_a_bits_opcode; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_out_1_a_bits_opcode = coupler_from_rockettile_x1_tlOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] coupler_from_rockettile_x1_tlIn_a_bits_param; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_out_1_a_bits_param = coupler_from_rockettile_x1_tlOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] coupler_from_rockettile_x1_tlIn_a_bits_size; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_out_1_a_bits_size = coupler_from_rockettile_x1_tlOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] coupler_from_rockettile_x1_tlIn_a_bits_source; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_out_1_a_bits_source = coupler_from_rockettile_x1_tlOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] coupler_from_rockettile_x1_tlIn_a_bits_address; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_out_1_a_bits_address = coupler_from_rockettile_x1_tlOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [15:0] coupler_from_rockettile_x1_tlIn_a_bits_mask; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_out_1_a_bits_mask = coupler_from_rockettile_x1_tlOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [127:0] coupler_from_rockettile_x1_tlIn_a_bits_data; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_out_1_a_bits_data = coupler_from_rockettile_x1_tlOut_a_bits_data; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_x1_tlIn_a_bits_corrupt; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_out_1_a_bits_corrupt = coupler_from_rockettile_x1_tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_x1_tlIn_b_ready; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_out_1_b_ready = coupler_from_rockettile_x1_tlOut_b_ready; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_x1_tlIn_b_valid = coupler_from_rockettile_x1_tlOut_b_valid; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_x1_tlIn_b_bits_param = coupler_from_rockettile_x1_tlOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] coupler_from_rockettile_x1_tlIn_b_bits_address = coupler_from_rockettile_x1_tlOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_x1_tlIn_c_ready = coupler_from_rockettile_x1_tlOut_c_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_x1_tlIn_c_valid; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_out_1_c_valid = coupler_from_rockettile_x1_tlOut_c_valid; // @[MixedNode.scala:542:17]
wire [2:0] coupler_from_rockettile_x1_tlIn_c_bits_opcode; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_out_1_c_bits_opcode = coupler_from_rockettile_x1_tlOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] coupler_from_rockettile_x1_tlIn_c_bits_param; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_out_1_c_bits_param = coupler_from_rockettile_x1_tlOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] coupler_from_rockettile_x1_tlIn_c_bits_size; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_out_1_c_bits_size = coupler_from_rockettile_x1_tlOut_c_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] coupler_from_rockettile_x1_tlIn_c_bits_source; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_out_1_c_bits_source = coupler_from_rockettile_x1_tlOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] coupler_from_rockettile_x1_tlIn_c_bits_address; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_out_1_c_bits_address = coupler_from_rockettile_x1_tlOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [127:0] coupler_from_rockettile_x1_tlIn_c_bits_data; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_out_1_c_bits_data = coupler_from_rockettile_x1_tlOut_c_bits_data; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_x1_tlIn_c_bits_corrupt; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_out_1_c_bits_corrupt = coupler_from_rockettile_x1_tlOut_c_bits_corrupt; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_x1_tlIn_d_ready; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_out_1_d_ready = coupler_from_rockettile_x1_tlOut_d_ready; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_x1_tlIn_d_valid = coupler_from_rockettile_x1_tlOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_x1_tlIn_d_bits_opcode = coupler_from_rockettile_x1_tlOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_x1_tlIn_d_bits_param = coupler_from_rockettile_x1_tlOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_x1_tlIn_d_bits_size = coupler_from_rockettile_x1_tlOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_x1_tlIn_d_bits_source = coupler_from_rockettile_x1_tlOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_x1_tlIn_d_bits_sink = coupler_from_rockettile_x1_tlOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_x1_tlIn_d_bits_denied = coupler_from_rockettile_x1_tlOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [127:0] coupler_from_rockettile_x1_tlIn_d_bits_data = coupler_from_rockettile_x1_tlOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_x1_tlIn_d_bits_corrupt = coupler_from_rockettile_x1_tlOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_x1_tlIn_e_valid; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_out_1_e_valid = coupler_from_rockettile_x1_tlOut_e_valid; // @[MixedNode.scala:542:17]
wire [3:0] coupler_from_rockettile_x1_tlIn_e_bits_sink; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_out_1_e_bits_sink = coupler_from_rockettile_x1_tlOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_no_bufferOut_a_ready = coupler_from_rockettile_tlIn_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_no_bufferOut_a_valid; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_tlOut_a_valid = coupler_from_rockettile_tlIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_no_bufferOut_a_bits_opcode; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_tlOut_a_bits_opcode = coupler_from_rockettile_tlIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_no_bufferOut_a_bits_param; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_tlOut_a_bits_param = coupler_from_rockettile_tlIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_no_bufferOut_a_bits_size; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_tlOut_a_bits_size = coupler_from_rockettile_tlIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [4:0] coupler_from_rockettile_no_bufferOut_a_bits_source; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_tlOut_a_bits_source = coupler_from_rockettile_tlIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] coupler_from_rockettile_no_bufferOut_a_bits_address; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_tlOut_a_bits_address = coupler_from_rockettile_tlIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [15:0] coupler_from_rockettile_no_bufferOut_a_bits_mask; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_tlOut_a_bits_mask = coupler_from_rockettile_tlIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
wire [127:0] coupler_from_rockettile_no_bufferOut_a_bits_data; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_tlOut_a_bits_data = coupler_from_rockettile_tlIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_no_bufferOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_tlOut_a_bits_corrupt = coupler_from_rockettile_tlIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_no_bufferOut_d_ready; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_tlOut_d_ready = coupler_from_rockettile_tlIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_no_bufferOut_d_valid = coupler_from_rockettile_tlIn_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_no_bufferOut_d_bits_opcode = coupler_from_rockettile_tlIn_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_no_bufferOut_d_bits_param = coupler_from_rockettile_tlIn_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_no_bufferOut_d_bits_size = coupler_from_rockettile_tlIn_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [4:0] coupler_from_rockettile_no_bufferOut_d_bits_source = coupler_from_rockettile_tlIn_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_no_bufferOut_d_bits_sink = coupler_from_rockettile_tlIn_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_no_bufferOut_d_bits_denied = coupler_from_rockettile_tlIn_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [127:0] coupler_from_rockettile_no_bufferOut_d_bits_data = coupler_from_rockettile_tlIn_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_no_bufferOut_d_bits_corrupt = coupler_from_rockettile_tlIn_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_x1_no_bufferOut_a_ready = coupler_from_rockettile_x1_tlIn_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_x1_no_bufferOut_a_valid; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_x1_tlOut_a_valid = coupler_from_rockettile_x1_tlIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_x1_no_bufferOut_a_bits_opcode; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_x1_tlOut_a_bits_opcode = coupler_from_rockettile_x1_tlIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_x1_no_bufferOut_a_bits_param; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_x1_tlOut_a_bits_param = coupler_from_rockettile_x1_tlIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_x1_no_bufferOut_a_bits_size; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_x1_tlOut_a_bits_size = coupler_from_rockettile_x1_tlIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_x1_no_bufferOut_a_bits_source; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_x1_tlOut_a_bits_source = coupler_from_rockettile_x1_tlIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] coupler_from_rockettile_x1_no_bufferOut_a_bits_address; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_x1_tlOut_a_bits_address = coupler_from_rockettile_x1_tlIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [15:0] coupler_from_rockettile_x1_no_bufferOut_a_bits_mask; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_x1_tlOut_a_bits_mask = coupler_from_rockettile_x1_tlIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
wire [127:0] coupler_from_rockettile_x1_no_bufferOut_a_bits_data; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_x1_tlOut_a_bits_data = coupler_from_rockettile_x1_tlIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_x1_no_bufferOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_x1_tlOut_a_bits_corrupt = coupler_from_rockettile_x1_tlIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_x1_no_bufferOut_b_ready; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_x1_tlOut_b_ready = coupler_from_rockettile_x1_tlIn_b_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_x1_no_bufferOut_b_valid = coupler_from_rockettile_x1_tlIn_b_valid; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_x1_no_bufferOut_b_bits_param = coupler_from_rockettile_x1_tlIn_b_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] coupler_from_rockettile_x1_no_bufferOut_b_bits_address = coupler_from_rockettile_x1_tlIn_b_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_x1_no_bufferOut_c_ready = coupler_from_rockettile_x1_tlIn_c_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_x1_no_bufferOut_c_valid; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_x1_tlOut_c_valid = coupler_from_rockettile_x1_tlIn_c_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_x1_no_bufferOut_c_bits_opcode; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_x1_tlOut_c_bits_opcode = coupler_from_rockettile_x1_tlIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_x1_no_bufferOut_c_bits_param; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_x1_tlOut_c_bits_param = coupler_from_rockettile_x1_tlIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_x1_no_bufferOut_c_bits_size; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_x1_tlOut_c_bits_size = coupler_from_rockettile_x1_tlIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_x1_no_bufferOut_c_bits_source; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_x1_tlOut_c_bits_source = coupler_from_rockettile_x1_tlIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] coupler_from_rockettile_x1_no_bufferOut_c_bits_address; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_x1_tlOut_c_bits_address = coupler_from_rockettile_x1_tlIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [127:0] coupler_from_rockettile_x1_no_bufferOut_c_bits_data; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_x1_tlOut_c_bits_data = coupler_from_rockettile_x1_tlIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_x1_no_bufferOut_c_bits_corrupt; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_x1_tlOut_c_bits_corrupt = coupler_from_rockettile_x1_tlIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_x1_no_bufferOut_d_ready; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_x1_tlOut_d_ready = coupler_from_rockettile_x1_tlIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_x1_no_bufferOut_d_valid = coupler_from_rockettile_x1_tlIn_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_x1_no_bufferOut_d_bits_opcode = coupler_from_rockettile_x1_tlIn_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_x1_no_bufferOut_d_bits_param = coupler_from_rockettile_x1_tlIn_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_x1_no_bufferOut_d_bits_size = coupler_from_rockettile_x1_tlIn_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_x1_no_bufferOut_d_bits_source = coupler_from_rockettile_x1_tlIn_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_x1_no_bufferOut_d_bits_sink = coupler_from_rockettile_x1_tlIn_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_x1_no_bufferOut_d_bits_denied = coupler_from_rockettile_x1_tlIn_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [127:0] coupler_from_rockettile_x1_no_bufferOut_d_bits_data = coupler_from_rockettile_x1_tlIn_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_x1_no_bufferOut_d_bits_corrupt = coupler_from_rockettile_x1_tlIn_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_x1_no_bufferOut_e_valid; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_x1_tlOut_e_valid = coupler_from_rockettile_x1_tlIn_e_valid; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_x1_no_bufferOut_e_bits_sink; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_x1_tlOut_e_bits_sink = coupler_from_rockettile_x1_tlIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_no_bufferIn_a_ready = coupler_from_rockettile_no_bufferOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_no_bufferIn_a_valid; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_tlIn_a_valid = coupler_from_rockettile_no_bufferOut_a_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_no_bufferIn_a_bits_opcode; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_tlIn_a_bits_opcode = coupler_from_rockettile_no_bufferOut_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_no_bufferIn_a_bits_param; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_tlIn_a_bits_param = coupler_from_rockettile_no_bufferOut_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_no_bufferIn_a_bits_size; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_tlIn_a_bits_size = coupler_from_rockettile_no_bufferOut_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [4:0] coupler_from_rockettile_no_bufferIn_a_bits_source; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_tlIn_a_bits_source = coupler_from_rockettile_no_bufferOut_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] coupler_from_rockettile_no_bufferIn_a_bits_address; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_tlIn_a_bits_address = coupler_from_rockettile_no_bufferOut_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [15:0] coupler_from_rockettile_no_bufferIn_a_bits_mask; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_tlIn_a_bits_mask = coupler_from_rockettile_no_bufferOut_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
wire [127:0] coupler_from_rockettile_no_bufferIn_a_bits_data; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_tlIn_a_bits_data = coupler_from_rockettile_no_bufferOut_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_no_bufferIn_a_bits_corrupt; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_tlIn_a_bits_corrupt = coupler_from_rockettile_no_bufferOut_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_no_bufferIn_d_ready; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_tlIn_d_ready = coupler_from_rockettile_no_bufferOut_d_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_no_bufferIn_d_valid = coupler_from_rockettile_no_bufferOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_no_bufferIn_d_bits_opcode = coupler_from_rockettile_no_bufferOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_no_bufferIn_d_bits_param = coupler_from_rockettile_no_bufferOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_no_bufferIn_d_bits_size = coupler_from_rockettile_no_bufferOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [4:0] coupler_from_rockettile_no_bufferIn_d_bits_source = coupler_from_rockettile_no_bufferOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_no_bufferIn_d_bits_sink = coupler_from_rockettile_no_bufferOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_no_bufferIn_d_bits_denied = coupler_from_rockettile_no_bufferOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [127:0] coupler_from_rockettile_no_bufferIn_d_bits_data = coupler_from_rockettile_no_bufferOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_no_bufferIn_d_bits_corrupt = coupler_from_rockettile_no_bufferOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_x1_no_bufferIn_a_ready = coupler_from_rockettile_x1_no_bufferOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_x1_no_bufferIn_a_valid; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_x1_tlIn_a_valid = coupler_from_rockettile_x1_no_bufferOut_a_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_x1_no_bufferIn_a_bits_opcode; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_x1_tlIn_a_bits_opcode = coupler_from_rockettile_x1_no_bufferOut_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_x1_no_bufferIn_a_bits_param; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_x1_tlIn_a_bits_param = coupler_from_rockettile_x1_no_bufferOut_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_x1_no_bufferIn_a_bits_size; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_x1_tlIn_a_bits_size = coupler_from_rockettile_x1_no_bufferOut_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_x1_no_bufferIn_a_bits_source; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_x1_tlIn_a_bits_source = coupler_from_rockettile_x1_no_bufferOut_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] coupler_from_rockettile_x1_no_bufferIn_a_bits_address; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_x1_tlIn_a_bits_address = coupler_from_rockettile_x1_no_bufferOut_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [15:0] coupler_from_rockettile_x1_no_bufferIn_a_bits_mask; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_x1_tlIn_a_bits_mask = coupler_from_rockettile_x1_no_bufferOut_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
wire [127:0] coupler_from_rockettile_x1_no_bufferIn_a_bits_data; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_x1_tlIn_a_bits_data = coupler_from_rockettile_x1_no_bufferOut_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_x1_no_bufferIn_a_bits_corrupt; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_x1_tlIn_a_bits_corrupt = coupler_from_rockettile_x1_no_bufferOut_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_x1_no_bufferIn_b_ready; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_x1_tlIn_b_ready = coupler_from_rockettile_x1_no_bufferOut_b_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_x1_no_bufferIn_b_valid = coupler_from_rockettile_x1_no_bufferOut_b_valid; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_x1_no_bufferIn_b_bits_param = coupler_from_rockettile_x1_no_bufferOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] coupler_from_rockettile_x1_no_bufferIn_b_bits_address = coupler_from_rockettile_x1_no_bufferOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_x1_no_bufferIn_c_ready = coupler_from_rockettile_x1_no_bufferOut_c_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_x1_no_bufferIn_c_valid; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_x1_tlIn_c_valid = coupler_from_rockettile_x1_no_bufferOut_c_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_x1_no_bufferIn_c_bits_opcode; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_x1_tlIn_c_bits_opcode = coupler_from_rockettile_x1_no_bufferOut_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_x1_no_bufferIn_c_bits_param; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_x1_tlIn_c_bits_param = coupler_from_rockettile_x1_no_bufferOut_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_x1_no_bufferIn_c_bits_size; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_x1_tlIn_c_bits_size = coupler_from_rockettile_x1_no_bufferOut_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_x1_no_bufferIn_c_bits_source; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_x1_tlIn_c_bits_source = coupler_from_rockettile_x1_no_bufferOut_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] coupler_from_rockettile_x1_no_bufferIn_c_bits_address; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_x1_tlIn_c_bits_address = coupler_from_rockettile_x1_no_bufferOut_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [127:0] coupler_from_rockettile_x1_no_bufferIn_c_bits_data; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_x1_tlIn_c_bits_data = coupler_from_rockettile_x1_no_bufferOut_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_x1_no_bufferIn_c_bits_corrupt; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_x1_tlIn_c_bits_corrupt = coupler_from_rockettile_x1_no_bufferOut_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_x1_no_bufferIn_d_ready; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_x1_tlIn_d_ready = coupler_from_rockettile_x1_no_bufferOut_d_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_x1_no_bufferIn_d_valid = coupler_from_rockettile_x1_no_bufferOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_x1_no_bufferIn_d_bits_opcode = coupler_from_rockettile_x1_no_bufferOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_x1_no_bufferIn_d_bits_param = coupler_from_rockettile_x1_no_bufferOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_x1_no_bufferIn_d_bits_size = coupler_from_rockettile_x1_no_bufferOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_x1_no_bufferIn_d_bits_source = coupler_from_rockettile_x1_no_bufferOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_x1_no_bufferIn_d_bits_sink = coupler_from_rockettile_x1_no_bufferOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_x1_no_bufferIn_d_bits_denied = coupler_from_rockettile_x1_no_bufferOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [127:0] coupler_from_rockettile_x1_no_bufferIn_d_bits_data = coupler_from_rockettile_x1_no_bufferOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_x1_no_bufferIn_d_bits_corrupt = coupler_from_rockettile_x1_no_bufferOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_x1_no_bufferIn_e_valid; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_x1_tlIn_e_valid = coupler_from_rockettile_x1_no_bufferOut_e_valid; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_x1_no_bufferIn_e_bits_sink; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_x1_tlIn_e_bits_sink = coupler_from_rockettile_x1_no_bufferOut_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_tlMasterClockXingOut_a_ready = coupler_from_rockettile_no_bufferIn_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_tlMasterClockXingOut_a_valid; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_no_bufferOut_a_valid = coupler_from_rockettile_no_bufferIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_tlMasterClockXingOut_a_bits_opcode; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_no_bufferOut_a_bits_opcode = coupler_from_rockettile_no_bufferIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_tlMasterClockXingOut_a_bits_param; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_no_bufferOut_a_bits_param = coupler_from_rockettile_no_bufferIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_tlMasterClockXingOut_a_bits_size; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_no_bufferOut_a_bits_size = coupler_from_rockettile_no_bufferIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [4:0] coupler_from_rockettile_tlMasterClockXingOut_a_bits_source; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_no_bufferOut_a_bits_source = coupler_from_rockettile_no_bufferIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] coupler_from_rockettile_tlMasterClockXingOut_a_bits_address; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_no_bufferOut_a_bits_address = coupler_from_rockettile_no_bufferIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [15:0] coupler_from_rockettile_tlMasterClockXingOut_a_bits_mask; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_no_bufferOut_a_bits_mask = coupler_from_rockettile_no_bufferIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
wire [127:0] coupler_from_rockettile_tlMasterClockXingOut_a_bits_data; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_no_bufferOut_a_bits_data = coupler_from_rockettile_no_bufferIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_tlMasterClockXingOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_no_bufferOut_a_bits_corrupt = coupler_from_rockettile_no_bufferIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_tlMasterClockXingOut_d_ready; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_no_bufferOut_d_ready = coupler_from_rockettile_no_bufferIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_tlMasterClockXingOut_d_valid = coupler_from_rockettile_no_bufferIn_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_tlMasterClockXingOut_d_bits_opcode = coupler_from_rockettile_no_bufferIn_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_tlMasterClockXingOut_d_bits_param = coupler_from_rockettile_no_bufferIn_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_tlMasterClockXingOut_d_bits_size = coupler_from_rockettile_no_bufferIn_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [4:0] coupler_from_rockettile_tlMasterClockXingOut_d_bits_source = coupler_from_rockettile_no_bufferIn_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_tlMasterClockXingOut_d_bits_sink = coupler_from_rockettile_no_bufferIn_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_tlMasterClockXingOut_d_bits_denied = coupler_from_rockettile_no_bufferIn_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [127:0] coupler_from_rockettile_tlMasterClockXingOut_d_bits_data = coupler_from_rockettile_no_bufferIn_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_tlMasterClockXingOut_d_bits_corrupt = coupler_from_rockettile_no_bufferIn_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_x1_tlMasterClockXingOut_a_ready = coupler_from_rockettile_x1_no_bufferIn_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_x1_tlMasterClockXingOut_a_valid; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_x1_no_bufferOut_a_valid = coupler_from_rockettile_x1_no_bufferIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_x1_tlMasterClockXingOut_a_bits_opcode; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_x1_no_bufferOut_a_bits_opcode = coupler_from_rockettile_x1_no_bufferIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_x1_tlMasterClockXingOut_a_bits_param; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_x1_no_bufferOut_a_bits_param = coupler_from_rockettile_x1_no_bufferIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_x1_tlMasterClockXingOut_a_bits_size; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_x1_no_bufferOut_a_bits_size = coupler_from_rockettile_x1_no_bufferIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_x1_tlMasterClockXingOut_a_bits_source; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_x1_no_bufferOut_a_bits_source = coupler_from_rockettile_x1_no_bufferIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] coupler_from_rockettile_x1_tlMasterClockXingOut_a_bits_address; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_x1_no_bufferOut_a_bits_address = coupler_from_rockettile_x1_no_bufferIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [15:0] coupler_from_rockettile_x1_tlMasterClockXingOut_a_bits_mask; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_x1_no_bufferOut_a_bits_mask = coupler_from_rockettile_x1_no_bufferIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
wire [127:0] coupler_from_rockettile_x1_tlMasterClockXingOut_a_bits_data; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_x1_no_bufferOut_a_bits_data = coupler_from_rockettile_x1_no_bufferIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_x1_tlMasterClockXingOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_x1_no_bufferOut_a_bits_corrupt = coupler_from_rockettile_x1_no_bufferIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_x1_tlMasterClockXingOut_b_ready; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_x1_no_bufferOut_b_ready = coupler_from_rockettile_x1_no_bufferIn_b_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_x1_tlMasterClockXingOut_b_valid = coupler_from_rockettile_x1_no_bufferIn_b_valid; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_x1_tlMasterClockXingOut_b_bits_param = coupler_from_rockettile_x1_no_bufferIn_b_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] coupler_from_rockettile_x1_tlMasterClockXingOut_b_bits_address = coupler_from_rockettile_x1_no_bufferIn_b_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_x1_tlMasterClockXingOut_c_ready = coupler_from_rockettile_x1_no_bufferIn_c_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_x1_tlMasterClockXingOut_c_valid; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_x1_no_bufferOut_c_valid = coupler_from_rockettile_x1_no_bufferIn_c_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_x1_tlMasterClockXingOut_c_bits_opcode; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_x1_no_bufferOut_c_bits_opcode = coupler_from_rockettile_x1_no_bufferIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_x1_tlMasterClockXingOut_c_bits_param; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_x1_no_bufferOut_c_bits_param = coupler_from_rockettile_x1_no_bufferIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_x1_tlMasterClockXingOut_c_bits_size; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_x1_no_bufferOut_c_bits_size = coupler_from_rockettile_x1_no_bufferIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_x1_tlMasterClockXingOut_c_bits_source; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_x1_no_bufferOut_c_bits_source = coupler_from_rockettile_x1_no_bufferIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] coupler_from_rockettile_x1_tlMasterClockXingOut_c_bits_address; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_x1_no_bufferOut_c_bits_address = coupler_from_rockettile_x1_no_bufferIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [127:0] coupler_from_rockettile_x1_tlMasterClockXingOut_c_bits_data; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_x1_no_bufferOut_c_bits_data = coupler_from_rockettile_x1_no_bufferIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_x1_tlMasterClockXingOut_c_bits_corrupt; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_x1_no_bufferOut_c_bits_corrupt = coupler_from_rockettile_x1_no_bufferIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_x1_tlMasterClockXingOut_d_ready; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_x1_no_bufferOut_d_ready = coupler_from_rockettile_x1_no_bufferIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_x1_tlMasterClockXingOut_d_valid = coupler_from_rockettile_x1_no_bufferIn_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_x1_tlMasterClockXingOut_d_bits_opcode = coupler_from_rockettile_x1_no_bufferIn_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_x1_tlMasterClockXingOut_d_bits_param = coupler_from_rockettile_x1_no_bufferIn_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_x1_tlMasterClockXingOut_d_bits_size = coupler_from_rockettile_x1_no_bufferIn_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_x1_tlMasterClockXingOut_d_bits_source = coupler_from_rockettile_x1_no_bufferIn_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_x1_tlMasterClockXingOut_d_bits_sink = coupler_from_rockettile_x1_no_bufferIn_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_x1_tlMasterClockXingOut_d_bits_denied = coupler_from_rockettile_x1_no_bufferIn_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [127:0] coupler_from_rockettile_x1_tlMasterClockXingOut_d_bits_data = coupler_from_rockettile_x1_no_bufferIn_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_x1_tlMasterClockXingOut_d_bits_corrupt = coupler_from_rockettile_x1_no_bufferIn_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_x1_tlMasterClockXingOut_e_valid; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_x1_no_bufferOut_e_valid = coupler_from_rockettile_x1_no_bufferIn_e_valid; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_x1_tlMasterClockXingOut_e_bits_sink; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_x1_no_bufferOut_e_bits_sink = coupler_from_rockettile_x1_no_bufferIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingIn_a_ready = coupler_from_rockettile_tlMasterClockXingOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_no_bufferIn_a_valid = coupler_from_rockettile_tlMasterClockXingOut_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_no_bufferIn_a_bits_opcode = coupler_from_rockettile_tlMasterClockXingOut_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_no_bufferIn_a_bits_param = coupler_from_rockettile_tlMasterClockXingOut_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_no_bufferIn_a_bits_size = coupler_from_rockettile_tlMasterClockXingOut_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_no_bufferIn_a_bits_source = coupler_from_rockettile_tlMasterClockXingOut_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_no_bufferIn_a_bits_address = coupler_from_rockettile_tlMasterClockXingOut_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_no_bufferIn_a_bits_mask = coupler_from_rockettile_tlMasterClockXingOut_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_no_bufferIn_a_bits_data = coupler_from_rockettile_tlMasterClockXingOut_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_no_bufferIn_a_bits_corrupt = coupler_from_rockettile_tlMasterClockXingOut_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_no_bufferIn_d_ready = coupler_from_rockettile_tlMasterClockXingOut_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingIn_d_valid = coupler_from_rockettile_tlMasterClockXingOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingIn_d_bits_opcode = coupler_from_rockettile_tlMasterClockXingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingIn_d_bits_param = coupler_from_rockettile_tlMasterClockXingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingIn_d_bits_size = coupler_from_rockettile_tlMasterClockXingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingIn_d_bits_source = coupler_from_rockettile_tlMasterClockXingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingIn_d_bits_sink = coupler_from_rockettile_tlMasterClockXingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingIn_d_bits_denied = coupler_from_rockettile_tlMasterClockXingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingIn_d_bits_data = coupler_from_rockettile_tlMasterClockXingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingIn_d_bits_corrupt = coupler_from_rockettile_tlMasterClockXingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_x1_tlMasterClockXingIn_a_ready = coupler_from_rockettile_x1_tlMasterClockXingOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_x1_no_bufferIn_a_valid = coupler_from_rockettile_x1_tlMasterClockXingOut_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_x1_no_bufferIn_a_bits_opcode = coupler_from_rockettile_x1_tlMasterClockXingOut_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_x1_no_bufferIn_a_bits_param = coupler_from_rockettile_x1_tlMasterClockXingOut_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_x1_no_bufferIn_a_bits_size = coupler_from_rockettile_x1_tlMasterClockXingOut_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_x1_no_bufferIn_a_bits_source = coupler_from_rockettile_x1_tlMasterClockXingOut_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_x1_no_bufferIn_a_bits_address = coupler_from_rockettile_x1_tlMasterClockXingOut_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_x1_no_bufferIn_a_bits_mask = coupler_from_rockettile_x1_tlMasterClockXingOut_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_x1_no_bufferIn_a_bits_data = coupler_from_rockettile_x1_tlMasterClockXingOut_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_x1_no_bufferIn_a_bits_corrupt = coupler_from_rockettile_x1_tlMasterClockXingOut_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_x1_no_bufferIn_b_ready = coupler_from_rockettile_x1_tlMasterClockXingOut_b_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_x1_tlMasterClockXingIn_b_valid = coupler_from_rockettile_x1_tlMasterClockXingOut_b_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_x1_tlMasterClockXingIn_b_bits_param = coupler_from_rockettile_x1_tlMasterClockXingOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_x1_tlMasterClockXingIn_b_bits_address = coupler_from_rockettile_x1_tlMasterClockXingOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_x1_tlMasterClockXingIn_c_ready = coupler_from_rockettile_x1_tlMasterClockXingOut_c_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_x1_no_bufferIn_c_valid = coupler_from_rockettile_x1_tlMasterClockXingOut_c_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_x1_no_bufferIn_c_bits_opcode = coupler_from_rockettile_x1_tlMasterClockXingOut_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_x1_no_bufferIn_c_bits_param = coupler_from_rockettile_x1_tlMasterClockXingOut_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_x1_no_bufferIn_c_bits_size = coupler_from_rockettile_x1_tlMasterClockXingOut_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_x1_no_bufferIn_c_bits_source = coupler_from_rockettile_x1_tlMasterClockXingOut_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_x1_no_bufferIn_c_bits_address = coupler_from_rockettile_x1_tlMasterClockXingOut_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_x1_no_bufferIn_c_bits_data = coupler_from_rockettile_x1_tlMasterClockXingOut_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_x1_no_bufferIn_c_bits_corrupt = coupler_from_rockettile_x1_tlMasterClockXingOut_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_x1_no_bufferIn_d_ready = coupler_from_rockettile_x1_tlMasterClockXingOut_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_x1_tlMasterClockXingIn_d_valid = coupler_from_rockettile_x1_tlMasterClockXingOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_x1_tlMasterClockXingIn_d_bits_opcode = coupler_from_rockettile_x1_tlMasterClockXingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_x1_tlMasterClockXingIn_d_bits_param = coupler_from_rockettile_x1_tlMasterClockXingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_x1_tlMasterClockXingIn_d_bits_size = coupler_from_rockettile_x1_tlMasterClockXingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_x1_tlMasterClockXingIn_d_bits_source = coupler_from_rockettile_x1_tlMasterClockXingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_x1_tlMasterClockXingIn_d_bits_sink = coupler_from_rockettile_x1_tlMasterClockXingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_x1_tlMasterClockXingIn_d_bits_denied = coupler_from_rockettile_x1_tlMasterClockXingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_x1_tlMasterClockXingIn_d_bits_data = coupler_from_rockettile_x1_tlMasterClockXingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_x1_tlMasterClockXingIn_d_bits_corrupt = coupler_from_rockettile_x1_tlMasterClockXingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_x1_no_bufferIn_e_valid = coupler_from_rockettile_x1_tlMasterClockXingOut_e_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_x1_no_bufferIn_e_bits_sink = coupler_from_rockettile_x1_tlMasterClockXingOut_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_auto_tl_master_clock_xing_in_0_a_ready = coupler_from_rockettile_tlMasterClockXingIn_a_ready; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_tlMasterClockXingOut_a_valid = coupler_from_rockettile_tlMasterClockXingIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingOut_a_bits_opcode = coupler_from_rockettile_tlMasterClockXingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingOut_a_bits_param = coupler_from_rockettile_tlMasterClockXingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingOut_a_bits_size = coupler_from_rockettile_tlMasterClockXingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingOut_a_bits_source = coupler_from_rockettile_tlMasterClockXingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingOut_a_bits_address = coupler_from_rockettile_tlMasterClockXingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingOut_a_bits_mask = coupler_from_rockettile_tlMasterClockXingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingOut_a_bits_data = coupler_from_rockettile_tlMasterClockXingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingOut_a_bits_corrupt = coupler_from_rockettile_tlMasterClockXingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingOut_d_ready = coupler_from_rockettile_tlMasterClockXingIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_auto_tl_master_clock_xing_in_0_d_valid = coupler_from_rockettile_tlMasterClockXingIn_d_valid; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_master_clock_xing_in_0_d_bits_opcode = coupler_from_rockettile_tlMasterClockXingIn_d_bits_opcode; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_master_clock_xing_in_0_d_bits_param = coupler_from_rockettile_tlMasterClockXingIn_d_bits_param; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_master_clock_xing_in_0_d_bits_size = coupler_from_rockettile_tlMasterClockXingIn_d_bits_size; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_master_clock_xing_in_0_d_bits_source = coupler_from_rockettile_tlMasterClockXingIn_d_bits_source; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_master_clock_xing_in_0_d_bits_sink = coupler_from_rockettile_tlMasterClockXingIn_d_bits_sink; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_master_clock_xing_in_0_d_bits_denied = coupler_from_rockettile_tlMasterClockXingIn_d_bits_denied; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_master_clock_xing_in_0_d_bits_data = coupler_from_rockettile_tlMasterClockXingIn_d_bits_data; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_master_clock_xing_in_0_d_bits_corrupt = coupler_from_rockettile_tlMasterClockXingIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_master_clock_xing_in_1_a_ready = coupler_from_rockettile_x1_tlMasterClockXingIn_a_ready; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_x1_tlMasterClockXingOut_a_valid = coupler_from_rockettile_x1_tlMasterClockXingIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_x1_tlMasterClockXingOut_a_bits_opcode = coupler_from_rockettile_x1_tlMasterClockXingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_x1_tlMasterClockXingOut_a_bits_param = coupler_from_rockettile_x1_tlMasterClockXingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_x1_tlMasterClockXingOut_a_bits_size = coupler_from_rockettile_x1_tlMasterClockXingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_x1_tlMasterClockXingOut_a_bits_source = coupler_from_rockettile_x1_tlMasterClockXingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_x1_tlMasterClockXingOut_a_bits_address = coupler_from_rockettile_x1_tlMasterClockXingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_x1_tlMasterClockXingOut_a_bits_mask = coupler_from_rockettile_x1_tlMasterClockXingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_x1_tlMasterClockXingOut_a_bits_data = coupler_from_rockettile_x1_tlMasterClockXingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_x1_tlMasterClockXingOut_a_bits_corrupt = coupler_from_rockettile_x1_tlMasterClockXingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_x1_tlMasterClockXingOut_b_ready = coupler_from_rockettile_x1_tlMasterClockXingIn_b_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_auto_tl_master_clock_xing_in_1_b_valid = coupler_from_rockettile_x1_tlMasterClockXingIn_b_valid; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_master_clock_xing_in_1_b_bits_param = coupler_from_rockettile_x1_tlMasterClockXingIn_b_bits_param; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_master_clock_xing_in_1_b_bits_address = coupler_from_rockettile_x1_tlMasterClockXingIn_b_bits_address; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_master_clock_xing_in_1_c_ready = coupler_from_rockettile_x1_tlMasterClockXingIn_c_ready; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_x1_tlMasterClockXingOut_c_valid = coupler_from_rockettile_x1_tlMasterClockXingIn_c_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_x1_tlMasterClockXingOut_c_bits_opcode = coupler_from_rockettile_x1_tlMasterClockXingIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_x1_tlMasterClockXingOut_c_bits_param = coupler_from_rockettile_x1_tlMasterClockXingIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_x1_tlMasterClockXingOut_c_bits_size = coupler_from_rockettile_x1_tlMasterClockXingIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_x1_tlMasterClockXingOut_c_bits_source = coupler_from_rockettile_x1_tlMasterClockXingIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_x1_tlMasterClockXingOut_c_bits_address = coupler_from_rockettile_x1_tlMasterClockXingIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_x1_tlMasterClockXingOut_c_bits_data = coupler_from_rockettile_x1_tlMasterClockXingIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_x1_tlMasterClockXingOut_c_bits_corrupt = coupler_from_rockettile_x1_tlMasterClockXingIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_x1_tlMasterClockXingOut_d_ready = coupler_from_rockettile_x1_tlMasterClockXingIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_auto_tl_master_clock_xing_in_1_d_valid = coupler_from_rockettile_x1_tlMasterClockXingIn_d_valid; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_master_clock_xing_in_1_d_bits_opcode = coupler_from_rockettile_x1_tlMasterClockXingIn_d_bits_opcode; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_master_clock_xing_in_1_d_bits_param = coupler_from_rockettile_x1_tlMasterClockXingIn_d_bits_param; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_master_clock_xing_in_1_d_bits_size = coupler_from_rockettile_x1_tlMasterClockXingIn_d_bits_size; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_master_clock_xing_in_1_d_bits_source = coupler_from_rockettile_x1_tlMasterClockXingIn_d_bits_source; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_master_clock_xing_in_1_d_bits_sink = coupler_from_rockettile_x1_tlMasterClockXingIn_d_bits_sink; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_master_clock_xing_in_1_d_bits_denied = coupler_from_rockettile_x1_tlMasterClockXingIn_d_bits_denied; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_master_clock_xing_in_1_d_bits_data = coupler_from_rockettile_x1_tlMasterClockXingIn_d_bits_data; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_master_clock_xing_in_1_d_bits_corrupt = coupler_from_rockettile_x1_tlMasterClockXingIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_x1_tlMasterClockXingOut_e_valid = coupler_from_rockettile_x1_tlMasterClockXingIn_e_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_x1_tlMasterClockXingOut_e_bits_sink = coupler_from_rockettile_x1_tlMasterClockXingIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign childClock = clockSinkNodeIn_clock; // @[MixedNode.scala:551:17]
assign childReset = clockSinkNodeIn_reset; // @[MixedNode.scala:551:17]
wire fixer__T_1 = fixer_a_first & fixer__a_first_T; // @[Decoupled.scala:51:35]
wire fixer__T_3 = fixer_d_first & fixer__T_2; // @[Decoupled.scala:51:35]
wire fixer__T_31 = fixer_a_first_1 & fixer__a_first_T_1; // @[Decoupled.scala:51:35]
wire fixer__T_33 = fixer_d_first_1 & fixer__T_32; // @[Decoupled.scala:51:35]
wire fixer__T_76 = fixer_a_first_2 & fixer__a_first_T_2; // @[Decoupled.scala:51:35]
wire fixer__T_78 = fixer_d_first_2 & fixer__T_77; // @[Decoupled.scala:51:35]
always @(posedge childClock) begin // @[LazyModuleImp.scala:155:31]
if (childReset) begin // @[LazyModuleImp.scala:155:31, :158:31]
fixer_a_first_counter <= 8'h0; // @[Edges.scala:229:27]
fixer_d_first_counter <= 8'h0; // @[Edges.scala:229:27]
fixer_flight_0 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_1 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_2 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_3 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_4 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_5 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_6 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_7 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_8 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_9 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_10 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_11 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_12 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_13 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_14 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_15 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_16 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_SourceIdFIFOed <= 17'h0; // @[FIFOFixer.scala:115:35]
fixer_a_first_counter_1 <= 8'h0; // @[Edges.scala:229:27]
fixer_d_first_counter_1 <= 8'h0; // @[Edges.scala:229:27]
fixer_flight_1_0 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_1_1 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_1_2 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_1_3 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_1_4 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_1_5 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_1_6 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_1_7 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_1_8 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_1_9 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_1_10 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_1_11 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_1_12 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_1_13 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_1_14 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_1_15 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_1_16 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_1_17 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_1_18 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_1_19 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_1_20 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_1_21 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_1_22 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_1_23 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_1_24 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_1_25 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_1_26 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_1_27 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_1_28 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_1_29 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_1_30 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_1_31 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_SourceIdFIFOed_1 <= 32'h0; // @[FIFOFixer.scala:115:35]
fixer_a_first_counter_2 <= 8'h0; // @[Edges.scala:229:27]
fixer_d_first_counter_2 <= 8'h0; // @[Edges.scala:229:27]
fixer_flight_2_0 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_2_1 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_2_2 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_SourceIdFIFOed_2 <= 3'h0; // @[FIFOFixer.scala:115:35]
end
else begin // @[LazyModuleImp.scala:155:31]
if (fixer__a_first_T) // @[Decoupled.scala:51:35]
fixer_a_first_counter <= fixer__a_first_counter_T; // @[Edges.scala:229:27, :236:21]
if (fixer__d_first_T) // @[Decoupled.scala:51:35]
fixer_d_first_counter <= fixer__d_first_counter_T; // @[Edges.scala:229:27, :236:21]
fixer_flight_0 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h0) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h0 ? fixer__flight_T : fixer_flight_0); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_1 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h1) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h1 ? fixer__flight_T : fixer_flight_1); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_2 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h2) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h2 ? fixer__flight_T : fixer_flight_2); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_3 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h3) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h3 ? fixer__flight_T : fixer_flight_3); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_4 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h4) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h4 ? fixer__flight_T : fixer_flight_4); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_5 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h5) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h5 ? fixer__flight_T : fixer_flight_5); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_6 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h6) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h6 ? fixer__flight_T : fixer_flight_6); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_7 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h7) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h7 ? fixer__flight_T : fixer_flight_7); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_8 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h8) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h8 ? fixer__flight_T : fixer_flight_8); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_9 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h9) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h9 ? fixer__flight_T : fixer_flight_9); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_10 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'hA) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'hA ? fixer__flight_T : fixer_flight_10); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_11 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'hB) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'hB ? fixer__flight_T : fixer_flight_11); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_12 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'hC) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'hC ? fixer__flight_T : fixer_flight_12); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_13 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'hD) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'hD ? fixer__flight_T : fixer_flight_13); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_14 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'hE) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'hE ? fixer__flight_T : fixer_flight_14); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_15 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'hF) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'hF ? fixer__flight_T : fixer_flight_15); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_16 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h10) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h10 ? fixer__flight_T : fixer_flight_16); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_SourceIdFIFOed <= fixer__SourceIdFIFOed_T; // @[FIFOFixer.scala:115:35, :126:40]
if (fixer__a_first_T_1) // @[Decoupled.scala:51:35]
fixer_a_first_counter_1 <= fixer__a_first_counter_T_1; // @[Edges.scala:229:27, :236:21]
if (fixer__d_first_T_2) // @[Decoupled.scala:51:35]
fixer_d_first_counter_1 <= fixer__d_first_counter_T_1; // @[Edges.scala:229:27, :236:21]
fixer_flight_1_0 <= ~(fixer__T_33 & fixer_x1_anonIn_d_bits_source == 5'h0) & (fixer__T_31 & fixer_x1_anonIn_a_bits_source == 5'h0 ? fixer__flight_T_1 : fixer_flight_1_0); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_1_1 <= ~(fixer__T_33 & fixer_x1_anonIn_d_bits_source == 5'h1) & (fixer__T_31 & fixer_x1_anonIn_a_bits_source == 5'h1 ? fixer__flight_T_1 : fixer_flight_1_1); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_1_2 <= ~(fixer__T_33 & fixer_x1_anonIn_d_bits_source == 5'h2) & (fixer__T_31 & fixer_x1_anonIn_a_bits_source == 5'h2 ? fixer__flight_T_1 : fixer_flight_1_2); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_1_3 <= ~(fixer__T_33 & fixer_x1_anonIn_d_bits_source == 5'h3) & (fixer__T_31 & fixer_x1_anonIn_a_bits_source == 5'h3 ? fixer__flight_T_1 : fixer_flight_1_3); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_1_4 <= ~(fixer__T_33 & fixer_x1_anonIn_d_bits_source == 5'h4) & (fixer__T_31 & fixer_x1_anonIn_a_bits_source == 5'h4 ? fixer__flight_T_1 : fixer_flight_1_4); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_1_5 <= ~(fixer__T_33 & fixer_x1_anonIn_d_bits_source == 5'h5) & (fixer__T_31 & fixer_x1_anonIn_a_bits_source == 5'h5 ? fixer__flight_T_1 : fixer_flight_1_5); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_1_6 <= ~(fixer__T_33 & fixer_x1_anonIn_d_bits_source == 5'h6) & (fixer__T_31 & fixer_x1_anonIn_a_bits_source == 5'h6 ? fixer__flight_T_1 : fixer_flight_1_6); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_1_7 <= ~(fixer__T_33 & fixer_x1_anonIn_d_bits_source == 5'h7) & (fixer__T_31 & fixer_x1_anonIn_a_bits_source == 5'h7 ? fixer__flight_T_1 : fixer_flight_1_7); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_1_8 <= ~(fixer__T_33 & fixer_x1_anonIn_d_bits_source == 5'h8) & (fixer__T_31 & fixer_x1_anonIn_a_bits_source == 5'h8 ? fixer__flight_T_1 : fixer_flight_1_8); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_1_9 <= ~(fixer__T_33 & fixer_x1_anonIn_d_bits_source == 5'h9) & (fixer__T_31 & fixer_x1_anonIn_a_bits_source == 5'h9 ? fixer__flight_T_1 : fixer_flight_1_9); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_1_10 <= ~(fixer__T_33 & fixer_x1_anonIn_d_bits_source == 5'hA) & (fixer__T_31 & fixer_x1_anonIn_a_bits_source == 5'hA ? fixer__flight_T_1 : fixer_flight_1_10); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_1_11 <= ~(fixer__T_33 & fixer_x1_anonIn_d_bits_source == 5'hB) & (fixer__T_31 & fixer_x1_anonIn_a_bits_source == 5'hB ? fixer__flight_T_1 : fixer_flight_1_11); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_1_12 <= ~(fixer__T_33 & fixer_x1_anonIn_d_bits_source == 5'hC) & (fixer__T_31 & fixer_x1_anonIn_a_bits_source == 5'hC ? fixer__flight_T_1 : fixer_flight_1_12); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_1_13 <= ~(fixer__T_33 & fixer_x1_anonIn_d_bits_source == 5'hD) & (fixer__T_31 & fixer_x1_anonIn_a_bits_source == 5'hD ? fixer__flight_T_1 : fixer_flight_1_13); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_1_14 <= ~(fixer__T_33 & fixer_x1_anonIn_d_bits_source == 5'hE) & (fixer__T_31 & fixer_x1_anonIn_a_bits_source == 5'hE ? fixer__flight_T_1 : fixer_flight_1_14); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_1_15 <= ~(fixer__T_33 & fixer_x1_anonIn_d_bits_source == 5'hF) & (fixer__T_31 & fixer_x1_anonIn_a_bits_source == 5'hF ? fixer__flight_T_1 : fixer_flight_1_15); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_1_16 <= ~(fixer__T_33 & fixer_x1_anonIn_d_bits_source == 5'h10) & (fixer__T_31 & fixer_x1_anonIn_a_bits_source == 5'h10 ? fixer__flight_T_1 : fixer_flight_1_16); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_1_17 <= ~(fixer__T_33 & fixer_x1_anonIn_d_bits_source == 5'h11) & (fixer__T_31 & fixer_x1_anonIn_a_bits_source == 5'h11 ? fixer__flight_T_1 : fixer_flight_1_17); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_1_18 <= ~(fixer__T_33 & fixer_x1_anonIn_d_bits_source == 5'h12) & (fixer__T_31 & fixer_x1_anonIn_a_bits_source == 5'h12 ? fixer__flight_T_1 : fixer_flight_1_18); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_1_19 <= ~(fixer__T_33 & fixer_x1_anonIn_d_bits_source == 5'h13) & (fixer__T_31 & fixer_x1_anonIn_a_bits_source == 5'h13 ? fixer__flight_T_1 : fixer_flight_1_19); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_1_20 <= ~(fixer__T_33 & fixer_x1_anonIn_d_bits_source == 5'h14) & (fixer__T_31 & fixer_x1_anonIn_a_bits_source == 5'h14 ? fixer__flight_T_1 : fixer_flight_1_20); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_1_21 <= ~(fixer__T_33 & fixer_x1_anonIn_d_bits_source == 5'h15) & (fixer__T_31 & fixer_x1_anonIn_a_bits_source == 5'h15 ? fixer__flight_T_1 : fixer_flight_1_21); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_1_22 <= ~(fixer__T_33 & fixer_x1_anonIn_d_bits_source == 5'h16) & (fixer__T_31 & fixer_x1_anonIn_a_bits_source == 5'h16 ? fixer__flight_T_1 : fixer_flight_1_22); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_1_23 <= ~(fixer__T_33 & fixer_x1_anonIn_d_bits_source == 5'h17) & (fixer__T_31 & fixer_x1_anonIn_a_bits_source == 5'h17 ? fixer__flight_T_1 : fixer_flight_1_23); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_1_24 <= ~(fixer__T_33 & fixer_x1_anonIn_d_bits_source == 5'h18) & (fixer__T_31 & fixer_x1_anonIn_a_bits_source == 5'h18 ? fixer__flight_T_1 : fixer_flight_1_24); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_1_25 <= ~(fixer__T_33 & fixer_x1_anonIn_d_bits_source == 5'h19) & (fixer__T_31 & fixer_x1_anonIn_a_bits_source == 5'h19 ? fixer__flight_T_1 : fixer_flight_1_25); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_1_26 <= ~(fixer__T_33 & fixer_x1_anonIn_d_bits_source == 5'h1A) & (fixer__T_31 & fixer_x1_anonIn_a_bits_source == 5'h1A ? fixer__flight_T_1 : fixer_flight_1_26); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_1_27 <= ~(fixer__T_33 & fixer_x1_anonIn_d_bits_source == 5'h1B) & (fixer__T_31 & fixer_x1_anonIn_a_bits_source == 5'h1B ? fixer__flight_T_1 : fixer_flight_1_27); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_1_28 <= ~(fixer__T_33 & fixer_x1_anonIn_d_bits_source == 5'h1C) & (fixer__T_31 & fixer_x1_anonIn_a_bits_source == 5'h1C ? fixer__flight_T_1 : fixer_flight_1_28); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_1_29 <= ~(fixer__T_33 & fixer_x1_anonIn_d_bits_source == 5'h1D) & (fixer__T_31 & fixer_x1_anonIn_a_bits_source == 5'h1D ? fixer__flight_T_1 : fixer_flight_1_29); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_1_30 <= ~(fixer__T_33 & fixer_x1_anonIn_d_bits_source == 5'h1E) & (fixer__T_31 & fixer_x1_anonIn_a_bits_source == 5'h1E ? fixer__flight_T_1 : fixer_flight_1_30); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_1_31 <= ~(fixer__T_33 & (&fixer_x1_anonIn_d_bits_source)) & (fixer__T_31 & (&fixer_x1_anonIn_a_bits_source) ? fixer__flight_T_1 : fixer_flight_1_31); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_SourceIdFIFOed_1 <= fixer__SourceIdFIFOed_T_1; // @[FIFOFixer.scala:115:35, :126:40]
if (fixer__a_first_T_2) // @[Decoupled.scala:51:35]
fixer_a_first_counter_2 <= fixer__a_first_counter_T_2; // @[Edges.scala:229:27, :236:21]
if (fixer__d_first_T_4) // @[Decoupled.scala:51:35]
fixer_d_first_counter_2 <= fixer__d_first_counter_T_2; // @[Edges.scala:229:27, :236:21]
fixer_flight_2_0 <= ~(fixer__T_78 & fixer_x1_anonIn_1_d_bits_source == 2'h0) & (fixer__T_76 & fixer_x1_anonIn_1_a_bits_source == 2'h0 ? fixer__flight_T_2 : fixer_flight_2_0); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_2_1 <= ~(fixer__T_78 & fixer_x1_anonIn_1_d_bits_source == 2'h1) & (fixer__T_76 & fixer_x1_anonIn_1_a_bits_source == 2'h1 ? fixer__flight_T_2 : fixer_flight_2_1); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_2_2 <= ~(fixer__T_78 & fixer_x1_anonIn_1_d_bits_source == 2'h2) & (fixer__T_76 & fixer_x1_anonIn_1_a_bits_source == 2'h2 ? fixer__flight_T_2 : fixer_flight_2_2); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_SourceIdFIFOed_2 <= fixer__SourceIdFIFOed_T_2; // @[FIFOFixer.scala:115:35, :126:40]
end
always @(posedge)
FixedClockBroadcast_4 fixedClockNode ( // @[ClockGroup.scala:115:114]
.auto_anon_in_clock (clockGroup_auto_out_clock), // @[ClockGroup.scala:24:9]
.auto_anon_in_reset (clockGroup_auto_out_reset), // @[ClockGroup.scala:24:9]
.auto_anon_out_3_clock (auto_fixedClockNode_anon_out_2_clock_0),
.auto_anon_out_3_reset (auto_fixedClockNode_anon_out_2_reset_0),
.auto_anon_out_2_clock (auto_fixedClockNode_anon_out_1_clock_0),
.auto_anon_out_2_reset (auto_fixedClockNode_anon_out_1_reset_0),
.auto_anon_out_1_clock (auto_fixedClockNode_anon_out_0_clock_0),
.auto_anon_out_1_reset (auto_fixedClockNode_anon_out_0_reset_0),
.auto_anon_out_0_clock (clockSinkNodeIn_clock),
.auto_anon_out_0_reset (clockSinkNodeIn_reset)
); // @[ClockGroup.scala:115:114]
TLXbar_sbus_i3_o2_a32d128s7k4z4c system_bus_xbar ( // @[SystemBus.scala:47:43]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_anon_in_2_a_ready (fixer_auto_anon_out_2_a_ready),
.auto_anon_in_2_a_valid (fixer_auto_anon_out_2_a_valid), // @[FIFOFixer.scala:50:9]
.auto_anon_in_2_a_bits_opcode (fixer_auto_anon_out_2_a_bits_opcode), // @[FIFOFixer.scala:50:9]
.auto_anon_in_2_a_bits_param (fixer_auto_anon_out_2_a_bits_param), // @[FIFOFixer.scala:50:9]
.auto_anon_in_2_a_bits_size (fixer_auto_anon_out_2_a_bits_size), // @[FIFOFixer.scala:50:9]
.auto_anon_in_2_a_bits_source (fixer_auto_anon_out_2_a_bits_source), // @[FIFOFixer.scala:50:9]
.auto_anon_in_2_a_bits_address (fixer_auto_anon_out_2_a_bits_address), // @[FIFOFixer.scala:50:9]
.auto_anon_in_2_a_bits_mask (fixer_auto_anon_out_2_a_bits_mask), // @[FIFOFixer.scala:50:9]
.auto_anon_in_2_a_bits_data (fixer_auto_anon_out_2_a_bits_data), // @[FIFOFixer.scala:50:9]
.auto_anon_in_2_a_bits_corrupt (fixer_auto_anon_out_2_a_bits_corrupt), // @[FIFOFixer.scala:50:9]
.auto_anon_in_2_b_ready (fixer_auto_anon_out_2_b_ready), // @[FIFOFixer.scala:50:9]
.auto_anon_in_2_b_valid (fixer_auto_anon_out_2_b_valid),
.auto_anon_in_2_b_bits_param (fixer_auto_anon_out_2_b_bits_param),
.auto_anon_in_2_b_bits_address (fixer_auto_anon_out_2_b_bits_address),
.auto_anon_in_2_c_ready (fixer_auto_anon_out_2_c_ready),
.auto_anon_in_2_c_valid (fixer_auto_anon_out_2_c_valid), // @[FIFOFixer.scala:50:9]
.auto_anon_in_2_c_bits_opcode (fixer_auto_anon_out_2_c_bits_opcode), // @[FIFOFixer.scala:50:9]
.auto_anon_in_2_c_bits_param (fixer_auto_anon_out_2_c_bits_param), // @[FIFOFixer.scala:50:9]
.auto_anon_in_2_c_bits_size (fixer_auto_anon_out_2_c_bits_size), // @[FIFOFixer.scala:50:9]
.auto_anon_in_2_c_bits_source (fixer_auto_anon_out_2_c_bits_source), // @[FIFOFixer.scala:50:9]
.auto_anon_in_2_c_bits_address (fixer_auto_anon_out_2_c_bits_address), // @[FIFOFixer.scala:50:9]
.auto_anon_in_2_c_bits_data (fixer_auto_anon_out_2_c_bits_data), // @[FIFOFixer.scala:50:9]
.auto_anon_in_2_c_bits_corrupt (fixer_auto_anon_out_2_c_bits_corrupt), // @[FIFOFixer.scala:50:9]
.auto_anon_in_2_d_ready (fixer_auto_anon_out_2_d_ready), // @[FIFOFixer.scala:50:9]
.auto_anon_in_2_d_valid (fixer_auto_anon_out_2_d_valid),
.auto_anon_in_2_d_bits_opcode (fixer_auto_anon_out_2_d_bits_opcode),
.auto_anon_in_2_d_bits_param (fixer_auto_anon_out_2_d_bits_param),
.auto_anon_in_2_d_bits_size (fixer_auto_anon_out_2_d_bits_size),
.auto_anon_in_2_d_bits_source (fixer_auto_anon_out_2_d_bits_source),
.auto_anon_in_2_d_bits_sink (fixer_auto_anon_out_2_d_bits_sink),
.auto_anon_in_2_d_bits_denied (fixer_auto_anon_out_2_d_bits_denied),
.auto_anon_in_2_d_bits_data (fixer_auto_anon_out_2_d_bits_data),
.auto_anon_in_2_d_bits_corrupt (fixer_auto_anon_out_2_d_bits_corrupt),
.auto_anon_in_2_e_valid (fixer_auto_anon_out_2_e_valid), // @[FIFOFixer.scala:50:9]
.auto_anon_in_2_e_bits_sink (fixer_auto_anon_out_2_e_bits_sink), // @[FIFOFixer.scala:50:9]
.auto_anon_in_1_a_ready (fixer_auto_anon_out_1_a_ready),
.auto_anon_in_1_a_valid (fixer_auto_anon_out_1_a_valid), // @[FIFOFixer.scala:50:9]
.auto_anon_in_1_a_bits_opcode (fixer_auto_anon_out_1_a_bits_opcode), // @[FIFOFixer.scala:50:9]
.auto_anon_in_1_a_bits_param (fixer_auto_anon_out_1_a_bits_param), // @[FIFOFixer.scala:50:9]
.auto_anon_in_1_a_bits_size (fixer_auto_anon_out_1_a_bits_size), // @[FIFOFixer.scala:50:9]
.auto_anon_in_1_a_bits_source (fixer_auto_anon_out_1_a_bits_source), // @[FIFOFixer.scala:50:9]
.auto_anon_in_1_a_bits_address (fixer_auto_anon_out_1_a_bits_address), // @[FIFOFixer.scala:50:9]
.auto_anon_in_1_a_bits_mask (fixer_auto_anon_out_1_a_bits_mask), // @[FIFOFixer.scala:50:9]
.auto_anon_in_1_a_bits_data (fixer_auto_anon_out_1_a_bits_data), // @[FIFOFixer.scala:50:9]
.auto_anon_in_1_a_bits_corrupt (fixer_auto_anon_out_1_a_bits_corrupt), // @[FIFOFixer.scala:50:9]
.auto_anon_in_1_d_ready (fixer_auto_anon_out_1_d_ready), // @[FIFOFixer.scala:50:9]
.auto_anon_in_1_d_valid (fixer_auto_anon_out_1_d_valid),
.auto_anon_in_1_d_bits_opcode (fixer_auto_anon_out_1_d_bits_opcode),
.auto_anon_in_1_d_bits_param (fixer_auto_anon_out_1_d_bits_param),
.auto_anon_in_1_d_bits_size (fixer_auto_anon_out_1_d_bits_size),
.auto_anon_in_1_d_bits_source (fixer_auto_anon_out_1_d_bits_source),
.auto_anon_in_1_d_bits_sink (fixer_auto_anon_out_1_d_bits_sink),
.auto_anon_in_1_d_bits_denied (fixer_auto_anon_out_1_d_bits_denied),
.auto_anon_in_1_d_bits_data (fixer_auto_anon_out_1_d_bits_data),
.auto_anon_in_1_d_bits_corrupt (fixer_auto_anon_out_1_d_bits_corrupt),
.auto_anon_in_0_a_ready (fixer_auto_anon_out_0_a_ready),
.auto_anon_in_0_a_valid (fixer_auto_anon_out_0_a_valid), // @[FIFOFixer.scala:50:9]
.auto_anon_in_0_a_bits_opcode (fixer_auto_anon_out_0_a_bits_opcode), // @[FIFOFixer.scala:50:9]
.auto_anon_in_0_a_bits_param (fixer_auto_anon_out_0_a_bits_param), // @[FIFOFixer.scala:50:9]
.auto_anon_in_0_a_bits_size (fixer_auto_anon_out_0_a_bits_size), // @[FIFOFixer.scala:50:9]
.auto_anon_in_0_a_bits_source (fixer_auto_anon_out_0_a_bits_source), // @[FIFOFixer.scala:50:9]
.auto_anon_in_0_a_bits_address (fixer_auto_anon_out_0_a_bits_address), // @[FIFOFixer.scala:50:9]
.auto_anon_in_0_a_bits_mask (fixer_auto_anon_out_0_a_bits_mask), // @[FIFOFixer.scala:50:9]
.auto_anon_in_0_a_bits_data (fixer_auto_anon_out_0_a_bits_data), // @[FIFOFixer.scala:50:9]
.auto_anon_in_0_a_bits_corrupt (fixer_auto_anon_out_0_a_bits_corrupt), // @[FIFOFixer.scala:50:9]
.auto_anon_in_0_d_ready (fixer_auto_anon_out_0_d_ready), // @[FIFOFixer.scala:50:9]
.auto_anon_in_0_d_valid (fixer_auto_anon_out_0_d_valid),
.auto_anon_in_0_d_bits_opcode (fixer_auto_anon_out_0_d_bits_opcode),
.auto_anon_in_0_d_bits_param (fixer_auto_anon_out_0_d_bits_param),
.auto_anon_in_0_d_bits_size (fixer_auto_anon_out_0_d_bits_size),
.auto_anon_in_0_d_bits_source (fixer_auto_anon_out_0_d_bits_source),
.auto_anon_in_0_d_bits_sink (fixer_auto_anon_out_0_d_bits_sink),
.auto_anon_in_0_d_bits_denied (fixer_auto_anon_out_0_d_bits_denied),
.auto_anon_in_0_d_bits_data (fixer_auto_anon_out_0_d_bits_data),
.auto_anon_in_0_d_bits_corrupt (fixer_auto_anon_out_0_d_bits_corrupt),
.auto_anon_out_1_a_ready (coupler_to_bus_named_coh_auto_widget_anon_in_a_ready), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_1_a_valid (coupler_to_bus_named_coh_auto_widget_anon_in_a_valid),
.auto_anon_out_1_a_bits_opcode (coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_opcode),
.auto_anon_out_1_a_bits_param (coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_param),
.auto_anon_out_1_a_bits_size (coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_size),
.auto_anon_out_1_a_bits_source (coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_source),
.auto_anon_out_1_a_bits_address (coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_address),
.auto_anon_out_1_a_bits_mask (coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_mask),
.auto_anon_out_1_a_bits_data (coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_data),
.auto_anon_out_1_a_bits_corrupt (coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_corrupt),
.auto_anon_out_1_b_ready (coupler_to_bus_named_coh_auto_widget_anon_in_b_ready),
.auto_anon_out_1_b_valid (coupler_to_bus_named_coh_auto_widget_anon_in_b_valid), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_1_b_bits_param (coupler_to_bus_named_coh_auto_widget_anon_in_b_bits_param), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_1_b_bits_address (coupler_to_bus_named_coh_auto_widget_anon_in_b_bits_address), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_1_c_ready (coupler_to_bus_named_coh_auto_widget_anon_in_c_ready), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_1_c_valid (coupler_to_bus_named_coh_auto_widget_anon_in_c_valid),
.auto_anon_out_1_c_bits_opcode (coupler_to_bus_named_coh_auto_widget_anon_in_c_bits_opcode),
.auto_anon_out_1_c_bits_param (coupler_to_bus_named_coh_auto_widget_anon_in_c_bits_param),
.auto_anon_out_1_c_bits_size (coupler_to_bus_named_coh_auto_widget_anon_in_c_bits_size),
.auto_anon_out_1_c_bits_source (coupler_to_bus_named_coh_auto_widget_anon_in_c_bits_source),
.auto_anon_out_1_c_bits_address (coupler_to_bus_named_coh_auto_widget_anon_in_c_bits_address),
.auto_anon_out_1_c_bits_data (coupler_to_bus_named_coh_auto_widget_anon_in_c_bits_data),
.auto_anon_out_1_c_bits_corrupt (coupler_to_bus_named_coh_auto_widget_anon_in_c_bits_corrupt),
.auto_anon_out_1_d_ready (coupler_to_bus_named_coh_auto_widget_anon_in_d_ready),
.auto_anon_out_1_d_valid (coupler_to_bus_named_coh_auto_widget_anon_in_d_valid), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_1_d_bits_opcode (coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_opcode), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_1_d_bits_param (coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_param), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_1_d_bits_size (coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_size), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_1_d_bits_source (coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_source), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_1_d_bits_sink (coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_sink), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_1_d_bits_denied (coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_denied), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_1_d_bits_data (coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_data), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_1_d_bits_corrupt (coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_corrupt), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_1_e_valid (coupler_to_bus_named_coh_auto_widget_anon_in_e_valid),
.auto_anon_out_1_e_bits_sink (coupler_to_bus_named_coh_auto_widget_anon_in_e_bits_sink),
.auto_anon_out_0_a_ready (_coupler_to_bus_named_cbus_auto_widget_anon_in_a_ready), // @[LazyScope.scala:98:27]
.auto_anon_out_0_a_valid (_system_bus_xbar_auto_anon_out_0_a_valid),
.auto_anon_out_0_a_bits_opcode (_system_bus_xbar_auto_anon_out_0_a_bits_opcode),
.auto_anon_out_0_a_bits_param (_system_bus_xbar_auto_anon_out_0_a_bits_param),
.auto_anon_out_0_a_bits_size (_system_bus_xbar_auto_anon_out_0_a_bits_size),
.auto_anon_out_0_a_bits_source (_system_bus_xbar_auto_anon_out_0_a_bits_source),
.auto_anon_out_0_a_bits_address (_system_bus_xbar_auto_anon_out_0_a_bits_address),
.auto_anon_out_0_a_bits_mask (_system_bus_xbar_auto_anon_out_0_a_bits_mask),
.auto_anon_out_0_a_bits_data (_system_bus_xbar_auto_anon_out_0_a_bits_data),
.auto_anon_out_0_a_bits_corrupt (_system_bus_xbar_auto_anon_out_0_a_bits_corrupt),
.auto_anon_out_0_d_ready (_system_bus_xbar_auto_anon_out_0_d_ready),
.auto_anon_out_0_d_valid (_coupler_to_bus_named_cbus_auto_widget_anon_in_d_valid), // @[LazyScope.scala:98:27]
.auto_anon_out_0_d_bits_opcode (_coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_opcode), // @[LazyScope.scala:98:27]
.auto_anon_out_0_d_bits_param (_coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_param), // @[LazyScope.scala:98:27]
.auto_anon_out_0_d_bits_size (_coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_size), // @[LazyScope.scala:98:27]
.auto_anon_out_0_d_bits_source (_coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_source), // @[LazyScope.scala:98:27]
.auto_anon_out_0_d_bits_sink (_coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_sink), // @[LazyScope.scala:98:27]
.auto_anon_out_0_d_bits_denied (_coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_denied), // @[LazyScope.scala:98:27]
.auto_anon_out_0_d_bits_data (_coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_data), // @[LazyScope.scala:98:27]
.auto_anon_out_0_d_bits_corrupt (_coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_corrupt) // @[LazyScope.scala:98:27]
); // @[SystemBus.scala:47:43]
TLInterconnectCoupler_sbus_to_bus_named_cbus coupler_to_bus_named_cbus ( // @[LazyScope.scala:98:27]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_widget_anon_in_a_ready (_coupler_to_bus_named_cbus_auto_widget_anon_in_a_ready),
.auto_widget_anon_in_a_valid (_system_bus_xbar_auto_anon_out_0_a_valid), // @[SystemBus.scala:47:43]
.auto_widget_anon_in_a_bits_opcode (_system_bus_xbar_auto_anon_out_0_a_bits_opcode), // @[SystemBus.scala:47:43]
.auto_widget_anon_in_a_bits_param (_system_bus_xbar_auto_anon_out_0_a_bits_param), // @[SystemBus.scala:47:43]
.auto_widget_anon_in_a_bits_size (_system_bus_xbar_auto_anon_out_0_a_bits_size), // @[SystemBus.scala:47:43]
.auto_widget_anon_in_a_bits_source (_system_bus_xbar_auto_anon_out_0_a_bits_source), // @[SystemBus.scala:47:43]
.auto_widget_anon_in_a_bits_address (_system_bus_xbar_auto_anon_out_0_a_bits_address), // @[SystemBus.scala:47:43]
.auto_widget_anon_in_a_bits_mask (_system_bus_xbar_auto_anon_out_0_a_bits_mask), // @[SystemBus.scala:47:43]
.auto_widget_anon_in_a_bits_data (_system_bus_xbar_auto_anon_out_0_a_bits_data), // @[SystemBus.scala:47:43]
.auto_widget_anon_in_a_bits_corrupt (_system_bus_xbar_auto_anon_out_0_a_bits_corrupt), // @[SystemBus.scala:47:43]
.auto_widget_anon_in_d_ready (_system_bus_xbar_auto_anon_out_0_d_ready), // @[SystemBus.scala:47:43]
.auto_widget_anon_in_d_valid (_coupler_to_bus_named_cbus_auto_widget_anon_in_d_valid),
.auto_widget_anon_in_d_bits_opcode (_coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_opcode),
.auto_widget_anon_in_d_bits_param (_coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_param),
.auto_widget_anon_in_d_bits_size (_coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_size),
.auto_widget_anon_in_d_bits_source (_coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_source),
.auto_widget_anon_in_d_bits_sink (_coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_sink),
.auto_widget_anon_in_d_bits_denied (_coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_denied),
.auto_widget_anon_in_d_bits_data (_coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_data),
.auto_widget_anon_in_d_bits_corrupt (_coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_corrupt),
.auto_bus_xing_out_a_ready (auto_coupler_to_bus_named_cbus_bus_xing_out_a_ready_0), // @[ClockDomain.scala:14:9]
.auto_bus_xing_out_a_valid (auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid_0),
.auto_bus_xing_out_a_bits_opcode (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode_0),
.auto_bus_xing_out_a_bits_param (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param_0),
.auto_bus_xing_out_a_bits_size (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size_0),
.auto_bus_xing_out_a_bits_source (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source_0),
.auto_bus_xing_out_a_bits_address (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address_0),
.auto_bus_xing_out_a_bits_mask (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask_0),
.auto_bus_xing_out_a_bits_data (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data_0),
.auto_bus_xing_out_a_bits_corrupt (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt_0),
.auto_bus_xing_out_d_ready (auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready_0),
.auto_bus_xing_out_d_valid (auto_coupler_to_bus_named_cbus_bus_xing_out_d_valid_0), // @[ClockDomain.scala:14:9]
.auto_bus_xing_out_d_bits_opcode (auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_opcode_0), // @[ClockDomain.scala:14:9]
.auto_bus_xing_out_d_bits_param (auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_param_0), // @[ClockDomain.scala:14:9]
.auto_bus_xing_out_d_bits_size (auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_size_0), // @[ClockDomain.scala:14:9]
.auto_bus_xing_out_d_bits_source (auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_source_0), // @[ClockDomain.scala:14:9]
.auto_bus_xing_out_d_bits_sink (auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_sink_0), // @[ClockDomain.scala:14:9]
.auto_bus_xing_out_d_bits_denied (auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_denied_0), // @[ClockDomain.scala:14:9]
.auto_bus_xing_out_d_bits_data (auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_data_0), // @[ClockDomain.scala:14:9]
.auto_bus_xing_out_d_bits_corrupt (auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_corrupt_0) // @[ClockDomain.scala:14:9]
); // @[LazyScope.scala:98:27]
TLInterconnectCoupler_sbus_from_bus_named_fbus coupler_from_bus_named_fbus ( // @[LazyScope.scala:98:27]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_widget_anon_out_a_ready (fixer_auto_anon_in_0_a_ready), // @[FIFOFixer.scala:50:9]
.auto_widget_anon_out_a_valid (fixer_auto_anon_in_0_a_valid),
.auto_widget_anon_out_a_bits_opcode (fixer_auto_anon_in_0_a_bits_opcode),
.auto_widget_anon_out_a_bits_param (fixer_auto_anon_in_0_a_bits_param),
.auto_widget_anon_out_a_bits_size (fixer_auto_anon_in_0_a_bits_size),
.auto_widget_anon_out_a_bits_source (fixer_auto_anon_in_0_a_bits_source),
.auto_widget_anon_out_a_bits_address (fixer_auto_anon_in_0_a_bits_address),
.auto_widget_anon_out_a_bits_mask (fixer_auto_anon_in_0_a_bits_mask),
.auto_widget_anon_out_a_bits_data (fixer_auto_anon_in_0_a_bits_data),
.auto_widget_anon_out_a_bits_corrupt (fixer_auto_anon_in_0_a_bits_corrupt),
.auto_widget_anon_out_d_ready (fixer_auto_anon_in_0_d_ready),
.auto_widget_anon_out_d_valid (fixer_auto_anon_in_0_d_valid), // @[FIFOFixer.scala:50:9]
.auto_widget_anon_out_d_bits_opcode (fixer_auto_anon_in_0_d_bits_opcode), // @[FIFOFixer.scala:50:9]
.auto_widget_anon_out_d_bits_param (fixer_auto_anon_in_0_d_bits_param), // @[FIFOFixer.scala:50:9]
.auto_widget_anon_out_d_bits_size (fixer_auto_anon_in_0_d_bits_size), // @[FIFOFixer.scala:50:9]
.auto_widget_anon_out_d_bits_source (fixer_auto_anon_in_0_d_bits_source), // @[FIFOFixer.scala:50:9]
.auto_widget_anon_out_d_bits_sink (fixer_auto_anon_in_0_d_bits_sink), // @[FIFOFixer.scala:50:9]
.auto_widget_anon_out_d_bits_denied (fixer_auto_anon_in_0_d_bits_denied), // @[FIFOFixer.scala:50:9]
.auto_widget_anon_out_d_bits_data (fixer_auto_anon_in_0_d_bits_data), // @[FIFOFixer.scala:50:9]
.auto_widget_anon_out_d_bits_corrupt (fixer_auto_anon_in_0_d_bits_corrupt), // @[FIFOFixer.scala:50:9]
.auto_bus_xing_in_a_ready (auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready_0),
.auto_bus_xing_in_a_valid (auto_coupler_from_bus_named_fbus_bus_xing_in_a_valid_0), // @[ClockDomain.scala:14:9]
.auto_bus_xing_in_a_bits_opcode (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_opcode_0), // @[ClockDomain.scala:14:9]
.auto_bus_xing_in_a_bits_param (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_param_0), // @[ClockDomain.scala:14:9]
.auto_bus_xing_in_a_bits_size (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_size_0), // @[ClockDomain.scala:14:9]
.auto_bus_xing_in_a_bits_source (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_source_0), // @[ClockDomain.scala:14:9]
.auto_bus_xing_in_a_bits_address (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_address_0), // @[ClockDomain.scala:14:9]
.auto_bus_xing_in_a_bits_mask (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_mask_0), // @[ClockDomain.scala:14:9]
.auto_bus_xing_in_a_bits_data (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_data_0), // @[ClockDomain.scala:14:9]
.auto_bus_xing_in_a_bits_corrupt (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_corrupt_0), // @[ClockDomain.scala:14:9]
.auto_bus_xing_in_d_ready (auto_coupler_from_bus_named_fbus_bus_xing_in_d_ready_0), // @[ClockDomain.scala:14:9]
.auto_bus_xing_in_d_valid (auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid_0),
.auto_bus_xing_in_d_bits_opcode (auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode_0),
.auto_bus_xing_in_d_bits_param (auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param_0),
.auto_bus_xing_in_d_bits_size (auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size_0),
.auto_bus_xing_in_d_bits_source (auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source_0),
.auto_bus_xing_in_d_bits_sink (auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink_0),
.auto_bus_xing_in_d_bits_denied (auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied_0),
.auto_bus_xing_in_d_bits_data (auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data_0),
.auto_bus_xing_in_d_bits_corrupt (auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt_0)
); // @[LazyScope.scala:98:27]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_ready_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_valid_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_param = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_address = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_address_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_ready_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_valid_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_opcode = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_param = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_size = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_source = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_sink = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_sink_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_denied = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_denied_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_data = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_corrupt = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_corrupt_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_ready_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_valid_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_opcode = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_param = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_size = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_source = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_sink = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_sink_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_denied = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_denied_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_data = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_corrupt = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_corrupt_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_valid = auto_coupler_to_bus_named_coh_widget_anon_out_a_valid_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_opcode = auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_param = auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_size = auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_source = auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_address = auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_mask = auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_data = auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_corrupt = auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_b_ready = auto_coupler_to_bus_named_coh_widget_anon_out_b_ready_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_c_valid = auto_coupler_to_bus_named_coh_widget_anon_out_c_valid_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_opcode = auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_param = auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_size = auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_source = auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_address = auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_address_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_data = auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_corrupt = auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_corrupt_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_d_ready = auto_coupler_to_bus_named_coh_widget_anon_out_d_ready_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_e_valid = auto_coupler_to_bus_named_coh_widget_anon_out_e_valid_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_coh_widget_anon_out_e_bits_sink = auto_coupler_to_bus_named_coh_widget_anon_out_e_bits_sink_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready = auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid = auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode = auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param = auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size = auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source = auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink = auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied = auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data = auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt = auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid = auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode = auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param = auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size = auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source = auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address = auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask = auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data = auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt = auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready = auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready_0; // @[ClockDomain.scala:14:9]
assign auto_fixedClockNode_anon_out_2_clock = auto_fixedClockNode_anon_out_2_clock_0; // @[ClockDomain.scala:14:9]
assign auto_fixedClockNode_anon_out_2_reset = auto_fixedClockNode_anon_out_2_reset_0; // @[ClockDomain.scala:14:9]
assign auto_fixedClockNode_anon_out_1_clock = auto_fixedClockNode_anon_out_1_clock_0; // @[ClockDomain.scala:14:9]
assign auto_fixedClockNode_anon_out_1_reset = auto_fixedClockNode_anon_out_1_reset_0; // @[ClockDomain.scala:14:9]
assign auto_fixedClockNode_anon_out_0_clock = auto_fixedClockNode_anon_out_0_clock_0; // @[ClockDomain.scala:14:9]
assign auto_fixedClockNode_anon_out_0_reset = auto_fixedClockNode_anon_out_0_reset_0; // @[ClockDomain.scala:14:9]
assign auto_sbus_clock_groups_out_member_coh_0_clock = auto_sbus_clock_groups_out_member_coh_0_clock_0; // @[ClockDomain.scala:14:9]
assign auto_sbus_clock_groups_out_member_coh_0_reset = auto_sbus_clock_groups_out_member_coh_0_reset_0; // @[ClockDomain.scala:14:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RoundRawFNToRecFN_e8_s24_5 :
output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_5
connect roundAnyRawFNToRecFN.io.invalidExc, io.invalidExc
connect roundAnyRawFNToRecFN.io.infiniteExc, io.infiniteExc
connect roundAnyRawFNToRecFN.io.in.sig, io.in.sig
connect roundAnyRawFNToRecFN.io.in.sExp, io.in.sExp
connect roundAnyRawFNToRecFN.io.in.sign, io.in.sign
connect roundAnyRawFNToRecFN.io.in.isZero, io.in.isZero
connect roundAnyRawFNToRecFN.io.in.isInf, io.in.isInf
connect roundAnyRawFNToRecFN.io.in.isNaN, io.in.isNaN
connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode
connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess
connect io.out, roundAnyRawFNToRecFN.io.out
connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags | module RoundRawFNToRecFN_e8_s24_5( // @[RoundAnyRawFNToRecFN.scala:295:5]
input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16]
input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16]
input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16]
input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_detectTininess, // @[RoundAnyRawFNToRecFN.scala:299:16]
output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16]
output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16]
);
wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_detectTininess_0 = io_detectTininess; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15]
wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_5 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15]
.io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_roundingMode (io_roundingMode_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_detectTininess (io_detectTininess_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags_0)
); // @[RoundAnyRawFNToRecFN.scala:310:15]
assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module InputUnit_26 :
input clock : Clock
input reset : Reset
output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}}, flip vcalloc_resp : { vc_sel : { `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}, flip out_credit_available : { `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}[1], debug : { va_stall : UInt<3>, sa_stall : UInt<3>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}}
inst input_buffer of InputBuffer_26
connect input_buffer.clock, clock
connect input_buffer.reset, reset
connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id
connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id
connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node
connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id
connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node
connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id
connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload
connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail
connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head
connect input_buffer.io.enq[0].valid, io.in.flit[0].valid
connect input_buffer.io.deq[0].ready, UInt<1>(0h0)
connect input_buffer.io.deq[1].ready, UInt<1>(0h0)
connect input_buffer.io.deq[2].ready, UInt<1>(0h0)
connect input_buffer.io.deq[3].ready, UInt<1>(0h0)
connect input_buffer.io.deq[4].ready, UInt<1>(0h0)
connect input_buffer.io.deq[5].ready, UInt<1>(0h0)
connect input_buffer.io.deq[6].ready, UInt<1>(0h0)
connect input_buffer.io.deq[7].ready, UInt<1>(0h0)
inst route_arbiter of Arbiter8_RouteComputerReq_26
connect route_arbiter.clock, clock
connect route_arbiter.reset, reset
connect io.router_req.bits, route_arbiter.io.out.bits
connect io.router_req.valid, route_arbiter.io.out.valid
connect route_arbiter.io.out.ready, io.router_req.ready
reg states : { g : UInt<3>, vc_sel : { `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, fifo_deps : UInt<8>}[8], clock
node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head)
when _T :
node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<4>(0h8))
node _T_2 = asUInt(reset)
node _T_3 = eq(_T_2, UInt<1>(0h0))
when _T_3 :
node _T_4 = eq(_T_1, UInt<1>(0h0))
when _T_4 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf
assert(clock, _T_1, UInt<1>(0h1), "") : assert
node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0))
node _T_6 = asUInt(reset)
node _T_7 = eq(_T_6, UInt<1>(0h0))
when _T_7 :
node _T_8 = eq(_T_5, UInt<1>(0h0))
when _T_8 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1
assert(clock, _T_5, UInt<1>(0h1), "") : assert_1
node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<5>(0h13))
node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1))
connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[2], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[3], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[4], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[5], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[6], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[7], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[2], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[3], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[4], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[5], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[6], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[7], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[2], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[3], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[4], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[5], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[6], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[7], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow
connect route_arbiter.io.in[0].valid, UInt<1>(0h0)
invalidate route_arbiter.io.in[0].bits.flow.egress_node_id
invalidate route_arbiter.io.in[0].bits.flow.egress_node
invalidate route_arbiter.io.in[0].bits.flow.ingress_node_id
invalidate route_arbiter.io.in[0].bits.flow.ingress_node
invalidate route_arbiter.io.in[0].bits.flow.vnet_id
invalidate route_arbiter.io.in[0].bits.src_virt_id
connect route_arbiter.io.in[1].valid, UInt<1>(0h0)
invalidate route_arbiter.io.in[1].bits.flow.egress_node_id
invalidate route_arbiter.io.in[1].bits.flow.egress_node
invalidate route_arbiter.io.in[1].bits.flow.ingress_node_id
invalidate route_arbiter.io.in[1].bits.flow.ingress_node
invalidate route_arbiter.io.in[1].bits.flow.vnet_id
invalidate route_arbiter.io.in[1].bits.src_virt_id
connect route_arbiter.io.in[2].valid, UInt<1>(0h0)
invalidate route_arbiter.io.in[2].bits.flow.egress_node_id
invalidate route_arbiter.io.in[2].bits.flow.egress_node
invalidate route_arbiter.io.in[2].bits.flow.ingress_node_id
invalidate route_arbiter.io.in[2].bits.flow.ingress_node
invalidate route_arbiter.io.in[2].bits.flow.vnet_id
invalidate route_arbiter.io.in[2].bits.src_virt_id
connect route_arbiter.io.in[3].valid, UInt<1>(0h0)
invalidate route_arbiter.io.in[3].bits.flow.egress_node_id
invalidate route_arbiter.io.in[3].bits.flow.egress_node
invalidate route_arbiter.io.in[3].bits.flow.ingress_node_id
invalidate route_arbiter.io.in[3].bits.flow.ingress_node
invalidate route_arbiter.io.in[3].bits.flow.vnet_id
invalidate route_arbiter.io.in[3].bits.src_virt_id
node _route_arbiter_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h1))
connect route_arbiter.io.in[4].valid, _route_arbiter_io_in_4_valid_T
connect route_arbiter.io.in[4].bits.flow.egress_node_id, states[4].flow.egress_node_id
connect route_arbiter.io.in[4].bits.flow.egress_node, states[4].flow.egress_node
connect route_arbiter.io.in[4].bits.flow.ingress_node_id, states[4].flow.ingress_node_id
connect route_arbiter.io.in[4].bits.flow.ingress_node, states[4].flow.ingress_node
connect route_arbiter.io.in[4].bits.flow.vnet_id, states[4].flow.vnet_id
connect route_arbiter.io.in[4].bits.src_virt_id, UInt<3>(0h4)
node _T_9 = and(route_arbiter.io.in[4].ready, route_arbiter.io.in[4].valid)
when _T_9 :
connect states[4].g, UInt<3>(0h2)
node _route_arbiter_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h1))
connect route_arbiter.io.in[5].valid, _route_arbiter_io_in_5_valid_T
connect route_arbiter.io.in[5].bits.flow.egress_node_id, states[5].flow.egress_node_id
connect route_arbiter.io.in[5].bits.flow.egress_node, states[5].flow.egress_node
connect route_arbiter.io.in[5].bits.flow.ingress_node_id, states[5].flow.ingress_node_id
connect route_arbiter.io.in[5].bits.flow.ingress_node, states[5].flow.ingress_node
connect route_arbiter.io.in[5].bits.flow.vnet_id, states[5].flow.vnet_id
connect route_arbiter.io.in[5].bits.src_virt_id, UInt<3>(0h5)
node _T_10 = and(route_arbiter.io.in[5].ready, route_arbiter.io.in[5].valid)
when _T_10 :
connect states[5].g, UInt<3>(0h2)
node _route_arbiter_io_in_6_valid_T = eq(states[6].g, UInt<3>(0h1))
connect route_arbiter.io.in[6].valid, _route_arbiter_io_in_6_valid_T
connect route_arbiter.io.in[6].bits.flow.egress_node_id, states[6].flow.egress_node_id
connect route_arbiter.io.in[6].bits.flow.egress_node, states[6].flow.egress_node
connect route_arbiter.io.in[6].bits.flow.ingress_node_id, states[6].flow.ingress_node_id
connect route_arbiter.io.in[6].bits.flow.ingress_node, states[6].flow.ingress_node
connect route_arbiter.io.in[6].bits.flow.vnet_id, states[6].flow.vnet_id
connect route_arbiter.io.in[6].bits.src_virt_id, UInt<3>(0h6)
node _T_11 = and(route_arbiter.io.in[6].ready, route_arbiter.io.in[6].valid)
when _T_11 :
connect states[6].g, UInt<3>(0h2)
node _route_arbiter_io_in_7_valid_T = eq(states[7].g, UInt<3>(0h1))
connect route_arbiter.io.in[7].valid, _route_arbiter_io_in_7_valid_T
connect route_arbiter.io.in[7].bits.flow.egress_node_id, states[7].flow.egress_node_id
connect route_arbiter.io.in[7].bits.flow.egress_node, states[7].flow.egress_node
connect route_arbiter.io.in[7].bits.flow.ingress_node_id, states[7].flow.ingress_node_id
connect route_arbiter.io.in[7].bits.flow.ingress_node, states[7].flow.ingress_node
connect route_arbiter.io.in[7].bits.flow.vnet_id, states[7].flow.vnet_id
connect route_arbiter.io.in[7].bits.src_virt_id, UInt<3>(0h7)
node _T_12 = and(route_arbiter.io.in[7].ready, route_arbiter.io.in[7].valid)
when _T_12 :
connect states[7].g, UInt<3>(0h2)
node _T_13 = and(io.router_req.ready, io.router_req.valid)
when _T_13 :
node _T_14 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1))
node _T_15 = asUInt(reset)
node _T_16 = eq(_T_15, UInt<1>(0h0))
when _T_16 :
node _T_17 = eq(_T_14, UInt<1>(0h0))
when _T_17 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2
assert(clock, _T_14, UInt<1>(0h1), "") : assert_2
connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2)
node _T_18 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id)
when _T_18 :
connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[0].vc_sel.`2`, io.router_resp.vc_sel.`2`
node _T_19 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id)
when _T_19 :
connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[1].vc_sel.`2`, io.router_resp.vc_sel.`2`
node _T_20 = eq(UInt<2>(0h2), io.router_req.bits.src_virt_id)
when _T_20 :
connect states[2].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[2].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[2].vc_sel.`2`, io.router_resp.vc_sel.`2`
node _T_21 = eq(UInt<2>(0h3), io.router_req.bits.src_virt_id)
when _T_21 :
connect states[3].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[3].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[3].vc_sel.`2`, io.router_resp.vc_sel.`2`
node _T_22 = eq(UInt<3>(0h4), io.router_req.bits.src_virt_id)
when _T_22 :
connect states[4].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[4].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[4].vc_sel.`2`, io.router_resp.vc_sel.`2`
node _T_23 = eq(UInt<3>(0h5), io.router_req.bits.src_virt_id)
when _T_23 :
connect states[5].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[5].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[5].vc_sel.`2`, io.router_resp.vc_sel.`2`
node _T_24 = eq(UInt<3>(0h6), io.router_req.bits.src_virt_id)
when _T_24 :
connect states[6].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[6].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[6].vc_sel.`2`, io.router_resp.vc_sel.`2`
node _T_25 = eq(UInt<3>(0h7), io.router_req.bits.src_virt_id)
when _T_25 :
connect states[7].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[7].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[7].vc_sel.`2`, io.router_resp.vc_sel.`2`
regreset mask : UInt<8>, clock, reset, UInt<8>(0h0)
wire vcalloc_reqs : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}[8]
wire vcalloc_vals : UInt<1>[8]
node vcalloc_filter_lo_lo = cat(vcalloc_vals[1], vcalloc_vals[0])
node vcalloc_filter_lo_hi = cat(vcalloc_vals[3], vcalloc_vals[2])
node vcalloc_filter_lo = cat(vcalloc_filter_lo_hi, vcalloc_filter_lo_lo)
node vcalloc_filter_hi_lo = cat(vcalloc_vals[5], vcalloc_vals[4])
node vcalloc_filter_hi_hi = cat(vcalloc_vals[7], vcalloc_vals[6])
node vcalloc_filter_hi = cat(vcalloc_filter_hi_hi, vcalloc_filter_hi_lo)
node _vcalloc_filter_T = cat(vcalloc_filter_hi, vcalloc_filter_lo)
node vcalloc_filter_lo_lo_1 = cat(vcalloc_vals[1], vcalloc_vals[0])
node vcalloc_filter_lo_hi_1 = cat(vcalloc_vals[3], vcalloc_vals[2])
node vcalloc_filter_lo_1 = cat(vcalloc_filter_lo_hi_1, vcalloc_filter_lo_lo_1)
node vcalloc_filter_hi_lo_1 = cat(vcalloc_vals[5], vcalloc_vals[4])
node vcalloc_filter_hi_hi_1 = cat(vcalloc_vals[7], vcalloc_vals[6])
node vcalloc_filter_hi_1 = cat(vcalloc_filter_hi_hi_1, vcalloc_filter_hi_lo_1)
node _vcalloc_filter_T_1 = cat(vcalloc_filter_hi_1, vcalloc_filter_lo_1)
node _vcalloc_filter_T_2 = not(mask)
node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2)
node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3)
node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0)
node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1)
node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2)
node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3)
node _vcalloc_filter_T_9 = bits(_vcalloc_filter_T_4, 4, 4)
node _vcalloc_filter_T_10 = bits(_vcalloc_filter_T_4, 5, 5)
node _vcalloc_filter_T_11 = bits(_vcalloc_filter_T_4, 6, 6)
node _vcalloc_filter_T_12 = bits(_vcalloc_filter_T_4, 7, 7)
node _vcalloc_filter_T_13 = bits(_vcalloc_filter_T_4, 8, 8)
node _vcalloc_filter_T_14 = bits(_vcalloc_filter_T_4, 9, 9)
node _vcalloc_filter_T_15 = bits(_vcalloc_filter_T_4, 10, 10)
node _vcalloc_filter_T_16 = bits(_vcalloc_filter_T_4, 11, 11)
node _vcalloc_filter_T_17 = bits(_vcalloc_filter_T_4, 12, 12)
node _vcalloc_filter_T_18 = bits(_vcalloc_filter_T_4, 13, 13)
node _vcalloc_filter_T_19 = bits(_vcalloc_filter_T_4, 14, 14)
node _vcalloc_filter_T_20 = bits(_vcalloc_filter_T_4, 15, 15)
node _vcalloc_filter_T_21 = mux(_vcalloc_filter_T_20, UInt<16>(0h8000), UInt<16>(0h0))
node _vcalloc_filter_T_22 = mux(_vcalloc_filter_T_19, UInt<16>(0h4000), _vcalloc_filter_T_21)
node _vcalloc_filter_T_23 = mux(_vcalloc_filter_T_18, UInt<16>(0h2000), _vcalloc_filter_T_22)
node _vcalloc_filter_T_24 = mux(_vcalloc_filter_T_17, UInt<16>(0h1000), _vcalloc_filter_T_23)
node _vcalloc_filter_T_25 = mux(_vcalloc_filter_T_16, UInt<16>(0h800), _vcalloc_filter_T_24)
node _vcalloc_filter_T_26 = mux(_vcalloc_filter_T_15, UInt<16>(0h400), _vcalloc_filter_T_25)
node _vcalloc_filter_T_27 = mux(_vcalloc_filter_T_14, UInt<16>(0h200), _vcalloc_filter_T_26)
node _vcalloc_filter_T_28 = mux(_vcalloc_filter_T_13, UInt<16>(0h100), _vcalloc_filter_T_27)
node _vcalloc_filter_T_29 = mux(_vcalloc_filter_T_12, UInt<16>(0h80), _vcalloc_filter_T_28)
node _vcalloc_filter_T_30 = mux(_vcalloc_filter_T_11, UInt<16>(0h40), _vcalloc_filter_T_29)
node _vcalloc_filter_T_31 = mux(_vcalloc_filter_T_10, UInt<16>(0h20), _vcalloc_filter_T_30)
node _vcalloc_filter_T_32 = mux(_vcalloc_filter_T_9, UInt<16>(0h10), _vcalloc_filter_T_31)
node _vcalloc_filter_T_33 = mux(_vcalloc_filter_T_8, UInt<16>(0h8), _vcalloc_filter_T_32)
node _vcalloc_filter_T_34 = mux(_vcalloc_filter_T_7, UInt<16>(0h4), _vcalloc_filter_T_33)
node _vcalloc_filter_T_35 = mux(_vcalloc_filter_T_6, UInt<16>(0h2), _vcalloc_filter_T_34)
node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<16>(0h1), _vcalloc_filter_T_35)
node _vcalloc_sel_T = bits(vcalloc_filter, 7, 0)
node _vcalloc_sel_T_1 = shr(vcalloc_filter, 8)
node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1)
node _T_26 = and(io.router_req.ready, io.router_req.valid)
when _T_26 :
node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id)
node _mask_T_1 = sub(_mask_T, UInt<1>(0h1))
node _mask_T_2 = tail(_mask_T_1, 1)
connect mask, _mask_T_2
else :
node _T_27 = or(vcalloc_vals[0], vcalloc_vals[1])
node _T_28 = or(_T_27, vcalloc_vals[2])
node _T_29 = or(_T_28, vcalloc_vals[3])
node _T_30 = or(_T_29, vcalloc_vals[4])
node _T_31 = or(_T_30, vcalloc_vals[5])
node _T_32 = or(_T_31, vcalloc_vals[6])
node _T_33 = or(_T_32, vcalloc_vals[7])
when _T_33 :
node _mask_T_3 = not(UInt<1>(0h0))
node _mask_T_4 = not(UInt<2>(0h0))
node _mask_T_5 = not(UInt<3>(0h0))
node _mask_T_6 = not(UInt<4>(0h0))
node _mask_T_7 = not(UInt<5>(0h0))
node _mask_T_8 = not(UInt<6>(0h0))
node _mask_T_9 = not(UInt<7>(0h0))
node _mask_T_10 = not(UInt<8>(0h0))
node _mask_T_11 = bits(vcalloc_sel, 0, 0)
node _mask_T_12 = bits(vcalloc_sel, 1, 1)
node _mask_T_13 = bits(vcalloc_sel, 2, 2)
node _mask_T_14 = bits(vcalloc_sel, 3, 3)
node _mask_T_15 = bits(vcalloc_sel, 4, 4)
node _mask_T_16 = bits(vcalloc_sel, 5, 5)
node _mask_T_17 = bits(vcalloc_sel, 6, 6)
node _mask_T_18 = bits(vcalloc_sel, 7, 7)
node _mask_T_19 = mux(_mask_T_11, _mask_T_3, UInt<1>(0h0))
node _mask_T_20 = mux(_mask_T_12, _mask_T_4, UInt<1>(0h0))
node _mask_T_21 = mux(_mask_T_13, _mask_T_5, UInt<1>(0h0))
node _mask_T_22 = mux(_mask_T_14, _mask_T_6, UInt<1>(0h0))
node _mask_T_23 = mux(_mask_T_15, _mask_T_7, UInt<1>(0h0))
node _mask_T_24 = mux(_mask_T_16, _mask_T_8, UInt<1>(0h0))
node _mask_T_25 = mux(_mask_T_17, _mask_T_9, UInt<1>(0h0))
node _mask_T_26 = mux(_mask_T_18, _mask_T_10, UInt<1>(0h0))
node _mask_T_27 = or(_mask_T_19, _mask_T_20)
node _mask_T_28 = or(_mask_T_27, _mask_T_21)
node _mask_T_29 = or(_mask_T_28, _mask_T_22)
node _mask_T_30 = or(_mask_T_29, _mask_T_23)
node _mask_T_31 = or(_mask_T_30, _mask_T_24)
node _mask_T_32 = or(_mask_T_31, _mask_T_25)
node _mask_T_33 = or(_mask_T_32, _mask_T_26)
wire _mask_WIRE : UInt<8>
connect _mask_WIRE, _mask_T_33
connect mask, _mask_WIRE
node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1])
node _io_vcalloc_req_valid_T_1 = or(_io_vcalloc_req_valid_T, vcalloc_vals[2])
node _io_vcalloc_req_valid_T_2 = or(_io_vcalloc_req_valid_T_1, vcalloc_vals[3])
node _io_vcalloc_req_valid_T_3 = or(_io_vcalloc_req_valid_T_2, vcalloc_vals[4])
node _io_vcalloc_req_valid_T_4 = or(_io_vcalloc_req_valid_T_3, vcalloc_vals[5])
node _io_vcalloc_req_valid_T_5 = or(_io_vcalloc_req_valid_T_4, vcalloc_vals[6])
node _io_vcalloc_req_valid_T_6 = or(_io_vcalloc_req_valid_T_5, vcalloc_vals[7])
connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_6
node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0)
node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1)
node _io_vcalloc_req_bits_T_2 = bits(vcalloc_sel, 2, 2)
node _io_vcalloc_req_bits_T_3 = bits(vcalloc_sel, 3, 3)
node _io_vcalloc_req_bits_T_4 = bits(vcalloc_sel, 4, 4)
node _io_vcalloc_req_bits_T_5 = bits(vcalloc_sel, 5, 5)
node _io_vcalloc_req_bits_T_6 = bits(vcalloc_sel, 6, 6)
node _io_vcalloc_req_bits_T_7 = bits(vcalloc_sel, 7, 7)
wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}
wire _io_vcalloc_req_bits_WIRE_1 : { `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}
wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[8]
node _io_vcalloc_req_bits_T_8 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_9 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_10 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_11 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_12 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_13 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_15 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_16 = or(_io_vcalloc_req_bits_T_8, _io_vcalloc_req_bits_T_9)
node _io_vcalloc_req_bits_T_17 = or(_io_vcalloc_req_bits_T_16, _io_vcalloc_req_bits_T_10)
node _io_vcalloc_req_bits_T_18 = or(_io_vcalloc_req_bits_T_17, _io_vcalloc_req_bits_T_11)
node _io_vcalloc_req_bits_T_19 = or(_io_vcalloc_req_bits_T_18, _io_vcalloc_req_bits_T_12)
node _io_vcalloc_req_bits_T_20 = or(_io_vcalloc_req_bits_T_19, _io_vcalloc_req_bits_T_13)
node _io_vcalloc_req_bits_T_21 = or(_io_vcalloc_req_bits_T_20, _io_vcalloc_req_bits_T_14)
node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_21, _io_vcalloc_req_bits_T_15)
wire _io_vcalloc_req_bits_WIRE_3 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_22
connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3
node _io_vcalloc_req_bits_T_23 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_24 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_25 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_26 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_27 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_28 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_29 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_30 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_31 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_24)
node _io_vcalloc_req_bits_T_32 = or(_io_vcalloc_req_bits_T_31, _io_vcalloc_req_bits_T_25)
node _io_vcalloc_req_bits_T_33 = or(_io_vcalloc_req_bits_T_32, _io_vcalloc_req_bits_T_26)
node _io_vcalloc_req_bits_T_34 = or(_io_vcalloc_req_bits_T_33, _io_vcalloc_req_bits_T_27)
node _io_vcalloc_req_bits_T_35 = or(_io_vcalloc_req_bits_T_34, _io_vcalloc_req_bits_T_28)
node _io_vcalloc_req_bits_T_36 = or(_io_vcalloc_req_bits_T_35, _io_vcalloc_req_bits_T_29)
node _io_vcalloc_req_bits_T_37 = or(_io_vcalloc_req_bits_T_36, _io_vcalloc_req_bits_T_30)
wire _io_vcalloc_req_bits_WIRE_4 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_37
connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4
node _io_vcalloc_req_bits_T_38 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_39 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_40 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_41 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_42 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_43 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_44 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_45 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_46 = or(_io_vcalloc_req_bits_T_38, _io_vcalloc_req_bits_T_39)
node _io_vcalloc_req_bits_T_47 = or(_io_vcalloc_req_bits_T_46, _io_vcalloc_req_bits_T_40)
node _io_vcalloc_req_bits_T_48 = or(_io_vcalloc_req_bits_T_47, _io_vcalloc_req_bits_T_41)
node _io_vcalloc_req_bits_T_49 = or(_io_vcalloc_req_bits_T_48, _io_vcalloc_req_bits_T_42)
node _io_vcalloc_req_bits_T_50 = or(_io_vcalloc_req_bits_T_49, _io_vcalloc_req_bits_T_43)
node _io_vcalloc_req_bits_T_51 = or(_io_vcalloc_req_bits_T_50, _io_vcalloc_req_bits_T_44)
node _io_vcalloc_req_bits_T_52 = or(_io_vcalloc_req_bits_T_51, _io_vcalloc_req_bits_T_45)
wire _io_vcalloc_req_bits_WIRE_5 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_5, _io_vcalloc_req_bits_T_52
connect _io_vcalloc_req_bits_WIRE_2[2], _io_vcalloc_req_bits_WIRE_5
node _io_vcalloc_req_bits_T_53 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_54 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_55 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_56 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_57 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_58 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_59 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_60 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_61 = or(_io_vcalloc_req_bits_T_53, _io_vcalloc_req_bits_T_54)
node _io_vcalloc_req_bits_T_62 = or(_io_vcalloc_req_bits_T_61, _io_vcalloc_req_bits_T_55)
node _io_vcalloc_req_bits_T_63 = or(_io_vcalloc_req_bits_T_62, _io_vcalloc_req_bits_T_56)
node _io_vcalloc_req_bits_T_64 = or(_io_vcalloc_req_bits_T_63, _io_vcalloc_req_bits_T_57)
node _io_vcalloc_req_bits_T_65 = or(_io_vcalloc_req_bits_T_64, _io_vcalloc_req_bits_T_58)
node _io_vcalloc_req_bits_T_66 = or(_io_vcalloc_req_bits_T_65, _io_vcalloc_req_bits_T_59)
node _io_vcalloc_req_bits_T_67 = or(_io_vcalloc_req_bits_T_66, _io_vcalloc_req_bits_T_60)
wire _io_vcalloc_req_bits_WIRE_6 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_6, _io_vcalloc_req_bits_T_67
connect _io_vcalloc_req_bits_WIRE_2[3], _io_vcalloc_req_bits_WIRE_6
node _io_vcalloc_req_bits_T_68 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_69 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_70 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_71 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_72 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_73 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_74 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_75 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_76 = or(_io_vcalloc_req_bits_T_68, _io_vcalloc_req_bits_T_69)
node _io_vcalloc_req_bits_T_77 = or(_io_vcalloc_req_bits_T_76, _io_vcalloc_req_bits_T_70)
node _io_vcalloc_req_bits_T_78 = or(_io_vcalloc_req_bits_T_77, _io_vcalloc_req_bits_T_71)
node _io_vcalloc_req_bits_T_79 = or(_io_vcalloc_req_bits_T_78, _io_vcalloc_req_bits_T_72)
node _io_vcalloc_req_bits_T_80 = or(_io_vcalloc_req_bits_T_79, _io_vcalloc_req_bits_T_73)
node _io_vcalloc_req_bits_T_81 = or(_io_vcalloc_req_bits_T_80, _io_vcalloc_req_bits_T_74)
node _io_vcalloc_req_bits_T_82 = or(_io_vcalloc_req_bits_T_81, _io_vcalloc_req_bits_T_75)
wire _io_vcalloc_req_bits_WIRE_7 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_82
connect _io_vcalloc_req_bits_WIRE_2[4], _io_vcalloc_req_bits_WIRE_7
node _io_vcalloc_req_bits_T_83 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_84 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_85 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_86 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_87 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_88 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_89 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_90 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_91 = or(_io_vcalloc_req_bits_T_83, _io_vcalloc_req_bits_T_84)
node _io_vcalloc_req_bits_T_92 = or(_io_vcalloc_req_bits_T_91, _io_vcalloc_req_bits_T_85)
node _io_vcalloc_req_bits_T_93 = or(_io_vcalloc_req_bits_T_92, _io_vcalloc_req_bits_T_86)
node _io_vcalloc_req_bits_T_94 = or(_io_vcalloc_req_bits_T_93, _io_vcalloc_req_bits_T_87)
node _io_vcalloc_req_bits_T_95 = or(_io_vcalloc_req_bits_T_94, _io_vcalloc_req_bits_T_88)
node _io_vcalloc_req_bits_T_96 = or(_io_vcalloc_req_bits_T_95, _io_vcalloc_req_bits_T_89)
node _io_vcalloc_req_bits_T_97 = or(_io_vcalloc_req_bits_T_96, _io_vcalloc_req_bits_T_90)
wire _io_vcalloc_req_bits_WIRE_8 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_8, _io_vcalloc_req_bits_T_97
connect _io_vcalloc_req_bits_WIRE_2[5], _io_vcalloc_req_bits_WIRE_8
node _io_vcalloc_req_bits_T_98 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_99 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_100 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_101 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_102 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_103 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_104 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_105 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_106 = or(_io_vcalloc_req_bits_T_98, _io_vcalloc_req_bits_T_99)
node _io_vcalloc_req_bits_T_107 = or(_io_vcalloc_req_bits_T_106, _io_vcalloc_req_bits_T_100)
node _io_vcalloc_req_bits_T_108 = or(_io_vcalloc_req_bits_T_107, _io_vcalloc_req_bits_T_101)
node _io_vcalloc_req_bits_T_109 = or(_io_vcalloc_req_bits_T_108, _io_vcalloc_req_bits_T_102)
node _io_vcalloc_req_bits_T_110 = or(_io_vcalloc_req_bits_T_109, _io_vcalloc_req_bits_T_103)
node _io_vcalloc_req_bits_T_111 = or(_io_vcalloc_req_bits_T_110, _io_vcalloc_req_bits_T_104)
node _io_vcalloc_req_bits_T_112 = or(_io_vcalloc_req_bits_T_111, _io_vcalloc_req_bits_T_105)
wire _io_vcalloc_req_bits_WIRE_9 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_9, _io_vcalloc_req_bits_T_112
connect _io_vcalloc_req_bits_WIRE_2[6], _io_vcalloc_req_bits_WIRE_9
node _io_vcalloc_req_bits_T_113 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_114 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_115 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_116 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_117 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_118 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_119 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_120 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_121 = or(_io_vcalloc_req_bits_T_113, _io_vcalloc_req_bits_T_114)
node _io_vcalloc_req_bits_T_122 = or(_io_vcalloc_req_bits_T_121, _io_vcalloc_req_bits_T_115)
node _io_vcalloc_req_bits_T_123 = or(_io_vcalloc_req_bits_T_122, _io_vcalloc_req_bits_T_116)
node _io_vcalloc_req_bits_T_124 = or(_io_vcalloc_req_bits_T_123, _io_vcalloc_req_bits_T_117)
node _io_vcalloc_req_bits_T_125 = or(_io_vcalloc_req_bits_T_124, _io_vcalloc_req_bits_T_118)
node _io_vcalloc_req_bits_T_126 = or(_io_vcalloc_req_bits_T_125, _io_vcalloc_req_bits_T_119)
node _io_vcalloc_req_bits_T_127 = or(_io_vcalloc_req_bits_T_126, _io_vcalloc_req_bits_T_120)
wire _io_vcalloc_req_bits_WIRE_10 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_10, _io_vcalloc_req_bits_T_127
connect _io_vcalloc_req_bits_WIRE_2[7], _io_vcalloc_req_bits_WIRE_10
connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2
wire _io_vcalloc_req_bits_WIRE_11 : UInt<1>[8]
node _io_vcalloc_req_bits_T_128 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_129 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_130 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_131 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_132 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_133 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_134 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_135 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_136 = or(_io_vcalloc_req_bits_T_128, _io_vcalloc_req_bits_T_129)
node _io_vcalloc_req_bits_T_137 = or(_io_vcalloc_req_bits_T_136, _io_vcalloc_req_bits_T_130)
node _io_vcalloc_req_bits_T_138 = or(_io_vcalloc_req_bits_T_137, _io_vcalloc_req_bits_T_131)
node _io_vcalloc_req_bits_T_139 = or(_io_vcalloc_req_bits_T_138, _io_vcalloc_req_bits_T_132)
node _io_vcalloc_req_bits_T_140 = or(_io_vcalloc_req_bits_T_139, _io_vcalloc_req_bits_T_133)
node _io_vcalloc_req_bits_T_141 = or(_io_vcalloc_req_bits_T_140, _io_vcalloc_req_bits_T_134)
node _io_vcalloc_req_bits_T_142 = or(_io_vcalloc_req_bits_T_141, _io_vcalloc_req_bits_T_135)
wire _io_vcalloc_req_bits_WIRE_12 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_142
connect _io_vcalloc_req_bits_WIRE_11[0], _io_vcalloc_req_bits_WIRE_12
node _io_vcalloc_req_bits_T_143 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_144 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_145 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_146 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_147 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_148 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_149 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_150 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_151 = or(_io_vcalloc_req_bits_T_143, _io_vcalloc_req_bits_T_144)
node _io_vcalloc_req_bits_T_152 = or(_io_vcalloc_req_bits_T_151, _io_vcalloc_req_bits_T_145)
node _io_vcalloc_req_bits_T_153 = or(_io_vcalloc_req_bits_T_152, _io_vcalloc_req_bits_T_146)
node _io_vcalloc_req_bits_T_154 = or(_io_vcalloc_req_bits_T_153, _io_vcalloc_req_bits_T_147)
node _io_vcalloc_req_bits_T_155 = or(_io_vcalloc_req_bits_T_154, _io_vcalloc_req_bits_T_148)
node _io_vcalloc_req_bits_T_156 = or(_io_vcalloc_req_bits_T_155, _io_vcalloc_req_bits_T_149)
node _io_vcalloc_req_bits_T_157 = or(_io_vcalloc_req_bits_T_156, _io_vcalloc_req_bits_T_150)
wire _io_vcalloc_req_bits_WIRE_13 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_13, _io_vcalloc_req_bits_T_157
connect _io_vcalloc_req_bits_WIRE_11[1], _io_vcalloc_req_bits_WIRE_13
node _io_vcalloc_req_bits_T_158 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_159 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_160 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_161 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_162 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_163 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_164 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_165 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_166 = or(_io_vcalloc_req_bits_T_158, _io_vcalloc_req_bits_T_159)
node _io_vcalloc_req_bits_T_167 = or(_io_vcalloc_req_bits_T_166, _io_vcalloc_req_bits_T_160)
node _io_vcalloc_req_bits_T_168 = or(_io_vcalloc_req_bits_T_167, _io_vcalloc_req_bits_T_161)
node _io_vcalloc_req_bits_T_169 = or(_io_vcalloc_req_bits_T_168, _io_vcalloc_req_bits_T_162)
node _io_vcalloc_req_bits_T_170 = or(_io_vcalloc_req_bits_T_169, _io_vcalloc_req_bits_T_163)
node _io_vcalloc_req_bits_T_171 = or(_io_vcalloc_req_bits_T_170, _io_vcalloc_req_bits_T_164)
node _io_vcalloc_req_bits_T_172 = or(_io_vcalloc_req_bits_T_171, _io_vcalloc_req_bits_T_165)
wire _io_vcalloc_req_bits_WIRE_14 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_14, _io_vcalloc_req_bits_T_172
connect _io_vcalloc_req_bits_WIRE_11[2], _io_vcalloc_req_bits_WIRE_14
node _io_vcalloc_req_bits_T_173 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_174 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_175 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_176 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_177 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_178 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_179 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_180 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_181 = or(_io_vcalloc_req_bits_T_173, _io_vcalloc_req_bits_T_174)
node _io_vcalloc_req_bits_T_182 = or(_io_vcalloc_req_bits_T_181, _io_vcalloc_req_bits_T_175)
node _io_vcalloc_req_bits_T_183 = or(_io_vcalloc_req_bits_T_182, _io_vcalloc_req_bits_T_176)
node _io_vcalloc_req_bits_T_184 = or(_io_vcalloc_req_bits_T_183, _io_vcalloc_req_bits_T_177)
node _io_vcalloc_req_bits_T_185 = or(_io_vcalloc_req_bits_T_184, _io_vcalloc_req_bits_T_178)
node _io_vcalloc_req_bits_T_186 = or(_io_vcalloc_req_bits_T_185, _io_vcalloc_req_bits_T_179)
node _io_vcalloc_req_bits_T_187 = or(_io_vcalloc_req_bits_T_186, _io_vcalloc_req_bits_T_180)
wire _io_vcalloc_req_bits_WIRE_15 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_15, _io_vcalloc_req_bits_T_187
connect _io_vcalloc_req_bits_WIRE_11[3], _io_vcalloc_req_bits_WIRE_15
node _io_vcalloc_req_bits_T_188 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_189 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_190 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_191 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_192 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_193 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_194 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_195 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_196 = or(_io_vcalloc_req_bits_T_188, _io_vcalloc_req_bits_T_189)
node _io_vcalloc_req_bits_T_197 = or(_io_vcalloc_req_bits_T_196, _io_vcalloc_req_bits_T_190)
node _io_vcalloc_req_bits_T_198 = or(_io_vcalloc_req_bits_T_197, _io_vcalloc_req_bits_T_191)
node _io_vcalloc_req_bits_T_199 = or(_io_vcalloc_req_bits_T_198, _io_vcalloc_req_bits_T_192)
node _io_vcalloc_req_bits_T_200 = or(_io_vcalloc_req_bits_T_199, _io_vcalloc_req_bits_T_193)
node _io_vcalloc_req_bits_T_201 = or(_io_vcalloc_req_bits_T_200, _io_vcalloc_req_bits_T_194)
node _io_vcalloc_req_bits_T_202 = or(_io_vcalloc_req_bits_T_201, _io_vcalloc_req_bits_T_195)
wire _io_vcalloc_req_bits_WIRE_16 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_16, _io_vcalloc_req_bits_T_202
connect _io_vcalloc_req_bits_WIRE_11[4], _io_vcalloc_req_bits_WIRE_16
node _io_vcalloc_req_bits_T_203 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_204 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_205 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_206 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_207 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_208 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_209 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_210 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_211 = or(_io_vcalloc_req_bits_T_203, _io_vcalloc_req_bits_T_204)
node _io_vcalloc_req_bits_T_212 = or(_io_vcalloc_req_bits_T_211, _io_vcalloc_req_bits_T_205)
node _io_vcalloc_req_bits_T_213 = or(_io_vcalloc_req_bits_T_212, _io_vcalloc_req_bits_T_206)
node _io_vcalloc_req_bits_T_214 = or(_io_vcalloc_req_bits_T_213, _io_vcalloc_req_bits_T_207)
node _io_vcalloc_req_bits_T_215 = or(_io_vcalloc_req_bits_T_214, _io_vcalloc_req_bits_T_208)
node _io_vcalloc_req_bits_T_216 = or(_io_vcalloc_req_bits_T_215, _io_vcalloc_req_bits_T_209)
node _io_vcalloc_req_bits_T_217 = or(_io_vcalloc_req_bits_T_216, _io_vcalloc_req_bits_T_210)
wire _io_vcalloc_req_bits_WIRE_17 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_17, _io_vcalloc_req_bits_T_217
connect _io_vcalloc_req_bits_WIRE_11[5], _io_vcalloc_req_bits_WIRE_17
node _io_vcalloc_req_bits_T_218 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_219 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_220 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_221 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_222 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_223 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_224 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_225 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_226 = or(_io_vcalloc_req_bits_T_218, _io_vcalloc_req_bits_T_219)
node _io_vcalloc_req_bits_T_227 = or(_io_vcalloc_req_bits_T_226, _io_vcalloc_req_bits_T_220)
node _io_vcalloc_req_bits_T_228 = or(_io_vcalloc_req_bits_T_227, _io_vcalloc_req_bits_T_221)
node _io_vcalloc_req_bits_T_229 = or(_io_vcalloc_req_bits_T_228, _io_vcalloc_req_bits_T_222)
node _io_vcalloc_req_bits_T_230 = or(_io_vcalloc_req_bits_T_229, _io_vcalloc_req_bits_T_223)
node _io_vcalloc_req_bits_T_231 = or(_io_vcalloc_req_bits_T_230, _io_vcalloc_req_bits_T_224)
node _io_vcalloc_req_bits_T_232 = or(_io_vcalloc_req_bits_T_231, _io_vcalloc_req_bits_T_225)
wire _io_vcalloc_req_bits_WIRE_18 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_18, _io_vcalloc_req_bits_T_232
connect _io_vcalloc_req_bits_WIRE_11[6], _io_vcalloc_req_bits_WIRE_18
node _io_vcalloc_req_bits_T_233 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_234 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_235 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_236 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_237 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_238 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_239 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_240 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_241 = or(_io_vcalloc_req_bits_T_233, _io_vcalloc_req_bits_T_234)
node _io_vcalloc_req_bits_T_242 = or(_io_vcalloc_req_bits_T_241, _io_vcalloc_req_bits_T_235)
node _io_vcalloc_req_bits_T_243 = or(_io_vcalloc_req_bits_T_242, _io_vcalloc_req_bits_T_236)
node _io_vcalloc_req_bits_T_244 = or(_io_vcalloc_req_bits_T_243, _io_vcalloc_req_bits_T_237)
node _io_vcalloc_req_bits_T_245 = or(_io_vcalloc_req_bits_T_244, _io_vcalloc_req_bits_T_238)
node _io_vcalloc_req_bits_T_246 = or(_io_vcalloc_req_bits_T_245, _io_vcalloc_req_bits_T_239)
node _io_vcalloc_req_bits_T_247 = or(_io_vcalloc_req_bits_T_246, _io_vcalloc_req_bits_T_240)
wire _io_vcalloc_req_bits_WIRE_19 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_19, _io_vcalloc_req_bits_T_247
connect _io_vcalloc_req_bits_WIRE_11[7], _io_vcalloc_req_bits_WIRE_19
connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_11
wire _io_vcalloc_req_bits_WIRE_20 : UInt<1>[8]
node _io_vcalloc_req_bits_T_248 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_249 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_250 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_251 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_252 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_253 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_254 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_255 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_256 = or(_io_vcalloc_req_bits_T_248, _io_vcalloc_req_bits_T_249)
node _io_vcalloc_req_bits_T_257 = or(_io_vcalloc_req_bits_T_256, _io_vcalloc_req_bits_T_250)
node _io_vcalloc_req_bits_T_258 = or(_io_vcalloc_req_bits_T_257, _io_vcalloc_req_bits_T_251)
node _io_vcalloc_req_bits_T_259 = or(_io_vcalloc_req_bits_T_258, _io_vcalloc_req_bits_T_252)
node _io_vcalloc_req_bits_T_260 = or(_io_vcalloc_req_bits_T_259, _io_vcalloc_req_bits_T_253)
node _io_vcalloc_req_bits_T_261 = or(_io_vcalloc_req_bits_T_260, _io_vcalloc_req_bits_T_254)
node _io_vcalloc_req_bits_T_262 = or(_io_vcalloc_req_bits_T_261, _io_vcalloc_req_bits_T_255)
wire _io_vcalloc_req_bits_WIRE_21 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_21, _io_vcalloc_req_bits_T_262
connect _io_vcalloc_req_bits_WIRE_20[0], _io_vcalloc_req_bits_WIRE_21
node _io_vcalloc_req_bits_T_263 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_264 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_265 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_266 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_267 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_268 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_269 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_270 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_271 = or(_io_vcalloc_req_bits_T_263, _io_vcalloc_req_bits_T_264)
node _io_vcalloc_req_bits_T_272 = or(_io_vcalloc_req_bits_T_271, _io_vcalloc_req_bits_T_265)
node _io_vcalloc_req_bits_T_273 = or(_io_vcalloc_req_bits_T_272, _io_vcalloc_req_bits_T_266)
node _io_vcalloc_req_bits_T_274 = or(_io_vcalloc_req_bits_T_273, _io_vcalloc_req_bits_T_267)
node _io_vcalloc_req_bits_T_275 = or(_io_vcalloc_req_bits_T_274, _io_vcalloc_req_bits_T_268)
node _io_vcalloc_req_bits_T_276 = or(_io_vcalloc_req_bits_T_275, _io_vcalloc_req_bits_T_269)
node _io_vcalloc_req_bits_T_277 = or(_io_vcalloc_req_bits_T_276, _io_vcalloc_req_bits_T_270)
wire _io_vcalloc_req_bits_WIRE_22 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_22, _io_vcalloc_req_bits_T_277
connect _io_vcalloc_req_bits_WIRE_20[1], _io_vcalloc_req_bits_WIRE_22
node _io_vcalloc_req_bits_T_278 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_279 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_280 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_281 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_282 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_283 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_284 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_285 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_286 = or(_io_vcalloc_req_bits_T_278, _io_vcalloc_req_bits_T_279)
node _io_vcalloc_req_bits_T_287 = or(_io_vcalloc_req_bits_T_286, _io_vcalloc_req_bits_T_280)
node _io_vcalloc_req_bits_T_288 = or(_io_vcalloc_req_bits_T_287, _io_vcalloc_req_bits_T_281)
node _io_vcalloc_req_bits_T_289 = or(_io_vcalloc_req_bits_T_288, _io_vcalloc_req_bits_T_282)
node _io_vcalloc_req_bits_T_290 = or(_io_vcalloc_req_bits_T_289, _io_vcalloc_req_bits_T_283)
node _io_vcalloc_req_bits_T_291 = or(_io_vcalloc_req_bits_T_290, _io_vcalloc_req_bits_T_284)
node _io_vcalloc_req_bits_T_292 = or(_io_vcalloc_req_bits_T_291, _io_vcalloc_req_bits_T_285)
wire _io_vcalloc_req_bits_WIRE_23 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_23, _io_vcalloc_req_bits_T_292
connect _io_vcalloc_req_bits_WIRE_20[2], _io_vcalloc_req_bits_WIRE_23
node _io_vcalloc_req_bits_T_293 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_294 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_295 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_296 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_297 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_298 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_299 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_300 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_301 = or(_io_vcalloc_req_bits_T_293, _io_vcalloc_req_bits_T_294)
node _io_vcalloc_req_bits_T_302 = or(_io_vcalloc_req_bits_T_301, _io_vcalloc_req_bits_T_295)
node _io_vcalloc_req_bits_T_303 = or(_io_vcalloc_req_bits_T_302, _io_vcalloc_req_bits_T_296)
node _io_vcalloc_req_bits_T_304 = or(_io_vcalloc_req_bits_T_303, _io_vcalloc_req_bits_T_297)
node _io_vcalloc_req_bits_T_305 = or(_io_vcalloc_req_bits_T_304, _io_vcalloc_req_bits_T_298)
node _io_vcalloc_req_bits_T_306 = or(_io_vcalloc_req_bits_T_305, _io_vcalloc_req_bits_T_299)
node _io_vcalloc_req_bits_T_307 = or(_io_vcalloc_req_bits_T_306, _io_vcalloc_req_bits_T_300)
wire _io_vcalloc_req_bits_WIRE_24 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_24, _io_vcalloc_req_bits_T_307
connect _io_vcalloc_req_bits_WIRE_20[3], _io_vcalloc_req_bits_WIRE_24
node _io_vcalloc_req_bits_T_308 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_309 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_310 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_311 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_312 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_313 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_314 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_315 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_316 = or(_io_vcalloc_req_bits_T_308, _io_vcalloc_req_bits_T_309)
node _io_vcalloc_req_bits_T_317 = or(_io_vcalloc_req_bits_T_316, _io_vcalloc_req_bits_T_310)
node _io_vcalloc_req_bits_T_318 = or(_io_vcalloc_req_bits_T_317, _io_vcalloc_req_bits_T_311)
node _io_vcalloc_req_bits_T_319 = or(_io_vcalloc_req_bits_T_318, _io_vcalloc_req_bits_T_312)
node _io_vcalloc_req_bits_T_320 = or(_io_vcalloc_req_bits_T_319, _io_vcalloc_req_bits_T_313)
node _io_vcalloc_req_bits_T_321 = or(_io_vcalloc_req_bits_T_320, _io_vcalloc_req_bits_T_314)
node _io_vcalloc_req_bits_T_322 = or(_io_vcalloc_req_bits_T_321, _io_vcalloc_req_bits_T_315)
wire _io_vcalloc_req_bits_WIRE_25 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_25, _io_vcalloc_req_bits_T_322
connect _io_vcalloc_req_bits_WIRE_20[4], _io_vcalloc_req_bits_WIRE_25
node _io_vcalloc_req_bits_T_323 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_324 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_325 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_326 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_327 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_328 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_329 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_330 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_331 = or(_io_vcalloc_req_bits_T_323, _io_vcalloc_req_bits_T_324)
node _io_vcalloc_req_bits_T_332 = or(_io_vcalloc_req_bits_T_331, _io_vcalloc_req_bits_T_325)
node _io_vcalloc_req_bits_T_333 = or(_io_vcalloc_req_bits_T_332, _io_vcalloc_req_bits_T_326)
node _io_vcalloc_req_bits_T_334 = or(_io_vcalloc_req_bits_T_333, _io_vcalloc_req_bits_T_327)
node _io_vcalloc_req_bits_T_335 = or(_io_vcalloc_req_bits_T_334, _io_vcalloc_req_bits_T_328)
node _io_vcalloc_req_bits_T_336 = or(_io_vcalloc_req_bits_T_335, _io_vcalloc_req_bits_T_329)
node _io_vcalloc_req_bits_T_337 = or(_io_vcalloc_req_bits_T_336, _io_vcalloc_req_bits_T_330)
wire _io_vcalloc_req_bits_WIRE_26 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_26, _io_vcalloc_req_bits_T_337
connect _io_vcalloc_req_bits_WIRE_20[5], _io_vcalloc_req_bits_WIRE_26
node _io_vcalloc_req_bits_T_338 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_339 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_340 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_341 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_342 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_343 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_344 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_345 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_346 = or(_io_vcalloc_req_bits_T_338, _io_vcalloc_req_bits_T_339)
node _io_vcalloc_req_bits_T_347 = or(_io_vcalloc_req_bits_T_346, _io_vcalloc_req_bits_T_340)
node _io_vcalloc_req_bits_T_348 = or(_io_vcalloc_req_bits_T_347, _io_vcalloc_req_bits_T_341)
node _io_vcalloc_req_bits_T_349 = or(_io_vcalloc_req_bits_T_348, _io_vcalloc_req_bits_T_342)
node _io_vcalloc_req_bits_T_350 = or(_io_vcalloc_req_bits_T_349, _io_vcalloc_req_bits_T_343)
node _io_vcalloc_req_bits_T_351 = or(_io_vcalloc_req_bits_T_350, _io_vcalloc_req_bits_T_344)
node _io_vcalloc_req_bits_T_352 = or(_io_vcalloc_req_bits_T_351, _io_vcalloc_req_bits_T_345)
wire _io_vcalloc_req_bits_WIRE_27 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_27, _io_vcalloc_req_bits_T_352
connect _io_vcalloc_req_bits_WIRE_20[6], _io_vcalloc_req_bits_WIRE_27
node _io_vcalloc_req_bits_T_353 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_354 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_355 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_356 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_357 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_358 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_359 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_360 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_361 = or(_io_vcalloc_req_bits_T_353, _io_vcalloc_req_bits_T_354)
node _io_vcalloc_req_bits_T_362 = or(_io_vcalloc_req_bits_T_361, _io_vcalloc_req_bits_T_355)
node _io_vcalloc_req_bits_T_363 = or(_io_vcalloc_req_bits_T_362, _io_vcalloc_req_bits_T_356)
node _io_vcalloc_req_bits_T_364 = or(_io_vcalloc_req_bits_T_363, _io_vcalloc_req_bits_T_357)
node _io_vcalloc_req_bits_T_365 = or(_io_vcalloc_req_bits_T_364, _io_vcalloc_req_bits_T_358)
node _io_vcalloc_req_bits_T_366 = or(_io_vcalloc_req_bits_T_365, _io_vcalloc_req_bits_T_359)
node _io_vcalloc_req_bits_T_367 = or(_io_vcalloc_req_bits_T_366, _io_vcalloc_req_bits_T_360)
wire _io_vcalloc_req_bits_WIRE_28 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_28, _io_vcalloc_req_bits_T_367
connect _io_vcalloc_req_bits_WIRE_20[7], _io_vcalloc_req_bits_WIRE_28
connect _io_vcalloc_req_bits_WIRE_1.`2`, _io_vcalloc_req_bits_WIRE_20
connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1
node _io_vcalloc_req_bits_T_368 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_369 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_370 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_371 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_372 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_373 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_374 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_375 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_376 = or(_io_vcalloc_req_bits_T_368, _io_vcalloc_req_bits_T_369)
node _io_vcalloc_req_bits_T_377 = or(_io_vcalloc_req_bits_T_376, _io_vcalloc_req_bits_T_370)
node _io_vcalloc_req_bits_T_378 = or(_io_vcalloc_req_bits_T_377, _io_vcalloc_req_bits_T_371)
node _io_vcalloc_req_bits_T_379 = or(_io_vcalloc_req_bits_T_378, _io_vcalloc_req_bits_T_372)
node _io_vcalloc_req_bits_T_380 = or(_io_vcalloc_req_bits_T_379, _io_vcalloc_req_bits_T_373)
node _io_vcalloc_req_bits_T_381 = or(_io_vcalloc_req_bits_T_380, _io_vcalloc_req_bits_T_374)
node _io_vcalloc_req_bits_T_382 = or(_io_vcalloc_req_bits_T_381, _io_vcalloc_req_bits_T_375)
wire _io_vcalloc_req_bits_WIRE_29 : UInt<3>
connect _io_vcalloc_req_bits_WIRE_29, _io_vcalloc_req_bits_T_382
connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_29
wire _io_vcalloc_req_bits_WIRE_30 : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}
node _io_vcalloc_req_bits_T_383 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_384 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_385 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_386 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_387 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_388 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_389 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_390 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_391 = or(_io_vcalloc_req_bits_T_383, _io_vcalloc_req_bits_T_384)
node _io_vcalloc_req_bits_T_392 = or(_io_vcalloc_req_bits_T_391, _io_vcalloc_req_bits_T_385)
node _io_vcalloc_req_bits_T_393 = or(_io_vcalloc_req_bits_T_392, _io_vcalloc_req_bits_T_386)
node _io_vcalloc_req_bits_T_394 = or(_io_vcalloc_req_bits_T_393, _io_vcalloc_req_bits_T_387)
node _io_vcalloc_req_bits_T_395 = or(_io_vcalloc_req_bits_T_394, _io_vcalloc_req_bits_T_388)
node _io_vcalloc_req_bits_T_396 = or(_io_vcalloc_req_bits_T_395, _io_vcalloc_req_bits_T_389)
node _io_vcalloc_req_bits_T_397 = or(_io_vcalloc_req_bits_T_396, _io_vcalloc_req_bits_T_390)
wire _io_vcalloc_req_bits_WIRE_31 : UInt<2>
connect _io_vcalloc_req_bits_WIRE_31, _io_vcalloc_req_bits_T_397
connect _io_vcalloc_req_bits_WIRE_30.egress_node_id, _io_vcalloc_req_bits_WIRE_31
node _io_vcalloc_req_bits_T_398 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_399 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_400 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_401 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_402 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_403 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_404 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_405 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_406 = or(_io_vcalloc_req_bits_T_398, _io_vcalloc_req_bits_T_399)
node _io_vcalloc_req_bits_T_407 = or(_io_vcalloc_req_bits_T_406, _io_vcalloc_req_bits_T_400)
node _io_vcalloc_req_bits_T_408 = or(_io_vcalloc_req_bits_T_407, _io_vcalloc_req_bits_T_401)
node _io_vcalloc_req_bits_T_409 = or(_io_vcalloc_req_bits_T_408, _io_vcalloc_req_bits_T_402)
node _io_vcalloc_req_bits_T_410 = or(_io_vcalloc_req_bits_T_409, _io_vcalloc_req_bits_T_403)
node _io_vcalloc_req_bits_T_411 = or(_io_vcalloc_req_bits_T_410, _io_vcalloc_req_bits_T_404)
node _io_vcalloc_req_bits_T_412 = or(_io_vcalloc_req_bits_T_411, _io_vcalloc_req_bits_T_405)
wire _io_vcalloc_req_bits_WIRE_32 : UInt<5>
connect _io_vcalloc_req_bits_WIRE_32, _io_vcalloc_req_bits_T_412
connect _io_vcalloc_req_bits_WIRE_30.egress_node, _io_vcalloc_req_bits_WIRE_32
node _io_vcalloc_req_bits_T_413 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_414 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_415 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_416 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_417 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_418 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_419 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_420 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_421 = or(_io_vcalloc_req_bits_T_413, _io_vcalloc_req_bits_T_414)
node _io_vcalloc_req_bits_T_422 = or(_io_vcalloc_req_bits_T_421, _io_vcalloc_req_bits_T_415)
node _io_vcalloc_req_bits_T_423 = or(_io_vcalloc_req_bits_T_422, _io_vcalloc_req_bits_T_416)
node _io_vcalloc_req_bits_T_424 = or(_io_vcalloc_req_bits_T_423, _io_vcalloc_req_bits_T_417)
node _io_vcalloc_req_bits_T_425 = or(_io_vcalloc_req_bits_T_424, _io_vcalloc_req_bits_T_418)
node _io_vcalloc_req_bits_T_426 = or(_io_vcalloc_req_bits_T_425, _io_vcalloc_req_bits_T_419)
node _io_vcalloc_req_bits_T_427 = or(_io_vcalloc_req_bits_T_426, _io_vcalloc_req_bits_T_420)
wire _io_vcalloc_req_bits_WIRE_33 : UInt<2>
connect _io_vcalloc_req_bits_WIRE_33, _io_vcalloc_req_bits_T_427
connect _io_vcalloc_req_bits_WIRE_30.ingress_node_id, _io_vcalloc_req_bits_WIRE_33
node _io_vcalloc_req_bits_T_428 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_429 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_430 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_431 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_432 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_433 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_434 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_435 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_436 = or(_io_vcalloc_req_bits_T_428, _io_vcalloc_req_bits_T_429)
node _io_vcalloc_req_bits_T_437 = or(_io_vcalloc_req_bits_T_436, _io_vcalloc_req_bits_T_430)
node _io_vcalloc_req_bits_T_438 = or(_io_vcalloc_req_bits_T_437, _io_vcalloc_req_bits_T_431)
node _io_vcalloc_req_bits_T_439 = or(_io_vcalloc_req_bits_T_438, _io_vcalloc_req_bits_T_432)
node _io_vcalloc_req_bits_T_440 = or(_io_vcalloc_req_bits_T_439, _io_vcalloc_req_bits_T_433)
node _io_vcalloc_req_bits_T_441 = or(_io_vcalloc_req_bits_T_440, _io_vcalloc_req_bits_T_434)
node _io_vcalloc_req_bits_T_442 = or(_io_vcalloc_req_bits_T_441, _io_vcalloc_req_bits_T_435)
wire _io_vcalloc_req_bits_WIRE_34 : UInt<5>
connect _io_vcalloc_req_bits_WIRE_34, _io_vcalloc_req_bits_T_442
connect _io_vcalloc_req_bits_WIRE_30.ingress_node, _io_vcalloc_req_bits_WIRE_34
node _io_vcalloc_req_bits_T_443 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_444 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_445 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_446 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_447 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_448 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_449 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_450 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_451 = or(_io_vcalloc_req_bits_T_443, _io_vcalloc_req_bits_T_444)
node _io_vcalloc_req_bits_T_452 = or(_io_vcalloc_req_bits_T_451, _io_vcalloc_req_bits_T_445)
node _io_vcalloc_req_bits_T_453 = or(_io_vcalloc_req_bits_T_452, _io_vcalloc_req_bits_T_446)
node _io_vcalloc_req_bits_T_454 = or(_io_vcalloc_req_bits_T_453, _io_vcalloc_req_bits_T_447)
node _io_vcalloc_req_bits_T_455 = or(_io_vcalloc_req_bits_T_454, _io_vcalloc_req_bits_T_448)
node _io_vcalloc_req_bits_T_456 = or(_io_vcalloc_req_bits_T_455, _io_vcalloc_req_bits_T_449)
node _io_vcalloc_req_bits_T_457 = or(_io_vcalloc_req_bits_T_456, _io_vcalloc_req_bits_T_450)
wire _io_vcalloc_req_bits_WIRE_35 : UInt<3>
connect _io_vcalloc_req_bits_WIRE_35, _io_vcalloc_req_bits_T_457
connect _io_vcalloc_req_bits_WIRE_30.vnet_id, _io_vcalloc_req_bits_WIRE_35
connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_30
connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE
connect vcalloc_vals[0], UInt<1>(0h0)
invalidate vcalloc_reqs[0].vc_sel.`0`[0]
invalidate vcalloc_reqs[0].vc_sel.`0`[1]
invalidate vcalloc_reqs[0].vc_sel.`0`[2]
invalidate vcalloc_reqs[0].vc_sel.`0`[3]
invalidate vcalloc_reqs[0].vc_sel.`0`[4]
invalidate vcalloc_reqs[0].vc_sel.`0`[5]
invalidate vcalloc_reqs[0].vc_sel.`0`[6]
invalidate vcalloc_reqs[0].vc_sel.`0`[7]
invalidate vcalloc_reqs[0].vc_sel.`1`[0]
invalidate vcalloc_reqs[0].vc_sel.`1`[1]
invalidate vcalloc_reqs[0].vc_sel.`1`[2]
invalidate vcalloc_reqs[0].vc_sel.`1`[3]
invalidate vcalloc_reqs[0].vc_sel.`1`[4]
invalidate vcalloc_reqs[0].vc_sel.`1`[5]
invalidate vcalloc_reqs[0].vc_sel.`1`[6]
invalidate vcalloc_reqs[0].vc_sel.`1`[7]
invalidate vcalloc_reqs[0].vc_sel.`2`[0]
invalidate vcalloc_reqs[0].vc_sel.`2`[1]
invalidate vcalloc_reqs[0].vc_sel.`2`[2]
invalidate vcalloc_reqs[0].vc_sel.`2`[3]
invalidate vcalloc_reqs[0].vc_sel.`2`[4]
invalidate vcalloc_reqs[0].vc_sel.`2`[5]
invalidate vcalloc_reqs[0].vc_sel.`2`[6]
invalidate vcalloc_reqs[0].vc_sel.`2`[7]
invalidate vcalloc_reqs[0].in_vc
invalidate vcalloc_reqs[0].flow.egress_node_id
invalidate vcalloc_reqs[0].flow.egress_node
invalidate vcalloc_reqs[0].flow.ingress_node_id
invalidate vcalloc_reqs[0].flow.ingress_node
invalidate vcalloc_reqs[0].flow.vnet_id
connect vcalloc_vals[1], UInt<1>(0h0)
invalidate vcalloc_reqs[1].vc_sel.`0`[0]
invalidate vcalloc_reqs[1].vc_sel.`0`[1]
invalidate vcalloc_reqs[1].vc_sel.`0`[2]
invalidate vcalloc_reqs[1].vc_sel.`0`[3]
invalidate vcalloc_reqs[1].vc_sel.`0`[4]
invalidate vcalloc_reqs[1].vc_sel.`0`[5]
invalidate vcalloc_reqs[1].vc_sel.`0`[6]
invalidate vcalloc_reqs[1].vc_sel.`0`[7]
invalidate vcalloc_reqs[1].vc_sel.`1`[0]
invalidate vcalloc_reqs[1].vc_sel.`1`[1]
invalidate vcalloc_reqs[1].vc_sel.`1`[2]
invalidate vcalloc_reqs[1].vc_sel.`1`[3]
invalidate vcalloc_reqs[1].vc_sel.`1`[4]
invalidate vcalloc_reqs[1].vc_sel.`1`[5]
invalidate vcalloc_reqs[1].vc_sel.`1`[6]
invalidate vcalloc_reqs[1].vc_sel.`1`[7]
invalidate vcalloc_reqs[1].vc_sel.`2`[0]
invalidate vcalloc_reqs[1].vc_sel.`2`[1]
invalidate vcalloc_reqs[1].vc_sel.`2`[2]
invalidate vcalloc_reqs[1].vc_sel.`2`[3]
invalidate vcalloc_reqs[1].vc_sel.`2`[4]
invalidate vcalloc_reqs[1].vc_sel.`2`[5]
invalidate vcalloc_reqs[1].vc_sel.`2`[6]
invalidate vcalloc_reqs[1].vc_sel.`2`[7]
invalidate vcalloc_reqs[1].in_vc
invalidate vcalloc_reqs[1].flow.egress_node_id
invalidate vcalloc_reqs[1].flow.egress_node
invalidate vcalloc_reqs[1].flow.ingress_node_id
invalidate vcalloc_reqs[1].flow.ingress_node
invalidate vcalloc_reqs[1].flow.vnet_id
connect vcalloc_vals[2], UInt<1>(0h0)
invalidate vcalloc_reqs[2].vc_sel.`0`[0]
invalidate vcalloc_reqs[2].vc_sel.`0`[1]
invalidate vcalloc_reqs[2].vc_sel.`0`[2]
invalidate vcalloc_reqs[2].vc_sel.`0`[3]
invalidate vcalloc_reqs[2].vc_sel.`0`[4]
invalidate vcalloc_reqs[2].vc_sel.`0`[5]
invalidate vcalloc_reqs[2].vc_sel.`0`[6]
invalidate vcalloc_reqs[2].vc_sel.`0`[7]
invalidate vcalloc_reqs[2].vc_sel.`1`[0]
invalidate vcalloc_reqs[2].vc_sel.`1`[1]
invalidate vcalloc_reqs[2].vc_sel.`1`[2]
invalidate vcalloc_reqs[2].vc_sel.`1`[3]
invalidate vcalloc_reqs[2].vc_sel.`1`[4]
invalidate vcalloc_reqs[2].vc_sel.`1`[5]
invalidate vcalloc_reqs[2].vc_sel.`1`[6]
invalidate vcalloc_reqs[2].vc_sel.`1`[7]
invalidate vcalloc_reqs[2].vc_sel.`2`[0]
invalidate vcalloc_reqs[2].vc_sel.`2`[1]
invalidate vcalloc_reqs[2].vc_sel.`2`[2]
invalidate vcalloc_reqs[2].vc_sel.`2`[3]
invalidate vcalloc_reqs[2].vc_sel.`2`[4]
invalidate vcalloc_reqs[2].vc_sel.`2`[5]
invalidate vcalloc_reqs[2].vc_sel.`2`[6]
invalidate vcalloc_reqs[2].vc_sel.`2`[7]
invalidate vcalloc_reqs[2].in_vc
invalidate vcalloc_reqs[2].flow.egress_node_id
invalidate vcalloc_reqs[2].flow.egress_node
invalidate vcalloc_reqs[2].flow.ingress_node_id
invalidate vcalloc_reqs[2].flow.ingress_node
invalidate vcalloc_reqs[2].flow.vnet_id
connect vcalloc_vals[3], UInt<1>(0h0)
invalidate vcalloc_reqs[3].vc_sel.`0`[0]
invalidate vcalloc_reqs[3].vc_sel.`0`[1]
invalidate vcalloc_reqs[3].vc_sel.`0`[2]
invalidate vcalloc_reqs[3].vc_sel.`0`[3]
invalidate vcalloc_reqs[3].vc_sel.`0`[4]
invalidate vcalloc_reqs[3].vc_sel.`0`[5]
invalidate vcalloc_reqs[3].vc_sel.`0`[6]
invalidate vcalloc_reqs[3].vc_sel.`0`[7]
invalidate vcalloc_reqs[3].vc_sel.`1`[0]
invalidate vcalloc_reqs[3].vc_sel.`1`[1]
invalidate vcalloc_reqs[3].vc_sel.`1`[2]
invalidate vcalloc_reqs[3].vc_sel.`1`[3]
invalidate vcalloc_reqs[3].vc_sel.`1`[4]
invalidate vcalloc_reqs[3].vc_sel.`1`[5]
invalidate vcalloc_reqs[3].vc_sel.`1`[6]
invalidate vcalloc_reqs[3].vc_sel.`1`[7]
invalidate vcalloc_reqs[3].vc_sel.`2`[0]
invalidate vcalloc_reqs[3].vc_sel.`2`[1]
invalidate vcalloc_reqs[3].vc_sel.`2`[2]
invalidate vcalloc_reqs[3].vc_sel.`2`[3]
invalidate vcalloc_reqs[3].vc_sel.`2`[4]
invalidate vcalloc_reqs[3].vc_sel.`2`[5]
invalidate vcalloc_reqs[3].vc_sel.`2`[6]
invalidate vcalloc_reqs[3].vc_sel.`2`[7]
invalidate vcalloc_reqs[3].in_vc
invalidate vcalloc_reqs[3].flow.egress_node_id
invalidate vcalloc_reqs[3].flow.egress_node
invalidate vcalloc_reqs[3].flow.ingress_node_id
invalidate vcalloc_reqs[3].flow.ingress_node
invalidate vcalloc_reqs[3].flow.vnet_id
node _vcalloc_vals_4_T = eq(states[4].g, UInt<3>(0h2))
node _vcalloc_vals_4_T_1 = eq(states[4].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_4_T_2 = and(_vcalloc_vals_4_T, _vcalloc_vals_4_T_1)
connect vcalloc_vals[4], _vcalloc_vals_4_T_2
connect vcalloc_reqs[4].in_vc, UInt<3>(0h4)
connect vcalloc_reqs[4].vc_sel.`0`, states[4].vc_sel.`0`
connect vcalloc_reqs[4].vc_sel.`1`, states[4].vc_sel.`1`
connect vcalloc_reqs[4].vc_sel.`2`, states[4].vc_sel.`2`
connect vcalloc_reqs[4].flow, states[4].flow
node _T_34 = bits(vcalloc_sel, 4, 4)
node _T_35 = and(vcalloc_vals[4], _T_34)
node _T_36 = and(_T_35, io.vcalloc_req.ready)
when _T_36 :
connect states[4].g, UInt<3>(0h3)
node _vcalloc_vals_5_T = eq(states[5].g, UInt<3>(0h2))
node _vcalloc_vals_5_T_1 = eq(states[5].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_5_T_2 = and(_vcalloc_vals_5_T, _vcalloc_vals_5_T_1)
connect vcalloc_vals[5], _vcalloc_vals_5_T_2
connect vcalloc_reqs[5].in_vc, UInt<3>(0h5)
connect vcalloc_reqs[5].vc_sel.`0`, states[5].vc_sel.`0`
connect vcalloc_reqs[5].vc_sel.`1`, states[5].vc_sel.`1`
connect vcalloc_reqs[5].vc_sel.`2`, states[5].vc_sel.`2`
connect vcalloc_reqs[5].flow, states[5].flow
node _T_37 = bits(vcalloc_sel, 5, 5)
node _T_38 = and(vcalloc_vals[5], _T_37)
node _T_39 = and(_T_38, io.vcalloc_req.ready)
when _T_39 :
connect states[5].g, UInt<3>(0h3)
node _vcalloc_vals_6_T = eq(states[6].g, UInt<3>(0h2))
node _vcalloc_vals_6_T_1 = eq(states[6].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_6_T_2 = and(_vcalloc_vals_6_T, _vcalloc_vals_6_T_1)
connect vcalloc_vals[6], _vcalloc_vals_6_T_2
connect vcalloc_reqs[6].in_vc, UInt<3>(0h6)
connect vcalloc_reqs[6].vc_sel.`0`, states[6].vc_sel.`0`
connect vcalloc_reqs[6].vc_sel.`1`, states[6].vc_sel.`1`
connect vcalloc_reqs[6].vc_sel.`2`, states[6].vc_sel.`2`
connect vcalloc_reqs[6].flow, states[6].flow
node _T_40 = bits(vcalloc_sel, 6, 6)
node _T_41 = and(vcalloc_vals[6], _T_40)
node _T_42 = and(_T_41, io.vcalloc_req.ready)
when _T_42 :
connect states[6].g, UInt<3>(0h3)
node _vcalloc_vals_7_T = eq(states[7].g, UInt<3>(0h2))
node _vcalloc_vals_7_T_1 = eq(states[7].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_7_T_2 = and(_vcalloc_vals_7_T, _vcalloc_vals_7_T_1)
connect vcalloc_vals[7], _vcalloc_vals_7_T_2
connect vcalloc_reqs[7].in_vc, UInt<3>(0h7)
connect vcalloc_reqs[7].vc_sel.`0`, states[7].vc_sel.`0`
connect vcalloc_reqs[7].vc_sel.`1`, states[7].vc_sel.`1`
connect vcalloc_reqs[7].vc_sel.`2`, states[7].vc_sel.`2`
connect vcalloc_reqs[7].flow, states[7].flow
node _T_43 = bits(vcalloc_sel, 7, 7)
node _T_44 = and(vcalloc_vals[7], _T_43)
node _T_45 = and(_T_44, io.vcalloc_req.ready)
when _T_45 :
connect states[7].g, UInt<3>(0h3)
node _io_debug_va_stall_T = add(vcalloc_vals[0], vcalloc_vals[1])
node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0)
node _io_debug_va_stall_T_2 = add(vcalloc_vals[2], vcalloc_vals[3])
node _io_debug_va_stall_T_3 = bits(_io_debug_va_stall_T_2, 1, 0)
node _io_debug_va_stall_T_4 = add(_io_debug_va_stall_T_1, _io_debug_va_stall_T_3)
node _io_debug_va_stall_T_5 = bits(_io_debug_va_stall_T_4, 2, 0)
node _io_debug_va_stall_T_6 = add(vcalloc_vals[4], vcalloc_vals[5])
node _io_debug_va_stall_T_7 = bits(_io_debug_va_stall_T_6, 1, 0)
node _io_debug_va_stall_T_8 = add(vcalloc_vals[6], vcalloc_vals[7])
node _io_debug_va_stall_T_9 = bits(_io_debug_va_stall_T_8, 1, 0)
node _io_debug_va_stall_T_10 = add(_io_debug_va_stall_T_7, _io_debug_va_stall_T_9)
node _io_debug_va_stall_T_11 = bits(_io_debug_va_stall_T_10, 2, 0)
node _io_debug_va_stall_T_12 = add(_io_debug_va_stall_T_5, _io_debug_va_stall_T_11)
node _io_debug_va_stall_T_13 = bits(_io_debug_va_stall_T_12, 3, 0)
node _io_debug_va_stall_T_14 = sub(_io_debug_va_stall_T_13, io.vcalloc_req.ready)
node _io_debug_va_stall_T_15 = tail(_io_debug_va_stall_T_14, 1)
connect io.debug.va_stall, _io_debug_va_stall_T_15
node _T_46 = and(io.vcalloc_req.ready, io.vcalloc_req.valid)
when _T_46 :
node _T_47 = bits(vcalloc_sel, 0, 0)
when _T_47 :
connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[0].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[0].g, UInt<3>(0h3)
node _T_48 = eq(states[0].g, UInt<3>(0h2))
node _T_49 = asUInt(reset)
node _T_50 = eq(_T_49, UInt<1>(0h0))
when _T_50 :
node _T_51 = eq(_T_48, UInt<1>(0h0))
when _T_51 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_3
assert(clock, _T_48, UInt<1>(0h1), "") : assert_3
node _T_52 = bits(vcalloc_sel, 1, 1)
when _T_52 :
connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[1].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[1].g, UInt<3>(0h3)
node _T_53 = eq(states[1].g, UInt<3>(0h2))
node _T_54 = asUInt(reset)
node _T_55 = eq(_T_54, UInt<1>(0h0))
when _T_55 :
node _T_56 = eq(_T_53, UInt<1>(0h0))
when _T_56 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_4
assert(clock, _T_53, UInt<1>(0h1), "") : assert_4
node _T_57 = bits(vcalloc_sel, 2, 2)
when _T_57 :
connect states[2].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[2].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[2].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[2].g, UInt<3>(0h3)
node _T_58 = eq(states[2].g, UInt<3>(0h2))
node _T_59 = asUInt(reset)
node _T_60 = eq(_T_59, UInt<1>(0h0))
when _T_60 :
node _T_61 = eq(_T_58, UInt<1>(0h0))
when _T_61 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_5
assert(clock, _T_58, UInt<1>(0h1), "") : assert_5
node _T_62 = bits(vcalloc_sel, 3, 3)
when _T_62 :
connect states[3].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[3].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[3].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[3].g, UInt<3>(0h3)
node _T_63 = eq(states[3].g, UInt<3>(0h2))
node _T_64 = asUInt(reset)
node _T_65 = eq(_T_64, UInt<1>(0h0))
when _T_65 :
node _T_66 = eq(_T_63, UInt<1>(0h0))
when _T_66 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_6
assert(clock, _T_63, UInt<1>(0h1), "") : assert_6
node _T_67 = bits(vcalloc_sel, 4, 4)
when _T_67 :
connect states[4].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[4].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[4].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[4].g, UInt<3>(0h3)
node _T_68 = eq(states[4].g, UInt<3>(0h2))
node _T_69 = asUInt(reset)
node _T_70 = eq(_T_69, UInt<1>(0h0))
when _T_70 :
node _T_71 = eq(_T_68, UInt<1>(0h0))
when _T_71 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_7
assert(clock, _T_68, UInt<1>(0h1), "") : assert_7
node _T_72 = bits(vcalloc_sel, 5, 5)
when _T_72 :
connect states[5].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[5].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[5].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[5].g, UInt<3>(0h3)
node _T_73 = eq(states[5].g, UInt<3>(0h2))
node _T_74 = asUInt(reset)
node _T_75 = eq(_T_74, UInt<1>(0h0))
when _T_75 :
node _T_76 = eq(_T_73, UInt<1>(0h0))
when _T_76 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_8
assert(clock, _T_73, UInt<1>(0h1), "") : assert_8
node _T_77 = bits(vcalloc_sel, 6, 6)
when _T_77 :
connect states[6].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[6].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[6].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[6].g, UInt<3>(0h3)
node _T_78 = eq(states[6].g, UInt<3>(0h2))
node _T_79 = asUInt(reset)
node _T_80 = eq(_T_79, UInt<1>(0h0))
when _T_80 :
node _T_81 = eq(_T_78, UInt<1>(0h0))
when _T_81 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_9
assert(clock, _T_78, UInt<1>(0h1), "") : assert_9
node _T_82 = bits(vcalloc_sel, 7, 7)
when _T_82 :
connect states[7].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[7].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[7].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[7].g, UInt<3>(0h3)
node _T_83 = eq(states[7].g, UInt<3>(0h2))
node _T_84 = asUInt(reset)
node _T_85 = eq(_T_84, UInt<1>(0h0))
when _T_85 :
node _T_86 = eq(_T_83, UInt<1>(0h0))
when _T_86 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_10
assert(clock, _T_83, UInt<1>(0h1), "") : assert_10
inst salloc_arb of SwitchArbiter_84
connect salloc_arb.clock, clock
connect salloc_arb.reset, reset
connect salloc_arb.io.in[0].valid, UInt<1>(0h0)
invalidate salloc_arb.io.in[0].bits.tail
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[0]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[1]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[2]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[3]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[4]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[5]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[6]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[7]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[0]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[1]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[2]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[3]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[4]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[5]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[6]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[7]
invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[0]
invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[1]
invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[2]
invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[3]
invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[4]
invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[5]
invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[6]
invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[7]
connect salloc_arb.io.in[1].valid, UInt<1>(0h0)
invalidate salloc_arb.io.in[1].bits.tail
invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[0]
invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[1]
invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[2]
invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[3]
invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[4]
invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[5]
invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[6]
invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[7]
invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[0]
invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[1]
invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[2]
invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[3]
invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[4]
invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[5]
invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[6]
invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[7]
invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[0]
invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[1]
invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[2]
invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[3]
invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[4]
invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[5]
invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[6]
invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[7]
connect salloc_arb.io.in[2].valid, UInt<1>(0h0)
invalidate salloc_arb.io.in[2].bits.tail
invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[0]
invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[1]
invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[2]
invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[3]
invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[4]
invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[5]
invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[6]
invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[7]
invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[0]
invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[1]
invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[2]
invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[3]
invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[4]
invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[5]
invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[6]
invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[7]
invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[0]
invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[1]
invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[2]
invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[3]
invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[4]
invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[5]
invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[6]
invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[7]
connect salloc_arb.io.in[3].valid, UInt<1>(0h0)
invalidate salloc_arb.io.in[3].bits.tail
invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[0]
invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[1]
invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[2]
invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[3]
invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[4]
invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[5]
invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[6]
invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[7]
invalidate salloc_arb.io.in[3].bits.vc_sel.`1`[0]
invalidate salloc_arb.io.in[3].bits.vc_sel.`1`[1]
invalidate salloc_arb.io.in[3].bits.vc_sel.`1`[2]
invalidate salloc_arb.io.in[3].bits.vc_sel.`1`[3]
invalidate salloc_arb.io.in[3].bits.vc_sel.`1`[4]
invalidate salloc_arb.io.in[3].bits.vc_sel.`1`[5]
invalidate salloc_arb.io.in[3].bits.vc_sel.`1`[6]
invalidate salloc_arb.io.in[3].bits.vc_sel.`1`[7]
invalidate salloc_arb.io.in[3].bits.vc_sel.`2`[0]
invalidate salloc_arb.io.in[3].bits.vc_sel.`2`[1]
invalidate salloc_arb.io.in[3].bits.vc_sel.`2`[2]
invalidate salloc_arb.io.in[3].bits.vc_sel.`2`[3]
invalidate salloc_arb.io.in[3].bits.vc_sel.`2`[4]
invalidate salloc_arb.io.in[3].bits.vc_sel.`2`[5]
invalidate salloc_arb.io.in[3].bits.vc_sel.`2`[6]
invalidate salloc_arb.io.in[3].bits.vc_sel.`2`[7]
node credit_available_lo_lo = cat(states[4].vc_sel.`0`[1], states[4].vc_sel.`0`[0])
node credit_available_lo_hi = cat(states[4].vc_sel.`0`[3], states[4].vc_sel.`0`[2])
node credit_available_lo = cat(credit_available_lo_hi, credit_available_lo_lo)
node credit_available_hi_lo = cat(states[4].vc_sel.`0`[5], states[4].vc_sel.`0`[4])
node credit_available_hi_hi = cat(states[4].vc_sel.`0`[7], states[4].vc_sel.`0`[6])
node credit_available_hi = cat(credit_available_hi_hi, credit_available_hi_lo)
node _credit_available_T = cat(credit_available_hi, credit_available_lo)
node credit_available_lo_lo_1 = cat(states[4].vc_sel.`1`[1], states[4].vc_sel.`1`[0])
node credit_available_lo_hi_1 = cat(states[4].vc_sel.`1`[3], states[4].vc_sel.`1`[2])
node credit_available_lo_1 = cat(credit_available_lo_hi_1, credit_available_lo_lo_1)
node credit_available_hi_lo_1 = cat(states[4].vc_sel.`1`[5], states[4].vc_sel.`1`[4])
node credit_available_hi_hi_1 = cat(states[4].vc_sel.`1`[7], states[4].vc_sel.`1`[6])
node credit_available_hi_1 = cat(credit_available_hi_hi_1, credit_available_hi_lo_1)
node _credit_available_T_1 = cat(credit_available_hi_1, credit_available_lo_1)
node credit_available_lo_lo_2 = cat(states[4].vc_sel.`2`[1], states[4].vc_sel.`2`[0])
node credit_available_lo_hi_2 = cat(states[4].vc_sel.`2`[3], states[4].vc_sel.`2`[2])
node credit_available_lo_2 = cat(credit_available_lo_hi_2, credit_available_lo_lo_2)
node credit_available_hi_lo_2 = cat(states[4].vc_sel.`2`[5], states[4].vc_sel.`2`[4])
node credit_available_hi_hi_2 = cat(states[4].vc_sel.`2`[7], states[4].vc_sel.`2`[6])
node credit_available_hi_2 = cat(credit_available_hi_hi_2, credit_available_hi_lo_2)
node _credit_available_T_2 = cat(credit_available_hi_2, credit_available_lo_2)
node credit_available_hi_3 = cat(_credit_available_T_2, _credit_available_T_1)
node _credit_available_T_3 = cat(credit_available_hi_3, _credit_available_T)
node credit_available_lo_lo_3 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_3 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_3 = cat(credit_available_lo_hi_3, credit_available_lo_lo_3)
node credit_available_hi_lo_3 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_3 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_4 = cat(credit_available_hi_hi_3, credit_available_hi_lo_3)
node _credit_available_T_4 = cat(credit_available_hi_4, credit_available_lo_3)
node credit_available_lo_lo_4 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_4 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2])
node credit_available_lo_4 = cat(credit_available_lo_hi_4, credit_available_lo_lo_4)
node credit_available_hi_lo_4 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4])
node credit_available_hi_hi_4 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6])
node credit_available_hi_5 = cat(credit_available_hi_hi_4, credit_available_hi_lo_4)
node _credit_available_T_5 = cat(credit_available_hi_5, credit_available_lo_4)
node credit_available_lo_lo_5 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_5 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2])
node credit_available_lo_5 = cat(credit_available_lo_hi_5, credit_available_lo_lo_5)
node credit_available_hi_lo_5 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4])
node credit_available_hi_hi_5 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6])
node credit_available_hi_6 = cat(credit_available_hi_hi_5, credit_available_hi_lo_5)
node _credit_available_T_6 = cat(credit_available_hi_6, credit_available_lo_5)
node credit_available_hi_7 = cat(_credit_available_T_6, _credit_available_T_5)
node _credit_available_T_7 = cat(credit_available_hi_7, _credit_available_T_4)
node _credit_available_T_8 = and(_credit_available_T_3, _credit_available_T_7)
node credit_available = neq(_credit_available_T_8, UInt<1>(0h0))
node _salloc_arb_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h3))
node _salloc_arb_io_in_4_valid_T_1 = and(_salloc_arb_io_in_4_valid_T, credit_available)
node _salloc_arb_io_in_4_valid_T_2 = and(_salloc_arb_io_in_4_valid_T_1, input_buffer.io.deq[4].valid)
connect salloc_arb.io.in[4].valid, _salloc_arb_io_in_4_valid_T_2
connect salloc_arb.io.in[4].bits.vc_sel.`0`[0], states[4].vc_sel.`0`[0]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[1], states[4].vc_sel.`0`[1]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[2], states[4].vc_sel.`0`[2]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[3], states[4].vc_sel.`0`[3]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[4], states[4].vc_sel.`0`[4]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[5], states[4].vc_sel.`0`[5]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[6], states[4].vc_sel.`0`[6]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[7], states[4].vc_sel.`0`[7]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[0], states[4].vc_sel.`1`[0]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[1], states[4].vc_sel.`1`[1]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[2], states[4].vc_sel.`1`[2]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[3], states[4].vc_sel.`1`[3]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[4], states[4].vc_sel.`1`[4]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[5], states[4].vc_sel.`1`[5]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[6], states[4].vc_sel.`1`[6]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[7], states[4].vc_sel.`1`[7]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[0], states[4].vc_sel.`2`[0]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[1], states[4].vc_sel.`2`[1]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[2], states[4].vc_sel.`2`[2]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[3], states[4].vc_sel.`2`[3]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[4], states[4].vc_sel.`2`[4]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[5], states[4].vc_sel.`2`[5]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[6], states[4].vc_sel.`2`[6]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[7], states[4].vc_sel.`2`[7]
connect salloc_arb.io.in[4].bits.tail, input_buffer.io.deq[4].bits.tail
node _T_87 = and(salloc_arb.io.in[4].ready, salloc_arb.io.in[4].valid)
node _T_88 = and(_T_87, input_buffer.io.deq[4].bits.tail)
when _T_88 :
connect states[4].g, UInt<3>(0h0)
connect input_buffer.io.deq[4].ready, salloc_arb.io.in[4].ready
node credit_available_lo_lo_6 = cat(states[5].vc_sel.`0`[1], states[5].vc_sel.`0`[0])
node credit_available_lo_hi_6 = cat(states[5].vc_sel.`0`[3], states[5].vc_sel.`0`[2])
node credit_available_lo_6 = cat(credit_available_lo_hi_6, credit_available_lo_lo_6)
node credit_available_hi_lo_6 = cat(states[5].vc_sel.`0`[5], states[5].vc_sel.`0`[4])
node credit_available_hi_hi_6 = cat(states[5].vc_sel.`0`[7], states[5].vc_sel.`0`[6])
node credit_available_hi_8 = cat(credit_available_hi_hi_6, credit_available_hi_lo_6)
node _credit_available_T_9 = cat(credit_available_hi_8, credit_available_lo_6)
node credit_available_lo_lo_7 = cat(states[5].vc_sel.`1`[1], states[5].vc_sel.`1`[0])
node credit_available_lo_hi_7 = cat(states[5].vc_sel.`1`[3], states[5].vc_sel.`1`[2])
node credit_available_lo_7 = cat(credit_available_lo_hi_7, credit_available_lo_lo_7)
node credit_available_hi_lo_7 = cat(states[5].vc_sel.`1`[5], states[5].vc_sel.`1`[4])
node credit_available_hi_hi_7 = cat(states[5].vc_sel.`1`[7], states[5].vc_sel.`1`[6])
node credit_available_hi_9 = cat(credit_available_hi_hi_7, credit_available_hi_lo_7)
node _credit_available_T_10 = cat(credit_available_hi_9, credit_available_lo_7)
node credit_available_lo_lo_8 = cat(states[5].vc_sel.`2`[1], states[5].vc_sel.`2`[0])
node credit_available_lo_hi_8 = cat(states[5].vc_sel.`2`[3], states[5].vc_sel.`2`[2])
node credit_available_lo_8 = cat(credit_available_lo_hi_8, credit_available_lo_lo_8)
node credit_available_hi_lo_8 = cat(states[5].vc_sel.`2`[5], states[5].vc_sel.`2`[4])
node credit_available_hi_hi_8 = cat(states[5].vc_sel.`2`[7], states[5].vc_sel.`2`[6])
node credit_available_hi_10 = cat(credit_available_hi_hi_8, credit_available_hi_lo_8)
node _credit_available_T_11 = cat(credit_available_hi_10, credit_available_lo_8)
node credit_available_hi_11 = cat(_credit_available_T_11, _credit_available_T_10)
node _credit_available_T_12 = cat(credit_available_hi_11, _credit_available_T_9)
node credit_available_lo_lo_9 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_9 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_9 = cat(credit_available_lo_hi_9, credit_available_lo_lo_9)
node credit_available_hi_lo_9 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_9 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_12 = cat(credit_available_hi_hi_9, credit_available_hi_lo_9)
node _credit_available_T_13 = cat(credit_available_hi_12, credit_available_lo_9)
node credit_available_lo_lo_10 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_10 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2])
node credit_available_lo_10 = cat(credit_available_lo_hi_10, credit_available_lo_lo_10)
node credit_available_hi_lo_10 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4])
node credit_available_hi_hi_10 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6])
node credit_available_hi_13 = cat(credit_available_hi_hi_10, credit_available_hi_lo_10)
node _credit_available_T_14 = cat(credit_available_hi_13, credit_available_lo_10)
node credit_available_lo_lo_11 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_11 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2])
node credit_available_lo_11 = cat(credit_available_lo_hi_11, credit_available_lo_lo_11)
node credit_available_hi_lo_11 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4])
node credit_available_hi_hi_11 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6])
node credit_available_hi_14 = cat(credit_available_hi_hi_11, credit_available_hi_lo_11)
node _credit_available_T_15 = cat(credit_available_hi_14, credit_available_lo_11)
node credit_available_hi_15 = cat(_credit_available_T_15, _credit_available_T_14)
node _credit_available_T_16 = cat(credit_available_hi_15, _credit_available_T_13)
node _credit_available_T_17 = and(_credit_available_T_12, _credit_available_T_16)
node credit_available_1 = neq(_credit_available_T_17, UInt<1>(0h0))
node _salloc_arb_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h3))
node _salloc_arb_io_in_5_valid_T_1 = and(_salloc_arb_io_in_5_valid_T, credit_available_1)
node _salloc_arb_io_in_5_valid_T_2 = and(_salloc_arb_io_in_5_valid_T_1, input_buffer.io.deq[5].valid)
connect salloc_arb.io.in[5].valid, _salloc_arb_io_in_5_valid_T_2
connect salloc_arb.io.in[5].bits.vc_sel.`0`[0], states[5].vc_sel.`0`[0]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[1], states[5].vc_sel.`0`[1]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[2], states[5].vc_sel.`0`[2]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[3], states[5].vc_sel.`0`[3]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[4], states[5].vc_sel.`0`[4]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[5], states[5].vc_sel.`0`[5]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[6], states[5].vc_sel.`0`[6]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[7], states[5].vc_sel.`0`[7]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[0], states[5].vc_sel.`1`[0]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[1], states[5].vc_sel.`1`[1]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[2], states[5].vc_sel.`1`[2]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[3], states[5].vc_sel.`1`[3]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[4], states[5].vc_sel.`1`[4]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[5], states[5].vc_sel.`1`[5]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[6], states[5].vc_sel.`1`[6]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[7], states[5].vc_sel.`1`[7]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[0], states[5].vc_sel.`2`[0]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[1], states[5].vc_sel.`2`[1]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[2], states[5].vc_sel.`2`[2]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[3], states[5].vc_sel.`2`[3]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[4], states[5].vc_sel.`2`[4]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[5], states[5].vc_sel.`2`[5]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[6], states[5].vc_sel.`2`[6]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[7], states[5].vc_sel.`2`[7]
connect salloc_arb.io.in[5].bits.tail, input_buffer.io.deq[5].bits.tail
node _T_89 = and(salloc_arb.io.in[5].ready, salloc_arb.io.in[5].valid)
node _T_90 = and(_T_89, input_buffer.io.deq[5].bits.tail)
when _T_90 :
connect states[5].g, UInt<3>(0h0)
connect input_buffer.io.deq[5].ready, salloc_arb.io.in[5].ready
node credit_available_lo_lo_12 = cat(states[6].vc_sel.`0`[1], states[6].vc_sel.`0`[0])
node credit_available_lo_hi_12 = cat(states[6].vc_sel.`0`[3], states[6].vc_sel.`0`[2])
node credit_available_lo_12 = cat(credit_available_lo_hi_12, credit_available_lo_lo_12)
node credit_available_hi_lo_12 = cat(states[6].vc_sel.`0`[5], states[6].vc_sel.`0`[4])
node credit_available_hi_hi_12 = cat(states[6].vc_sel.`0`[7], states[6].vc_sel.`0`[6])
node credit_available_hi_16 = cat(credit_available_hi_hi_12, credit_available_hi_lo_12)
node _credit_available_T_18 = cat(credit_available_hi_16, credit_available_lo_12)
node credit_available_lo_lo_13 = cat(states[6].vc_sel.`1`[1], states[6].vc_sel.`1`[0])
node credit_available_lo_hi_13 = cat(states[6].vc_sel.`1`[3], states[6].vc_sel.`1`[2])
node credit_available_lo_13 = cat(credit_available_lo_hi_13, credit_available_lo_lo_13)
node credit_available_hi_lo_13 = cat(states[6].vc_sel.`1`[5], states[6].vc_sel.`1`[4])
node credit_available_hi_hi_13 = cat(states[6].vc_sel.`1`[7], states[6].vc_sel.`1`[6])
node credit_available_hi_17 = cat(credit_available_hi_hi_13, credit_available_hi_lo_13)
node _credit_available_T_19 = cat(credit_available_hi_17, credit_available_lo_13)
node credit_available_lo_lo_14 = cat(states[6].vc_sel.`2`[1], states[6].vc_sel.`2`[0])
node credit_available_lo_hi_14 = cat(states[6].vc_sel.`2`[3], states[6].vc_sel.`2`[2])
node credit_available_lo_14 = cat(credit_available_lo_hi_14, credit_available_lo_lo_14)
node credit_available_hi_lo_14 = cat(states[6].vc_sel.`2`[5], states[6].vc_sel.`2`[4])
node credit_available_hi_hi_14 = cat(states[6].vc_sel.`2`[7], states[6].vc_sel.`2`[6])
node credit_available_hi_18 = cat(credit_available_hi_hi_14, credit_available_hi_lo_14)
node _credit_available_T_20 = cat(credit_available_hi_18, credit_available_lo_14)
node credit_available_hi_19 = cat(_credit_available_T_20, _credit_available_T_19)
node _credit_available_T_21 = cat(credit_available_hi_19, _credit_available_T_18)
node credit_available_lo_lo_15 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_15 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_15 = cat(credit_available_lo_hi_15, credit_available_lo_lo_15)
node credit_available_hi_lo_15 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_15 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_20 = cat(credit_available_hi_hi_15, credit_available_hi_lo_15)
node _credit_available_T_22 = cat(credit_available_hi_20, credit_available_lo_15)
node credit_available_lo_lo_16 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_16 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2])
node credit_available_lo_16 = cat(credit_available_lo_hi_16, credit_available_lo_lo_16)
node credit_available_hi_lo_16 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4])
node credit_available_hi_hi_16 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6])
node credit_available_hi_21 = cat(credit_available_hi_hi_16, credit_available_hi_lo_16)
node _credit_available_T_23 = cat(credit_available_hi_21, credit_available_lo_16)
node credit_available_lo_lo_17 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_17 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2])
node credit_available_lo_17 = cat(credit_available_lo_hi_17, credit_available_lo_lo_17)
node credit_available_hi_lo_17 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4])
node credit_available_hi_hi_17 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6])
node credit_available_hi_22 = cat(credit_available_hi_hi_17, credit_available_hi_lo_17)
node _credit_available_T_24 = cat(credit_available_hi_22, credit_available_lo_17)
node credit_available_hi_23 = cat(_credit_available_T_24, _credit_available_T_23)
node _credit_available_T_25 = cat(credit_available_hi_23, _credit_available_T_22)
node _credit_available_T_26 = and(_credit_available_T_21, _credit_available_T_25)
node credit_available_2 = neq(_credit_available_T_26, UInt<1>(0h0))
node _salloc_arb_io_in_6_valid_T = eq(states[6].g, UInt<3>(0h3))
node _salloc_arb_io_in_6_valid_T_1 = and(_salloc_arb_io_in_6_valid_T, credit_available_2)
node _salloc_arb_io_in_6_valid_T_2 = and(_salloc_arb_io_in_6_valid_T_1, input_buffer.io.deq[6].valid)
connect salloc_arb.io.in[6].valid, _salloc_arb_io_in_6_valid_T_2
connect salloc_arb.io.in[6].bits.vc_sel.`0`[0], states[6].vc_sel.`0`[0]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[1], states[6].vc_sel.`0`[1]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[2], states[6].vc_sel.`0`[2]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[3], states[6].vc_sel.`0`[3]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[4], states[6].vc_sel.`0`[4]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[5], states[6].vc_sel.`0`[5]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[6], states[6].vc_sel.`0`[6]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[7], states[6].vc_sel.`0`[7]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[0], states[6].vc_sel.`1`[0]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[1], states[6].vc_sel.`1`[1]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[2], states[6].vc_sel.`1`[2]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[3], states[6].vc_sel.`1`[3]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[4], states[6].vc_sel.`1`[4]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[5], states[6].vc_sel.`1`[5]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[6], states[6].vc_sel.`1`[6]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[7], states[6].vc_sel.`1`[7]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[0], states[6].vc_sel.`2`[0]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[1], states[6].vc_sel.`2`[1]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[2], states[6].vc_sel.`2`[2]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[3], states[6].vc_sel.`2`[3]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[4], states[6].vc_sel.`2`[4]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[5], states[6].vc_sel.`2`[5]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[6], states[6].vc_sel.`2`[6]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[7], states[6].vc_sel.`2`[7]
connect salloc_arb.io.in[6].bits.tail, input_buffer.io.deq[6].bits.tail
node _T_91 = and(salloc_arb.io.in[6].ready, salloc_arb.io.in[6].valid)
node _T_92 = and(_T_91, input_buffer.io.deq[6].bits.tail)
when _T_92 :
connect states[6].g, UInt<3>(0h0)
connect input_buffer.io.deq[6].ready, salloc_arb.io.in[6].ready
node credit_available_lo_lo_18 = cat(states[7].vc_sel.`0`[1], states[7].vc_sel.`0`[0])
node credit_available_lo_hi_18 = cat(states[7].vc_sel.`0`[3], states[7].vc_sel.`0`[2])
node credit_available_lo_18 = cat(credit_available_lo_hi_18, credit_available_lo_lo_18)
node credit_available_hi_lo_18 = cat(states[7].vc_sel.`0`[5], states[7].vc_sel.`0`[4])
node credit_available_hi_hi_18 = cat(states[7].vc_sel.`0`[7], states[7].vc_sel.`0`[6])
node credit_available_hi_24 = cat(credit_available_hi_hi_18, credit_available_hi_lo_18)
node _credit_available_T_27 = cat(credit_available_hi_24, credit_available_lo_18)
node credit_available_lo_lo_19 = cat(states[7].vc_sel.`1`[1], states[7].vc_sel.`1`[0])
node credit_available_lo_hi_19 = cat(states[7].vc_sel.`1`[3], states[7].vc_sel.`1`[2])
node credit_available_lo_19 = cat(credit_available_lo_hi_19, credit_available_lo_lo_19)
node credit_available_hi_lo_19 = cat(states[7].vc_sel.`1`[5], states[7].vc_sel.`1`[4])
node credit_available_hi_hi_19 = cat(states[7].vc_sel.`1`[7], states[7].vc_sel.`1`[6])
node credit_available_hi_25 = cat(credit_available_hi_hi_19, credit_available_hi_lo_19)
node _credit_available_T_28 = cat(credit_available_hi_25, credit_available_lo_19)
node credit_available_lo_lo_20 = cat(states[7].vc_sel.`2`[1], states[7].vc_sel.`2`[0])
node credit_available_lo_hi_20 = cat(states[7].vc_sel.`2`[3], states[7].vc_sel.`2`[2])
node credit_available_lo_20 = cat(credit_available_lo_hi_20, credit_available_lo_lo_20)
node credit_available_hi_lo_20 = cat(states[7].vc_sel.`2`[5], states[7].vc_sel.`2`[4])
node credit_available_hi_hi_20 = cat(states[7].vc_sel.`2`[7], states[7].vc_sel.`2`[6])
node credit_available_hi_26 = cat(credit_available_hi_hi_20, credit_available_hi_lo_20)
node _credit_available_T_29 = cat(credit_available_hi_26, credit_available_lo_20)
node credit_available_hi_27 = cat(_credit_available_T_29, _credit_available_T_28)
node _credit_available_T_30 = cat(credit_available_hi_27, _credit_available_T_27)
node credit_available_lo_lo_21 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_21 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_21 = cat(credit_available_lo_hi_21, credit_available_lo_lo_21)
node credit_available_hi_lo_21 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_21 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_28 = cat(credit_available_hi_hi_21, credit_available_hi_lo_21)
node _credit_available_T_31 = cat(credit_available_hi_28, credit_available_lo_21)
node credit_available_lo_lo_22 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_22 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2])
node credit_available_lo_22 = cat(credit_available_lo_hi_22, credit_available_lo_lo_22)
node credit_available_hi_lo_22 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4])
node credit_available_hi_hi_22 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6])
node credit_available_hi_29 = cat(credit_available_hi_hi_22, credit_available_hi_lo_22)
node _credit_available_T_32 = cat(credit_available_hi_29, credit_available_lo_22)
node credit_available_lo_lo_23 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_23 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2])
node credit_available_lo_23 = cat(credit_available_lo_hi_23, credit_available_lo_lo_23)
node credit_available_hi_lo_23 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4])
node credit_available_hi_hi_23 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6])
node credit_available_hi_30 = cat(credit_available_hi_hi_23, credit_available_hi_lo_23)
node _credit_available_T_33 = cat(credit_available_hi_30, credit_available_lo_23)
node credit_available_hi_31 = cat(_credit_available_T_33, _credit_available_T_32)
node _credit_available_T_34 = cat(credit_available_hi_31, _credit_available_T_31)
node _credit_available_T_35 = and(_credit_available_T_30, _credit_available_T_34)
node credit_available_3 = neq(_credit_available_T_35, UInt<1>(0h0))
node _salloc_arb_io_in_7_valid_T = eq(states[7].g, UInt<3>(0h3))
node _salloc_arb_io_in_7_valid_T_1 = and(_salloc_arb_io_in_7_valid_T, credit_available_3)
node _salloc_arb_io_in_7_valid_T_2 = and(_salloc_arb_io_in_7_valid_T_1, input_buffer.io.deq[7].valid)
connect salloc_arb.io.in[7].valid, _salloc_arb_io_in_7_valid_T_2
connect salloc_arb.io.in[7].bits.vc_sel.`0`[0], states[7].vc_sel.`0`[0]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[1], states[7].vc_sel.`0`[1]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[2], states[7].vc_sel.`0`[2]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[3], states[7].vc_sel.`0`[3]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[4], states[7].vc_sel.`0`[4]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[5], states[7].vc_sel.`0`[5]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[6], states[7].vc_sel.`0`[6]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[7], states[7].vc_sel.`0`[7]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[0], states[7].vc_sel.`1`[0]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[1], states[7].vc_sel.`1`[1]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[2], states[7].vc_sel.`1`[2]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[3], states[7].vc_sel.`1`[3]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[4], states[7].vc_sel.`1`[4]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[5], states[7].vc_sel.`1`[5]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[6], states[7].vc_sel.`1`[6]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[7], states[7].vc_sel.`1`[7]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[0], states[7].vc_sel.`2`[0]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[1], states[7].vc_sel.`2`[1]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[2], states[7].vc_sel.`2`[2]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[3], states[7].vc_sel.`2`[3]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[4], states[7].vc_sel.`2`[4]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[5], states[7].vc_sel.`2`[5]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[6], states[7].vc_sel.`2`[6]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[7], states[7].vc_sel.`2`[7]
connect salloc_arb.io.in[7].bits.tail, input_buffer.io.deq[7].bits.tail
node _T_93 = and(salloc_arb.io.in[7].ready, salloc_arb.io.in[7].valid)
node _T_94 = and(_T_93, input_buffer.io.deq[7].bits.tail)
when _T_94 :
connect states[7].g, UInt<3>(0h0)
connect input_buffer.io.deq[7].ready, salloc_arb.io.in[7].ready
node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T)
node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2)
node _io_debug_sa_stall_T_4 = eq(salloc_arb.io.in[2].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_5 = and(salloc_arb.io.in[2].valid, _io_debug_sa_stall_T_4)
node _io_debug_sa_stall_T_6 = eq(salloc_arb.io.in[3].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_7 = and(salloc_arb.io.in[3].valid, _io_debug_sa_stall_T_6)
node _io_debug_sa_stall_T_8 = eq(salloc_arb.io.in[4].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_9 = and(salloc_arb.io.in[4].valid, _io_debug_sa_stall_T_8)
node _io_debug_sa_stall_T_10 = eq(salloc_arb.io.in[5].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_11 = and(salloc_arb.io.in[5].valid, _io_debug_sa_stall_T_10)
node _io_debug_sa_stall_T_12 = eq(salloc_arb.io.in[6].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_13 = and(salloc_arb.io.in[6].valid, _io_debug_sa_stall_T_12)
node _io_debug_sa_stall_T_14 = eq(salloc_arb.io.in[7].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_15 = and(salloc_arb.io.in[7].valid, _io_debug_sa_stall_T_14)
node _io_debug_sa_stall_T_16 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_3)
node _io_debug_sa_stall_T_17 = bits(_io_debug_sa_stall_T_16, 1, 0)
node _io_debug_sa_stall_T_18 = add(_io_debug_sa_stall_T_5, _io_debug_sa_stall_T_7)
node _io_debug_sa_stall_T_19 = bits(_io_debug_sa_stall_T_18, 1, 0)
node _io_debug_sa_stall_T_20 = add(_io_debug_sa_stall_T_17, _io_debug_sa_stall_T_19)
node _io_debug_sa_stall_T_21 = bits(_io_debug_sa_stall_T_20, 2, 0)
node _io_debug_sa_stall_T_22 = add(_io_debug_sa_stall_T_9, _io_debug_sa_stall_T_11)
node _io_debug_sa_stall_T_23 = bits(_io_debug_sa_stall_T_22, 1, 0)
node _io_debug_sa_stall_T_24 = add(_io_debug_sa_stall_T_13, _io_debug_sa_stall_T_15)
node _io_debug_sa_stall_T_25 = bits(_io_debug_sa_stall_T_24, 1, 0)
node _io_debug_sa_stall_T_26 = add(_io_debug_sa_stall_T_23, _io_debug_sa_stall_T_25)
node _io_debug_sa_stall_T_27 = bits(_io_debug_sa_stall_T_26, 2, 0)
node _io_debug_sa_stall_T_28 = add(_io_debug_sa_stall_T_21, _io_debug_sa_stall_T_27)
node _io_debug_sa_stall_T_29 = bits(_io_debug_sa_stall_T_28, 3, 0)
connect io.debug.sa_stall, _io_debug_sa_stall_T_29
connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits
connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid
connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready
when io.block :
connect salloc_arb.io.out[0].ready, UInt<1>(0h0)
connect io.salloc_req[0].valid, UInt<1>(0h0)
reg salloc_outs : { valid : UInt<1>, vid : UInt<3>, out_vid : UInt<3>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], clock
node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0))
connect io.in.credit_return, _io_in_credit_return_T_1
node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _io_in_vc_free_T_3 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _io_in_vc_free_T_4 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _io_in_vc_free_T_5 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _io_in_vc_free_T_6 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _io_in_vc_free_T_7 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _io_in_vc_free_T_8 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
node _io_in_vc_free_T_9 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_10 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_11 = mux(_io_in_vc_free_T_3, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_12 = mux(_io_in_vc_free_T_4, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_13 = mux(_io_in_vc_free_T_5, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_14 = mux(_io_in_vc_free_T_6, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_15 = mux(_io_in_vc_free_T_7, input_buffer.io.deq[6].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_16 = mux(_io_in_vc_free_T_8, input_buffer.io.deq[7].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_17 = or(_io_in_vc_free_T_9, _io_in_vc_free_T_10)
node _io_in_vc_free_T_18 = or(_io_in_vc_free_T_17, _io_in_vc_free_T_11)
node _io_in_vc_free_T_19 = or(_io_in_vc_free_T_18, _io_in_vc_free_T_12)
node _io_in_vc_free_T_20 = or(_io_in_vc_free_T_19, _io_in_vc_free_T_13)
node _io_in_vc_free_T_21 = or(_io_in_vc_free_T_20, _io_in_vc_free_T_14)
node _io_in_vc_free_T_22 = or(_io_in_vc_free_T_21, _io_in_vc_free_T_15)
node _io_in_vc_free_T_23 = or(_io_in_vc_free_T_22, _io_in_vc_free_T_16)
wire _io_in_vc_free_WIRE : UInt<1>
connect _io_in_vc_free_WIRE, _io_in_vc_free_T_23
node _io_in_vc_free_T_24 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE)
node _io_in_vc_free_T_25 = mux(_io_in_vc_free_T_24, salloc_arb.io.chosen_oh[0], UInt<1>(0h0))
connect io.in.vc_free, _io_in_vc_free_T_25
node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
connect salloc_outs[0].valid, _salloc_outs_0_valid_T
node salloc_outs_0_vid_hi = bits(salloc_arb.io.chosen_oh[0], 7, 4)
node salloc_outs_0_vid_lo = bits(salloc_arb.io.chosen_oh[0], 3, 0)
node _salloc_outs_0_vid_T = orr(salloc_outs_0_vid_hi)
node _salloc_outs_0_vid_T_1 = or(salloc_outs_0_vid_hi, salloc_outs_0_vid_lo)
node salloc_outs_0_vid_hi_1 = bits(_salloc_outs_0_vid_T_1, 3, 2)
node salloc_outs_0_vid_lo_1 = bits(_salloc_outs_0_vid_T_1, 1, 0)
node _salloc_outs_0_vid_T_2 = orr(salloc_outs_0_vid_hi_1)
node _salloc_outs_0_vid_T_3 = or(salloc_outs_0_vid_hi_1, salloc_outs_0_vid_lo_1)
node _salloc_outs_0_vid_T_4 = bits(_salloc_outs_0_vid_T_3, 1, 1)
node _salloc_outs_0_vid_T_5 = cat(_salloc_outs_0_vid_T_2, _salloc_outs_0_vid_T_4)
node _salloc_outs_0_vid_T_6 = cat(_salloc_outs_0_vid_T, _salloc_outs_0_vid_T_5)
connect salloc_outs[0].vid, _salloc_outs_0_vid_T_6
node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _vc_sel_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _vc_sel_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _vc_sel_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _vc_sel_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _vc_sel_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _vc_sel_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
wire vc_sel : { `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}
wire _vc_sel_WIRE : UInt<1>[8]
node _vc_sel_T_8 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_9 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_10 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_11 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_12 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_13 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_14 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_15 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_16 = or(_vc_sel_T_8, _vc_sel_T_9)
node _vc_sel_T_17 = or(_vc_sel_T_16, _vc_sel_T_10)
node _vc_sel_T_18 = or(_vc_sel_T_17, _vc_sel_T_11)
node _vc_sel_T_19 = or(_vc_sel_T_18, _vc_sel_T_12)
node _vc_sel_T_20 = or(_vc_sel_T_19, _vc_sel_T_13)
node _vc_sel_T_21 = or(_vc_sel_T_20, _vc_sel_T_14)
node _vc_sel_T_22 = or(_vc_sel_T_21, _vc_sel_T_15)
wire _vc_sel_WIRE_1 : UInt<1>
connect _vc_sel_WIRE_1, _vc_sel_T_22
connect _vc_sel_WIRE[0], _vc_sel_WIRE_1
node _vc_sel_T_23 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_24 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_25 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_26 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_27 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_28 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_29 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_30 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_31 = or(_vc_sel_T_23, _vc_sel_T_24)
node _vc_sel_T_32 = or(_vc_sel_T_31, _vc_sel_T_25)
node _vc_sel_T_33 = or(_vc_sel_T_32, _vc_sel_T_26)
node _vc_sel_T_34 = or(_vc_sel_T_33, _vc_sel_T_27)
node _vc_sel_T_35 = or(_vc_sel_T_34, _vc_sel_T_28)
node _vc_sel_T_36 = or(_vc_sel_T_35, _vc_sel_T_29)
node _vc_sel_T_37 = or(_vc_sel_T_36, _vc_sel_T_30)
wire _vc_sel_WIRE_2 : UInt<1>
connect _vc_sel_WIRE_2, _vc_sel_T_37
connect _vc_sel_WIRE[1], _vc_sel_WIRE_2
node _vc_sel_T_38 = mux(_vc_sel_T, states[0].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_39 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_40 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_41 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_42 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_43 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_44 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_45 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_46 = or(_vc_sel_T_38, _vc_sel_T_39)
node _vc_sel_T_47 = or(_vc_sel_T_46, _vc_sel_T_40)
node _vc_sel_T_48 = or(_vc_sel_T_47, _vc_sel_T_41)
node _vc_sel_T_49 = or(_vc_sel_T_48, _vc_sel_T_42)
node _vc_sel_T_50 = or(_vc_sel_T_49, _vc_sel_T_43)
node _vc_sel_T_51 = or(_vc_sel_T_50, _vc_sel_T_44)
node _vc_sel_T_52 = or(_vc_sel_T_51, _vc_sel_T_45)
wire _vc_sel_WIRE_3 : UInt<1>
connect _vc_sel_WIRE_3, _vc_sel_T_52
connect _vc_sel_WIRE[2], _vc_sel_WIRE_3
node _vc_sel_T_53 = mux(_vc_sel_T, states[0].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_54 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_55 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_56 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_57 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_58 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_59 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_60 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_61 = or(_vc_sel_T_53, _vc_sel_T_54)
node _vc_sel_T_62 = or(_vc_sel_T_61, _vc_sel_T_55)
node _vc_sel_T_63 = or(_vc_sel_T_62, _vc_sel_T_56)
node _vc_sel_T_64 = or(_vc_sel_T_63, _vc_sel_T_57)
node _vc_sel_T_65 = or(_vc_sel_T_64, _vc_sel_T_58)
node _vc_sel_T_66 = or(_vc_sel_T_65, _vc_sel_T_59)
node _vc_sel_T_67 = or(_vc_sel_T_66, _vc_sel_T_60)
wire _vc_sel_WIRE_4 : UInt<1>
connect _vc_sel_WIRE_4, _vc_sel_T_67
connect _vc_sel_WIRE[3], _vc_sel_WIRE_4
node _vc_sel_T_68 = mux(_vc_sel_T, states[0].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_69 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_70 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_71 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_72 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_73 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_74 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_75 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_76 = or(_vc_sel_T_68, _vc_sel_T_69)
node _vc_sel_T_77 = or(_vc_sel_T_76, _vc_sel_T_70)
node _vc_sel_T_78 = or(_vc_sel_T_77, _vc_sel_T_71)
node _vc_sel_T_79 = or(_vc_sel_T_78, _vc_sel_T_72)
node _vc_sel_T_80 = or(_vc_sel_T_79, _vc_sel_T_73)
node _vc_sel_T_81 = or(_vc_sel_T_80, _vc_sel_T_74)
node _vc_sel_T_82 = or(_vc_sel_T_81, _vc_sel_T_75)
wire _vc_sel_WIRE_5 : UInt<1>
connect _vc_sel_WIRE_5, _vc_sel_T_82
connect _vc_sel_WIRE[4], _vc_sel_WIRE_5
node _vc_sel_T_83 = mux(_vc_sel_T, states[0].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_84 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_85 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_86 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_87 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_88 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_89 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_90 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_91 = or(_vc_sel_T_83, _vc_sel_T_84)
node _vc_sel_T_92 = or(_vc_sel_T_91, _vc_sel_T_85)
node _vc_sel_T_93 = or(_vc_sel_T_92, _vc_sel_T_86)
node _vc_sel_T_94 = or(_vc_sel_T_93, _vc_sel_T_87)
node _vc_sel_T_95 = or(_vc_sel_T_94, _vc_sel_T_88)
node _vc_sel_T_96 = or(_vc_sel_T_95, _vc_sel_T_89)
node _vc_sel_T_97 = or(_vc_sel_T_96, _vc_sel_T_90)
wire _vc_sel_WIRE_6 : UInt<1>
connect _vc_sel_WIRE_6, _vc_sel_T_97
connect _vc_sel_WIRE[5], _vc_sel_WIRE_6
node _vc_sel_T_98 = mux(_vc_sel_T, states[0].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_99 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_100 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_101 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_102 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_103 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_104 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_105 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_106 = or(_vc_sel_T_98, _vc_sel_T_99)
node _vc_sel_T_107 = or(_vc_sel_T_106, _vc_sel_T_100)
node _vc_sel_T_108 = or(_vc_sel_T_107, _vc_sel_T_101)
node _vc_sel_T_109 = or(_vc_sel_T_108, _vc_sel_T_102)
node _vc_sel_T_110 = or(_vc_sel_T_109, _vc_sel_T_103)
node _vc_sel_T_111 = or(_vc_sel_T_110, _vc_sel_T_104)
node _vc_sel_T_112 = or(_vc_sel_T_111, _vc_sel_T_105)
wire _vc_sel_WIRE_7 : UInt<1>
connect _vc_sel_WIRE_7, _vc_sel_T_112
connect _vc_sel_WIRE[6], _vc_sel_WIRE_7
node _vc_sel_T_113 = mux(_vc_sel_T, states[0].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_114 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_115 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_116 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_117 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_118 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_119 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_120 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_121 = or(_vc_sel_T_113, _vc_sel_T_114)
node _vc_sel_T_122 = or(_vc_sel_T_121, _vc_sel_T_115)
node _vc_sel_T_123 = or(_vc_sel_T_122, _vc_sel_T_116)
node _vc_sel_T_124 = or(_vc_sel_T_123, _vc_sel_T_117)
node _vc_sel_T_125 = or(_vc_sel_T_124, _vc_sel_T_118)
node _vc_sel_T_126 = or(_vc_sel_T_125, _vc_sel_T_119)
node _vc_sel_T_127 = or(_vc_sel_T_126, _vc_sel_T_120)
wire _vc_sel_WIRE_8 : UInt<1>
connect _vc_sel_WIRE_8, _vc_sel_T_127
connect _vc_sel_WIRE[7], _vc_sel_WIRE_8
connect vc_sel.`0`, _vc_sel_WIRE
wire _vc_sel_WIRE_9 : UInt<1>[8]
node _vc_sel_T_128 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_129 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_130 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_131 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_132 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_133 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_134 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_135 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_136 = or(_vc_sel_T_128, _vc_sel_T_129)
node _vc_sel_T_137 = or(_vc_sel_T_136, _vc_sel_T_130)
node _vc_sel_T_138 = or(_vc_sel_T_137, _vc_sel_T_131)
node _vc_sel_T_139 = or(_vc_sel_T_138, _vc_sel_T_132)
node _vc_sel_T_140 = or(_vc_sel_T_139, _vc_sel_T_133)
node _vc_sel_T_141 = or(_vc_sel_T_140, _vc_sel_T_134)
node _vc_sel_T_142 = or(_vc_sel_T_141, _vc_sel_T_135)
wire _vc_sel_WIRE_10 : UInt<1>
connect _vc_sel_WIRE_10, _vc_sel_T_142
connect _vc_sel_WIRE_9[0], _vc_sel_WIRE_10
node _vc_sel_T_143 = mux(_vc_sel_T, states[0].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_144 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_145 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_146 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_147 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_148 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_149 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_150 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_151 = or(_vc_sel_T_143, _vc_sel_T_144)
node _vc_sel_T_152 = or(_vc_sel_T_151, _vc_sel_T_145)
node _vc_sel_T_153 = or(_vc_sel_T_152, _vc_sel_T_146)
node _vc_sel_T_154 = or(_vc_sel_T_153, _vc_sel_T_147)
node _vc_sel_T_155 = or(_vc_sel_T_154, _vc_sel_T_148)
node _vc_sel_T_156 = or(_vc_sel_T_155, _vc_sel_T_149)
node _vc_sel_T_157 = or(_vc_sel_T_156, _vc_sel_T_150)
wire _vc_sel_WIRE_11 : UInt<1>
connect _vc_sel_WIRE_11, _vc_sel_T_157
connect _vc_sel_WIRE_9[1], _vc_sel_WIRE_11
node _vc_sel_T_158 = mux(_vc_sel_T, states[0].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_159 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_160 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_161 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_162 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_163 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_164 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_165 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_166 = or(_vc_sel_T_158, _vc_sel_T_159)
node _vc_sel_T_167 = or(_vc_sel_T_166, _vc_sel_T_160)
node _vc_sel_T_168 = or(_vc_sel_T_167, _vc_sel_T_161)
node _vc_sel_T_169 = or(_vc_sel_T_168, _vc_sel_T_162)
node _vc_sel_T_170 = or(_vc_sel_T_169, _vc_sel_T_163)
node _vc_sel_T_171 = or(_vc_sel_T_170, _vc_sel_T_164)
node _vc_sel_T_172 = or(_vc_sel_T_171, _vc_sel_T_165)
wire _vc_sel_WIRE_12 : UInt<1>
connect _vc_sel_WIRE_12, _vc_sel_T_172
connect _vc_sel_WIRE_9[2], _vc_sel_WIRE_12
node _vc_sel_T_173 = mux(_vc_sel_T, states[0].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_174 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_175 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_176 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_177 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_178 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_179 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_180 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_181 = or(_vc_sel_T_173, _vc_sel_T_174)
node _vc_sel_T_182 = or(_vc_sel_T_181, _vc_sel_T_175)
node _vc_sel_T_183 = or(_vc_sel_T_182, _vc_sel_T_176)
node _vc_sel_T_184 = or(_vc_sel_T_183, _vc_sel_T_177)
node _vc_sel_T_185 = or(_vc_sel_T_184, _vc_sel_T_178)
node _vc_sel_T_186 = or(_vc_sel_T_185, _vc_sel_T_179)
node _vc_sel_T_187 = or(_vc_sel_T_186, _vc_sel_T_180)
wire _vc_sel_WIRE_13 : UInt<1>
connect _vc_sel_WIRE_13, _vc_sel_T_187
connect _vc_sel_WIRE_9[3], _vc_sel_WIRE_13
node _vc_sel_T_188 = mux(_vc_sel_T, states[0].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_189 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_190 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_191 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_192 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_193 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_194 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_195 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_196 = or(_vc_sel_T_188, _vc_sel_T_189)
node _vc_sel_T_197 = or(_vc_sel_T_196, _vc_sel_T_190)
node _vc_sel_T_198 = or(_vc_sel_T_197, _vc_sel_T_191)
node _vc_sel_T_199 = or(_vc_sel_T_198, _vc_sel_T_192)
node _vc_sel_T_200 = or(_vc_sel_T_199, _vc_sel_T_193)
node _vc_sel_T_201 = or(_vc_sel_T_200, _vc_sel_T_194)
node _vc_sel_T_202 = or(_vc_sel_T_201, _vc_sel_T_195)
wire _vc_sel_WIRE_14 : UInt<1>
connect _vc_sel_WIRE_14, _vc_sel_T_202
connect _vc_sel_WIRE_9[4], _vc_sel_WIRE_14
node _vc_sel_T_203 = mux(_vc_sel_T, states[0].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_204 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_205 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_206 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_207 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_208 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_209 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_210 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_211 = or(_vc_sel_T_203, _vc_sel_T_204)
node _vc_sel_T_212 = or(_vc_sel_T_211, _vc_sel_T_205)
node _vc_sel_T_213 = or(_vc_sel_T_212, _vc_sel_T_206)
node _vc_sel_T_214 = or(_vc_sel_T_213, _vc_sel_T_207)
node _vc_sel_T_215 = or(_vc_sel_T_214, _vc_sel_T_208)
node _vc_sel_T_216 = or(_vc_sel_T_215, _vc_sel_T_209)
node _vc_sel_T_217 = or(_vc_sel_T_216, _vc_sel_T_210)
wire _vc_sel_WIRE_15 : UInt<1>
connect _vc_sel_WIRE_15, _vc_sel_T_217
connect _vc_sel_WIRE_9[5], _vc_sel_WIRE_15
node _vc_sel_T_218 = mux(_vc_sel_T, states[0].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_219 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_220 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_221 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_222 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_223 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_224 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_225 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_226 = or(_vc_sel_T_218, _vc_sel_T_219)
node _vc_sel_T_227 = or(_vc_sel_T_226, _vc_sel_T_220)
node _vc_sel_T_228 = or(_vc_sel_T_227, _vc_sel_T_221)
node _vc_sel_T_229 = or(_vc_sel_T_228, _vc_sel_T_222)
node _vc_sel_T_230 = or(_vc_sel_T_229, _vc_sel_T_223)
node _vc_sel_T_231 = or(_vc_sel_T_230, _vc_sel_T_224)
node _vc_sel_T_232 = or(_vc_sel_T_231, _vc_sel_T_225)
wire _vc_sel_WIRE_16 : UInt<1>
connect _vc_sel_WIRE_16, _vc_sel_T_232
connect _vc_sel_WIRE_9[6], _vc_sel_WIRE_16
node _vc_sel_T_233 = mux(_vc_sel_T, states[0].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_234 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_235 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_236 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_237 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_238 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_239 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_240 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_241 = or(_vc_sel_T_233, _vc_sel_T_234)
node _vc_sel_T_242 = or(_vc_sel_T_241, _vc_sel_T_235)
node _vc_sel_T_243 = or(_vc_sel_T_242, _vc_sel_T_236)
node _vc_sel_T_244 = or(_vc_sel_T_243, _vc_sel_T_237)
node _vc_sel_T_245 = or(_vc_sel_T_244, _vc_sel_T_238)
node _vc_sel_T_246 = or(_vc_sel_T_245, _vc_sel_T_239)
node _vc_sel_T_247 = or(_vc_sel_T_246, _vc_sel_T_240)
wire _vc_sel_WIRE_17 : UInt<1>
connect _vc_sel_WIRE_17, _vc_sel_T_247
connect _vc_sel_WIRE_9[7], _vc_sel_WIRE_17
connect vc_sel.`1`, _vc_sel_WIRE_9
wire _vc_sel_WIRE_18 : UInt<1>[8]
node _vc_sel_T_248 = mux(_vc_sel_T, states[0].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_249 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_250 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_251 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_252 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_253 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_254 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_255 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_256 = or(_vc_sel_T_248, _vc_sel_T_249)
node _vc_sel_T_257 = or(_vc_sel_T_256, _vc_sel_T_250)
node _vc_sel_T_258 = or(_vc_sel_T_257, _vc_sel_T_251)
node _vc_sel_T_259 = or(_vc_sel_T_258, _vc_sel_T_252)
node _vc_sel_T_260 = or(_vc_sel_T_259, _vc_sel_T_253)
node _vc_sel_T_261 = or(_vc_sel_T_260, _vc_sel_T_254)
node _vc_sel_T_262 = or(_vc_sel_T_261, _vc_sel_T_255)
wire _vc_sel_WIRE_19 : UInt<1>
connect _vc_sel_WIRE_19, _vc_sel_T_262
connect _vc_sel_WIRE_18[0], _vc_sel_WIRE_19
node _vc_sel_T_263 = mux(_vc_sel_T, states[0].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_264 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_265 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_266 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_267 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_268 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_269 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_270 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_271 = or(_vc_sel_T_263, _vc_sel_T_264)
node _vc_sel_T_272 = or(_vc_sel_T_271, _vc_sel_T_265)
node _vc_sel_T_273 = or(_vc_sel_T_272, _vc_sel_T_266)
node _vc_sel_T_274 = or(_vc_sel_T_273, _vc_sel_T_267)
node _vc_sel_T_275 = or(_vc_sel_T_274, _vc_sel_T_268)
node _vc_sel_T_276 = or(_vc_sel_T_275, _vc_sel_T_269)
node _vc_sel_T_277 = or(_vc_sel_T_276, _vc_sel_T_270)
wire _vc_sel_WIRE_20 : UInt<1>
connect _vc_sel_WIRE_20, _vc_sel_T_277
connect _vc_sel_WIRE_18[1], _vc_sel_WIRE_20
node _vc_sel_T_278 = mux(_vc_sel_T, states[0].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_279 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_280 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_281 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_282 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_283 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_284 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_285 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_286 = or(_vc_sel_T_278, _vc_sel_T_279)
node _vc_sel_T_287 = or(_vc_sel_T_286, _vc_sel_T_280)
node _vc_sel_T_288 = or(_vc_sel_T_287, _vc_sel_T_281)
node _vc_sel_T_289 = or(_vc_sel_T_288, _vc_sel_T_282)
node _vc_sel_T_290 = or(_vc_sel_T_289, _vc_sel_T_283)
node _vc_sel_T_291 = or(_vc_sel_T_290, _vc_sel_T_284)
node _vc_sel_T_292 = or(_vc_sel_T_291, _vc_sel_T_285)
wire _vc_sel_WIRE_21 : UInt<1>
connect _vc_sel_WIRE_21, _vc_sel_T_292
connect _vc_sel_WIRE_18[2], _vc_sel_WIRE_21
node _vc_sel_T_293 = mux(_vc_sel_T, states[0].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_294 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_295 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_296 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_297 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_298 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_299 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_300 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_301 = or(_vc_sel_T_293, _vc_sel_T_294)
node _vc_sel_T_302 = or(_vc_sel_T_301, _vc_sel_T_295)
node _vc_sel_T_303 = or(_vc_sel_T_302, _vc_sel_T_296)
node _vc_sel_T_304 = or(_vc_sel_T_303, _vc_sel_T_297)
node _vc_sel_T_305 = or(_vc_sel_T_304, _vc_sel_T_298)
node _vc_sel_T_306 = or(_vc_sel_T_305, _vc_sel_T_299)
node _vc_sel_T_307 = or(_vc_sel_T_306, _vc_sel_T_300)
wire _vc_sel_WIRE_22 : UInt<1>
connect _vc_sel_WIRE_22, _vc_sel_T_307
connect _vc_sel_WIRE_18[3], _vc_sel_WIRE_22
node _vc_sel_T_308 = mux(_vc_sel_T, states[0].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_309 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_310 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_311 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_312 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_313 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_314 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_315 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_316 = or(_vc_sel_T_308, _vc_sel_T_309)
node _vc_sel_T_317 = or(_vc_sel_T_316, _vc_sel_T_310)
node _vc_sel_T_318 = or(_vc_sel_T_317, _vc_sel_T_311)
node _vc_sel_T_319 = or(_vc_sel_T_318, _vc_sel_T_312)
node _vc_sel_T_320 = or(_vc_sel_T_319, _vc_sel_T_313)
node _vc_sel_T_321 = or(_vc_sel_T_320, _vc_sel_T_314)
node _vc_sel_T_322 = or(_vc_sel_T_321, _vc_sel_T_315)
wire _vc_sel_WIRE_23 : UInt<1>
connect _vc_sel_WIRE_23, _vc_sel_T_322
connect _vc_sel_WIRE_18[4], _vc_sel_WIRE_23
node _vc_sel_T_323 = mux(_vc_sel_T, states[0].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_324 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_325 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_326 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_327 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_328 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_329 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_330 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_331 = or(_vc_sel_T_323, _vc_sel_T_324)
node _vc_sel_T_332 = or(_vc_sel_T_331, _vc_sel_T_325)
node _vc_sel_T_333 = or(_vc_sel_T_332, _vc_sel_T_326)
node _vc_sel_T_334 = or(_vc_sel_T_333, _vc_sel_T_327)
node _vc_sel_T_335 = or(_vc_sel_T_334, _vc_sel_T_328)
node _vc_sel_T_336 = or(_vc_sel_T_335, _vc_sel_T_329)
node _vc_sel_T_337 = or(_vc_sel_T_336, _vc_sel_T_330)
wire _vc_sel_WIRE_24 : UInt<1>
connect _vc_sel_WIRE_24, _vc_sel_T_337
connect _vc_sel_WIRE_18[5], _vc_sel_WIRE_24
node _vc_sel_T_338 = mux(_vc_sel_T, states[0].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_339 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_340 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_341 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_342 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_343 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_344 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_345 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_346 = or(_vc_sel_T_338, _vc_sel_T_339)
node _vc_sel_T_347 = or(_vc_sel_T_346, _vc_sel_T_340)
node _vc_sel_T_348 = or(_vc_sel_T_347, _vc_sel_T_341)
node _vc_sel_T_349 = or(_vc_sel_T_348, _vc_sel_T_342)
node _vc_sel_T_350 = or(_vc_sel_T_349, _vc_sel_T_343)
node _vc_sel_T_351 = or(_vc_sel_T_350, _vc_sel_T_344)
node _vc_sel_T_352 = or(_vc_sel_T_351, _vc_sel_T_345)
wire _vc_sel_WIRE_25 : UInt<1>
connect _vc_sel_WIRE_25, _vc_sel_T_352
connect _vc_sel_WIRE_18[6], _vc_sel_WIRE_25
node _vc_sel_T_353 = mux(_vc_sel_T, states[0].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_354 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_355 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_356 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_357 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_358 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_359 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_360 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_361 = or(_vc_sel_T_353, _vc_sel_T_354)
node _vc_sel_T_362 = or(_vc_sel_T_361, _vc_sel_T_355)
node _vc_sel_T_363 = or(_vc_sel_T_362, _vc_sel_T_356)
node _vc_sel_T_364 = or(_vc_sel_T_363, _vc_sel_T_357)
node _vc_sel_T_365 = or(_vc_sel_T_364, _vc_sel_T_358)
node _vc_sel_T_366 = or(_vc_sel_T_365, _vc_sel_T_359)
node _vc_sel_T_367 = or(_vc_sel_T_366, _vc_sel_T_360)
wire _vc_sel_WIRE_26 : UInt<1>
connect _vc_sel_WIRE_26, _vc_sel_T_367
connect _vc_sel_WIRE_18[7], _vc_sel_WIRE_26
connect vc_sel.`2`, _vc_sel_WIRE_18
node _channel_oh_T = or(vc_sel.`0`[0], vc_sel.`0`[1])
node _channel_oh_T_1 = or(_channel_oh_T, vc_sel.`0`[2])
node _channel_oh_T_2 = or(_channel_oh_T_1, vc_sel.`0`[3])
node _channel_oh_T_3 = or(_channel_oh_T_2, vc_sel.`0`[4])
node _channel_oh_T_4 = or(_channel_oh_T_3, vc_sel.`0`[5])
node _channel_oh_T_5 = or(_channel_oh_T_4, vc_sel.`0`[6])
node channel_oh_0 = or(_channel_oh_T_5, vc_sel.`0`[7])
node _channel_oh_T_6 = or(vc_sel.`1`[0], vc_sel.`1`[1])
node _channel_oh_T_7 = or(_channel_oh_T_6, vc_sel.`1`[2])
node _channel_oh_T_8 = or(_channel_oh_T_7, vc_sel.`1`[3])
node _channel_oh_T_9 = or(_channel_oh_T_8, vc_sel.`1`[4])
node _channel_oh_T_10 = or(_channel_oh_T_9, vc_sel.`1`[5])
node _channel_oh_T_11 = or(_channel_oh_T_10, vc_sel.`1`[6])
node channel_oh_1 = or(_channel_oh_T_11, vc_sel.`1`[7])
node _channel_oh_T_12 = or(vc_sel.`2`[0], vc_sel.`2`[1])
node _channel_oh_T_13 = or(_channel_oh_T_12, vc_sel.`2`[2])
node _channel_oh_T_14 = or(_channel_oh_T_13, vc_sel.`2`[3])
node _channel_oh_T_15 = or(_channel_oh_T_14, vc_sel.`2`[4])
node _channel_oh_T_16 = or(_channel_oh_T_15, vc_sel.`2`[5])
node _channel_oh_T_17 = or(_channel_oh_T_16, vc_sel.`2`[6])
node channel_oh_2 = or(_channel_oh_T_17, vc_sel.`2`[7])
node virt_channel_lo_lo = cat(vc_sel.`0`[1], vc_sel.`0`[0])
node virt_channel_lo_hi = cat(vc_sel.`0`[3], vc_sel.`0`[2])
node virt_channel_lo = cat(virt_channel_lo_hi, virt_channel_lo_lo)
node virt_channel_hi_lo = cat(vc_sel.`0`[5], vc_sel.`0`[4])
node virt_channel_hi_hi = cat(vc_sel.`0`[7], vc_sel.`0`[6])
node virt_channel_hi = cat(virt_channel_hi_hi, virt_channel_hi_lo)
node _virt_channel_T = cat(virt_channel_hi, virt_channel_lo)
node virt_channel_hi_1 = bits(_virt_channel_T, 7, 4)
node virt_channel_lo_1 = bits(_virt_channel_T, 3, 0)
node _virt_channel_T_1 = orr(virt_channel_hi_1)
node _virt_channel_T_2 = or(virt_channel_hi_1, virt_channel_lo_1)
node virt_channel_hi_2 = bits(_virt_channel_T_2, 3, 2)
node virt_channel_lo_2 = bits(_virt_channel_T_2, 1, 0)
node _virt_channel_T_3 = orr(virt_channel_hi_2)
node _virt_channel_T_4 = or(virt_channel_hi_2, virt_channel_lo_2)
node _virt_channel_T_5 = bits(_virt_channel_T_4, 1, 1)
node _virt_channel_T_6 = cat(_virt_channel_T_3, _virt_channel_T_5)
node _virt_channel_T_7 = cat(_virt_channel_T_1, _virt_channel_T_6)
node virt_channel_lo_lo_1 = cat(vc_sel.`1`[1], vc_sel.`1`[0])
node virt_channel_lo_hi_1 = cat(vc_sel.`1`[3], vc_sel.`1`[2])
node virt_channel_lo_3 = cat(virt_channel_lo_hi_1, virt_channel_lo_lo_1)
node virt_channel_hi_lo_1 = cat(vc_sel.`1`[5], vc_sel.`1`[4])
node virt_channel_hi_hi_1 = cat(vc_sel.`1`[7], vc_sel.`1`[6])
node virt_channel_hi_3 = cat(virt_channel_hi_hi_1, virt_channel_hi_lo_1)
node _virt_channel_T_8 = cat(virt_channel_hi_3, virt_channel_lo_3)
node virt_channel_hi_4 = bits(_virt_channel_T_8, 7, 4)
node virt_channel_lo_4 = bits(_virt_channel_T_8, 3, 0)
node _virt_channel_T_9 = orr(virt_channel_hi_4)
node _virt_channel_T_10 = or(virt_channel_hi_4, virt_channel_lo_4)
node virt_channel_hi_5 = bits(_virt_channel_T_10, 3, 2)
node virt_channel_lo_5 = bits(_virt_channel_T_10, 1, 0)
node _virt_channel_T_11 = orr(virt_channel_hi_5)
node _virt_channel_T_12 = or(virt_channel_hi_5, virt_channel_lo_5)
node _virt_channel_T_13 = bits(_virt_channel_T_12, 1, 1)
node _virt_channel_T_14 = cat(_virt_channel_T_11, _virt_channel_T_13)
node _virt_channel_T_15 = cat(_virt_channel_T_9, _virt_channel_T_14)
node virt_channel_lo_lo_2 = cat(vc_sel.`2`[1], vc_sel.`2`[0])
node virt_channel_lo_hi_2 = cat(vc_sel.`2`[3], vc_sel.`2`[2])
node virt_channel_lo_6 = cat(virt_channel_lo_hi_2, virt_channel_lo_lo_2)
node virt_channel_hi_lo_2 = cat(vc_sel.`2`[5], vc_sel.`2`[4])
node virt_channel_hi_hi_2 = cat(vc_sel.`2`[7], vc_sel.`2`[6])
node virt_channel_hi_6 = cat(virt_channel_hi_hi_2, virt_channel_hi_lo_2)
node _virt_channel_T_16 = cat(virt_channel_hi_6, virt_channel_lo_6)
node virt_channel_hi_7 = bits(_virt_channel_T_16, 7, 4)
node virt_channel_lo_7 = bits(_virt_channel_T_16, 3, 0)
node _virt_channel_T_17 = orr(virt_channel_hi_7)
node _virt_channel_T_18 = or(virt_channel_hi_7, virt_channel_lo_7)
node virt_channel_hi_8 = bits(_virt_channel_T_18, 3, 2)
node virt_channel_lo_8 = bits(_virt_channel_T_18, 1, 0)
node _virt_channel_T_19 = orr(virt_channel_hi_8)
node _virt_channel_T_20 = or(virt_channel_hi_8, virt_channel_lo_8)
node _virt_channel_T_21 = bits(_virt_channel_T_20, 1, 1)
node _virt_channel_T_22 = cat(_virt_channel_T_19, _virt_channel_T_21)
node _virt_channel_T_23 = cat(_virt_channel_T_17, _virt_channel_T_22)
node _virt_channel_T_24 = mux(channel_oh_0, _virt_channel_T_7, UInt<1>(0h0))
node _virt_channel_T_25 = mux(channel_oh_1, _virt_channel_T_15, UInt<1>(0h0))
node _virt_channel_T_26 = mux(channel_oh_2, _virt_channel_T_23, UInt<1>(0h0))
node _virt_channel_T_27 = or(_virt_channel_T_24, _virt_channel_T_25)
node _virt_channel_T_28 = or(_virt_channel_T_27, _virt_channel_T_26)
wire virt_channel : UInt<3>
connect virt_channel, _virt_channel_T_28
node _T_95 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
when _T_95 :
connect salloc_outs[0].out_vid, virt_channel
node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_payload_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_payload_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_payload_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _salloc_outs_0_flit_payload_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _salloc_outs_0_flit_payload_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _salloc_outs_0_flit_payload_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
node _salloc_outs_0_flit_payload_T_8 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_9 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_10 = mux(_salloc_outs_0_flit_payload_T_2, input_buffer.io.deq[2].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_11 = mux(_salloc_outs_0_flit_payload_T_3, input_buffer.io.deq[3].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_12 = mux(_salloc_outs_0_flit_payload_T_4, input_buffer.io.deq[4].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_13 = mux(_salloc_outs_0_flit_payload_T_5, input_buffer.io.deq[5].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_14 = mux(_salloc_outs_0_flit_payload_T_6, input_buffer.io.deq[6].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_15 = mux(_salloc_outs_0_flit_payload_T_7, input_buffer.io.deq[7].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_16 = or(_salloc_outs_0_flit_payload_T_8, _salloc_outs_0_flit_payload_T_9)
node _salloc_outs_0_flit_payload_T_17 = or(_salloc_outs_0_flit_payload_T_16, _salloc_outs_0_flit_payload_T_10)
node _salloc_outs_0_flit_payload_T_18 = or(_salloc_outs_0_flit_payload_T_17, _salloc_outs_0_flit_payload_T_11)
node _salloc_outs_0_flit_payload_T_19 = or(_salloc_outs_0_flit_payload_T_18, _salloc_outs_0_flit_payload_T_12)
node _salloc_outs_0_flit_payload_T_20 = or(_salloc_outs_0_flit_payload_T_19, _salloc_outs_0_flit_payload_T_13)
node _salloc_outs_0_flit_payload_T_21 = or(_salloc_outs_0_flit_payload_T_20, _salloc_outs_0_flit_payload_T_14)
node _salloc_outs_0_flit_payload_T_22 = or(_salloc_outs_0_flit_payload_T_21, _salloc_outs_0_flit_payload_T_15)
wire _salloc_outs_0_flit_payload_WIRE : UInt<73>
connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_22
connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE
node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_head_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_head_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_head_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _salloc_outs_0_flit_head_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _salloc_outs_0_flit_head_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _salloc_outs_0_flit_head_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
node _salloc_outs_0_flit_head_T_8 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_9 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_10 = mux(_salloc_outs_0_flit_head_T_2, input_buffer.io.deq[2].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_11 = mux(_salloc_outs_0_flit_head_T_3, input_buffer.io.deq[3].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_12 = mux(_salloc_outs_0_flit_head_T_4, input_buffer.io.deq[4].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_13 = mux(_salloc_outs_0_flit_head_T_5, input_buffer.io.deq[5].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_14 = mux(_salloc_outs_0_flit_head_T_6, input_buffer.io.deq[6].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_15 = mux(_salloc_outs_0_flit_head_T_7, input_buffer.io.deq[7].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_16 = or(_salloc_outs_0_flit_head_T_8, _salloc_outs_0_flit_head_T_9)
node _salloc_outs_0_flit_head_T_17 = or(_salloc_outs_0_flit_head_T_16, _salloc_outs_0_flit_head_T_10)
node _salloc_outs_0_flit_head_T_18 = or(_salloc_outs_0_flit_head_T_17, _salloc_outs_0_flit_head_T_11)
node _salloc_outs_0_flit_head_T_19 = or(_salloc_outs_0_flit_head_T_18, _salloc_outs_0_flit_head_T_12)
node _salloc_outs_0_flit_head_T_20 = or(_salloc_outs_0_flit_head_T_19, _salloc_outs_0_flit_head_T_13)
node _salloc_outs_0_flit_head_T_21 = or(_salloc_outs_0_flit_head_T_20, _salloc_outs_0_flit_head_T_14)
node _salloc_outs_0_flit_head_T_22 = or(_salloc_outs_0_flit_head_T_21, _salloc_outs_0_flit_head_T_15)
wire _salloc_outs_0_flit_head_WIRE : UInt<1>
connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_22
connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE
node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_tail_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_tail_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_tail_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _salloc_outs_0_flit_tail_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _salloc_outs_0_flit_tail_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _salloc_outs_0_flit_tail_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
node _salloc_outs_0_flit_tail_T_8 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_9 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_10 = mux(_salloc_outs_0_flit_tail_T_2, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_11 = mux(_salloc_outs_0_flit_tail_T_3, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_12 = mux(_salloc_outs_0_flit_tail_T_4, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_13 = mux(_salloc_outs_0_flit_tail_T_5, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_14 = mux(_salloc_outs_0_flit_tail_T_6, input_buffer.io.deq[6].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_15 = mux(_salloc_outs_0_flit_tail_T_7, input_buffer.io.deq[7].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_16 = or(_salloc_outs_0_flit_tail_T_8, _salloc_outs_0_flit_tail_T_9)
node _salloc_outs_0_flit_tail_T_17 = or(_salloc_outs_0_flit_tail_T_16, _salloc_outs_0_flit_tail_T_10)
node _salloc_outs_0_flit_tail_T_18 = or(_salloc_outs_0_flit_tail_T_17, _salloc_outs_0_flit_tail_T_11)
node _salloc_outs_0_flit_tail_T_19 = or(_salloc_outs_0_flit_tail_T_18, _salloc_outs_0_flit_tail_T_12)
node _salloc_outs_0_flit_tail_T_20 = or(_salloc_outs_0_flit_tail_T_19, _salloc_outs_0_flit_tail_T_13)
node _salloc_outs_0_flit_tail_T_21 = or(_salloc_outs_0_flit_tail_T_20, _salloc_outs_0_flit_tail_T_14)
node _salloc_outs_0_flit_tail_T_22 = or(_salloc_outs_0_flit_tail_T_21, _salloc_outs_0_flit_tail_T_15)
wire _salloc_outs_0_flit_tail_WIRE : UInt<1>
connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_22
connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE
node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_flow_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_flow_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_flow_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _salloc_outs_0_flit_flow_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _salloc_outs_0_flit_flow_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _salloc_outs_0_flit_flow_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}
node _salloc_outs_0_flit_flow_T_8 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_9 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_10 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_11 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_12 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_13 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_15 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_16 = or(_salloc_outs_0_flit_flow_T_8, _salloc_outs_0_flit_flow_T_9)
node _salloc_outs_0_flit_flow_T_17 = or(_salloc_outs_0_flit_flow_T_16, _salloc_outs_0_flit_flow_T_10)
node _salloc_outs_0_flit_flow_T_18 = or(_salloc_outs_0_flit_flow_T_17, _salloc_outs_0_flit_flow_T_11)
node _salloc_outs_0_flit_flow_T_19 = or(_salloc_outs_0_flit_flow_T_18, _salloc_outs_0_flit_flow_T_12)
node _salloc_outs_0_flit_flow_T_20 = or(_salloc_outs_0_flit_flow_T_19, _salloc_outs_0_flit_flow_T_13)
node _salloc_outs_0_flit_flow_T_21 = or(_salloc_outs_0_flit_flow_T_20, _salloc_outs_0_flit_flow_T_14)
node _salloc_outs_0_flit_flow_T_22 = or(_salloc_outs_0_flit_flow_T_21, _salloc_outs_0_flit_flow_T_15)
wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<2>
connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_22
connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1
node _salloc_outs_0_flit_flow_T_23 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_24 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_25 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_26 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_27 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_28 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_29 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_30 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_31 = or(_salloc_outs_0_flit_flow_T_23, _salloc_outs_0_flit_flow_T_24)
node _salloc_outs_0_flit_flow_T_32 = or(_salloc_outs_0_flit_flow_T_31, _salloc_outs_0_flit_flow_T_25)
node _salloc_outs_0_flit_flow_T_33 = or(_salloc_outs_0_flit_flow_T_32, _salloc_outs_0_flit_flow_T_26)
node _salloc_outs_0_flit_flow_T_34 = or(_salloc_outs_0_flit_flow_T_33, _salloc_outs_0_flit_flow_T_27)
node _salloc_outs_0_flit_flow_T_35 = or(_salloc_outs_0_flit_flow_T_34, _salloc_outs_0_flit_flow_T_28)
node _salloc_outs_0_flit_flow_T_36 = or(_salloc_outs_0_flit_flow_T_35, _salloc_outs_0_flit_flow_T_29)
node _salloc_outs_0_flit_flow_T_37 = or(_salloc_outs_0_flit_flow_T_36, _salloc_outs_0_flit_flow_T_30)
wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<5>
connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_37
connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2
node _salloc_outs_0_flit_flow_T_38 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_39 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_40 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_41 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_42 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_43 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_44 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_45 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_46 = or(_salloc_outs_0_flit_flow_T_38, _salloc_outs_0_flit_flow_T_39)
node _salloc_outs_0_flit_flow_T_47 = or(_salloc_outs_0_flit_flow_T_46, _salloc_outs_0_flit_flow_T_40)
node _salloc_outs_0_flit_flow_T_48 = or(_salloc_outs_0_flit_flow_T_47, _salloc_outs_0_flit_flow_T_41)
node _salloc_outs_0_flit_flow_T_49 = or(_salloc_outs_0_flit_flow_T_48, _salloc_outs_0_flit_flow_T_42)
node _salloc_outs_0_flit_flow_T_50 = or(_salloc_outs_0_flit_flow_T_49, _salloc_outs_0_flit_flow_T_43)
node _salloc_outs_0_flit_flow_T_51 = or(_salloc_outs_0_flit_flow_T_50, _salloc_outs_0_flit_flow_T_44)
node _salloc_outs_0_flit_flow_T_52 = or(_salloc_outs_0_flit_flow_T_51, _salloc_outs_0_flit_flow_T_45)
wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<2>
connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_52
connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3
node _salloc_outs_0_flit_flow_T_53 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_54 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_55 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_56 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_57 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_58 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_59 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_60 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_61 = or(_salloc_outs_0_flit_flow_T_53, _salloc_outs_0_flit_flow_T_54)
node _salloc_outs_0_flit_flow_T_62 = or(_salloc_outs_0_flit_flow_T_61, _salloc_outs_0_flit_flow_T_55)
node _salloc_outs_0_flit_flow_T_63 = or(_salloc_outs_0_flit_flow_T_62, _salloc_outs_0_flit_flow_T_56)
node _salloc_outs_0_flit_flow_T_64 = or(_salloc_outs_0_flit_flow_T_63, _salloc_outs_0_flit_flow_T_57)
node _salloc_outs_0_flit_flow_T_65 = or(_salloc_outs_0_flit_flow_T_64, _salloc_outs_0_flit_flow_T_58)
node _salloc_outs_0_flit_flow_T_66 = or(_salloc_outs_0_flit_flow_T_65, _salloc_outs_0_flit_flow_T_59)
node _salloc_outs_0_flit_flow_T_67 = or(_salloc_outs_0_flit_flow_T_66, _salloc_outs_0_flit_flow_T_60)
wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<5>
connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_67
connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4
node _salloc_outs_0_flit_flow_T_68 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_69 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_70 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_71 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_72 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_73 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_74 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_75 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_76 = or(_salloc_outs_0_flit_flow_T_68, _salloc_outs_0_flit_flow_T_69)
node _salloc_outs_0_flit_flow_T_77 = or(_salloc_outs_0_flit_flow_T_76, _salloc_outs_0_flit_flow_T_70)
node _salloc_outs_0_flit_flow_T_78 = or(_salloc_outs_0_flit_flow_T_77, _salloc_outs_0_flit_flow_T_71)
node _salloc_outs_0_flit_flow_T_79 = or(_salloc_outs_0_flit_flow_T_78, _salloc_outs_0_flit_flow_T_72)
node _salloc_outs_0_flit_flow_T_80 = or(_salloc_outs_0_flit_flow_T_79, _salloc_outs_0_flit_flow_T_73)
node _salloc_outs_0_flit_flow_T_81 = or(_salloc_outs_0_flit_flow_T_80, _salloc_outs_0_flit_flow_T_74)
node _salloc_outs_0_flit_flow_T_82 = or(_salloc_outs_0_flit_flow_T_81, _salloc_outs_0_flit_flow_T_75)
wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<3>
connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_82
connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5
connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE
else :
invalidate salloc_outs[0].out_vid
invalidate salloc_outs[0].flit.virt_channel_id
invalidate salloc_outs[0].flit.flow.egress_node_id
invalidate salloc_outs[0].flit.flow.egress_node
invalidate salloc_outs[0].flit.flow.ingress_node_id
invalidate salloc_outs[0].flit.flow.ingress_node
invalidate salloc_outs[0].flit.flow.vnet_id
invalidate salloc_outs[0].flit.payload
invalidate salloc_outs[0].flit.tail
invalidate salloc_outs[0].flit.head
invalidate salloc_outs[0].flit.virt_channel_id
connect io.out[0].valid, salloc_outs[0].valid
connect io.out[0].bits.flit, salloc_outs[0].flit
connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid
invalidate states[0].fifo_deps
invalidate states[0].flow.egress_node_id
invalidate states[0].flow.egress_node
invalidate states[0].flow.ingress_node_id
invalidate states[0].flow.ingress_node
invalidate states[0].flow.vnet_id
invalidate states[0].vc_sel.`0`[0]
invalidate states[0].vc_sel.`0`[1]
invalidate states[0].vc_sel.`0`[2]
invalidate states[0].vc_sel.`0`[3]
invalidate states[0].vc_sel.`0`[4]
invalidate states[0].vc_sel.`0`[5]
invalidate states[0].vc_sel.`0`[6]
invalidate states[0].vc_sel.`0`[7]
invalidate states[0].vc_sel.`1`[0]
invalidate states[0].vc_sel.`1`[1]
invalidate states[0].vc_sel.`1`[2]
invalidate states[0].vc_sel.`1`[3]
invalidate states[0].vc_sel.`1`[4]
invalidate states[0].vc_sel.`1`[5]
invalidate states[0].vc_sel.`1`[6]
invalidate states[0].vc_sel.`1`[7]
invalidate states[0].vc_sel.`2`[0]
invalidate states[0].vc_sel.`2`[1]
invalidate states[0].vc_sel.`2`[2]
invalidate states[0].vc_sel.`2`[3]
invalidate states[0].vc_sel.`2`[4]
invalidate states[0].vc_sel.`2`[5]
invalidate states[0].vc_sel.`2`[6]
invalidate states[0].vc_sel.`2`[7]
invalidate states[0].g
invalidate states[1].fifo_deps
invalidate states[1].flow.egress_node_id
invalidate states[1].flow.egress_node
invalidate states[1].flow.ingress_node_id
invalidate states[1].flow.ingress_node
invalidate states[1].flow.vnet_id
invalidate states[1].vc_sel.`0`[0]
invalidate states[1].vc_sel.`0`[1]
invalidate states[1].vc_sel.`0`[2]
invalidate states[1].vc_sel.`0`[3]
invalidate states[1].vc_sel.`0`[4]
invalidate states[1].vc_sel.`0`[5]
invalidate states[1].vc_sel.`0`[6]
invalidate states[1].vc_sel.`0`[7]
invalidate states[1].vc_sel.`1`[0]
invalidate states[1].vc_sel.`1`[1]
invalidate states[1].vc_sel.`1`[2]
invalidate states[1].vc_sel.`1`[3]
invalidate states[1].vc_sel.`1`[4]
invalidate states[1].vc_sel.`1`[5]
invalidate states[1].vc_sel.`1`[6]
invalidate states[1].vc_sel.`1`[7]
invalidate states[1].vc_sel.`2`[0]
invalidate states[1].vc_sel.`2`[1]
invalidate states[1].vc_sel.`2`[2]
invalidate states[1].vc_sel.`2`[3]
invalidate states[1].vc_sel.`2`[4]
invalidate states[1].vc_sel.`2`[5]
invalidate states[1].vc_sel.`2`[6]
invalidate states[1].vc_sel.`2`[7]
invalidate states[1].g
invalidate states[2].fifo_deps
invalidate states[2].flow.egress_node_id
invalidate states[2].flow.egress_node
invalidate states[2].flow.ingress_node_id
invalidate states[2].flow.ingress_node
invalidate states[2].flow.vnet_id
invalidate states[2].vc_sel.`0`[0]
invalidate states[2].vc_sel.`0`[1]
invalidate states[2].vc_sel.`0`[2]
invalidate states[2].vc_sel.`0`[3]
invalidate states[2].vc_sel.`0`[4]
invalidate states[2].vc_sel.`0`[5]
invalidate states[2].vc_sel.`0`[6]
invalidate states[2].vc_sel.`0`[7]
invalidate states[2].vc_sel.`1`[0]
invalidate states[2].vc_sel.`1`[1]
invalidate states[2].vc_sel.`1`[2]
invalidate states[2].vc_sel.`1`[3]
invalidate states[2].vc_sel.`1`[4]
invalidate states[2].vc_sel.`1`[5]
invalidate states[2].vc_sel.`1`[6]
invalidate states[2].vc_sel.`1`[7]
invalidate states[2].vc_sel.`2`[0]
invalidate states[2].vc_sel.`2`[1]
invalidate states[2].vc_sel.`2`[2]
invalidate states[2].vc_sel.`2`[3]
invalidate states[2].vc_sel.`2`[4]
invalidate states[2].vc_sel.`2`[5]
invalidate states[2].vc_sel.`2`[6]
invalidate states[2].vc_sel.`2`[7]
invalidate states[2].g
invalidate states[3].fifo_deps
invalidate states[3].flow.egress_node_id
invalidate states[3].flow.egress_node
invalidate states[3].flow.ingress_node_id
invalidate states[3].flow.ingress_node
invalidate states[3].flow.vnet_id
invalidate states[3].vc_sel.`0`[0]
invalidate states[3].vc_sel.`0`[1]
invalidate states[3].vc_sel.`0`[2]
invalidate states[3].vc_sel.`0`[3]
invalidate states[3].vc_sel.`0`[4]
invalidate states[3].vc_sel.`0`[5]
invalidate states[3].vc_sel.`0`[6]
invalidate states[3].vc_sel.`0`[7]
invalidate states[3].vc_sel.`1`[0]
invalidate states[3].vc_sel.`1`[1]
invalidate states[3].vc_sel.`1`[2]
invalidate states[3].vc_sel.`1`[3]
invalidate states[3].vc_sel.`1`[4]
invalidate states[3].vc_sel.`1`[5]
invalidate states[3].vc_sel.`1`[6]
invalidate states[3].vc_sel.`1`[7]
invalidate states[3].vc_sel.`2`[0]
invalidate states[3].vc_sel.`2`[1]
invalidate states[3].vc_sel.`2`[2]
invalidate states[3].vc_sel.`2`[3]
invalidate states[3].vc_sel.`2`[4]
invalidate states[3].vc_sel.`2`[5]
invalidate states[3].vc_sel.`2`[6]
invalidate states[3].vc_sel.`2`[7]
invalidate states[3].g
connect states[4].vc_sel.`0`[0], UInt<1>(0h0)
connect states[4].vc_sel.`0`[1], UInt<1>(0h0)
connect states[4].vc_sel.`0`[2], UInt<1>(0h0)
connect states[4].vc_sel.`0`[3], UInt<1>(0h0)
connect states[4].vc_sel.`1`[0], UInt<1>(0h0)
connect states[4].vc_sel.`1`[1], UInt<1>(0h0)
connect states[4].vc_sel.`1`[2], UInt<1>(0h0)
connect states[4].vc_sel.`1`[3], UInt<1>(0h0)
connect states[4].vc_sel.`1`[4], UInt<1>(0h0)
connect states[4].vc_sel.`1`[5], UInt<1>(0h0)
connect states[4].vc_sel.`1`[6], UInt<1>(0h0)
connect states[4].vc_sel.`1`[7], UInt<1>(0h0)
connect states[4].vc_sel.`2`[0], UInt<1>(0h0)
connect states[4].vc_sel.`2`[1], UInt<1>(0h0)
connect states[4].vc_sel.`2`[2], UInt<1>(0h0)
connect states[4].vc_sel.`2`[3], UInt<1>(0h0)
connect states[4].vc_sel.`2`[4], UInt<1>(0h0)
connect states[4].vc_sel.`2`[5], UInt<1>(0h0)
connect states[4].vc_sel.`2`[6], UInt<1>(0h0)
connect states[4].vc_sel.`2`[7], UInt<1>(0h0)
connect states[5].vc_sel.`0`[0], UInt<1>(0h0)
connect states[5].vc_sel.`0`[1], UInt<1>(0h0)
connect states[5].vc_sel.`0`[2], UInt<1>(0h0)
connect states[5].vc_sel.`0`[3], UInt<1>(0h0)
connect states[5].vc_sel.`1`[0], UInt<1>(0h0)
connect states[5].vc_sel.`1`[1], UInt<1>(0h0)
connect states[5].vc_sel.`1`[2], UInt<1>(0h0)
connect states[5].vc_sel.`1`[3], UInt<1>(0h0)
connect states[5].vc_sel.`1`[4], UInt<1>(0h0)
connect states[5].vc_sel.`1`[5], UInt<1>(0h0)
connect states[5].vc_sel.`1`[6], UInt<1>(0h0)
connect states[5].vc_sel.`1`[7], UInt<1>(0h0)
connect states[5].vc_sel.`2`[0], UInt<1>(0h0)
connect states[5].vc_sel.`2`[1], UInt<1>(0h0)
connect states[5].vc_sel.`2`[2], UInt<1>(0h0)
connect states[5].vc_sel.`2`[3], UInt<1>(0h0)
connect states[5].vc_sel.`2`[4], UInt<1>(0h0)
connect states[5].vc_sel.`2`[5], UInt<1>(0h0)
connect states[5].vc_sel.`2`[6], UInt<1>(0h0)
connect states[5].vc_sel.`2`[7], UInt<1>(0h0)
connect states[6].vc_sel.`0`[0], UInt<1>(0h0)
connect states[6].vc_sel.`0`[1], UInt<1>(0h0)
connect states[6].vc_sel.`0`[2], UInt<1>(0h0)
connect states[6].vc_sel.`0`[3], UInt<1>(0h0)
connect states[6].vc_sel.`1`[0], UInt<1>(0h0)
connect states[6].vc_sel.`1`[1], UInt<1>(0h0)
connect states[6].vc_sel.`1`[2], UInt<1>(0h0)
connect states[6].vc_sel.`1`[3], UInt<1>(0h0)
connect states[6].vc_sel.`1`[4], UInt<1>(0h0)
connect states[6].vc_sel.`1`[5], UInt<1>(0h0)
connect states[6].vc_sel.`1`[6], UInt<1>(0h0)
connect states[6].vc_sel.`1`[7], UInt<1>(0h0)
connect states[6].vc_sel.`2`[0], UInt<1>(0h0)
connect states[6].vc_sel.`2`[1], UInt<1>(0h0)
connect states[6].vc_sel.`2`[2], UInt<1>(0h0)
connect states[6].vc_sel.`2`[3], UInt<1>(0h0)
connect states[6].vc_sel.`2`[4], UInt<1>(0h0)
connect states[6].vc_sel.`2`[5], UInt<1>(0h0)
connect states[6].vc_sel.`2`[6], UInt<1>(0h0)
connect states[6].vc_sel.`2`[7], UInt<1>(0h0)
connect states[7].vc_sel.`0`[0], UInt<1>(0h0)
connect states[7].vc_sel.`0`[1], UInt<1>(0h0)
connect states[7].vc_sel.`0`[2], UInt<1>(0h0)
connect states[7].vc_sel.`0`[3], UInt<1>(0h0)
connect states[7].vc_sel.`1`[0], UInt<1>(0h0)
connect states[7].vc_sel.`1`[1], UInt<1>(0h0)
connect states[7].vc_sel.`1`[2], UInt<1>(0h0)
connect states[7].vc_sel.`1`[3], UInt<1>(0h0)
connect states[7].vc_sel.`1`[4], UInt<1>(0h0)
connect states[7].vc_sel.`1`[5], UInt<1>(0h0)
connect states[7].vc_sel.`1`[6], UInt<1>(0h0)
connect states[7].vc_sel.`1`[7], UInt<1>(0h0)
connect states[7].vc_sel.`2`[0], UInt<1>(0h0)
connect states[7].vc_sel.`2`[1], UInt<1>(0h0)
connect states[7].vc_sel.`2`[2], UInt<1>(0h0)
connect states[7].vc_sel.`2`[3], UInt<1>(0h0)
connect states[7].vc_sel.`2`[4], UInt<1>(0h0)
connect states[7].vc_sel.`2`[5], UInt<1>(0h0)
connect states[7].vc_sel.`2`[6], UInt<1>(0h0)
connect states[7].vc_sel.`2`[7], UInt<1>(0h0)
node _T_96 = asUInt(reset)
when _T_96 :
connect states[0].g, UInt<3>(0h0)
connect states[1].g, UInt<3>(0h0)
connect states[2].g, UInt<3>(0h0)
connect states[3].g, UInt<3>(0h0)
connect states[4].g, UInt<3>(0h0)
connect states[5].g, UInt<3>(0h0)
connect states[6].g, UInt<3>(0h0)
connect states[7].g, UInt<3>(0h0) | module InputUnit_26( // @[InputUnit.scala:158:7]
input clock, // @[InputUnit.scala:158:7]
input reset, // @[InputUnit.scala:158:7]
output [2:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14]
output [2:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
output [4:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
output [1:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [4:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14]
output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_4, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_5, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_6, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_7, // @[InputUnit.scala:170:14]
input io_vcalloc_req_ready, // @[InputUnit.scala:170:14]
output io_vcalloc_req_valid, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_4, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_5, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_6, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_7, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_4, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_5, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_6, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_7, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_2, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_3, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_4, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_5, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_6, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_7, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_2, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_3, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_4, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_5, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_6, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_7, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_4, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_5, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_6, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_7, // @[InputUnit.scala:170:14]
input io_salloc_req_0_ready, // @[InputUnit.scala:170:14]
output io_salloc_req_0_valid, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_3, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_4, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_5, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_6, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_7, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_3, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_4, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_5, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_6, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_7, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_3, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_4, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_5, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_6, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_7, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14]
output io_out_0_valid, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14]
output [72:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14]
output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14]
output [4:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [4:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14]
output [2:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14]
output [2:0] io_debug_va_stall, // @[InputUnit.scala:170:14]
output [2:0] io_debug_sa_stall, // @[InputUnit.scala:170:14]
input io_in_flit_0_valid, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14]
input [72:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14]
input [2:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
input [4:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input [2:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14]
output [7:0] io_in_credit_return, // @[InputUnit.scala:170:14]
output [7:0] io_in_vc_free // @[InputUnit.scala:170:14]
);
wire vcalloc_vals_7; // @[InputUnit.scala:266:32]
wire vcalloc_vals_6; // @[InputUnit.scala:266:32]
wire vcalloc_vals_5; // @[InputUnit.scala:266:32]
wire vcalloc_vals_4; // @[InputUnit.scala:266:32]
wire _salloc_arb_io_in_4_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_5_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_6_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_7_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26]
wire [7:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26]
wire _route_arbiter_io_in_4_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_5_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_6_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_7_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29]
wire [2:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29]
wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_4_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_5_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_5_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_5_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_5_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_6_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_6_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_6_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_6_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_7_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_7_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_7_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_7_bits_payload; // @[InputUnit.scala:181:28]
reg [2:0] states_4_g; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_0_4; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_0_5; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_0_6; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_0_7; // @[InputUnit.scala:192:19]
reg [2:0] states_4_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_4_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_4_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_4_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_4_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_5_g; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_0_4; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_0_5; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_0_6; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_0_7; // @[InputUnit.scala:192:19]
reg [2:0] states_5_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_5_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_5_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_5_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_5_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_6_g; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_0_4; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_0_5; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_0_6; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_0_7; // @[InputUnit.scala:192:19]
reg [2:0] states_6_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_6_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_6_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_6_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_6_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_7_g; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_0_4; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_0_5; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_0_6; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_0_7; // @[InputUnit.scala:192:19]
reg [2:0] states_7_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_7_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_7_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_7_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_7_flow_egress_node_id; // @[InputUnit.scala:192:19]
wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30]
wire route_arbiter_io_in_4_valid = states_4_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_5_valid = states_5_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_6_valid = states_6_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_7_valid = states_7_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
reg [7:0] mask; // @[InputUnit.scala:250:21]
wire [7:0] _vcalloc_filter_T_3 = {vcalloc_vals_7, vcalloc_vals_6, vcalloc_vals_5, vcalloc_vals_4, 4'h0} & ~mask; // @[InputUnit.scala:250:21, :253:{80,87,89}, :266:32]
wire [15:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 16'h1 : _vcalloc_filter_T_3[1] ? 16'h2 : _vcalloc_filter_T_3[2] ? 16'h4 : _vcalloc_filter_T_3[3] ? 16'h8 : _vcalloc_filter_T_3[4] ? 16'h10 : _vcalloc_filter_T_3[5] ? 16'h20 : _vcalloc_filter_T_3[6] ? 16'h40 : _vcalloc_filter_T_3[7] ? 16'h80 : vcalloc_vals_4 ? 16'h1000 : vcalloc_vals_5 ? 16'h2000 : vcalloc_vals_6 ? 16'h4000 : {vcalloc_vals_7, 15'h0}; // @[OneHot.scala:85:71]
wire [7:0] vcalloc_sel = vcalloc_filter[7:0] | vcalloc_filter[15:8]; // @[Mux.scala:50:70]
wire io_vcalloc_req_valid_0 = vcalloc_vals_4 | vcalloc_vals_5 | vcalloc_vals_6 | vcalloc_vals_7; // @[package.scala:81:59]
assign vcalloc_vals_4 = states_4_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_5 = states_5_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_6 = states_6_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_7 = states_7_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
wire _GEN_0 = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]
wire _GEN_1 = _GEN_0 & vcalloc_sel[4]; // @[Mux.scala:32:36]
wire _GEN_2 = _GEN_0 & vcalloc_sel[5]; // @[Mux.scala:32:36]
wire _GEN_3 = _GEN_0 & vcalloc_sel[6]; // @[Mux.scala:32:36]
wire _GEN_4 = _GEN_0 & vcalloc_sel[7]; // @[Mux.scala:32:36] |
Generate the Verilog code corresponding to this FIRRTL code module PE_327 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>}
inst mac_unit of MacUnit_71
connect mac_unit.clock, clock
connect mac_unit.reset, reset
reg c1 : SInt<8>, clock
reg c2 : SInt<8>, clock
connect io.out_a, io.in_a
connect io.out_control.dataflow, io.in_control.dataflow
connect io.out_control.propagate, io.in_control.propagate
connect io.out_control.shift, io.in_control.shift
connect io.out_id, io.in_id
connect io.out_last, io.in_last
connect io.out_valid, io.in_valid
connect mac_unit.io.in_a, io.in_a
reg last_s : UInt<1>, clock
when io.in_valid :
connect last_s, io.in_control.propagate
node flip = neq(last_s, io.in_control.propagate)
node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0))
connect io.bad_dataflow, UInt<1>(0h0)
node _T = eq(io.in_control.dataflow, UInt<1>(0h0))
node _T_1 = and(UInt<1>(0h0), _T)
node _T_2 = or(UInt<1>(0h0), _T_1)
when _T_2 :
node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_3 :
node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1)
node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2)
node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0)
node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4)
node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_1 = asUInt(c1)
node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1)
node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3)
node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1))
node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1)
node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6)
node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7)
node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0))
node _io_out_c_ones_digit_T = dshr(c1, shift_offset)
node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0)
node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit)
node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T)
node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0)
node _io_out_c_T = dshr(c1, shift_offset)
node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1)
node _io_out_c_T_3 = tail(_io_out_c_T_2, 1)
node _io_out_c_T_4 = asSInt(_io_out_c_T_3)
node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4)
node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7)
node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0)
node _io_out_c_T_10 = asSInt(_io_out_c_T_9)
connect io.out_c, _io_out_c_T_10
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE : SInt<8>
node _mac_unit_io_in_b_T = asUInt(io.in_b)
node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T)
connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE
connect mac_unit.io.in_c, c2
connect c2, mac_unit.io.out_d
node _c1_T = bits(io.in_d, 7, 0)
node _c1_T_1 = asSInt(_c1_T)
connect c1, _c1_T_1
else :
node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1)
node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7)
node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0)
node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9)
node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_10 = asUInt(c2)
node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1)
node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12)
node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1))
node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1)
node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15)
node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16)
node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0))
node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset)
node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0)
node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1)
node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2)
node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0)
node _io_out_c_T_11 = dshr(c2, shift_offset)
node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12)
node _io_out_c_T_14 = tail(_io_out_c_T_13, 1)
node _io_out_c_T_15 = asSInt(_io_out_c_T_14)
node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15)
node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18)
node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0)
node _io_out_c_T_21 = asSInt(_io_out_c_T_20)
connect io.out_c, _io_out_c_T_21
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE_1 : SInt<8>
node _mac_unit_io_in_b_T_2 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2)
connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1
connect mac_unit.io.in_c, c1
connect c1, mac_unit.io.out_d
node _c2_T = bits(io.in_d, 7, 0)
node _c2_T_1 = asSInt(_c2_T)
connect c2, _c2_T_1
else :
node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1))
node _T_5 = and(UInt<1>(0h0), _T_4)
node _T_6 = or(UInt<1>(0h1), _T_5)
when _T_6 :
node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_7 :
connect io.out_c, c1
wire _mac_unit_io_in_b_WIRE_2 : SInt<8>
node _mac_unit_io_in_b_T_4 = asUInt(c2)
node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4)
connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c1, io.in_d
else :
connect io.out_c, c2
wire _mac_unit_io_in_b_WIRE_3 : SInt<8>
node _mac_unit_io_in_b_T_6 = asUInt(c1)
node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6)
connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c2, io.in_d
else :
connect io.bad_dataflow, UInt<1>(0h1)
invalidate io.out_c
invalidate io.out_b
wire _mac_unit_io_in_b_WIRE_4 : SInt<8>
node _mac_unit_io_in_b_T_8 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8)
connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4
connect mac_unit.io.in_c, c2
node _T_8 = eq(io.in_valid, UInt<1>(0h0))
when _T_8 :
connect c1, c1
connect c2, c2
invalidate mac_unit.io.in_b
invalidate mac_unit.io.in_c | module PE_327( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid // @[PE.scala:35:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7]
wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60]
wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [7:0] c1; // @[PE.scala:70:15]
wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [7:0] c2; // @[PE.scala:71:15]
wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25]
wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}]
wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16]
wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8]
c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15]
if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8]
c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15]
if (io_in_valid_0) // @[PE.scala:31:7]
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
always @(posedge)
MacUnit_71 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_b_0), // @[PE.scala:31:7]
.io_out_d (io_out_b_0)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_26 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0)
node _source_ok_T_25 = shr(io.in.a.bits.source, 2)
node _source_ok_T_26 = eq(_source_ok_T_25, UInt<4>(0ha))
node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27)
node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<2>(0h2))
node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29)
node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<6>(0h2b))
node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0)
node _source_ok_T_33 = shr(io.in.a.bits.source, 2)
node _source_ok_T_34 = eq(_source_ok_T_33, UInt<4>(0h8))
node _source_ok_T_35 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_36 = and(_source_ok_T_34, _source_ok_T_35)
node _source_ok_T_37 = leq(source_ok_uncommonBits_5, UInt<2>(0h2))
node _source_ok_T_38 = and(_source_ok_T_36, _source_ok_T_37)
node _source_ok_T_39 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _source_ok_T_40 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _source_ok_T_41 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE : UInt<1>[12]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_30
connect _source_ok_WIRE[6], _source_ok_T_31
connect _source_ok_WIRE[7], _source_ok_T_32
connect _source_ok_WIRE[8], _source_ok_T_38
connect _source_ok_WIRE[9], _source_ok_T_39
connect _source_ok_WIRE[10], _source_ok_T_40
connect _source_ok_WIRE[11], _source_ok_T_41
node _source_ok_T_42 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_43 = or(_source_ok_T_42, _source_ok_WIRE[2])
node _source_ok_T_44 = or(_source_ok_T_43, _source_ok_WIRE[3])
node _source_ok_T_45 = or(_source_ok_T_44, _source_ok_WIRE[4])
node _source_ok_T_46 = or(_source_ok_T_45, _source_ok_WIRE[5])
node _source_ok_T_47 = or(_source_ok_T_46, _source_ok_WIRE[6])
node _source_ok_T_48 = or(_source_ok_T_47, _source_ok_WIRE[7])
node _source_ok_T_49 = or(_source_ok_T_48, _source_ok_WIRE[8])
node _source_ok_T_50 = or(_source_ok_T_49, _source_ok_WIRE[9])
node _source_ok_T_51 = or(_source_ok_T_50, _source_ok_WIRE[10])
node source_ok = or(_source_ok_T_51, _source_ok_WIRE[11])
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<1>(0h0))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<1>(0h1))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<2>(0h2))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<2>(0h3))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0)
node _T_64 = shr(io.in.a.bits.source, 2)
node _T_65 = eq(_T_64, UInt<4>(0ha))
node _T_66 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_67 = and(_T_65, _T_66)
node _T_68 = leq(uncommonBits_4, UInt<2>(0h2))
node _T_69 = and(_T_67, _T_68)
node _T_70 = eq(_T_69, UInt<1>(0h0))
node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_72 = cvt(_T_71)
node _T_73 = and(_T_72, asSInt(UInt<1>(0h0)))
node _T_74 = asSInt(_T_73)
node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0)))
node _T_76 = or(_T_70, _T_75)
node _T_77 = eq(io.in.a.bits.source, UInt<6>(0h2b))
node _T_78 = eq(_T_77, UInt<1>(0h0))
node _T_79 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_80 = cvt(_T_79)
node _T_81 = and(_T_80, asSInt(UInt<1>(0h0)))
node _T_82 = asSInt(_T_81)
node _T_83 = eq(_T_82, asSInt(UInt<1>(0h0)))
node _T_84 = or(_T_78, _T_83)
node _T_85 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_86 = eq(_T_85, UInt<1>(0h0))
node _T_87 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_88 = cvt(_T_87)
node _T_89 = and(_T_88, asSInt(UInt<1>(0h0)))
node _T_90 = asSInt(_T_89)
node _T_91 = eq(_T_90, asSInt(UInt<1>(0h0)))
node _T_92 = or(_T_86, _T_91)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0)
node _T_93 = shr(io.in.a.bits.source, 2)
node _T_94 = eq(_T_93, UInt<4>(0h8))
node _T_95 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_96 = and(_T_94, _T_95)
node _T_97 = leq(uncommonBits_5, UInt<2>(0h2))
node _T_98 = and(_T_96, _T_97)
node _T_99 = eq(_T_98, UInt<1>(0h0))
node _T_100 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_101 = cvt(_T_100)
node _T_102 = and(_T_101, asSInt(UInt<1>(0h0)))
node _T_103 = asSInt(_T_102)
node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0)))
node _T_105 = or(_T_99, _T_104)
node _T_106 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _T_107 = eq(_T_106, UInt<1>(0h0))
node _T_108 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_109 = cvt(_T_108)
node _T_110 = and(_T_109, asSInt(UInt<1>(0h0)))
node _T_111 = asSInt(_T_110)
node _T_112 = eq(_T_111, asSInt(UInt<1>(0h0)))
node _T_113 = or(_T_107, _T_112)
node _T_114 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_115 = eq(_T_114, UInt<1>(0h0))
node _T_116 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_117 = cvt(_T_116)
node _T_118 = and(_T_117, asSInt(UInt<1>(0h0)))
node _T_119 = asSInt(_T_118)
node _T_120 = eq(_T_119, asSInt(UInt<1>(0h0)))
node _T_121 = or(_T_115, _T_120)
node _T_122 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_123 = eq(_T_122, UInt<1>(0h0))
node _T_124 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_125 = cvt(_T_124)
node _T_126 = and(_T_125, asSInt(UInt<1>(0h0)))
node _T_127 = asSInt(_T_126)
node _T_128 = eq(_T_127, asSInt(UInt<1>(0h0)))
node _T_129 = or(_T_123, _T_128)
node _T_130 = and(_T_11, _T_24)
node _T_131 = and(_T_130, _T_37)
node _T_132 = and(_T_131, _T_50)
node _T_133 = and(_T_132, _T_63)
node _T_134 = and(_T_133, _T_76)
node _T_135 = and(_T_134, _T_84)
node _T_136 = and(_T_135, _T_92)
node _T_137 = and(_T_136, _T_105)
node _T_138 = and(_T_137, _T_113)
node _T_139 = and(_T_138, _T_121)
node _T_140 = and(_T_139, _T_129)
node _T_141 = asUInt(reset)
node _T_142 = eq(_T_141, UInt<1>(0h0))
when _T_142 :
node _T_143 = eq(_T_140, UInt<1>(0h0))
when _T_143 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_140, UInt<1>(0h1), "") : assert_1
node _T_144 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_144 :
node _T_145 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_146 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_147 = and(_T_145, _T_146)
node _T_148 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_149 = shr(io.in.a.bits.source, 2)
node _T_150 = eq(_T_149, UInt<1>(0h0))
node _T_151 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_152 = and(_T_150, _T_151)
node _T_153 = leq(uncommonBits_6, UInt<2>(0h3))
node _T_154 = and(_T_152, _T_153)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_155 = shr(io.in.a.bits.source, 2)
node _T_156 = eq(_T_155, UInt<1>(0h1))
node _T_157 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_158 = and(_T_156, _T_157)
node _T_159 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_160 = and(_T_158, _T_159)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_161 = shr(io.in.a.bits.source, 2)
node _T_162 = eq(_T_161, UInt<2>(0h2))
node _T_163 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_164 = and(_T_162, _T_163)
node _T_165 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_166 = and(_T_164, _T_165)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_167 = shr(io.in.a.bits.source, 2)
node _T_168 = eq(_T_167, UInt<2>(0h3))
node _T_169 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_170 = and(_T_168, _T_169)
node _T_171 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_172 = and(_T_170, _T_171)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0)
node _T_173 = shr(io.in.a.bits.source, 2)
node _T_174 = eq(_T_173, UInt<4>(0ha))
node _T_175 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_176 = and(_T_174, _T_175)
node _T_177 = leq(uncommonBits_10, UInt<2>(0h2))
node _T_178 = and(_T_176, _T_177)
node _T_179 = eq(io.in.a.bits.source, UInt<6>(0h2b))
node _T_180 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0)
node _T_181 = shr(io.in.a.bits.source, 2)
node _T_182 = eq(_T_181, UInt<4>(0h8))
node _T_183 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_184 = and(_T_182, _T_183)
node _T_185 = leq(uncommonBits_11, UInt<2>(0h2))
node _T_186 = and(_T_184, _T_185)
node _T_187 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _T_188 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_189 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_190 = or(_T_148, _T_154)
node _T_191 = or(_T_190, _T_160)
node _T_192 = or(_T_191, _T_166)
node _T_193 = or(_T_192, _T_172)
node _T_194 = or(_T_193, _T_178)
node _T_195 = or(_T_194, _T_179)
node _T_196 = or(_T_195, _T_180)
node _T_197 = or(_T_196, _T_186)
node _T_198 = or(_T_197, _T_187)
node _T_199 = or(_T_198, _T_188)
node _T_200 = or(_T_199, _T_189)
node _T_201 = and(_T_147, _T_200)
node _T_202 = or(UInt<1>(0h0), _T_201)
node _T_203 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_204 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_205 = cvt(_T_204)
node _T_206 = and(_T_205, asSInt(UInt<13>(0h1000)))
node _T_207 = asSInt(_T_206)
node _T_208 = eq(_T_207, asSInt(UInt<1>(0h0)))
node _T_209 = and(_T_203, _T_208)
node _T_210 = or(UInt<1>(0h0), _T_209)
node _T_211 = and(_T_202, _T_210)
node _T_212 = asUInt(reset)
node _T_213 = eq(_T_212, UInt<1>(0h0))
when _T_213 :
node _T_214 = eq(_T_211, UInt<1>(0h0))
when _T_214 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_211, UInt<1>(0h1), "") : assert_2
node _T_215 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_216 = shr(io.in.a.bits.source, 2)
node _T_217 = eq(_T_216, UInt<1>(0h0))
node _T_218 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_219 = and(_T_217, _T_218)
node _T_220 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_221 = and(_T_219, _T_220)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_222 = shr(io.in.a.bits.source, 2)
node _T_223 = eq(_T_222, UInt<1>(0h1))
node _T_224 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_225 = and(_T_223, _T_224)
node _T_226 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_227 = and(_T_225, _T_226)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_228 = shr(io.in.a.bits.source, 2)
node _T_229 = eq(_T_228, UInt<2>(0h2))
node _T_230 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_231 = and(_T_229, _T_230)
node _T_232 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_233 = and(_T_231, _T_232)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_234 = shr(io.in.a.bits.source, 2)
node _T_235 = eq(_T_234, UInt<2>(0h3))
node _T_236 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_237 = and(_T_235, _T_236)
node _T_238 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_239 = and(_T_237, _T_238)
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0)
node _T_240 = shr(io.in.a.bits.source, 2)
node _T_241 = eq(_T_240, UInt<4>(0ha))
node _T_242 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_243 = and(_T_241, _T_242)
node _T_244 = leq(uncommonBits_16, UInt<2>(0h2))
node _T_245 = and(_T_243, _T_244)
node _T_246 = eq(io.in.a.bits.source, UInt<6>(0h2b))
node _T_247 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0)
node _T_248 = shr(io.in.a.bits.source, 2)
node _T_249 = eq(_T_248, UInt<4>(0h8))
node _T_250 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_251 = and(_T_249, _T_250)
node _T_252 = leq(uncommonBits_17, UInt<2>(0h2))
node _T_253 = and(_T_251, _T_252)
node _T_254 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _T_255 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_256 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _WIRE : UInt<1>[12]
connect _WIRE[0], _T_215
connect _WIRE[1], _T_221
connect _WIRE[2], _T_227
connect _WIRE[3], _T_233
connect _WIRE[4], _T_239
connect _WIRE[5], _T_245
connect _WIRE[6], _T_246
connect _WIRE[7], _T_247
connect _WIRE[8], _T_253
connect _WIRE[9], _T_254
connect _WIRE[10], _T_255
connect _WIRE[11], _T_256
node _T_257 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_258 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_259 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_260 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_261 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_262 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_263 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_264 = mux(_WIRE[5], _T_257, UInt<1>(0h0))
node _T_265 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_266 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_267 = mux(_WIRE[8], _T_258, UInt<1>(0h0))
node _T_268 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_269 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_270 = mux(_WIRE[11], UInt<1>(0h0), UInt<1>(0h0))
node _T_271 = or(_T_259, _T_260)
node _T_272 = or(_T_271, _T_261)
node _T_273 = or(_T_272, _T_262)
node _T_274 = or(_T_273, _T_263)
node _T_275 = or(_T_274, _T_264)
node _T_276 = or(_T_275, _T_265)
node _T_277 = or(_T_276, _T_266)
node _T_278 = or(_T_277, _T_267)
node _T_279 = or(_T_278, _T_268)
node _T_280 = or(_T_279, _T_269)
node _T_281 = or(_T_280, _T_270)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_281
node _T_282 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_283 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_284 = and(_T_282, _T_283)
node _T_285 = or(UInt<1>(0h0), _T_284)
node _T_286 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_287 = cvt(_T_286)
node _T_288 = and(_T_287, asSInt(UInt<13>(0h1000)))
node _T_289 = asSInt(_T_288)
node _T_290 = eq(_T_289, asSInt(UInt<1>(0h0)))
node _T_291 = and(_T_285, _T_290)
node _T_292 = or(UInt<1>(0h0), _T_291)
node _T_293 = and(_WIRE_1, _T_292)
node _T_294 = asUInt(reset)
node _T_295 = eq(_T_294, UInt<1>(0h0))
when _T_295 :
node _T_296 = eq(_T_293, UInt<1>(0h0))
when _T_296 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_293, UInt<1>(0h1), "") : assert_3
node _T_297 = asUInt(reset)
node _T_298 = eq(_T_297, UInt<1>(0h0))
when _T_298 :
node _T_299 = eq(source_ok, UInt<1>(0h0))
when _T_299 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_300 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_301 = asUInt(reset)
node _T_302 = eq(_T_301, UInt<1>(0h0))
when _T_302 :
node _T_303 = eq(_T_300, UInt<1>(0h0))
when _T_303 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_300, UInt<1>(0h1), "") : assert_5
node _T_304 = asUInt(reset)
node _T_305 = eq(_T_304, UInt<1>(0h0))
when _T_305 :
node _T_306 = eq(is_aligned, UInt<1>(0h0))
when _T_306 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_307 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_308 = asUInt(reset)
node _T_309 = eq(_T_308, UInt<1>(0h0))
when _T_309 :
node _T_310 = eq(_T_307, UInt<1>(0h0))
when _T_310 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_307, UInt<1>(0h1), "") : assert_7
node _T_311 = not(io.in.a.bits.mask)
node _T_312 = eq(_T_311, UInt<1>(0h0))
node _T_313 = asUInt(reset)
node _T_314 = eq(_T_313, UInt<1>(0h0))
when _T_314 :
node _T_315 = eq(_T_312, UInt<1>(0h0))
when _T_315 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_312, UInt<1>(0h1), "") : assert_8
node _T_316 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_317 = asUInt(reset)
node _T_318 = eq(_T_317, UInt<1>(0h0))
when _T_318 :
node _T_319 = eq(_T_316, UInt<1>(0h0))
when _T_319 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_316, UInt<1>(0h1), "") : assert_9
node _T_320 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_320 :
node _T_321 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_322 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_323 = and(_T_321, _T_322)
node _T_324 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0)
node _T_325 = shr(io.in.a.bits.source, 2)
node _T_326 = eq(_T_325, UInt<1>(0h0))
node _T_327 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_328 = and(_T_326, _T_327)
node _T_329 = leq(uncommonBits_18, UInt<2>(0h3))
node _T_330 = and(_T_328, _T_329)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0)
node _T_331 = shr(io.in.a.bits.source, 2)
node _T_332 = eq(_T_331, UInt<1>(0h1))
node _T_333 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_334 = and(_T_332, _T_333)
node _T_335 = leq(uncommonBits_19, UInt<2>(0h3))
node _T_336 = and(_T_334, _T_335)
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_337 = shr(io.in.a.bits.source, 2)
node _T_338 = eq(_T_337, UInt<2>(0h2))
node _T_339 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_340 = and(_T_338, _T_339)
node _T_341 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_342 = and(_T_340, _T_341)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_343 = shr(io.in.a.bits.source, 2)
node _T_344 = eq(_T_343, UInt<2>(0h3))
node _T_345 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_346 = and(_T_344, _T_345)
node _T_347 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_348 = and(_T_346, _T_347)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0)
node _T_349 = shr(io.in.a.bits.source, 2)
node _T_350 = eq(_T_349, UInt<4>(0ha))
node _T_351 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_352 = and(_T_350, _T_351)
node _T_353 = leq(uncommonBits_22, UInt<2>(0h2))
node _T_354 = and(_T_352, _T_353)
node _T_355 = eq(io.in.a.bits.source, UInt<6>(0h2b))
node _T_356 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0)
node _T_357 = shr(io.in.a.bits.source, 2)
node _T_358 = eq(_T_357, UInt<4>(0h8))
node _T_359 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_360 = and(_T_358, _T_359)
node _T_361 = leq(uncommonBits_23, UInt<2>(0h2))
node _T_362 = and(_T_360, _T_361)
node _T_363 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _T_364 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_365 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_366 = or(_T_324, _T_330)
node _T_367 = or(_T_366, _T_336)
node _T_368 = or(_T_367, _T_342)
node _T_369 = or(_T_368, _T_348)
node _T_370 = or(_T_369, _T_354)
node _T_371 = or(_T_370, _T_355)
node _T_372 = or(_T_371, _T_356)
node _T_373 = or(_T_372, _T_362)
node _T_374 = or(_T_373, _T_363)
node _T_375 = or(_T_374, _T_364)
node _T_376 = or(_T_375, _T_365)
node _T_377 = and(_T_323, _T_376)
node _T_378 = or(UInt<1>(0h0), _T_377)
node _T_379 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_380 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_381 = cvt(_T_380)
node _T_382 = and(_T_381, asSInt(UInt<13>(0h1000)))
node _T_383 = asSInt(_T_382)
node _T_384 = eq(_T_383, asSInt(UInt<1>(0h0)))
node _T_385 = and(_T_379, _T_384)
node _T_386 = or(UInt<1>(0h0), _T_385)
node _T_387 = and(_T_378, _T_386)
node _T_388 = asUInt(reset)
node _T_389 = eq(_T_388, UInt<1>(0h0))
when _T_389 :
node _T_390 = eq(_T_387, UInt<1>(0h0))
when _T_390 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_387, UInt<1>(0h1), "") : assert_10
node _T_391 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_392 = shr(io.in.a.bits.source, 2)
node _T_393 = eq(_T_392, UInt<1>(0h0))
node _T_394 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_395 = and(_T_393, _T_394)
node _T_396 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_397 = and(_T_395, _T_396)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_398 = shr(io.in.a.bits.source, 2)
node _T_399 = eq(_T_398, UInt<1>(0h1))
node _T_400 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_401 = and(_T_399, _T_400)
node _T_402 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_403 = and(_T_401, _T_402)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_404 = shr(io.in.a.bits.source, 2)
node _T_405 = eq(_T_404, UInt<2>(0h2))
node _T_406 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_407 = and(_T_405, _T_406)
node _T_408 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_409 = and(_T_407, _T_408)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_410 = shr(io.in.a.bits.source, 2)
node _T_411 = eq(_T_410, UInt<2>(0h3))
node _T_412 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_413 = and(_T_411, _T_412)
node _T_414 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_415 = and(_T_413, _T_414)
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0)
node _T_416 = shr(io.in.a.bits.source, 2)
node _T_417 = eq(_T_416, UInt<4>(0ha))
node _T_418 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_419 = and(_T_417, _T_418)
node _T_420 = leq(uncommonBits_28, UInt<2>(0h2))
node _T_421 = and(_T_419, _T_420)
node _T_422 = eq(io.in.a.bits.source, UInt<6>(0h2b))
node _T_423 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0)
node _T_424 = shr(io.in.a.bits.source, 2)
node _T_425 = eq(_T_424, UInt<4>(0h8))
node _T_426 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_427 = and(_T_425, _T_426)
node _T_428 = leq(uncommonBits_29, UInt<2>(0h2))
node _T_429 = and(_T_427, _T_428)
node _T_430 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _T_431 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_432 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _WIRE_2 : UInt<1>[12]
connect _WIRE_2[0], _T_391
connect _WIRE_2[1], _T_397
connect _WIRE_2[2], _T_403
connect _WIRE_2[3], _T_409
connect _WIRE_2[4], _T_415
connect _WIRE_2[5], _T_421
connect _WIRE_2[6], _T_422
connect _WIRE_2[7], _T_423
connect _WIRE_2[8], _T_429
connect _WIRE_2[9], _T_430
connect _WIRE_2[10], _T_431
connect _WIRE_2[11], _T_432
node _T_433 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_434 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_435 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_436 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_437 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_438 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_439 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_440 = mux(_WIRE_2[5], _T_433, UInt<1>(0h0))
node _T_441 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_442 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_443 = mux(_WIRE_2[8], _T_434, UInt<1>(0h0))
node _T_444 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_445 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_446 = mux(_WIRE_2[11], UInt<1>(0h0), UInt<1>(0h0))
node _T_447 = or(_T_435, _T_436)
node _T_448 = or(_T_447, _T_437)
node _T_449 = or(_T_448, _T_438)
node _T_450 = or(_T_449, _T_439)
node _T_451 = or(_T_450, _T_440)
node _T_452 = or(_T_451, _T_441)
node _T_453 = or(_T_452, _T_442)
node _T_454 = or(_T_453, _T_443)
node _T_455 = or(_T_454, _T_444)
node _T_456 = or(_T_455, _T_445)
node _T_457 = or(_T_456, _T_446)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_457
node _T_458 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_459 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_460 = and(_T_458, _T_459)
node _T_461 = or(UInt<1>(0h0), _T_460)
node _T_462 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_463 = cvt(_T_462)
node _T_464 = and(_T_463, asSInt(UInt<13>(0h1000)))
node _T_465 = asSInt(_T_464)
node _T_466 = eq(_T_465, asSInt(UInt<1>(0h0)))
node _T_467 = and(_T_461, _T_466)
node _T_468 = or(UInt<1>(0h0), _T_467)
node _T_469 = and(_WIRE_3, _T_468)
node _T_470 = asUInt(reset)
node _T_471 = eq(_T_470, UInt<1>(0h0))
when _T_471 :
node _T_472 = eq(_T_469, UInt<1>(0h0))
when _T_472 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_469, UInt<1>(0h1), "") : assert_11
node _T_473 = asUInt(reset)
node _T_474 = eq(_T_473, UInt<1>(0h0))
when _T_474 :
node _T_475 = eq(source_ok, UInt<1>(0h0))
when _T_475 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_476 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_477 = asUInt(reset)
node _T_478 = eq(_T_477, UInt<1>(0h0))
when _T_478 :
node _T_479 = eq(_T_476, UInt<1>(0h0))
when _T_479 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_476, UInt<1>(0h1), "") : assert_13
node _T_480 = asUInt(reset)
node _T_481 = eq(_T_480, UInt<1>(0h0))
when _T_481 :
node _T_482 = eq(is_aligned, UInt<1>(0h0))
when _T_482 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_483 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_484 = asUInt(reset)
node _T_485 = eq(_T_484, UInt<1>(0h0))
when _T_485 :
node _T_486 = eq(_T_483, UInt<1>(0h0))
when _T_486 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_483, UInt<1>(0h1), "") : assert_15
node _T_487 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_488 = asUInt(reset)
node _T_489 = eq(_T_488, UInt<1>(0h0))
when _T_489 :
node _T_490 = eq(_T_487, UInt<1>(0h0))
when _T_490 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_487, UInt<1>(0h1), "") : assert_16
node _T_491 = not(io.in.a.bits.mask)
node _T_492 = eq(_T_491, UInt<1>(0h0))
node _T_493 = asUInt(reset)
node _T_494 = eq(_T_493, UInt<1>(0h0))
when _T_494 :
node _T_495 = eq(_T_492, UInt<1>(0h0))
when _T_495 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_492, UInt<1>(0h1), "") : assert_17
node _T_496 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_497 = asUInt(reset)
node _T_498 = eq(_T_497, UInt<1>(0h0))
when _T_498 :
node _T_499 = eq(_T_496, UInt<1>(0h0))
when _T_499 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_496, UInt<1>(0h1), "") : assert_18
node _T_500 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_500 :
node _T_501 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_502 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_503 = and(_T_501, _T_502)
node _T_504 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_505 = shr(io.in.a.bits.source, 2)
node _T_506 = eq(_T_505, UInt<1>(0h0))
node _T_507 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_508 = and(_T_506, _T_507)
node _T_509 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_510 = and(_T_508, _T_509)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_511 = shr(io.in.a.bits.source, 2)
node _T_512 = eq(_T_511, UInt<1>(0h1))
node _T_513 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_514 = and(_T_512, _T_513)
node _T_515 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_516 = and(_T_514, _T_515)
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_517 = shr(io.in.a.bits.source, 2)
node _T_518 = eq(_T_517, UInt<2>(0h2))
node _T_519 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_520 = and(_T_518, _T_519)
node _T_521 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_522 = and(_T_520, _T_521)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_523 = shr(io.in.a.bits.source, 2)
node _T_524 = eq(_T_523, UInt<2>(0h3))
node _T_525 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_526 = and(_T_524, _T_525)
node _T_527 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_528 = and(_T_526, _T_527)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0)
node _T_529 = shr(io.in.a.bits.source, 2)
node _T_530 = eq(_T_529, UInt<4>(0ha))
node _T_531 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_532 = and(_T_530, _T_531)
node _T_533 = leq(uncommonBits_34, UInt<2>(0h2))
node _T_534 = and(_T_532, _T_533)
node _T_535 = eq(io.in.a.bits.source, UInt<6>(0h2b))
node _T_536 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0)
node _T_537 = shr(io.in.a.bits.source, 2)
node _T_538 = eq(_T_537, UInt<4>(0h8))
node _T_539 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_540 = and(_T_538, _T_539)
node _T_541 = leq(uncommonBits_35, UInt<2>(0h2))
node _T_542 = and(_T_540, _T_541)
node _T_543 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _T_544 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_545 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_546 = or(_T_504, _T_510)
node _T_547 = or(_T_546, _T_516)
node _T_548 = or(_T_547, _T_522)
node _T_549 = or(_T_548, _T_528)
node _T_550 = or(_T_549, _T_534)
node _T_551 = or(_T_550, _T_535)
node _T_552 = or(_T_551, _T_536)
node _T_553 = or(_T_552, _T_542)
node _T_554 = or(_T_553, _T_543)
node _T_555 = or(_T_554, _T_544)
node _T_556 = or(_T_555, _T_545)
node _T_557 = and(_T_503, _T_556)
node _T_558 = or(UInt<1>(0h0), _T_557)
node _T_559 = asUInt(reset)
node _T_560 = eq(_T_559, UInt<1>(0h0))
when _T_560 :
node _T_561 = eq(_T_558, UInt<1>(0h0))
when _T_561 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_558, UInt<1>(0h1), "") : assert_19
node _T_562 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_563 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_564 = and(_T_562, _T_563)
node _T_565 = or(UInt<1>(0h0), _T_564)
node _T_566 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_567 = cvt(_T_566)
node _T_568 = and(_T_567, asSInt(UInt<13>(0h1000)))
node _T_569 = asSInt(_T_568)
node _T_570 = eq(_T_569, asSInt(UInt<1>(0h0)))
node _T_571 = and(_T_565, _T_570)
node _T_572 = or(UInt<1>(0h0), _T_571)
node _T_573 = asUInt(reset)
node _T_574 = eq(_T_573, UInt<1>(0h0))
when _T_574 :
node _T_575 = eq(_T_572, UInt<1>(0h0))
when _T_575 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_572, UInt<1>(0h1), "") : assert_20
node _T_576 = asUInt(reset)
node _T_577 = eq(_T_576, UInt<1>(0h0))
when _T_577 :
node _T_578 = eq(source_ok, UInt<1>(0h0))
when _T_578 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_579 = asUInt(reset)
node _T_580 = eq(_T_579, UInt<1>(0h0))
when _T_580 :
node _T_581 = eq(is_aligned, UInt<1>(0h0))
when _T_581 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_582 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_583 = asUInt(reset)
node _T_584 = eq(_T_583, UInt<1>(0h0))
when _T_584 :
node _T_585 = eq(_T_582, UInt<1>(0h0))
when _T_585 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_582, UInt<1>(0h1), "") : assert_23
node _T_586 = eq(io.in.a.bits.mask, mask)
node _T_587 = asUInt(reset)
node _T_588 = eq(_T_587, UInt<1>(0h0))
when _T_588 :
node _T_589 = eq(_T_586, UInt<1>(0h0))
when _T_589 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_586, UInt<1>(0h1), "") : assert_24
node _T_590 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_591 = asUInt(reset)
node _T_592 = eq(_T_591, UInt<1>(0h0))
when _T_592 :
node _T_593 = eq(_T_590, UInt<1>(0h0))
when _T_593 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_590, UInt<1>(0h1), "") : assert_25
node _T_594 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_594 :
node _T_595 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_596 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_597 = and(_T_595, _T_596)
node _T_598 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0)
node _T_599 = shr(io.in.a.bits.source, 2)
node _T_600 = eq(_T_599, UInt<1>(0h0))
node _T_601 = leq(UInt<1>(0h0), uncommonBits_36)
node _T_602 = and(_T_600, _T_601)
node _T_603 = leq(uncommonBits_36, UInt<2>(0h3))
node _T_604 = and(_T_602, _T_603)
node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0)
node _T_605 = shr(io.in.a.bits.source, 2)
node _T_606 = eq(_T_605, UInt<1>(0h1))
node _T_607 = leq(UInt<1>(0h0), uncommonBits_37)
node _T_608 = and(_T_606, _T_607)
node _T_609 = leq(uncommonBits_37, UInt<2>(0h3))
node _T_610 = and(_T_608, _T_609)
node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0)
node _T_611 = shr(io.in.a.bits.source, 2)
node _T_612 = eq(_T_611, UInt<2>(0h2))
node _T_613 = leq(UInt<1>(0h0), uncommonBits_38)
node _T_614 = and(_T_612, _T_613)
node _T_615 = leq(uncommonBits_38, UInt<2>(0h3))
node _T_616 = and(_T_614, _T_615)
node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0)
node _T_617 = shr(io.in.a.bits.source, 2)
node _T_618 = eq(_T_617, UInt<2>(0h3))
node _T_619 = leq(UInt<1>(0h0), uncommonBits_39)
node _T_620 = and(_T_618, _T_619)
node _T_621 = leq(uncommonBits_39, UInt<2>(0h3))
node _T_622 = and(_T_620, _T_621)
node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0)
node _T_623 = shr(io.in.a.bits.source, 2)
node _T_624 = eq(_T_623, UInt<4>(0ha))
node _T_625 = leq(UInt<1>(0h0), uncommonBits_40)
node _T_626 = and(_T_624, _T_625)
node _T_627 = leq(uncommonBits_40, UInt<2>(0h2))
node _T_628 = and(_T_626, _T_627)
node _T_629 = eq(io.in.a.bits.source, UInt<6>(0h2b))
node _T_630 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0)
node _T_631 = shr(io.in.a.bits.source, 2)
node _T_632 = eq(_T_631, UInt<4>(0h8))
node _T_633 = leq(UInt<1>(0h0), uncommonBits_41)
node _T_634 = and(_T_632, _T_633)
node _T_635 = leq(uncommonBits_41, UInt<2>(0h2))
node _T_636 = and(_T_634, _T_635)
node _T_637 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _T_638 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_639 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_640 = or(_T_598, _T_604)
node _T_641 = or(_T_640, _T_610)
node _T_642 = or(_T_641, _T_616)
node _T_643 = or(_T_642, _T_622)
node _T_644 = or(_T_643, _T_628)
node _T_645 = or(_T_644, _T_629)
node _T_646 = or(_T_645, _T_630)
node _T_647 = or(_T_646, _T_636)
node _T_648 = or(_T_647, _T_637)
node _T_649 = or(_T_648, _T_638)
node _T_650 = or(_T_649, _T_639)
node _T_651 = and(_T_597, _T_650)
node _T_652 = or(UInt<1>(0h0), _T_651)
node _T_653 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_654 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_655 = and(_T_653, _T_654)
node _T_656 = or(UInt<1>(0h0), _T_655)
node _T_657 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_658 = cvt(_T_657)
node _T_659 = and(_T_658, asSInt(UInt<13>(0h1000)))
node _T_660 = asSInt(_T_659)
node _T_661 = eq(_T_660, asSInt(UInt<1>(0h0)))
node _T_662 = and(_T_656, _T_661)
node _T_663 = or(UInt<1>(0h0), _T_662)
node _T_664 = and(_T_652, _T_663)
node _T_665 = asUInt(reset)
node _T_666 = eq(_T_665, UInt<1>(0h0))
when _T_666 :
node _T_667 = eq(_T_664, UInt<1>(0h0))
when _T_667 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_664, UInt<1>(0h1), "") : assert_26
node _T_668 = asUInt(reset)
node _T_669 = eq(_T_668, UInt<1>(0h0))
when _T_669 :
node _T_670 = eq(source_ok, UInt<1>(0h0))
when _T_670 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_671 = asUInt(reset)
node _T_672 = eq(_T_671, UInt<1>(0h0))
when _T_672 :
node _T_673 = eq(is_aligned, UInt<1>(0h0))
when _T_673 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_674 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_675 = asUInt(reset)
node _T_676 = eq(_T_675, UInt<1>(0h0))
when _T_676 :
node _T_677 = eq(_T_674, UInt<1>(0h0))
when _T_677 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_674, UInt<1>(0h1), "") : assert_29
node _T_678 = eq(io.in.a.bits.mask, mask)
node _T_679 = asUInt(reset)
node _T_680 = eq(_T_679, UInt<1>(0h0))
when _T_680 :
node _T_681 = eq(_T_678, UInt<1>(0h0))
when _T_681 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_678, UInt<1>(0h1), "") : assert_30
node _T_682 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_682 :
node _T_683 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_684 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_685 = and(_T_683, _T_684)
node _T_686 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0)
node _T_687 = shr(io.in.a.bits.source, 2)
node _T_688 = eq(_T_687, UInt<1>(0h0))
node _T_689 = leq(UInt<1>(0h0), uncommonBits_42)
node _T_690 = and(_T_688, _T_689)
node _T_691 = leq(uncommonBits_42, UInt<2>(0h3))
node _T_692 = and(_T_690, _T_691)
node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0)
node _T_693 = shr(io.in.a.bits.source, 2)
node _T_694 = eq(_T_693, UInt<1>(0h1))
node _T_695 = leq(UInt<1>(0h0), uncommonBits_43)
node _T_696 = and(_T_694, _T_695)
node _T_697 = leq(uncommonBits_43, UInt<2>(0h3))
node _T_698 = and(_T_696, _T_697)
node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0)
node _T_699 = shr(io.in.a.bits.source, 2)
node _T_700 = eq(_T_699, UInt<2>(0h2))
node _T_701 = leq(UInt<1>(0h0), uncommonBits_44)
node _T_702 = and(_T_700, _T_701)
node _T_703 = leq(uncommonBits_44, UInt<2>(0h3))
node _T_704 = and(_T_702, _T_703)
node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0)
node _T_705 = shr(io.in.a.bits.source, 2)
node _T_706 = eq(_T_705, UInt<2>(0h3))
node _T_707 = leq(UInt<1>(0h0), uncommonBits_45)
node _T_708 = and(_T_706, _T_707)
node _T_709 = leq(uncommonBits_45, UInt<2>(0h3))
node _T_710 = and(_T_708, _T_709)
node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_46 = bits(_uncommonBits_T_46, 1, 0)
node _T_711 = shr(io.in.a.bits.source, 2)
node _T_712 = eq(_T_711, UInt<4>(0ha))
node _T_713 = leq(UInt<1>(0h0), uncommonBits_46)
node _T_714 = and(_T_712, _T_713)
node _T_715 = leq(uncommonBits_46, UInt<2>(0h2))
node _T_716 = and(_T_714, _T_715)
node _T_717 = eq(io.in.a.bits.source, UInt<6>(0h2b))
node _T_718 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_47 = bits(_uncommonBits_T_47, 1, 0)
node _T_719 = shr(io.in.a.bits.source, 2)
node _T_720 = eq(_T_719, UInt<4>(0h8))
node _T_721 = leq(UInt<1>(0h0), uncommonBits_47)
node _T_722 = and(_T_720, _T_721)
node _T_723 = leq(uncommonBits_47, UInt<2>(0h2))
node _T_724 = and(_T_722, _T_723)
node _T_725 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _T_726 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_727 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_728 = or(_T_686, _T_692)
node _T_729 = or(_T_728, _T_698)
node _T_730 = or(_T_729, _T_704)
node _T_731 = or(_T_730, _T_710)
node _T_732 = or(_T_731, _T_716)
node _T_733 = or(_T_732, _T_717)
node _T_734 = or(_T_733, _T_718)
node _T_735 = or(_T_734, _T_724)
node _T_736 = or(_T_735, _T_725)
node _T_737 = or(_T_736, _T_726)
node _T_738 = or(_T_737, _T_727)
node _T_739 = and(_T_685, _T_738)
node _T_740 = or(UInt<1>(0h0), _T_739)
node _T_741 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_742 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_743 = and(_T_741, _T_742)
node _T_744 = or(UInt<1>(0h0), _T_743)
node _T_745 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_746 = cvt(_T_745)
node _T_747 = and(_T_746, asSInt(UInt<13>(0h1000)))
node _T_748 = asSInt(_T_747)
node _T_749 = eq(_T_748, asSInt(UInt<1>(0h0)))
node _T_750 = and(_T_744, _T_749)
node _T_751 = or(UInt<1>(0h0), _T_750)
node _T_752 = and(_T_740, _T_751)
node _T_753 = asUInt(reset)
node _T_754 = eq(_T_753, UInt<1>(0h0))
when _T_754 :
node _T_755 = eq(_T_752, UInt<1>(0h0))
when _T_755 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_752, UInt<1>(0h1), "") : assert_31
node _T_756 = asUInt(reset)
node _T_757 = eq(_T_756, UInt<1>(0h0))
when _T_757 :
node _T_758 = eq(source_ok, UInt<1>(0h0))
when _T_758 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_759 = asUInt(reset)
node _T_760 = eq(_T_759, UInt<1>(0h0))
when _T_760 :
node _T_761 = eq(is_aligned, UInt<1>(0h0))
when _T_761 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_762 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_763 = asUInt(reset)
node _T_764 = eq(_T_763, UInt<1>(0h0))
when _T_764 :
node _T_765 = eq(_T_762, UInt<1>(0h0))
when _T_765 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_762, UInt<1>(0h1), "") : assert_34
node _T_766 = not(mask)
node _T_767 = and(io.in.a.bits.mask, _T_766)
node _T_768 = eq(_T_767, UInt<1>(0h0))
node _T_769 = asUInt(reset)
node _T_770 = eq(_T_769, UInt<1>(0h0))
when _T_770 :
node _T_771 = eq(_T_768, UInt<1>(0h0))
when _T_771 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_768, UInt<1>(0h1), "") : assert_35
node _T_772 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_772 :
node _T_773 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_774 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_775 = and(_T_773, _T_774)
node _T_776 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0)
node _T_777 = shr(io.in.a.bits.source, 2)
node _T_778 = eq(_T_777, UInt<1>(0h0))
node _T_779 = leq(UInt<1>(0h0), uncommonBits_48)
node _T_780 = and(_T_778, _T_779)
node _T_781 = leq(uncommonBits_48, UInt<2>(0h3))
node _T_782 = and(_T_780, _T_781)
node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0)
node _T_783 = shr(io.in.a.bits.source, 2)
node _T_784 = eq(_T_783, UInt<1>(0h1))
node _T_785 = leq(UInt<1>(0h0), uncommonBits_49)
node _T_786 = and(_T_784, _T_785)
node _T_787 = leq(uncommonBits_49, UInt<2>(0h3))
node _T_788 = and(_T_786, _T_787)
node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0)
node _T_789 = shr(io.in.a.bits.source, 2)
node _T_790 = eq(_T_789, UInt<2>(0h2))
node _T_791 = leq(UInt<1>(0h0), uncommonBits_50)
node _T_792 = and(_T_790, _T_791)
node _T_793 = leq(uncommonBits_50, UInt<2>(0h3))
node _T_794 = and(_T_792, _T_793)
node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0)
node _T_795 = shr(io.in.a.bits.source, 2)
node _T_796 = eq(_T_795, UInt<2>(0h3))
node _T_797 = leq(UInt<1>(0h0), uncommonBits_51)
node _T_798 = and(_T_796, _T_797)
node _T_799 = leq(uncommonBits_51, UInt<2>(0h3))
node _T_800 = and(_T_798, _T_799)
node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_52 = bits(_uncommonBits_T_52, 1, 0)
node _T_801 = shr(io.in.a.bits.source, 2)
node _T_802 = eq(_T_801, UInt<4>(0ha))
node _T_803 = leq(UInt<1>(0h0), uncommonBits_52)
node _T_804 = and(_T_802, _T_803)
node _T_805 = leq(uncommonBits_52, UInt<2>(0h2))
node _T_806 = and(_T_804, _T_805)
node _T_807 = eq(io.in.a.bits.source, UInt<6>(0h2b))
node _T_808 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_53 = bits(_uncommonBits_T_53, 1, 0)
node _T_809 = shr(io.in.a.bits.source, 2)
node _T_810 = eq(_T_809, UInt<4>(0h8))
node _T_811 = leq(UInt<1>(0h0), uncommonBits_53)
node _T_812 = and(_T_810, _T_811)
node _T_813 = leq(uncommonBits_53, UInt<2>(0h2))
node _T_814 = and(_T_812, _T_813)
node _T_815 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _T_816 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_817 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_818 = or(_T_776, _T_782)
node _T_819 = or(_T_818, _T_788)
node _T_820 = or(_T_819, _T_794)
node _T_821 = or(_T_820, _T_800)
node _T_822 = or(_T_821, _T_806)
node _T_823 = or(_T_822, _T_807)
node _T_824 = or(_T_823, _T_808)
node _T_825 = or(_T_824, _T_814)
node _T_826 = or(_T_825, _T_815)
node _T_827 = or(_T_826, _T_816)
node _T_828 = or(_T_827, _T_817)
node _T_829 = and(_T_775, _T_828)
node _T_830 = or(UInt<1>(0h0), _T_829)
node _T_831 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_832 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_833 = cvt(_T_832)
node _T_834 = and(_T_833, asSInt(UInt<13>(0h1000)))
node _T_835 = asSInt(_T_834)
node _T_836 = eq(_T_835, asSInt(UInt<1>(0h0)))
node _T_837 = and(_T_831, _T_836)
node _T_838 = or(UInt<1>(0h0), _T_837)
node _T_839 = and(_T_830, _T_838)
node _T_840 = asUInt(reset)
node _T_841 = eq(_T_840, UInt<1>(0h0))
when _T_841 :
node _T_842 = eq(_T_839, UInt<1>(0h0))
when _T_842 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_839, UInt<1>(0h1), "") : assert_36
node _T_843 = asUInt(reset)
node _T_844 = eq(_T_843, UInt<1>(0h0))
when _T_844 :
node _T_845 = eq(source_ok, UInt<1>(0h0))
when _T_845 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_846 = asUInt(reset)
node _T_847 = eq(_T_846, UInt<1>(0h0))
when _T_847 :
node _T_848 = eq(is_aligned, UInt<1>(0h0))
when _T_848 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_849 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_850 = asUInt(reset)
node _T_851 = eq(_T_850, UInt<1>(0h0))
when _T_851 :
node _T_852 = eq(_T_849, UInt<1>(0h0))
when _T_852 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_849, UInt<1>(0h1), "") : assert_39
node _T_853 = eq(io.in.a.bits.mask, mask)
node _T_854 = asUInt(reset)
node _T_855 = eq(_T_854, UInt<1>(0h0))
when _T_855 :
node _T_856 = eq(_T_853, UInt<1>(0h0))
when _T_856 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_853, UInt<1>(0h1), "") : assert_40
node _T_857 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_857 :
node _T_858 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_859 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_860 = and(_T_858, _T_859)
node _T_861 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_54 = bits(_uncommonBits_T_54, 1, 0)
node _T_862 = shr(io.in.a.bits.source, 2)
node _T_863 = eq(_T_862, UInt<1>(0h0))
node _T_864 = leq(UInt<1>(0h0), uncommonBits_54)
node _T_865 = and(_T_863, _T_864)
node _T_866 = leq(uncommonBits_54, UInt<2>(0h3))
node _T_867 = and(_T_865, _T_866)
node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_55 = bits(_uncommonBits_T_55, 1, 0)
node _T_868 = shr(io.in.a.bits.source, 2)
node _T_869 = eq(_T_868, UInt<1>(0h1))
node _T_870 = leq(UInt<1>(0h0), uncommonBits_55)
node _T_871 = and(_T_869, _T_870)
node _T_872 = leq(uncommonBits_55, UInt<2>(0h3))
node _T_873 = and(_T_871, _T_872)
node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0)
node _T_874 = shr(io.in.a.bits.source, 2)
node _T_875 = eq(_T_874, UInt<2>(0h2))
node _T_876 = leq(UInt<1>(0h0), uncommonBits_56)
node _T_877 = and(_T_875, _T_876)
node _T_878 = leq(uncommonBits_56, UInt<2>(0h3))
node _T_879 = and(_T_877, _T_878)
node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0)
node _T_880 = shr(io.in.a.bits.source, 2)
node _T_881 = eq(_T_880, UInt<2>(0h3))
node _T_882 = leq(UInt<1>(0h0), uncommonBits_57)
node _T_883 = and(_T_881, _T_882)
node _T_884 = leq(uncommonBits_57, UInt<2>(0h3))
node _T_885 = and(_T_883, _T_884)
node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_58 = bits(_uncommonBits_T_58, 1, 0)
node _T_886 = shr(io.in.a.bits.source, 2)
node _T_887 = eq(_T_886, UInt<4>(0ha))
node _T_888 = leq(UInt<1>(0h0), uncommonBits_58)
node _T_889 = and(_T_887, _T_888)
node _T_890 = leq(uncommonBits_58, UInt<2>(0h2))
node _T_891 = and(_T_889, _T_890)
node _T_892 = eq(io.in.a.bits.source, UInt<6>(0h2b))
node _T_893 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_59 = bits(_uncommonBits_T_59, 1, 0)
node _T_894 = shr(io.in.a.bits.source, 2)
node _T_895 = eq(_T_894, UInt<4>(0h8))
node _T_896 = leq(UInt<1>(0h0), uncommonBits_59)
node _T_897 = and(_T_895, _T_896)
node _T_898 = leq(uncommonBits_59, UInt<2>(0h2))
node _T_899 = and(_T_897, _T_898)
node _T_900 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _T_901 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_902 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_903 = or(_T_861, _T_867)
node _T_904 = or(_T_903, _T_873)
node _T_905 = or(_T_904, _T_879)
node _T_906 = or(_T_905, _T_885)
node _T_907 = or(_T_906, _T_891)
node _T_908 = or(_T_907, _T_892)
node _T_909 = or(_T_908, _T_893)
node _T_910 = or(_T_909, _T_899)
node _T_911 = or(_T_910, _T_900)
node _T_912 = or(_T_911, _T_901)
node _T_913 = or(_T_912, _T_902)
node _T_914 = and(_T_860, _T_913)
node _T_915 = or(UInt<1>(0h0), _T_914)
node _T_916 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_917 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_918 = cvt(_T_917)
node _T_919 = and(_T_918, asSInt(UInt<13>(0h1000)))
node _T_920 = asSInt(_T_919)
node _T_921 = eq(_T_920, asSInt(UInt<1>(0h0)))
node _T_922 = and(_T_916, _T_921)
node _T_923 = or(UInt<1>(0h0), _T_922)
node _T_924 = and(_T_915, _T_923)
node _T_925 = asUInt(reset)
node _T_926 = eq(_T_925, UInt<1>(0h0))
when _T_926 :
node _T_927 = eq(_T_924, UInt<1>(0h0))
when _T_927 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_924, UInt<1>(0h1), "") : assert_41
node _T_928 = asUInt(reset)
node _T_929 = eq(_T_928, UInt<1>(0h0))
when _T_929 :
node _T_930 = eq(source_ok, UInt<1>(0h0))
when _T_930 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_931 = asUInt(reset)
node _T_932 = eq(_T_931, UInt<1>(0h0))
when _T_932 :
node _T_933 = eq(is_aligned, UInt<1>(0h0))
when _T_933 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_934 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_935 = asUInt(reset)
node _T_936 = eq(_T_935, UInt<1>(0h0))
when _T_936 :
node _T_937 = eq(_T_934, UInt<1>(0h0))
when _T_937 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_934, UInt<1>(0h1), "") : assert_44
node _T_938 = eq(io.in.a.bits.mask, mask)
node _T_939 = asUInt(reset)
node _T_940 = eq(_T_939, UInt<1>(0h0))
when _T_940 :
node _T_941 = eq(_T_938, UInt<1>(0h0))
when _T_941 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_938, UInt<1>(0h1), "") : assert_45
node _T_942 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_942 :
node _T_943 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_944 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_945 = and(_T_943, _T_944)
node _T_946 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_60 = bits(_uncommonBits_T_60, 1, 0)
node _T_947 = shr(io.in.a.bits.source, 2)
node _T_948 = eq(_T_947, UInt<1>(0h0))
node _T_949 = leq(UInt<1>(0h0), uncommonBits_60)
node _T_950 = and(_T_948, _T_949)
node _T_951 = leq(uncommonBits_60, UInt<2>(0h3))
node _T_952 = and(_T_950, _T_951)
node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_61 = bits(_uncommonBits_T_61, 1, 0)
node _T_953 = shr(io.in.a.bits.source, 2)
node _T_954 = eq(_T_953, UInt<1>(0h1))
node _T_955 = leq(UInt<1>(0h0), uncommonBits_61)
node _T_956 = and(_T_954, _T_955)
node _T_957 = leq(uncommonBits_61, UInt<2>(0h3))
node _T_958 = and(_T_956, _T_957)
node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_62 = bits(_uncommonBits_T_62, 1, 0)
node _T_959 = shr(io.in.a.bits.source, 2)
node _T_960 = eq(_T_959, UInt<2>(0h2))
node _T_961 = leq(UInt<1>(0h0), uncommonBits_62)
node _T_962 = and(_T_960, _T_961)
node _T_963 = leq(uncommonBits_62, UInt<2>(0h3))
node _T_964 = and(_T_962, _T_963)
node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0)
node _T_965 = shr(io.in.a.bits.source, 2)
node _T_966 = eq(_T_965, UInt<2>(0h3))
node _T_967 = leq(UInt<1>(0h0), uncommonBits_63)
node _T_968 = and(_T_966, _T_967)
node _T_969 = leq(uncommonBits_63, UInt<2>(0h3))
node _T_970 = and(_T_968, _T_969)
node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_64 = bits(_uncommonBits_T_64, 1, 0)
node _T_971 = shr(io.in.a.bits.source, 2)
node _T_972 = eq(_T_971, UInt<4>(0ha))
node _T_973 = leq(UInt<1>(0h0), uncommonBits_64)
node _T_974 = and(_T_972, _T_973)
node _T_975 = leq(uncommonBits_64, UInt<2>(0h2))
node _T_976 = and(_T_974, _T_975)
node _T_977 = eq(io.in.a.bits.source, UInt<6>(0h2b))
node _T_978 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_65 = bits(_uncommonBits_T_65, 1, 0)
node _T_979 = shr(io.in.a.bits.source, 2)
node _T_980 = eq(_T_979, UInt<4>(0h8))
node _T_981 = leq(UInt<1>(0h0), uncommonBits_65)
node _T_982 = and(_T_980, _T_981)
node _T_983 = leq(uncommonBits_65, UInt<2>(0h2))
node _T_984 = and(_T_982, _T_983)
node _T_985 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _T_986 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_987 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_988 = or(_T_946, _T_952)
node _T_989 = or(_T_988, _T_958)
node _T_990 = or(_T_989, _T_964)
node _T_991 = or(_T_990, _T_970)
node _T_992 = or(_T_991, _T_976)
node _T_993 = or(_T_992, _T_977)
node _T_994 = or(_T_993, _T_978)
node _T_995 = or(_T_994, _T_984)
node _T_996 = or(_T_995, _T_985)
node _T_997 = or(_T_996, _T_986)
node _T_998 = or(_T_997, _T_987)
node _T_999 = and(_T_945, _T_998)
node _T_1000 = or(UInt<1>(0h0), _T_999)
node _T_1001 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1002 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1003 = cvt(_T_1002)
node _T_1004 = and(_T_1003, asSInt(UInt<13>(0h1000)))
node _T_1005 = asSInt(_T_1004)
node _T_1006 = eq(_T_1005, asSInt(UInt<1>(0h0)))
node _T_1007 = and(_T_1001, _T_1006)
node _T_1008 = or(UInt<1>(0h0), _T_1007)
node _T_1009 = and(_T_1000, _T_1008)
node _T_1010 = asUInt(reset)
node _T_1011 = eq(_T_1010, UInt<1>(0h0))
when _T_1011 :
node _T_1012 = eq(_T_1009, UInt<1>(0h0))
when _T_1012 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_1009, UInt<1>(0h1), "") : assert_46
node _T_1013 = asUInt(reset)
node _T_1014 = eq(_T_1013, UInt<1>(0h0))
when _T_1014 :
node _T_1015 = eq(source_ok, UInt<1>(0h0))
when _T_1015 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_1016 = asUInt(reset)
node _T_1017 = eq(_T_1016, UInt<1>(0h0))
when _T_1017 :
node _T_1018 = eq(is_aligned, UInt<1>(0h0))
when _T_1018 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_1019 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_1020 = asUInt(reset)
node _T_1021 = eq(_T_1020, UInt<1>(0h0))
when _T_1021 :
node _T_1022 = eq(_T_1019, UInt<1>(0h0))
when _T_1022 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_1019, UInt<1>(0h1), "") : assert_49
node _T_1023 = eq(io.in.a.bits.mask, mask)
node _T_1024 = asUInt(reset)
node _T_1025 = eq(_T_1024, UInt<1>(0h0))
when _T_1025 :
node _T_1026 = eq(_T_1023, UInt<1>(0h0))
when _T_1026 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_1023, UInt<1>(0h1), "") : assert_50
node _T_1027 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1028 = asUInt(reset)
node _T_1029 = eq(_T_1028, UInt<1>(0h0))
when _T_1029 :
node _T_1030 = eq(_T_1027, UInt<1>(0h0))
when _T_1030 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_1027, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_1031 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1032 = asUInt(reset)
node _T_1033 = eq(_T_1032, UInt<1>(0h0))
when _T_1033 :
node _T_1034 = eq(_T_1031, UInt<1>(0h0))
when _T_1034 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_1031, UInt<1>(0h1), "") : assert_52
node _source_ok_T_52 = eq(io.in.d.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0)
node _source_ok_T_53 = shr(io.in.d.bits.source, 2)
node _source_ok_T_54 = eq(_source_ok_T_53, UInt<1>(0h0))
node _source_ok_T_55 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_56 = and(_source_ok_T_54, _source_ok_T_55)
node _source_ok_T_57 = leq(source_ok_uncommonBits_6, UInt<2>(0h3))
node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_59 = shr(io.in.d.bits.source, 2)
node _source_ok_T_60 = eq(_source_ok_T_59, UInt<1>(0h1))
node _source_ok_T_61 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_62 = and(_source_ok_T_60, _source_ok_T_61)
node _source_ok_T_63 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_64 = and(_source_ok_T_62, _source_ok_T_63)
node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0)
node _source_ok_T_65 = shr(io.in.d.bits.source, 2)
node _source_ok_T_66 = eq(_source_ok_T_65, UInt<2>(0h2))
node _source_ok_T_67 = leq(UInt<1>(0h0), source_ok_uncommonBits_8)
node _source_ok_T_68 = and(_source_ok_T_66, _source_ok_T_67)
node _source_ok_T_69 = leq(source_ok_uncommonBits_8, UInt<2>(0h3))
node _source_ok_T_70 = and(_source_ok_T_68, _source_ok_T_69)
node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0)
node _source_ok_T_71 = shr(io.in.d.bits.source, 2)
node _source_ok_T_72 = eq(_source_ok_T_71, UInt<2>(0h3))
node _source_ok_T_73 = leq(UInt<1>(0h0), source_ok_uncommonBits_9)
node _source_ok_T_74 = and(_source_ok_T_72, _source_ok_T_73)
node _source_ok_T_75 = leq(source_ok_uncommonBits_9, UInt<2>(0h3))
node _source_ok_T_76 = and(_source_ok_T_74, _source_ok_T_75)
node _source_ok_uncommonBits_T_10 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 1, 0)
node _source_ok_T_77 = shr(io.in.d.bits.source, 2)
node _source_ok_T_78 = eq(_source_ok_T_77, UInt<4>(0ha))
node _source_ok_T_79 = leq(UInt<1>(0h0), source_ok_uncommonBits_10)
node _source_ok_T_80 = and(_source_ok_T_78, _source_ok_T_79)
node _source_ok_T_81 = leq(source_ok_uncommonBits_10, UInt<2>(0h2))
node _source_ok_T_82 = and(_source_ok_T_80, _source_ok_T_81)
node _source_ok_T_83 = eq(io.in.d.bits.source, UInt<6>(0h2b))
node _source_ok_T_84 = eq(io.in.d.bits.source, UInt<6>(0h2c))
node _source_ok_uncommonBits_T_11 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 1, 0)
node _source_ok_T_85 = shr(io.in.d.bits.source, 2)
node _source_ok_T_86 = eq(_source_ok_T_85, UInt<4>(0h8))
node _source_ok_T_87 = leq(UInt<1>(0h0), source_ok_uncommonBits_11)
node _source_ok_T_88 = and(_source_ok_T_86, _source_ok_T_87)
node _source_ok_T_89 = leq(source_ok_uncommonBits_11, UInt<2>(0h2))
node _source_ok_T_90 = and(_source_ok_T_88, _source_ok_T_89)
node _source_ok_T_91 = eq(io.in.d.bits.source, UInt<6>(0h23))
node _source_ok_T_92 = eq(io.in.d.bits.source, UInt<6>(0h24))
node _source_ok_T_93 = eq(io.in.d.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE_1 : UInt<1>[12]
connect _source_ok_WIRE_1[0], _source_ok_T_52
connect _source_ok_WIRE_1[1], _source_ok_T_58
connect _source_ok_WIRE_1[2], _source_ok_T_64
connect _source_ok_WIRE_1[3], _source_ok_T_70
connect _source_ok_WIRE_1[4], _source_ok_T_76
connect _source_ok_WIRE_1[5], _source_ok_T_82
connect _source_ok_WIRE_1[6], _source_ok_T_83
connect _source_ok_WIRE_1[7], _source_ok_T_84
connect _source_ok_WIRE_1[8], _source_ok_T_90
connect _source_ok_WIRE_1[9], _source_ok_T_91
connect _source_ok_WIRE_1[10], _source_ok_T_92
connect _source_ok_WIRE_1[11], _source_ok_T_93
node _source_ok_T_94 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_95 = or(_source_ok_T_94, _source_ok_WIRE_1[2])
node _source_ok_T_96 = or(_source_ok_T_95, _source_ok_WIRE_1[3])
node _source_ok_T_97 = or(_source_ok_T_96, _source_ok_WIRE_1[4])
node _source_ok_T_98 = or(_source_ok_T_97, _source_ok_WIRE_1[5])
node _source_ok_T_99 = or(_source_ok_T_98, _source_ok_WIRE_1[6])
node _source_ok_T_100 = or(_source_ok_T_99, _source_ok_WIRE_1[7])
node _source_ok_T_101 = or(_source_ok_T_100, _source_ok_WIRE_1[8])
node _source_ok_T_102 = or(_source_ok_T_101, _source_ok_WIRE_1[9])
node _source_ok_T_103 = or(_source_ok_T_102, _source_ok_WIRE_1[10])
node source_ok_1 = or(_source_ok_T_103, _source_ok_WIRE_1[11])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_1035 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1035 :
node _T_1036 = asUInt(reset)
node _T_1037 = eq(_T_1036, UInt<1>(0h0))
when _T_1037 :
node _T_1038 = eq(source_ok_1, UInt<1>(0h0))
when _T_1038 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_1039 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1040 = asUInt(reset)
node _T_1041 = eq(_T_1040, UInt<1>(0h0))
when _T_1041 :
node _T_1042 = eq(_T_1039, UInt<1>(0h0))
when _T_1042 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1039, UInt<1>(0h1), "") : assert_54
node _T_1043 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1044 = asUInt(reset)
node _T_1045 = eq(_T_1044, UInt<1>(0h0))
when _T_1045 :
node _T_1046 = eq(_T_1043, UInt<1>(0h0))
when _T_1046 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1043, UInt<1>(0h1), "") : assert_55
node _T_1047 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1048 = asUInt(reset)
node _T_1049 = eq(_T_1048, UInt<1>(0h0))
when _T_1049 :
node _T_1050 = eq(_T_1047, UInt<1>(0h0))
when _T_1050 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1047, UInt<1>(0h1), "") : assert_56
node _T_1051 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1052 = asUInt(reset)
node _T_1053 = eq(_T_1052, UInt<1>(0h0))
when _T_1053 :
node _T_1054 = eq(_T_1051, UInt<1>(0h0))
when _T_1054 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1051, UInt<1>(0h1), "") : assert_57
node _T_1055 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1055 :
node _T_1056 = asUInt(reset)
node _T_1057 = eq(_T_1056, UInt<1>(0h0))
when _T_1057 :
node _T_1058 = eq(source_ok_1, UInt<1>(0h0))
when _T_1058 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1059 = asUInt(reset)
node _T_1060 = eq(_T_1059, UInt<1>(0h0))
when _T_1060 :
node _T_1061 = eq(sink_ok, UInt<1>(0h0))
when _T_1061 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1062 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1063 = asUInt(reset)
node _T_1064 = eq(_T_1063, UInt<1>(0h0))
when _T_1064 :
node _T_1065 = eq(_T_1062, UInt<1>(0h0))
when _T_1065 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1062, UInt<1>(0h1), "") : assert_60
node _T_1066 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1067 = asUInt(reset)
node _T_1068 = eq(_T_1067, UInt<1>(0h0))
when _T_1068 :
node _T_1069 = eq(_T_1066, UInt<1>(0h0))
when _T_1069 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1066, UInt<1>(0h1), "") : assert_61
node _T_1070 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1071 = asUInt(reset)
node _T_1072 = eq(_T_1071, UInt<1>(0h0))
when _T_1072 :
node _T_1073 = eq(_T_1070, UInt<1>(0h0))
when _T_1073 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1070, UInt<1>(0h1), "") : assert_62
node _T_1074 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1075 = asUInt(reset)
node _T_1076 = eq(_T_1075, UInt<1>(0h0))
when _T_1076 :
node _T_1077 = eq(_T_1074, UInt<1>(0h0))
when _T_1077 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1074, UInt<1>(0h1), "") : assert_63
node _T_1078 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1079 = or(UInt<1>(0h0), _T_1078)
node _T_1080 = asUInt(reset)
node _T_1081 = eq(_T_1080, UInt<1>(0h0))
when _T_1081 :
node _T_1082 = eq(_T_1079, UInt<1>(0h0))
when _T_1082 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1079, UInt<1>(0h1), "") : assert_64
node _T_1083 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1083 :
node _T_1084 = asUInt(reset)
node _T_1085 = eq(_T_1084, UInt<1>(0h0))
when _T_1085 :
node _T_1086 = eq(source_ok_1, UInt<1>(0h0))
when _T_1086 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1087 = asUInt(reset)
node _T_1088 = eq(_T_1087, UInt<1>(0h0))
when _T_1088 :
node _T_1089 = eq(sink_ok, UInt<1>(0h0))
when _T_1089 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1090 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1091 = asUInt(reset)
node _T_1092 = eq(_T_1091, UInt<1>(0h0))
when _T_1092 :
node _T_1093 = eq(_T_1090, UInt<1>(0h0))
when _T_1093 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1090, UInt<1>(0h1), "") : assert_67
node _T_1094 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1095 = asUInt(reset)
node _T_1096 = eq(_T_1095, UInt<1>(0h0))
when _T_1096 :
node _T_1097 = eq(_T_1094, UInt<1>(0h0))
when _T_1097 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1094, UInt<1>(0h1), "") : assert_68
node _T_1098 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1099 = asUInt(reset)
node _T_1100 = eq(_T_1099, UInt<1>(0h0))
when _T_1100 :
node _T_1101 = eq(_T_1098, UInt<1>(0h0))
when _T_1101 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1098, UInt<1>(0h1), "") : assert_69
node _T_1102 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1103 = or(_T_1102, io.in.d.bits.corrupt)
node _T_1104 = asUInt(reset)
node _T_1105 = eq(_T_1104, UInt<1>(0h0))
when _T_1105 :
node _T_1106 = eq(_T_1103, UInt<1>(0h0))
when _T_1106 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1103, UInt<1>(0h1), "") : assert_70
node _T_1107 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1108 = or(UInt<1>(0h0), _T_1107)
node _T_1109 = asUInt(reset)
node _T_1110 = eq(_T_1109, UInt<1>(0h0))
when _T_1110 :
node _T_1111 = eq(_T_1108, UInt<1>(0h0))
when _T_1111 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1108, UInt<1>(0h1), "") : assert_71
node _T_1112 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1112 :
node _T_1113 = asUInt(reset)
node _T_1114 = eq(_T_1113, UInt<1>(0h0))
when _T_1114 :
node _T_1115 = eq(source_ok_1, UInt<1>(0h0))
when _T_1115 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1116 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1117 = asUInt(reset)
node _T_1118 = eq(_T_1117, UInt<1>(0h0))
when _T_1118 :
node _T_1119 = eq(_T_1116, UInt<1>(0h0))
when _T_1119 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1116, UInt<1>(0h1), "") : assert_73
node _T_1120 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1121 = asUInt(reset)
node _T_1122 = eq(_T_1121, UInt<1>(0h0))
when _T_1122 :
node _T_1123 = eq(_T_1120, UInt<1>(0h0))
when _T_1123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1120, UInt<1>(0h1), "") : assert_74
node _T_1124 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1125 = or(UInt<1>(0h0), _T_1124)
node _T_1126 = asUInt(reset)
node _T_1127 = eq(_T_1126, UInt<1>(0h0))
when _T_1127 :
node _T_1128 = eq(_T_1125, UInt<1>(0h0))
when _T_1128 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1125, UInt<1>(0h1), "") : assert_75
node _T_1129 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1129 :
node _T_1130 = asUInt(reset)
node _T_1131 = eq(_T_1130, UInt<1>(0h0))
when _T_1131 :
node _T_1132 = eq(source_ok_1, UInt<1>(0h0))
when _T_1132 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1133 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1134 = asUInt(reset)
node _T_1135 = eq(_T_1134, UInt<1>(0h0))
when _T_1135 :
node _T_1136 = eq(_T_1133, UInt<1>(0h0))
when _T_1136 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1133, UInt<1>(0h1), "") : assert_77
node _T_1137 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1138 = or(_T_1137, io.in.d.bits.corrupt)
node _T_1139 = asUInt(reset)
node _T_1140 = eq(_T_1139, UInt<1>(0h0))
when _T_1140 :
node _T_1141 = eq(_T_1138, UInt<1>(0h0))
when _T_1141 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1138, UInt<1>(0h1), "") : assert_78
node _T_1142 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1143 = or(UInt<1>(0h0), _T_1142)
node _T_1144 = asUInt(reset)
node _T_1145 = eq(_T_1144, UInt<1>(0h0))
when _T_1145 :
node _T_1146 = eq(_T_1143, UInt<1>(0h0))
when _T_1146 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1143, UInt<1>(0h1), "") : assert_79
node _T_1147 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1147 :
node _T_1148 = asUInt(reset)
node _T_1149 = eq(_T_1148, UInt<1>(0h0))
when _T_1149 :
node _T_1150 = eq(source_ok_1, UInt<1>(0h0))
when _T_1150 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1151 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1152 = asUInt(reset)
node _T_1153 = eq(_T_1152, UInt<1>(0h0))
when _T_1153 :
node _T_1154 = eq(_T_1151, UInt<1>(0h0))
when _T_1154 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1151, UInt<1>(0h1), "") : assert_81
node _T_1155 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1156 = asUInt(reset)
node _T_1157 = eq(_T_1156, UInt<1>(0h0))
when _T_1157 :
node _T_1158 = eq(_T_1155, UInt<1>(0h0))
when _T_1158 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1155, UInt<1>(0h1), "") : assert_82
node _T_1159 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1160 = or(UInt<1>(0h0), _T_1159)
node _T_1161 = asUInt(reset)
node _T_1162 = eq(_T_1161, UInt<1>(0h0))
when _T_1162 :
node _T_1163 = eq(_T_1160, UInt<1>(0h0))
when _T_1163 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1160, UInt<1>(0h1), "") : assert_83
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.mask, UInt<8>(0h0)
connect _WIRE_4.bits.address, UInt<12>(0h0)
connect _WIRE_4.bits.source, UInt<7>(0h0)
connect _WIRE_4.bits.size, UInt<3>(0h0)
connect _WIRE_4.bits.param, UInt<2>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1164 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1165 = asUInt(reset)
node _T_1166 = eq(_T_1165, UInt<1>(0h0))
when _T_1166 :
node _T_1167 = eq(_T_1164, UInt<1>(0h0))
when _T_1167 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1164, UInt<1>(0h1), "") : assert_84
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<12>(0h0)
connect _WIRE_6.bits.source, UInt<7>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1168 = eq(_WIRE_7.valid, UInt<1>(0h0))
node _T_1169 = asUInt(reset)
node _T_1170 = eq(_T_1169, UInt<1>(0h0))
when _T_1170 :
node _T_1171 = eq(_T_1168, UInt<1>(0h0))
when _T_1171 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1168, UInt<1>(0h1), "") : assert_85
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_8.bits.sink, UInt<1>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1172 = eq(_WIRE_9.valid, UInt<1>(0h0))
node _T_1173 = asUInt(reset)
node _T_1174 = eq(_T_1173, UInt<1>(0h0))
when _T_1174 :
node _T_1175 = eq(_T_1172, UInt<1>(0h0))
when _T_1175 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1172, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1176 = eq(a_first, UInt<1>(0h0))
node _T_1177 = and(io.in.a.valid, _T_1176)
when _T_1177 :
node _T_1178 = eq(io.in.a.bits.opcode, opcode)
node _T_1179 = asUInt(reset)
node _T_1180 = eq(_T_1179, UInt<1>(0h0))
when _T_1180 :
node _T_1181 = eq(_T_1178, UInt<1>(0h0))
when _T_1181 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1178, UInt<1>(0h1), "") : assert_87
node _T_1182 = eq(io.in.a.bits.param, param)
node _T_1183 = asUInt(reset)
node _T_1184 = eq(_T_1183, UInt<1>(0h0))
when _T_1184 :
node _T_1185 = eq(_T_1182, UInt<1>(0h0))
when _T_1185 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1182, UInt<1>(0h1), "") : assert_88
node _T_1186 = eq(io.in.a.bits.size, size)
node _T_1187 = asUInt(reset)
node _T_1188 = eq(_T_1187, UInt<1>(0h0))
when _T_1188 :
node _T_1189 = eq(_T_1186, UInt<1>(0h0))
when _T_1189 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1186, UInt<1>(0h1), "") : assert_89
node _T_1190 = eq(io.in.a.bits.source, source)
node _T_1191 = asUInt(reset)
node _T_1192 = eq(_T_1191, UInt<1>(0h0))
when _T_1192 :
node _T_1193 = eq(_T_1190, UInt<1>(0h0))
when _T_1193 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1190, UInt<1>(0h1), "") : assert_90
node _T_1194 = eq(io.in.a.bits.address, address)
node _T_1195 = asUInt(reset)
node _T_1196 = eq(_T_1195, UInt<1>(0h0))
when _T_1196 :
node _T_1197 = eq(_T_1194, UInt<1>(0h0))
when _T_1197 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1194, UInt<1>(0h1), "") : assert_91
node _T_1198 = and(io.in.a.ready, io.in.a.valid)
node _T_1199 = and(_T_1198, a_first)
when _T_1199 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1200 = eq(d_first, UInt<1>(0h0))
node _T_1201 = and(io.in.d.valid, _T_1200)
when _T_1201 :
node _T_1202 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1203 = asUInt(reset)
node _T_1204 = eq(_T_1203, UInt<1>(0h0))
when _T_1204 :
node _T_1205 = eq(_T_1202, UInt<1>(0h0))
when _T_1205 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1202, UInt<1>(0h1), "") : assert_92
node _T_1206 = eq(io.in.d.bits.param, param_1)
node _T_1207 = asUInt(reset)
node _T_1208 = eq(_T_1207, UInt<1>(0h0))
when _T_1208 :
node _T_1209 = eq(_T_1206, UInt<1>(0h0))
when _T_1209 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1206, UInt<1>(0h1), "") : assert_93
node _T_1210 = eq(io.in.d.bits.size, size_1)
node _T_1211 = asUInt(reset)
node _T_1212 = eq(_T_1211, UInt<1>(0h0))
when _T_1212 :
node _T_1213 = eq(_T_1210, UInt<1>(0h0))
when _T_1213 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1210, UInt<1>(0h1), "") : assert_94
node _T_1214 = eq(io.in.d.bits.source, source_1)
node _T_1215 = asUInt(reset)
node _T_1216 = eq(_T_1215, UInt<1>(0h0))
when _T_1216 :
node _T_1217 = eq(_T_1214, UInt<1>(0h0))
when _T_1217 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1214, UInt<1>(0h1), "") : assert_95
node _T_1218 = eq(io.in.d.bits.sink, sink)
node _T_1219 = asUInt(reset)
node _T_1220 = eq(_T_1219, UInt<1>(0h0))
when _T_1220 :
node _T_1221 = eq(_T_1218, UInt<1>(0h0))
when _T_1221 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1218, UInt<1>(0h1), "") : assert_96
node _T_1222 = eq(io.in.d.bits.denied, denied)
node _T_1223 = asUInt(reset)
node _T_1224 = eq(_T_1223, UInt<1>(0h0))
when _T_1224 :
node _T_1225 = eq(_T_1222, UInt<1>(0h0))
when _T_1225 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1222, UInt<1>(0h1), "") : assert_97
node _T_1226 = and(io.in.d.ready, io.in.d.valid)
node _T_1227 = and(_T_1226, d_first)
when _T_1227 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<65>
connect a_set, UInt<65>(0h0)
wire a_set_wo_ready : UInt<65>
connect a_set_wo_ready, UInt<65>(0h0)
wire a_opcodes_set : UInt<260>
connect a_opcodes_set, UInt<260>(0h0)
wire a_sizes_set : UInt<260>
connect a_sizes_set, UInt<260>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_1228 = and(io.in.a.valid, a_first_1)
node _T_1229 = and(_T_1228, UInt<1>(0h1))
when _T_1229 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1230 = and(io.in.a.ready, io.in.a.valid)
node _T_1231 = and(_T_1230, a_first_1)
node _T_1232 = and(_T_1231, UInt<1>(0h1))
when _T_1232 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1233 = dshr(inflight, io.in.a.bits.source)
node _T_1234 = bits(_T_1233, 0, 0)
node _T_1235 = eq(_T_1234, UInt<1>(0h0))
node _T_1236 = asUInt(reset)
node _T_1237 = eq(_T_1236, UInt<1>(0h0))
when _T_1237 :
node _T_1238 = eq(_T_1235, UInt<1>(0h0))
when _T_1238 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1235, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<65>
connect d_clr, UInt<65>(0h0)
wire d_clr_wo_ready : UInt<65>
connect d_clr_wo_ready, UInt<65>(0h0)
wire d_opcodes_clr : UInt<260>
connect d_opcodes_clr, UInt<260>(0h0)
wire d_sizes_clr : UInt<260>
connect d_sizes_clr, UInt<260>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1239 = and(io.in.d.valid, d_first_1)
node _T_1240 = and(_T_1239, UInt<1>(0h1))
node _T_1241 = eq(d_release_ack, UInt<1>(0h0))
node _T_1242 = and(_T_1240, _T_1241)
when _T_1242 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1243 = and(io.in.d.ready, io.in.d.valid)
node _T_1244 = and(_T_1243, d_first_1)
node _T_1245 = and(_T_1244, UInt<1>(0h1))
node _T_1246 = eq(d_release_ack, UInt<1>(0h0))
node _T_1247 = and(_T_1245, _T_1246)
when _T_1247 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1248 = and(io.in.d.valid, d_first_1)
node _T_1249 = and(_T_1248, UInt<1>(0h1))
node _T_1250 = eq(d_release_ack, UInt<1>(0h0))
node _T_1251 = and(_T_1249, _T_1250)
when _T_1251 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1252 = dshr(inflight, io.in.d.bits.source)
node _T_1253 = bits(_T_1252, 0, 0)
node _T_1254 = or(_T_1253, same_cycle_resp)
node _T_1255 = asUInt(reset)
node _T_1256 = eq(_T_1255, UInt<1>(0h0))
when _T_1256 :
node _T_1257 = eq(_T_1254, UInt<1>(0h0))
when _T_1257 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1254, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1258 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1259 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1260 = or(_T_1258, _T_1259)
node _T_1261 = asUInt(reset)
node _T_1262 = eq(_T_1261, UInt<1>(0h0))
when _T_1262 :
node _T_1263 = eq(_T_1260, UInt<1>(0h0))
when _T_1263 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1260, UInt<1>(0h1), "") : assert_100
node _T_1264 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1265 = asUInt(reset)
node _T_1266 = eq(_T_1265, UInt<1>(0h0))
when _T_1266 :
node _T_1267 = eq(_T_1264, UInt<1>(0h0))
when _T_1267 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1264, UInt<1>(0h1), "") : assert_101
else :
node _T_1268 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1269 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1270 = or(_T_1268, _T_1269)
node _T_1271 = asUInt(reset)
node _T_1272 = eq(_T_1271, UInt<1>(0h0))
when _T_1272 :
node _T_1273 = eq(_T_1270, UInt<1>(0h0))
when _T_1273 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1270, UInt<1>(0h1), "") : assert_102
node _T_1274 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1275 = asUInt(reset)
node _T_1276 = eq(_T_1275, UInt<1>(0h0))
when _T_1276 :
node _T_1277 = eq(_T_1274, UInt<1>(0h0))
when _T_1277 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1274, UInt<1>(0h1), "") : assert_103
node _T_1278 = and(io.in.d.valid, d_first_1)
node _T_1279 = and(_T_1278, a_first_1)
node _T_1280 = and(_T_1279, io.in.a.valid)
node _T_1281 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1282 = and(_T_1280, _T_1281)
node _T_1283 = eq(d_release_ack, UInt<1>(0h0))
node _T_1284 = and(_T_1282, _T_1283)
when _T_1284 :
node _T_1285 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1286 = or(_T_1285, io.in.a.ready)
node _T_1287 = asUInt(reset)
node _T_1288 = eq(_T_1287, UInt<1>(0h0))
when _T_1288 :
node _T_1289 = eq(_T_1286, UInt<1>(0h0))
when _T_1289 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1286, UInt<1>(0h1), "") : assert_104
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_52
node _T_1290 = orr(inflight)
node _T_1291 = eq(_T_1290, UInt<1>(0h0))
node _T_1292 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1293 = or(_T_1291, _T_1292)
node _T_1294 = lt(watchdog, plusarg_reader.out)
node _T_1295 = or(_T_1293, _T_1294)
node _T_1296 = asUInt(reset)
node _T_1297 = eq(_T_1296, UInt<1>(0h0))
when _T_1297 :
node _T_1298 = eq(_T_1295, UInt<1>(0h0))
when _T_1298 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_1295, UInt<1>(0h1), "") : assert_105
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1299 = and(io.in.a.ready, io.in.a.valid)
node _T_1300 = and(io.in.d.ready, io.in.d.valid)
node _T_1301 = or(_T_1299, _T_1300)
when _T_1301 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<12>(0h0)
connect _c_first_WIRE.bits.source, UInt<7>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<12>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<65>
connect c_set, UInt<65>(0h0)
wire c_set_wo_ready : UInt<65>
connect c_set_wo_ready, UInt<65>(0h0)
wire c_opcodes_set : UInt<260>
connect c_opcodes_set, UInt<260>(0h0)
wire c_sizes_set : UInt<260>
connect c_sizes_set, UInt<260>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<12>(0h0)
connect _WIRE_10.bits.source, UInt<7>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1302 = and(_WIRE_11.valid, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<12>(0h0)
connect _WIRE_12.bits.source, UInt<7>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1303 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1304 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1305 = and(_T_1303, _T_1304)
node _T_1306 = and(_T_1302, _T_1305)
when _T_1306 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<12>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<12>(0h0)
connect _WIRE_14.bits.source, UInt<7>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1307 = and(_WIRE_15.ready, _WIRE_15.valid)
node _T_1308 = and(_T_1307, c_first)
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<12>(0h0)
connect _WIRE_16.bits.source, UInt<7>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1309 = bits(_WIRE_17.bits.opcode, 2, 2)
node _T_1310 = bits(_WIRE_17.bits.opcode, 1, 1)
node _T_1311 = and(_T_1309, _T_1310)
node _T_1312 = and(_T_1308, _T_1311)
when _T_1312 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<12>(0h0)
connect _c_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<12>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<12>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<12>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<12>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<12>(0h0)
connect _WIRE_18.bits.source, UInt<7>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1313 = dshr(inflight_1, _WIRE_19.bits.source)
node _T_1314 = bits(_T_1313, 0, 0)
node _T_1315 = eq(_T_1314, UInt<1>(0h0))
node _T_1316 = asUInt(reset)
node _T_1317 = eq(_T_1316, UInt<1>(0h0))
when _T_1317 :
node _T_1318 = eq(_T_1315, UInt<1>(0h0))
when _T_1318 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1315, UInt<1>(0h1), "") : assert_106
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<12>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<12>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<65>
connect d_clr_1, UInt<65>(0h0)
wire d_clr_wo_ready_1 : UInt<65>
connect d_clr_wo_ready_1, UInt<65>(0h0)
wire d_opcodes_clr_1 : UInt<260>
connect d_opcodes_clr_1, UInt<260>(0h0)
wire d_sizes_clr_1 : UInt<260>
connect d_sizes_clr_1, UInt<260>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1319 = and(io.in.d.valid, d_first_2)
node _T_1320 = and(_T_1319, UInt<1>(0h1))
node _T_1321 = and(_T_1320, d_release_ack_1)
when _T_1321 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1322 = and(io.in.d.ready, io.in.d.valid)
node _T_1323 = and(_T_1322, d_first_2)
node _T_1324 = and(_T_1323, UInt<1>(0h1))
node _T_1325 = and(_T_1324, d_release_ack_1)
when _T_1325 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1326 = and(io.in.d.valid, d_first_2)
node _T_1327 = and(_T_1326, UInt<1>(0h1))
node _T_1328 = and(_T_1327, d_release_ack_1)
when _T_1328 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<12>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<12>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<12>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1329 = dshr(inflight_1, io.in.d.bits.source)
node _T_1330 = bits(_T_1329, 0, 0)
node _T_1331 = or(_T_1330, same_cycle_resp_1)
node _T_1332 = asUInt(reset)
node _T_1333 = eq(_T_1332, UInt<1>(0h0))
when _T_1333 :
node _T_1334 = eq(_T_1331, UInt<1>(0h0))
when _T_1334 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107
assert(clock, _T_1331, UInt<1>(0h1), "") : assert_107
when same_cycle_resp_1 :
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<12>(0h0)
connect _WIRE_20.bits.source, UInt<7>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1335 = eq(io.in.d.bits.size, _WIRE_21.bits.size)
node _T_1336 = asUInt(reset)
node _T_1337 = eq(_T_1336, UInt<1>(0h0))
when _T_1337 :
node _T_1338 = eq(_T_1335, UInt<1>(0h0))
when _T_1338 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1335, UInt<1>(0h1), "") : assert_108
else :
node _T_1339 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1340 = asUInt(reset)
node _T_1341 = eq(_T_1340, UInt<1>(0h0))
when _T_1341 :
node _T_1342 = eq(_T_1339, UInt<1>(0h0))
when _T_1342 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1339, UInt<1>(0h1), "") : assert_109
node _T_1343 = and(io.in.d.valid, d_first_2)
node _T_1344 = and(_T_1343, c_first)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<12>(0h0)
connect _WIRE_22.bits.source, UInt<7>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1345 = and(_T_1344, _WIRE_23.valid)
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<12>(0h0)
connect _WIRE_24.bits.source, UInt<7>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1346 = eq(_WIRE_25.bits.source, io.in.d.bits.source)
node _T_1347 = and(_T_1345, _T_1346)
node _T_1348 = and(_T_1347, d_release_ack_1)
node _T_1349 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1350 = and(_T_1348, _T_1349)
when _T_1350 :
node _T_1351 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<64>(0h0)
connect _WIRE_26.bits.address, UInt<12>(0h0)
connect _WIRE_26.bits.source, UInt<7>(0h0)
connect _WIRE_26.bits.size, UInt<3>(0h0)
connect _WIRE_26.bits.param, UInt<3>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
node _T_1352 = or(_T_1351, _WIRE_27.ready)
node _T_1353 = asUInt(reset)
node _T_1354 = eq(_T_1353, UInt<1>(0h0))
when _T_1354 :
node _T_1355 = eq(_T_1352, UInt<1>(0h0))
when _T_1355 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1352, UInt<1>(0h1), "") : assert_110
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_53
node _T_1356 = orr(inflight_1)
node _T_1357 = eq(_T_1356, UInt<1>(0h0))
node _T_1358 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1359 = or(_T_1357, _T_1358)
node _T_1360 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1361 = or(_T_1359, _T_1360)
node _T_1362 = asUInt(reset)
node _T_1363 = eq(_T_1362, UInt<1>(0h0))
when _T_1363 :
node _T_1364 = eq(_T_1361, UInt<1>(0h0))
when _T_1364 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_1361, UInt<1>(0h1), "") : assert_111
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<64>(0h0)
connect _WIRE_28.bits.address, UInt<12>(0h0)
connect _WIRE_28.bits.source, UInt<7>(0h0)
connect _WIRE_28.bits.size, UInt<3>(0h0)
connect _WIRE_28.bits.param, UInt<3>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
node _T_1365 = and(_WIRE_29.ready, _WIRE_29.valid)
node _T_1366 = and(io.in.d.ready, io.in.d.valid)
node _T_1367 = or(_T_1365, _T_1366)
when _T_1367 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_26( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [11:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [11:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_61 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_63 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_67 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_69 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_73 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_75 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_79 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_87 = 1'h1; // @[Parameters.scala:56:32]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_first_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_first_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_first_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_first_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_set_wo_ready_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_set_wo_ready_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_opcodes_set_interm_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_opcodes_set_interm_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_sizes_set_interm_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_sizes_set_interm_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_opcodes_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_opcodes_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_sizes_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_sizes_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_probe_ack_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_probe_ack_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_probe_ack_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_probe_ack_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _same_cycle_resp_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _same_cycle_resp_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _same_cycle_resp_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _same_cycle_resp_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _same_cycle_resp_WIRE_4_bits_address = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _same_cycle_resp_WIRE_5_bits_address = 12'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54]
wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52]
wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79]
wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35]
wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35]
wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34]
wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34]
wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34]
wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_25 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_33 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_26 = _source_ok_T_25 == 5'hA; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_29 = source_ok_uncommonBits_4 != 2'h3; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_30 = _source_ok_T_28 & _source_ok_T_29; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31]
wire _source_ok_T_31 = io_in_a_bits_source_0 == 7'h2B; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_6 = _source_ok_T_31; // @[Parameters.scala:1138:31]
wire _source_ok_T_32 = io_in_a_bits_source_0 == 7'h2C; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_34 = _source_ok_T_33 == 5'h8; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_37 = source_ok_uncommonBits_5 != 2'h3; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_38 = _source_ok_T_36 & _source_ok_T_37; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_8 = _source_ok_T_38; // @[Parameters.scala:1138:31]
wire _source_ok_T_39 = io_in_a_bits_source_0 == 7'h23; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_9 = _source_ok_T_39; // @[Parameters.scala:1138:31]
wire _source_ok_T_40 = io_in_a_bits_source_0 == 7'h24; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_10 = _source_ok_T_40; // @[Parameters.scala:1138:31]
wire _source_ok_T_41 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_11 = _source_ok_T_41; // @[Parameters.scala:1138:31]
wire _source_ok_T_42 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_43 = _source_ok_T_42 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_44 = _source_ok_T_43 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_45 = _source_ok_T_44 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_46 = _source_ok_T_45 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_47 = _source_ok_T_46 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_48 = _source_ok_T_47 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_49 = _source_ok_T_48 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_50 = _source_ok_T_49 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_51 = _source_ok_T_50 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_51 | _source_ok_WIRE_11; // @[Parameters.scala:1138:31, :1139:46]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [11:0] _is_aligned_T = {6'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 12'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_53 = _uncommonBits_T_53[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_55 = _uncommonBits_T_55[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_58 = _uncommonBits_T_58[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_59 = _uncommonBits_T_59[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_60 = _uncommonBits_T_60[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_61 = _uncommonBits_T_61[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_62 = _uncommonBits_T_62[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_64 = _uncommonBits_T_64[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_65 = _uncommonBits_T_65[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_52 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_52; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_53 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_59 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_65 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_71 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_77 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_85 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_54 = _source_ok_T_53 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_58; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_60 = _source_ok_T_59 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_62 = _source_ok_T_60; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_64 = _source_ok_T_62; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_64; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_66 = _source_ok_T_65 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_68 = _source_ok_T_66; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_70 = _source_ok_T_68; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_70; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_72 = _source_ok_T_71 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_74 = _source_ok_T_72; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_76 = _source_ok_T_74; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_76; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_78 = _source_ok_T_77 == 5'hA; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_80 = _source_ok_T_78; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_81 = source_ok_uncommonBits_10 != 2'h3; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_82 = _source_ok_T_80 & _source_ok_T_81; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_1_5 = _source_ok_T_82; // @[Parameters.scala:1138:31]
wire _source_ok_T_83 = io_in_d_bits_source_0 == 7'h2B; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_6 = _source_ok_T_83; // @[Parameters.scala:1138:31]
wire _source_ok_T_84 = io_in_d_bits_source_0 == 7'h2C; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_7 = _source_ok_T_84; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_86 = _source_ok_T_85 == 5'h8; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_88 = _source_ok_T_86; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_89 = source_ok_uncommonBits_11 != 2'h3; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_90 = _source_ok_T_88 & _source_ok_T_89; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_1_8 = _source_ok_T_90; // @[Parameters.scala:1138:31]
wire _source_ok_T_91 = io_in_d_bits_source_0 == 7'h23; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_9 = _source_ok_T_91; // @[Parameters.scala:1138:31]
wire _source_ok_T_92 = io_in_d_bits_source_0 == 7'h24; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_10 = _source_ok_T_92; // @[Parameters.scala:1138:31]
wire _source_ok_T_93 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_11 = _source_ok_T_93; // @[Parameters.scala:1138:31]
wire _source_ok_T_94 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_95 = _source_ok_T_94 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_96 = _source_ok_T_95 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_97 = _source_ok_T_96 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_98 = _source_ok_T_97 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_99 = _source_ok_T_98 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_100 = _source_ok_T_99 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_101 = _source_ok_T_100 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_102 = _source_ok_T_101 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_103 = _source_ok_T_102 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_103 | _source_ok_WIRE_1_11; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1299 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1299; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1299; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [6:0] source; // @[Monitor.scala:390:22]
reg [11:0] address; // @[Monitor.scala:391:22]
wire _T_1367 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1367; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1367; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1367; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [6:0] source_1; // @[Monitor.scala:541:22]
reg [64:0] inflight; // @[Monitor.scala:614:27]
reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [259:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [64:0] a_set; // @[Monitor.scala:626:34]
wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [259:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [127:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1232 = _T_1299 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1232 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1232 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1232 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1232 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1232 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [64:0] d_clr; // @[Monitor.scala:664:34]
wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1278 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1278 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1247 = _T_1367 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1247 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1247 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1247 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [259:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [64:0] inflight_1; // @[Monitor.scala:726:35]
wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [64:0] d_clr_1; // @[Monitor.scala:774:34]
wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1343 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1343 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1325 = _T_1367 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1325 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1325 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1325 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113]
wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncQueueSource_TLBundleA_a32d64s4k1z3u :
input clock : Clock
input reset : Reset
output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, async : { mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}[8], flip ridx : UInt<4>, widx : UInt<4>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}}
wire sink_ready : UInt<1>
connect sink_ready, UInt<1>(0h1)
reg mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}[8], clock
node _widx_T = asAsyncReset(reset)
node _widx_T_1 = and(io.enq.ready, io.enq.valid)
node _widx_T_2 = eq(sink_ready, UInt<1>(0h0))
wire widx_incremented : UInt<4>
regreset widx_widx_bin : UInt, clock, _widx_T, UInt<1>(0h0)
connect widx_widx_bin, widx_incremented
node _widx_incremented_T = add(widx_widx_bin, _widx_T_1)
node _widx_incremented_T_1 = tail(_widx_incremented_T, 1)
node _widx_incremented_T_2 = mux(_widx_T_2, UInt<1>(0h0), _widx_incremented_T_1)
connect widx_incremented, _widx_incremented_T_2
node _widx_T_3 = shr(widx_incremented, 1)
node widx = xor(widx_incremented, _widx_T_3)
inst ridx_ridx_gray of AsyncResetSynchronizerShiftReg_w4_d3_i0_15
connect ridx_ridx_gray.clock, clock
connect ridx_ridx_gray.reset, reset
connect ridx_ridx_gray.io.d, io.async.ridx
wire ridx : UInt<4>
connect ridx, ridx_ridx_gray.io.q
node _ready_T = xor(ridx, UInt<4>(0hc))
node _ready_T_1 = neq(widx, _ready_T)
node ready = and(sink_ready, _ready_T_1)
node _index_T = bits(io.async.widx, 2, 0)
node _index_T_1 = bits(io.async.widx, 3, 3)
node _index_T_2 = shl(_index_T_1, 2)
node index = xor(_index_T, _index_T_2)
node _T = and(io.enq.ready, io.enq.valid)
when _T :
connect mem[index], io.enq.bits
node _ready_reg_T = asAsyncReset(reset)
regreset ready_reg : UInt<1>, clock, _ready_reg_T, UInt<1>(0h0)
connect ready_reg, ready
node _io_enq_ready_T = and(ready_reg, sink_ready)
connect io.enq.ready, _io_enq_ready_T
node _widx_reg_T = asAsyncReset(reset)
regreset widx_gray : UInt, clock, _widx_reg_T, UInt<1>(0h0)
connect widx_gray, widx
connect io.async.widx, widx_gray
connect io.async.mem, mem
inst source_valid_0 of AsyncValidSync_60
inst source_valid_1 of AsyncValidSync_61
inst sink_extend of AsyncValidSync_62
inst sink_valid of AsyncValidSync_63
node _source_valid_0_reset_T = asUInt(reset)
node _source_valid_0_reset_T_1 = eq(io.async.safe.sink_reset_n, UInt<1>(0h0))
node _source_valid_0_reset_T_2 = or(_source_valid_0_reset_T, _source_valid_0_reset_T_1)
node _source_valid_0_reset_T_3 = asAsyncReset(_source_valid_0_reset_T_2)
connect source_valid_0.reset, _source_valid_0_reset_T_3
node _source_valid_1_reset_T = asUInt(reset)
node _source_valid_1_reset_T_1 = eq(io.async.safe.sink_reset_n, UInt<1>(0h0))
node _source_valid_1_reset_T_2 = or(_source_valid_1_reset_T, _source_valid_1_reset_T_1)
node _source_valid_1_reset_T_3 = asAsyncReset(_source_valid_1_reset_T_2)
connect source_valid_1.reset, _source_valid_1_reset_T_3
node _sink_extend_reset_T = asUInt(reset)
node _sink_extend_reset_T_1 = eq(io.async.safe.sink_reset_n, UInt<1>(0h0))
node _sink_extend_reset_T_2 = or(_sink_extend_reset_T, _sink_extend_reset_T_1)
node _sink_extend_reset_T_3 = asAsyncReset(_sink_extend_reset_T_2)
connect sink_extend.reset, _sink_extend_reset_T_3
node _sink_valid_reset_T = asAsyncReset(reset)
connect sink_valid.reset, _sink_valid_reset_T
connect source_valid_0.clock, clock
connect source_valid_1.clock, clock
connect sink_extend.clock, clock
connect sink_valid.clock, clock
connect source_valid_0.io.in, UInt<1>(0h1)
connect source_valid_1.io.in, source_valid_0.io.out
connect io.async.safe.widx_valid, source_valid_1.io.out
connect sink_extend.io.in, io.async.safe.ridx_valid
connect sink_valid.io.in, sink_extend.io.out
connect sink_ready, sink_valid.io.out
node _io_async_safe_source_reset_n_T = asUInt(reset)
node _io_async_safe_source_reset_n_T_1 = eq(_io_async_safe_source_reset_n_T, UInt<1>(0h0))
connect io.async.safe.source_reset_n, _io_async_safe_source_reset_n_T_1 | module AsyncQueueSource_TLBundleA_a32d64s4k1z3u( // @[AsyncQueue.scala:70:7]
input clock, // @[AsyncQueue.scala:70:7]
input reset, // @[AsyncQueue.scala:70:7]
output io_enq_ready, // @[AsyncQueue.scala:73:14]
input io_enq_valid, // @[AsyncQueue.scala:73:14]
input [2:0] io_enq_bits_opcode, // @[AsyncQueue.scala:73:14]
input [2:0] io_enq_bits_param, // @[AsyncQueue.scala:73:14]
input [2:0] io_enq_bits_size, // @[AsyncQueue.scala:73:14]
input [3:0] io_enq_bits_source, // @[AsyncQueue.scala:73:14]
input [31:0] io_enq_bits_address, // @[AsyncQueue.scala:73:14]
input [7:0] io_enq_bits_mask, // @[AsyncQueue.scala:73:14]
input [63:0] io_enq_bits_data, // @[AsyncQueue.scala:73:14]
input io_enq_bits_corrupt, // @[AsyncQueue.scala:73:14]
output [2:0] io_async_mem_0_opcode, // @[AsyncQueue.scala:73:14]
output [2:0] io_async_mem_0_param, // @[AsyncQueue.scala:73:14]
output [2:0] io_async_mem_0_size, // @[AsyncQueue.scala:73:14]
output [3:0] io_async_mem_0_source, // @[AsyncQueue.scala:73:14]
output [31:0] io_async_mem_0_address, // @[AsyncQueue.scala:73:14]
output [7:0] io_async_mem_0_mask, // @[AsyncQueue.scala:73:14]
output [63:0] io_async_mem_0_data, // @[AsyncQueue.scala:73:14]
output io_async_mem_0_corrupt, // @[AsyncQueue.scala:73:14]
output [2:0] io_async_mem_1_opcode, // @[AsyncQueue.scala:73:14]
output [2:0] io_async_mem_1_param, // @[AsyncQueue.scala:73:14]
output [2:0] io_async_mem_1_size, // @[AsyncQueue.scala:73:14]
output [3:0] io_async_mem_1_source, // @[AsyncQueue.scala:73:14]
output [31:0] io_async_mem_1_address, // @[AsyncQueue.scala:73:14]
output [7:0] io_async_mem_1_mask, // @[AsyncQueue.scala:73:14]
output [63:0] io_async_mem_1_data, // @[AsyncQueue.scala:73:14]
output io_async_mem_1_corrupt, // @[AsyncQueue.scala:73:14]
output [2:0] io_async_mem_2_opcode, // @[AsyncQueue.scala:73:14]
output [2:0] io_async_mem_2_param, // @[AsyncQueue.scala:73:14]
output [2:0] io_async_mem_2_size, // @[AsyncQueue.scala:73:14]
output [3:0] io_async_mem_2_source, // @[AsyncQueue.scala:73:14]
output [31:0] io_async_mem_2_address, // @[AsyncQueue.scala:73:14]
output [7:0] io_async_mem_2_mask, // @[AsyncQueue.scala:73:14]
output [63:0] io_async_mem_2_data, // @[AsyncQueue.scala:73:14]
output io_async_mem_2_corrupt, // @[AsyncQueue.scala:73:14]
output [2:0] io_async_mem_3_opcode, // @[AsyncQueue.scala:73:14]
output [2:0] io_async_mem_3_param, // @[AsyncQueue.scala:73:14]
output [2:0] io_async_mem_3_size, // @[AsyncQueue.scala:73:14]
output [3:0] io_async_mem_3_source, // @[AsyncQueue.scala:73:14]
output [31:0] io_async_mem_3_address, // @[AsyncQueue.scala:73:14]
output [7:0] io_async_mem_3_mask, // @[AsyncQueue.scala:73:14]
output [63:0] io_async_mem_3_data, // @[AsyncQueue.scala:73:14]
output io_async_mem_3_corrupt, // @[AsyncQueue.scala:73:14]
output [2:0] io_async_mem_4_opcode, // @[AsyncQueue.scala:73:14]
output [2:0] io_async_mem_4_param, // @[AsyncQueue.scala:73:14]
output [2:0] io_async_mem_4_size, // @[AsyncQueue.scala:73:14]
output [3:0] io_async_mem_4_source, // @[AsyncQueue.scala:73:14]
output [31:0] io_async_mem_4_address, // @[AsyncQueue.scala:73:14]
output [7:0] io_async_mem_4_mask, // @[AsyncQueue.scala:73:14]
output [63:0] io_async_mem_4_data, // @[AsyncQueue.scala:73:14]
output io_async_mem_4_corrupt, // @[AsyncQueue.scala:73:14]
output [2:0] io_async_mem_5_opcode, // @[AsyncQueue.scala:73:14]
output [2:0] io_async_mem_5_param, // @[AsyncQueue.scala:73:14]
output [2:0] io_async_mem_5_size, // @[AsyncQueue.scala:73:14]
output [3:0] io_async_mem_5_source, // @[AsyncQueue.scala:73:14]
output [31:0] io_async_mem_5_address, // @[AsyncQueue.scala:73:14]
output [7:0] io_async_mem_5_mask, // @[AsyncQueue.scala:73:14]
output [63:0] io_async_mem_5_data, // @[AsyncQueue.scala:73:14]
output io_async_mem_5_corrupt, // @[AsyncQueue.scala:73:14]
output [2:0] io_async_mem_6_opcode, // @[AsyncQueue.scala:73:14]
output [2:0] io_async_mem_6_param, // @[AsyncQueue.scala:73:14]
output [2:0] io_async_mem_6_size, // @[AsyncQueue.scala:73:14]
output [3:0] io_async_mem_6_source, // @[AsyncQueue.scala:73:14]
output [31:0] io_async_mem_6_address, // @[AsyncQueue.scala:73:14]
output [7:0] io_async_mem_6_mask, // @[AsyncQueue.scala:73:14]
output [63:0] io_async_mem_6_data, // @[AsyncQueue.scala:73:14]
output io_async_mem_6_corrupt, // @[AsyncQueue.scala:73:14]
output [2:0] io_async_mem_7_opcode, // @[AsyncQueue.scala:73:14]
output [2:0] io_async_mem_7_param, // @[AsyncQueue.scala:73:14]
output [2:0] io_async_mem_7_size, // @[AsyncQueue.scala:73:14]
output [3:0] io_async_mem_7_source, // @[AsyncQueue.scala:73:14]
output [31:0] io_async_mem_7_address, // @[AsyncQueue.scala:73:14]
output [7:0] io_async_mem_7_mask, // @[AsyncQueue.scala:73:14]
output [63:0] io_async_mem_7_data, // @[AsyncQueue.scala:73:14]
output io_async_mem_7_corrupt, // @[AsyncQueue.scala:73:14]
input [3:0] io_async_ridx, // @[AsyncQueue.scala:73:14]
output [3:0] io_async_widx, // @[AsyncQueue.scala:73:14]
input io_async_safe_ridx_valid, // @[AsyncQueue.scala:73:14]
output io_async_safe_widx_valid, // @[AsyncQueue.scala:73:14]
output io_async_safe_source_reset_n, // @[AsyncQueue.scala:73:14]
input io_async_safe_sink_reset_n // @[AsyncQueue.scala:73:14]
);
wire _sink_extend_io_out; // @[AsyncQueue.scala:105:30]
wire _source_valid_0_io_out; // @[AsyncQueue.scala:102:32]
wire io_enq_valid_0 = io_enq_valid; // @[AsyncQueue.scala:70:7]
wire [2:0] io_enq_bits_opcode_0 = io_enq_bits_opcode; // @[AsyncQueue.scala:70:7]
wire [2:0] io_enq_bits_param_0 = io_enq_bits_param; // @[AsyncQueue.scala:70:7]
wire [2:0] io_enq_bits_size_0 = io_enq_bits_size; // @[AsyncQueue.scala:70:7]
wire [3:0] io_enq_bits_source_0 = io_enq_bits_source; // @[AsyncQueue.scala:70:7]
wire [31:0] io_enq_bits_address_0 = io_enq_bits_address; // @[AsyncQueue.scala:70:7]
wire [7:0] io_enq_bits_mask_0 = io_enq_bits_mask; // @[AsyncQueue.scala:70:7]
wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[AsyncQueue.scala:70:7]
wire io_enq_bits_corrupt_0 = io_enq_bits_corrupt; // @[AsyncQueue.scala:70:7]
wire [3:0] io_async_ridx_0 = io_async_ridx; // @[AsyncQueue.scala:70:7]
wire io_async_safe_ridx_valid_0 = io_async_safe_ridx_valid; // @[AsyncQueue.scala:70:7]
wire io_async_safe_sink_reset_n_0 = io_async_safe_sink_reset_n; // @[AsyncQueue.scala:70:7]
wire _widx_T = reset; // @[AsyncQueue.scala:83:30]
wire _ready_reg_T = reset; // @[AsyncQueue.scala:90:35]
wire _widx_reg_T = reset; // @[AsyncQueue.scala:93:34]
wire _source_valid_0_reset_T = reset; // @[AsyncQueue.scala:107:36]
wire _source_valid_1_reset_T = reset; // @[AsyncQueue.scala:108:36]
wire _sink_extend_reset_T = reset; // @[AsyncQueue.scala:109:36]
wire _sink_valid_reset_T = reset; // @[AsyncQueue.scala:110:35]
wire _io_async_safe_source_reset_n_T = reset; // @[AsyncQueue.scala:123:34]
wire _io_enq_ready_T; // @[AsyncQueue.scala:91:29]
wire _io_async_safe_source_reset_n_T_1; // @[AsyncQueue.scala:123:27]
wire io_enq_ready_0; // @[AsyncQueue.scala:70:7]
wire [2:0] io_async_mem_0_opcode_0; // @[AsyncQueue.scala:70:7]
wire [2:0] io_async_mem_0_param_0; // @[AsyncQueue.scala:70:7]
wire [2:0] io_async_mem_0_size_0; // @[AsyncQueue.scala:70:7]
wire [3:0] io_async_mem_0_source_0; // @[AsyncQueue.scala:70:7]
wire [31:0] io_async_mem_0_address_0; // @[AsyncQueue.scala:70:7]
wire [7:0] io_async_mem_0_mask_0; // @[AsyncQueue.scala:70:7]
wire [63:0] io_async_mem_0_data_0; // @[AsyncQueue.scala:70:7]
wire io_async_mem_0_corrupt_0; // @[AsyncQueue.scala:70:7]
wire [2:0] io_async_mem_1_opcode_0; // @[AsyncQueue.scala:70:7]
wire [2:0] io_async_mem_1_param_0; // @[AsyncQueue.scala:70:7]
wire [2:0] io_async_mem_1_size_0; // @[AsyncQueue.scala:70:7]
wire [3:0] io_async_mem_1_source_0; // @[AsyncQueue.scala:70:7]
wire [31:0] io_async_mem_1_address_0; // @[AsyncQueue.scala:70:7]
wire [7:0] io_async_mem_1_mask_0; // @[AsyncQueue.scala:70:7]
wire [63:0] io_async_mem_1_data_0; // @[AsyncQueue.scala:70:7]
wire io_async_mem_1_corrupt_0; // @[AsyncQueue.scala:70:7]
wire [2:0] io_async_mem_2_opcode_0; // @[AsyncQueue.scala:70:7]
wire [2:0] io_async_mem_2_param_0; // @[AsyncQueue.scala:70:7]
wire [2:0] io_async_mem_2_size_0; // @[AsyncQueue.scala:70:7]
wire [3:0] io_async_mem_2_source_0; // @[AsyncQueue.scala:70:7]
wire [31:0] io_async_mem_2_address_0; // @[AsyncQueue.scala:70:7]
wire [7:0] io_async_mem_2_mask_0; // @[AsyncQueue.scala:70:7]
wire [63:0] io_async_mem_2_data_0; // @[AsyncQueue.scala:70:7]
wire io_async_mem_2_corrupt_0; // @[AsyncQueue.scala:70:7]
wire [2:0] io_async_mem_3_opcode_0; // @[AsyncQueue.scala:70:7]
wire [2:0] io_async_mem_3_param_0; // @[AsyncQueue.scala:70:7]
wire [2:0] io_async_mem_3_size_0; // @[AsyncQueue.scala:70:7]
wire [3:0] io_async_mem_3_source_0; // @[AsyncQueue.scala:70:7]
wire [31:0] io_async_mem_3_address_0; // @[AsyncQueue.scala:70:7]
wire [7:0] io_async_mem_3_mask_0; // @[AsyncQueue.scala:70:7]
wire [63:0] io_async_mem_3_data_0; // @[AsyncQueue.scala:70:7]
wire io_async_mem_3_corrupt_0; // @[AsyncQueue.scala:70:7]
wire [2:0] io_async_mem_4_opcode_0; // @[AsyncQueue.scala:70:7]
wire [2:0] io_async_mem_4_param_0; // @[AsyncQueue.scala:70:7]
wire [2:0] io_async_mem_4_size_0; // @[AsyncQueue.scala:70:7]
wire [3:0] io_async_mem_4_source_0; // @[AsyncQueue.scala:70:7]
wire [31:0] io_async_mem_4_address_0; // @[AsyncQueue.scala:70:7]
wire [7:0] io_async_mem_4_mask_0; // @[AsyncQueue.scala:70:7]
wire [63:0] io_async_mem_4_data_0; // @[AsyncQueue.scala:70:7]
wire io_async_mem_4_corrupt_0; // @[AsyncQueue.scala:70:7]
wire [2:0] io_async_mem_5_opcode_0; // @[AsyncQueue.scala:70:7]
wire [2:0] io_async_mem_5_param_0; // @[AsyncQueue.scala:70:7]
wire [2:0] io_async_mem_5_size_0; // @[AsyncQueue.scala:70:7]
wire [3:0] io_async_mem_5_source_0; // @[AsyncQueue.scala:70:7]
wire [31:0] io_async_mem_5_address_0; // @[AsyncQueue.scala:70:7]
wire [7:0] io_async_mem_5_mask_0; // @[AsyncQueue.scala:70:7]
wire [63:0] io_async_mem_5_data_0; // @[AsyncQueue.scala:70:7]
wire io_async_mem_5_corrupt_0; // @[AsyncQueue.scala:70:7]
wire [2:0] io_async_mem_6_opcode_0; // @[AsyncQueue.scala:70:7]
wire [2:0] io_async_mem_6_param_0; // @[AsyncQueue.scala:70:7]
wire [2:0] io_async_mem_6_size_0; // @[AsyncQueue.scala:70:7]
wire [3:0] io_async_mem_6_source_0; // @[AsyncQueue.scala:70:7]
wire [31:0] io_async_mem_6_address_0; // @[AsyncQueue.scala:70:7]
wire [7:0] io_async_mem_6_mask_0; // @[AsyncQueue.scala:70:7]
wire [63:0] io_async_mem_6_data_0; // @[AsyncQueue.scala:70:7]
wire io_async_mem_6_corrupt_0; // @[AsyncQueue.scala:70:7]
wire [2:0] io_async_mem_7_opcode_0; // @[AsyncQueue.scala:70:7]
wire [2:0] io_async_mem_7_param_0; // @[AsyncQueue.scala:70:7]
wire [2:0] io_async_mem_7_size_0; // @[AsyncQueue.scala:70:7]
wire [3:0] io_async_mem_7_source_0; // @[AsyncQueue.scala:70:7]
wire [31:0] io_async_mem_7_address_0; // @[AsyncQueue.scala:70:7]
wire [7:0] io_async_mem_7_mask_0; // @[AsyncQueue.scala:70:7]
wire [63:0] io_async_mem_7_data_0; // @[AsyncQueue.scala:70:7]
wire io_async_mem_7_corrupt_0; // @[AsyncQueue.scala:70:7]
wire io_async_safe_widx_valid_0; // @[AsyncQueue.scala:70:7]
wire io_async_safe_source_reset_n_0; // @[AsyncQueue.scala:70:7]
wire [3:0] io_async_widx_0; // @[AsyncQueue.scala:70:7]
wire sink_ready; // @[AsyncQueue.scala:81:28]
reg [2:0] mem_0_opcode; // @[AsyncQueue.scala:82:16]
assign io_async_mem_0_opcode_0 = mem_0_opcode; // @[AsyncQueue.scala:70:7, :82:16]
reg [2:0] mem_0_param; // @[AsyncQueue.scala:82:16]
assign io_async_mem_0_param_0 = mem_0_param; // @[AsyncQueue.scala:70:7, :82:16]
reg [2:0] mem_0_size; // @[AsyncQueue.scala:82:16]
assign io_async_mem_0_size_0 = mem_0_size; // @[AsyncQueue.scala:70:7, :82:16]
reg [3:0] mem_0_source; // @[AsyncQueue.scala:82:16]
assign io_async_mem_0_source_0 = mem_0_source; // @[AsyncQueue.scala:70:7, :82:16]
reg [31:0] mem_0_address; // @[AsyncQueue.scala:82:16]
assign io_async_mem_0_address_0 = mem_0_address; // @[AsyncQueue.scala:70:7, :82:16]
reg [7:0] mem_0_mask; // @[AsyncQueue.scala:82:16]
assign io_async_mem_0_mask_0 = mem_0_mask; // @[AsyncQueue.scala:70:7, :82:16]
reg [63:0] mem_0_data; // @[AsyncQueue.scala:82:16]
assign io_async_mem_0_data_0 = mem_0_data; // @[AsyncQueue.scala:70:7, :82:16]
reg mem_0_corrupt; // @[AsyncQueue.scala:82:16]
assign io_async_mem_0_corrupt_0 = mem_0_corrupt; // @[AsyncQueue.scala:70:7, :82:16]
reg [2:0] mem_1_opcode; // @[AsyncQueue.scala:82:16]
assign io_async_mem_1_opcode_0 = mem_1_opcode; // @[AsyncQueue.scala:70:7, :82:16]
reg [2:0] mem_1_param; // @[AsyncQueue.scala:82:16]
assign io_async_mem_1_param_0 = mem_1_param; // @[AsyncQueue.scala:70:7, :82:16]
reg [2:0] mem_1_size; // @[AsyncQueue.scala:82:16]
assign io_async_mem_1_size_0 = mem_1_size; // @[AsyncQueue.scala:70:7, :82:16]
reg [3:0] mem_1_source; // @[AsyncQueue.scala:82:16]
assign io_async_mem_1_source_0 = mem_1_source; // @[AsyncQueue.scala:70:7, :82:16]
reg [31:0] mem_1_address; // @[AsyncQueue.scala:82:16]
assign io_async_mem_1_address_0 = mem_1_address; // @[AsyncQueue.scala:70:7, :82:16]
reg [7:0] mem_1_mask; // @[AsyncQueue.scala:82:16]
assign io_async_mem_1_mask_0 = mem_1_mask; // @[AsyncQueue.scala:70:7, :82:16]
reg [63:0] mem_1_data; // @[AsyncQueue.scala:82:16]
assign io_async_mem_1_data_0 = mem_1_data; // @[AsyncQueue.scala:70:7, :82:16]
reg mem_1_corrupt; // @[AsyncQueue.scala:82:16]
assign io_async_mem_1_corrupt_0 = mem_1_corrupt; // @[AsyncQueue.scala:70:7, :82:16]
reg [2:0] mem_2_opcode; // @[AsyncQueue.scala:82:16]
assign io_async_mem_2_opcode_0 = mem_2_opcode; // @[AsyncQueue.scala:70:7, :82:16]
reg [2:0] mem_2_param; // @[AsyncQueue.scala:82:16]
assign io_async_mem_2_param_0 = mem_2_param; // @[AsyncQueue.scala:70:7, :82:16]
reg [2:0] mem_2_size; // @[AsyncQueue.scala:82:16]
assign io_async_mem_2_size_0 = mem_2_size; // @[AsyncQueue.scala:70:7, :82:16]
reg [3:0] mem_2_source; // @[AsyncQueue.scala:82:16]
assign io_async_mem_2_source_0 = mem_2_source; // @[AsyncQueue.scala:70:7, :82:16]
reg [31:0] mem_2_address; // @[AsyncQueue.scala:82:16]
assign io_async_mem_2_address_0 = mem_2_address; // @[AsyncQueue.scala:70:7, :82:16]
reg [7:0] mem_2_mask; // @[AsyncQueue.scala:82:16]
assign io_async_mem_2_mask_0 = mem_2_mask; // @[AsyncQueue.scala:70:7, :82:16]
reg [63:0] mem_2_data; // @[AsyncQueue.scala:82:16]
assign io_async_mem_2_data_0 = mem_2_data; // @[AsyncQueue.scala:70:7, :82:16]
reg mem_2_corrupt; // @[AsyncQueue.scala:82:16]
assign io_async_mem_2_corrupt_0 = mem_2_corrupt; // @[AsyncQueue.scala:70:7, :82:16]
reg [2:0] mem_3_opcode; // @[AsyncQueue.scala:82:16]
assign io_async_mem_3_opcode_0 = mem_3_opcode; // @[AsyncQueue.scala:70:7, :82:16]
reg [2:0] mem_3_param; // @[AsyncQueue.scala:82:16]
assign io_async_mem_3_param_0 = mem_3_param; // @[AsyncQueue.scala:70:7, :82:16]
reg [2:0] mem_3_size; // @[AsyncQueue.scala:82:16]
assign io_async_mem_3_size_0 = mem_3_size; // @[AsyncQueue.scala:70:7, :82:16]
reg [3:0] mem_3_source; // @[AsyncQueue.scala:82:16]
assign io_async_mem_3_source_0 = mem_3_source; // @[AsyncQueue.scala:70:7, :82:16]
reg [31:0] mem_3_address; // @[AsyncQueue.scala:82:16]
assign io_async_mem_3_address_0 = mem_3_address; // @[AsyncQueue.scala:70:7, :82:16]
reg [7:0] mem_3_mask; // @[AsyncQueue.scala:82:16]
assign io_async_mem_3_mask_0 = mem_3_mask; // @[AsyncQueue.scala:70:7, :82:16]
reg [63:0] mem_3_data; // @[AsyncQueue.scala:82:16]
assign io_async_mem_3_data_0 = mem_3_data; // @[AsyncQueue.scala:70:7, :82:16]
reg mem_3_corrupt; // @[AsyncQueue.scala:82:16]
assign io_async_mem_3_corrupt_0 = mem_3_corrupt; // @[AsyncQueue.scala:70:7, :82:16]
reg [2:0] mem_4_opcode; // @[AsyncQueue.scala:82:16]
assign io_async_mem_4_opcode_0 = mem_4_opcode; // @[AsyncQueue.scala:70:7, :82:16]
reg [2:0] mem_4_param; // @[AsyncQueue.scala:82:16]
assign io_async_mem_4_param_0 = mem_4_param; // @[AsyncQueue.scala:70:7, :82:16]
reg [2:0] mem_4_size; // @[AsyncQueue.scala:82:16]
assign io_async_mem_4_size_0 = mem_4_size; // @[AsyncQueue.scala:70:7, :82:16]
reg [3:0] mem_4_source; // @[AsyncQueue.scala:82:16]
assign io_async_mem_4_source_0 = mem_4_source; // @[AsyncQueue.scala:70:7, :82:16]
reg [31:0] mem_4_address; // @[AsyncQueue.scala:82:16]
assign io_async_mem_4_address_0 = mem_4_address; // @[AsyncQueue.scala:70:7, :82:16]
reg [7:0] mem_4_mask; // @[AsyncQueue.scala:82:16]
assign io_async_mem_4_mask_0 = mem_4_mask; // @[AsyncQueue.scala:70:7, :82:16]
reg [63:0] mem_4_data; // @[AsyncQueue.scala:82:16]
assign io_async_mem_4_data_0 = mem_4_data; // @[AsyncQueue.scala:70:7, :82:16]
reg mem_4_corrupt; // @[AsyncQueue.scala:82:16]
assign io_async_mem_4_corrupt_0 = mem_4_corrupt; // @[AsyncQueue.scala:70:7, :82:16]
reg [2:0] mem_5_opcode; // @[AsyncQueue.scala:82:16]
assign io_async_mem_5_opcode_0 = mem_5_opcode; // @[AsyncQueue.scala:70:7, :82:16]
reg [2:0] mem_5_param; // @[AsyncQueue.scala:82:16]
assign io_async_mem_5_param_0 = mem_5_param; // @[AsyncQueue.scala:70:7, :82:16]
reg [2:0] mem_5_size; // @[AsyncQueue.scala:82:16]
assign io_async_mem_5_size_0 = mem_5_size; // @[AsyncQueue.scala:70:7, :82:16]
reg [3:0] mem_5_source; // @[AsyncQueue.scala:82:16]
assign io_async_mem_5_source_0 = mem_5_source; // @[AsyncQueue.scala:70:7, :82:16]
reg [31:0] mem_5_address; // @[AsyncQueue.scala:82:16]
assign io_async_mem_5_address_0 = mem_5_address; // @[AsyncQueue.scala:70:7, :82:16]
reg [7:0] mem_5_mask; // @[AsyncQueue.scala:82:16]
assign io_async_mem_5_mask_0 = mem_5_mask; // @[AsyncQueue.scala:70:7, :82:16]
reg [63:0] mem_5_data; // @[AsyncQueue.scala:82:16]
assign io_async_mem_5_data_0 = mem_5_data; // @[AsyncQueue.scala:70:7, :82:16]
reg mem_5_corrupt; // @[AsyncQueue.scala:82:16]
assign io_async_mem_5_corrupt_0 = mem_5_corrupt; // @[AsyncQueue.scala:70:7, :82:16]
reg [2:0] mem_6_opcode; // @[AsyncQueue.scala:82:16]
assign io_async_mem_6_opcode_0 = mem_6_opcode; // @[AsyncQueue.scala:70:7, :82:16]
reg [2:0] mem_6_param; // @[AsyncQueue.scala:82:16]
assign io_async_mem_6_param_0 = mem_6_param; // @[AsyncQueue.scala:70:7, :82:16]
reg [2:0] mem_6_size; // @[AsyncQueue.scala:82:16]
assign io_async_mem_6_size_0 = mem_6_size; // @[AsyncQueue.scala:70:7, :82:16]
reg [3:0] mem_6_source; // @[AsyncQueue.scala:82:16]
assign io_async_mem_6_source_0 = mem_6_source; // @[AsyncQueue.scala:70:7, :82:16]
reg [31:0] mem_6_address; // @[AsyncQueue.scala:82:16]
assign io_async_mem_6_address_0 = mem_6_address; // @[AsyncQueue.scala:70:7, :82:16]
reg [7:0] mem_6_mask; // @[AsyncQueue.scala:82:16]
assign io_async_mem_6_mask_0 = mem_6_mask; // @[AsyncQueue.scala:70:7, :82:16]
reg [63:0] mem_6_data; // @[AsyncQueue.scala:82:16]
assign io_async_mem_6_data_0 = mem_6_data; // @[AsyncQueue.scala:70:7, :82:16]
reg mem_6_corrupt; // @[AsyncQueue.scala:82:16]
assign io_async_mem_6_corrupt_0 = mem_6_corrupt; // @[AsyncQueue.scala:70:7, :82:16]
reg [2:0] mem_7_opcode; // @[AsyncQueue.scala:82:16]
assign io_async_mem_7_opcode_0 = mem_7_opcode; // @[AsyncQueue.scala:70:7, :82:16]
reg [2:0] mem_7_param; // @[AsyncQueue.scala:82:16]
assign io_async_mem_7_param_0 = mem_7_param; // @[AsyncQueue.scala:70:7, :82:16]
reg [2:0] mem_7_size; // @[AsyncQueue.scala:82:16]
assign io_async_mem_7_size_0 = mem_7_size; // @[AsyncQueue.scala:70:7, :82:16]
reg [3:0] mem_7_source; // @[AsyncQueue.scala:82:16]
assign io_async_mem_7_source_0 = mem_7_source; // @[AsyncQueue.scala:70:7, :82:16]
reg [31:0] mem_7_address; // @[AsyncQueue.scala:82:16]
assign io_async_mem_7_address_0 = mem_7_address; // @[AsyncQueue.scala:70:7, :82:16]
reg [7:0] mem_7_mask; // @[AsyncQueue.scala:82:16]
assign io_async_mem_7_mask_0 = mem_7_mask; // @[AsyncQueue.scala:70:7, :82:16]
reg [63:0] mem_7_data; // @[AsyncQueue.scala:82:16]
assign io_async_mem_7_data_0 = mem_7_data; // @[AsyncQueue.scala:70:7, :82:16]
reg mem_7_corrupt; // @[AsyncQueue.scala:82:16]
assign io_async_mem_7_corrupt_0 = mem_7_corrupt; // @[AsyncQueue.scala:70:7, :82:16]
wire _widx_T_1 = io_enq_ready_0 & io_enq_valid_0; // @[Decoupled.scala:51:35]
wire _widx_T_2 = ~sink_ready; // @[AsyncQueue.scala:81:28, :83:77]
wire [3:0] _widx_incremented_T_2; // @[AsyncQueue.scala:53:23]
wire [3:0] widx_incremented; // @[AsyncQueue.scala:51:27]
reg [3:0] widx_widx_bin; // @[AsyncQueue.scala:52:25]
wire [4:0] _widx_incremented_T = {1'h0, widx_widx_bin} + {4'h0, _widx_T_1}; // @[Decoupled.scala:51:35]
wire [3:0] _widx_incremented_T_1 = _widx_incremented_T[3:0]; // @[AsyncQueue.scala:53:43]
assign _widx_incremented_T_2 = _widx_T_2 ? 4'h0 : _widx_incremented_T_1; // @[AsyncQueue.scala:52:25, :53:{23,43}, :83:77]
assign widx_incremented = _widx_incremented_T_2; // @[AsyncQueue.scala:51:27, :53:23]
wire [2:0] _widx_T_3 = widx_incremented[3:1]; // @[AsyncQueue.scala:51:27, :54:32]
wire [3:0] widx = {widx_incremented[3], widx_incremented[2:0] ^ _widx_T_3}; // @[AsyncQueue.scala:51:27, :54:{17,32}]
wire [3:0] ridx; // @[ShiftReg.scala:48:24]
wire [3:0] _ready_T = ridx ^ 4'hC; // @[ShiftReg.scala:48:24]
wire _ready_T_1 = widx != _ready_T; // @[AsyncQueue.scala:54:17, :85:{34,44}]
wire ready = sink_ready & _ready_T_1; // @[AsyncQueue.scala:81:28, :85:{26,34}]
wire [2:0] _index_T = io_async_widx_0[2:0]; // @[AsyncQueue.scala:70:7, :87:52]
wire _index_T_1 = io_async_widx_0[3]; // @[AsyncQueue.scala:70:7, :87:80]
wire [2:0] _index_T_2 = {_index_T_1, 2'h0}; // @[AsyncQueue.scala:87:{80,93}]
wire [2:0] index = _index_T ^ _index_T_2; // @[AsyncQueue.scala:87:{52,64,93}]
reg ready_reg; // @[AsyncQueue.scala:90:56]
assign _io_enq_ready_T = ready_reg & sink_ready; // @[AsyncQueue.scala:81:28, :90:56, :91:29]
assign io_enq_ready_0 = _io_enq_ready_T; // @[AsyncQueue.scala:70:7, :91:29]
reg [3:0] widx_gray; // @[AsyncQueue.scala:93:55]
assign io_async_widx_0 = widx_gray; // @[AsyncQueue.scala:70:7, :93:55]
wire _source_valid_0_reset_T_1 = ~io_async_safe_sink_reset_n_0; // @[AsyncQueue.scala:70:7, :107:46]
wire _source_valid_0_reset_T_2 = _source_valid_0_reset_T | _source_valid_0_reset_T_1; // @[AsyncQueue.scala:107:{36,43,46}]
wire _source_valid_0_reset_T_3 = _source_valid_0_reset_T_2; // @[AsyncQueue.scala:107:{43,65}]
wire _source_valid_1_reset_T_1 = ~io_async_safe_sink_reset_n_0; // @[AsyncQueue.scala:70:7, :107:46, :108:46]
wire _source_valid_1_reset_T_2 = _source_valid_1_reset_T | _source_valid_1_reset_T_1; // @[AsyncQueue.scala:108:{36,43,46}]
wire _source_valid_1_reset_T_3 = _source_valid_1_reset_T_2; // @[AsyncQueue.scala:108:{43,65}]
wire _sink_extend_reset_T_1 = ~io_async_safe_sink_reset_n_0; // @[AsyncQueue.scala:70:7, :107:46, :109:46]
wire _sink_extend_reset_T_2 = _sink_extend_reset_T | _sink_extend_reset_T_1; // @[AsyncQueue.scala:109:{36,43,46}]
wire _sink_extend_reset_T_3 = _sink_extend_reset_T_2; // @[AsyncQueue.scala:109:{43,65}]
assign _io_async_safe_source_reset_n_T_1 = ~_io_async_safe_source_reset_n_T; // @[AsyncQueue.scala:123:{27,34}]
assign io_async_safe_source_reset_n_0 = _io_async_safe_source_reset_n_T_1; // @[AsyncQueue.scala:70:7, :123:27]
always @(posedge clock) begin // @[AsyncQueue.scala:70:7]
if (_widx_T_1 & index == 3'h0) begin // @[Decoupled.scala:51:35]
mem_0_opcode <= io_enq_bits_opcode_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_0_param <= io_enq_bits_param_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_0_size <= io_enq_bits_size_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_0_source <= io_enq_bits_source_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_0_address <= io_enq_bits_address_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_0_mask <= io_enq_bits_mask_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_0_data <= io_enq_bits_data_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_0_corrupt <= io_enq_bits_corrupt_0; // @[AsyncQueue.scala:70:7, :82:16]
end
if (_widx_T_1 & index == 3'h1) begin // @[Decoupled.scala:51:35]
mem_1_opcode <= io_enq_bits_opcode_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_1_param <= io_enq_bits_param_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_1_size <= io_enq_bits_size_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_1_source <= io_enq_bits_source_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_1_address <= io_enq_bits_address_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_1_mask <= io_enq_bits_mask_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_1_data <= io_enq_bits_data_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_1_corrupt <= io_enq_bits_corrupt_0; // @[AsyncQueue.scala:70:7, :82:16]
end
if (_widx_T_1 & index == 3'h2) begin // @[Decoupled.scala:51:35]
mem_2_opcode <= io_enq_bits_opcode_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_2_param <= io_enq_bits_param_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_2_size <= io_enq_bits_size_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_2_source <= io_enq_bits_source_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_2_address <= io_enq_bits_address_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_2_mask <= io_enq_bits_mask_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_2_data <= io_enq_bits_data_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_2_corrupt <= io_enq_bits_corrupt_0; // @[AsyncQueue.scala:70:7, :82:16]
end
if (_widx_T_1 & index == 3'h3) begin // @[Decoupled.scala:51:35]
mem_3_opcode <= io_enq_bits_opcode_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_3_param <= io_enq_bits_param_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_3_size <= io_enq_bits_size_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_3_source <= io_enq_bits_source_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_3_address <= io_enq_bits_address_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_3_mask <= io_enq_bits_mask_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_3_data <= io_enq_bits_data_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_3_corrupt <= io_enq_bits_corrupt_0; // @[AsyncQueue.scala:70:7, :82:16]
end
if (_widx_T_1 & index == 3'h4) begin // @[Decoupled.scala:51:35]
mem_4_opcode <= io_enq_bits_opcode_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_4_param <= io_enq_bits_param_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_4_size <= io_enq_bits_size_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_4_source <= io_enq_bits_source_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_4_address <= io_enq_bits_address_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_4_mask <= io_enq_bits_mask_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_4_data <= io_enq_bits_data_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_4_corrupt <= io_enq_bits_corrupt_0; // @[AsyncQueue.scala:70:7, :82:16]
end
if (_widx_T_1 & index == 3'h5) begin // @[Decoupled.scala:51:35]
mem_5_opcode <= io_enq_bits_opcode_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_5_param <= io_enq_bits_param_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_5_size <= io_enq_bits_size_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_5_source <= io_enq_bits_source_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_5_address <= io_enq_bits_address_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_5_mask <= io_enq_bits_mask_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_5_data <= io_enq_bits_data_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_5_corrupt <= io_enq_bits_corrupt_0; // @[AsyncQueue.scala:70:7, :82:16]
end
if (_widx_T_1 & index == 3'h6) begin // @[Decoupled.scala:51:35]
mem_6_opcode <= io_enq_bits_opcode_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_6_param <= io_enq_bits_param_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_6_size <= io_enq_bits_size_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_6_source <= io_enq_bits_source_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_6_address <= io_enq_bits_address_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_6_mask <= io_enq_bits_mask_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_6_data <= io_enq_bits_data_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_6_corrupt <= io_enq_bits_corrupt_0; // @[AsyncQueue.scala:70:7, :82:16]
end
if (_widx_T_1 & (&index)) begin // @[Decoupled.scala:51:35]
mem_7_opcode <= io_enq_bits_opcode_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_7_param <= io_enq_bits_param_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_7_size <= io_enq_bits_size_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_7_source <= io_enq_bits_source_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_7_address <= io_enq_bits_address_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_7_mask <= io_enq_bits_mask_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_7_data <= io_enq_bits_data_0; // @[AsyncQueue.scala:70:7, :82:16]
mem_7_corrupt <= io_enq_bits_corrupt_0; // @[AsyncQueue.scala:70:7, :82:16]
end
always @(posedge)
always @(posedge clock or posedge _widx_T) begin // @[AsyncQueue.scala:70:7, :83:30]
if (_widx_T) // @[AsyncQueue.scala:70:7, :83:30]
widx_widx_bin <= 4'h0; // @[AsyncQueue.scala:52:25]
else // @[AsyncQueue.scala:70:7]
widx_widx_bin <= widx_incremented; // @[AsyncQueue.scala:51:27, :52:25]
always @(posedge, posedge)
always @(posedge clock or posedge _ready_reg_T) begin // @[AsyncQueue.scala:70:7, :90:35]
if (_ready_reg_T) // @[AsyncQueue.scala:70:7, :90:35]
ready_reg <= 1'h0; // @[AsyncQueue.scala:90:56]
else // @[AsyncQueue.scala:70:7]
ready_reg <= ready; // @[AsyncQueue.scala:85:26, :90:56]
always @(posedge, posedge)
always @(posedge clock or posedge _widx_reg_T) begin // @[AsyncQueue.scala:70:7, :93:34]
if (_widx_reg_T) // @[AsyncQueue.scala:70:7, :93:34]
widx_gray <= 4'h0; // @[AsyncQueue.scala:52:25, :93:55]
else // @[AsyncQueue.scala:70:7]
widx_gray <= widx; // @[AsyncQueue.scala:54:17, :93:55]
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_127 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_219
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_127( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
output io_q // @[ShiftReg.scala:36:14]
);
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_219 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_22 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<6>(0h20))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 2, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 3)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<2>(0h2))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<3>(0h7))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 2, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 3)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<2>(0h3))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<3>(0h7))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<1>(0h0))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<1>(0h1))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0)
node _source_ok_T_25 = shr(io.in.a.bits.source, 2)
node _source_ok_T_26 = eq(_source_ok_T_25, UInt<2>(0h2))
node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27)
node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<2>(0h3))
node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29)
node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0)
node _source_ok_T_31 = shr(io.in.a.bits.source, 2)
node _source_ok_T_32 = eq(_source_ok_T_31, UInt<2>(0h3))
node _source_ok_T_33 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_34 = and(_source_ok_T_32, _source_ok_T_33)
node _source_ok_T_35 = leq(source_ok_uncommonBits_5, UInt<2>(0h3))
node _source_ok_T_36 = and(_source_ok_T_34, _source_ok_T_35)
node _source_ok_T_37 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _source_ok_T_38 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE : UInt<1>[9]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_30
connect _source_ok_WIRE[6], _source_ok_T_36
connect _source_ok_WIRE[7], _source_ok_T_37
connect _source_ok_WIRE[8], _source_ok_T_38
node _source_ok_T_39 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_40 = or(_source_ok_T_39, _source_ok_WIRE[2])
node _source_ok_T_41 = or(_source_ok_T_40, _source_ok_WIRE[3])
node _source_ok_T_42 = or(_source_ok_T_41, _source_ok_WIRE[4])
node _source_ok_T_43 = or(_source_ok_T_42, _source_ok_WIRE[5])
node _source_ok_T_44 = or(_source_ok_T_43, _source_ok_WIRE[6])
node _source_ok_T_45 = or(_source_ok_T_44, _source_ok_WIRE[7])
node source_ok = or(_source_ok_T_45, _source_ok_WIRE[8])
node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits = bits(_uncommonBits_T, 2, 0)
node _T_12 = shr(io.in.a.bits.source, 3)
node _T_13 = eq(_T_12, UInt<2>(0h2))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<3>(0h7))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 2, 0)
node _T_25 = shr(io.in.a.bits.source, 3)
node _T_26 = eq(_T_25, UInt<2>(0h3))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<3>(0h7))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<1>(0h0))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<1>(0h1))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0)
node _T_64 = shr(io.in.a.bits.source, 2)
node _T_65 = eq(_T_64, UInt<2>(0h2))
node _T_66 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_67 = and(_T_65, _T_66)
node _T_68 = leq(uncommonBits_4, UInt<2>(0h3))
node _T_69 = and(_T_67, _T_68)
node _T_70 = eq(_T_69, UInt<1>(0h0))
node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_72 = cvt(_T_71)
node _T_73 = and(_T_72, asSInt(UInt<1>(0h0)))
node _T_74 = asSInt(_T_73)
node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0)))
node _T_76 = or(_T_70, _T_75)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0)
node _T_77 = shr(io.in.a.bits.source, 2)
node _T_78 = eq(_T_77, UInt<2>(0h3))
node _T_79 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_80 = and(_T_78, _T_79)
node _T_81 = leq(uncommonBits_5, UInt<2>(0h3))
node _T_82 = and(_T_80, _T_81)
node _T_83 = eq(_T_82, UInt<1>(0h0))
node _T_84 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_85 = cvt(_T_84)
node _T_86 = and(_T_85, asSInt(UInt<1>(0h0)))
node _T_87 = asSInt(_T_86)
node _T_88 = eq(_T_87, asSInt(UInt<1>(0h0)))
node _T_89 = or(_T_83, _T_88)
node _T_90 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_91 = eq(_T_90, UInt<1>(0h0))
node _T_92 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_93 = cvt(_T_92)
node _T_94 = and(_T_93, asSInt(UInt<1>(0h0)))
node _T_95 = asSInt(_T_94)
node _T_96 = eq(_T_95, asSInt(UInt<1>(0h0)))
node _T_97 = or(_T_91, _T_96)
node _T_98 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_99 = eq(_T_98, UInt<1>(0h0))
node _T_100 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_101 = cvt(_T_100)
node _T_102 = and(_T_101, asSInt(UInt<1>(0h0)))
node _T_103 = asSInt(_T_102)
node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0)))
node _T_105 = or(_T_99, _T_104)
node _T_106 = and(_T_11, _T_24)
node _T_107 = and(_T_106, _T_37)
node _T_108 = and(_T_107, _T_50)
node _T_109 = and(_T_108, _T_63)
node _T_110 = and(_T_109, _T_76)
node _T_111 = and(_T_110, _T_89)
node _T_112 = and(_T_111, _T_97)
node _T_113 = and(_T_112, _T_105)
node _T_114 = asUInt(reset)
node _T_115 = eq(_T_114, UInt<1>(0h0))
when _T_115 :
node _T_116 = eq(_T_113, UInt<1>(0h0))
when _T_116 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_113, UInt<1>(0h1), "") : assert_1
node _T_117 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_117 :
node _T_118 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_119 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_120 = and(_T_118, _T_119)
node _T_121 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 2, 0)
node _T_122 = shr(io.in.a.bits.source, 3)
node _T_123 = eq(_T_122, UInt<2>(0h2))
node _T_124 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_125 = and(_T_123, _T_124)
node _T_126 = leq(uncommonBits_6, UInt<3>(0h7))
node _T_127 = and(_T_125, _T_126)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 2, 0)
node _T_128 = shr(io.in.a.bits.source, 3)
node _T_129 = eq(_T_128, UInt<2>(0h3))
node _T_130 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_131 = and(_T_129, _T_130)
node _T_132 = leq(uncommonBits_7, UInt<3>(0h7))
node _T_133 = and(_T_131, _T_132)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_134 = shr(io.in.a.bits.source, 2)
node _T_135 = eq(_T_134, UInt<1>(0h0))
node _T_136 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_137 = and(_T_135, _T_136)
node _T_138 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_139 = and(_T_137, _T_138)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_140 = shr(io.in.a.bits.source, 2)
node _T_141 = eq(_T_140, UInt<1>(0h1))
node _T_142 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_143 = and(_T_141, _T_142)
node _T_144 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_145 = and(_T_143, _T_144)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0)
node _T_146 = shr(io.in.a.bits.source, 2)
node _T_147 = eq(_T_146, UInt<2>(0h2))
node _T_148 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_149 = and(_T_147, _T_148)
node _T_150 = leq(uncommonBits_10, UInt<2>(0h3))
node _T_151 = and(_T_149, _T_150)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0)
node _T_152 = shr(io.in.a.bits.source, 2)
node _T_153 = eq(_T_152, UInt<2>(0h3))
node _T_154 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_155 = and(_T_153, _T_154)
node _T_156 = leq(uncommonBits_11, UInt<2>(0h3))
node _T_157 = and(_T_155, _T_156)
node _T_158 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_159 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_160 = or(_T_121, _T_127)
node _T_161 = or(_T_160, _T_133)
node _T_162 = or(_T_161, _T_139)
node _T_163 = or(_T_162, _T_145)
node _T_164 = or(_T_163, _T_151)
node _T_165 = or(_T_164, _T_157)
node _T_166 = or(_T_165, _T_158)
node _T_167 = or(_T_166, _T_159)
node _T_168 = and(_T_120, _T_167)
node _T_169 = or(UInt<1>(0h0), _T_168)
node _T_170 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_171 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_172 = cvt(_T_171)
node _T_173 = and(_T_172, asSInt(UInt<14>(0h2000)))
node _T_174 = asSInt(_T_173)
node _T_175 = eq(_T_174, asSInt(UInt<1>(0h0)))
node _T_176 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_177 = cvt(_T_176)
node _T_178 = and(_T_177, asSInt(UInt<13>(0h1000)))
node _T_179 = asSInt(_T_178)
node _T_180 = eq(_T_179, asSInt(UInt<1>(0h0)))
node _T_181 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_182 = cvt(_T_181)
node _T_183 = and(_T_182, asSInt(UInt<17>(0h10000)))
node _T_184 = asSInt(_T_183)
node _T_185 = eq(_T_184, asSInt(UInt<1>(0h0)))
node _T_186 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_187 = cvt(_T_186)
node _T_188 = and(_T_187, asSInt(UInt<18>(0h2f000)))
node _T_189 = asSInt(_T_188)
node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0)))
node _T_191 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_192 = cvt(_T_191)
node _T_193 = and(_T_192, asSInt(UInt<17>(0h10000)))
node _T_194 = asSInt(_T_193)
node _T_195 = eq(_T_194, asSInt(UInt<1>(0h0)))
node _T_196 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_197 = cvt(_T_196)
node _T_198 = and(_T_197, asSInt(UInt<27>(0h4000000)))
node _T_199 = asSInt(_T_198)
node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0)))
node _T_201 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_202 = cvt(_T_201)
node _T_203 = and(_T_202, asSInt(UInt<13>(0h1000)))
node _T_204 = asSInt(_T_203)
node _T_205 = eq(_T_204, asSInt(UInt<1>(0h0)))
node _T_206 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_207 = cvt(_T_206)
node _T_208 = and(_T_207, asSInt(UInt<15>(0h4000)))
node _T_209 = asSInt(_T_208)
node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0)))
node _T_211 = or(_T_175, _T_180)
node _T_212 = or(_T_211, _T_185)
node _T_213 = or(_T_212, _T_190)
node _T_214 = or(_T_213, _T_195)
node _T_215 = or(_T_214, _T_200)
node _T_216 = or(_T_215, _T_205)
node _T_217 = or(_T_216, _T_210)
node _T_218 = and(_T_170, _T_217)
node _T_219 = or(UInt<1>(0h0), _T_218)
node _T_220 = and(_T_169, _T_219)
node _T_221 = asUInt(reset)
node _T_222 = eq(_T_221, UInt<1>(0h0))
when _T_222 :
node _T_223 = eq(_T_220, UInt<1>(0h0))
when _T_223 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_220, UInt<1>(0h1), "") : assert_2
node _T_224 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_225 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_226 = and(_T_224, _T_225)
node _T_227 = or(UInt<1>(0h0), _T_226)
node _T_228 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_229 = cvt(_T_228)
node _T_230 = and(_T_229, asSInt(UInt<14>(0h2000)))
node _T_231 = asSInt(_T_230)
node _T_232 = eq(_T_231, asSInt(UInt<1>(0h0)))
node _T_233 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_234 = cvt(_T_233)
node _T_235 = and(_T_234, asSInt(UInt<13>(0h1000)))
node _T_236 = asSInt(_T_235)
node _T_237 = eq(_T_236, asSInt(UInt<1>(0h0)))
node _T_238 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_239 = cvt(_T_238)
node _T_240 = and(_T_239, asSInt(UInt<17>(0h10000)))
node _T_241 = asSInt(_T_240)
node _T_242 = eq(_T_241, asSInt(UInt<1>(0h0)))
node _T_243 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_244 = cvt(_T_243)
node _T_245 = and(_T_244, asSInt(UInt<18>(0h2f000)))
node _T_246 = asSInt(_T_245)
node _T_247 = eq(_T_246, asSInt(UInt<1>(0h0)))
node _T_248 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_249 = cvt(_T_248)
node _T_250 = and(_T_249, asSInt(UInt<17>(0h10000)))
node _T_251 = asSInt(_T_250)
node _T_252 = eq(_T_251, asSInt(UInt<1>(0h0)))
node _T_253 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_254 = cvt(_T_253)
node _T_255 = and(_T_254, asSInt(UInt<27>(0h4000000)))
node _T_256 = asSInt(_T_255)
node _T_257 = eq(_T_256, asSInt(UInt<1>(0h0)))
node _T_258 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_259 = cvt(_T_258)
node _T_260 = and(_T_259, asSInt(UInt<13>(0h1000)))
node _T_261 = asSInt(_T_260)
node _T_262 = eq(_T_261, asSInt(UInt<1>(0h0)))
node _T_263 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_264 = cvt(_T_263)
node _T_265 = and(_T_264, asSInt(UInt<15>(0h4000)))
node _T_266 = asSInt(_T_265)
node _T_267 = eq(_T_266, asSInt(UInt<1>(0h0)))
node _T_268 = or(_T_232, _T_237)
node _T_269 = or(_T_268, _T_242)
node _T_270 = or(_T_269, _T_247)
node _T_271 = or(_T_270, _T_252)
node _T_272 = or(_T_271, _T_257)
node _T_273 = or(_T_272, _T_262)
node _T_274 = or(_T_273, _T_267)
node _T_275 = and(_T_227, _T_274)
node _T_276 = or(UInt<1>(0h0), _T_275)
node _T_277 = and(UInt<1>(0h0), _T_276)
node _T_278 = asUInt(reset)
node _T_279 = eq(_T_278, UInt<1>(0h0))
when _T_279 :
node _T_280 = eq(_T_277, UInt<1>(0h0))
when _T_280 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_277, UInt<1>(0h1), "") : assert_3
node _T_281 = asUInt(reset)
node _T_282 = eq(_T_281, UInt<1>(0h0))
when _T_282 :
node _T_283 = eq(source_ok, UInt<1>(0h0))
when _T_283 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_284 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_285 = asUInt(reset)
node _T_286 = eq(_T_285, UInt<1>(0h0))
when _T_286 :
node _T_287 = eq(_T_284, UInt<1>(0h0))
when _T_287 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_284, UInt<1>(0h1), "") : assert_5
node _T_288 = asUInt(reset)
node _T_289 = eq(_T_288, UInt<1>(0h0))
when _T_289 :
node _T_290 = eq(is_aligned, UInt<1>(0h0))
when _T_290 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_291 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_292 = asUInt(reset)
node _T_293 = eq(_T_292, UInt<1>(0h0))
when _T_293 :
node _T_294 = eq(_T_291, UInt<1>(0h0))
when _T_294 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_291, UInt<1>(0h1), "") : assert_7
node _T_295 = not(io.in.a.bits.mask)
node _T_296 = eq(_T_295, UInt<1>(0h0))
node _T_297 = asUInt(reset)
node _T_298 = eq(_T_297, UInt<1>(0h0))
when _T_298 :
node _T_299 = eq(_T_296, UInt<1>(0h0))
when _T_299 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_296, UInt<1>(0h1), "") : assert_8
node _T_300 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_301 = asUInt(reset)
node _T_302 = eq(_T_301, UInt<1>(0h0))
when _T_302 :
node _T_303 = eq(_T_300, UInt<1>(0h0))
when _T_303 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_300, UInt<1>(0h1), "") : assert_9
node _T_304 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_304 :
node _T_305 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_306 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_307 = and(_T_305, _T_306)
node _T_308 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 2, 0)
node _T_309 = shr(io.in.a.bits.source, 3)
node _T_310 = eq(_T_309, UInt<2>(0h2))
node _T_311 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_312 = and(_T_310, _T_311)
node _T_313 = leq(uncommonBits_12, UInt<3>(0h7))
node _T_314 = and(_T_312, _T_313)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 2, 0)
node _T_315 = shr(io.in.a.bits.source, 3)
node _T_316 = eq(_T_315, UInt<2>(0h3))
node _T_317 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_318 = and(_T_316, _T_317)
node _T_319 = leq(uncommonBits_13, UInt<3>(0h7))
node _T_320 = and(_T_318, _T_319)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_321 = shr(io.in.a.bits.source, 2)
node _T_322 = eq(_T_321, UInt<1>(0h0))
node _T_323 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_324 = and(_T_322, _T_323)
node _T_325 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_326 = and(_T_324, _T_325)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_327 = shr(io.in.a.bits.source, 2)
node _T_328 = eq(_T_327, UInt<1>(0h1))
node _T_329 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_330 = and(_T_328, _T_329)
node _T_331 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_332 = and(_T_330, _T_331)
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0)
node _T_333 = shr(io.in.a.bits.source, 2)
node _T_334 = eq(_T_333, UInt<2>(0h2))
node _T_335 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_336 = and(_T_334, _T_335)
node _T_337 = leq(uncommonBits_16, UInt<2>(0h3))
node _T_338 = and(_T_336, _T_337)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0)
node _T_339 = shr(io.in.a.bits.source, 2)
node _T_340 = eq(_T_339, UInt<2>(0h3))
node _T_341 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_342 = and(_T_340, _T_341)
node _T_343 = leq(uncommonBits_17, UInt<2>(0h3))
node _T_344 = and(_T_342, _T_343)
node _T_345 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_346 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_347 = or(_T_308, _T_314)
node _T_348 = or(_T_347, _T_320)
node _T_349 = or(_T_348, _T_326)
node _T_350 = or(_T_349, _T_332)
node _T_351 = or(_T_350, _T_338)
node _T_352 = or(_T_351, _T_344)
node _T_353 = or(_T_352, _T_345)
node _T_354 = or(_T_353, _T_346)
node _T_355 = and(_T_307, _T_354)
node _T_356 = or(UInt<1>(0h0), _T_355)
node _T_357 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_358 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_359 = cvt(_T_358)
node _T_360 = and(_T_359, asSInt(UInt<14>(0h2000)))
node _T_361 = asSInt(_T_360)
node _T_362 = eq(_T_361, asSInt(UInt<1>(0h0)))
node _T_363 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_364 = cvt(_T_363)
node _T_365 = and(_T_364, asSInt(UInt<13>(0h1000)))
node _T_366 = asSInt(_T_365)
node _T_367 = eq(_T_366, asSInt(UInt<1>(0h0)))
node _T_368 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_369 = cvt(_T_368)
node _T_370 = and(_T_369, asSInt(UInt<17>(0h10000)))
node _T_371 = asSInt(_T_370)
node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0)))
node _T_373 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_374 = cvt(_T_373)
node _T_375 = and(_T_374, asSInt(UInt<18>(0h2f000)))
node _T_376 = asSInt(_T_375)
node _T_377 = eq(_T_376, asSInt(UInt<1>(0h0)))
node _T_378 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_379 = cvt(_T_378)
node _T_380 = and(_T_379, asSInt(UInt<17>(0h10000)))
node _T_381 = asSInt(_T_380)
node _T_382 = eq(_T_381, asSInt(UInt<1>(0h0)))
node _T_383 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_384 = cvt(_T_383)
node _T_385 = and(_T_384, asSInt(UInt<27>(0h4000000)))
node _T_386 = asSInt(_T_385)
node _T_387 = eq(_T_386, asSInt(UInt<1>(0h0)))
node _T_388 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_389 = cvt(_T_388)
node _T_390 = and(_T_389, asSInt(UInt<13>(0h1000)))
node _T_391 = asSInt(_T_390)
node _T_392 = eq(_T_391, asSInt(UInt<1>(0h0)))
node _T_393 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_394 = cvt(_T_393)
node _T_395 = and(_T_394, asSInt(UInt<15>(0h4000)))
node _T_396 = asSInt(_T_395)
node _T_397 = eq(_T_396, asSInt(UInt<1>(0h0)))
node _T_398 = or(_T_362, _T_367)
node _T_399 = or(_T_398, _T_372)
node _T_400 = or(_T_399, _T_377)
node _T_401 = or(_T_400, _T_382)
node _T_402 = or(_T_401, _T_387)
node _T_403 = or(_T_402, _T_392)
node _T_404 = or(_T_403, _T_397)
node _T_405 = and(_T_357, _T_404)
node _T_406 = or(UInt<1>(0h0), _T_405)
node _T_407 = and(_T_356, _T_406)
node _T_408 = asUInt(reset)
node _T_409 = eq(_T_408, UInt<1>(0h0))
when _T_409 :
node _T_410 = eq(_T_407, UInt<1>(0h0))
when _T_410 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_407, UInt<1>(0h1), "") : assert_10
node _T_411 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_412 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_413 = and(_T_411, _T_412)
node _T_414 = or(UInt<1>(0h0), _T_413)
node _T_415 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_416 = cvt(_T_415)
node _T_417 = and(_T_416, asSInt(UInt<14>(0h2000)))
node _T_418 = asSInt(_T_417)
node _T_419 = eq(_T_418, asSInt(UInt<1>(0h0)))
node _T_420 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_421 = cvt(_T_420)
node _T_422 = and(_T_421, asSInt(UInt<13>(0h1000)))
node _T_423 = asSInt(_T_422)
node _T_424 = eq(_T_423, asSInt(UInt<1>(0h0)))
node _T_425 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_426 = cvt(_T_425)
node _T_427 = and(_T_426, asSInt(UInt<17>(0h10000)))
node _T_428 = asSInt(_T_427)
node _T_429 = eq(_T_428, asSInt(UInt<1>(0h0)))
node _T_430 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_431 = cvt(_T_430)
node _T_432 = and(_T_431, asSInt(UInt<18>(0h2f000)))
node _T_433 = asSInt(_T_432)
node _T_434 = eq(_T_433, asSInt(UInt<1>(0h0)))
node _T_435 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_436 = cvt(_T_435)
node _T_437 = and(_T_436, asSInt(UInt<17>(0h10000)))
node _T_438 = asSInt(_T_437)
node _T_439 = eq(_T_438, asSInt(UInt<1>(0h0)))
node _T_440 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_441 = cvt(_T_440)
node _T_442 = and(_T_441, asSInt(UInt<27>(0h4000000)))
node _T_443 = asSInt(_T_442)
node _T_444 = eq(_T_443, asSInt(UInt<1>(0h0)))
node _T_445 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_446 = cvt(_T_445)
node _T_447 = and(_T_446, asSInt(UInt<13>(0h1000)))
node _T_448 = asSInt(_T_447)
node _T_449 = eq(_T_448, asSInt(UInt<1>(0h0)))
node _T_450 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_451 = cvt(_T_450)
node _T_452 = and(_T_451, asSInt(UInt<15>(0h4000)))
node _T_453 = asSInt(_T_452)
node _T_454 = eq(_T_453, asSInt(UInt<1>(0h0)))
node _T_455 = or(_T_419, _T_424)
node _T_456 = or(_T_455, _T_429)
node _T_457 = or(_T_456, _T_434)
node _T_458 = or(_T_457, _T_439)
node _T_459 = or(_T_458, _T_444)
node _T_460 = or(_T_459, _T_449)
node _T_461 = or(_T_460, _T_454)
node _T_462 = and(_T_414, _T_461)
node _T_463 = or(UInt<1>(0h0), _T_462)
node _T_464 = and(UInt<1>(0h0), _T_463)
node _T_465 = asUInt(reset)
node _T_466 = eq(_T_465, UInt<1>(0h0))
when _T_466 :
node _T_467 = eq(_T_464, UInt<1>(0h0))
when _T_467 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_464, UInt<1>(0h1), "") : assert_11
node _T_468 = asUInt(reset)
node _T_469 = eq(_T_468, UInt<1>(0h0))
when _T_469 :
node _T_470 = eq(source_ok, UInt<1>(0h0))
when _T_470 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_471 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_472 = asUInt(reset)
node _T_473 = eq(_T_472, UInt<1>(0h0))
when _T_473 :
node _T_474 = eq(_T_471, UInt<1>(0h0))
when _T_474 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_471, UInt<1>(0h1), "") : assert_13
node _T_475 = asUInt(reset)
node _T_476 = eq(_T_475, UInt<1>(0h0))
when _T_476 :
node _T_477 = eq(is_aligned, UInt<1>(0h0))
when _T_477 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_478 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_479 = asUInt(reset)
node _T_480 = eq(_T_479, UInt<1>(0h0))
when _T_480 :
node _T_481 = eq(_T_478, UInt<1>(0h0))
when _T_481 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_478, UInt<1>(0h1), "") : assert_15
node _T_482 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_483 = asUInt(reset)
node _T_484 = eq(_T_483, UInt<1>(0h0))
when _T_484 :
node _T_485 = eq(_T_482, UInt<1>(0h0))
when _T_485 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_482, UInt<1>(0h1), "") : assert_16
node _T_486 = not(io.in.a.bits.mask)
node _T_487 = eq(_T_486, UInt<1>(0h0))
node _T_488 = asUInt(reset)
node _T_489 = eq(_T_488, UInt<1>(0h0))
when _T_489 :
node _T_490 = eq(_T_487, UInt<1>(0h0))
when _T_490 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_487, UInt<1>(0h1), "") : assert_17
node _T_491 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_492 = asUInt(reset)
node _T_493 = eq(_T_492, UInt<1>(0h0))
when _T_493 :
node _T_494 = eq(_T_491, UInt<1>(0h0))
when _T_494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_491, UInt<1>(0h1), "") : assert_18
node _T_495 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_495 :
node _T_496 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_497 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_498 = and(_T_496, _T_497)
node _T_499 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 2, 0)
node _T_500 = shr(io.in.a.bits.source, 3)
node _T_501 = eq(_T_500, UInt<2>(0h2))
node _T_502 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_503 = and(_T_501, _T_502)
node _T_504 = leq(uncommonBits_18, UInt<3>(0h7))
node _T_505 = and(_T_503, _T_504)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 2, 0)
node _T_506 = shr(io.in.a.bits.source, 3)
node _T_507 = eq(_T_506, UInt<2>(0h3))
node _T_508 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_509 = and(_T_507, _T_508)
node _T_510 = leq(uncommonBits_19, UInt<3>(0h7))
node _T_511 = and(_T_509, _T_510)
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_512 = shr(io.in.a.bits.source, 2)
node _T_513 = eq(_T_512, UInt<1>(0h0))
node _T_514 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_515 = and(_T_513, _T_514)
node _T_516 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_517 = and(_T_515, _T_516)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_518 = shr(io.in.a.bits.source, 2)
node _T_519 = eq(_T_518, UInt<1>(0h1))
node _T_520 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_521 = and(_T_519, _T_520)
node _T_522 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_523 = and(_T_521, _T_522)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0)
node _T_524 = shr(io.in.a.bits.source, 2)
node _T_525 = eq(_T_524, UInt<2>(0h2))
node _T_526 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_527 = and(_T_525, _T_526)
node _T_528 = leq(uncommonBits_22, UInt<2>(0h3))
node _T_529 = and(_T_527, _T_528)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0)
node _T_530 = shr(io.in.a.bits.source, 2)
node _T_531 = eq(_T_530, UInt<2>(0h3))
node _T_532 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_533 = and(_T_531, _T_532)
node _T_534 = leq(uncommonBits_23, UInt<2>(0h3))
node _T_535 = and(_T_533, _T_534)
node _T_536 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_537 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_538 = or(_T_499, _T_505)
node _T_539 = or(_T_538, _T_511)
node _T_540 = or(_T_539, _T_517)
node _T_541 = or(_T_540, _T_523)
node _T_542 = or(_T_541, _T_529)
node _T_543 = or(_T_542, _T_535)
node _T_544 = or(_T_543, _T_536)
node _T_545 = or(_T_544, _T_537)
node _T_546 = and(_T_498, _T_545)
node _T_547 = or(UInt<1>(0h0), _T_546)
node _T_548 = asUInt(reset)
node _T_549 = eq(_T_548, UInt<1>(0h0))
when _T_549 :
node _T_550 = eq(_T_547, UInt<1>(0h0))
when _T_550 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_547, UInt<1>(0h1), "") : assert_19
node _T_551 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_552 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_553 = and(_T_551, _T_552)
node _T_554 = or(UInt<1>(0h0), _T_553)
node _T_555 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_556 = cvt(_T_555)
node _T_557 = and(_T_556, asSInt(UInt<13>(0h1000)))
node _T_558 = asSInt(_T_557)
node _T_559 = eq(_T_558, asSInt(UInt<1>(0h0)))
node _T_560 = and(_T_554, _T_559)
node _T_561 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_562 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_563 = and(_T_561, _T_562)
node _T_564 = or(UInt<1>(0h0), _T_563)
node _T_565 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_566 = cvt(_T_565)
node _T_567 = and(_T_566, asSInt(UInt<14>(0h2000)))
node _T_568 = asSInt(_T_567)
node _T_569 = eq(_T_568, asSInt(UInt<1>(0h0)))
node _T_570 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_571 = cvt(_T_570)
node _T_572 = and(_T_571, asSInt(UInt<17>(0h10000)))
node _T_573 = asSInt(_T_572)
node _T_574 = eq(_T_573, asSInt(UInt<1>(0h0)))
node _T_575 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_576 = cvt(_T_575)
node _T_577 = and(_T_576, asSInt(UInt<18>(0h2f000)))
node _T_578 = asSInt(_T_577)
node _T_579 = eq(_T_578, asSInt(UInt<1>(0h0)))
node _T_580 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_581 = cvt(_T_580)
node _T_582 = and(_T_581, asSInt(UInt<17>(0h10000)))
node _T_583 = asSInt(_T_582)
node _T_584 = eq(_T_583, asSInt(UInt<1>(0h0)))
node _T_585 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_586 = cvt(_T_585)
node _T_587 = and(_T_586, asSInt(UInt<27>(0h4000000)))
node _T_588 = asSInt(_T_587)
node _T_589 = eq(_T_588, asSInt(UInt<1>(0h0)))
node _T_590 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_591 = cvt(_T_590)
node _T_592 = and(_T_591, asSInt(UInt<13>(0h1000)))
node _T_593 = asSInt(_T_592)
node _T_594 = eq(_T_593, asSInt(UInt<1>(0h0)))
node _T_595 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_596 = cvt(_T_595)
node _T_597 = and(_T_596, asSInt(UInt<15>(0h4000)))
node _T_598 = asSInt(_T_597)
node _T_599 = eq(_T_598, asSInt(UInt<1>(0h0)))
node _T_600 = or(_T_569, _T_574)
node _T_601 = or(_T_600, _T_579)
node _T_602 = or(_T_601, _T_584)
node _T_603 = or(_T_602, _T_589)
node _T_604 = or(_T_603, _T_594)
node _T_605 = or(_T_604, _T_599)
node _T_606 = and(_T_564, _T_605)
node _T_607 = or(UInt<1>(0h0), _T_560)
node _T_608 = or(_T_607, _T_606)
node _T_609 = asUInt(reset)
node _T_610 = eq(_T_609, UInt<1>(0h0))
when _T_610 :
node _T_611 = eq(_T_608, UInt<1>(0h0))
when _T_611 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_608, UInt<1>(0h1), "") : assert_20
node _T_612 = asUInt(reset)
node _T_613 = eq(_T_612, UInt<1>(0h0))
when _T_613 :
node _T_614 = eq(source_ok, UInt<1>(0h0))
when _T_614 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_615 = asUInt(reset)
node _T_616 = eq(_T_615, UInt<1>(0h0))
when _T_616 :
node _T_617 = eq(is_aligned, UInt<1>(0h0))
when _T_617 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_618 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_619 = asUInt(reset)
node _T_620 = eq(_T_619, UInt<1>(0h0))
when _T_620 :
node _T_621 = eq(_T_618, UInt<1>(0h0))
when _T_621 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_618, UInt<1>(0h1), "") : assert_23
node _T_622 = eq(io.in.a.bits.mask, mask)
node _T_623 = asUInt(reset)
node _T_624 = eq(_T_623, UInt<1>(0h0))
when _T_624 :
node _T_625 = eq(_T_622, UInt<1>(0h0))
when _T_625 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_622, UInt<1>(0h1), "") : assert_24
node _T_626 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_627 = asUInt(reset)
node _T_628 = eq(_T_627, UInt<1>(0h0))
when _T_628 :
node _T_629 = eq(_T_626, UInt<1>(0h0))
when _T_629 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_626, UInt<1>(0h1), "") : assert_25
node _T_630 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_630 :
node _T_631 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_632 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_633 = and(_T_631, _T_632)
node _T_634 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 2, 0)
node _T_635 = shr(io.in.a.bits.source, 3)
node _T_636 = eq(_T_635, UInt<2>(0h2))
node _T_637 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_638 = and(_T_636, _T_637)
node _T_639 = leq(uncommonBits_24, UInt<3>(0h7))
node _T_640 = and(_T_638, _T_639)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 2, 0)
node _T_641 = shr(io.in.a.bits.source, 3)
node _T_642 = eq(_T_641, UInt<2>(0h3))
node _T_643 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_644 = and(_T_642, _T_643)
node _T_645 = leq(uncommonBits_25, UInt<3>(0h7))
node _T_646 = and(_T_644, _T_645)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_647 = shr(io.in.a.bits.source, 2)
node _T_648 = eq(_T_647, UInt<1>(0h0))
node _T_649 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_650 = and(_T_648, _T_649)
node _T_651 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_652 = and(_T_650, _T_651)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_653 = shr(io.in.a.bits.source, 2)
node _T_654 = eq(_T_653, UInt<1>(0h1))
node _T_655 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_656 = and(_T_654, _T_655)
node _T_657 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_658 = and(_T_656, _T_657)
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0)
node _T_659 = shr(io.in.a.bits.source, 2)
node _T_660 = eq(_T_659, UInt<2>(0h2))
node _T_661 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_662 = and(_T_660, _T_661)
node _T_663 = leq(uncommonBits_28, UInt<2>(0h3))
node _T_664 = and(_T_662, _T_663)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0)
node _T_665 = shr(io.in.a.bits.source, 2)
node _T_666 = eq(_T_665, UInt<2>(0h3))
node _T_667 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_668 = and(_T_666, _T_667)
node _T_669 = leq(uncommonBits_29, UInt<2>(0h3))
node _T_670 = and(_T_668, _T_669)
node _T_671 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_672 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_673 = or(_T_634, _T_640)
node _T_674 = or(_T_673, _T_646)
node _T_675 = or(_T_674, _T_652)
node _T_676 = or(_T_675, _T_658)
node _T_677 = or(_T_676, _T_664)
node _T_678 = or(_T_677, _T_670)
node _T_679 = or(_T_678, _T_671)
node _T_680 = or(_T_679, _T_672)
node _T_681 = and(_T_633, _T_680)
node _T_682 = or(UInt<1>(0h0), _T_681)
node _T_683 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_684 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_685 = and(_T_683, _T_684)
node _T_686 = or(UInt<1>(0h0), _T_685)
node _T_687 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_688 = cvt(_T_687)
node _T_689 = and(_T_688, asSInt(UInt<13>(0h1000)))
node _T_690 = asSInt(_T_689)
node _T_691 = eq(_T_690, asSInt(UInt<1>(0h0)))
node _T_692 = and(_T_686, _T_691)
node _T_693 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_694 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_695 = and(_T_693, _T_694)
node _T_696 = or(UInt<1>(0h0), _T_695)
node _T_697 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_698 = cvt(_T_697)
node _T_699 = and(_T_698, asSInt(UInt<14>(0h2000)))
node _T_700 = asSInt(_T_699)
node _T_701 = eq(_T_700, asSInt(UInt<1>(0h0)))
node _T_702 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_703 = cvt(_T_702)
node _T_704 = and(_T_703, asSInt(UInt<18>(0h2f000)))
node _T_705 = asSInt(_T_704)
node _T_706 = eq(_T_705, asSInt(UInt<1>(0h0)))
node _T_707 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_708 = cvt(_T_707)
node _T_709 = and(_T_708, asSInt(UInt<17>(0h10000)))
node _T_710 = asSInt(_T_709)
node _T_711 = eq(_T_710, asSInt(UInt<1>(0h0)))
node _T_712 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_713 = cvt(_T_712)
node _T_714 = and(_T_713, asSInt(UInt<27>(0h4000000)))
node _T_715 = asSInt(_T_714)
node _T_716 = eq(_T_715, asSInt(UInt<1>(0h0)))
node _T_717 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_718 = cvt(_T_717)
node _T_719 = and(_T_718, asSInt(UInt<13>(0h1000)))
node _T_720 = asSInt(_T_719)
node _T_721 = eq(_T_720, asSInt(UInt<1>(0h0)))
node _T_722 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_723 = cvt(_T_722)
node _T_724 = and(_T_723, asSInt(UInt<15>(0h4000)))
node _T_725 = asSInt(_T_724)
node _T_726 = eq(_T_725, asSInt(UInt<1>(0h0)))
node _T_727 = or(_T_701, _T_706)
node _T_728 = or(_T_727, _T_711)
node _T_729 = or(_T_728, _T_716)
node _T_730 = or(_T_729, _T_721)
node _T_731 = or(_T_730, _T_726)
node _T_732 = and(_T_696, _T_731)
node _T_733 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_734 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_735 = cvt(_T_734)
node _T_736 = and(_T_735, asSInt(UInt<17>(0h10000)))
node _T_737 = asSInt(_T_736)
node _T_738 = eq(_T_737, asSInt(UInt<1>(0h0)))
node _T_739 = and(_T_733, _T_738)
node _T_740 = or(UInt<1>(0h0), _T_692)
node _T_741 = or(_T_740, _T_732)
node _T_742 = or(_T_741, _T_739)
node _T_743 = and(_T_682, _T_742)
node _T_744 = asUInt(reset)
node _T_745 = eq(_T_744, UInt<1>(0h0))
when _T_745 :
node _T_746 = eq(_T_743, UInt<1>(0h0))
when _T_746 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_743, UInt<1>(0h1), "") : assert_26
node _T_747 = asUInt(reset)
node _T_748 = eq(_T_747, UInt<1>(0h0))
when _T_748 :
node _T_749 = eq(source_ok, UInt<1>(0h0))
when _T_749 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_750 = asUInt(reset)
node _T_751 = eq(_T_750, UInt<1>(0h0))
when _T_751 :
node _T_752 = eq(is_aligned, UInt<1>(0h0))
when _T_752 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_753 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_754 = asUInt(reset)
node _T_755 = eq(_T_754, UInt<1>(0h0))
when _T_755 :
node _T_756 = eq(_T_753, UInt<1>(0h0))
when _T_756 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_753, UInt<1>(0h1), "") : assert_29
node _T_757 = eq(io.in.a.bits.mask, mask)
node _T_758 = asUInt(reset)
node _T_759 = eq(_T_758, UInt<1>(0h0))
when _T_759 :
node _T_760 = eq(_T_757, UInt<1>(0h0))
when _T_760 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_757, UInt<1>(0h1), "") : assert_30
node _T_761 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_761 :
node _T_762 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_763 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_764 = and(_T_762, _T_763)
node _T_765 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 2, 0)
node _T_766 = shr(io.in.a.bits.source, 3)
node _T_767 = eq(_T_766, UInt<2>(0h2))
node _T_768 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_769 = and(_T_767, _T_768)
node _T_770 = leq(uncommonBits_30, UInt<3>(0h7))
node _T_771 = and(_T_769, _T_770)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 2, 0)
node _T_772 = shr(io.in.a.bits.source, 3)
node _T_773 = eq(_T_772, UInt<2>(0h3))
node _T_774 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_775 = and(_T_773, _T_774)
node _T_776 = leq(uncommonBits_31, UInt<3>(0h7))
node _T_777 = and(_T_775, _T_776)
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_778 = shr(io.in.a.bits.source, 2)
node _T_779 = eq(_T_778, UInt<1>(0h0))
node _T_780 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_781 = and(_T_779, _T_780)
node _T_782 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_783 = and(_T_781, _T_782)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_784 = shr(io.in.a.bits.source, 2)
node _T_785 = eq(_T_784, UInt<1>(0h1))
node _T_786 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_787 = and(_T_785, _T_786)
node _T_788 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_789 = and(_T_787, _T_788)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0)
node _T_790 = shr(io.in.a.bits.source, 2)
node _T_791 = eq(_T_790, UInt<2>(0h2))
node _T_792 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_793 = and(_T_791, _T_792)
node _T_794 = leq(uncommonBits_34, UInt<2>(0h3))
node _T_795 = and(_T_793, _T_794)
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0)
node _T_796 = shr(io.in.a.bits.source, 2)
node _T_797 = eq(_T_796, UInt<2>(0h3))
node _T_798 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_799 = and(_T_797, _T_798)
node _T_800 = leq(uncommonBits_35, UInt<2>(0h3))
node _T_801 = and(_T_799, _T_800)
node _T_802 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_803 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_804 = or(_T_765, _T_771)
node _T_805 = or(_T_804, _T_777)
node _T_806 = or(_T_805, _T_783)
node _T_807 = or(_T_806, _T_789)
node _T_808 = or(_T_807, _T_795)
node _T_809 = or(_T_808, _T_801)
node _T_810 = or(_T_809, _T_802)
node _T_811 = or(_T_810, _T_803)
node _T_812 = and(_T_764, _T_811)
node _T_813 = or(UInt<1>(0h0), _T_812)
node _T_814 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_815 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_816 = and(_T_814, _T_815)
node _T_817 = or(UInt<1>(0h0), _T_816)
node _T_818 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_819 = cvt(_T_818)
node _T_820 = and(_T_819, asSInt(UInt<13>(0h1000)))
node _T_821 = asSInt(_T_820)
node _T_822 = eq(_T_821, asSInt(UInt<1>(0h0)))
node _T_823 = and(_T_817, _T_822)
node _T_824 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_825 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_826 = and(_T_824, _T_825)
node _T_827 = or(UInt<1>(0h0), _T_826)
node _T_828 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_829 = cvt(_T_828)
node _T_830 = and(_T_829, asSInt(UInt<14>(0h2000)))
node _T_831 = asSInt(_T_830)
node _T_832 = eq(_T_831, asSInt(UInt<1>(0h0)))
node _T_833 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_834 = cvt(_T_833)
node _T_835 = and(_T_834, asSInt(UInt<18>(0h2f000)))
node _T_836 = asSInt(_T_835)
node _T_837 = eq(_T_836, asSInt(UInt<1>(0h0)))
node _T_838 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_839 = cvt(_T_838)
node _T_840 = and(_T_839, asSInt(UInt<17>(0h10000)))
node _T_841 = asSInt(_T_840)
node _T_842 = eq(_T_841, asSInt(UInt<1>(0h0)))
node _T_843 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_844 = cvt(_T_843)
node _T_845 = and(_T_844, asSInt(UInt<27>(0h4000000)))
node _T_846 = asSInt(_T_845)
node _T_847 = eq(_T_846, asSInt(UInt<1>(0h0)))
node _T_848 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_849 = cvt(_T_848)
node _T_850 = and(_T_849, asSInt(UInt<13>(0h1000)))
node _T_851 = asSInt(_T_850)
node _T_852 = eq(_T_851, asSInt(UInt<1>(0h0)))
node _T_853 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_854 = cvt(_T_853)
node _T_855 = and(_T_854, asSInt(UInt<15>(0h4000)))
node _T_856 = asSInt(_T_855)
node _T_857 = eq(_T_856, asSInt(UInt<1>(0h0)))
node _T_858 = or(_T_832, _T_837)
node _T_859 = or(_T_858, _T_842)
node _T_860 = or(_T_859, _T_847)
node _T_861 = or(_T_860, _T_852)
node _T_862 = or(_T_861, _T_857)
node _T_863 = and(_T_827, _T_862)
node _T_864 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_865 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_866 = cvt(_T_865)
node _T_867 = and(_T_866, asSInt(UInt<17>(0h10000)))
node _T_868 = asSInt(_T_867)
node _T_869 = eq(_T_868, asSInt(UInt<1>(0h0)))
node _T_870 = and(_T_864, _T_869)
node _T_871 = or(UInt<1>(0h0), _T_823)
node _T_872 = or(_T_871, _T_863)
node _T_873 = or(_T_872, _T_870)
node _T_874 = and(_T_813, _T_873)
node _T_875 = asUInt(reset)
node _T_876 = eq(_T_875, UInt<1>(0h0))
when _T_876 :
node _T_877 = eq(_T_874, UInt<1>(0h0))
when _T_877 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_874, UInt<1>(0h1), "") : assert_31
node _T_878 = asUInt(reset)
node _T_879 = eq(_T_878, UInt<1>(0h0))
when _T_879 :
node _T_880 = eq(source_ok, UInt<1>(0h0))
when _T_880 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_881 = asUInt(reset)
node _T_882 = eq(_T_881, UInt<1>(0h0))
when _T_882 :
node _T_883 = eq(is_aligned, UInt<1>(0h0))
when _T_883 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_884 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_885 = asUInt(reset)
node _T_886 = eq(_T_885, UInt<1>(0h0))
when _T_886 :
node _T_887 = eq(_T_884, UInt<1>(0h0))
when _T_887 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_884, UInt<1>(0h1), "") : assert_34
node _T_888 = not(mask)
node _T_889 = and(io.in.a.bits.mask, _T_888)
node _T_890 = eq(_T_889, UInt<1>(0h0))
node _T_891 = asUInt(reset)
node _T_892 = eq(_T_891, UInt<1>(0h0))
when _T_892 :
node _T_893 = eq(_T_890, UInt<1>(0h0))
when _T_893 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_890, UInt<1>(0h1), "") : assert_35
node _T_894 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_894 :
node _T_895 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_896 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_897 = and(_T_895, _T_896)
node _T_898 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_36 = bits(_uncommonBits_T_36, 2, 0)
node _T_899 = shr(io.in.a.bits.source, 3)
node _T_900 = eq(_T_899, UInt<2>(0h2))
node _T_901 = leq(UInt<1>(0h0), uncommonBits_36)
node _T_902 = and(_T_900, _T_901)
node _T_903 = leq(uncommonBits_36, UInt<3>(0h7))
node _T_904 = and(_T_902, _T_903)
node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_37 = bits(_uncommonBits_T_37, 2, 0)
node _T_905 = shr(io.in.a.bits.source, 3)
node _T_906 = eq(_T_905, UInt<2>(0h3))
node _T_907 = leq(UInt<1>(0h0), uncommonBits_37)
node _T_908 = and(_T_906, _T_907)
node _T_909 = leq(uncommonBits_37, UInt<3>(0h7))
node _T_910 = and(_T_908, _T_909)
node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0)
node _T_911 = shr(io.in.a.bits.source, 2)
node _T_912 = eq(_T_911, UInt<1>(0h0))
node _T_913 = leq(UInt<1>(0h0), uncommonBits_38)
node _T_914 = and(_T_912, _T_913)
node _T_915 = leq(uncommonBits_38, UInt<2>(0h3))
node _T_916 = and(_T_914, _T_915)
node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0)
node _T_917 = shr(io.in.a.bits.source, 2)
node _T_918 = eq(_T_917, UInt<1>(0h1))
node _T_919 = leq(UInt<1>(0h0), uncommonBits_39)
node _T_920 = and(_T_918, _T_919)
node _T_921 = leq(uncommonBits_39, UInt<2>(0h3))
node _T_922 = and(_T_920, _T_921)
node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0)
node _T_923 = shr(io.in.a.bits.source, 2)
node _T_924 = eq(_T_923, UInt<2>(0h2))
node _T_925 = leq(UInt<1>(0h0), uncommonBits_40)
node _T_926 = and(_T_924, _T_925)
node _T_927 = leq(uncommonBits_40, UInt<2>(0h3))
node _T_928 = and(_T_926, _T_927)
node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0)
node _T_929 = shr(io.in.a.bits.source, 2)
node _T_930 = eq(_T_929, UInt<2>(0h3))
node _T_931 = leq(UInt<1>(0h0), uncommonBits_41)
node _T_932 = and(_T_930, _T_931)
node _T_933 = leq(uncommonBits_41, UInt<2>(0h3))
node _T_934 = and(_T_932, _T_933)
node _T_935 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_936 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_937 = or(_T_898, _T_904)
node _T_938 = or(_T_937, _T_910)
node _T_939 = or(_T_938, _T_916)
node _T_940 = or(_T_939, _T_922)
node _T_941 = or(_T_940, _T_928)
node _T_942 = or(_T_941, _T_934)
node _T_943 = or(_T_942, _T_935)
node _T_944 = or(_T_943, _T_936)
node _T_945 = and(_T_897, _T_944)
node _T_946 = or(UInt<1>(0h0), _T_945)
node _T_947 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_948 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_949 = and(_T_947, _T_948)
node _T_950 = or(UInt<1>(0h0), _T_949)
node _T_951 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_952 = cvt(_T_951)
node _T_953 = and(_T_952, asSInt(UInt<14>(0h2000)))
node _T_954 = asSInt(_T_953)
node _T_955 = eq(_T_954, asSInt(UInt<1>(0h0)))
node _T_956 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_957 = cvt(_T_956)
node _T_958 = and(_T_957, asSInt(UInt<13>(0h1000)))
node _T_959 = asSInt(_T_958)
node _T_960 = eq(_T_959, asSInt(UInt<1>(0h0)))
node _T_961 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_962 = cvt(_T_961)
node _T_963 = and(_T_962, asSInt(UInt<18>(0h2f000)))
node _T_964 = asSInt(_T_963)
node _T_965 = eq(_T_964, asSInt(UInt<1>(0h0)))
node _T_966 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_967 = cvt(_T_966)
node _T_968 = and(_T_967, asSInt(UInt<17>(0h10000)))
node _T_969 = asSInt(_T_968)
node _T_970 = eq(_T_969, asSInt(UInt<1>(0h0)))
node _T_971 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_972 = cvt(_T_971)
node _T_973 = and(_T_972, asSInt(UInt<27>(0h4000000)))
node _T_974 = asSInt(_T_973)
node _T_975 = eq(_T_974, asSInt(UInt<1>(0h0)))
node _T_976 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_977 = cvt(_T_976)
node _T_978 = and(_T_977, asSInt(UInt<13>(0h1000)))
node _T_979 = asSInt(_T_978)
node _T_980 = eq(_T_979, asSInt(UInt<1>(0h0)))
node _T_981 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_982 = cvt(_T_981)
node _T_983 = and(_T_982, asSInt(UInt<15>(0h4000)))
node _T_984 = asSInt(_T_983)
node _T_985 = eq(_T_984, asSInt(UInt<1>(0h0)))
node _T_986 = or(_T_955, _T_960)
node _T_987 = or(_T_986, _T_965)
node _T_988 = or(_T_987, _T_970)
node _T_989 = or(_T_988, _T_975)
node _T_990 = or(_T_989, _T_980)
node _T_991 = or(_T_990, _T_985)
node _T_992 = and(_T_950, _T_991)
node _T_993 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_994 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_995 = cvt(_T_994)
node _T_996 = and(_T_995, asSInt(UInt<17>(0h10000)))
node _T_997 = asSInt(_T_996)
node _T_998 = eq(_T_997, asSInt(UInt<1>(0h0)))
node _T_999 = and(_T_993, _T_998)
node _T_1000 = or(UInt<1>(0h0), _T_992)
node _T_1001 = or(_T_1000, _T_999)
node _T_1002 = and(_T_946, _T_1001)
node _T_1003 = asUInt(reset)
node _T_1004 = eq(_T_1003, UInt<1>(0h0))
when _T_1004 :
node _T_1005 = eq(_T_1002, UInt<1>(0h0))
when _T_1005 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_1002, UInt<1>(0h1), "") : assert_36
node _T_1006 = asUInt(reset)
node _T_1007 = eq(_T_1006, UInt<1>(0h0))
when _T_1007 :
node _T_1008 = eq(source_ok, UInt<1>(0h0))
when _T_1008 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_1009 = asUInt(reset)
node _T_1010 = eq(_T_1009, UInt<1>(0h0))
when _T_1010 :
node _T_1011 = eq(is_aligned, UInt<1>(0h0))
when _T_1011 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_1012 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_1013 = asUInt(reset)
node _T_1014 = eq(_T_1013, UInt<1>(0h0))
when _T_1014 :
node _T_1015 = eq(_T_1012, UInt<1>(0h0))
when _T_1015 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_1012, UInt<1>(0h1), "") : assert_39
node _T_1016 = eq(io.in.a.bits.mask, mask)
node _T_1017 = asUInt(reset)
node _T_1018 = eq(_T_1017, UInt<1>(0h0))
when _T_1018 :
node _T_1019 = eq(_T_1016, UInt<1>(0h0))
when _T_1019 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_1016, UInt<1>(0h1), "") : assert_40
node _T_1020 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_1020 :
node _T_1021 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1022 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1023 = and(_T_1021, _T_1022)
node _T_1024 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_42 = bits(_uncommonBits_T_42, 2, 0)
node _T_1025 = shr(io.in.a.bits.source, 3)
node _T_1026 = eq(_T_1025, UInt<2>(0h2))
node _T_1027 = leq(UInt<1>(0h0), uncommonBits_42)
node _T_1028 = and(_T_1026, _T_1027)
node _T_1029 = leq(uncommonBits_42, UInt<3>(0h7))
node _T_1030 = and(_T_1028, _T_1029)
node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_43 = bits(_uncommonBits_T_43, 2, 0)
node _T_1031 = shr(io.in.a.bits.source, 3)
node _T_1032 = eq(_T_1031, UInt<2>(0h3))
node _T_1033 = leq(UInt<1>(0h0), uncommonBits_43)
node _T_1034 = and(_T_1032, _T_1033)
node _T_1035 = leq(uncommonBits_43, UInt<3>(0h7))
node _T_1036 = and(_T_1034, _T_1035)
node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0)
node _T_1037 = shr(io.in.a.bits.source, 2)
node _T_1038 = eq(_T_1037, UInt<1>(0h0))
node _T_1039 = leq(UInt<1>(0h0), uncommonBits_44)
node _T_1040 = and(_T_1038, _T_1039)
node _T_1041 = leq(uncommonBits_44, UInt<2>(0h3))
node _T_1042 = and(_T_1040, _T_1041)
node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0)
node _T_1043 = shr(io.in.a.bits.source, 2)
node _T_1044 = eq(_T_1043, UInt<1>(0h1))
node _T_1045 = leq(UInt<1>(0h0), uncommonBits_45)
node _T_1046 = and(_T_1044, _T_1045)
node _T_1047 = leq(uncommonBits_45, UInt<2>(0h3))
node _T_1048 = and(_T_1046, _T_1047)
node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_46 = bits(_uncommonBits_T_46, 1, 0)
node _T_1049 = shr(io.in.a.bits.source, 2)
node _T_1050 = eq(_T_1049, UInt<2>(0h2))
node _T_1051 = leq(UInt<1>(0h0), uncommonBits_46)
node _T_1052 = and(_T_1050, _T_1051)
node _T_1053 = leq(uncommonBits_46, UInt<2>(0h3))
node _T_1054 = and(_T_1052, _T_1053)
node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_47 = bits(_uncommonBits_T_47, 1, 0)
node _T_1055 = shr(io.in.a.bits.source, 2)
node _T_1056 = eq(_T_1055, UInt<2>(0h3))
node _T_1057 = leq(UInt<1>(0h0), uncommonBits_47)
node _T_1058 = and(_T_1056, _T_1057)
node _T_1059 = leq(uncommonBits_47, UInt<2>(0h3))
node _T_1060 = and(_T_1058, _T_1059)
node _T_1061 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_1062 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_1063 = or(_T_1024, _T_1030)
node _T_1064 = or(_T_1063, _T_1036)
node _T_1065 = or(_T_1064, _T_1042)
node _T_1066 = or(_T_1065, _T_1048)
node _T_1067 = or(_T_1066, _T_1054)
node _T_1068 = or(_T_1067, _T_1060)
node _T_1069 = or(_T_1068, _T_1061)
node _T_1070 = or(_T_1069, _T_1062)
node _T_1071 = and(_T_1023, _T_1070)
node _T_1072 = or(UInt<1>(0h0), _T_1071)
node _T_1073 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1074 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_1075 = and(_T_1073, _T_1074)
node _T_1076 = or(UInt<1>(0h0), _T_1075)
node _T_1077 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1078 = cvt(_T_1077)
node _T_1079 = and(_T_1078, asSInt(UInt<14>(0h2000)))
node _T_1080 = asSInt(_T_1079)
node _T_1081 = eq(_T_1080, asSInt(UInt<1>(0h0)))
node _T_1082 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_1083 = cvt(_T_1082)
node _T_1084 = and(_T_1083, asSInt(UInt<13>(0h1000)))
node _T_1085 = asSInt(_T_1084)
node _T_1086 = eq(_T_1085, asSInt(UInt<1>(0h0)))
node _T_1087 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1088 = cvt(_T_1087)
node _T_1089 = and(_T_1088, asSInt(UInt<18>(0h2f000)))
node _T_1090 = asSInt(_T_1089)
node _T_1091 = eq(_T_1090, asSInt(UInt<1>(0h0)))
node _T_1092 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1093 = cvt(_T_1092)
node _T_1094 = and(_T_1093, asSInt(UInt<17>(0h10000)))
node _T_1095 = asSInt(_T_1094)
node _T_1096 = eq(_T_1095, asSInt(UInt<1>(0h0)))
node _T_1097 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1098 = cvt(_T_1097)
node _T_1099 = and(_T_1098, asSInt(UInt<27>(0h4000000)))
node _T_1100 = asSInt(_T_1099)
node _T_1101 = eq(_T_1100, asSInt(UInt<1>(0h0)))
node _T_1102 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1103 = cvt(_T_1102)
node _T_1104 = and(_T_1103, asSInt(UInt<13>(0h1000)))
node _T_1105 = asSInt(_T_1104)
node _T_1106 = eq(_T_1105, asSInt(UInt<1>(0h0)))
node _T_1107 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_1108 = cvt(_T_1107)
node _T_1109 = and(_T_1108, asSInt(UInt<15>(0h4000)))
node _T_1110 = asSInt(_T_1109)
node _T_1111 = eq(_T_1110, asSInt(UInt<1>(0h0)))
node _T_1112 = or(_T_1081, _T_1086)
node _T_1113 = or(_T_1112, _T_1091)
node _T_1114 = or(_T_1113, _T_1096)
node _T_1115 = or(_T_1114, _T_1101)
node _T_1116 = or(_T_1115, _T_1106)
node _T_1117 = or(_T_1116, _T_1111)
node _T_1118 = and(_T_1076, _T_1117)
node _T_1119 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1120 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1121 = cvt(_T_1120)
node _T_1122 = and(_T_1121, asSInt(UInt<17>(0h10000)))
node _T_1123 = asSInt(_T_1122)
node _T_1124 = eq(_T_1123, asSInt(UInt<1>(0h0)))
node _T_1125 = and(_T_1119, _T_1124)
node _T_1126 = or(UInt<1>(0h0), _T_1118)
node _T_1127 = or(_T_1126, _T_1125)
node _T_1128 = and(_T_1072, _T_1127)
node _T_1129 = asUInt(reset)
node _T_1130 = eq(_T_1129, UInt<1>(0h0))
when _T_1130 :
node _T_1131 = eq(_T_1128, UInt<1>(0h0))
when _T_1131 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_1128, UInt<1>(0h1), "") : assert_41
node _T_1132 = asUInt(reset)
node _T_1133 = eq(_T_1132, UInt<1>(0h0))
when _T_1133 :
node _T_1134 = eq(source_ok, UInt<1>(0h0))
when _T_1134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_1135 = asUInt(reset)
node _T_1136 = eq(_T_1135, UInt<1>(0h0))
when _T_1136 :
node _T_1137 = eq(is_aligned, UInt<1>(0h0))
when _T_1137 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_1138 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_1139 = asUInt(reset)
node _T_1140 = eq(_T_1139, UInt<1>(0h0))
when _T_1140 :
node _T_1141 = eq(_T_1138, UInt<1>(0h0))
when _T_1141 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_1138, UInt<1>(0h1), "") : assert_44
node _T_1142 = eq(io.in.a.bits.mask, mask)
node _T_1143 = asUInt(reset)
node _T_1144 = eq(_T_1143, UInt<1>(0h0))
when _T_1144 :
node _T_1145 = eq(_T_1142, UInt<1>(0h0))
when _T_1145 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_1142, UInt<1>(0h1), "") : assert_45
node _T_1146 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_1146 :
node _T_1147 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1148 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1149 = and(_T_1147, _T_1148)
node _T_1150 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_48 = bits(_uncommonBits_T_48, 2, 0)
node _T_1151 = shr(io.in.a.bits.source, 3)
node _T_1152 = eq(_T_1151, UInt<2>(0h2))
node _T_1153 = leq(UInt<1>(0h0), uncommonBits_48)
node _T_1154 = and(_T_1152, _T_1153)
node _T_1155 = leq(uncommonBits_48, UInt<3>(0h7))
node _T_1156 = and(_T_1154, _T_1155)
node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_49 = bits(_uncommonBits_T_49, 2, 0)
node _T_1157 = shr(io.in.a.bits.source, 3)
node _T_1158 = eq(_T_1157, UInt<2>(0h3))
node _T_1159 = leq(UInt<1>(0h0), uncommonBits_49)
node _T_1160 = and(_T_1158, _T_1159)
node _T_1161 = leq(uncommonBits_49, UInt<3>(0h7))
node _T_1162 = and(_T_1160, _T_1161)
node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0)
node _T_1163 = shr(io.in.a.bits.source, 2)
node _T_1164 = eq(_T_1163, UInt<1>(0h0))
node _T_1165 = leq(UInt<1>(0h0), uncommonBits_50)
node _T_1166 = and(_T_1164, _T_1165)
node _T_1167 = leq(uncommonBits_50, UInt<2>(0h3))
node _T_1168 = and(_T_1166, _T_1167)
node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0)
node _T_1169 = shr(io.in.a.bits.source, 2)
node _T_1170 = eq(_T_1169, UInt<1>(0h1))
node _T_1171 = leq(UInt<1>(0h0), uncommonBits_51)
node _T_1172 = and(_T_1170, _T_1171)
node _T_1173 = leq(uncommonBits_51, UInt<2>(0h3))
node _T_1174 = and(_T_1172, _T_1173)
node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_52 = bits(_uncommonBits_T_52, 1, 0)
node _T_1175 = shr(io.in.a.bits.source, 2)
node _T_1176 = eq(_T_1175, UInt<2>(0h2))
node _T_1177 = leq(UInt<1>(0h0), uncommonBits_52)
node _T_1178 = and(_T_1176, _T_1177)
node _T_1179 = leq(uncommonBits_52, UInt<2>(0h3))
node _T_1180 = and(_T_1178, _T_1179)
node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_53 = bits(_uncommonBits_T_53, 1, 0)
node _T_1181 = shr(io.in.a.bits.source, 2)
node _T_1182 = eq(_T_1181, UInt<2>(0h3))
node _T_1183 = leq(UInt<1>(0h0), uncommonBits_53)
node _T_1184 = and(_T_1182, _T_1183)
node _T_1185 = leq(uncommonBits_53, UInt<2>(0h3))
node _T_1186 = and(_T_1184, _T_1185)
node _T_1187 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_1188 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_1189 = or(_T_1150, _T_1156)
node _T_1190 = or(_T_1189, _T_1162)
node _T_1191 = or(_T_1190, _T_1168)
node _T_1192 = or(_T_1191, _T_1174)
node _T_1193 = or(_T_1192, _T_1180)
node _T_1194 = or(_T_1193, _T_1186)
node _T_1195 = or(_T_1194, _T_1187)
node _T_1196 = or(_T_1195, _T_1188)
node _T_1197 = and(_T_1149, _T_1196)
node _T_1198 = or(UInt<1>(0h0), _T_1197)
node _T_1199 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1200 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1201 = and(_T_1199, _T_1200)
node _T_1202 = or(UInt<1>(0h0), _T_1201)
node _T_1203 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_1204 = cvt(_T_1203)
node _T_1205 = and(_T_1204, asSInt(UInt<13>(0h1000)))
node _T_1206 = asSInt(_T_1205)
node _T_1207 = eq(_T_1206, asSInt(UInt<1>(0h0)))
node _T_1208 = and(_T_1202, _T_1207)
node _T_1209 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1210 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1211 = cvt(_T_1210)
node _T_1212 = and(_T_1211, asSInt(UInt<14>(0h2000)))
node _T_1213 = asSInt(_T_1212)
node _T_1214 = eq(_T_1213, asSInt(UInt<1>(0h0)))
node _T_1215 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1216 = cvt(_T_1215)
node _T_1217 = and(_T_1216, asSInt(UInt<17>(0h10000)))
node _T_1218 = asSInt(_T_1217)
node _T_1219 = eq(_T_1218, asSInt(UInt<1>(0h0)))
node _T_1220 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1221 = cvt(_T_1220)
node _T_1222 = and(_T_1221, asSInt(UInt<18>(0h2f000)))
node _T_1223 = asSInt(_T_1222)
node _T_1224 = eq(_T_1223, asSInt(UInt<1>(0h0)))
node _T_1225 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1226 = cvt(_T_1225)
node _T_1227 = and(_T_1226, asSInt(UInt<17>(0h10000)))
node _T_1228 = asSInt(_T_1227)
node _T_1229 = eq(_T_1228, asSInt(UInt<1>(0h0)))
node _T_1230 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1231 = cvt(_T_1230)
node _T_1232 = and(_T_1231, asSInt(UInt<27>(0h4000000)))
node _T_1233 = asSInt(_T_1232)
node _T_1234 = eq(_T_1233, asSInt(UInt<1>(0h0)))
node _T_1235 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1236 = cvt(_T_1235)
node _T_1237 = and(_T_1236, asSInt(UInt<13>(0h1000)))
node _T_1238 = asSInt(_T_1237)
node _T_1239 = eq(_T_1238, asSInt(UInt<1>(0h0)))
node _T_1240 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_1241 = cvt(_T_1240)
node _T_1242 = and(_T_1241, asSInt(UInt<15>(0h4000)))
node _T_1243 = asSInt(_T_1242)
node _T_1244 = eq(_T_1243, asSInt(UInt<1>(0h0)))
node _T_1245 = or(_T_1214, _T_1219)
node _T_1246 = or(_T_1245, _T_1224)
node _T_1247 = or(_T_1246, _T_1229)
node _T_1248 = or(_T_1247, _T_1234)
node _T_1249 = or(_T_1248, _T_1239)
node _T_1250 = or(_T_1249, _T_1244)
node _T_1251 = and(_T_1209, _T_1250)
node _T_1252 = or(UInt<1>(0h0), _T_1208)
node _T_1253 = or(_T_1252, _T_1251)
node _T_1254 = and(_T_1198, _T_1253)
node _T_1255 = asUInt(reset)
node _T_1256 = eq(_T_1255, UInt<1>(0h0))
when _T_1256 :
node _T_1257 = eq(_T_1254, UInt<1>(0h0))
when _T_1257 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_1254, UInt<1>(0h1), "") : assert_46
node _T_1258 = asUInt(reset)
node _T_1259 = eq(_T_1258, UInt<1>(0h0))
when _T_1259 :
node _T_1260 = eq(source_ok, UInt<1>(0h0))
when _T_1260 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_1261 = asUInt(reset)
node _T_1262 = eq(_T_1261, UInt<1>(0h0))
when _T_1262 :
node _T_1263 = eq(is_aligned, UInt<1>(0h0))
when _T_1263 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_1264 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_1265 = asUInt(reset)
node _T_1266 = eq(_T_1265, UInt<1>(0h0))
when _T_1266 :
node _T_1267 = eq(_T_1264, UInt<1>(0h0))
when _T_1267 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_1264, UInt<1>(0h1), "") : assert_49
node _T_1268 = eq(io.in.a.bits.mask, mask)
node _T_1269 = asUInt(reset)
node _T_1270 = eq(_T_1269, UInt<1>(0h0))
when _T_1270 :
node _T_1271 = eq(_T_1268, UInt<1>(0h0))
when _T_1271 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_1268, UInt<1>(0h1), "") : assert_50
node _T_1272 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1273 = asUInt(reset)
node _T_1274 = eq(_T_1273, UInt<1>(0h0))
when _T_1274 :
node _T_1275 = eq(_T_1272, UInt<1>(0h0))
when _T_1275 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_1272, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_1276 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1277 = asUInt(reset)
node _T_1278 = eq(_T_1277, UInt<1>(0h0))
when _T_1278 :
node _T_1279 = eq(_T_1276, UInt<1>(0h0))
when _T_1279 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_1276, UInt<1>(0h1), "") : assert_52
node _source_ok_T_46 = eq(io.in.d.bits.source, UInt<6>(0h20))
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 2, 0)
node _source_ok_T_47 = shr(io.in.d.bits.source, 3)
node _source_ok_T_48 = eq(_source_ok_T_47, UInt<2>(0h2))
node _source_ok_T_49 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_50 = and(_source_ok_T_48, _source_ok_T_49)
node _source_ok_T_51 = leq(source_ok_uncommonBits_6, UInt<3>(0h7))
node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 2, 0)
node _source_ok_T_53 = shr(io.in.d.bits.source, 3)
node _source_ok_T_54 = eq(_source_ok_T_53, UInt<2>(0h3))
node _source_ok_T_55 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_56 = and(_source_ok_T_54, _source_ok_T_55)
node _source_ok_T_57 = leq(source_ok_uncommonBits_7, UInt<3>(0h7))
node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57)
node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0)
node _source_ok_T_59 = shr(io.in.d.bits.source, 2)
node _source_ok_T_60 = eq(_source_ok_T_59, UInt<1>(0h0))
node _source_ok_T_61 = leq(UInt<1>(0h0), source_ok_uncommonBits_8)
node _source_ok_T_62 = and(_source_ok_T_60, _source_ok_T_61)
node _source_ok_T_63 = leq(source_ok_uncommonBits_8, UInt<2>(0h3))
node _source_ok_T_64 = and(_source_ok_T_62, _source_ok_T_63)
node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0)
node _source_ok_T_65 = shr(io.in.d.bits.source, 2)
node _source_ok_T_66 = eq(_source_ok_T_65, UInt<1>(0h1))
node _source_ok_T_67 = leq(UInt<1>(0h0), source_ok_uncommonBits_9)
node _source_ok_T_68 = and(_source_ok_T_66, _source_ok_T_67)
node _source_ok_T_69 = leq(source_ok_uncommonBits_9, UInt<2>(0h3))
node _source_ok_T_70 = and(_source_ok_T_68, _source_ok_T_69)
node _source_ok_uncommonBits_T_10 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 1, 0)
node _source_ok_T_71 = shr(io.in.d.bits.source, 2)
node _source_ok_T_72 = eq(_source_ok_T_71, UInt<2>(0h2))
node _source_ok_T_73 = leq(UInt<1>(0h0), source_ok_uncommonBits_10)
node _source_ok_T_74 = and(_source_ok_T_72, _source_ok_T_73)
node _source_ok_T_75 = leq(source_ok_uncommonBits_10, UInt<2>(0h3))
node _source_ok_T_76 = and(_source_ok_T_74, _source_ok_T_75)
node _source_ok_uncommonBits_T_11 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 1, 0)
node _source_ok_T_77 = shr(io.in.d.bits.source, 2)
node _source_ok_T_78 = eq(_source_ok_T_77, UInt<2>(0h3))
node _source_ok_T_79 = leq(UInt<1>(0h0), source_ok_uncommonBits_11)
node _source_ok_T_80 = and(_source_ok_T_78, _source_ok_T_79)
node _source_ok_T_81 = leq(source_ok_uncommonBits_11, UInt<2>(0h3))
node _source_ok_T_82 = and(_source_ok_T_80, _source_ok_T_81)
node _source_ok_T_83 = eq(io.in.d.bits.source, UInt<7>(0h41))
node _source_ok_T_84 = eq(io.in.d.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE_1 : UInt<1>[9]
connect _source_ok_WIRE_1[0], _source_ok_T_46
connect _source_ok_WIRE_1[1], _source_ok_T_52
connect _source_ok_WIRE_1[2], _source_ok_T_58
connect _source_ok_WIRE_1[3], _source_ok_T_64
connect _source_ok_WIRE_1[4], _source_ok_T_70
connect _source_ok_WIRE_1[5], _source_ok_T_76
connect _source_ok_WIRE_1[6], _source_ok_T_82
connect _source_ok_WIRE_1[7], _source_ok_T_83
connect _source_ok_WIRE_1[8], _source_ok_T_84
node _source_ok_T_85 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_86 = or(_source_ok_T_85, _source_ok_WIRE_1[2])
node _source_ok_T_87 = or(_source_ok_T_86, _source_ok_WIRE_1[3])
node _source_ok_T_88 = or(_source_ok_T_87, _source_ok_WIRE_1[4])
node _source_ok_T_89 = or(_source_ok_T_88, _source_ok_WIRE_1[5])
node _source_ok_T_90 = or(_source_ok_T_89, _source_ok_WIRE_1[6])
node _source_ok_T_91 = or(_source_ok_T_90, _source_ok_WIRE_1[7])
node source_ok_1 = or(_source_ok_T_91, _source_ok_WIRE_1[8])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_1280 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1280 :
node _T_1281 = asUInt(reset)
node _T_1282 = eq(_T_1281, UInt<1>(0h0))
when _T_1282 :
node _T_1283 = eq(source_ok_1, UInt<1>(0h0))
when _T_1283 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_1284 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1285 = asUInt(reset)
node _T_1286 = eq(_T_1285, UInt<1>(0h0))
when _T_1286 :
node _T_1287 = eq(_T_1284, UInt<1>(0h0))
when _T_1287 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1284, UInt<1>(0h1), "") : assert_54
node _T_1288 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1289 = asUInt(reset)
node _T_1290 = eq(_T_1289, UInt<1>(0h0))
when _T_1290 :
node _T_1291 = eq(_T_1288, UInt<1>(0h0))
when _T_1291 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1288, UInt<1>(0h1), "") : assert_55
node _T_1292 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1293 = asUInt(reset)
node _T_1294 = eq(_T_1293, UInt<1>(0h0))
when _T_1294 :
node _T_1295 = eq(_T_1292, UInt<1>(0h0))
when _T_1295 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1292, UInt<1>(0h1), "") : assert_56
node _T_1296 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1297 = asUInt(reset)
node _T_1298 = eq(_T_1297, UInt<1>(0h0))
when _T_1298 :
node _T_1299 = eq(_T_1296, UInt<1>(0h0))
when _T_1299 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1296, UInt<1>(0h1), "") : assert_57
node _T_1300 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1300 :
node _T_1301 = asUInt(reset)
node _T_1302 = eq(_T_1301, UInt<1>(0h0))
when _T_1302 :
node _T_1303 = eq(source_ok_1, UInt<1>(0h0))
when _T_1303 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1304 = asUInt(reset)
node _T_1305 = eq(_T_1304, UInt<1>(0h0))
when _T_1305 :
node _T_1306 = eq(sink_ok, UInt<1>(0h0))
when _T_1306 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1307 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1308 = asUInt(reset)
node _T_1309 = eq(_T_1308, UInt<1>(0h0))
when _T_1309 :
node _T_1310 = eq(_T_1307, UInt<1>(0h0))
when _T_1310 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1307, UInt<1>(0h1), "") : assert_60
node _T_1311 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1312 = asUInt(reset)
node _T_1313 = eq(_T_1312, UInt<1>(0h0))
when _T_1313 :
node _T_1314 = eq(_T_1311, UInt<1>(0h0))
when _T_1314 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1311, UInt<1>(0h1), "") : assert_61
node _T_1315 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1316 = asUInt(reset)
node _T_1317 = eq(_T_1316, UInt<1>(0h0))
when _T_1317 :
node _T_1318 = eq(_T_1315, UInt<1>(0h0))
when _T_1318 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1315, UInt<1>(0h1), "") : assert_62
node _T_1319 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1320 = asUInt(reset)
node _T_1321 = eq(_T_1320, UInt<1>(0h0))
when _T_1321 :
node _T_1322 = eq(_T_1319, UInt<1>(0h0))
when _T_1322 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1319, UInt<1>(0h1), "") : assert_63
node _T_1323 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1324 = or(UInt<1>(0h1), _T_1323)
node _T_1325 = asUInt(reset)
node _T_1326 = eq(_T_1325, UInt<1>(0h0))
when _T_1326 :
node _T_1327 = eq(_T_1324, UInt<1>(0h0))
when _T_1327 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1324, UInt<1>(0h1), "") : assert_64
node _T_1328 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1328 :
node _T_1329 = asUInt(reset)
node _T_1330 = eq(_T_1329, UInt<1>(0h0))
when _T_1330 :
node _T_1331 = eq(source_ok_1, UInt<1>(0h0))
when _T_1331 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1332 = asUInt(reset)
node _T_1333 = eq(_T_1332, UInt<1>(0h0))
when _T_1333 :
node _T_1334 = eq(sink_ok, UInt<1>(0h0))
when _T_1334 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1335 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1336 = asUInt(reset)
node _T_1337 = eq(_T_1336, UInt<1>(0h0))
when _T_1337 :
node _T_1338 = eq(_T_1335, UInt<1>(0h0))
when _T_1338 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1335, UInt<1>(0h1), "") : assert_67
node _T_1339 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1340 = asUInt(reset)
node _T_1341 = eq(_T_1340, UInt<1>(0h0))
when _T_1341 :
node _T_1342 = eq(_T_1339, UInt<1>(0h0))
when _T_1342 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1339, UInt<1>(0h1), "") : assert_68
node _T_1343 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1344 = asUInt(reset)
node _T_1345 = eq(_T_1344, UInt<1>(0h0))
when _T_1345 :
node _T_1346 = eq(_T_1343, UInt<1>(0h0))
when _T_1346 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1343, UInt<1>(0h1), "") : assert_69
node _T_1347 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1348 = or(_T_1347, io.in.d.bits.corrupt)
node _T_1349 = asUInt(reset)
node _T_1350 = eq(_T_1349, UInt<1>(0h0))
when _T_1350 :
node _T_1351 = eq(_T_1348, UInt<1>(0h0))
when _T_1351 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1348, UInt<1>(0h1), "") : assert_70
node _T_1352 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1353 = or(UInt<1>(0h1), _T_1352)
node _T_1354 = asUInt(reset)
node _T_1355 = eq(_T_1354, UInt<1>(0h0))
when _T_1355 :
node _T_1356 = eq(_T_1353, UInt<1>(0h0))
when _T_1356 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1353, UInt<1>(0h1), "") : assert_71
node _T_1357 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1357 :
node _T_1358 = asUInt(reset)
node _T_1359 = eq(_T_1358, UInt<1>(0h0))
when _T_1359 :
node _T_1360 = eq(source_ok_1, UInt<1>(0h0))
when _T_1360 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1361 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1362 = asUInt(reset)
node _T_1363 = eq(_T_1362, UInt<1>(0h0))
when _T_1363 :
node _T_1364 = eq(_T_1361, UInt<1>(0h0))
when _T_1364 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1361, UInt<1>(0h1), "") : assert_73
node _T_1365 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1366 = asUInt(reset)
node _T_1367 = eq(_T_1366, UInt<1>(0h0))
when _T_1367 :
node _T_1368 = eq(_T_1365, UInt<1>(0h0))
when _T_1368 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1365, UInt<1>(0h1), "") : assert_74
node _T_1369 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1370 = or(UInt<1>(0h1), _T_1369)
node _T_1371 = asUInt(reset)
node _T_1372 = eq(_T_1371, UInt<1>(0h0))
when _T_1372 :
node _T_1373 = eq(_T_1370, UInt<1>(0h0))
when _T_1373 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1370, UInt<1>(0h1), "") : assert_75
node _T_1374 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1374 :
node _T_1375 = asUInt(reset)
node _T_1376 = eq(_T_1375, UInt<1>(0h0))
when _T_1376 :
node _T_1377 = eq(source_ok_1, UInt<1>(0h0))
when _T_1377 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1378 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1379 = asUInt(reset)
node _T_1380 = eq(_T_1379, UInt<1>(0h0))
when _T_1380 :
node _T_1381 = eq(_T_1378, UInt<1>(0h0))
when _T_1381 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1378, UInt<1>(0h1), "") : assert_77
node _T_1382 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1383 = or(_T_1382, io.in.d.bits.corrupt)
node _T_1384 = asUInt(reset)
node _T_1385 = eq(_T_1384, UInt<1>(0h0))
when _T_1385 :
node _T_1386 = eq(_T_1383, UInt<1>(0h0))
when _T_1386 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1383, UInt<1>(0h1), "") : assert_78
node _T_1387 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1388 = or(UInt<1>(0h1), _T_1387)
node _T_1389 = asUInt(reset)
node _T_1390 = eq(_T_1389, UInt<1>(0h0))
when _T_1390 :
node _T_1391 = eq(_T_1388, UInt<1>(0h0))
when _T_1391 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1388, UInt<1>(0h1), "") : assert_79
node _T_1392 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1392 :
node _T_1393 = asUInt(reset)
node _T_1394 = eq(_T_1393, UInt<1>(0h0))
when _T_1394 :
node _T_1395 = eq(source_ok_1, UInt<1>(0h0))
when _T_1395 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1396 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1397 = asUInt(reset)
node _T_1398 = eq(_T_1397, UInt<1>(0h0))
when _T_1398 :
node _T_1399 = eq(_T_1396, UInt<1>(0h0))
when _T_1399 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1396, UInt<1>(0h1), "") : assert_81
node _T_1400 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1401 = asUInt(reset)
node _T_1402 = eq(_T_1401, UInt<1>(0h0))
when _T_1402 :
node _T_1403 = eq(_T_1400, UInt<1>(0h0))
when _T_1403 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1400, UInt<1>(0h1), "") : assert_82
node _T_1404 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1405 = or(UInt<1>(0h1), _T_1404)
node _T_1406 = asUInt(reset)
node _T_1407 = eq(_T_1406, UInt<1>(0h0))
when _T_1407 :
node _T_1408 = eq(_T_1405, UInt<1>(0h0))
when _T_1408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1405, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<7>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_1409 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_1410 = asUInt(reset)
node _T_1411 = eq(_T_1410, UInt<1>(0h0))
when _T_1411 :
node _T_1412 = eq(_T_1409, UInt<1>(0h0))
when _T_1412 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1409, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<7>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_1413 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_1414 = asUInt(reset)
node _T_1415 = eq(_T_1414, UInt<1>(0h0))
when _T_1415 :
node _T_1416 = eq(_T_1413, UInt<1>(0h0))
when _T_1416 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1413, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1417 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1418 = asUInt(reset)
node _T_1419 = eq(_T_1418, UInt<1>(0h0))
when _T_1419 :
node _T_1420 = eq(_T_1417, UInt<1>(0h0))
when _T_1420 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1417, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1421 = eq(a_first, UInt<1>(0h0))
node _T_1422 = and(io.in.a.valid, _T_1421)
when _T_1422 :
node _T_1423 = eq(io.in.a.bits.opcode, opcode)
node _T_1424 = asUInt(reset)
node _T_1425 = eq(_T_1424, UInt<1>(0h0))
when _T_1425 :
node _T_1426 = eq(_T_1423, UInt<1>(0h0))
when _T_1426 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1423, UInt<1>(0h1), "") : assert_87
node _T_1427 = eq(io.in.a.bits.param, param)
node _T_1428 = asUInt(reset)
node _T_1429 = eq(_T_1428, UInt<1>(0h0))
when _T_1429 :
node _T_1430 = eq(_T_1427, UInt<1>(0h0))
when _T_1430 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1427, UInt<1>(0h1), "") : assert_88
node _T_1431 = eq(io.in.a.bits.size, size)
node _T_1432 = asUInt(reset)
node _T_1433 = eq(_T_1432, UInt<1>(0h0))
when _T_1433 :
node _T_1434 = eq(_T_1431, UInt<1>(0h0))
when _T_1434 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1431, UInt<1>(0h1), "") : assert_89
node _T_1435 = eq(io.in.a.bits.source, source)
node _T_1436 = asUInt(reset)
node _T_1437 = eq(_T_1436, UInt<1>(0h0))
when _T_1437 :
node _T_1438 = eq(_T_1435, UInt<1>(0h0))
when _T_1438 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1435, UInt<1>(0h1), "") : assert_90
node _T_1439 = eq(io.in.a.bits.address, address)
node _T_1440 = asUInt(reset)
node _T_1441 = eq(_T_1440, UInt<1>(0h0))
when _T_1441 :
node _T_1442 = eq(_T_1439, UInt<1>(0h0))
when _T_1442 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1439, UInt<1>(0h1), "") : assert_91
node _T_1443 = and(io.in.a.ready, io.in.a.valid)
node _T_1444 = and(_T_1443, a_first)
when _T_1444 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1445 = eq(d_first, UInt<1>(0h0))
node _T_1446 = and(io.in.d.valid, _T_1445)
when _T_1446 :
node _T_1447 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1448 = asUInt(reset)
node _T_1449 = eq(_T_1448, UInt<1>(0h0))
when _T_1449 :
node _T_1450 = eq(_T_1447, UInt<1>(0h0))
when _T_1450 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1447, UInt<1>(0h1), "") : assert_92
node _T_1451 = eq(io.in.d.bits.param, param_1)
node _T_1452 = asUInt(reset)
node _T_1453 = eq(_T_1452, UInt<1>(0h0))
when _T_1453 :
node _T_1454 = eq(_T_1451, UInt<1>(0h0))
when _T_1454 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1451, UInt<1>(0h1), "") : assert_93
node _T_1455 = eq(io.in.d.bits.size, size_1)
node _T_1456 = asUInt(reset)
node _T_1457 = eq(_T_1456, UInt<1>(0h0))
when _T_1457 :
node _T_1458 = eq(_T_1455, UInt<1>(0h0))
when _T_1458 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1455, UInt<1>(0h1), "") : assert_94
node _T_1459 = eq(io.in.d.bits.source, source_1)
node _T_1460 = asUInt(reset)
node _T_1461 = eq(_T_1460, UInt<1>(0h0))
when _T_1461 :
node _T_1462 = eq(_T_1459, UInt<1>(0h0))
when _T_1462 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1459, UInt<1>(0h1), "") : assert_95
node _T_1463 = eq(io.in.d.bits.sink, sink)
node _T_1464 = asUInt(reset)
node _T_1465 = eq(_T_1464, UInt<1>(0h0))
when _T_1465 :
node _T_1466 = eq(_T_1463, UInt<1>(0h0))
when _T_1466 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1463, UInt<1>(0h1), "") : assert_96
node _T_1467 = eq(io.in.d.bits.denied, denied)
node _T_1468 = asUInt(reset)
node _T_1469 = eq(_T_1468, UInt<1>(0h0))
when _T_1469 :
node _T_1470 = eq(_T_1467, UInt<1>(0h0))
when _T_1470 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1467, UInt<1>(0h1), "") : assert_97
node _T_1471 = and(io.in.d.ready, io.in.d.valid)
node _T_1472 = and(_T_1471, d_first)
when _T_1472 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<66>, clock, reset, UInt<66>(0h0)
regreset inflight_opcodes : UInt<264>, clock, reset, UInt<264>(0h0)
regreset inflight_sizes : UInt<528>, clock, reset, UInt<528>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<66>
connect a_set, UInt<66>(0h0)
wire a_set_wo_ready : UInt<66>
connect a_set_wo_ready, UInt<66>(0h0)
wire a_opcodes_set : UInt<264>
connect a_opcodes_set, UInt<264>(0h0)
wire a_sizes_set : UInt<528>
connect a_sizes_set, UInt<528>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<8>
connect a_size_lookup, UInt<8>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<5>
connect a_sizes_set_interm, UInt<5>(0h0)
node _T_1473 = and(io.in.a.valid, a_first_1)
node _T_1474 = and(_T_1473, UInt<1>(0h1))
when _T_1474 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1475 = and(io.in.a.ready, io.in.a.valid)
node _T_1476 = and(_T_1475, a_first_1)
node _T_1477 = and(_T_1476, UInt<1>(0h1))
when _T_1477 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1478 = dshr(inflight, io.in.a.bits.source)
node _T_1479 = bits(_T_1478, 0, 0)
node _T_1480 = eq(_T_1479, UInt<1>(0h0))
node _T_1481 = asUInt(reset)
node _T_1482 = eq(_T_1481, UInt<1>(0h0))
when _T_1482 :
node _T_1483 = eq(_T_1480, UInt<1>(0h0))
when _T_1483 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1480, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<66>
connect d_clr, UInt<66>(0h0)
wire d_clr_wo_ready : UInt<66>
connect d_clr_wo_ready, UInt<66>(0h0)
wire d_opcodes_clr : UInt<264>
connect d_opcodes_clr, UInt<264>(0h0)
wire d_sizes_clr : UInt<528>
connect d_sizes_clr, UInt<528>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1484 = and(io.in.d.valid, d_first_1)
node _T_1485 = and(_T_1484, UInt<1>(0h1))
node _T_1486 = eq(d_release_ack, UInt<1>(0h0))
node _T_1487 = and(_T_1485, _T_1486)
when _T_1487 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1488 = and(io.in.d.ready, io.in.d.valid)
node _T_1489 = and(_T_1488, d_first_1)
node _T_1490 = and(_T_1489, UInt<1>(0h1))
node _T_1491 = eq(d_release_ack, UInt<1>(0h0))
node _T_1492 = and(_T_1490, _T_1491)
when _T_1492 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1493 = and(io.in.d.valid, d_first_1)
node _T_1494 = and(_T_1493, UInt<1>(0h1))
node _T_1495 = eq(d_release_ack, UInt<1>(0h0))
node _T_1496 = and(_T_1494, _T_1495)
when _T_1496 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1497 = dshr(inflight, io.in.d.bits.source)
node _T_1498 = bits(_T_1497, 0, 0)
node _T_1499 = or(_T_1498, same_cycle_resp)
node _T_1500 = asUInt(reset)
node _T_1501 = eq(_T_1500, UInt<1>(0h0))
when _T_1501 :
node _T_1502 = eq(_T_1499, UInt<1>(0h0))
when _T_1502 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1499, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1503 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1504 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1505 = or(_T_1503, _T_1504)
node _T_1506 = asUInt(reset)
node _T_1507 = eq(_T_1506, UInt<1>(0h0))
when _T_1507 :
node _T_1508 = eq(_T_1505, UInt<1>(0h0))
when _T_1508 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1505, UInt<1>(0h1), "") : assert_100
node _T_1509 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1510 = asUInt(reset)
node _T_1511 = eq(_T_1510, UInt<1>(0h0))
when _T_1511 :
node _T_1512 = eq(_T_1509, UInt<1>(0h0))
when _T_1512 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1509, UInt<1>(0h1), "") : assert_101
else :
node _T_1513 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1514 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1515 = or(_T_1513, _T_1514)
node _T_1516 = asUInt(reset)
node _T_1517 = eq(_T_1516, UInt<1>(0h0))
when _T_1517 :
node _T_1518 = eq(_T_1515, UInt<1>(0h0))
when _T_1518 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1515, UInt<1>(0h1), "") : assert_102
node _T_1519 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1520 = asUInt(reset)
node _T_1521 = eq(_T_1520, UInt<1>(0h0))
when _T_1521 :
node _T_1522 = eq(_T_1519, UInt<1>(0h0))
when _T_1522 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1519, UInt<1>(0h1), "") : assert_103
node _T_1523 = and(io.in.d.valid, d_first_1)
node _T_1524 = and(_T_1523, a_first_1)
node _T_1525 = and(_T_1524, io.in.a.valid)
node _T_1526 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1527 = and(_T_1525, _T_1526)
node _T_1528 = eq(d_release_ack, UInt<1>(0h0))
node _T_1529 = and(_T_1527, _T_1528)
when _T_1529 :
node _T_1530 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1531 = or(_T_1530, io.in.a.ready)
node _T_1532 = asUInt(reset)
node _T_1533 = eq(_T_1532, UInt<1>(0h0))
when _T_1533 :
node _T_1534 = eq(_T_1531, UInt<1>(0h0))
when _T_1534 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1531, UInt<1>(0h1), "") : assert_104
node _T_1535 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_1536 = orr(a_set_wo_ready)
node _T_1537 = eq(_T_1536, UInt<1>(0h0))
node _T_1538 = or(_T_1535, _T_1537)
node _T_1539 = asUInt(reset)
node _T_1540 = eq(_T_1539, UInt<1>(0h0))
when _T_1540 :
node _T_1541 = eq(_T_1538, UInt<1>(0h0))
when _T_1541 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_1538, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_44
node _T_1542 = orr(inflight)
node _T_1543 = eq(_T_1542, UInt<1>(0h0))
node _T_1544 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1545 = or(_T_1543, _T_1544)
node _T_1546 = lt(watchdog, plusarg_reader.out)
node _T_1547 = or(_T_1545, _T_1546)
node _T_1548 = asUInt(reset)
node _T_1549 = eq(_T_1548, UInt<1>(0h0))
when _T_1549 :
node _T_1550 = eq(_T_1547, UInt<1>(0h0))
when _T_1550 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1547, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1551 = and(io.in.a.ready, io.in.a.valid)
node _T_1552 = and(io.in.d.ready, io.in.d.valid)
node _T_1553 = or(_T_1551, _T_1552)
when _T_1553 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<66>, clock, reset, UInt<66>(0h0)
regreset inflight_opcodes_1 : UInt<264>, clock, reset, UInt<264>(0h0)
regreset inflight_sizes_1 : UInt<528>, clock, reset, UInt<528>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<32>(0h0)
connect _c_first_WIRE.bits.source, UInt<7>(0h0)
connect _c_first_WIRE.bits.size, UInt<4>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<66>
connect c_set, UInt<66>(0h0)
wire c_set_wo_ready : UInt<66>
connect c_set_wo_ready, UInt<66>(0h0)
wire c_opcodes_set : UInt<264>
connect c_opcodes_set, UInt<264>(0h0)
wire c_sizes_set : UInt<528>
connect c_sizes_set, UInt<528>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<8>
connect c_size_lookup, UInt<8>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<5>
connect c_sizes_set_interm, UInt<5>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<7>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1554 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<7>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1555 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_1556 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_1557 = and(_T_1555, _T_1556)
node _T_1558 = and(_T_1554, _T_1557)
when _T_1558 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<32>(0h0)
connect _WIRE_10.bits.source, UInt<7>(0h0)
connect _WIRE_10.bits.size, UInt<4>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1559 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_1560 = and(_T_1559, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<32>(0h0)
connect _WIRE_12.bits.source, UInt<7>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1561 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1562 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1563 = and(_T_1561, _T_1562)
node _T_1564 = and(_T_1560, _T_1563)
when _T_1564 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<32>(0h0)
connect _WIRE_14.bits.source, UInt<7>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1565 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_1566 = bits(_T_1565, 0, 0)
node _T_1567 = eq(_T_1566, UInt<1>(0h0))
node _T_1568 = asUInt(reset)
node _T_1569 = eq(_T_1568, UInt<1>(0h0))
when _T_1569 :
node _T_1570 = eq(_T_1567, UInt<1>(0h0))
when _T_1570 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_1567, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<66>
connect d_clr_1, UInt<66>(0h0)
wire d_clr_wo_ready_1 : UInt<66>
connect d_clr_wo_ready_1, UInt<66>(0h0)
wire d_opcodes_clr_1 : UInt<264>
connect d_opcodes_clr_1, UInt<264>(0h0)
wire d_sizes_clr_1 : UInt<528>
connect d_sizes_clr_1, UInt<528>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1571 = and(io.in.d.valid, d_first_2)
node _T_1572 = and(_T_1571, UInt<1>(0h1))
node _T_1573 = and(_T_1572, d_release_ack_1)
when _T_1573 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1574 = and(io.in.d.ready, io.in.d.valid)
node _T_1575 = and(_T_1574, d_first_2)
node _T_1576 = and(_T_1575, UInt<1>(0h1))
node _T_1577 = and(_T_1576, d_release_ack_1)
when _T_1577 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1578 = and(io.in.d.valid, d_first_2)
node _T_1579 = and(_T_1578, UInt<1>(0h1))
node _T_1580 = and(_T_1579, d_release_ack_1)
when _T_1580 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1581 = dshr(inflight_1, io.in.d.bits.source)
node _T_1582 = bits(_T_1581, 0, 0)
node _T_1583 = or(_T_1582, same_cycle_resp_1)
node _T_1584 = asUInt(reset)
node _T_1585 = eq(_T_1584, UInt<1>(0h0))
when _T_1585 :
node _T_1586 = eq(_T_1583, UInt<1>(0h0))
when _T_1586 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1583, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<32>(0h0)
connect _WIRE_16.bits.source, UInt<7>(0h0)
connect _WIRE_16.bits.size, UInt<4>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1587 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_1588 = asUInt(reset)
node _T_1589 = eq(_T_1588, UInt<1>(0h0))
when _T_1589 :
node _T_1590 = eq(_T_1587, UInt<1>(0h0))
when _T_1590 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1587, UInt<1>(0h1), "") : assert_109
else :
node _T_1591 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1592 = asUInt(reset)
node _T_1593 = eq(_T_1592, UInt<1>(0h0))
when _T_1593 :
node _T_1594 = eq(_T_1591, UInt<1>(0h0))
when _T_1594 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1591, UInt<1>(0h1), "") : assert_110
node _T_1595 = and(io.in.d.valid, d_first_2)
node _T_1596 = and(_T_1595, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<32>(0h0)
connect _WIRE_18.bits.source, UInt<7>(0h0)
connect _WIRE_18.bits.size, UInt<4>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1597 = and(_T_1596, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<32>(0h0)
connect _WIRE_20.bits.source, UInt<7>(0h0)
connect _WIRE_20.bits.size, UInt<4>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1598 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_1599 = and(_T_1597, _T_1598)
node _T_1600 = and(_T_1599, d_release_ack_1)
node _T_1601 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1602 = and(_T_1600, _T_1601)
when _T_1602 :
node _T_1603 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<32>(0h0)
connect _WIRE_22.bits.source, UInt<7>(0h0)
connect _WIRE_22.bits.size, UInt<4>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1604 = or(_T_1603, _WIRE_23.ready)
node _T_1605 = asUInt(reset)
node _T_1606 = eq(_T_1605, UInt<1>(0h0))
when _T_1606 :
node _T_1607 = eq(_T_1604, UInt<1>(0h0))
when _T_1607 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_1604, UInt<1>(0h1), "") : assert_111
node _T_1608 = orr(c_set_wo_ready)
when _T_1608 :
node _T_1609 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_1610 = asUInt(reset)
node _T_1611 = eq(_T_1610, UInt<1>(0h0))
when _T_1611 :
node _T_1612 = eq(_T_1609, UInt<1>(0h0))
when _T_1612 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_1609, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_45
node _T_1613 = orr(inflight_1)
node _T_1614 = eq(_T_1613, UInt<1>(0h0))
node _T_1615 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1616 = or(_T_1614, _T_1615)
node _T_1617 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1618 = or(_T_1616, _T_1617)
node _T_1619 = asUInt(reset)
node _T_1620 = eq(_T_1619, UInt<1>(0h0))
when _T_1620 :
node _T_1621 = eq(_T_1618, UInt<1>(0h0))
when _T_1621 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:34:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_1618, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<32>(0h0)
connect _WIRE_24.bits.source, UInt<7>(0h0)
connect _WIRE_24.bits.size, UInt<4>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1622 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_1623 = and(io.in.d.ready, io.in.d.valid)
node _T_1624 = or(_T_1622, _T_1623)
when _T_1624 :
connect watchdog_1, UInt<1>(0h0)
extmodule plusarg_reader_46 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_47 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLMonitor_22( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27]
wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_49 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_61 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_63 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_67 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_69 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_73 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_75 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_79 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:57:20]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28]
wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [1027:0] _c_sizes_set_T_1 = 1028'h0; // @[Monitor.scala:768:52]
wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79]
wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77]
wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35]
wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35]
wire [527:0] c_sizes_set = 528'h0; // @[Monitor.scala:741:34]
wire [263:0] c_opcodes_set = 264'h0; // @[Monitor.scala:740:34]
wire [65:0] c_set = 66'h0; // @[Monitor.scala:738:34]
wire [65:0] c_set_wo_ready = 66'h0; // @[Monitor.scala:739:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _source_ok_T_1 = io_in_a_bits_source_0[6:3]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_7 = io_in_a_bits_source_0[6:3]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 4'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 4'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_25 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_31 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_14 = _source_ok_T_13 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_26 = _source_ok_T_25 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_32 = _source_ok_T_31 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_6 = _source_ok_T_36; // @[Parameters.scala:1138:31]
wire _source_ok_T_37 = io_in_a_bits_source_0 == 7'h41; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_7 = _source_ok_T_37; // @[Parameters.scala:1138:31]
wire _source_ok_T_38 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_8 = _source_ok_T_38; // @[Parameters.scala:1138:31]
wire _source_ok_T_39 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_40 = _source_ok_T_39 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_41 = _source_ok_T_40 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_42 = _source_ok_T_41 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_43 = _source_ok_T_42 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_44 = _source_ok_T_43 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_45 = _source_ok_T_44 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_45 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [2:0] uncommonBits = _uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_1 = _uncommonBits_T_1[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_6 = _uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_7 = _uncommonBits_T_7[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_12 = _uncommonBits_T_12[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_13 = _uncommonBits_T_13[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_18 = _uncommonBits_T_18[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_19 = _uncommonBits_T_19[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_24 = _uncommonBits_T_24[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_25 = _uncommonBits_T_25[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_30 = _uncommonBits_T_30[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_31 = _uncommonBits_T_31[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_36 = _uncommonBits_T_36[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_37 = _uncommonBits_T_37[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_42 = _uncommonBits_T_42[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_43 = _uncommonBits_T_43[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_48 = _uncommonBits_T_48[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_49 = _uncommonBits_T_49[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_53 = _uncommonBits_T_53[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_46 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_46; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _source_ok_T_47 = io_in_d_bits_source_0[6:3]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_53 = io_in_d_bits_source_0[6:3]; // @[Monitor.scala:36:7]
wire _source_ok_T_48 = _source_ok_T_47 == 4'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_50 = _source_ok_T_48; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_52; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_54 = _source_ok_T_53 == 4'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_58; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_59 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_65 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_71 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_77 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_60 = _source_ok_T_59 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_62 = _source_ok_T_60; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_64 = _source_ok_T_62; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_64; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_66 = _source_ok_T_65 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_68 = _source_ok_T_66; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_70 = _source_ok_T_68; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_70; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_72 = _source_ok_T_71 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_74 = _source_ok_T_72; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_76 = _source_ok_T_74; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_5 = _source_ok_T_76; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_78 = _source_ok_T_77 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_80 = _source_ok_T_78; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_6 = _source_ok_T_82; // @[Parameters.scala:1138:31]
wire _source_ok_T_83 = io_in_d_bits_source_0 == 7'h41; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_7 = _source_ok_T_83; // @[Parameters.scala:1138:31]
wire _source_ok_T_84 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_8 = _source_ok_T_84; // @[Parameters.scala:1138:31]
wire _source_ok_T_85 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_86 = _source_ok_T_85 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_87 = _source_ok_T_86 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_88 = _source_ok_T_87 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_89 = _source_ok_T_88 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_90 = _source_ok_T_89 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_91 = _source_ok_T_90 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_91 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1551 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1551; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1551; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [6:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_1624 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1624; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1624; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1624; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [6:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [65:0] inflight; // @[Monitor.scala:614:27]
reg [263:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [527:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [65:0] a_set; // @[Monitor.scala:626:34]
wire [65:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [263:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [527:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [263:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [263:0] _a_opcode_lookup_T_6 = {260'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [263:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[263:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [9:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [527:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [527:0] _a_size_lookup_T_6 = {520'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}]
wire [527:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[527:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [127:0] _GEN_3 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35]
wire [127:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[65:0] : 66'h0; // @[OneHot.scala:58:35]
wire _T_1477 = _T_1551 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1477 ? _a_set_T[65:0] : 66'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1477 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1477 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [9:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1477 ? _a_opcodes_set_T_1[263:0] : 264'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [9:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [1027:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1477 ? _a_sizes_set_T_1[527:0] : 528'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [65:0] d_clr; // @[Monitor.scala:664:34]
wire [65:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [263:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [527:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1523 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1523 & ~d_release_ack ? _d_clr_wo_ready_T[65:0] : 66'h0; // @[OneHot.scala:58:35]
wire _T_1492 = _T_1624 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1492 ? _d_clr_T[65:0] : 66'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1492 ? _d_opcodes_clr_T_5[263:0] : 264'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [1038:0] _d_sizes_clr_T_5 = 1039'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1492 ? _d_sizes_clr_T_5[527:0] : 528'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [65:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [65:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [65:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [263:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [263:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [263:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [527:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [527:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [527:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [65:0] inflight_1; // @[Monitor.scala:726:35]
wire [65:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [263:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [263:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [527:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [527:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [263:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [263:0] _c_opcode_lookup_T_6 = {260'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [263:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[263:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [527:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [527:0] _c_size_lookup_T_6 = {520'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}]
wire [527:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[527:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [65:0] d_clr_1; // @[Monitor.scala:774:34]
wire [65:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [263:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [527:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1595 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1595 & d_release_ack_1 ? _d_clr_wo_ready_T_1[65:0] : 66'h0; // @[OneHot.scala:58:35]
wire _T_1577 = _T_1624 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1577 ? _d_clr_T_1[65:0] : 66'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1577 ? _d_opcodes_clr_T_11[263:0] : 264'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [1038:0] _d_sizes_clr_T_11 = 1039'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1577 ? _d_sizes_clr_T_11[527:0] : 528'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113]
wire [65:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [65:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [263:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [263:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [527:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [527:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_41 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<6>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 5, 0)
node _source_ok_T = shr(io.in.a.bits.source, 6)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<6>(0h39))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T_5
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits = bits(_uncommonBits_T, 5, 0)
node _T_4 = shr(io.in.a.bits.source, 6)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<6>(0h39))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_16, UInt<1>(0h1), "") : assert_1
node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_20 :
node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_23 = and(_T_21, _T_22)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 5, 0)
node _T_24 = shr(io.in.a.bits.source, 6)
node _T_25 = eq(_T_24, UInt<1>(0h0))
node _T_26 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_27 = and(_T_25, _T_26)
node _T_28 = leq(uncommonBits_1, UInt<6>(0h39))
node _T_29 = and(_T_27, _T_28)
node _T_30 = and(_T_23, _T_29)
node _T_31 = or(UInt<1>(0h0), _T_30)
node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_33 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_34 = cvt(_T_33)
node _T_35 = and(_T_34, asSInt(UInt<29>(0h10000000)))
node _T_36 = asSInt(_T_35)
node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0)))
node _T_38 = and(_T_32, _T_37)
node _T_39 = or(UInt<1>(0h0), _T_38)
node _T_40 = and(_T_31, _T_39)
node _T_41 = asUInt(reset)
node _T_42 = eq(_T_41, UInt<1>(0h0))
when _T_42 :
node _T_43 = eq(_T_40, UInt<1>(0h0))
when _T_43 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_40, UInt<1>(0h1), "") : assert_2
node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_46 = and(_T_44, _T_45)
node _T_47 = or(UInt<1>(0h0), _T_46)
node _T_48 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_49 = cvt(_T_48)
node _T_50 = and(_T_49, asSInt(UInt<29>(0h10000000)))
node _T_51 = asSInt(_T_50)
node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0)))
node _T_53 = and(_T_47, _T_52)
node _T_54 = or(UInt<1>(0h0), _T_53)
node _T_55 = and(UInt<1>(0h0), _T_54)
node _T_56 = asUInt(reset)
node _T_57 = eq(_T_56, UInt<1>(0h0))
when _T_57 :
node _T_58 = eq(_T_55, UInt<1>(0h0))
when _T_58 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_55, UInt<1>(0h1), "") : assert_3
node _T_59 = asUInt(reset)
node _T_60 = eq(_T_59, UInt<1>(0h0))
when _T_60 :
node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_61 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_63 = asUInt(reset)
node _T_64 = eq(_T_63, UInt<1>(0h0))
when _T_64 :
node _T_65 = eq(_T_62, UInt<1>(0h0))
when _T_65 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_62, UInt<1>(0h1), "") : assert_5
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(is_aligned, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_70 = asUInt(reset)
node _T_71 = eq(_T_70, UInt<1>(0h0))
when _T_71 :
node _T_72 = eq(_T_69, UInt<1>(0h0))
when _T_72 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_69, UInt<1>(0h1), "") : assert_7
node _T_73 = not(io.in.a.bits.mask)
node _T_74 = eq(_T_73, UInt<1>(0h0))
node _T_75 = asUInt(reset)
node _T_76 = eq(_T_75, UInt<1>(0h0))
when _T_76 :
node _T_77 = eq(_T_74, UInt<1>(0h0))
when _T_77 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_74, UInt<1>(0h1), "") : assert_8
node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_79 = asUInt(reset)
node _T_80 = eq(_T_79, UInt<1>(0h0))
when _T_80 :
node _T_81 = eq(_T_78, UInt<1>(0h0))
when _T_81 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_78, UInt<1>(0h1), "") : assert_9
node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_82 :
node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_85 = and(_T_83, _T_84)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 5, 0)
node _T_86 = shr(io.in.a.bits.source, 6)
node _T_87 = eq(_T_86, UInt<1>(0h0))
node _T_88 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_89 = and(_T_87, _T_88)
node _T_90 = leq(uncommonBits_2, UInt<6>(0h39))
node _T_91 = and(_T_89, _T_90)
node _T_92 = and(_T_85, _T_91)
node _T_93 = or(UInt<1>(0h0), _T_92)
node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_95 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_96 = cvt(_T_95)
node _T_97 = and(_T_96, asSInt(UInt<29>(0h10000000)))
node _T_98 = asSInt(_T_97)
node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = and(_T_94, _T_99)
node _T_101 = or(UInt<1>(0h0), _T_100)
node _T_102 = and(_T_93, _T_101)
node _T_103 = asUInt(reset)
node _T_104 = eq(_T_103, UInt<1>(0h0))
when _T_104 :
node _T_105 = eq(_T_102, UInt<1>(0h0))
when _T_105 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_102, UInt<1>(0h1), "") : assert_10
node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_108 = and(_T_106, _T_107)
node _T_109 = or(UInt<1>(0h0), _T_108)
node _T_110 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_111 = cvt(_T_110)
node _T_112 = and(_T_111, asSInt(UInt<29>(0h10000000)))
node _T_113 = asSInt(_T_112)
node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0)))
node _T_115 = and(_T_109, _T_114)
node _T_116 = or(UInt<1>(0h0), _T_115)
node _T_117 = and(UInt<1>(0h0), _T_116)
node _T_118 = asUInt(reset)
node _T_119 = eq(_T_118, UInt<1>(0h0))
when _T_119 :
node _T_120 = eq(_T_117, UInt<1>(0h0))
when _T_120 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_117, UInt<1>(0h1), "") : assert_11
node _T_121 = asUInt(reset)
node _T_122 = eq(_T_121, UInt<1>(0h0))
when _T_122 :
node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_125 = asUInt(reset)
node _T_126 = eq(_T_125, UInt<1>(0h0))
when _T_126 :
node _T_127 = eq(_T_124, UInt<1>(0h0))
when _T_127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_124, UInt<1>(0h1), "") : assert_13
node _T_128 = asUInt(reset)
node _T_129 = eq(_T_128, UInt<1>(0h0))
when _T_129 :
node _T_130 = eq(is_aligned, UInt<1>(0h0))
when _T_130 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_132 = asUInt(reset)
node _T_133 = eq(_T_132, UInt<1>(0h0))
when _T_133 :
node _T_134 = eq(_T_131, UInt<1>(0h0))
when _T_134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_131, UInt<1>(0h1), "") : assert_15
node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_136 = asUInt(reset)
node _T_137 = eq(_T_136, UInt<1>(0h0))
when _T_137 :
node _T_138 = eq(_T_135, UInt<1>(0h0))
when _T_138 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_135, UInt<1>(0h1), "") : assert_16
node _T_139 = not(io.in.a.bits.mask)
node _T_140 = eq(_T_139, UInt<1>(0h0))
node _T_141 = asUInt(reset)
node _T_142 = eq(_T_141, UInt<1>(0h0))
when _T_142 :
node _T_143 = eq(_T_140, UInt<1>(0h0))
when _T_143 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_140, UInt<1>(0h1), "") : assert_17
node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_145 = asUInt(reset)
node _T_146 = eq(_T_145, UInt<1>(0h0))
when _T_146 :
node _T_147 = eq(_T_144, UInt<1>(0h0))
when _T_147 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_144, UInt<1>(0h1), "") : assert_18
node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_148 :
node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_151 = and(_T_149, _T_150)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 5, 0)
node _T_152 = shr(io.in.a.bits.source, 6)
node _T_153 = eq(_T_152, UInt<1>(0h0))
node _T_154 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_155 = and(_T_153, _T_154)
node _T_156 = leq(uncommonBits_3, UInt<6>(0h39))
node _T_157 = and(_T_155, _T_156)
node _T_158 = and(_T_151, _T_157)
node _T_159 = or(UInt<1>(0h0), _T_158)
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(_T_159, UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_159, UInt<1>(0h1), "") : assert_19
node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_164 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_165 = and(_T_163, _T_164)
node _T_166 = or(UInt<1>(0h0), _T_165)
node _T_167 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_168 = cvt(_T_167)
node _T_169 = and(_T_168, asSInt(UInt<29>(0h10000000)))
node _T_170 = asSInt(_T_169)
node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0)))
node _T_172 = and(_T_166, _T_171)
node _T_173 = or(UInt<1>(0h0), _T_172)
node _T_174 = asUInt(reset)
node _T_175 = eq(_T_174, UInt<1>(0h0))
when _T_175 :
node _T_176 = eq(_T_173, UInt<1>(0h0))
when _T_176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_173, UInt<1>(0h1), "") : assert_20
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_180 = asUInt(reset)
node _T_181 = eq(_T_180, UInt<1>(0h0))
when _T_181 :
node _T_182 = eq(is_aligned, UInt<1>(0h0))
when _T_182 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_183, UInt<1>(0h1), "") : assert_23
node _T_187 = eq(io.in.a.bits.mask, mask)
node _T_188 = asUInt(reset)
node _T_189 = eq(_T_188, UInt<1>(0h0))
when _T_189 :
node _T_190 = eq(_T_187, UInt<1>(0h0))
when _T_190 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_187, UInt<1>(0h1), "") : assert_24
node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_192 = asUInt(reset)
node _T_193 = eq(_T_192, UInt<1>(0h0))
when _T_193 :
node _T_194 = eq(_T_191, UInt<1>(0h0))
when _T_194 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_191, UInt<1>(0h1), "") : assert_25
node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_195 :
node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_198 = and(_T_196, _T_197)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 5, 0)
node _T_199 = shr(io.in.a.bits.source, 6)
node _T_200 = eq(_T_199, UInt<1>(0h0))
node _T_201 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_202 = and(_T_200, _T_201)
node _T_203 = leq(uncommonBits_4, UInt<6>(0h39))
node _T_204 = and(_T_202, _T_203)
node _T_205 = and(_T_198, _T_204)
node _T_206 = or(UInt<1>(0h0), _T_205)
node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_208 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_209 = and(_T_207, _T_208)
node _T_210 = or(UInt<1>(0h0), _T_209)
node _T_211 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_212 = cvt(_T_211)
node _T_213 = and(_T_212, asSInt(UInt<29>(0h10000000)))
node _T_214 = asSInt(_T_213)
node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0)))
node _T_216 = and(_T_210, _T_215)
node _T_217 = or(UInt<1>(0h0), _T_216)
node _T_218 = and(_T_206, _T_217)
node _T_219 = asUInt(reset)
node _T_220 = eq(_T_219, UInt<1>(0h0))
when _T_220 :
node _T_221 = eq(_T_218, UInt<1>(0h0))
when _T_221 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_218, UInt<1>(0h1), "") : assert_26
node _T_222 = asUInt(reset)
node _T_223 = eq(_T_222, UInt<1>(0h0))
when _T_223 :
node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_225 = asUInt(reset)
node _T_226 = eq(_T_225, UInt<1>(0h0))
when _T_226 :
node _T_227 = eq(is_aligned, UInt<1>(0h0))
when _T_227 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_229 = asUInt(reset)
node _T_230 = eq(_T_229, UInt<1>(0h0))
when _T_230 :
node _T_231 = eq(_T_228, UInt<1>(0h0))
when _T_231 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_228, UInt<1>(0h1), "") : assert_29
node _T_232 = eq(io.in.a.bits.mask, mask)
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_232, UInt<1>(0h1), "") : assert_30
node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_236 :
node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_239 = and(_T_237, _T_238)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 5, 0)
node _T_240 = shr(io.in.a.bits.source, 6)
node _T_241 = eq(_T_240, UInt<1>(0h0))
node _T_242 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_243 = and(_T_241, _T_242)
node _T_244 = leq(uncommonBits_5, UInt<6>(0h39))
node _T_245 = and(_T_243, _T_244)
node _T_246 = and(_T_239, _T_245)
node _T_247 = or(UInt<1>(0h0), _T_246)
node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_249 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_250 = and(_T_248, _T_249)
node _T_251 = or(UInt<1>(0h0), _T_250)
node _T_252 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_253 = cvt(_T_252)
node _T_254 = and(_T_253, asSInt(UInt<29>(0h10000000)))
node _T_255 = asSInt(_T_254)
node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0)))
node _T_257 = and(_T_251, _T_256)
node _T_258 = or(UInt<1>(0h0), _T_257)
node _T_259 = and(_T_247, _T_258)
node _T_260 = asUInt(reset)
node _T_261 = eq(_T_260, UInt<1>(0h0))
when _T_261 :
node _T_262 = eq(_T_259, UInt<1>(0h0))
when _T_262 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_259, UInt<1>(0h1), "") : assert_31
node _T_263 = asUInt(reset)
node _T_264 = eq(_T_263, UInt<1>(0h0))
when _T_264 :
node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_265 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_266 = asUInt(reset)
node _T_267 = eq(_T_266, UInt<1>(0h0))
when _T_267 :
node _T_268 = eq(is_aligned, UInt<1>(0h0))
when _T_268 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_270 = asUInt(reset)
node _T_271 = eq(_T_270, UInt<1>(0h0))
when _T_271 :
node _T_272 = eq(_T_269, UInt<1>(0h0))
when _T_272 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_269, UInt<1>(0h1), "") : assert_34
node _T_273 = not(mask)
node _T_274 = and(io.in.a.bits.mask, _T_273)
node _T_275 = eq(_T_274, UInt<1>(0h0))
node _T_276 = asUInt(reset)
node _T_277 = eq(_T_276, UInt<1>(0h0))
when _T_277 :
node _T_278 = eq(_T_275, UInt<1>(0h0))
when _T_278 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_275, UInt<1>(0h1), "") : assert_35
node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_279 :
node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_282 = and(_T_280, _T_281)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 5, 0)
node _T_283 = shr(io.in.a.bits.source, 6)
node _T_284 = eq(_T_283, UInt<1>(0h0))
node _T_285 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_286 = and(_T_284, _T_285)
node _T_287 = leq(uncommonBits_6, UInt<6>(0h39))
node _T_288 = and(_T_286, _T_287)
node _T_289 = and(_T_282, _T_288)
node _T_290 = or(UInt<1>(0h0), _T_289)
node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_292 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_293 = cvt(_T_292)
node _T_294 = and(_T_293, asSInt(UInt<29>(0h10000000)))
node _T_295 = asSInt(_T_294)
node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0)))
node _T_297 = and(_T_291, _T_296)
node _T_298 = or(UInt<1>(0h0), _T_297)
node _T_299 = and(_T_290, _T_298)
node _T_300 = asUInt(reset)
node _T_301 = eq(_T_300, UInt<1>(0h0))
when _T_301 :
node _T_302 = eq(_T_299, UInt<1>(0h0))
when _T_302 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_299, UInt<1>(0h1), "") : assert_36
node _T_303 = asUInt(reset)
node _T_304 = eq(_T_303, UInt<1>(0h0))
when _T_304 :
node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_305 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_306 = asUInt(reset)
node _T_307 = eq(_T_306, UInt<1>(0h0))
when _T_307 :
node _T_308 = eq(is_aligned, UInt<1>(0h0))
when _T_308 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_310 = asUInt(reset)
node _T_311 = eq(_T_310, UInt<1>(0h0))
when _T_311 :
node _T_312 = eq(_T_309, UInt<1>(0h0))
when _T_312 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_309, UInt<1>(0h1), "") : assert_39
node _T_313 = eq(io.in.a.bits.mask, mask)
node _T_314 = asUInt(reset)
node _T_315 = eq(_T_314, UInt<1>(0h0))
when _T_315 :
node _T_316 = eq(_T_313, UInt<1>(0h0))
when _T_316 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_313, UInt<1>(0h1), "") : assert_40
node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_317 :
node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_320 = and(_T_318, _T_319)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 5, 0)
node _T_321 = shr(io.in.a.bits.source, 6)
node _T_322 = eq(_T_321, UInt<1>(0h0))
node _T_323 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_324 = and(_T_322, _T_323)
node _T_325 = leq(uncommonBits_7, UInt<6>(0h39))
node _T_326 = and(_T_324, _T_325)
node _T_327 = and(_T_320, _T_326)
node _T_328 = or(UInt<1>(0h0), _T_327)
node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_330 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_331 = cvt(_T_330)
node _T_332 = and(_T_331, asSInt(UInt<29>(0h10000000)))
node _T_333 = asSInt(_T_332)
node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0)))
node _T_335 = and(_T_329, _T_334)
node _T_336 = or(UInt<1>(0h0), _T_335)
node _T_337 = and(_T_328, _T_336)
node _T_338 = asUInt(reset)
node _T_339 = eq(_T_338, UInt<1>(0h0))
when _T_339 :
node _T_340 = eq(_T_337, UInt<1>(0h0))
when _T_340 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_337, UInt<1>(0h1), "") : assert_41
node _T_341 = asUInt(reset)
node _T_342 = eq(_T_341, UInt<1>(0h0))
when _T_342 :
node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_343 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_344 = asUInt(reset)
node _T_345 = eq(_T_344, UInt<1>(0h0))
when _T_345 :
node _T_346 = eq(is_aligned, UInt<1>(0h0))
when _T_346 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_348 = asUInt(reset)
node _T_349 = eq(_T_348, UInt<1>(0h0))
when _T_349 :
node _T_350 = eq(_T_347, UInt<1>(0h0))
when _T_350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_347, UInt<1>(0h1), "") : assert_44
node _T_351 = eq(io.in.a.bits.mask, mask)
node _T_352 = asUInt(reset)
node _T_353 = eq(_T_352, UInt<1>(0h0))
when _T_353 :
node _T_354 = eq(_T_351, UInt<1>(0h0))
when _T_354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_351, UInt<1>(0h1), "") : assert_45
node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_355 :
node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_358 = and(_T_356, _T_357)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 5, 0)
node _T_359 = shr(io.in.a.bits.source, 6)
node _T_360 = eq(_T_359, UInt<1>(0h0))
node _T_361 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_362 = and(_T_360, _T_361)
node _T_363 = leq(uncommonBits_8, UInt<6>(0h39))
node _T_364 = and(_T_362, _T_363)
node _T_365 = and(_T_358, _T_364)
node _T_366 = or(UInt<1>(0h0), _T_365)
node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_368 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_369 = cvt(_T_368)
node _T_370 = and(_T_369, asSInt(UInt<29>(0h10000000)))
node _T_371 = asSInt(_T_370)
node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0)))
node _T_373 = and(_T_367, _T_372)
node _T_374 = or(UInt<1>(0h0), _T_373)
node _T_375 = and(_T_366, _T_374)
node _T_376 = asUInt(reset)
node _T_377 = eq(_T_376, UInt<1>(0h0))
when _T_377 :
node _T_378 = eq(_T_375, UInt<1>(0h0))
when _T_378 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_375, UInt<1>(0h1), "") : assert_46
node _T_379 = asUInt(reset)
node _T_380 = eq(_T_379, UInt<1>(0h0))
when _T_380 :
node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_381 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_382 = asUInt(reset)
node _T_383 = eq(_T_382, UInt<1>(0h0))
when _T_383 :
node _T_384 = eq(is_aligned, UInt<1>(0h0))
when _T_384 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_386 = asUInt(reset)
node _T_387 = eq(_T_386, UInt<1>(0h0))
when _T_387 :
node _T_388 = eq(_T_385, UInt<1>(0h0))
when _T_388 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_385, UInt<1>(0h1), "") : assert_49
node _T_389 = eq(io.in.a.bits.mask, mask)
node _T_390 = asUInt(reset)
node _T_391 = eq(_T_390, UInt<1>(0h0))
when _T_391 :
node _T_392 = eq(_T_389, UInt<1>(0h0))
when _T_392 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_389, UInt<1>(0h1), "") : assert_50
node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_394 = asUInt(reset)
node _T_395 = eq(_T_394, UInt<1>(0h0))
when _T_395 :
node _T_396 = eq(_T_393, UInt<1>(0h0))
when _T_396 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_393, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(_T_397, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_397, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<6>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 5, 0)
node _source_ok_T_6 = shr(io.in.d.bits.source, 6)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<6>(0h39))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_11
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_401 :
node _T_402 = asUInt(reset)
node _T_403 = eq(_T_402, UInt<1>(0h0))
when _T_403 :
node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_404 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_406 = asUInt(reset)
node _T_407 = eq(_T_406, UInt<1>(0h0))
when _T_407 :
node _T_408 = eq(_T_405, UInt<1>(0h0))
when _T_408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_405, UInt<1>(0h1), "") : assert_54
node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_410 = asUInt(reset)
node _T_411 = eq(_T_410, UInt<1>(0h0))
when _T_411 :
node _T_412 = eq(_T_409, UInt<1>(0h0))
when _T_412 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_409, UInt<1>(0h1), "") : assert_55
node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_414 = asUInt(reset)
node _T_415 = eq(_T_414, UInt<1>(0h0))
when _T_415 :
node _T_416 = eq(_T_413, UInt<1>(0h0))
when _T_416 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_413, UInt<1>(0h1), "") : assert_56
node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_418 = asUInt(reset)
node _T_419 = eq(_T_418, UInt<1>(0h0))
when _T_419 :
node _T_420 = eq(_T_417, UInt<1>(0h0))
when _T_420 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_417, UInt<1>(0h1), "") : assert_57
node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_421 :
node _T_422 = asUInt(reset)
node _T_423 = eq(_T_422, UInt<1>(0h0))
when _T_423 :
node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_424 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_425 = asUInt(reset)
node _T_426 = eq(_T_425, UInt<1>(0h0))
when _T_426 :
node _T_427 = eq(sink_ok, UInt<1>(0h0))
when _T_427 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_429 = asUInt(reset)
node _T_430 = eq(_T_429, UInt<1>(0h0))
when _T_430 :
node _T_431 = eq(_T_428, UInt<1>(0h0))
when _T_431 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_428, UInt<1>(0h1), "") : assert_60
node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_433 = asUInt(reset)
node _T_434 = eq(_T_433, UInt<1>(0h0))
when _T_434 :
node _T_435 = eq(_T_432, UInt<1>(0h0))
when _T_435 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_432, UInt<1>(0h1), "") : assert_61
node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_437 = asUInt(reset)
node _T_438 = eq(_T_437, UInt<1>(0h0))
when _T_438 :
node _T_439 = eq(_T_436, UInt<1>(0h0))
when _T_439 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_436, UInt<1>(0h1), "") : assert_62
node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_441 = asUInt(reset)
node _T_442 = eq(_T_441, UInt<1>(0h0))
when _T_442 :
node _T_443 = eq(_T_440, UInt<1>(0h0))
when _T_443 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_440, UInt<1>(0h1), "") : assert_63
node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_445 = or(UInt<1>(0h1), _T_444)
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_445, UInt<1>(0h1), "") : assert_64
node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_449 :
node _T_450 = asUInt(reset)
node _T_451 = eq(_T_450, UInt<1>(0h0))
when _T_451 :
node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_452 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(sink_ok, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_457 = asUInt(reset)
node _T_458 = eq(_T_457, UInt<1>(0h0))
when _T_458 :
node _T_459 = eq(_T_456, UInt<1>(0h0))
when _T_459 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_456, UInt<1>(0h1), "") : assert_67
node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_461 = asUInt(reset)
node _T_462 = eq(_T_461, UInt<1>(0h0))
when _T_462 :
node _T_463 = eq(_T_460, UInt<1>(0h0))
when _T_463 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_460, UInt<1>(0h1), "") : assert_68
node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_465 = asUInt(reset)
node _T_466 = eq(_T_465, UInt<1>(0h0))
when _T_466 :
node _T_467 = eq(_T_464, UInt<1>(0h0))
when _T_467 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_464, UInt<1>(0h1), "") : assert_69
node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_469 = or(_T_468, io.in.d.bits.corrupt)
node _T_470 = asUInt(reset)
node _T_471 = eq(_T_470, UInt<1>(0h0))
when _T_471 :
node _T_472 = eq(_T_469, UInt<1>(0h0))
when _T_472 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_469, UInt<1>(0h1), "") : assert_70
node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_474 = or(UInt<1>(0h1), _T_473)
node _T_475 = asUInt(reset)
node _T_476 = eq(_T_475, UInt<1>(0h0))
when _T_476 :
node _T_477 = eq(_T_474, UInt<1>(0h0))
when _T_477 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_474, UInt<1>(0h1), "") : assert_71
node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_478 :
node _T_479 = asUInt(reset)
node _T_480 = eq(_T_479, UInt<1>(0h0))
when _T_480 :
node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_481 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_483 = asUInt(reset)
node _T_484 = eq(_T_483, UInt<1>(0h0))
when _T_484 :
node _T_485 = eq(_T_482, UInt<1>(0h0))
when _T_485 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_482, UInt<1>(0h1), "") : assert_73
node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_487 = asUInt(reset)
node _T_488 = eq(_T_487, UInt<1>(0h0))
when _T_488 :
node _T_489 = eq(_T_486, UInt<1>(0h0))
when _T_489 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_486, UInt<1>(0h1), "") : assert_74
node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_491 = or(UInt<1>(0h1), _T_490)
node _T_492 = asUInt(reset)
node _T_493 = eq(_T_492, UInt<1>(0h0))
when _T_493 :
node _T_494 = eq(_T_491, UInt<1>(0h0))
when _T_494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_491, UInt<1>(0h1), "") : assert_75
node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_495 :
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_500 = asUInt(reset)
node _T_501 = eq(_T_500, UInt<1>(0h0))
when _T_501 :
node _T_502 = eq(_T_499, UInt<1>(0h0))
when _T_502 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_499, UInt<1>(0h1), "") : assert_77
node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_504 = or(_T_503, io.in.d.bits.corrupt)
node _T_505 = asUInt(reset)
node _T_506 = eq(_T_505, UInt<1>(0h0))
when _T_506 :
node _T_507 = eq(_T_504, UInt<1>(0h0))
when _T_507 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_504, UInt<1>(0h1), "") : assert_78
node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_509 = or(UInt<1>(0h1), _T_508)
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_T_509, UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_509, UInt<1>(0h1), "") : assert_79
node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_513 :
node _T_514 = asUInt(reset)
node _T_515 = eq(_T_514, UInt<1>(0h0))
when _T_515 :
node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_516 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_518 = asUInt(reset)
node _T_519 = eq(_T_518, UInt<1>(0h0))
when _T_519 :
node _T_520 = eq(_T_517, UInt<1>(0h0))
when _T_520 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_517, UInt<1>(0h1), "") : assert_81
node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_522 = asUInt(reset)
node _T_523 = eq(_T_522, UInt<1>(0h0))
when _T_523 :
node _T_524 = eq(_T_521, UInt<1>(0h0))
when _T_524 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_521, UInt<1>(0h1), "") : assert_82
node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_526 = or(UInt<1>(0h1), _T_525)
node _T_527 = asUInt(reset)
node _T_528 = eq(_T_527, UInt<1>(0h0))
when _T_528 :
node _T_529 = eq(_T_526, UInt<1>(0h0))
when _T_529 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_526, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<6>(0h0)
connect _WIRE.bits.size, UInt<3>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_531 = asUInt(reset)
node _T_532 = eq(_T_531, UInt<1>(0h0))
when _T_532 :
node _T_533 = eq(_T_530, UInt<1>(0h0))
when _T_533 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_530, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<6>(0h0)
connect _WIRE_2.bits.size, UInt<3>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_535 = asUInt(reset)
node _T_536 = eq(_T_535, UInt<1>(0h0))
when _T_536 :
node _T_537 = eq(_T_534, UInt<1>(0h0))
when _T_537 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_534, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_539 = asUInt(reset)
node _T_540 = eq(_T_539, UInt<1>(0h0))
when _T_540 :
node _T_541 = eq(_T_538, UInt<1>(0h0))
when _T_541 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_538, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_542 = eq(a_first, UInt<1>(0h0))
node _T_543 = and(io.in.a.valid, _T_542)
when _T_543 :
node _T_544 = eq(io.in.a.bits.opcode, opcode)
node _T_545 = asUInt(reset)
node _T_546 = eq(_T_545, UInt<1>(0h0))
when _T_546 :
node _T_547 = eq(_T_544, UInt<1>(0h0))
when _T_547 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_544, UInt<1>(0h1), "") : assert_87
node _T_548 = eq(io.in.a.bits.param, param)
node _T_549 = asUInt(reset)
node _T_550 = eq(_T_549, UInt<1>(0h0))
when _T_550 :
node _T_551 = eq(_T_548, UInt<1>(0h0))
when _T_551 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_548, UInt<1>(0h1), "") : assert_88
node _T_552 = eq(io.in.a.bits.size, size)
node _T_553 = asUInt(reset)
node _T_554 = eq(_T_553, UInt<1>(0h0))
when _T_554 :
node _T_555 = eq(_T_552, UInt<1>(0h0))
when _T_555 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_552, UInt<1>(0h1), "") : assert_89
node _T_556 = eq(io.in.a.bits.source, source)
node _T_557 = asUInt(reset)
node _T_558 = eq(_T_557, UInt<1>(0h0))
when _T_558 :
node _T_559 = eq(_T_556, UInt<1>(0h0))
when _T_559 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_556, UInt<1>(0h1), "") : assert_90
node _T_560 = eq(io.in.a.bits.address, address)
node _T_561 = asUInt(reset)
node _T_562 = eq(_T_561, UInt<1>(0h0))
when _T_562 :
node _T_563 = eq(_T_560, UInt<1>(0h0))
when _T_563 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_560, UInt<1>(0h1), "") : assert_91
node _T_564 = and(io.in.a.ready, io.in.a.valid)
node _T_565 = and(_T_564, a_first)
when _T_565 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_566 = eq(d_first, UInt<1>(0h0))
node _T_567 = and(io.in.d.valid, _T_566)
when _T_567 :
node _T_568 = eq(io.in.d.bits.opcode, opcode_1)
node _T_569 = asUInt(reset)
node _T_570 = eq(_T_569, UInt<1>(0h0))
when _T_570 :
node _T_571 = eq(_T_568, UInt<1>(0h0))
when _T_571 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_568, UInt<1>(0h1), "") : assert_92
node _T_572 = eq(io.in.d.bits.param, param_1)
node _T_573 = asUInt(reset)
node _T_574 = eq(_T_573, UInt<1>(0h0))
when _T_574 :
node _T_575 = eq(_T_572, UInt<1>(0h0))
when _T_575 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_572, UInt<1>(0h1), "") : assert_93
node _T_576 = eq(io.in.d.bits.size, size_1)
node _T_577 = asUInt(reset)
node _T_578 = eq(_T_577, UInt<1>(0h0))
when _T_578 :
node _T_579 = eq(_T_576, UInt<1>(0h0))
when _T_579 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_576, UInt<1>(0h1), "") : assert_94
node _T_580 = eq(io.in.d.bits.source, source_1)
node _T_581 = asUInt(reset)
node _T_582 = eq(_T_581, UInt<1>(0h0))
when _T_582 :
node _T_583 = eq(_T_580, UInt<1>(0h0))
when _T_583 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_580, UInt<1>(0h1), "") : assert_95
node _T_584 = eq(io.in.d.bits.sink, sink)
node _T_585 = asUInt(reset)
node _T_586 = eq(_T_585, UInt<1>(0h0))
when _T_586 :
node _T_587 = eq(_T_584, UInt<1>(0h0))
when _T_587 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_584, UInt<1>(0h1), "") : assert_96
node _T_588 = eq(io.in.d.bits.denied, denied)
node _T_589 = asUInt(reset)
node _T_590 = eq(_T_589, UInt<1>(0h0))
when _T_590 :
node _T_591 = eq(_T_588, UInt<1>(0h0))
when _T_591 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_588, UInt<1>(0h1), "") : assert_97
node _T_592 = and(io.in.d.ready, io.in.d.valid)
node _T_593 = and(_T_592, d_first)
when _T_593 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<58>, clock, reset, UInt<58>(0h0)
regreset inflight_opcodes : UInt<232>, clock, reset, UInt<232>(0h0)
regreset inflight_sizes : UInt<232>, clock, reset, UInt<232>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<58>
connect a_set, UInt<58>(0h0)
wire a_set_wo_ready : UInt<58>
connect a_set_wo_ready, UInt<58>(0h0)
wire a_opcodes_set : UInt<232>
connect a_opcodes_set, UInt<232>(0h0)
wire a_sizes_set : UInt<232>
connect a_sizes_set, UInt<232>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_594 = and(io.in.a.valid, a_first_1)
node _T_595 = and(_T_594, UInt<1>(0h1))
when _T_595 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_596 = and(io.in.a.ready, io.in.a.valid)
node _T_597 = and(_T_596, a_first_1)
node _T_598 = and(_T_597, UInt<1>(0h1))
when _T_598 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_599 = dshr(inflight, io.in.a.bits.source)
node _T_600 = bits(_T_599, 0, 0)
node _T_601 = eq(_T_600, UInt<1>(0h0))
node _T_602 = asUInt(reset)
node _T_603 = eq(_T_602, UInt<1>(0h0))
when _T_603 :
node _T_604 = eq(_T_601, UInt<1>(0h0))
when _T_604 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_601, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<58>
connect d_clr, UInt<58>(0h0)
wire d_clr_wo_ready : UInt<58>
connect d_clr_wo_ready, UInt<58>(0h0)
wire d_opcodes_clr : UInt<232>
connect d_opcodes_clr, UInt<232>(0h0)
wire d_sizes_clr : UInt<232>
connect d_sizes_clr, UInt<232>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_605 = and(io.in.d.valid, d_first_1)
node _T_606 = and(_T_605, UInt<1>(0h1))
node _T_607 = eq(d_release_ack, UInt<1>(0h0))
node _T_608 = and(_T_606, _T_607)
when _T_608 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_609 = and(io.in.d.ready, io.in.d.valid)
node _T_610 = and(_T_609, d_first_1)
node _T_611 = and(_T_610, UInt<1>(0h1))
node _T_612 = eq(d_release_ack, UInt<1>(0h0))
node _T_613 = and(_T_611, _T_612)
when _T_613 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_614 = and(io.in.d.valid, d_first_1)
node _T_615 = and(_T_614, UInt<1>(0h1))
node _T_616 = eq(d_release_ack, UInt<1>(0h0))
node _T_617 = and(_T_615, _T_616)
when _T_617 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_618 = dshr(inflight, io.in.d.bits.source)
node _T_619 = bits(_T_618, 0, 0)
node _T_620 = or(_T_619, same_cycle_resp)
node _T_621 = asUInt(reset)
node _T_622 = eq(_T_621, UInt<1>(0h0))
when _T_622 :
node _T_623 = eq(_T_620, UInt<1>(0h0))
when _T_623 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_620, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_626 = or(_T_624, _T_625)
node _T_627 = asUInt(reset)
node _T_628 = eq(_T_627, UInt<1>(0h0))
when _T_628 :
node _T_629 = eq(_T_626, UInt<1>(0h0))
when _T_629 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_626, UInt<1>(0h1), "") : assert_100
node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_631 = asUInt(reset)
node _T_632 = eq(_T_631, UInt<1>(0h0))
when _T_632 :
node _T_633 = eq(_T_630, UInt<1>(0h0))
when _T_633 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_630, UInt<1>(0h1), "") : assert_101
else :
node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_636 = or(_T_634, _T_635)
node _T_637 = asUInt(reset)
node _T_638 = eq(_T_637, UInt<1>(0h0))
when _T_638 :
node _T_639 = eq(_T_636, UInt<1>(0h0))
when _T_639 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_636, UInt<1>(0h1), "") : assert_102
node _T_640 = eq(io.in.d.bits.size, a_size_lookup)
node _T_641 = asUInt(reset)
node _T_642 = eq(_T_641, UInt<1>(0h0))
when _T_642 :
node _T_643 = eq(_T_640, UInt<1>(0h0))
when _T_643 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_640, UInt<1>(0h1), "") : assert_103
node _T_644 = and(io.in.d.valid, d_first_1)
node _T_645 = and(_T_644, a_first_1)
node _T_646 = and(_T_645, io.in.a.valid)
node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_648 = and(_T_646, _T_647)
node _T_649 = eq(d_release_ack, UInt<1>(0h0))
node _T_650 = and(_T_648, _T_649)
when _T_650 :
node _T_651 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_652 = or(_T_651, io.in.a.ready)
node _T_653 = asUInt(reset)
node _T_654 = eq(_T_653, UInt<1>(0h0))
when _T_654 :
node _T_655 = eq(_T_652, UInt<1>(0h0))
when _T_655 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_652, UInt<1>(0h1), "") : assert_104
node _T_656 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_657 = orr(a_set_wo_ready)
node _T_658 = eq(_T_657, UInt<1>(0h0))
node _T_659 = or(_T_656, _T_658)
node _T_660 = asUInt(reset)
node _T_661 = eq(_T_660, UInt<1>(0h0))
when _T_661 :
node _T_662 = eq(_T_659, UInt<1>(0h0))
when _T_662 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_659, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_108
node _T_663 = orr(inflight)
node _T_664 = eq(_T_663, UInt<1>(0h0))
node _T_665 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_666 = or(_T_664, _T_665)
node _T_667 = lt(watchdog, plusarg_reader.out)
node _T_668 = or(_T_666, _T_667)
node _T_669 = asUInt(reset)
node _T_670 = eq(_T_669, UInt<1>(0h0))
when _T_670 :
node _T_671 = eq(_T_668, UInt<1>(0h0))
when _T_671 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_668, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_672 = and(io.in.a.ready, io.in.a.valid)
node _T_673 = and(io.in.d.ready, io.in.d.valid)
node _T_674 = or(_T_672, _T_673)
when _T_674 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<58>, clock, reset, UInt<58>(0h0)
regreset inflight_opcodes_1 : UInt<232>, clock, reset, UInt<232>(0h0)
regreset inflight_sizes_1 : UInt<232>, clock, reset, UInt<232>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<32>(0h0)
connect _c_first_WIRE.bits.source, UInt<6>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<6>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<58>
connect c_set, UInt<58>(0h0)
wire c_set_wo_ready : UInt<58>
connect c_set_wo_ready, UInt<58>(0h0)
wire c_opcodes_set : UInt<232>
connect c_opcodes_set, UInt<232>(0h0)
wire c_sizes_set : UInt<232>
connect c_sizes_set, UInt<232>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<6>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_675 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<6>(0h0)
connect _WIRE_8.bits.size, UInt<3>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_676 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_677 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_678 = and(_T_676, _T_677)
node _T_679 = and(_T_675, _T_678)
when _T_679 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<6>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<32>(0h0)
connect _WIRE_10.bits.source, UInt<6>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_680 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_681 = and(_T_680, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<32>(0h0)
connect _WIRE_12.bits.source, UInt<6>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_682 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_683 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_684 = and(_T_682, _T_683)
node _T_685 = and(_T_681, _T_684)
when _T_685 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_WIRE.bits.source, UInt<6>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<6>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<6>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<6>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<6>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<32>(0h0)
connect _WIRE_14.bits.source, UInt<6>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_686 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_687 = bits(_T_686, 0, 0)
node _T_688 = eq(_T_687, UInt<1>(0h0))
node _T_689 = asUInt(reset)
node _T_690 = eq(_T_689, UInt<1>(0h0))
when _T_690 :
node _T_691 = eq(_T_688, UInt<1>(0h0))
when _T_691 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_688, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<6>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<6>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<58>
connect d_clr_1, UInt<58>(0h0)
wire d_clr_wo_ready_1 : UInt<58>
connect d_clr_wo_ready_1, UInt<58>(0h0)
wire d_opcodes_clr_1 : UInt<232>
connect d_opcodes_clr_1, UInt<232>(0h0)
wire d_sizes_clr_1 : UInt<232>
connect d_sizes_clr_1, UInt<232>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_692 = and(io.in.d.valid, d_first_2)
node _T_693 = and(_T_692, UInt<1>(0h1))
node _T_694 = and(_T_693, d_release_ack_1)
when _T_694 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_695 = and(io.in.d.ready, io.in.d.valid)
node _T_696 = and(_T_695, d_first_2)
node _T_697 = and(_T_696, UInt<1>(0h1))
node _T_698 = and(_T_697, d_release_ack_1)
when _T_698 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_699 = and(io.in.d.valid, d_first_2)
node _T_700 = and(_T_699, UInt<1>(0h1))
node _T_701 = and(_T_700, d_release_ack_1)
when _T_701 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<6>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<6>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<6>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_702 = dshr(inflight_1, io.in.d.bits.source)
node _T_703 = bits(_T_702, 0, 0)
node _T_704 = or(_T_703, same_cycle_resp_1)
node _T_705 = asUInt(reset)
node _T_706 = eq(_T_705, UInt<1>(0h0))
when _T_706 :
node _T_707 = eq(_T_704, UInt<1>(0h0))
when _T_707 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_704, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<32>(0h0)
connect _WIRE_16.bits.source, UInt<6>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_708 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_709 = asUInt(reset)
node _T_710 = eq(_T_709, UInt<1>(0h0))
when _T_710 :
node _T_711 = eq(_T_708, UInt<1>(0h0))
when _T_711 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_708, UInt<1>(0h1), "") : assert_109
else :
node _T_712 = eq(io.in.d.bits.size, c_size_lookup)
node _T_713 = asUInt(reset)
node _T_714 = eq(_T_713, UInt<1>(0h0))
when _T_714 :
node _T_715 = eq(_T_712, UInt<1>(0h0))
when _T_715 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_712, UInt<1>(0h1), "") : assert_110
node _T_716 = and(io.in.d.valid, d_first_2)
node _T_717 = and(_T_716, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<32>(0h0)
connect _WIRE_18.bits.source, UInt<6>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_718 = and(_T_717, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<32>(0h0)
connect _WIRE_20.bits.source, UInt<6>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_719 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_720 = and(_T_718, _T_719)
node _T_721 = and(_T_720, d_release_ack_1)
node _T_722 = eq(c_probe_ack, UInt<1>(0h0))
node _T_723 = and(_T_721, _T_722)
when _T_723 :
node _T_724 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<32>(0h0)
connect _WIRE_22.bits.source, UInt<6>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_725 = or(_T_724, _WIRE_23.ready)
node _T_726 = asUInt(reset)
node _T_727 = eq(_T_726, UInt<1>(0h0))
when _T_727 :
node _T_728 = eq(_T_725, UInt<1>(0h0))
when _T_728 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_725, UInt<1>(0h1), "") : assert_111
node _T_729 = orr(c_set_wo_ready)
when _T_729 :
node _T_730 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_731 = asUInt(reset)
node _T_732 = eq(_T_731, UInt<1>(0h0))
when _T_732 :
node _T_733 = eq(_T_730, UInt<1>(0h0))
when _T_733 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_730, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_109
node _T_734 = orr(inflight_1)
node _T_735 = eq(_T_734, UInt<1>(0h0))
node _T_736 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_737 = or(_T_735, _T_736)
node _T_738 = lt(watchdog_1, plusarg_reader_1.out)
node _T_739 = or(_T_737, _T_738)
node _T_740 = asUInt(reset)
node _T_741 = eq(_T_740, UInt<1>(0h0))
when _T_741 :
node _T_742 = eq(_T_739, UInt<1>(0h0))
when _T_742 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_739, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<32>(0h0)
connect _WIRE_24.bits.source, UInt<6>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_743 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_744 = and(io.in.d.ready, io.in.d.valid)
node _T_745 = or(_T_743, _T_744)
when _T_745 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_41( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [5:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [5:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71]
wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [5:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [5:0] source_1; // @[Monitor.scala:541:22]
reg denied; // @[Monitor.scala:543:22]
reg [57:0] inflight; // @[Monitor.scala:614:27]
reg [231:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [231:0] inflight_sizes; // @[Monitor.scala:618:33]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire [63:0] _GEN_0 = {58'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35]
wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
wire [63:0] _GEN_3 = {58'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [57:0] inflight_1; // @[Monitor.scala:726:35]
reg [231:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module FPUFMAPipe_l3_f32_2 :
input clock : Clock
input reset : Reset
output io : { flip in : { valid : UInt<1>, bits : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, out : { valid : UInt<1>, bits : { data : UInt<65>, exc : UInt<5>}}}
reg valid : UInt<1>, clock
connect valid, io.in.valid
reg in : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clock
when io.in.valid :
node one = shl(UInt<1>(0h1), 31)
node _zero_T = xor(io.in.bits.in1, io.in.bits.in2)
node _zero_T_1 = shl(UInt<1>(0h1), 32)
node zero = and(_zero_T, _zero_T_1)
connect in, io.in.bits
when io.in.bits.swap23 :
connect in.in2, one
node _T = or(io.in.bits.ren3, io.in.bits.swap23)
node _T_1 = eq(_T, UInt<1>(0h0))
when _T_1 :
connect in.in3, zero
inst fma of MulAddRecFNPipe_l2_e8_s24_2
connect fma.clock, clock
connect fma.reset, reset
connect fma.io.validin, valid
connect fma.io.op, in.fmaCmd
connect fma.io.roundingMode, in.rm
connect fma.io.detectTininess, UInt<1>(0h1)
connect fma.io.a, in.in1
connect fma.io.b, in.in2
connect fma.io.c, in.in3
wire res : { data : UInt<65>, exc : UInt<5>}
node _res_data_maskedNaN_T = not(UInt<33>(0h10800000))
node res_data_maskedNaN = and(fma.io.out, _res_data_maskedNaN_T)
node _res_data_T = bits(fma.io.out, 31, 29)
node _res_data_T_1 = andr(_res_data_T)
node _res_data_T_2 = mux(_res_data_T_1, res_data_maskedNaN, fma.io.out)
connect res.data, _res_data_T_2
connect res.exc, fma.io.exceptionFlags
wire io_out_out : { valid : UInt<1>, bits : { data : UInt<65>, exc : UInt<5>}}
connect io_out_out.valid, fma.io.validout
connect io_out_out.bits, res
connect io.out, io_out_out | module FPUFMAPipe_l3_f32_2( // @[FPU.scala:697:7]
input clock, // @[FPU.scala:697:7]
input reset, // @[FPU.scala:697:7]
input io_in_valid, // @[FPU.scala:702:14]
input io_in_bits_ldst, // @[FPU.scala:702:14]
input io_in_bits_wen, // @[FPU.scala:702:14]
input io_in_bits_ren1, // @[FPU.scala:702:14]
input io_in_bits_ren2, // @[FPU.scala:702:14]
input io_in_bits_ren3, // @[FPU.scala:702:14]
input io_in_bits_swap12, // @[FPU.scala:702:14]
input io_in_bits_swap23, // @[FPU.scala:702:14]
input [1:0] io_in_bits_typeTagIn, // @[FPU.scala:702:14]
input [1:0] io_in_bits_typeTagOut, // @[FPU.scala:702:14]
input io_in_bits_fromint, // @[FPU.scala:702:14]
input io_in_bits_toint, // @[FPU.scala:702:14]
input io_in_bits_fastpipe, // @[FPU.scala:702:14]
input io_in_bits_fma, // @[FPU.scala:702:14]
input io_in_bits_div, // @[FPU.scala:702:14]
input io_in_bits_sqrt, // @[FPU.scala:702:14]
input io_in_bits_wflags, // @[FPU.scala:702:14]
input io_in_bits_vec, // @[FPU.scala:702:14]
input [2:0] io_in_bits_rm, // @[FPU.scala:702:14]
input [1:0] io_in_bits_fmaCmd, // @[FPU.scala:702:14]
input [1:0] io_in_bits_typ, // @[FPU.scala:702:14]
input [1:0] io_in_bits_fmt, // @[FPU.scala:702:14]
input [64:0] io_in_bits_in1, // @[FPU.scala:702:14]
input [64:0] io_in_bits_in2, // @[FPU.scala:702:14]
input [64:0] io_in_bits_in3, // @[FPU.scala:702:14]
output [64:0] io_out_bits_data, // @[FPU.scala:702:14]
output [4:0] io_out_bits_exc // @[FPU.scala:702:14]
);
wire [64:0] res_data; // @[FPU.scala:728:17]
wire [32:0] _fma_io_out; // @[FPU.scala:719:19]
wire io_in_valid_0 = io_in_valid; // @[FPU.scala:697:7]
wire io_in_bits_ldst_0 = io_in_bits_ldst; // @[FPU.scala:697:7]
wire io_in_bits_wen_0 = io_in_bits_wen; // @[FPU.scala:697:7]
wire io_in_bits_ren1_0 = io_in_bits_ren1; // @[FPU.scala:697:7]
wire io_in_bits_ren2_0 = io_in_bits_ren2; // @[FPU.scala:697:7]
wire io_in_bits_ren3_0 = io_in_bits_ren3; // @[FPU.scala:697:7]
wire io_in_bits_swap12_0 = io_in_bits_swap12; // @[FPU.scala:697:7]
wire io_in_bits_swap23_0 = io_in_bits_swap23; // @[FPU.scala:697:7]
wire [1:0] io_in_bits_typeTagIn_0 = io_in_bits_typeTagIn; // @[FPU.scala:697:7]
wire [1:0] io_in_bits_typeTagOut_0 = io_in_bits_typeTagOut; // @[FPU.scala:697:7]
wire io_in_bits_fromint_0 = io_in_bits_fromint; // @[FPU.scala:697:7]
wire io_in_bits_toint_0 = io_in_bits_toint; // @[FPU.scala:697:7]
wire io_in_bits_fastpipe_0 = io_in_bits_fastpipe; // @[FPU.scala:697:7]
wire io_in_bits_fma_0 = io_in_bits_fma; // @[FPU.scala:697:7]
wire io_in_bits_div_0 = io_in_bits_div; // @[FPU.scala:697:7]
wire io_in_bits_sqrt_0 = io_in_bits_sqrt; // @[FPU.scala:697:7]
wire io_in_bits_wflags_0 = io_in_bits_wflags; // @[FPU.scala:697:7]
wire io_in_bits_vec_0 = io_in_bits_vec; // @[FPU.scala:697:7]
wire [2:0] io_in_bits_rm_0 = io_in_bits_rm; // @[FPU.scala:697:7]
wire [1:0] io_in_bits_fmaCmd_0 = io_in_bits_fmaCmd; // @[FPU.scala:697:7]
wire [1:0] io_in_bits_typ_0 = io_in_bits_typ; // @[FPU.scala:697:7]
wire [1:0] io_in_bits_fmt_0 = io_in_bits_fmt; // @[FPU.scala:697:7]
wire [64:0] io_in_bits_in1_0 = io_in_bits_in1; // @[FPU.scala:697:7]
wire [64:0] io_in_bits_in2_0 = io_in_bits_in2; // @[FPU.scala:697:7]
wire [64:0] io_in_bits_in3_0 = io_in_bits_in3; // @[FPU.scala:697:7]
wire [31:0] one = 32'h80000000; // @[FPU.scala:710:19]
wire [32:0] _zero_T_1 = 33'h100000000; // @[FPU.scala:711:57]
wire [32:0] _res_data_maskedNaN_T = 33'h1EF7FFFFF; // @[FPU.scala:413:27]
wire io_out_out_valid; // @[Valid.scala:135:21]
wire [64:0] io_out_out_bits_data; // @[Valid.scala:135:21]
wire [4:0] io_out_out_bits_exc; // @[Valid.scala:135:21]
wire [64:0] io_out_bits_data_0; // @[FPU.scala:697:7]
wire [4:0] io_out_bits_exc_0; // @[FPU.scala:697:7]
wire io_out_valid; // @[FPU.scala:697:7]
reg valid; // @[FPU.scala:707:22]
reg in_ldst; // @[FPU.scala:708:15]
reg in_wen; // @[FPU.scala:708:15]
reg in_ren1; // @[FPU.scala:708:15]
reg in_ren2; // @[FPU.scala:708:15]
reg in_ren3; // @[FPU.scala:708:15]
reg in_swap12; // @[FPU.scala:708:15]
reg in_swap23; // @[FPU.scala:708:15]
reg [1:0] in_typeTagIn; // @[FPU.scala:708:15]
reg [1:0] in_typeTagOut; // @[FPU.scala:708:15]
reg in_fromint; // @[FPU.scala:708:15]
reg in_toint; // @[FPU.scala:708:15]
reg in_fastpipe; // @[FPU.scala:708:15]
reg in_fma; // @[FPU.scala:708:15]
reg in_div; // @[FPU.scala:708:15]
reg in_sqrt; // @[FPU.scala:708:15]
reg in_wflags; // @[FPU.scala:708:15]
reg in_vec; // @[FPU.scala:708:15]
reg [2:0] in_rm; // @[FPU.scala:708:15]
reg [1:0] in_fmaCmd; // @[FPU.scala:708:15]
reg [1:0] in_typ; // @[FPU.scala:708:15]
reg [1:0] in_fmt; // @[FPU.scala:708:15]
reg [64:0] in_in1; // @[FPU.scala:708:15]
reg [64:0] in_in2; // @[FPU.scala:708:15]
reg [64:0] in_in3; // @[FPU.scala:708:15]
wire [64:0] _zero_T = io_in_bits_in1_0 ^ io_in_bits_in2_0; // @[FPU.scala:697:7, :711:32]
wire [64:0] zero = {32'h0, _zero_T[32], 32'h0}; // @[FPU.scala:711:{32,50}]
assign io_out_out_bits_data = res_data; // @[Valid.scala:135:21]
wire [4:0] res_exc; // @[FPU.scala:728:17]
assign io_out_out_bits_exc = res_exc; // @[Valid.scala:135:21]
wire [32:0] res_data_maskedNaN = _fma_io_out & 33'h1EF7FFFFF; // @[FPU.scala:413:25, :719:19]
wire [2:0] _res_data_T = _fma_io_out[31:29]; // @[FPU.scala:249:25, :719:19]
wire _res_data_T_1 = &_res_data_T; // @[FPU.scala:249:{25,56}]
wire [32:0] _res_data_T_2 = _res_data_T_1 ? res_data_maskedNaN : _fma_io_out; // @[FPU.scala:249:56, :413:25, :414:10, :719:19]
assign res_data = {32'h0, _res_data_T_2}; // @[FPU.scala:414:10, :728:17, :729:12]
assign io_out_valid = io_out_out_valid; // @[Valid.scala:135:21]
assign io_out_bits_data_0 = io_out_out_bits_data; // @[Valid.scala:135:21]
assign io_out_bits_exc_0 = io_out_out_bits_exc; // @[Valid.scala:135:21]
always @(posedge clock) begin // @[FPU.scala:697:7]
valid <= io_in_valid_0; // @[FPU.scala:697:7, :707:22]
if (io_in_valid_0) begin // @[FPU.scala:697:7]
in_ldst <= io_in_bits_ldst_0; // @[FPU.scala:697:7, :708:15]
in_wen <= io_in_bits_wen_0; // @[FPU.scala:697:7, :708:15]
in_ren1 <= io_in_bits_ren1_0; // @[FPU.scala:697:7, :708:15]
in_ren2 <= io_in_bits_ren2_0; // @[FPU.scala:697:7, :708:15]
in_ren3 <= io_in_bits_ren3_0; // @[FPU.scala:697:7, :708:15]
in_swap12 <= io_in_bits_swap12_0; // @[FPU.scala:697:7, :708:15]
in_swap23 <= io_in_bits_swap23_0; // @[FPU.scala:697:7, :708:15]
in_typeTagIn <= io_in_bits_typeTagIn_0; // @[FPU.scala:697:7, :708:15]
in_typeTagOut <= io_in_bits_typeTagOut_0; // @[FPU.scala:697:7, :708:15]
in_fromint <= io_in_bits_fromint_0; // @[FPU.scala:697:7, :708:15]
in_toint <= io_in_bits_toint_0; // @[FPU.scala:697:7, :708:15]
in_fastpipe <= io_in_bits_fastpipe_0; // @[FPU.scala:697:7, :708:15]
in_fma <= io_in_bits_fma_0; // @[FPU.scala:697:7, :708:15]
in_div <= io_in_bits_div_0; // @[FPU.scala:697:7, :708:15]
in_sqrt <= io_in_bits_sqrt_0; // @[FPU.scala:697:7, :708:15]
in_wflags <= io_in_bits_wflags_0; // @[FPU.scala:697:7, :708:15]
in_vec <= io_in_bits_vec_0; // @[FPU.scala:697:7, :708:15]
in_rm <= io_in_bits_rm_0; // @[FPU.scala:697:7, :708:15]
in_fmaCmd <= io_in_bits_fmaCmd_0; // @[FPU.scala:697:7, :708:15]
in_typ <= io_in_bits_typ_0; // @[FPU.scala:697:7, :708:15]
in_fmt <= io_in_bits_fmt_0; // @[FPU.scala:697:7, :708:15]
in_in1 <= io_in_bits_in1_0; // @[FPU.scala:697:7, :708:15]
in_in2 <= io_in_bits_swap23_0 ? 65'h80000000 : io_in_bits_in2_0; // @[FPU.scala:697:7, :708:15, :714:8, :715:{23,32}]
in_in3 <= io_in_bits_ren3_0 | io_in_bits_swap23_0 ? io_in_bits_in3_0 : zero; // @[FPU.scala:697:7, :708:15, :711:50, :714:8, :716:{21,37,46}]
end
always @(posedge)
MulAddRecFNPipe_l2_e8_s24_2 fma ( // @[FPU.scala:719:19]
.clock (clock),
.reset (reset),
.io_validin (valid), // @[FPU.scala:707:22]
.io_op (in_fmaCmd), // @[FPU.scala:708:15]
.io_a (in_in1[32:0]), // @[FPU.scala:708:15, :724:12]
.io_b (in_in2[32:0]), // @[FPU.scala:708:15, :725:12]
.io_c (in_in3[32:0]), // @[FPU.scala:708:15, :726:12]
.io_roundingMode (in_rm), // @[FPU.scala:708:15]
.io_out (_fma_io_out),
.io_exceptionFlags (res_exc),
.io_validout (io_out_out_valid)
); // @[FPU.scala:719:19]
assign io_out_bits_data = io_out_bits_data_0; // @[FPU.scala:697:7]
assign io_out_bits_exc = io_out_bits_exc_0; // @[FPU.scala:697:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_135 :
output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node rawIn_exp = bits(io.in, 31, 23)
node _rawIn_isZero_T = bits(rawIn_exp, 8, 6)
node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0))
node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7)
node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3))
wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T)
connect rawIn.isNaN, _rawIn_out_isNaN_T_1
node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0))
node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1)
connect rawIn.isInf, _rawIn_out_isInf_T_2
connect rawIn.isZero, rawIn_isZero
node _rawIn_out_sign_T = bits(io.in, 32, 32)
connect rawIn.sign, _rawIn_out_sign_T
node _rawIn_out_sExp_T = cvt(rawIn_exp)
connect rawIn.sExp, _rawIn_out_sExp_T
node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0))
node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T)
node _rawIn_out_sig_T_2 = bits(io.in, 22, 0)
node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2)
connect rawIn.sig, _rawIn_out_sig_T_3
node _io_out_T = shl(io.in, 0)
connect io.out, _io_out_T
node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22)
node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0))
node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0))
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RecFNToRecFN_135( // @[RecFNToRecFN.scala:44:5]
input [32:0] io_in, // @[RecFNToRecFN.scala:48:16]
output [32:0] io_out // @[RecFNToRecFN.scala:48:16]
);
wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5]
wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35]
wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54]
wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5]
wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5]
wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35]
wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}]
wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46]
assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54]
assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PE_357 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>}
inst mac_unit of MacUnit_101
connect mac_unit.clock, clock
connect mac_unit.reset, reset
reg c1 : SInt<8>, clock
reg c2 : SInt<8>, clock
connect io.out_a, io.in_a
connect io.out_control.dataflow, io.in_control.dataflow
connect io.out_control.propagate, io.in_control.propagate
connect io.out_control.shift, io.in_control.shift
connect io.out_id, io.in_id
connect io.out_last, io.in_last
connect io.out_valid, io.in_valid
connect mac_unit.io.in_a, io.in_a
reg last_s : UInt<1>, clock
when io.in_valid :
connect last_s, io.in_control.propagate
node flip = neq(last_s, io.in_control.propagate)
node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0))
connect io.bad_dataflow, UInt<1>(0h0)
node _T = eq(io.in_control.dataflow, UInt<1>(0h0))
node _T_1 = and(UInt<1>(0h0), _T)
node _T_2 = or(UInt<1>(0h0), _T_1)
when _T_2 :
node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_3 :
node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1)
node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2)
node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0)
node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4)
node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_1 = asUInt(c1)
node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1)
node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3)
node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1))
node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1)
node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6)
node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7)
node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0))
node _io_out_c_ones_digit_T = dshr(c1, shift_offset)
node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0)
node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit)
node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T)
node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0)
node _io_out_c_T = dshr(c1, shift_offset)
node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1)
node _io_out_c_T_3 = tail(_io_out_c_T_2, 1)
node _io_out_c_T_4 = asSInt(_io_out_c_T_3)
node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4)
node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7)
node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0)
node _io_out_c_T_10 = asSInt(_io_out_c_T_9)
connect io.out_c, _io_out_c_T_10
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE : SInt<8>
node _mac_unit_io_in_b_T = asUInt(io.in_b)
node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T)
connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE
connect mac_unit.io.in_c, c2
connect c2, mac_unit.io.out_d
node _c1_T = bits(io.in_d, 7, 0)
node _c1_T_1 = asSInt(_c1_T)
connect c1, _c1_T_1
else :
node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1)
node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7)
node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0)
node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9)
node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_10 = asUInt(c2)
node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1)
node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12)
node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1))
node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1)
node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15)
node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16)
node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0))
node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset)
node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0)
node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1)
node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2)
node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0)
node _io_out_c_T_11 = dshr(c2, shift_offset)
node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12)
node _io_out_c_T_14 = tail(_io_out_c_T_13, 1)
node _io_out_c_T_15 = asSInt(_io_out_c_T_14)
node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15)
node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18)
node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0)
node _io_out_c_T_21 = asSInt(_io_out_c_T_20)
connect io.out_c, _io_out_c_T_21
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE_1 : SInt<8>
node _mac_unit_io_in_b_T_2 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2)
connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1
connect mac_unit.io.in_c, c1
connect c1, mac_unit.io.out_d
node _c2_T = bits(io.in_d, 7, 0)
node _c2_T_1 = asSInt(_c2_T)
connect c2, _c2_T_1
else :
node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1))
node _T_5 = and(UInt<1>(0h0), _T_4)
node _T_6 = or(UInt<1>(0h1), _T_5)
when _T_6 :
node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_7 :
connect io.out_c, c1
wire _mac_unit_io_in_b_WIRE_2 : SInt<8>
node _mac_unit_io_in_b_T_4 = asUInt(c2)
node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4)
connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c1, io.in_d
else :
connect io.out_c, c2
wire _mac_unit_io_in_b_WIRE_3 : SInt<8>
node _mac_unit_io_in_b_T_6 = asUInt(c1)
node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6)
connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c2, io.in_d
else :
connect io.bad_dataflow, UInt<1>(0h1)
invalidate io.out_c
invalidate io.out_b
wire _mac_unit_io_in_b_WIRE_4 : SInt<8>
node _mac_unit_io_in_b_T_8 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8)
connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4
connect mac_unit.io.in_c, c2
node _T_8 = eq(io.in_valid, UInt<1>(0h0))
when _T_8 :
connect c1, c1
connect c2, c2
invalidate mac_unit.io.in_b
invalidate mac_unit.io.in_c | module PE_357( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid // @[PE.scala:35:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7]
wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60]
wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [7:0] c1; // @[PE.scala:70:15]
wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [7:0] c2; // @[PE.scala:71:15]
wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25]
wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}]
wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16]
wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8]
c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15]
if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8]
c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15]
if (io_in_valid_0) // @[PE.scala:31:7]
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
always @(posedge)
MacUnit_101 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_b_0), // @[PE.scala:31:7]
.io_out_d (io_out_b_0)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RoundRawFNToRecFN_e8_s24_1 :
output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_1
connect roundAnyRawFNToRecFN.io.invalidExc, io.invalidExc
connect roundAnyRawFNToRecFN.io.infiniteExc, io.infiniteExc
connect roundAnyRawFNToRecFN.io.in.sig, io.in.sig
connect roundAnyRawFNToRecFN.io.in.sExp, io.in.sExp
connect roundAnyRawFNToRecFN.io.in.sign, io.in.sign
connect roundAnyRawFNToRecFN.io.in.isZero, io.in.isZero
connect roundAnyRawFNToRecFN.io.in.isInf, io.in.isInf
connect roundAnyRawFNToRecFN.io.in.isNaN, io.in.isNaN
connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode
connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess
connect io.out, roundAnyRawFNToRecFN.io.out
connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags | module RoundRawFNToRecFN_e8_s24_1( // @[RoundAnyRawFNToRecFN.scala:295:5]
input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_infiniteExc, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16]
input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16]
input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16]
input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:299:16]
output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16]
output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16]
);
wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_infiniteExc_0 = io_infiniteExc; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15]
wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_1 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15]
.io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_infiniteExc (io_infiniteExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_roundingMode (io_roundingMode_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags_0)
); // @[RoundAnyRawFNToRecFN.scala:310:15]
assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RoundRawFNToRecFN_e5_s11_13 :
output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<14>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<17>, exceptionFlags : UInt<5>}
inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie5_is13_oe5_os11_13
connect roundAnyRawFNToRecFN.io.invalidExc, io.invalidExc
connect roundAnyRawFNToRecFN.io.infiniteExc, io.infiniteExc
connect roundAnyRawFNToRecFN.io.in.sig, io.in.sig
connect roundAnyRawFNToRecFN.io.in.sExp, io.in.sExp
connect roundAnyRawFNToRecFN.io.in.sign, io.in.sign
connect roundAnyRawFNToRecFN.io.in.isZero, io.in.isZero
connect roundAnyRawFNToRecFN.io.in.isInf, io.in.isInf
connect roundAnyRawFNToRecFN.io.in.isNaN, io.in.isNaN
connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode
connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess
connect io.out, roundAnyRawFNToRecFN.io.out
connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags | module RoundRawFNToRecFN_e5_s11_13( // @[RoundAnyRawFNToRecFN.scala:295:5]
input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_infiniteExc, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16]
input [6:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16]
input [13:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16]
input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:299:16]
output [16:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16]
output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16]
);
wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_infiniteExc_0 = io_infiniteExc; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [6:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [13:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15]
wire [16:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
RoundAnyRawFNToRecFN_ie5_is13_oe5_os11_13 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15]
.io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_infiniteExc (io_infiniteExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_roundingMode (io_roundingMode_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags_0)
); // @[RoundAnyRawFNToRecFN.scala:310:15]
assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_45 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T
node _is_aligned_mask_T = dshl(UInt<2>(0h3), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 1, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<2>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 0, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 1, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h2))
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(UInt<1>(0h1), mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(UInt<1>(0h1), mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_lo = cat(mask_acc_1, mask_acc)
node mask_hi = cat(mask_acc_3, mask_acc_2)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_11, UInt<1>(0h1), "") : assert_1
node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_15 :
node _T_16 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_17 = and(UInt<1>(0h0), _T_16)
node _T_18 = or(UInt<1>(0h0), _T_17)
node _T_19 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_20 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_21 = cvt(_T_20)
node _T_22 = and(_T_21, asSInt(UInt<10>(0h200)))
node _T_23 = asSInt(_T_22)
node _T_24 = eq(_T_23, asSInt(UInt<1>(0h0)))
node _T_25 = and(_T_19, _T_24)
node _T_26 = or(UInt<1>(0h0), _T_25)
node _T_27 = and(_T_18, _T_26)
node _T_28 = asUInt(reset)
node _T_29 = eq(_T_28, UInt<1>(0h0))
when _T_29 :
node _T_30 = eq(_T_27, UInt<1>(0h0))
when _T_30 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_27, UInt<1>(0h1), "") : assert_2
node _T_31 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_32 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_33 = and(_T_31, _T_32)
node _T_34 = or(UInt<1>(0h0), _T_33)
node _T_35 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_36 = cvt(_T_35)
node _T_37 = and(_T_36, asSInt(UInt<10>(0h200)))
node _T_38 = asSInt(_T_37)
node _T_39 = eq(_T_38, asSInt(UInt<1>(0h0)))
node _T_40 = and(_T_34, _T_39)
node _T_41 = or(UInt<1>(0h0), _T_40)
node _T_42 = and(UInt<1>(0h0), _T_41)
node _T_43 = asUInt(reset)
node _T_44 = eq(_T_43, UInt<1>(0h0))
when _T_44 :
node _T_45 = eq(_T_42, UInt<1>(0h0))
when _T_45 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_42, UInt<1>(0h1), "") : assert_3
node _T_46 = asUInt(reset)
node _T_47 = eq(_T_46, UInt<1>(0h0))
when _T_47 :
node _T_48 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_48 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_49 = geq(io.in.a.bits.size, UInt<2>(0h2))
node _T_50 = asUInt(reset)
node _T_51 = eq(_T_50, UInt<1>(0h0))
when _T_51 :
node _T_52 = eq(_T_49, UInt<1>(0h0))
when _T_52 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_49, UInt<1>(0h1), "") : assert_5
node _T_53 = asUInt(reset)
node _T_54 = eq(_T_53, UInt<1>(0h0))
when _T_54 :
node _T_55 = eq(is_aligned, UInt<1>(0h0))
when _T_55 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_56 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_57 = asUInt(reset)
node _T_58 = eq(_T_57, UInt<1>(0h0))
when _T_58 :
node _T_59 = eq(_T_56, UInt<1>(0h0))
when _T_59 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_56, UInt<1>(0h1), "") : assert_7
node _T_60 = not(io.in.a.bits.mask)
node _T_61 = eq(_T_60, UInt<1>(0h0))
node _T_62 = asUInt(reset)
node _T_63 = eq(_T_62, UInt<1>(0h0))
when _T_63 :
node _T_64 = eq(_T_61, UInt<1>(0h0))
when _T_64 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_61, UInt<1>(0h1), "") : assert_8
node _T_65 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(_T_65, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_65, UInt<1>(0h1), "") : assert_9
node _T_69 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_69 :
node _T_70 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_71 = and(UInt<1>(0h0), _T_70)
node _T_72 = or(UInt<1>(0h0), _T_71)
node _T_73 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_75 = cvt(_T_74)
node _T_76 = and(_T_75, asSInt(UInt<10>(0h200)))
node _T_77 = asSInt(_T_76)
node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0)))
node _T_79 = and(_T_73, _T_78)
node _T_80 = or(UInt<1>(0h0), _T_79)
node _T_81 = and(_T_72, _T_80)
node _T_82 = asUInt(reset)
node _T_83 = eq(_T_82, UInt<1>(0h0))
when _T_83 :
node _T_84 = eq(_T_81, UInt<1>(0h0))
when _T_84 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_81, UInt<1>(0h1), "") : assert_10
node _T_85 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_86 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_87 = and(_T_85, _T_86)
node _T_88 = or(UInt<1>(0h0), _T_87)
node _T_89 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_90 = cvt(_T_89)
node _T_91 = and(_T_90, asSInt(UInt<10>(0h200)))
node _T_92 = asSInt(_T_91)
node _T_93 = eq(_T_92, asSInt(UInt<1>(0h0)))
node _T_94 = and(_T_88, _T_93)
node _T_95 = or(UInt<1>(0h0), _T_94)
node _T_96 = and(UInt<1>(0h0), _T_95)
node _T_97 = asUInt(reset)
node _T_98 = eq(_T_97, UInt<1>(0h0))
when _T_98 :
node _T_99 = eq(_T_96, UInt<1>(0h0))
when _T_99 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_96, UInt<1>(0h1), "") : assert_11
node _T_100 = asUInt(reset)
node _T_101 = eq(_T_100, UInt<1>(0h0))
when _T_101 :
node _T_102 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_102 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_103 = geq(io.in.a.bits.size, UInt<2>(0h2))
node _T_104 = asUInt(reset)
node _T_105 = eq(_T_104, UInt<1>(0h0))
when _T_105 :
node _T_106 = eq(_T_103, UInt<1>(0h0))
when _T_106 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_103, UInt<1>(0h1), "") : assert_13
node _T_107 = asUInt(reset)
node _T_108 = eq(_T_107, UInt<1>(0h0))
when _T_108 :
node _T_109 = eq(is_aligned, UInt<1>(0h0))
when _T_109 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_110 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_111 = asUInt(reset)
node _T_112 = eq(_T_111, UInt<1>(0h0))
when _T_112 :
node _T_113 = eq(_T_110, UInt<1>(0h0))
when _T_113 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_110, UInt<1>(0h1), "") : assert_15
node _T_114 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_115 = asUInt(reset)
node _T_116 = eq(_T_115, UInt<1>(0h0))
when _T_116 :
node _T_117 = eq(_T_114, UInt<1>(0h0))
when _T_117 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_114, UInt<1>(0h1), "") : assert_16
node _T_118 = not(io.in.a.bits.mask)
node _T_119 = eq(_T_118, UInt<1>(0h0))
node _T_120 = asUInt(reset)
node _T_121 = eq(_T_120, UInt<1>(0h0))
when _T_121 :
node _T_122 = eq(_T_119, UInt<1>(0h0))
when _T_122 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_119, UInt<1>(0h1), "") : assert_17
node _T_123 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_124 = asUInt(reset)
node _T_125 = eq(_T_124, UInt<1>(0h0))
when _T_125 :
node _T_126 = eq(_T_123, UInt<1>(0h0))
when _T_126 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_123, UInt<1>(0h1), "") : assert_18
node _T_127 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_127 :
node _T_128 = eq(UInt<2>(0h2), io.in.a.bits.size)
node _T_129 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_130 = and(_T_128, _T_129)
node _T_131 = or(UInt<1>(0h0), _T_130)
node _T_132 = asUInt(reset)
node _T_133 = eq(_T_132, UInt<1>(0h0))
when _T_133 :
node _T_134 = eq(_T_131, UInt<1>(0h0))
when _T_134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_131, UInt<1>(0h1), "") : assert_19
node _T_135 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_136 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_137 = and(_T_135, _T_136)
node _T_138 = or(UInt<1>(0h0), _T_137)
node _T_139 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_140 = cvt(_T_139)
node _T_141 = and(_T_140, asSInt(UInt<10>(0h200)))
node _T_142 = asSInt(_T_141)
node _T_143 = eq(_T_142, asSInt(UInt<1>(0h0)))
node _T_144 = and(_T_138, _T_143)
node _T_145 = or(UInt<1>(0h0), _T_144)
node _T_146 = asUInt(reset)
node _T_147 = eq(_T_146, UInt<1>(0h0))
when _T_147 :
node _T_148 = eq(_T_145, UInt<1>(0h0))
when _T_148 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_145, UInt<1>(0h1), "") : assert_20
node _T_149 = asUInt(reset)
node _T_150 = eq(_T_149, UInt<1>(0h0))
when _T_150 :
node _T_151 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_151 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_152 = asUInt(reset)
node _T_153 = eq(_T_152, UInt<1>(0h0))
when _T_153 :
node _T_154 = eq(is_aligned, UInt<1>(0h0))
when _T_154 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_155 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_156 = asUInt(reset)
node _T_157 = eq(_T_156, UInt<1>(0h0))
when _T_157 :
node _T_158 = eq(_T_155, UInt<1>(0h0))
when _T_158 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_155, UInt<1>(0h1), "") : assert_23
node _T_159 = eq(io.in.a.bits.mask, mask)
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(_T_159, UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_159, UInt<1>(0h1), "") : assert_24
node _T_163 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_164 = asUInt(reset)
node _T_165 = eq(_T_164, UInt<1>(0h0))
when _T_165 :
node _T_166 = eq(_T_163, UInt<1>(0h0))
when _T_166 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_163, UInt<1>(0h1), "") : assert_25
node _T_167 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_167 :
node _T_168 = eq(UInt<2>(0h2), io.in.a.bits.size)
node _T_169 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_170 = and(_T_168, _T_169)
node _T_171 = or(UInt<1>(0h0), _T_170)
node _T_172 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_173 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_174 = and(_T_172, _T_173)
node _T_175 = or(UInt<1>(0h0), _T_174)
node _T_176 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_177 = cvt(_T_176)
node _T_178 = and(_T_177, asSInt(UInt<10>(0h200)))
node _T_179 = asSInt(_T_178)
node _T_180 = eq(_T_179, asSInt(UInt<1>(0h0)))
node _T_181 = and(_T_175, _T_180)
node _T_182 = or(UInt<1>(0h0), _T_181)
node _T_183 = and(_T_171, _T_182)
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_183, UInt<1>(0h1), "") : assert_26
node _T_187 = asUInt(reset)
node _T_188 = eq(_T_187, UInt<1>(0h0))
when _T_188 :
node _T_189 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_189 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_190 = asUInt(reset)
node _T_191 = eq(_T_190, UInt<1>(0h0))
when _T_191 :
node _T_192 = eq(is_aligned, UInt<1>(0h0))
when _T_192 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_193 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_194 = asUInt(reset)
node _T_195 = eq(_T_194, UInt<1>(0h0))
when _T_195 :
node _T_196 = eq(_T_193, UInt<1>(0h0))
when _T_196 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_193, UInt<1>(0h1), "") : assert_29
node _T_197 = eq(io.in.a.bits.mask, mask)
node _T_198 = asUInt(reset)
node _T_199 = eq(_T_198, UInt<1>(0h0))
when _T_199 :
node _T_200 = eq(_T_197, UInt<1>(0h0))
when _T_200 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_197, UInt<1>(0h1), "") : assert_30
node _T_201 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_201 :
node _T_202 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_203 = and(UInt<1>(0h0), _T_202)
node _T_204 = or(UInt<1>(0h0), _T_203)
node _T_205 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_206 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_207 = and(_T_205, _T_206)
node _T_208 = or(UInt<1>(0h0), _T_207)
node _T_209 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_210 = cvt(_T_209)
node _T_211 = and(_T_210, asSInt(UInt<10>(0h200)))
node _T_212 = asSInt(_T_211)
node _T_213 = eq(_T_212, asSInt(UInt<1>(0h0)))
node _T_214 = and(_T_208, _T_213)
node _T_215 = or(UInt<1>(0h0), _T_214)
node _T_216 = and(_T_204, _T_215)
node _T_217 = asUInt(reset)
node _T_218 = eq(_T_217, UInt<1>(0h0))
when _T_218 :
node _T_219 = eq(_T_216, UInt<1>(0h0))
when _T_219 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_216, UInt<1>(0h1), "") : assert_31
node _T_220 = asUInt(reset)
node _T_221 = eq(_T_220, UInt<1>(0h0))
when _T_221 :
node _T_222 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_222 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_223 = asUInt(reset)
node _T_224 = eq(_T_223, UInt<1>(0h0))
when _T_224 :
node _T_225 = eq(is_aligned, UInt<1>(0h0))
when _T_225 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_226 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_227 = asUInt(reset)
node _T_228 = eq(_T_227, UInt<1>(0h0))
when _T_228 :
node _T_229 = eq(_T_226, UInt<1>(0h0))
when _T_229 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_226, UInt<1>(0h1), "") : assert_34
node _T_230 = not(mask)
node _T_231 = and(io.in.a.bits.mask, _T_230)
node _T_232 = eq(_T_231, UInt<1>(0h0))
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_232, UInt<1>(0h1), "") : assert_35
node _T_236 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_236 :
node _T_237 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_238 = and(UInt<1>(0h0), _T_237)
node _T_239 = or(UInt<1>(0h0), _T_238)
node _T_240 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_241 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_242 = cvt(_T_241)
node _T_243 = and(_T_242, asSInt(UInt<10>(0h200)))
node _T_244 = asSInt(_T_243)
node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0)))
node _T_246 = and(_T_240, _T_245)
node _T_247 = or(UInt<1>(0h0), _T_246)
node _T_248 = and(_T_239, _T_247)
node _T_249 = asUInt(reset)
node _T_250 = eq(_T_249, UInt<1>(0h0))
when _T_250 :
node _T_251 = eq(_T_248, UInt<1>(0h0))
when _T_251 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_248, UInt<1>(0h1), "") : assert_36
node _T_252 = asUInt(reset)
node _T_253 = eq(_T_252, UInt<1>(0h0))
when _T_253 :
node _T_254 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_254 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_255 = asUInt(reset)
node _T_256 = eq(_T_255, UInt<1>(0h0))
when _T_256 :
node _T_257 = eq(is_aligned, UInt<1>(0h0))
when _T_257 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_258 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_259 = asUInt(reset)
node _T_260 = eq(_T_259, UInt<1>(0h0))
when _T_260 :
node _T_261 = eq(_T_258, UInt<1>(0h0))
when _T_261 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_258, UInt<1>(0h1), "") : assert_39
node _T_262 = eq(io.in.a.bits.mask, mask)
node _T_263 = asUInt(reset)
node _T_264 = eq(_T_263, UInt<1>(0h0))
when _T_264 :
node _T_265 = eq(_T_262, UInt<1>(0h0))
when _T_265 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_262, UInt<1>(0h1), "") : assert_40
node _T_266 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_266 :
node _T_267 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_268 = and(UInt<1>(0h0), _T_267)
node _T_269 = or(UInt<1>(0h0), _T_268)
node _T_270 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_271 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_272 = cvt(_T_271)
node _T_273 = and(_T_272, asSInt(UInt<10>(0h200)))
node _T_274 = asSInt(_T_273)
node _T_275 = eq(_T_274, asSInt(UInt<1>(0h0)))
node _T_276 = and(_T_270, _T_275)
node _T_277 = or(UInt<1>(0h0), _T_276)
node _T_278 = and(_T_269, _T_277)
node _T_279 = asUInt(reset)
node _T_280 = eq(_T_279, UInt<1>(0h0))
when _T_280 :
node _T_281 = eq(_T_278, UInt<1>(0h0))
when _T_281 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_278, UInt<1>(0h1), "") : assert_41
node _T_282 = asUInt(reset)
node _T_283 = eq(_T_282, UInt<1>(0h0))
when _T_283 :
node _T_284 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_284 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_285 = asUInt(reset)
node _T_286 = eq(_T_285, UInt<1>(0h0))
when _T_286 :
node _T_287 = eq(is_aligned, UInt<1>(0h0))
when _T_287 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_288 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_289 = asUInt(reset)
node _T_290 = eq(_T_289, UInt<1>(0h0))
when _T_290 :
node _T_291 = eq(_T_288, UInt<1>(0h0))
when _T_291 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_288, UInt<1>(0h1), "") : assert_44
node _T_292 = eq(io.in.a.bits.mask, mask)
node _T_293 = asUInt(reset)
node _T_294 = eq(_T_293, UInt<1>(0h0))
when _T_294 :
node _T_295 = eq(_T_292, UInt<1>(0h0))
when _T_295 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_292, UInt<1>(0h1), "") : assert_45
node _T_296 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_296 :
node _T_297 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_298 = and(UInt<1>(0h0), _T_297)
node _T_299 = or(UInt<1>(0h0), _T_298)
node _T_300 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_301 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_302 = cvt(_T_301)
node _T_303 = and(_T_302, asSInt(UInt<10>(0h200)))
node _T_304 = asSInt(_T_303)
node _T_305 = eq(_T_304, asSInt(UInt<1>(0h0)))
node _T_306 = and(_T_300, _T_305)
node _T_307 = or(UInt<1>(0h0), _T_306)
node _T_308 = and(_T_299, _T_307)
node _T_309 = asUInt(reset)
node _T_310 = eq(_T_309, UInt<1>(0h0))
when _T_310 :
node _T_311 = eq(_T_308, UInt<1>(0h0))
when _T_311 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_308, UInt<1>(0h1), "") : assert_46
node _T_312 = asUInt(reset)
node _T_313 = eq(_T_312, UInt<1>(0h0))
when _T_313 :
node _T_314 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_314 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_315 = asUInt(reset)
node _T_316 = eq(_T_315, UInt<1>(0h0))
when _T_316 :
node _T_317 = eq(is_aligned, UInt<1>(0h0))
when _T_317 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_318 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_319 = asUInt(reset)
node _T_320 = eq(_T_319, UInt<1>(0h0))
when _T_320 :
node _T_321 = eq(_T_318, UInt<1>(0h0))
when _T_321 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_318, UInt<1>(0h1), "") : assert_49
node _T_322 = eq(io.in.a.bits.mask, mask)
node _T_323 = asUInt(reset)
node _T_324 = eq(_T_323, UInt<1>(0h0))
when _T_324 :
node _T_325 = eq(_T_322, UInt<1>(0h0))
when _T_325 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_322, UInt<1>(0h1), "") : assert_50
node _T_326 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_327 = asUInt(reset)
node _T_328 = eq(_T_327, UInt<1>(0h0))
when _T_328 :
node _T_329 = eq(_T_326, UInt<1>(0h0))
when _T_329 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_326, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_330 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_331 = asUInt(reset)
node _T_332 = eq(_T_331, UInt<1>(0h0))
when _T_332 :
node _T_333 = eq(_T_330, UInt<1>(0h0))
when _T_333 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_330, UInt<1>(0h1), "") : assert_52
node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_1
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_334 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_334 :
node _T_335 = asUInt(reset)
node _T_336 = eq(_T_335, UInt<1>(0h0))
when _T_336 :
node _T_337 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_337 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_338 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_339 = asUInt(reset)
node _T_340 = eq(_T_339, UInt<1>(0h0))
when _T_340 :
node _T_341 = eq(_T_338, UInt<1>(0h0))
when _T_341 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_338, UInt<1>(0h1), "") : assert_54
node _T_342 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_343 = asUInt(reset)
node _T_344 = eq(_T_343, UInt<1>(0h0))
when _T_344 :
node _T_345 = eq(_T_342, UInt<1>(0h0))
when _T_345 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_342, UInt<1>(0h1), "") : assert_55
node _T_346 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_347 = asUInt(reset)
node _T_348 = eq(_T_347, UInt<1>(0h0))
when _T_348 :
node _T_349 = eq(_T_346, UInt<1>(0h0))
when _T_349 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_346, UInt<1>(0h1), "") : assert_56
node _T_350 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_351 = asUInt(reset)
node _T_352 = eq(_T_351, UInt<1>(0h0))
when _T_352 :
node _T_353 = eq(_T_350, UInt<1>(0h0))
when _T_353 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_350, UInt<1>(0h1), "") : assert_57
node _T_354 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_354 :
node _T_355 = asUInt(reset)
node _T_356 = eq(_T_355, UInt<1>(0h0))
when _T_356 :
node _T_357 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_357 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_358 = asUInt(reset)
node _T_359 = eq(_T_358, UInt<1>(0h0))
when _T_359 :
node _T_360 = eq(sink_ok, UInt<1>(0h0))
when _T_360 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_361 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_362 = asUInt(reset)
node _T_363 = eq(_T_362, UInt<1>(0h0))
when _T_363 :
node _T_364 = eq(_T_361, UInt<1>(0h0))
when _T_364 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_361, UInt<1>(0h1), "") : assert_60
node _T_365 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_366 = asUInt(reset)
node _T_367 = eq(_T_366, UInt<1>(0h0))
when _T_367 :
node _T_368 = eq(_T_365, UInt<1>(0h0))
when _T_368 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_365, UInt<1>(0h1), "") : assert_61
node _T_369 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_370 = asUInt(reset)
node _T_371 = eq(_T_370, UInt<1>(0h0))
when _T_371 :
node _T_372 = eq(_T_369, UInt<1>(0h0))
when _T_372 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_369, UInt<1>(0h1), "") : assert_62
node _T_373 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_374 = asUInt(reset)
node _T_375 = eq(_T_374, UInt<1>(0h0))
when _T_375 :
node _T_376 = eq(_T_373, UInt<1>(0h0))
when _T_376 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_373, UInt<1>(0h1), "") : assert_63
node _T_377 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_378 = or(UInt<1>(0h1), _T_377)
node _T_379 = asUInt(reset)
node _T_380 = eq(_T_379, UInt<1>(0h0))
when _T_380 :
node _T_381 = eq(_T_378, UInt<1>(0h0))
when _T_381 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_378, UInt<1>(0h1), "") : assert_64
node _T_382 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_382 :
node _T_383 = asUInt(reset)
node _T_384 = eq(_T_383, UInt<1>(0h0))
when _T_384 :
node _T_385 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_385 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_386 = asUInt(reset)
node _T_387 = eq(_T_386, UInt<1>(0h0))
when _T_387 :
node _T_388 = eq(sink_ok, UInt<1>(0h0))
when _T_388 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_389 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_390 = asUInt(reset)
node _T_391 = eq(_T_390, UInt<1>(0h0))
when _T_391 :
node _T_392 = eq(_T_389, UInt<1>(0h0))
when _T_392 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_389, UInt<1>(0h1), "") : assert_67
node _T_393 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_394 = asUInt(reset)
node _T_395 = eq(_T_394, UInt<1>(0h0))
when _T_395 :
node _T_396 = eq(_T_393, UInt<1>(0h0))
when _T_396 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_393, UInt<1>(0h1), "") : assert_68
node _T_397 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(_T_397, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_397, UInt<1>(0h1), "") : assert_69
node _T_401 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_402 = or(_T_401, io.in.d.bits.corrupt)
node _T_403 = asUInt(reset)
node _T_404 = eq(_T_403, UInt<1>(0h0))
when _T_404 :
node _T_405 = eq(_T_402, UInt<1>(0h0))
when _T_405 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_402, UInt<1>(0h1), "") : assert_70
node _T_406 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_407 = or(UInt<1>(0h1), _T_406)
node _T_408 = asUInt(reset)
node _T_409 = eq(_T_408, UInt<1>(0h0))
when _T_409 :
node _T_410 = eq(_T_407, UInt<1>(0h0))
when _T_410 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_407, UInt<1>(0h1), "") : assert_71
node _T_411 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_411 :
node _T_412 = asUInt(reset)
node _T_413 = eq(_T_412, UInt<1>(0h0))
when _T_413 :
node _T_414 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_414 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_415 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_416 = asUInt(reset)
node _T_417 = eq(_T_416, UInt<1>(0h0))
when _T_417 :
node _T_418 = eq(_T_415, UInt<1>(0h0))
when _T_418 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_415, UInt<1>(0h1), "") : assert_73
node _T_419 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_420 = asUInt(reset)
node _T_421 = eq(_T_420, UInt<1>(0h0))
when _T_421 :
node _T_422 = eq(_T_419, UInt<1>(0h0))
when _T_422 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_419, UInt<1>(0h1), "") : assert_74
node _T_423 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_424 = or(UInt<1>(0h1), _T_423)
node _T_425 = asUInt(reset)
node _T_426 = eq(_T_425, UInt<1>(0h0))
when _T_426 :
node _T_427 = eq(_T_424, UInt<1>(0h0))
when _T_427 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_424, UInt<1>(0h1), "") : assert_75
node _T_428 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_428 :
node _T_429 = asUInt(reset)
node _T_430 = eq(_T_429, UInt<1>(0h0))
when _T_430 :
node _T_431 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_431 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_432 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_433 = asUInt(reset)
node _T_434 = eq(_T_433, UInt<1>(0h0))
when _T_434 :
node _T_435 = eq(_T_432, UInt<1>(0h0))
when _T_435 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_432, UInt<1>(0h1), "") : assert_77
node _T_436 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_437 = or(_T_436, io.in.d.bits.corrupt)
node _T_438 = asUInt(reset)
node _T_439 = eq(_T_438, UInt<1>(0h0))
when _T_439 :
node _T_440 = eq(_T_437, UInt<1>(0h0))
when _T_440 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_437, UInt<1>(0h1), "") : assert_78
node _T_441 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_442 = or(UInt<1>(0h1), _T_441)
node _T_443 = asUInt(reset)
node _T_444 = eq(_T_443, UInt<1>(0h0))
when _T_444 :
node _T_445 = eq(_T_442, UInt<1>(0h0))
when _T_445 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_442, UInt<1>(0h1), "") : assert_79
node _T_446 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_446 :
node _T_447 = asUInt(reset)
node _T_448 = eq(_T_447, UInt<1>(0h0))
when _T_448 :
node _T_449 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_449 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_450 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_451 = asUInt(reset)
node _T_452 = eq(_T_451, UInt<1>(0h0))
when _T_452 :
node _T_453 = eq(_T_450, UInt<1>(0h0))
when _T_453 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_450, UInt<1>(0h1), "") : assert_81
node _T_454 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_455 = asUInt(reset)
node _T_456 = eq(_T_455, UInt<1>(0h0))
when _T_456 :
node _T_457 = eq(_T_454, UInt<1>(0h0))
when _T_457 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_454, UInt<1>(0h1), "") : assert_82
node _T_458 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_459 = or(UInt<1>(0h1), _T_458)
node _T_460 = asUInt(reset)
node _T_461 = eq(_T_460, UInt<1>(0h0))
when _T_461 :
node _T_462 = eq(_T_459, UInt<1>(0h0))
when _T_462 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_459, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<32>(0h0)
connect _WIRE.bits.mask, UInt<4>(0h0)
connect _WIRE.bits.address, UInt<9>(0h0)
connect _WIRE.bits.source, UInt<1>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_463 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_464 = asUInt(reset)
node _T_465 = eq(_T_464, UInt<1>(0h0))
when _T_465 :
node _T_466 = eq(_T_463, UInt<1>(0h0))
when _T_466 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_463, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<32>(0h0)
connect _WIRE_2.bits.address, UInt<9>(0h0)
connect _WIRE_2.bits.source, UInt<1>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_467 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_468 = asUInt(reset)
node _T_469 = eq(_T_468, UInt<1>(0h0))
when _T_469 :
node _T_470 = eq(_T_467, UInt<1>(0h0))
when _T_470 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_467, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_471 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_472 = asUInt(reset)
node _T_473 = eq(_T_472, UInt<1>(0h0))
when _T_473 :
node _T_474 = eq(_T_471, UInt<1>(0h0))
when _T_474 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_471, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 1, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 2)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_475 = eq(a_first, UInt<1>(0h0))
node _T_476 = and(io.in.a.valid, _T_475)
when _T_476 :
node _T_477 = eq(io.in.a.bits.opcode, opcode)
node _T_478 = asUInt(reset)
node _T_479 = eq(_T_478, UInt<1>(0h0))
when _T_479 :
node _T_480 = eq(_T_477, UInt<1>(0h0))
when _T_480 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_477, UInt<1>(0h1), "") : assert_87
node _T_481 = eq(io.in.a.bits.param, param)
node _T_482 = asUInt(reset)
node _T_483 = eq(_T_482, UInt<1>(0h0))
when _T_483 :
node _T_484 = eq(_T_481, UInt<1>(0h0))
when _T_484 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_481, UInt<1>(0h1), "") : assert_88
node _T_485 = eq(io.in.a.bits.size, size)
node _T_486 = asUInt(reset)
node _T_487 = eq(_T_486, UInt<1>(0h0))
when _T_487 :
node _T_488 = eq(_T_485, UInt<1>(0h0))
when _T_488 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_485, UInt<1>(0h1), "") : assert_89
node _T_489 = eq(io.in.a.bits.source, source)
node _T_490 = asUInt(reset)
node _T_491 = eq(_T_490, UInt<1>(0h0))
when _T_491 :
node _T_492 = eq(_T_489, UInt<1>(0h0))
when _T_492 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_489, UInt<1>(0h1), "") : assert_90
node _T_493 = eq(io.in.a.bits.address, address)
node _T_494 = asUInt(reset)
node _T_495 = eq(_T_494, UInt<1>(0h0))
when _T_495 :
node _T_496 = eq(_T_493, UInt<1>(0h0))
when _T_496 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_493, UInt<1>(0h1), "") : assert_91
node _T_497 = and(io.in.a.ready, io.in.a.valid)
node _T_498 = and(_T_497, a_first)
when _T_498 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 1, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 2)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_499 = eq(d_first, UInt<1>(0h0))
node _T_500 = and(io.in.d.valid, _T_499)
when _T_500 :
node _T_501 = eq(io.in.d.bits.opcode, opcode_1)
node _T_502 = asUInt(reset)
node _T_503 = eq(_T_502, UInt<1>(0h0))
when _T_503 :
node _T_504 = eq(_T_501, UInt<1>(0h0))
when _T_504 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_501, UInt<1>(0h1), "") : assert_92
node _T_505 = eq(io.in.d.bits.param, param_1)
node _T_506 = asUInt(reset)
node _T_507 = eq(_T_506, UInt<1>(0h0))
when _T_507 :
node _T_508 = eq(_T_505, UInt<1>(0h0))
when _T_508 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_505, UInt<1>(0h1), "") : assert_93
node _T_509 = eq(io.in.d.bits.size, size_1)
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_T_509, UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_509, UInt<1>(0h1), "") : assert_94
node _T_513 = eq(io.in.d.bits.source, source_1)
node _T_514 = asUInt(reset)
node _T_515 = eq(_T_514, UInt<1>(0h0))
when _T_515 :
node _T_516 = eq(_T_513, UInt<1>(0h0))
when _T_516 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_513, UInt<1>(0h1), "") : assert_95
node _T_517 = eq(io.in.d.bits.sink, sink)
node _T_518 = asUInt(reset)
node _T_519 = eq(_T_518, UInt<1>(0h0))
when _T_519 :
node _T_520 = eq(_T_517, UInt<1>(0h0))
when _T_520 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_517, UInt<1>(0h1), "") : assert_96
node _T_521 = eq(io.in.d.bits.denied, denied)
node _T_522 = asUInt(reset)
node _T_523 = eq(_T_522, UInt<1>(0h0))
when _T_523 :
node _T_524 = eq(_T_521, UInt<1>(0h0))
when _T_524 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_521, UInt<1>(0h1), "") : assert_97
node _T_525 = and(io.in.d.ready, io.in.d.valid)
node _T_526 = and(_T_525, d_first)
when _T_526 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes : UInt<4>, clock, reset, UInt<4>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 1, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 2)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 1, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 2)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<1>
connect a_set, UInt<1>(0h0)
wire a_set_wo_ready : UInt<1>
connect a_set_wo_ready, UInt<1>(0h0)
wire a_opcodes_set : UInt<4>
connect a_opcodes_set, UInt<4>(0h0)
wire a_sizes_set : UInt<4>
connect a_sizes_set, UInt<4>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<3>
connect a_sizes_set_interm, UInt<3>(0h0)
node _T_527 = and(io.in.a.valid, a_first_1)
node _T_528 = and(_T_527, UInt<1>(0h1))
when _T_528 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_529 = and(io.in.a.ready, io.in.a.valid)
node _T_530 = and(_T_529, a_first_1)
node _T_531 = and(_T_530, UInt<1>(0h1))
when _T_531 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_532 = dshr(inflight, io.in.a.bits.source)
node _T_533 = bits(_T_532, 0, 0)
node _T_534 = eq(_T_533, UInt<1>(0h0))
node _T_535 = asUInt(reset)
node _T_536 = eq(_T_535, UInt<1>(0h0))
when _T_536 :
node _T_537 = eq(_T_534, UInt<1>(0h0))
when _T_537 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_534, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<1>
connect d_clr, UInt<1>(0h0)
wire d_clr_wo_ready : UInt<1>
connect d_clr_wo_ready, UInt<1>(0h0)
wire d_opcodes_clr : UInt<4>
connect d_opcodes_clr, UInt<4>(0h0)
wire d_sizes_clr : UInt<4>
connect d_sizes_clr, UInt<4>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_538 = and(io.in.d.valid, d_first_1)
node _T_539 = and(_T_538, UInt<1>(0h1))
node _T_540 = eq(d_release_ack, UInt<1>(0h0))
node _T_541 = and(_T_539, _T_540)
when _T_541 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_542 = and(io.in.d.ready, io.in.d.valid)
node _T_543 = and(_T_542, d_first_1)
node _T_544 = and(_T_543, UInt<1>(0h1))
node _T_545 = eq(d_release_ack, UInt<1>(0h0))
node _T_546 = and(_T_544, _T_545)
when _T_546 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_547 = and(io.in.d.valid, d_first_1)
node _T_548 = and(_T_547, UInt<1>(0h1))
node _T_549 = eq(d_release_ack, UInt<1>(0h0))
node _T_550 = and(_T_548, _T_549)
when _T_550 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_551 = dshr(inflight, io.in.d.bits.source)
node _T_552 = bits(_T_551, 0, 0)
node _T_553 = or(_T_552, same_cycle_resp)
node _T_554 = asUInt(reset)
node _T_555 = eq(_T_554, UInt<1>(0h0))
when _T_555 :
node _T_556 = eq(_T_553, UInt<1>(0h0))
when _T_556 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_553, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_557 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_558 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_559 = or(_T_557, _T_558)
node _T_560 = asUInt(reset)
node _T_561 = eq(_T_560, UInt<1>(0h0))
when _T_561 :
node _T_562 = eq(_T_559, UInt<1>(0h0))
when _T_562 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_559, UInt<1>(0h1), "") : assert_100
node _T_563 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_564 = asUInt(reset)
node _T_565 = eq(_T_564, UInt<1>(0h0))
when _T_565 :
node _T_566 = eq(_T_563, UInt<1>(0h0))
when _T_566 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_563, UInt<1>(0h1), "") : assert_101
else :
node _T_567 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_568 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_569 = or(_T_567, _T_568)
node _T_570 = asUInt(reset)
node _T_571 = eq(_T_570, UInt<1>(0h0))
when _T_571 :
node _T_572 = eq(_T_569, UInt<1>(0h0))
when _T_572 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_569, UInt<1>(0h1), "") : assert_102
node _T_573 = eq(io.in.d.bits.size, a_size_lookup)
node _T_574 = asUInt(reset)
node _T_575 = eq(_T_574, UInt<1>(0h0))
when _T_575 :
node _T_576 = eq(_T_573, UInt<1>(0h0))
when _T_576 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_573, UInt<1>(0h1), "") : assert_103
node _T_577 = and(io.in.d.valid, d_first_1)
node _T_578 = and(_T_577, a_first_1)
node _T_579 = and(_T_578, io.in.a.valid)
node _T_580 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_581 = and(_T_579, _T_580)
node _T_582 = eq(d_release_ack, UInt<1>(0h0))
node _T_583 = and(_T_581, _T_582)
when _T_583 :
node _T_584 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_585 = or(_T_584, io.in.a.ready)
node _T_586 = asUInt(reset)
node _T_587 = eq(_T_586, UInt<1>(0h0))
when _T_587 :
node _T_588 = eq(_T_585, UInt<1>(0h0))
when _T_588 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_585, UInt<1>(0h1), "") : assert_104
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_91
node _T_589 = orr(inflight)
node _T_590 = eq(_T_589, UInt<1>(0h0))
node _T_591 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_592 = or(_T_590, _T_591)
node _T_593 = lt(watchdog, plusarg_reader.out)
node _T_594 = or(_T_592, _T_593)
node _T_595 = asUInt(reset)
node _T_596 = eq(_T_595, UInt<1>(0h0))
when _T_596 :
node _T_597 = eq(_T_594, UInt<1>(0h0))
when _T_597 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_594, UInt<1>(0h1), "") : assert_105
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_598 = and(io.in.a.ready, io.in.a.valid)
node _T_599 = and(io.in.d.ready, io.in.d.valid)
node _T_600 = or(_T_598, _T_599)
when _T_600 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes_1 : UInt<4>, clock, reset, UInt<4>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<32>(0h0)
connect _c_first_WIRE.bits.address, UInt<9>(0h0)
connect _c_first_WIRE.bits.source, UInt<1>(0h0)
connect _c_first_WIRE.bits.size, UInt<2>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<9>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<2>(0h3), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 1, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 2)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<2>(0h3), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 1, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 2)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<1>
connect c_set, UInt<1>(0h0)
wire c_set_wo_ready : UInt<1>
connect c_set_wo_ready, UInt<1>(0h0)
wire c_opcodes_set : UInt<4>
connect c_opcodes_set, UInt<4>(0h0)
wire c_sizes_set : UInt<4>
connect c_sizes_set, UInt<4>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<3>
connect c_sizes_set_interm, UInt<3>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<32>(0h0)
connect _WIRE_6.bits.address, UInt<9>(0h0)
connect _WIRE_6.bits.source, UInt<1>(0h0)
connect _WIRE_6.bits.size, UInt<2>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_601 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<32>(0h0)
connect _WIRE_8.bits.address, UInt<9>(0h0)
connect _WIRE_8.bits.source, UInt<1>(0h0)
connect _WIRE_8.bits.size, UInt<2>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_602 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_603 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_604 = and(_T_602, _T_603)
node _T_605 = and(_T_601, _T_604)
when _T_605 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<9>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<32>(0h0)
connect _WIRE_10.bits.address, UInt<9>(0h0)
connect _WIRE_10.bits.source, UInt<1>(0h0)
connect _WIRE_10.bits.size, UInt<2>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_606 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_607 = and(_T_606, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<32>(0h0)
connect _WIRE_12.bits.address, UInt<9>(0h0)
connect _WIRE_12.bits.source, UInt<1>(0h0)
connect _WIRE_12.bits.size, UInt<2>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_608 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_609 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_610 = and(_T_608, _T_609)
node _T_611 = and(_T_607, _T_610)
when _T_611 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_set_WIRE.bits.address, UInt<9>(0h0)
connect _c_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<9>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<9>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<9>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<9>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<32>(0h0)
connect _WIRE_14.bits.address, UInt<9>(0h0)
connect _WIRE_14.bits.source, UInt<1>(0h0)
connect _WIRE_14.bits.size, UInt<2>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_612 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_613 = bits(_T_612, 0, 0)
node _T_614 = eq(_T_613, UInt<1>(0h0))
node _T_615 = asUInt(reset)
node _T_616 = eq(_T_615, UInt<1>(0h0))
when _T_616 :
node _T_617 = eq(_T_614, UInt<1>(0h0))
when _T_617 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_614, UInt<1>(0h1), "") : assert_106
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<9>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<9>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<1>
connect d_clr_1, UInt<1>(0h0)
wire d_clr_wo_ready_1 : UInt<1>
connect d_clr_wo_ready_1, UInt<1>(0h0)
wire d_opcodes_clr_1 : UInt<4>
connect d_opcodes_clr_1, UInt<4>(0h0)
wire d_sizes_clr_1 : UInt<4>
connect d_sizes_clr_1, UInt<4>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_618 = and(io.in.d.valid, d_first_2)
node _T_619 = and(_T_618, UInt<1>(0h1))
node _T_620 = and(_T_619, d_release_ack_1)
when _T_620 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_621 = and(io.in.d.ready, io.in.d.valid)
node _T_622 = and(_T_621, d_first_2)
node _T_623 = and(_T_622, UInt<1>(0h1))
node _T_624 = and(_T_623, d_release_ack_1)
when _T_624 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_625 = and(io.in.d.valid, d_first_2)
node _T_626 = and(_T_625, UInt<1>(0h1))
node _T_627 = and(_T_626, d_release_ack_1)
when _T_627 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<9>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<9>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<9>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_628 = dshr(inflight_1, io.in.d.bits.source)
node _T_629 = bits(_T_628, 0, 0)
node _T_630 = or(_T_629, same_cycle_resp_1)
node _T_631 = asUInt(reset)
node _T_632 = eq(_T_631, UInt<1>(0h0))
when _T_632 :
node _T_633 = eq(_T_630, UInt<1>(0h0))
when _T_633 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107
assert(clock, _T_630, UInt<1>(0h1), "") : assert_107
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<32>(0h0)
connect _WIRE_16.bits.address, UInt<9>(0h0)
connect _WIRE_16.bits.source, UInt<1>(0h0)
connect _WIRE_16.bits.size, UInt<2>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_634 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_635 = asUInt(reset)
node _T_636 = eq(_T_635, UInt<1>(0h0))
when _T_636 :
node _T_637 = eq(_T_634, UInt<1>(0h0))
when _T_637 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_634, UInt<1>(0h1), "") : assert_108
else :
node _T_638 = eq(io.in.d.bits.size, c_size_lookup)
node _T_639 = asUInt(reset)
node _T_640 = eq(_T_639, UInt<1>(0h0))
when _T_640 :
node _T_641 = eq(_T_638, UInt<1>(0h0))
when _T_641 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_638, UInt<1>(0h1), "") : assert_109
node _T_642 = and(io.in.d.valid, d_first_2)
node _T_643 = and(_T_642, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<32>(0h0)
connect _WIRE_18.bits.address, UInt<9>(0h0)
connect _WIRE_18.bits.source, UInt<1>(0h0)
connect _WIRE_18.bits.size, UInt<2>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_644 = and(_T_643, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<32>(0h0)
connect _WIRE_20.bits.address, UInt<9>(0h0)
connect _WIRE_20.bits.source, UInt<1>(0h0)
connect _WIRE_20.bits.size, UInt<2>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_645 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_646 = and(_T_644, _T_645)
node _T_647 = and(_T_646, d_release_ack_1)
node _T_648 = eq(c_probe_ack, UInt<1>(0h0))
node _T_649 = and(_T_647, _T_648)
when _T_649 :
node _T_650 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<32>(0h0)
connect _WIRE_22.bits.address, UInt<9>(0h0)
connect _WIRE_22.bits.source, UInt<1>(0h0)
connect _WIRE_22.bits.size, UInt<2>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_651 = or(_T_650, _WIRE_23.ready)
node _T_652 = asUInt(reset)
node _T_653 = eq(_T_652, UInt<1>(0h0))
when _T_653 :
node _T_654 = eq(_T_651, UInt<1>(0h0))
when _T_654 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_651, UInt<1>(0h1), "") : assert_110
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_92
node _T_655 = orr(inflight_1)
node _T_656 = eq(_T_655, UInt<1>(0h0))
node _T_657 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_658 = or(_T_656, _T_657)
node _T_659 = lt(watchdog_1, plusarg_reader_1.out)
node _T_660 = or(_T_658, _T_659)
node _T_661 = asUInt(reset)
node _T_662 = eq(_T_661, UInt<1>(0h0))
when _T_662 :
node _T_663 = eq(_T_660, UInt<1>(0h0))
when _T_663 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_660, UInt<1>(0h1), "") : assert_111
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<32>(0h0)
connect _WIRE_24.bits.address, UInt<9>(0h0)
connect _WIRE_24.bits.source, UInt<1>(0h0)
connect _WIRE_24.bits.size, UInt<2>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_664 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_665 = and(io.in.d.ready, io.in.d.valid)
node _T_666 = or(_T_664, _T_665)
when _T_666 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_45( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [8:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [8:0] address; // @[Monitor.scala:391:22]
reg d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [1:0] inflight; // @[Monitor.scala:614:27]
reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [3:0] inflight_sizes; // @[Monitor.scala:618:33]
reg a_first_counter_1; // @[Edges.scala:229:27]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire a_set = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [1:0] inflight_1; // @[Monitor.scala:726:35]
reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg d_first_counter_2; // @[Edges.scala:229:27]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_94 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_94( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_121 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_121( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_171 :
output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node rawIn_exp = bits(io.in, 31, 23)
node _rawIn_isZero_T = bits(rawIn_exp, 8, 6)
node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0))
node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7)
node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3))
wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T)
connect rawIn.isNaN, _rawIn_out_isNaN_T_1
node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0))
node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1)
connect rawIn.isInf, _rawIn_out_isInf_T_2
connect rawIn.isZero, rawIn_isZero
node _rawIn_out_sign_T = bits(io.in, 32, 32)
connect rawIn.sign, _rawIn_out_sign_T
node _rawIn_out_sExp_T = cvt(rawIn_exp)
connect rawIn.sExp, _rawIn_out_sExp_T
node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0))
node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T)
node _rawIn_out_sig_T_2 = bits(io.in, 22, 0)
node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2)
connect rawIn.sig, _rawIn_out_sig_T_3
node _io_out_T = shl(io.in, 0)
connect io.out, _io_out_T
node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22)
node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0))
node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0))
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RecFNToRecFN_171( // @[RecFNToRecFN.scala:44:5]
input [32:0] io_in, // @[RecFNToRecFN.scala:48:16]
output [32:0] io_out // @[RecFNToRecFN.scala:48:16]
);
wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5]
wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35]
wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54]
wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5]
wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5]
wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35]
wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}]
wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46]
assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54]
assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a32d64s3k3z4c :
input clock : Clock
input reset : Reset
output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}}
wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}
invalidate nodeIn.e.bits.sink
invalidate nodeIn.e.valid
invalidate nodeIn.e.ready
invalidate nodeIn.d.bits.corrupt
invalidate nodeIn.d.bits.data
invalidate nodeIn.d.bits.denied
invalidate nodeIn.d.bits.sink
invalidate nodeIn.d.bits.source
invalidate nodeIn.d.bits.size
invalidate nodeIn.d.bits.param
invalidate nodeIn.d.bits.opcode
invalidate nodeIn.d.valid
invalidate nodeIn.d.ready
invalidate nodeIn.c.bits.corrupt
invalidate nodeIn.c.bits.data
invalidate nodeIn.c.bits.address
invalidate nodeIn.c.bits.source
invalidate nodeIn.c.bits.size
invalidate nodeIn.c.bits.param
invalidate nodeIn.c.bits.opcode
invalidate nodeIn.c.valid
invalidate nodeIn.c.ready
invalidate nodeIn.b.bits.corrupt
invalidate nodeIn.b.bits.data
invalidate nodeIn.b.bits.mask
invalidate nodeIn.b.bits.address
invalidate nodeIn.b.bits.source
invalidate nodeIn.b.bits.size
invalidate nodeIn.b.bits.param
invalidate nodeIn.b.bits.opcode
invalidate nodeIn.b.valid
invalidate nodeIn.b.ready
invalidate nodeIn.a.bits.corrupt
invalidate nodeIn.a.bits.data
invalidate nodeIn.a.bits.mask
invalidate nodeIn.a.bits.address
invalidate nodeIn.a.bits.source
invalidate nodeIn.a.bits.size
invalidate nodeIn.a.bits.param
invalidate nodeIn.a.bits.opcode
invalidate nodeIn.a.valid
invalidate nodeIn.a.ready
inst monitor of TLMonitor_40
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.e.bits.sink, nodeIn.e.bits.sink
connect monitor.io.in.e.valid, nodeIn.e.valid
connect monitor.io.in.e.ready, nodeIn.e.ready
connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, nodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, nodeIn.d.bits.source
connect monitor.io.in.d.bits.size, nodeIn.d.bits.size
connect monitor.io.in.d.bits.param, nodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode
connect monitor.io.in.d.valid, nodeIn.d.valid
connect monitor.io.in.d.ready, nodeIn.d.ready
connect monitor.io.in.c.bits.corrupt, nodeIn.c.bits.corrupt
connect monitor.io.in.c.bits.data, nodeIn.c.bits.data
connect monitor.io.in.c.bits.address, nodeIn.c.bits.address
connect monitor.io.in.c.bits.source, nodeIn.c.bits.source
connect monitor.io.in.c.bits.size, nodeIn.c.bits.size
connect monitor.io.in.c.bits.param, nodeIn.c.bits.param
connect monitor.io.in.c.bits.opcode, nodeIn.c.bits.opcode
connect monitor.io.in.c.valid, nodeIn.c.valid
connect monitor.io.in.c.ready, nodeIn.c.ready
connect monitor.io.in.b.bits.corrupt, nodeIn.b.bits.corrupt
connect monitor.io.in.b.bits.data, nodeIn.b.bits.data
connect monitor.io.in.b.bits.mask, nodeIn.b.bits.mask
connect monitor.io.in.b.bits.address, nodeIn.b.bits.address
connect monitor.io.in.b.bits.source, nodeIn.b.bits.source
connect monitor.io.in.b.bits.size, nodeIn.b.bits.size
connect monitor.io.in.b.bits.param, nodeIn.b.bits.param
connect monitor.io.in.b.bits.opcode, nodeIn.b.bits.opcode
connect monitor.io.in.b.valid, nodeIn.b.valid
connect monitor.io.in.b.ready, nodeIn.b.ready
connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, nodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, nodeIn.a.bits.address
connect monitor.io.in.a.bits.source, nodeIn.a.bits.source
connect monitor.io.in.a.bits.size, nodeIn.a.bits.size
connect monitor.io.in.a.bits.param, nodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode
connect monitor.io.in.a.valid, nodeIn.a.valid
connect monitor.io.in.a.ready, nodeIn.a.ready
wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}
invalidate nodeOut.e.bits.sink
invalidate nodeOut.e.valid
invalidate nodeOut.e.ready
invalidate nodeOut.d.bits.corrupt
invalidate nodeOut.d.bits.data
invalidate nodeOut.d.bits.denied
invalidate nodeOut.d.bits.sink
invalidate nodeOut.d.bits.source
invalidate nodeOut.d.bits.size
invalidate nodeOut.d.bits.param
invalidate nodeOut.d.bits.opcode
invalidate nodeOut.d.valid
invalidate nodeOut.d.ready
invalidate nodeOut.c.bits.corrupt
invalidate nodeOut.c.bits.data
invalidate nodeOut.c.bits.address
invalidate nodeOut.c.bits.source
invalidate nodeOut.c.bits.size
invalidate nodeOut.c.bits.param
invalidate nodeOut.c.bits.opcode
invalidate nodeOut.c.valid
invalidate nodeOut.c.ready
invalidate nodeOut.b.bits.corrupt
invalidate nodeOut.b.bits.data
invalidate nodeOut.b.bits.mask
invalidate nodeOut.b.bits.address
invalidate nodeOut.b.bits.source
invalidate nodeOut.b.bits.size
invalidate nodeOut.b.bits.param
invalidate nodeOut.b.bits.opcode
invalidate nodeOut.b.valid
invalidate nodeOut.b.ready
invalidate nodeOut.a.bits.corrupt
invalidate nodeOut.a.bits.data
invalidate nodeOut.a.bits.mask
invalidate nodeOut.a.bits.address
invalidate nodeOut.a.bits.source
invalidate nodeOut.a.bits.size
invalidate nodeOut.a.bits.param
invalidate nodeOut.a.bits.opcode
invalidate nodeOut.a.valid
invalidate nodeOut.a.ready
connect auto.out, nodeOut
connect nodeIn, auto.in
inst nodeOut_a_q of Queue2_TLBundleA_a32d64s3k3z4c
connect nodeOut_a_q.clock, clock
connect nodeOut_a_q.reset, reset
connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid
connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt
connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data
connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask
connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address
connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source
connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size
connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param
connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode
connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready
connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits
connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid
connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready
inst nodeIn_d_q of Queue2_TLBundleD_a32d64s3k3z4c
connect nodeIn_d_q.clock, clock
connect nodeIn_d_q.reset, reset
connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid
connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt
connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data
connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied
connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink
connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source
connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size
connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param
connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode
connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready
connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits
connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid
connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready
inst nodeIn_b_q of Queue2_TLBundleB_a32d64s3k3z4c
connect nodeIn_b_q.clock, clock
connect nodeIn_b_q.reset, reset
connect nodeIn_b_q.io.enq.valid, nodeOut.b.valid
connect nodeIn_b_q.io.enq.bits.corrupt, nodeOut.b.bits.corrupt
connect nodeIn_b_q.io.enq.bits.data, nodeOut.b.bits.data
connect nodeIn_b_q.io.enq.bits.mask, nodeOut.b.bits.mask
connect nodeIn_b_q.io.enq.bits.address, nodeOut.b.bits.address
connect nodeIn_b_q.io.enq.bits.source, nodeOut.b.bits.source
connect nodeIn_b_q.io.enq.bits.size, nodeOut.b.bits.size
connect nodeIn_b_q.io.enq.bits.param, nodeOut.b.bits.param
connect nodeIn_b_q.io.enq.bits.opcode, nodeOut.b.bits.opcode
connect nodeOut.b.ready, nodeIn_b_q.io.enq.ready
connect nodeIn.b.bits, nodeIn_b_q.io.deq.bits
connect nodeIn.b.valid, nodeIn_b_q.io.deq.valid
connect nodeIn_b_q.io.deq.ready, nodeIn.b.ready
inst nodeOut_c_q of Queue2_TLBundleC_a32d64s3k3z4c
connect nodeOut_c_q.clock, clock
connect nodeOut_c_q.reset, reset
connect nodeOut_c_q.io.enq.valid, nodeIn.c.valid
connect nodeOut_c_q.io.enq.bits.corrupt, nodeIn.c.bits.corrupt
connect nodeOut_c_q.io.enq.bits.data, nodeIn.c.bits.data
connect nodeOut_c_q.io.enq.bits.address, nodeIn.c.bits.address
connect nodeOut_c_q.io.enq.bits.source, nodeIn.c.bits.source
connect nodeOut_c_q.io.enq.bits.size, nodeIn.c.bits.size
connect nodeOut_c_q.io.enq.bits.param, nodeIn.c.bits.param
connect nodeOut_c_q.io.enq.bits.opcode, nodeIn.c.bits.opcode
connect nodeIn.c.ready, nodeOut_c_q.io.enq.ready
connect nodeOut.c.bits, nodeOut_c_q.io.deq.bits
connect nodeOut.c.valid, nodeOut_c_q.io.deq.valid
connect nodeOut_c_q.io.deq.ready, nodeOut.c.ready
inst nodeOut_e_q of Queue2_TLBundleE_a32d64s3k3z4c
connect nodeOut_e_q.clock, clock
connect nodeOut_e_q.reset, reset
connect nodeOut_e_q.io.enq.valid, nodeIn.e.valid
connect nodeOut_e_q.io.enq.bits.sink, nodeIn.e.bits.sink
connect nodeIn.e.ready, nodeOut_e_q.io.enq.ready
connect nodeOut.e.bits, nodeOut_e_q.io.deq.bits
connect nodeOut.e.valid, nodeOut_e_q.io.deq.valid
connect nodeOut_e_q.io.deq.ready, nodeOut.e.ready
extmodule plusarg_reader_82 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_83 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLBuffer_a32d64s3k3z4c( // @[Buffer.scala:40:9]
input clock, // @[Buffer.scala:40:9]
input reset, // @[Buffer.scala:40:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_b_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_b_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_b_bits_size, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_b_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_in_b_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_in_b_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_b_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_c_bits_size, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_e_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_e_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_e_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_b_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_b_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_b_bits_size, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_b_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_out_b_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_out_b_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_b_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_c_bits_size, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_e_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_e_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_e_bits_sink // @[LazyModuleImp.scala:107:25]
);
wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9]
wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9]
wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9]
wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9]
wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9]
wire auto_in_b_ready_0 = auto_in_b_ready; // @[Buffer.scala:40:9]
wire auto_in_c_valid_0 = auto_in_c_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_in_c_bits_opcode_0 = auto_in_c_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] auto_in_c_bits_param_0 = auto_in_c_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_in_c_bits_size_0 = auto_in_c_bits_size; // @[Buffer.scala:40:9]
wire [2:0] auto_in_c_bits_source_0 = auto_in_c_bits_source; // @[Buffer.scala:40:9]
wire [31:0] auto_in_c_bits_address_0 = auto_in_c_bits_address; // @[Buffer.scala:40:9]
wire [63:0] auto_in_c_bits_data_0 = auto_in_c_bits_data; // @[Buffer.scala:40:9]
wire auto_in_c_bits_corrupt_0 = auto_in_c_bits_corrupt; // @[Buffer.scala:40:9]
wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9]
wire auto_in_e_valid_0 = auto_in_e_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_in_e_bits_sink_0 = auto_in_e_bits_sink; // @[Buffer.scala:40:9]
wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9]
wire auto_out_b_valid_0 = auto_out_b_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_out_b_bits_opcode_0 = auto_out_b_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] auto_out_b_bits_param_0 = auto_out_b_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_out_b_bits_size_0 = auto_out_b_bits_size; // @[Buffer.scala:40:9]
wire [2:0] auto_out_b_bits_source_0 = auto_out_b_bits_source; // @[Buffer.scala:40:9]
wire [31:0] auto_out_b_bits_address_0 = auto_out_b_bits_address; // @[Buffer.scala:40:9]
wire [7:0] auto_out_b_bits_mask_0 = auto_out_b_bits_mask; // @[Buffer.scala:40:9]
wire [63:0] auto_out_b_bits_data_0 = auto_out_b_bits_data; // @[Buffer.scala:40:9]
wire auto_out_b_bits_corrupt_0 = auto_out_b_bits_corrupt; // @[Buffer.scala:40:9]
wire auto_out_c_ready_0 = auto_out_c_ready; // @[Buffer.scala:40:9]
wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9]
wire [2:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9]
wire [2:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9]
wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9]
wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9]
wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9]
wire auto_out_e_ready_0 = auto_out_e_ready; // @[Buffer.scala:40:9]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9]
wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9]
wire nodeIn_b_ready = auto_in_b_ready_0; // @[Buffer.scala:40:9]
wire nodeIn_b_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_b_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_b_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_b_bits_size; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_b_bits_source; // @[MixedNode.scala:551:17]
wire [31:0] nodeIn_b_bits_address; // @[MixedNode.scala:551:17]
wire [7:0] nodeIn_b_bits_mask; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_b_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_b_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeIn_c_ready; // @[MixedNode.scala:551:17]
wire nodeIn_c_valid = auto_in_c_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_c_bits_opcode = auto_in_c_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_c_bits_param = auto_in_c_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeIn_c_bits_size = auto_in_c_bits_size_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_c_bits_source = auto_in_c_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] nodeIn_c_bits_address = auto_in_c_bits_address_0; // @[Buffer.scala:40:9]
wire [63:0] nodeIn_c_bits_data = auto_in_c_bits_data_0; // @[Buffer.scala:40:9]
wire nodeIn_c_bits_corrupt = auto_in_c_bits_corrupt_0; // @[Buffer.scala:40:9]
wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeIn_e_ready; // @[MixedNode.scala:551:17]
wire nodeIn_e_valid = auto_in_e_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_e_bits_sink = auto_in_e_bits_sink_0; // @[Buffer.scala:40:9]
wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_b_ready; // @[MixedNode.scala:542:17]
wire nodeOut_b_valid = auto_out_b_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_b_bits_opcode = auto_out_b_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] nodeOut_b_bits_param = auto_out_b_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeOut_b_bits_size = auto_out_b_bits_size_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_b_bits_source = auto_out_b_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] nodeOut_b_bits_address = auto_out_b_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] nodeOut_b_bits_mask = auto_out_b_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] nodeOut_b_bits_data = auto_out_b_bits_data_0; // @[Buffer.scala:40:9]
wire nodeOut_b_bits_corrupt = auto_out_b_bits_corrupt_0; // @[Buffer.scala:40:9]
wire nodeOut_c_ready = auto_out_c_ready_0; // @[Buffer.scala:40:9]
wire nodeOut_c_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_c_bits_size; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_c_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_c_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire nodeOut_e_ready = auto_out_e_ready_0; // @[Buffer.scala:40:9]
wire nodeOut_e_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire auto_in_a_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_b_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] auto_in_b_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_in_b_bits_size_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_b_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] auto_in_b_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] auto_in_b_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] auto_in_b_bits_data_0; // @[Buffer.scala:40:9]
wire auto_in_b_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_b_valid_0; // @[Buffer.scala:40:9]
wire auto_in_c_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_d_valid_0; // @[Buffer.scala:40:9]
wire auto_in_e_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_out_a_valid_0; // @[Buffer.scala:40:9]
wire auto_out_b_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_c_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_out_c_bits_size_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_c_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] auto_out_c_bits_address_0; // @[Buffer.scala:40:9]
wire [63:0] auto_out_c_bits_data_0; // @[Buffer.scala:40:9]
wire auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_out_c_valid_0; // @[Buffer.scala:40:9]
wire auto_out_d_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_e_bits_sink_0; // @[Buffer.scala:40:9]
wire auto_out_e_valid_0; // @[Buffer.scala:40:9]
assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9]
assign auto_in_b_valid_0 = nodeIn_b_valid; // @[Buffer.scala:40:9]
assign auto_in_b_bits_opcode_0 = nodeIn_b_bits_opcode; // @[Buffer.scala:40:9]
assign auto_in_b_bits_param_0 = nodeIn_b_bits_param; // @[Buffer.scala:40:9]
assign auto_in_b_bits_size_0 = nodeIn_b_bits_size; // @[Buffer.scala:40:9]
assign auto_in_b_bits_source_0 = nodeIn_b_bits_source; // @[Buffer.scala:40:9]
assign auto_in_b_bits_address_0 = nodeIn_b_bits_address; // @[Buffer.scala:40:9]
assign auto_in_b_bits_mask_0 = nodeIn_b_bits_mask; // @[Buffer.scala:40:9]
assign auto_in_b_bits_data_0 = nodeIn_b_bits_data; // @[Buffer.scala:40:9]
assign auto_in_b_bits_corrupt_0 = nodeIn_b_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_in_c_ready_0 = nodeIn_c_ready; // @[Buffer.scala:40:9]
assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_in_e_ready_0 = nodeIn_e_ready; // @[Buffer.scala:40:9]
assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_b_ready_0 = nodeOut_b_ready; // @[Buffer.scala:40:9]
assign auto_out_c_valid_0 = nodeOut_c_valid; // @[Buffer.scala:40:9]
assign auto_out_c_bits_opcode_0 = nodeOut_c_bits_opcode; // @[Buffer.scala:40:9]
assign auto_out_c_bits_param_0 = nodeOut_c_bits_param; // @[Buffer.scala:40:9]
assign auto_out_c_bits_size_0 = nodeOut_c_bits_size; // @[Buffer.scala:40:9]
assign auto_out_c_bits_source_0 = nodeOut_c_bits_source; // @[Buffer.scala:40:9]
assign auto_out_c_bits_address_0 = nodeOut_c_bits_address; // @[Buffer.scala:40:9]
assign auto_out_c_bits_data_0 = nodeOut_c_bits_data; // @[Buffer.scala:40:9]
assign auto_out_c_bits_corrupt_0 = nodeOut_c_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9]
assign auto_out_e_valid_0 = nodeOut_e_valid; // @[Buffer.scala:40:9]
assign auto_out_e_bits_sink_0 = nodeOut_e_bits_sink; // @[Buffer.scala:40:9]
TLMonitor_40 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_b_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17]
.io_in_b_valid (nodeIn_b_valid), // @[MixedNode.scala:551:17]
.io_in_b_bits_opcode (nodeIn_b_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_b_bits_param (nodeIn_b_bits_param), // @[MixedNode.scala:551:17]
.io_in_b_bits_size (nodeIn_b_bits_size), // @[MixedNode.scala:551:17]
.io_in_b_bits_source (nodeIn_b_bits_source), // @[MixedNode.scala:551:17]
.io_in_b_bits_address (nodeIn_b_bits_address), // @[MixedNode.scala:551:17]
.io_in_b_bits_mask (nodeIn_b_bits_mask), // @[MixedNode.scala:551:17]
.io_in_b_bits_data (nodeIn_b_bits_data), // @[MixedNode.scala:551:17]
.io_in_b_bits_corrupt (nodeIn_b_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_c_ready (nodeIn_c_ready), // @[MixedNode.scala:551:17]
.io_in_c_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17]
.io_in_c_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_c_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17]
.io_in_c_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17]
.io_in_c_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17]
.io_in_c_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17]
.io_in_c_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17]
.io_in_c_bits_corrupt (nodeIn_c_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (nodeIn_d_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_e_ready (nodeIn_e_ready), // @[MixedNode.scala:551:17]
.io_in_e_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17]
.io_in_e_bits_sink (nodeIn_e_bits_sink) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
Queue2_TLBundleA_a32d64s3k3z4c nodeOut_a_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_a_ready),
.io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17]
.io_deq_valid (nodeOut_a_valid),
.io_deq_bits_opcode (nodeOut_a_bits_opcode),
.io_deq_bits_param (nodeOut_a_bits_param),
.io_deq_bits_size (nodeOut_a_bits_size),
.io_deq_bits_source (nodeOut_a_bits_source),
.io_deq_bits_address (nodeOut_a_bits_address),
.io_deq_bits_mask (nodeOut_a_bits_mask),
.io_deq_bits_data (nodeOut_a_bits_data),
.io_deq_bits_corrupt (nodeOut_a_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleD_a32d64s3k3z4c nodeIn_d_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeOut_d_ready),
.io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17]
.io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17]
.io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17]
.io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17]
.io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17]
.io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17]
.io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17]
.io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17]
.io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17]
.io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_deq_valid (nodeIn_d_valid),
.io_deq_bits_opcode (nodeIn_d_bits_opcode),
.io_deq_bits_param (nodeIn_d_bits_param),
.io_deq_bits_size (nodeIn_d_bits_size),
.io_deq_bits_source (nodeIn_d_bits_source),
.io_deq_bits_sink (nodeIn_d_bits_sink),
.io_deq_bits_denied (nodeIn_d_bits_denied),
.io_deq_bits_data (nodeIn_d_bits_data),
.io_deq_bits_corrupt (nodeIn_d_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleB_a32d64s3k3z4c nodeIn_b_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeOut_b_ready),
.io_enq_valid (nodeOut_b_valid), // @[MixedNode.scala:542:17]
.io_enq_bits_opcode (nodeOut_b_bits_opcode), // @[MixedNode.scala:542:17]
.io_enq_bits_param (nodeOut_b_bits_param), // @[MixedNode.scala:542:17]
.io_enq_bits_size (nodeOut_b_bits_size), // @[MixedNode.scala:542:17]
.io_enq_bits_source (nodeOut_b_bits_source), // @[MixedNode.scala:542:17]
.io_enq_bits_address (nodeOut_b_bits_address), // @[MixedNode.scala:542:17]
.io_enq_bits_mask (nodeOut_b_bits_mask), // @[MixedNode.scala:542:17]
.io_enq_bits_data (nodeOut_b_bits_data), // @[MixedNode.scala:542:17]
.io_enq_bits_corrupt (nodeOut_b_bits_corrupt), // @[MixedNode.scala:542:17]
.io_deq_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17]
.io_deq_valid (nodeIn_b_valid),
.io_deq_bits_opcode (nodeIn_b_bits_opcode),
.io_deq_bits_param (nodeIn_b_bits_param),
.io_deq_bits_size (nodeIn_b_bits_size),
.io_deq_bits_source (nodeIn_b_bits_source),
.io_deq_bits_address (nodeIn_b_bits_address),
.io_deq_bits_mask (nodeIn_b_bits_mask),
.io_deq_bits_data (nodeIn_b_bits_data),
.io_deq_bits_corrupt (nodeIn_b_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleC_a32d64s3k3z4c nodeOut_c_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_c_ready),
.io_enq_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17]
.io_enq_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17]
.io_enq_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17]
.io_enq_bits_corrupt (nodeIn_c_bits_corrupt), // @[MixedNode.scala:551:17]
.io_deq_ready (nodeOut_c_ready), // @[MixedNode.scala:542:17]
.io_deq_valid (nodeOut_c_valid),
.io_deq_bits_opcode (nodeOut_c_bits_opcode),
.io_deq_bits_param (nodeOut_c_bits_param),
.io_deq_bits_size (nodeOut_c_bits_size),
.io_deq_bits_source (nodeOut_c_bits_source),
.io_deq_bits_address (nodeOut_c_bits_address),
.io_deq_bits_data (nodeOut_c_bits_data),
.io_deq_bits_corrupt (nodeOut_c_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleE_a32d64s3k3z4c nodeOut_e_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_e_ready),
.io_enq_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_sink (nodeIn_e_bits_sink), // @[MixedNode.scala:551:17]
.io_deq_ready (nodeOut_e_ready), // @[MixedNode.scala:542:17]
.io_deq_valid (nodeOut_e_valid),
.io_deq_bits_sink (nodeOut_e_bits_sink)
); // @[Decoupled.scala:362:21]
assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9]
assign auto_in_b_valid = auto_in_b_valid_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_opcode = auto_in_b_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_param = auto_in_b_bits_param_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_size = auto_in_b_bits_size_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_source = auto_in_b_bits_source_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_address = auto_in_b_bits_address_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_mask = auto_in_b_bits_mask_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_data = auto_in_b_bits_data_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_corrupt = auto_in_b_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_in_c_ready = auto_in_c_ready_0; // @[Buffer.scala:40:9]
assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_in_e_ready = auto_in_e_ready_0; // @[Buffer.scala:40:9]
assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_b_ready = auto_out_b_ready_0; // @[Buffer.scala:40:9]
assign auto_out_c_valid = auto_out_c_valid_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_opcode = auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_param = auto_out_c_bits_param_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_size = auto_out_c_bits_size_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_source = auto_out_c_bits_source_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_address = auto_out_c_bits_address_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_data = auto_out_c_bits_data_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_corrupt = auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9]
assign auto_out_e_valid = auto_out_e_valid_0; // @[Buffer.scala:40:9]
assign auto_out_e_bits_sink = auto_out_e_bits_sink_0; // @[Buffer.scala:40:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_36 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 3, 0)
node _source_ok_T = shr(io.in.a.bits.source, 4)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<4>(0h9))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T_5
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits = bits(_uncommonBits_T, 3, 0)
node _T_4 = shr(io.in.a.bits.source, 4)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<4>(0h9))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_16, UInt<1>(0h1), "") : assert_1
node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_20 :
node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_23 = and(_T_21, _T_22)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 3, 0)
node _T_24 = shr(io.in.a.bits.source, 4)
node _T_25 = eq(_T_24, UInt<1>(0h0))
node _T_26 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_27 = and(_T_25, _T_26)
node _T_28 = leq(uncommonBits_1, UInt<4>(0h9))
node _T_29 = and(_T_27, _T_28)
node _T_30 = and(_T_23, _T_29)
node _T_31 = or(UInt<1>(0h0), _T_30)
node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_33 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_34 = cvt(_T_33)
node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000)))
node _T_36 = asSInt(_T_35)
node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0)))
node _T_38 = and(_T_32, _T_37)
node _T_39 = or(UInt<1>(0h0), _T_38)
node _T_40 = and(_T_31, _T_39)
node _T_41 = asUInt(reset)
node _T_42 = eq(_T_41, UInt<1>(0h0))
when _T_42 :
node _T_43 = eq(_T_40, UInt<1>(0h0))
when _T_43 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_40, UInt<1>(0h1), "") : assert_2
node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_46 = and(_T_44, _T_45)
node _T_47 = or(UInt<1>(0h0), _T_46)
node _T_48 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_49 = cvt(_T_48)
node _T_50 = and(_T_49, asSInt(UInt<17>(0h10000)))
node _T_51 = asSInt(_T_50)
node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0)))
node _T_53 = and(_T_47, _T_52)
node _T_54 = or(UInt<1>(0h0), _T_53)
node _T_55 = and(UInt<1>(0h0), _T_54)
node _T_56 = asUInt(reset)
node _T_57 = eq(_T_56, UInt<1>(0h0))
when _T_57 :
node _T_58 = eq(_T_55, UInt<1>(0h0))
when _T_58 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_55, UInt<1>(0h1), "") : assert_3
node _T_59 = asUInt(reset)
node _T_60 = eq(_T_59, UInt<1>(0h0))
when _T_60 :
node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_61 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_63 = asUInt(reset)
node _T_64 = eq(_T_63, UInt<1>(0h0))
when _T_64 :
node _T_65 = eq(_T_62, UInt<1>(0h0))
when _T_65 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_62, UInt<1>(0h1), "") : assert_5
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(is_aligned, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_70 = asUInt(reset)
node _T_71 = eq(_T_70, UInt<1>(0h0))
when _T_71 :
node _T_72 = eq(_T_69, UInt<1>(0h0))
when _T_72 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_69, UInt<1>(0h1), "") : assert_7
node _T_73 = not(io.in.a.bits.mask)
node _T_74 = eq(_T_73, UInt<1>(0h0))
node _T_75 = asUInt(reset)
node _T_76 = eq(_T_75, UInt<1>(0h0))
when _T_76 :
node _T_77 = eq(_T_74, UInt<1>(0h0))
when _T_77 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_74, UInt<1>(0h1), "") : assert_8
node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_79 = asUInt(reset)
node _T_80 = eq(_T_79, UInt<1>(0h0))
when _T_80 :
node _T_81 = eq(_T_78, UInt<1>(0h0))
when _T_81 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_78, UInt<1>(0h1), "") : assert_9
node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_82 :
node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_85 = and(_T_83, _T_84)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 3, 0)
node _T_86 = shr(io.in.a.bits.source, 4)
node _T_87 = eq(_T_86, UInt<1>(0h0))
node _T_88 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_89 = and(_T_87, _T_88)
node _T_90 = leq(uncommonBits_2, UInt<4>(0h9))
node _T_91 = and(_T_89, _T_90)
node _T_92 = and(_T_85, _T_91)
node _T_93 = or(UInt<1>(0h0), _T_92)
node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_95 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_96 = cvt(_T_95)
node _T_97 = and(_T_96, asSInt(UInt<17>(0h10000)))
node _T_98 = asSInt(_T_97)
node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = and(_T_94, _T_99)
node _T_101 = or(UInt<1>(0h0), _T_100)
node _T_102 = and(_T_93, _T_101)
node _T_103 = asUInt(reset)
node _T_104 = eq(_T_103, UInt<1>(0h0))
when _T_104 :
node _T_105 = eq(_T_102, UInt<1>(0h0))
when _T_105 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_102, UInt<1>(0h1), "") : assert_10
node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_108 = and(_T_106, _T_107)
node _T_109 = or(UInt<1>(0h0), _T_108)
node _T_110 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_111 = cvt(_T_110)
node _T_112 = and(_T_111, asSInt(UInt<17>(0h10000)))
node _T_113 = asSInt(_T_112)
node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0)))
node _T_115 = and(_T_109, _T_114)
node _T_116 = or(UInt<1>(0h0), _T_115)
node _T_117 = and(UInt<1>(0h0), _T_116)
node _T_118 = asUInt(reset)
node _T_119 = eq(_T_118, UInt<1>(0h0))
when _T_119 :
node _T_120 = eq(_T_117, UInt<1>(0h0))
when _T_120 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_117, UInt<1>(0h1), "") : assert_11
node _T_121 = asUInt(reset)
node _T_122 = eq(_T_121, UInt<1>(0h0))
when _T_122 :
node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_125 = asUInt(reset)
node _T_126 = eq(_T_125, UInt<1>(0h0))
when _T_126 :
node _T_127 = eq(_T_124, UInt<1>(0h0))
when _T_127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_124, UInt<1>(0h1), "") : assert_13
node _T_128 = asUInt(reset)
node _T_129 = eq(_T_128, UInt<1>(0h0))
when _T_129 :
node _T_130 = eq(is_aligned, UInt<1>(0h0))
when _T_130 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_132 = asUInt(reset)
node _T_133 = eq(_T_132, UInt<1>(0h0))
when _T_133 :
node _T_134 = eq(_T_131, UInt<1>(0h0))
when _T_134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_131, UInt<1>(0h1), "") : assert_15
node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_136 = asUInt(reset)
node _T_137 = eq(_T_136, UInt<1>(0h0))
when _T_137 :
node _T_138 = eq(_T_135, UInt<1>(0h0))
when _T_138 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_135, UInt<1>(0h1), "") : assert_16
node _T_139 = not(io.in.a.bits.mask)
node _T_140 = eq(_T_139, UInt<1>(0h0))
node _T_141 = asUInt(reset)
node _T_142 = eq(_T_141, UInt<1>(0h0))
when _T_142 :
node _T_143 = eq(_T_140, UInt<1>(0h0))
when _T_143 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_140, UInt<1>(0h1), "") : assert_17
node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_145 = asUInt(reset)
node _T_146 = eq(_T_145, UInt<1>(0h0))
when _T_146 :
node _T_147 = eq(_T_144, UInt<1>(0h0))
when _T_147 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_144, UInt<1>(0h1), "") : assert_18
node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_148 :
node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_151 = and(_T_149, _T_150)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 3, 0)
node _T_152 = shr(io.in.a.bits.source, 4)
node _T_153 = eq(_T_152, UInt<1>(0h0))
node _T_154 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_155 = and(_T_153, _T_154)
node _T_156 = leq(uncommonBits_3, UInt<4>(0h9))
node _T_157 = and(_T_155, _T_156)
node _T_158 = and(_T_151, _T_157)
node _T_159 = or(UInt<1>(0h0), _T_158)
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(_T_159, UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_159, UInt<1>(0h1), "") : assert_19
node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_164 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_165 = and(_T_163, _T_164)
node _T_166 = or(UInt<1>(0h0), _T_165)
node _T_167 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_168 = cvt(_T_167)
node _T_169 = and(_T_168, asSInt(UInt<17>(0h10000)))
node _T_170 = asSInt(_T_169)
node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0)))
node _T_172 = and(_T_166, _T_171)
node _T_173 = or(UInt<1>(0h0), _T_172)
node _T_174 = asUInt(reset)
node _T_175 = eq(_T_174, UInt<1>(0h0))
when _T_175 :
node _T_176 = eq(_T_173, UInt<1>(0h0))
when _T_176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_173, UInt<1>(0h1), "") : assert_20
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_180 = asUInt(reset)
node _T_181 = eq(_T_180, UInt<1>(0h0))
when _T_181 :
node _T_182 = eq(is_aligned, UInt<1>(0h0))
when _T_182 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_183, UInt<1>(0h1), "") : assert_23
node _T_187 = eq(io.in.a.bits.mask, mask)
node _T_188 = asUInt(reset)
node _T_189 = eq(_T_188, UInt<1>(0h0))
when _T_189 :
node _T_190 = eq(_T_187, UInt<1>(0h0))
when _T_190 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_187, UInt<1>(0h1), "") : assert_24
node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_192 = asUInt(reset)
node _T_193 = eq(_T_192, UInt<1>(0h0))
when _T_193 :
node _T_194 = eq(_T_191, UInt<1>(0h0))
when _T_194 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_191, UInt<1>(0h1), "") : assert_25
node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_195 :
node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_198 = and(_T_196, _T_197)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 3, 0)
node _T_199 = shr(io.in.a.bits.source, 4)
node _T_200 = eq(_T_199, UInt<1>(0h0))
node _T_201 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_202 = and(_T_200, _T_201)
node _T_203 = leq(uncommonBits_4, UInt<4>(0h9))
node _T_204 = and(_T_202, _T_203)
node _T_205 = and(_T_198, _T_204)
node _T_206 = or(UInt<1>(0h0), _T_205)
node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_208 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_209 = and(_T_207, _T_208)
node _T_210 = or(UInt<1>(0h0), _T_209)
node _T_211 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_212 = cvt(_T_211)
node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000)))
node _T_214 = asSInt(_T_213)
node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0)))
node _T_216 = and(_T_210, _T_215)
node _T_217 = or(UInt<1>(0h0), _T_216)
node _T_218 = and(_T_206, _T_217)
node _T_219 = asUInt(reset)
node _T_220 = eq(_T_219, UInt<1>(0h0))
when _T_220 :
node _T_221 = eq(_T_218, UInt<1>(0h0))
when _T_221 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_218, UInt<1>(0h1), "") : assert_26
node _T_222 = asUInt(reset)
node _T_223 = eq(_T_222, UInt<1>(0h0))
when _T_223 :
node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_225 = asUInt(reset)
node _T_226 = eq(_T_225, UInt<1>(0h0))
when _T_226 :
node _T_227 = eq(is_aligned, UInt<1>(0h0))
when _T_227 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_229 = asUInt(reset)
node _T_230 = eq(_T_229, UInt<1>(0h0))
when _T_230 :
node _T_231 = eq(_T_228, UInt<1>(0h0))
when _T_231 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_228, UInt<1>(0h1), "") : assert_29
node _T_232 = eq(io.in.a.bits.mask, mask)
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_232, UInt<1>(0h1), "") : assert_30
node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_236 :
node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_239 = and(_T_237, _T_238)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 3, 0)
node _T_240 = shr(io.in.a.bits.source, 4)
node _T_241 = eq(_T_240, UInt<1>(0h0))
node _T_242 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_243 = and(_T_241, _T_242)
node _T_244 = leq(uncommonBits_5, UInt<4>(0h9))
node _T_245 = and(_T_243, _T_244)
node _T_246 = and(_T_239, _T_245)
node _T_247 = or(UInt<1>(0h0), _T_246)
node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_249 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_250 = and(_T_248, _T_249)
node _T_251 = or(UInt<1>(0h0), _T_250)
node _T_252 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_253 = cvt(_T_252)
node _T_254 = and(_T_253, asSInt(UInt<17>(0h10000)))
node _T_255 = asSInt(_T_254)
node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0)))
node _T_257 = and(_T_251, _T_256)
node _T_258 = or(UInt<1>(0h0), _T_257)
node _T_259 = and(_T_247, _T_258)
node _T_260 = asUInt(reset)
node _T_261 = eq(_T_260, UInt<1>(0h0))
when _T_261 :
node _T_262 = eq(_T_259, UInt<1>(0h0))
when _T_262 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_259, UInt<1>(0h1), "") : assert_31
node _T_263 = asUInt(reset)
node _T_264 = eq(_T_263, UInt<1>(0h0))
when _T_264 :
node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_265 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_266 = asUInt(reset)
node _T_267 = eq(_T_266, UInt<1>(0h0))
when _T_267 :
node _T_268 = eq(is_aligned, UInt<1>(0h0))
when _T_268 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_270 = asUInt(reset)
node _T_271 = eq(_T_270, UInt<1>(0h0))
when _T_271 :
node _T_272 = eq(_T_269, UInt<1>(0h0))
when _T_272 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_269, UInt<1>(0h1), "") : assert_34
node _T_273 = not(mask)
node _T_274 = and(io.in.a.bits.mask, _T_273)
node _T_275 = eq(_T_274, UInt<1>(0h0))
node _T_276 = asUInt(reset)
node _T_277 = eq(_T_276, UInt<1>(0h0))
when _T_277 :
node _T_278 = eq(_T_275, UInt<1>(0h0))
when _T_278 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_275, UInt<1>(0h1), "") : assert_35
node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_279 :
node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_282 = and(_T_280, _T_281)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 3, 0)
node _T_283 = shr(io.in.a.bits.source, 4)
node _T_284 = eq(_T_283, UInt<1>(0h0))
node _T_285 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_286 = and(_T_284, _T_285)
node _T_287 = leq(uncommonBits_6, UInt<4>(0h9))
node _T_288 = and(_T_286, _T_287)
node _T_289 = and(_T_282, _T_288)
node _T_290 = or(UInt<1>(0h0), _T_289)
node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_292 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_293 = cvt(_T_292)
node _T_294 = and(_T_293, asSInt(UInt<17>(0h10000)))
node _T_295 = asSInt(_T_294)
node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0)))
node _T_297 = and(_T_291, _T_296)
node _T_298 = or(UInt<1>(0h0), _T_297)
node _T_299 = and(_T_290, _T_298)
node _T_300 = asUInt(reset)
node _T_301 = eq(_T_300, UInt<1>(0h0))
when _T_301 :
node _T_302 = eq(_T_299, UInt<1>(0h0))
when _T_302 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_299, UInt<1>(0h1), "") : assert_36
node _T_303 = asUInt(reset)
node _T_304 = eq(_T_303, UInt<1>(0h0))
when _T_304 :
node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_305 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_306 = asUInt(reset)
node _T_307 = eq(_T_306, UInt<1>(0h0))
when _T_307 :
node _T_308 = eq(is_aligned, UInt<1>(0h0))
when _T_308 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_310 = asUInt(reset)
node _T_311 = eq(_T_310, UInt<1>(0h0))
when _T_311 :
node _T_312 = eq(_T_309, UInt<1>(0h0))
when _T_312 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_309, UInt<1>(0h1), "") : assert_39
node _T_313 = eq(io.in.a.bits.mask, mask)
node _T_314 = asUInt(reset)
node _T_315 = eq(_T_314, UInt<1>(0h0))
when _T_315 :
node _T_316 = eq(_T_313, UInt<1>(0h0))
when _T_316 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_313, UInt<1>(0h1), "") : assert_40
node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_317 :
node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_320 = and(_T_318, _T_319)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 3, 0)
node _T_321 = shr(io.in.a.bits.source, 4)
node _T_322 = eq(_T_321, UInt<1>(0h0))
node _T_323 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_324 = and(_T_322, _T_323)
node _T_325 = leq(uncommonBits_7, UInt<4>(0h9))
node _T_326 = and(_T_324, _T_325)
node _T_327 = and(_T_320, _T_326)
node _T_328 = or(UInt<1>(0h0), _T_327)
node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_330 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_331 = cvt(_T_330)
node _T_332 = and(_T_331, asSInt(UInt<17>(0h10000)))
node _T_333 = asSInt(_T_332)
node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0)))
node _T_335 = and(_T_329, _T_334)
node _T_336 = or(UInt<1>(0h0), _T_335)
node _T_337 = and(_T_328, _T_336)
node _T_338 = asUInt(reset)
node _T_339 = eq(_T_338, UInt<1>(0h0))
when _T_339 :
node _T_340 = eq(_T_337, UInt<1>(0h0))
when _T_340 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_337, UInt<1>(0h1), "") : assert_41
node _T_341 = asUInt(reset)
node _T_342 = eq(_T_341, UInt<1>(0h0))
when _T_342 :
node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_343 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_344 = asUInt(reset)
node _T_345 = eq(_T_344, UInt<1>(0h0))
when _T_345 :
node _T_346 = eq(is_aligned, UInt<1>(0h0))
when _T_346 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_348 = asUInt(reset)
node _T_349 = eq(_T_348, UInt<1>(0h0))
when _T_349 :
node _T_350 = eq(_T_347, UInt<1>(0h0))
when _T_350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_347, UInt<1>(0h1), "") : assert_44
node _T_351 = eq(io.in.a.bits.mask, mask)
node _T_352 = asUInt(reset)
node _T_353 = eq(_T_352, UInt<1>(0h0))
when _T_353 :
node _T_354 = eq(_T_351, UInt<1>(0h0))
when _T_354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_351, UInt<1>(0h1), "") : assert_45
node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_355 :
node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_358 = and(_T_356, _T_357)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 3, 0)
node _T_359 = shr(io.in.a.bits.source, 4)
node _T_360 = eq(_T_359, UInt<1>(0h0))
node _T_361 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_362 = and(_T_360, _T_361)
node _T_363 = leq(uncommonBits_8, UInt<4>(0h9))
node _T_364 = and(_T_362, _T_363)
node _T_365 = and(_T_358, _T_364)
node _T_366 = or(UInt<1>(0h0), _T_365)
node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_368 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_369 = cvt(_T_368)
node _T_370 = and(_T_369, asSInt(UInt<17>(0h10000)))
node _T_371 = asSInt(_T_370)
node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0)))
node _T_373 = and(_T_367, _T_372)
node _T_374 = or(UInt<1>(0h0), _T_373)
node _T_375 = and(_T_366, _T_374)
node _T_376 = asUInt(reset)
node _T_377 = eq(_T_376, UInt<1>(0h0))
when _T_377 :
node _T_378 = eq(_T_375, UInt<1>(0h0))
when _T_378 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_375, UInt<1>(0h1), "") : assert_46
node _T_379 = asUInt(reset)
node _T_380 = eq(_T_379, UInt<1>(0h0))
when _T_380 :
node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_381 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_382 = asUInt(reset)
node _T_383 = eq(_T_382, UInt<1>(0h0))
when _T_383 :
node _T_384 = eq(is_aligned, UInt<1>(0h0))
when _T_384 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_386 = asUInt(reset)
node _T_387 = eq(_T_386, UInt<1>(0h0))
when _T_387 :
node _T_388 = eq(_T_385, UInt<1>(0h0))
when _T_388 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_385, UInt<1>(0h1), "") : assert_49
node _T_389 = eq(io.in.a.bits.mask, mask)
node _T_390 = asUInt(reset)
node _T_391 = eq(_T_390, UInt<1>(0h0))
when _T_391 :
node _T_392 = eq(_T_389, UInt<1>(0h0))
when _T_392 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_389, UInt<1>(0h1), "") : assert_50
node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_394 = asUInt(reset)
node _T_395 = eq(_T_394, UInt<1>(0h0))
when _T_395 :
node _T_396 = eq(_T_393, UInt<1>(0h0))
when _T_396 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_393, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(_T_397, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_397, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 3, 0)
node _source_ok_T_6 = shr(io.in.d.bits.source, 4)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<4>(0h9))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_11
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_401 :
node _T_402 = asUInt(reset)
node _T_403 = eq(_T_402, UInt<1>(0h0))
when _T_403 :
node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_404 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_406 = asUInt(reset)
node _T_407 = eq(_T_406, UInt<1>(0h0))
when _T_407 :
node _T_408 = eq(_T_405, UInt<1>(0h0))
when _T_408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_405, UInt<1>(0h1), "") : assert_54
node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_410 = asUInt(reset)
node _T_411 = eq(_T_410, UInt<1>(0h0))
when _T_411 :
node _T_412 = eq(_T_409, UInt<1>(0h0))
when _T_412 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_409, UInt<1>(0h1), "") : assert_55
node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_414 = asUInt(reset)
node _T_415 = eq(_T_414, UInt<1>(0h0))
when _T_415 :
node _T_416 = eq(_T_413, UInt<1>(0h0))
when _T_416 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_413, UInt<1>(0h1), "") : assert_56
node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_418 = asUInt(reset)
node _T_419 = eq(_T_418, UInt<1>(0h0))
when _T_419 :
node _T_420 = eq(_T_417, UInt<1>(0h0))
when _T_420 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_417, UInt<1>(0h1), "") : assert_57
node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_421 :
node _T_422 = asUInt(reset)
node _T_423 = eq(_T_422, UInt<1>(0h0))
when _T_423 :
node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_424 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_425 = asUInt(reset)
node _T_426 = eq(_T_425, UInt<1>(0h0))
when _T_426 :
node _T_427 = eq(sink_ok, UInt<1>(0h0))
when _T_427 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_429 = asUInt(reset)
node _T_430 = eq(_T_429, UInt<1>(0h0))
when _T_430 :
node _T_431 = eq(_T_428, UInt<1>(0h0))
when _T_431 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_428, UInt<1>(0h1), "") : assert_60
node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_433 = asUInt(reset)
node _T_434 = eq(_T_433, UInt<1>(0h0))
when _T_434 :
node _T_435 = eq(_T_432, UInt<1>(0h0))
when _T_435 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_432, UInt<1>(0h1), "") : assert_61
node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_437 = asUInt(reset)
node _T_438 = eq(_T_437, UInt<1>(0h0))
when _T_438 :
node _T_439 = eq(_T_436, UInt<1>(0h0))
when _T_439 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_436, UInt<1>(0h1), "") : assert_62
node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_441 = asUInt(reset)
node _T_442 = eq(_T_441, UInt<1>(0h0))
when _T_442 :
node _T_443 = eq(_T_440, UInt<1>(0h0))
when _T_443 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_440, UInt<1>(0h1), "") : assert_63
node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_445 = or(UInt<1>(0h0), _T_444)
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_445, UInt<1>(0h1), "") : assert_64
node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_449 :
node _T_450 = asUInt(reset)
node _T_451 = eq(_T_450, UInt<1>(0h0))
when _T_451 :
node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_452 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(sink_ok, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_457 = asUInt(reset)
node _T_458 = eq(_T_457, UInt<1>(0h0))
when _T_458 :
node _T_459 = eq(_T_456, UInt<1>(0h0))
when _T_459 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_456, UInt<1>(0h1), "") : assert_67
node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_461 = asUInt(reset)
node _T_462 = eq(_T_461, UInt<1>(0h0))
when _T_462 :
node _T_463 = eq(_T_460, UInt<1>(0h0))
when _T_463 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_460, UInt<1>(0h1), "") : assert_68
node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_465 = asUInt(reset)
node _T_466 = eq(_T_465, UInt<1>(0h0))
when _T_466 :
node _T_467 = eq(_T_464, UInt<1>(0h0))
when _T_467 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_464, UInt<1>(0h1), "") : assert_69
node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_469 = or(_T_468, io.in.d.bits.corrupt)
node _T_470 = asUInt(reset)
node _T_471 = eq(_T_470, UInt<1>(0h0))
when _T_471 :
node _T_472 = eq(_T_469, UInt<1>(0h0))
when _T_472 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_469, UInt<1>(0h1), "") : assert_70
node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_474 = or(UInt<1>(0h0), _T_473)
node _T_475 = asUInt(reset)
node _T_476 = eq(_T_475, UInt<1>(0h0))
when _T_476 :
node _T_477 = eq(_T_474, UInt<1>(0h0))
when _T_477 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_474, UInt<1>(0h1), "") : assert_71
node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_478 :
node _T_479 = asUInt(reset)
node _T_480 = eq(_T_479, UInt<1>(0h0))
when _T_480 :
node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_481 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_483 = asUInt(reset)
node _T_484 = eq(_T_483, UInt<1>(0h0))
when _T_484 :
node _T_485 = eq(_T_482, UInt<1>(0h0))
when _T_485 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_482, UInt<1>(0h1), "") : assert_73
node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_487 = asUInt(reset)
node _T_488 = eq(_T_487, UInt<1>(0h0))
when _T_488 :
node _T_489 = eq(_T_486, UInt<1>(0h0))
when _T_489 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_486, UInt<1>(0h1), "") : assert_74
node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_491 = or(UInt<1>(0h0), _T_490)
node _T_492 = asUInt(reset)
node _T_493 = eq(_T_492, UInt<1>(0h0))
when _T_493 :
node _T_494 = eq(_T_491, UInt<1>(0h0))
when _T_494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_491, UInt<1>(0h1), "") : assert_75
node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_495 :
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_500 = asUInt(reset)
node _T_501 = eq(_T_500, UInt<1>(0h0))
when _T_501 :
node _T_502 = eq(_T_499, UInt<1>(0h0))
when _T_502 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_499, UInt<1>(0h1), "") : assert_77
node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_504 = or(_T_503, io.in.d.bits.corrupt)
node _T_505 = asUInt(reset)
node _T_506 = eq(_T_505, UInt<1>(0h0))
when _T_506 :
node _T_507 = eq(_T_504, UInt<1>(0h0))
when _T_507 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_504, UInt<1>(0h1), "") : assert_78
node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_509 = or(UInt<1>(0h0), _T_508)
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_T_509, UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_509, UInt<1>(0h1), "") : assert_79
node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_513 :
node _T_514 = asUInt(reset)
node _T_515 = eq(_T_514, UInt<1>(0h0))
when _T_515 :
node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_516 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_518 = asUInt(reset)
node _T_519 = eq(_T_518, UInt<1>(0h0))
when _T_519 :
node _T_520 = eq(_T_517, UInt<1>(0h0))
when _T_520 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_517, UInt<1>(0h1), "") : assert_81
node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_522 = asUInt(reset)
node _T_523 = eq(_T_522, UInt<1>(0h0))
when _T_523 :
node _T_524 = eq(_T_521, UInt<1>(0h0))
when _T_524 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_521, UInt<1>(0h1), "") : assert_82
node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_526 = or(UInt<1>(0h0), _T_525)
node _T_527 = asUInt(reset)
node _T_528 = eq(_T_527, UInt<1>(0h0))
when _T_528 :
node _T_529 = eq(_T_526, UInt<1>(0h0))
when _T_529 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_526, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<28>(0h0)
connect _WIRE.bits.source, UInt<4>(0h0)
connect _WIRE.bits.size, UInt<3>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_531 = asUInt(reset)
node _T_532 = eq(_T_531, UInt<1>(0h0))
when _T_532 :
node _T_533 = eq(_T_530, UInt<1>(0h0))
when _T_533 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_530, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<28>(0h0)
connect _WIRE_2.bits.source, UInt<4>(0h0)
connect _WIRE_2.bits.size, UInt<3>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_535 = asUInt(reset)
node _T_536 = eq(_T_535, UInt<1>(0h0))
when _T_536 :
node _T_537 = eq(_T_534, UInt<1>(0h0))
when _T_537 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_534, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_539 = asUInt(reset)
node _T_540 = eq(_T_539, UInt<1>(0h0))
when _T_540 :
node _T_541 = eq(_T_538, UInt<1>(0h0))
when _T_541 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_538, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_542 = eq(a_first, UInt<1>(0h0))
node _T_543 = and(io.in.a.valid, _T_542)
when _T_543 :
node _T_544 = eq(io.in.a.bits.opcode, opcode)
node _T_545 = asUInt(reset)
node _T_546 = eq(_T_545, UInt<1>(0h0))
when _T_546 :
node _T_547 = eq(_T_544, UInt<1>(0h0))
when _T_547 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_544, UInt<1>(0h1), "") : assert_87
node _T_548 = eq(io.in.a.bits.param, param)
node _T_549 = asUInt(reset)
node _T_550 = eq(_T_549, UInt<1>(0h0))
when _T_550 :
node _T_551 = eq(_T_548, UInt<1>(0h0))
when _T_551 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_548, UInt<1>(0h1), "") : assert_88
node _T_552 = eq(io.in.a.bits.size, size)
node _T_553 = asUInt(reset)
node _T_554 = eq(_T_553, UInt<1>(0h0))
when _T_554 :
node _T_555 = eq(_T_552, UInt<1>(0h0))
when _T_555 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_552, UInt<1>(0h1), "") : assert_89
node _T_556 = eq(io.in.a.bits.source, source)
node _T_557 = asUInt(reset)
node _T_558 = eq(_T_557, UInt<1>(0h0))
when _T_558 :
node _T_559 = eq(_T_556, UInt<1>(0h0))
when _T_559 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_556, UInt<1>(0h1), "") : assert_90
node _T_560 = eq(io.in.a.bits.address, address)
node _T_561 = asUInt(reset)
node _T_562 = eq(_T_561, UInt<1>(0h0))
when _T_562 :
node _T_563 = eq(_T_560, UInt<1>(0h0))
when _T_563 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_560, UInt<1>(0h1), "") : assert_91
node _T_564 = and(io.in.a.ready, io.in.a.valid)
node _T_565 = and(_T_564, a_first)
when _T_565 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_566 = eq(d_first, UInt<1>(0h0))
node _T_567 = and(io.in.d.valid, _T_566)
when _T_567 :
node _T_568 = eq(io.in.d.bits.opcode, opcode_1)
node _T_569 = asUInt(reset)
node _T_570 = eq(_T_569, UInt<1>(0h0))
when _T_570 :
node _T_571 = eq(_T_568, UInt<1>(0h0))
when _T_571 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_568, UInt<1>(0h1), "") : assert_92
node _T_572 = eq(io.in.d.bits.param, param_1)
node _T_573 = asUInt(reset)
node _T_574 = eq(_T_573, UInt<1>(0h0))
when _T_574 :
node _T_575 = eq(_T_572, UInt<1>(0h0))
when _T_575 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_572, UInt<1>(0h1), "") : assert_93
node _T_576 = eq(io.in.d.bits.size, size_1)
node _T_577 = asUInt(reset)
node _T_578 = eq(_T_577, UInt<1>(0h0))
when _T_578 :
node _T_579 = eq(_T_576, UInt<1>(0h0))
when _T_579 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_576, UInt<1>(0h1), "") : assert_94
node _T_580 = eq(io.in.d.bits.source, source_1)
node _T_581 = asUInt(reset)
node _T_582 = eq(_T_581, UInt<1>(0h0))
when _T_582 :
node _T_583 = eq(_T_580, UInt<1>(0h0))
when _T_583 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_580, UInt<1>(0h1), "") : assert_95
node _T_584 = eq(io.in.d.bits.sink, sink)
node _T_585 = asUInt(reset)
node _T_586 = eq(_T_585, UInt<1>(0h0))
when _T_586 :
node _T_587 = eq(_T_584, UInt<1>(0h0))
when _T_587 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_584, UInt<1>(0h1), "") : assert_96
node _T_588 = eq(io.in.d.bits.denied, denied)
node _T_589 = asUInt(reset)
node _T_590 = eq(_T_589, UInt<1>(0h0))
when _T_590 :
node _T_591 = eq(_T_588, UInt<1>(0h0))
when _T_591 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_588, UInt<1>(0h1), "") : assert_97
node _T_592 = and(io.in.d.ready, io.in.d.valid)
node _T_593 = and(_T_592, d_first)
when _T_593 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<10>, clock, reset, UInt<10>(0h0)
regreset inflight_opcodes : UInt<40>, clock, reset, UInt<40>(0h0)
regreset inflight_sizes : UInt<40>, clock, reset, UInt<40>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<10>
connect a_set, UInt<10>(0h0)
wire a_set_wo_ready : UInt<10>
connect a_set_wo_ready, UInt<10>(0h0)
wire a_opcodes_set : UInt<40>
connect a_opcodes_set, UInt<40>(0h0)
wire a_sizes_set : UInt<40>
connect a_sizes_set, UInt<40>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_594 = and(io.in.a.valid, a_first_1)
node _T_595 = and(_T_594, UInt<1>(0h1))
when _T_595 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_596 = and(io.in.a.ready, io.in.a.valid)
node _T_597 = and(_T_596, a_first_1)
node _T_598 = and(_T_597, UInt<1>(0h1))
when _T_598 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_599 = dshr(inflight, io.in.a.bits.source)
node _T_600 = bits(_T_599, 0, 0)
node _T_601 = eq(_T_600, UInt<1>(0h0))
node _T_602 = asUInt(reset)
node _T_603 = eq(_T_602, UInt<1>(0h0))
when _T_603 :
node _T_604 = eq(_T_601, UInt<1>(0h0))
when _T_604 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_601, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<10>
connect d_clr, UInt<10>(0h0)
wire d_clr_wo_ready : UInt<10>
connect d_clr_wo_ready, UInt<10>(0h0)
wire d_opcodes_clr : UInt<40>
connect d_opcodes_clr, UInt<40>(0h0)
wire d_sizes_clr : UInt<40>
connect d_sizes_clr, UInt<40>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_605 = and(io.in.d.valid, d_first_1)
node _T_606 = and(_T_605, UInt<1>(0h1))
node _T_607 = eq(d_release_ack, UInt<1>(0h0))
node _T_608 = and(_T_606, _T_607)
when _T_608 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_609 = and(io.in.d.ready, io.in.d.valid)
node _T_610 = and(_T_609, d_first_1)
node _T_611 = and(_T_610, UInt<1>(0h1))
node _T_612 = eq(d_release_ack, UInt<1>(0h0))
node _T_613 = and(_T_611, _T_612)
when _T_613 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_614 = and(io.in.d.valid, d_first_1)
node _T_615 = and(_T_614, UInt<1>(0h1))
node _T_616 = eq(d_release_ack, UInt<1>(0h0))
node _T_617 = and(_T_615, _T_616)
when _T_617 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_618 = dshr(inflight, io.in.d.bits.source)
node _T_619 = bits(_T_618, 0, 0)
node _T_620 = or(_T_619, same_cycle_resp)
node _T_621 = asUInt(reset)
node _T_622 = eq(_T_621, UInt<1>(0h0))
when _T_622 :
node _T_623 = eq(_T_620, UInt<1>(0h0))
when _T_623 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_620, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_626 = or(_T_624, _T_625)
node _T_627 = asUInt(reset)
node _T_628 = eq(_T_627, UInt<1>(0h0))
when _T_628 :
node _T_629 = eq(_T_626, UInt<1>(0h0))
when _T_629 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_626, UInt<1>(0h1), "") : assert_100
node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_631 = asUInt(reset)
node _T_632 = eq(_T_631, UInt<1>(0h0))
when _T_632 :
node _T_633 = eq(_T_630, UInt<1>(0h0))
when _T_633 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_630, UInt<1>(0h1), "") : assert_101
else :
node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_636 = or(_T_634, _T_635)
node _T_637 = asUInt(reset)
node _T_638 = eq(_T_637, UInt<1>(0h0))
when _T_638 :
node _T_639 = eq(_T_636, UInt<1>(0h0))
when _T_639 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_636, UInt<1>(0h1), "") : assert_102
node _T_640 = eq(io.in.d.bits.size, a_size_lookup)
node _T_641 = asUInt(reset)
node _T_642 = eq(_T_641, UInt<1>(0h0))
when _T_642 :
node _T_643 = eq(_T_640, UInt<1>(0h0))
when _T_643 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_640, UInt<1>(0h1), "") : assert_103
node _T_644 = and(io.in.d.valid, d_first_1)
node _T_645 = and(_T_644, a_first_1)
node _T_646 = and(_T_645, io.in.a.valid)
node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_648 = and(_T_646, _T_647)
node _T_649 = eq(d_release_ack, UInt<1>(0h0))
node _T_650 = and(_T_648, _T_649)
when _T_650 :
node _T_651 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_652 = or(_T_651, io.in.a.ready)
node _T_653 = asUInt(reset)
node _T_654 = eq(_T_653, UInt<1>(0h0))
when _T_654 :
node _T_655 = eq(_T_652, UInt<1>(0h0))
when _T_655 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_652, UInt<1>(0h1), "") : assert_104
node _T_656 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_657 = orr(a_set_wo_ready)
node _T_658 = eq(_T_657, UInt<1>(0h0))
node _T_659 = or(_T_656, _T_658)
node _T_660 = asUInt(reset)
node _T_661 = eq(_T_660, UInt<1>(0h0))
when _T_661 :
node _T_662 = eq(_T_659, UInt<1>(0h0))
when _T_662 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_659, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_72
node _T_663 = orr(inflight)
node _T_664 = eq(_T_663, UInt<1>(0h0))
node _T_665 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_666 = or(_T_664, _T_665)
node _T_667 = lt(watchdog, plusarg_reader.out)
node _T_668 = or(_T_666, _T_667)
node _T_669 = asUInt(reset)
node _T_670 = eq(_T_669, UInt<1>(0h0))
when _T_670 :
node _T_671 = eq(_T_668, UInt<1>(0h0))
when _T_671 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_668, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_672 = and(io.in.a.ready, io.in.a.valid)
node _T_673 = and(io.in.d.ready, io.in.d.valid)
node _T_674 = or(_T_672, _T_673)
when _T_674 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<10>, clock, reset, UInt<10>(0h0)
regreset inflight_opcodes_1 : UInt<40>, clock, reset, UInt<40>(0h0)
regreset inflight_sizes_1 : UInt<40>, clock, reset, UInt<40>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<28>(0h0)
connect _c_first_WIRE.bits.source, UInt<4>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<28>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<10>
connect c_set, UInt<10>(0h0)
wire c_set_wo_ready : UInt<10>
connect c_set_wo_ready, UInt<10>(0h0)
wire c_opcodes_set : UInt<40>
connect c_opcodes_set, UInt<40>(0h0)
wire c_sizes_set : UInt<40>
connect c_sizes_set, UInt<40>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<28>(0h0)
connect _WIRE_6.bits.source, UInt<4>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_675 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<28>(0h0)
connect _WIRE_8.bits.source, UInt<4>(0h0)
connect _WIRE_8.bits.size, UInt<3>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_676 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_677 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_678 = and(_T_676, _T_677)
node _T_679 = and(_T_675, _T_678)
when _T_679 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<28>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<28>(0h0)
connect _WIRE_10.bits.source, UInt<4>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_680 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_681 = and(_T_680, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<28>(0h0)
connect _WIRE_12.bits.source, UInt<4>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_682 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_683 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_684 = and(_T_682, _T_683)
node _T_685 = and(_T_681, _T_684)
when _T_685 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<28>(0h0)
connect _c_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<28>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<28>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<28>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<28>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<28>(0h0)
connect _WIRE_14.bits.source, UInt<4>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_686 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_687 = bits(_T_686, 0, 0)
node _T_688 = eq(_T_687, UInt<1>(0h0))
node _T_689 = asUInt(reset)
node _T_690 = eq(_T_689, UInt<1>(0h0))
when _T_690 :
node _T_691 = eq(_T_688, UInt<1>(0h0))
when _T_691 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_688, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<28>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<28>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<10>
connect d_clr_1, UInt<10>(0h0)
wire d_clr_wo_ready_1 : UInt<10>
connect d_clr_wo_ready_1, UInt<10>(0h0)
wire d_opcodes_clr_1 : UInt<40>
connect d_opcodes_clr_1, UInt<40>(0h0)
wire d_sizes_clr_1 : UInt<40>
connect d_sizes_clr_1, UInt<40>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_692 = and(io.in.d.valid, d_first_2)
node _T_693 = and(_T_692, UInt<1>(0h1))
node _T_694 = and(_T_693, d_release_ack_1)
when _T_694 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_695 = and(io.in.d.ready, io.in.d.valid)
node _T_696 = and(_T_695, d_first_2)
node _T_697 = and(_T_696, UInt<1>(0h1))
node _T_698 = and(_T_697, d_release_ack_1)
when _T_698 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_699 = and(io.in.d.valid, d_first_2)
node _T_700 = and(_T_699, UInt<1>(0h1))
node _T_701 = and(_T_700, d_release_ack_1)
when _T_701 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<28>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<28>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<28>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_702 = dshr(inflight_1, io.in.d.bits.source)
node _T_703 = bits(_T_702, 0, 0)
node _T_704 = or(_T_703, same_cycle_resp_1)
node _T_705 = asUInt(reset)
node _T_706 = eq(_T_705, UInt<1>(0h0))
when _T_706 :
node _T_707 = eq(_T_704, UInt<1>(0h0))
when _T_707 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_704, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<28>(0h0)
connect _WIRE_16.bits.source, UInt<4>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_708 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_709 = asUInt(reset)
node _T_710 = eq(_T_709, UInt<1>(0h0))
when _T_710 :
node _T_711 = eq(_T_708, UInt<1>(0h0))
when _T_711 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_708, UInt<1>(0h1), "") : assert_109
else :
node _T_712 = eq(io.in.d.bits.size, c_size_lookup)
node _T_713 = asUInt(reset)
node _T_714 = eq(_T_713, UInt<1>(0h0))
when _T_714 :
node _T_715 = eq(_T_712, UInt<1>(0h0))
when _T_715 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_712, UInt<1>(0h1), "") : assert_110
node _T_716 = and(io.in.d.valid, d_first_2)
node _T_717 = and(_T_716, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<28>(0h0)
connect _WIRE_18.bits.source, UInt<4>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_718 = and(_T_717, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<28>(0h0)
connect _WIRE_20.bits.source, UInt<4>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_719 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_720 = and(_T_718, _T_719)
node _T_721 = and(_T_720, d_release_ack_1)
node _T_722 = eq(c_probe_ack, UInt<1>(0h0))
node _T_723 = and(_T_721, _T_722)
when _T_723 :
node _T_724 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<28>(0h0)
connect _WIRE_22.bits.source, UInt<4>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_725 = or(_T_724, _WIRE_23.ready)
node _T_726 = asUInt(reset)
node _T_727 = eq(_T_726, UInt<1>(0h0))
when _T_727 :
node _T_728 = eq(_T_725, UInt<1>(0h0))
when _T_728 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_725, UInt<1>(0h1), "") : assert_111
node _T_729 = orr(c_set_wo_ready)
when _T_729 :
node _T_730 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_731 = asUInt(reset)
node _T_732 = eq(_T_731, UInt<1>(0h0))
when _T_732 :
node _T_733 = eq(_T_730, UInt<1>(0h0))
when _T_733 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_730, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_73
node _T_734 = orr(inflight_1)
node _T_735 = eq(_T_734, UInt<1>(0h0))
node _T_736 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_737 = or(_T_735, _T_736)
node _T_738 = lt(watchdog_1, plusarg_reader_1.out)
node _T_739 = or(_T_737, _T_738)
node _T_740 = asUInt(reset)
node _T_741 = eq(_T_740, UInt<1>(0h0))
when _T_741 :
node _T_742 = eq(_T_739, UInt<1>(0h0))
when _T_742 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_739, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<28>(0h0)
connect _WIRE_24.bits.source, UInt<4>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_743 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_744 = and(io.in.d.ready, io.in.d.valid)
node _T_745 = or(_T_743, _T_744)
when _T_745 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_36( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [27:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10]
wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_first_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_first_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_first_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_first_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_set_wo_ready_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_set_wo_ready_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_opcodes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_opcodes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_sizes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_sizes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_opcodes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_opcodes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_sizes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_sizes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_probe_ack_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_probe_ack_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_probe_ack_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_probe_ack_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _same_cycle_resp_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _same_cycle_resp_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _same_cycle_resp_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _same_cycle_resp_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _same_cycle_resp_WIRE_4_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _same_cycle_resp_WIRE_5_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [130:0] _c_opcodes_set_T_1 = 131'h0; // @[Monitor.scala:767:54]
wire [130:0] _c_sizes_set_T_1 = 131'h0; // @[Monitor.scala:768:52]
wire [6:0] _c_opcodes_set_T = 7'h0; // @[Monitor.scala:767:79]
wire [6:0] _c_sizes_set_T = 7'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [15:0] _c_set_wo_ready_T = 16'h1; // @[OneHot.scala:58:35]
wire [15:0] _c_set_T = 16'h1; // @[OneHot.scala:58:35]
wire [39:0] c_opcodes_set = 40'h0; // @[Monitor.scala:740:34]
wire [39:0] c_sizes_set = 40'h0; // @[Monitor.scala:741:34]
wire [9:0] c_set = 10'h0; // @[Monitor.scala:738:34]
wire [9:0] c_set_wo_ready = 10'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_4 = source_ok_uncommonBits < 4'hA; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [27:0] _is_aligned_T = {22'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 28'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [3:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}]
wire [3:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_10 = source_ok_uncommonBits_1 < 4'hA; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31]
wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_672; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_672; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [3:0] source; // @[Monitor.scala:390:22]
reg [27:0] address; // @[Monitor.scala:391:22]
wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_745; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_745; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_745; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [3:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [9:0] inflight; // @[Monitor.scala:614:27]
reg [39:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [39:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [9:0] a_set; // @[Monitor.scala:626:34]
wire [9:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [39:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [39:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [6:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [6:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [6:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [6:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [6:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [6:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [6:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [6:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [6:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [39:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [39:0] _a_opcode_lookup_T_6 = {36'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [39:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [39:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [39:0] _a_size_lookup_T_6 = {36'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [39:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[39:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [15:0] _GEN_2 = 16'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [15:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [15:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire _T_598 = _T_672 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_598 ? _a_set_T[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [6:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [6:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [6:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [130:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [9:0] d_clr; // @[Monitor.scala:664:34]
wire [9:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [39:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [39:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [15:0] _GEN_5 = 16'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire _T_613 = _T_745 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_613 ? _d_clr_T[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [142:0] _d_sizes_clr_T_5 = 143'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [9:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [9:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [9:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [39:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [39:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [39:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [39:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [39:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [39:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [9:0] inflight_1; // @[Monitor.scala:726:35]
wire [9:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [39:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [39:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [39:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [39:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [39:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [39:0] _c_opcode_lookup_T_6 = {36'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [39:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [39:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [39:0] _c_size_lookup_T_6 = {36'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [39:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[39:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [9:0] d_clr_1; // @[Monitor.scala:774:34]
wire [9:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [39:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [39:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_716 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire _T_698 = _T_745 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_698 ? _d_clr_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [142:0] _d_sizes_clr_T_11 = 143'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 4'h0; // @[Monitor.scala:36:7, :795:113]
wire [9:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [9:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [39:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [39:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [39:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [39:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_190 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_source_extend of AsyncResetSynchronizerShiftReg_w1_d3_i0_200
connect io_out_source_extend.clock, clock
connect io_out_source_extend.reset, reset
connect io_out_source_extend.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_source_extend.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_190( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_200 io_out_source_extend ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_103 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_source_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_120
connect io_out_source_valid.clock, clock
connect io_out_source_valid.reset, reset
connect io_out_source_valid.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_source_valid.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_103( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_120 io_out_source_valid ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_11 :
input clock : Clock
input reset : Reset
output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], credit_return : UInt<8>, vc_free : UInt<8>}}
wire _in_flight_WIRE : UInt<1>[8]
connect _in_flight_WIRE[0], UInt<1>(0h0)
connect _in_flight_WIRE[1], UInt<1>(0h0)
connect _in_flight_WIRE[2], UInt<1>(0h0)
connect _in_flight_WIRE[3], UInt<1>(0h0)
connect _in_flight_WIRE[4], UInt<1>(0h0)
connect _in_flight_WIRE[5], UInt<1>(0h0)
connect _in_flight_WIRE[6], UInt<1>(0h0)
connect _in_flight_WIRE[7], UInt<1>(0h0)
regreset in_flight : UInt<1>[8], clock, reset, _in_flight_WIRE
when io.in.flit[0].valid :
when io.in.flit[0].bits.head :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1)
node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
when io.in.flit[0].bits.tail :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)
node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head)
when _T_4 :
node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0))
node _T_6 = or(_T_5, UInt<1>(0h0))
node _T_7 = asUInt(reset)
node _T_8 = eq(_T_7, UInt<1>(0h0))
when _T_8 :
node _T_9 = eq(_T_6, UInt<1>(0h0))
when _T_9 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1
assert(clock, _T_6, UInt<1>(0h1), "") : assert_1
node _T_10 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1))
node _T_11 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_12 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_13 = and(_T_11, _T_12)
node _T_14 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_15 = and(_T_13, _T_14)
node _T_16 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_19 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_20 = and(_T_18, _T_19)
node _T_21 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_22 = and(_T_20, _T_21)
node _T_23 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_24 = and(_T_22, _T_23)
node _T_25 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_26 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_27 = and(_T_25, _T_26)
node _T_28 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_29 = and(_T_27, _T_28)
node _T_30 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_31 = and(_T_29, _T_30)
node _T_32 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_33 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_34 = and(_T_32, _T_33)
node _T_35 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_36 = and(_T_34, _T_35)
node _T_37 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_38 = and(_T_36, _T_37)
node _T_39 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_40 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_41 = and(_T_39, _T_40)
node _T_42 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_45 = and(_T_43, _T_44)
node _T_46 = or(_T_17, _T_24)
node _T_47 = or(_T_46, _T_31)
node _T_48 = or(_T_47, _T_38)
node _T_49 = or(_T_48, _T_45)
node _T_50 = or(_T_10, _T_49)
node _T_51 = asUInt(reset)
node _T_52 = eq(_T_51, UInt<1>(0h0))
when _T_52 :
node _T_53 = eq(_T_50, UInt<1>(0h0))
when _T_53 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2
assert(clock, _T_50, UInt<1>(0h1), "") : assert_2
node _T_54 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2))
node _T_55 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_56 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_57 = and(_T_55, _T_56)
node _T_58 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_59 = and(_T_57, _T_58)
node _T_60 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_61 = and(_T_59, _T_60)
node _T_62 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_63 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_64 = and(_T_62, _T_63)
node _T_65 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_66 = and(_T_64, _T_65)
node _T_67 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_68 = and(_T_66, _T_67)
node _T_69 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_70 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_71 = and(_T_69, _T_70)
node _T_72 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_73 = and(_T_71, _T_72)
node _T_74 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_75 = and(_T_73, _T_74)
node _T_76 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_77 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_78 = and(_T_76, _T_77)
node _T_79 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_80 = and(_T_78, _T_79)
node _T_81 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_82 = and(_T_80, _T_81)
node _T_83 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_84 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_85 = and(_T_83, _T_84)
node _T_86 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_87 = and(_T_85, _T_86)
node _T_88 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_89 = and(_T_87, _T_88)
node _T_90 = or(_T_61, _T_68)
node _T_91 = or(_T_90, _T_75)
node _T_92 = or(_T_91, _T_82)
node _T_93 = or(_T_92, _T_89)
node _T_94 = or(_T_54, _T_93)
node _T_95 = asUInt(reset)
node _T_96 = eq(_T_95, UInt<1>(0h0))
when _T_96 :
node _T_97 = eq(_T_94, UInt<1>(0h0))
when _T_97 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_3
assert(clock, _T_94, UInt<1>(0h1), "") : assert_3
node _T_98 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3))
node _T_99 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_100 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_101 = and(_T_99, _T_100)
node _T_102 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_103 = and(_T_101, _T_102)
node _T_104 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_105 = and(_T_103, _T_104)
node _T_106 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_107 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_108 = and(_T_106, _T_107)
node _T_109 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_110 = and(_T_108, _T_109)
node _T_111 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_112 = and(_T_110, _T_111)
node _T_113 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_114 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_115 = and(_T_113, _T_114)
node _T_116 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_117 = and(_T_115, _T_116)
node _T_118 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_119 = and(_T_117, _T_118)
node _T_120 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_121 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_122 = and(_T_120, _T_121)
node _T_123 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_124 = and(_T_122, _T_123)
node _T_125 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_126 = and(_T_124, _T_125)
node _T_127 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_128 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_129 = and(_T_127, _T_128)
node _T_130 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_131 = and(_T_129, _T_130)
node _T_132 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_133 = and(_T_131, _T_132)
node _T_134 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_135 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_136 = and(_T_134, _T_135)
node _T_137 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_138 = and(_T_136, _T_137)
node _T_139 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_140 = and(_T_138, _T_139)
node _T_141 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_142 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_143 = and(_T_141, _T_142)
node _T_144 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_145 = and(_T_143, _T_144)
node _T_146 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_147 = and(_T_145, _T_146)
node _T_148 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_149 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_150 = and(_T_148, _T_149)
node _T_151 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_152 = and(_T_150, _T_151)
node _T_153 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_154 = and(_T_152, _T_153)
node _T_155 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_156 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_157 = and(_T_155, _T_156)
node _T_158 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_159 = and(_T_157, _T_158)
node _T_160 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_161 = and(_T_159, _T_160)
node _T_162 = or(_T_105, _T_112)
node _T_163 = or(_T_162, _T_119)
node _T_164 = or(_T_163, _T_126)
node _T_165 = or(_T_164, _T_133)
node _T_166 = or(_T_165, _T_140)
node _T_167 = or(_T_166, _T_147)
node _T_168 = or(_T_167, _T_154)
node _T_169 = or(_T_168, _T_161)
node _T_170 = or(_T_98, _T_169)
node _T_171 = asUInt(reset)
node _T_172 = eq(_T_171, UInt<1>(0h0))
when _T_172 :
node _T_173 = eq(_T_170, UInt<1>(0h0))
when _T_173 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_4
assert(clock, _T_170, UInt<1>(0h1), "") : assert_4
node _T_174 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h4))
node _T_175 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_176 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_177 = and(_T_175, _T_176)
node _T_178 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_179 = and(_T_177, _T_178)
node _T_180 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_181 = and(_T_179, _T_180)
node _T_182 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_183 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_184 = and(_T_182, _T_183)
node _T_185 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_186 = and(_T_184, _T_185)
node _T_187 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_188 = and(_T_186, _T_187)
node _T_189 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_190 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_191 = and(_T_189, _T_190)
node _T_192 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_193 = and(_T_191, _T_192)
node _T_194 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_195 = and(_T_193, _T_194)
node _T_196 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_197 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_198 = and(_T_196, _T_197)
node _T_199 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_200 = and(_T_198, _T_199)
node _T_201 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_202 = and(_T_200, _T_201)
node _T_203 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_204 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_205 = and(_T_203, _T_204)
node _T_206 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_207 = and(_T_205, _T_206)
node _T_208 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_209 = and(_T_207, _T_208)
node _T_210 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_211 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_212 = and(_T_210, _T_211)
node _T_213 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_214 = and(_T_212, _T_213)
node _T_215 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_216 = and(_T_214, _T_215)
node _T_217 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_218 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_219 = and(_T_217, _T_218)
node _T_220 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_221 = and(_T_219, _T_220)
node _T_222 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_223 = and(_T_221, _T_222)
node _T_224 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_225 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_226 = and(_T_224, _T_225)
node _T_227 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_228 = and(_T_226, _T_227)
node _T_229 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_230 = and(_T_228, _T_229)
node _T_231 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_232 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_233 = and(_T_231, _T_232)
node _T_234 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_235 = and(_T_233, _T_234)
node _T_236 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_237 = and(_T_235, _T_236)
node _T_238 = or(_T_181, _T_188)
node _T_239 = or(_T_238, _T_195)
node _T_240 = or(_T_239, _T_202)
node _T_241 = or(_T_240, _T_209)
node _T_242 = or(_T_241, _T_216)
node _T_243 = or(_T_242, _T_223)
node _T_244 = or(_T_243, _T_230)
node _T_245 = or(_T_244, _T_237)
node _T_246 = or(_T_174, _T_245)
node _T_247 = asUInt(reset)
node _T_248 = eq(_T_247, UInt<1>(0h0))
when _T_248 :
node _T_249 = eq(_T_246, UInt<1>(0h0))
when _T_249 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_5
assert(clock, _T_246, UInt<1>(0h1), "") : assert_5
node _T_250 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h5))
node _T_251 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_252 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_253 = and(_T_251, _T_252)
node _T_254 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_255 = and(_T_253, _T_254)
node _T_256 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_257 = and(_T_255, _T_256)
node _T_258 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_259 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_260 = and(_T_258, _T_259)
node _T_261 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_262 = and(_T_260, _T_261)
node _T_263 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_264 = and(_T_262, _T_263)
node _T_265 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_266 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_267 = and(_T_265, _T_266)
node _T_268 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_269 = and(_T_267, _T_268)
node _T_270 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_271 = and(_T_269, _T_270)
node _T_272 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_273 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_274 = and(_T_272, _T_273)
node _T_275 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_276 = and(_T_274, _T_275)
node _T_277 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_278 = and(_T_276, _T_277)
node _T_279 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_280 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_281 = and(_T_279, _T_280)
node _T_282 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_283 = and(_T_281, _T_282)
node _T_284 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_285 = and(_T_283, _T_284)
node _T_286 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_287 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_288 = and(_T_286, _T_287)
node _T_289 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_290 = and(_T_288, _T_289)
node _T_291 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_292 = and(_T_290, _T_291)
node _T_293 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_294 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_295 = and(_T_293, _T_294)
node _T_296 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_297 = and(_T_295, _T_296)
node _T_298 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_299 = and(_T_297, _T_298)
node _T_300 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_301 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_302 = and(_T_300, _T_301)
node _T_303 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_304 = and(_T_302, _T_303)
node _T_305 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_306 = and(_T_304, _T_305)
node _T_307 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_308 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_309 = and(_T_307, _T_308)
node _T_310 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_311 = and(_T_309, _T_310)
node _T_312 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_313 = and(_T_311, _T_312)
node _T_314 = or(_T_257, _T_264)
node _T_315 = or(_T_314, _T_271)
node _T_316 = or(_T_315, _T_278)
node _T_317 = or(_T_316, _T_285)
node _T_318 = or(_T_317, _T_292)
node _T_319 = or(_T_318, _T_299)
node _T_320 = or(_T_319, _T_306)
node _T_321 = or(_T_320, _T_313)
node _T_322 = or(_T_250, _T_321)
node _T_323 = asUInt(reset)
node _T_324 = eq(_T_323, UInt<1>(0h0))
when _T_324 :
node _T_325 = eq(_T_322, UInt<1>(0h0))
when _T_325 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_6
assert(clock, _T_322, UInt<1>(0h1), "") : assert_6
node _T_326 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h6))
node _T_327 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_328 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_329 = and(_T_327, _T_328)
node _T_330 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_331 = and(_T_329, _T_330)
node _T_332 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_333 = and(_T_331, _T_332)
node _T_334 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_335 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_336 = and(_T_334, _T_335)
node _T_337 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_338 = and(_T_336, _T_337)
node _T_339 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_340 = and(_T_338, _T_339)
node _T_341 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_342 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_343 = and(_T_341, _T_342)
node _T_344 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_345 = and(_T_343, _T_344)
node _T_346 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_347 = and(_T_345, _T_346)
node _T_348 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_349 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_350 = and(_T_348, _T_349)
node _T_351 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_352 = and(_T_350, _T_351)
node _T_353 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_354 = and(_T_352, _T_353)
node _T_355 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_356 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_357 = and(_T_355, _T_356)
node _T_358 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_359 = and(_T_357, _T_358)
node _T_360 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_361 = and(_T_359, _T_360)
node _T_362 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_363 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_364 = and(_T_362, _T_363)
node _T_365 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_366 = and(_T_364, _T_365)
node _T_367 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_368 = and(_T_366, _T_367)
node _T_369 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_370 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_371 = and(_T_369, _T_370)
node _T_372 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_373 = and(_T_371, _T_372)
node _T_374 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_375 = and(_T_373, _T_374)
node _T_376 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_377 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_378 = and(_T_376, _T_377)
node _T_379 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_380 = and(_T_378, _T_379)
node _T_381 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_382 = and(_T_380, _T_381)
node _T_383 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_384 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_385 = and(_T_383, _T_384)
node _T_386 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_387 = and(_T_385, _T_386)
node _T_388 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_389 = and(_T_387, _T_388)
node _T_390 = or(_T_333, _T_340)
node _T_391 = or(_T_390, _T_347)
node _T_392 = or(_T_391, _T_354)
node _T_393 = or(_T_392, _T_361)
node _T_394 = or(_T_393, _T_368)
node _T_395 = or(_T_394, _T_375)
node _T_396 = or(_T_395, _T_382)
node _T_397 = or(_T_396, _T_389)
node _T_398 = or(_T_326, _T_397)
node _T_399 = asUInt(reset)
node _T_400 = eq(_T_399, UInt<1>(0h0))
when _T_400 :
node _T_401 = eq(_T_398, UInt<1>(0h0))
when _T_401 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_7
assert(clock, _T_398, UInt<1>(0h1), "") : assert_7
node _T_402 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h7))
node _T_403 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_404 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_405 = and(_T_403, _T_404)
node _T_406 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_407 = and(_T_405, _T_406)
node _T_408 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_409 = and(_T_407, _T_408)
node _T_410 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_411 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_412 = and(_T_410, _T_411)
node _T_413 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_414 = and(_T_412, _T_413)
node _T_415 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_416 = and(_T_414, _T_415)
node _T_417 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_418 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_419 = and(_T_417, _T_418)
node _T_420 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_421 = and(_T_419, _T_420)
node _T_422 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_423 = and(_T_421, _T_422)
node _T_424 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_425 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_426 = and(_T_424, _T_425)
node _T_427 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_428 = and(_T_426, _T_427)
node _T_429 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_430 = and(_T_428, _T_429)
node _T_431 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_432 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_433 = and(_T_431, _T_432)
node _T_434 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_435 = and(_T_433, _T_434)
node _T_436 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_437 = and(_T_435, _T_436)
node _T_438 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_439 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_440 = and(_T_438, _T_439)
node _T_441 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_442 = and(_T_440, _T_441)
node _T_443 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_444 = and(_T_442, _T_443)
node _T_445 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_446 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_447 = and(_T_445, _T_446)
node _T_448 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_449 = and(_T_447, _T_448)
node _T_450 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_451 = and(_T_449, _T_450)
node _T_452 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_453 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_454 = and(_T_452, _T_453)
node _T_455 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_456 = and(_T_454, _T_455)
node _T_457 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_458 = and(_T_456, _T_457)
node _T_459 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_460 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_461 = and(_T_459, _T_460)
node _T_462 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_463 = and(_T_461, _T_462)
node _T_464 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_465 = and(_T_463, _T_464)
node _T_466 = or(_T_409, _T_416)
node _T_467 = or(_T_466, _T_423)
node _T_468 = or(_T_467, _T_430)
node _T_469 = or(_T_468, _T_437)
node _T_470 = or(_T_469, _T_444)
node _T_471 = or(_T_470, _T_451)
node _T_472 = or(_T_471, _T_458)
node _T_473 = or(_T_472, _T_465)
node _T_474 = or(_T_402, _T_473)
node _T_475 = asUInt(reset)
node _T_476 = eq(_T_475, UInt<1>(0h0))
when _T_476 :
node _T_477 = eq(_T_474, UInt<1>(0h0))
when _T_477 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_8
assert(clock, _T_474, UInt<1>(0h1), "") : assert_8 | module NoCMonitor_11( // @[Monitor.scala:11:7]
input clock, // @[Monitor.scala:11:7]
input reset, // @[Monitor.scala:11:7]
input io_in_flit_0_valid, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_head, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14]
input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14]
input [4:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14]
input [2:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14]
);
reg in_flight_0; // @[Monitor.scala:16:26]
reg in_flight_1; // @[Monitor.scala:16:26]
reg in_flight_2; // @[Monitor.scala:16:26]
reg in_flight_3; // @[Monitor.scala:16:26]
reg in_flight_4; // @[Monitor.scala:16:26]
reg in_flight_5; // @[Monitor.scala:16:26]
reg in_flight_6; // @[Monitor.scala:16:26]
reg in_flight_7; // @[Monitor.scala:16:26]
wire _GEN = io_in_flit_0_bits_virt_channel_id == 3'h0; // @[Monitor.scala:21:46] |
Generate the Verilog code corresponding to this FIRRTL code module TageTable_8 :
input clock : Clock
input reset : Reset
output io : { flip f1_req_valid : UInt<1>, flip f1_req_pc : UInt<40>, flip f1_req_ghist : UInt<64>, f3_resp : { valid : UInt<1>, bits : { ctr : UInt<3>, u : UInt<2>}}[4], flip update_mask : UInt<1>[4], flip update_taken : UInt<1>[4], flip update_alloc : UInt<1>[4], flip update_old_ctr : UInt<3>[4], flip update_pc : UInt, flip update_hist : UInt, flip update_u_mask : UInt<1>[4], flip update_u : UInt<2>[4]}
regreset doing_reset : UInt<1>, clock, reset, UInt<1>(0h1)
regreset reset_idx : UInt<8>, clock, reset, UInt<8>(0h0)
node _reset_idx_T = add(reset_idx, doing_reset)
node _reset_idx_T_1 = tail(_reset_idx_T, 1)
connect reset_idx, _reset_idx_T_1
node _T = eq(reset_idx, UInt<8>(0hff))
when _T :
connect doing_reset, UInt<1>(0h0)
node _T_1 = shr(io.f1_req_pc, 4)
node idx_history = bits(io.f1_req_ghist, 7, 0)
node _idx_T = xor(_T_1, idx_history)
node s1_hashed_idx = bits(_idx_T, 7, 0)
node tag_history = bits(io.f1_req_ghist, 7, 0)
node _tag_T = shr(_T_1, 8)
node _tag_T_1 = xor(_tag_T, tag_history)
node s1_tag = bits(_tag_T_1, 7, 0)
smem hi_us : UInt<1>[4] [256]
smem lo_us : UInt<1>[4] [256]
smem table : UInt<12>[4] [256]
reg s2_tag : UInt, clock
connect s2_tag, s1_tag
wire _s2_req_rtage_WIRE : UInt<8>
invalidate _s2_req_rtage_WIRE
when io.f1_req_valid :
connect _s2_req_rtage_WIRE, s1_hashed_idx
read mport s2_req_rtage_MPORT = table[_s2_req_rtage_WIRE], clock
wire _s2_req_rtage_WIRE_1 : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>}
wire _s2_req_rtage_WIRE_2 : UInt<12>
connect _s2_req_rtage_WIRE_2, s2_req_rtage_MPORT[0]
node _s2_req_rtage_T = bits(_s2_req_rtage_WIRE_2, 2, 0)
connect _s2_req_rtage_WIRE_1.ctr, _s2_req_rtage_T
node _s2_req_rtage_T_1 = bits(_s2_req_rtage_WIRE_2, 10, 3)
connect _s2_req_rtage_WIRE_1.tag, _s2_req_rtage_T_1
node _s2_req_rtage_T_2 = bits(_s2_req_rtage_WIRE_2, 11, 11)
connect _s2_req_rtage_WIRE_1.valid, _s2_req_rtage_T_2
wire _s2_req_rtage_WIRE_3 : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>}
wire _s2_req_rtage_WIRE_4 : UInt<12>
connect _s2_req_rtage_WIRE_4, s2_req_rtage_MPORT[1]
node _s2_req_rtage_T_3 = bits(_s2_req_rtage_WIRE_4, 2, 0)
connect _s2_req_rtage_WIRE_3.ctr, _s2_req_rtage_T_3
node _s2_req_rtage_T_4 = bits(_s2_req_rtage_WIRE_4, 10, 3)
connect _s2_req_rtage_WIRE_3.tag, _s2_req_rtage_T_4
node _s2_req_rtage_T_5 = bits(_s2_req_rtage_WIRE_4, 11, 11)
connect _s2_req_rtage_WIRE_3.valid, _s2_req_rtage_T_5
wire _s2_req_rtage_WIRE_5 : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>}
wire _s2_req_rtage_WIRE_6 : UInt<12>
connect _s2_req_rtage_WIRE_6, s2_req_rtage_MPORT[2]
node _s2_req_rtage_T_6 = bits(_s2_req_rtage_WIRE_6, 2, 0)
connect _s2_req_rtage_WIRE_5.ctr, _s2_req_rtage_T_6
node _s2_req_rtage_T_7 = bits(_s2_req_rtage_WIRE_6, 10, 3)
connect _s2_req_rtage_WIRE_5.tag, _s2_req_rtage_T_7
node _s2_req_rtage_T_8 = bits(_s2_req_rtage_WIRE_6, 11, 11)
connect _s2_req_rtage_WIRE_5.valid, _s2_req_rtage_T_8
wire _s2_req_rtage_WIRE_7 : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>}
wire _s2_req_rtage_WIRE_8 : UInt<12>
connect _s2_req_rtage_WIRE_8, s2_req_rtage_MPORT[3]
node _s2_req_rtage_T_9 = bits(_s2_req_rtage_WIRE_8, 2, 0)
connect _s2_req_rtage_WIRE_7.ctr, _s2_req_rtage_T_9
node _s2_req_rtage_T_10 = bits(_s2_req_rtage_WIRE_8, 10, 3)
connect _s2_req_rtage_WIRE_7.tag, _s2_req_rtage_T_10
node _s2_req_rtage_T_11 = bits(_s2_req_rtage_WIRE_8, 11, 11)
connect _s2_req_rtage_WIRE_7.valid, _s2_req_rtage_T_11
wire s2_req_rtage : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>}[4]
connect s2_req_rtage[0].ctr, _s2_req_rtage_WIRE_1.ctr
connect s2_req_rtage[0].tag, _s2_req_rtage_WIRE_1.tag
connect s2_req_rtage[0].valid, _s2_req_rtage_WIRE_1.valid
connect s2_req_rtage[1].ctr, _s2_req_rtage_WIRE_3.ctr
connect s2_req_rtage[1].tag, _s2_req_rtage_WIRE_3.tag
connect s2_req_rtage[1].valid, _s2_req_rtage_WIRE_3.valid
connect s2_req_rtage[2].ctr, _s2_req_rtage_WIRE_5.ctr
connect s2_req_rtage[2].tag, _s2_req_rtage_WIRE_5.tag
connect s2_req_rtage[2].valid, _s2_req_rtage_WIRE_5.valid
connect s2_req_rtage[3].ctr, _s2_req_rtage_WIRE_7.ctr
connect s2_req_rtage[3].tag, _s2_req_rtage_WIRE_7.tag
connect s2_req_rtage[3].valid, _s2_req_rtage_WIRE_7.valid
wire _s2_req_rhius_WIRE : UInt<8>
invalidate _s2_req_rhius_WIRE
when io.f1_req_valid :
connect _s2_req_rhius_WIRE, s1_hashed_idx
read mport s2_req_rhius = hi_us[_s2_req_rhius_WIRE], clock
wire _s2_req_rlous_WIRE : UInt<8>
invalidate _s2_req_rlous_WIRE
when io.f1_req_valid :
connect _s2_req_rlous_WIRE, s1_hashed_idx
read mport s2_req_rlous = lo_us[_s2_req_rlous_WIRE], clock
node _s2_req_rhits_T = eq(s2_req_rtage[0].tag, s2_tag)
node _s2_req_rhits_T_1 = and(s2_req_rtage[0].valid, _s2_req_rhits_T)
node _s2_req_rhits_T_2 = eq(doing_reset, UInt<1>(0h0))
node _s2_req_rhits_T_3 = and(_s2_req_rhits_T_1, _s2_req_rhits_T_2)
node _s2_req_rhits_T_4 = eq(s2_req_rtage[1].tag, s2_tag)
node _s2_req_rhits_T_5 = and(s2_req_rtage[1].valid, _s2_req_rhits_T_4)
node _s2_req_rhits_T_6 = eq(doing_reset, UInt<1>(0h0))
node _s2_req_rhits_T_7 = and(_s2_req_rhits_T_5, _s2_req_rhits_T_6)
node _s2_req_rhits_T_8 = eq(s2_req_rtage[2].tag, s2_tag)
node _s2_req_rhits_T_9 = and(s2_req_rtage[2].valid, _s2_req_rhits_T_8)
node _s2_req_rhits_T_10 = eq(doing_reset, UInt<1>(0h0))
node _s2_req_rhits_T_11 = and(_s2_req_rhits_T_9, _s2_req_rhits_T_10)
node _s2_req_rhits_T_12 = eq(s2_req_rtage[3].tag, s2_tag)
node _s2_req_rhits_T_13 = and(s2_req_rtage[3].valid, _s2_req_rhits_T_12)
node _s2_req_rhits_T_14 = eq(doing_reset, UInt<1>(0h0))
node _s2_req_rhits_T_15 = and(_s2_req_rhits_T_13, _s2_req_rhits_T_14)
wire s2_req_rhits : UInt<1>[4]
connect s2_req_rhits[0], _s2_req_rhits_T_3
connect s2_req_rhits[1], _s2_req_rhits_T_7
connect s2_req_rhits[2], _s2_req_rhits_T_11
connect s2_req_rhits[3], _s2_req_rhits_T_15
reg io_f3_resp_0_valid_REG : UInt<1>, clock
connect io_f3_resp_0_valid_REG, s2_req_rhits[0]
connect io.f3_resp[0].valid, io_f3_resp_0_valid_REG
node _io_f3_resp_0_bits_u_T = cat(s2_req_rhius[0], s2_req_rlous[0])
reg io_f3_resp_0_bits_u_REG : UInt, clock
connect io_f3_resp_0_bits_u_REG, _io_f3_resp_0_bits_u_T
connect io.f3_resp[0].bits.u, io_f3_resp_0_bits_u_REG
reg io_f3_resp_0_bits_ctr_REG : UInt, clock
connect io_f3_resp_0_bits_ctr_REG, s2_req_rtage[0].ctr
connect io.f3_resp[0].bits.ctr, io_f3_resp_0_bits_ctr_REG
reg io_f3_resp_1_valid_REG : UInt<1>, clock
connect io_f3_resp_1_valid_REG, s2_req_rhits[1]
connect io.f3_resp[1].valid, io_f3_resp_1_valid_REG
node _io_f3_resp_1_bits_u_T = cat(s2_req_rhius[1], s2_req_rlous[1])
reg io_f3_resp_1_bits_u_REG : UInt, clock
connect io_f3_resp_1_bits_u_REG, _io_f3_resp_1_bits_u_T
connect io.f3_resp[1].bits.u, io_f3_resp_1_bits_u_REG
reg io_f3_resp_1_bits_ctr_REG : UInt, clock
connect io_f3_resp_1_bits_ctr_REG, s2_req_rtage[1].ctr
connect io.f3_resp[1].bits.ctr, io_f3_resp_1_bits_ctr_REG
reg io_f3_resp_2_valid_REG : UInt<1>, clock
connect io_f3_resp_2_valid_REG, s2_req_rhits[2]
connect io.f3_resp[2].valid, io_f3_resp_2_valid_REG
node _io_f3_resp_2_bits_u_T = cat(s2_req_rhius[2], s2_req_rlous[2])
reg io_f3_resp_2_bits_u_REG : UInt, clock
connect io_f3_resp_2_bits_u_REG, _io_f3_resp_2_bits_u_T
connect io.f3_resp[2].bits.u, io_f3_resp_2_bits_u_REG
reg io_f3_resp_2_bits_ctr_REG : UInt, clock
connect io_f3_resp_2_bits_ctr_REG, s2_req_rtage[2].ctr
connect io.f3_resp[2].bits.ctr, io_f3_resp_2_bits_ctr_REG
reg io_f3_resp_3_valid_REG : UInt<1>, clock
connect io_f3_resp_3_valid_REG, s2_req_rhits[3]
connect io.f3_resp[3].valid, io_f3_resp_3_valid_REG
node _io_f3_resp_3_bits_u_T = cat(s2_req_rhius[3], s2_req_rlous[3])
reg io_f3_resp_3_bits_u_REG : UInt, clock
connect io_f3_resp_3_bits_u_REG, _io_f3_resp_3_bits_u_T
connect io.f3_resp[3].bits.u, io_f3_resp_3_bits_u_REG
reg io_f3_resp_3_bits_ctr_REG : UInt, clock
connect io_f3_resp_3_bits_ctr_REG, s2_req_rtage[3].ctr
connect io.f3_resp[3].bits.ctr, io_f3_resp_3_bits_ctr_REG
regreset clear_u_ctr : UInt<20>, clock, reset, UInt<20>(0h0)
when doing_reset :
connect clear_u_ctr, UInt<1>(0h1)
else :
node _clear_u_ctr_T = add(clear_u_ctr, UInt<1>(0h1))
node _clear_u_ctr_T_1 = tail(_clear_u_ctr_T, 1)
connect clear_u_ctr, _clear_u_ctr_T_1
node _doing_clear_u_T = bits(clear_u_ctr, 10, 0)
node doing_clear_u = eq(_doing_clear_u_T, UInt<1>(0h0))
node _doing_clear_u_hi_T = bits(clear_u_ctr, 19, 19)
node _doing_clear_u_hi_T_1 = eq(_doing_clear_u_hi_T, UInt<1>(0h1))
node doing_clear_u_hi = and(doing_clear_u, _doing_clear_u_hi_T_1)
node _doing_clear_u_lo_T = bits(clear_u_ctr, 19, 19)
node _doing_clear_u_lo_T_1 = eq(_doing_clear_u_lo_T, UInt<1>(0h0))
node doing_clear_u_lo = and(doing_clear_u, _doing_clear_u_lo_T_1)
node clear_u_idx = shr(clear_u_ctr, 11)
node _T_2 = shr(io.update_pc, 4)
node idx_history_1 = bits(io.update_hist, 7, 0)
node _idx_T_1 = xor(_T_2, idx_history_1)
node update_idx = bits(_idx_T_1, 7, 0)
node tag_history_1 = bits(io.update_hist, 7, 0)
node _tag_T_2 = shr(_T_2, 8)
node _tag_T_3 = xor(_tag_T_2, tag_history_1)
node update_tag = bits(_tag_T_3, 7, 0)
wire update_wdata : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>}[4]
node _T_3 = mux(doing_reset, reset_idx, update_idx)
wire _WIRE : UInt<12>[4]
connect _WIRE[0], UInt<12>(0h0)
connect _WIRE[1], UInt<12>(0h0)
connect _WIRE[2], UInt<12>(0h0)
connect _WIRE[3], UInt<12>(0h0)
node hi = cat(update_wdata[0].valid, update_wdata[0].tag)
node _T_4 = cat(hi, update_wdata[0].ctr)
node hi_1 = cat(update_wdata[1].valid, update_wdata[1].tag)
node _T_5 = cat(hi_1, update_wdata[1].ctr)
node hi_2 = cat(update_wdata[2].valid, update_wdata[2].tag)
node _T_6 = cat(hi_2, update_wdata[2].ctr)
node hi_3 = cat(update_wdata[3].valid, update_wdata[3].tag)
node _T_7 = cat(hi_3, update_wdata[3].ctr)
wire _WIRE_1 : UInt<12>[4]
connect _WIRE_1[0], _T_4
connect _WIRE_1[1], _T_5
connect _WIRE_1[2], _T_6
connect _WIRE_1[3], _T_7
node _T_8 = mux(doing_reset, _WIRE, _WIRE_1)
node _T_9 = not(UInt<4>(0h0))
node lo = cat(io.update_mask[1], io.update_mask[0])
node hi_4 = cat(io.update_mask[3], io.update_mask[2])
node _T_10 = cat(hi_4, lo)
node _T_11 = mux(doing_reset, _T_9, _T_10)
node _T_12 = bits(_T_11, 0, 0)
node _T_13 = bits(_T_11, 1, 1)
node _T_14 = bits(_T_11, 2, 2)
node _T_15 = bits(_T_11, 3, 3)
write mport MPORT = table[_T_3], clock
when _T_12 :
connect MPORT[0], _T_8[0]
when _T_13 :
connect MPORT[1], _T_8[1]
when _T_14 :
connect MPORT[2], _T_8[2]
when _T_15 :
connect MPORT[3], _T_8[3]
wire update_hi_wdata : UInt<1>[4]
node _T_16 = mux(doing_clear_u_hi, clear_u_idx, update_idx)
node _T_17 = mux(doing_reset, reset_idx, _T_16)
node _T_18 = or(doing_reset, doing_clear_u_hi)
wire _WIRE_2 : UInt<1>[4]
connect _WIRE_2[0], UInt<1>(0h0)
connect _WIRE_2[1], UInt<1>(0h0)
connect _WIRE_2[2], UInt<1>(0h0)
connect _WIRE_2[3], UInt<1>(0h0)
node _T_19 = mux(_T_18, _WIRE_2, update_hi_wdata)
node _T_20 = or(doing_reset, doing_clear_u_hi)
node _T_21 = not(UInt<4>(0h0))
node lo_1 = cat(io.update_u_mask[1], io.update_u_mask[0])
node hi_5 = cat(io.update_u_mask[3], io.update_u_mask[2])
node _T_22 = cat(hi_5, lo_1)
node _T_23 = mux(_T_20, _T_21, _T_22)
node _T_24 = bits(_T_23, 0, 0)
node _T_25 = bits(_T_23, 1, 1)
node _T_26 = bits(_T_23, 2, 2)
node _T_27 = bits(_T_23, 3, 3)
node _T_28 = bits(_T_17, 7, 0)
write mport MPORT_1 = hi_us[_T_28], clock
when _T_24 :
connect MPORT_1[0], _T_19[0]
when _T_25 :
connect MPORT_1[1], _T_19[1]
when _T_26 :
connect MPORT_1[2], _T_19[2]
when _T_27 :
connect MPORT_1[3], _T_19[3]
wire update_lo_wdata : UInt<1>[4]
node _T_29 = mux(doing_clear_u_lo, clear_u_idx, update_idx)
node _T_30 = mux(doing_reset, reset_idx, _T_29)
node _T_31 = or(doing_reset, doing_clear_u_lo)
wire _WIRE_3 : UInt<1>[4]
connect _WIRE_3[0], UInt<1>(0h0)
connect _WIRE_3[1], UInt<1>(0h0)
connect _WIRE_3[2], UInt<1>(0h0)
connect _WIRE_3[3], UInt<1>(0h0)
node _T_32 = mux(_T_31, _WIRE_3, update_lo_wdata)
node _T_33 = or(doing_reset, doing_clear_u_lo)
node _T_34 = not(UInt<4>(0h0))
node lo_2 = cat(io.update_u_mask[1], io.update_u_mask[0])
node hi_6 = cat(io.update_u_mask[3], io.update_u_mask[2])
node _T_35 = cat(hi_6, lo_2)
node _T_36 = mux(_T_33, _T_34, _T_35)
node _T_37 = bits(_T_36, 0, 0)
node _T_38 = bits(_T_36, 1, 1)
node _T_39 = bits(_T_36, 2, 2)
node _T_40 = bits(_T_36, 3, 3)
node _T_41 = bits(_T_30, 7, 0)
write mport MPORT_2 = lo_us[_T_41], clock
when _T_37 :
connect MPORT_2[0], _T_32[0]
when _T_38 :
connect MPORT_2[1], _T_32[1]
when _T_39 :
connect MPORT_2[2], _T_32[2]
when _T_40 :
connect MPORT_2[3], _T_32[3]
reg wrbypass_tags : UInt<8>[2], clock
reg wrbypass_idxs : UInt<8>[2], clock
reg wrbypass : UInt<3>[4][2], clock
regreset wrbypass_enq_idx : UInt<1>, clock, reset, UInt<1>(0h0)
node _wrbypass_hits_T = eq(doing_reset, UInt<1>(0h0))
node _wrbypass_hits_T_1 = eq(wrbypass_tags[0], update_tag)
node _wrbypass_hits_T_2 = and(_wrbypass_hits_T, _wrbypass_hits_T_1)
node _wrbypass_hits_T_3 = eq(wrbypass_idxs[0], update_idx)
node _wrbypass_hits_T_4 = and(_wrbypass_hits_T_2, _wrbypass_hits_T_3)
node _wrbypass_hits_T_5 = eq(doing_reset, UInt<1>(0h0))
node _wrbypass_hits_T_6 = eq(wrbypass_tags[1], update_tag)
node _wrbypass_hits_T_7 = and(_wrbypass_hits_T_5, _wrbypass_hits_T_6)
node _wrbypass_hits_T_8 = eq(wrbypass_idxs[1], update_idx)
node _wrbypass_hits_T_9 = and(_wrbypass_hits_T_7, _wrbypass_hits_T_8)
wire wrbypass_hits : UInt<1>[2]
connect wrbypass_hits[0], _wrbypass_hits_T_4
connect wrbypass_hits[1], _wrbypass_hits_T_9
node wrbypass_hit = or(wrbypass_hits[0], wrbypass_hits[1])
node wrbypass_hit_idx = mux(wrbypass_hits[0], UInt<1>(0h0), UInt<1>(0h1))
node _update_wdata_0_ctr_T = mux(io.update_taken[0], UInt<3>(0h4), UInt<2>(0h3))
node _update_wdata_0_ctr_T_1 = eq(io.update_taken[0], UInt<1>(0h0))
node _update_wdata_0_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][0], UInt<1>(0h0))
node _update_wdata_0_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][0], UInt<1>(0h1))
node _update_wdata_0_ctr_T_4 = tail(_update_wdata_0_ctr_T_3, 1)
node _update_wdata_0_ctr_T_5 = mux(_update_wdata_0_ctr_T_2, UInt<1>(0h0), _update_wdata_0_ctr_T_4)
node _update_wdata_0_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][0], UInt<3>(0h7))
node _update_wdata_0_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][0], UInt<1>(0h1))
node _update_wdata_0_ctr_T_8 = tail(_update_wdata_0_ctr_T_7, 1)
node _update_wdata_0_ctr_T_9 = mux(_update_wdata_0_ctr_T_6, UInt<3>(0h7), _update_wdata_0_ctr_T_8)
node _update_wdata_0_ctr_T_10 = mux(_update_wdata_0_ctr_T_1, _update_wdata_0_ctr_T_5, _update_wdata_0_ctr_T_9)
node _update_wdata_0_ctr_T_11 = eq(io.update_taken[0], UInt<1>(0h0))
node _update_wdata_0_ctr_T_12 = eq(io.update_old_ctr[0], UInt<1>(0h0))
node _update_wdata_0_ctr_T_13 = sub(io.update_old_ctr[0], UInt<1>(0h1))
node _update_wdata_0_ctr_T_14 = tail(_update_wdata_0_ctr_T_13, 1)
node _update_wdata_0_ctr_T_15 = mux(_update_wdata_0_ctr_T_12, UInt<1>(0h0), _update_wdata_0_ctr_T_14)
node _update_wdata_0_ctr_T_16 = eq(io.update_old_ctr[0], UInt<3>(0h7))
node _update_wdata_0_ctr_T_17 = add(io.update_old_ctr[0], UInt<1>(0h1))
node _update_wdata_0_ctr_T_18 = tail(_update_wdata_0_ctr_T_17, 1)
node _update_wdata_0_ctr_T_19 = mux(_update_wdata_0_ctr_T_16, UInt<3>(0h7), _update_wdata_0_ctr_T_18)
node _update_wdata_0_ctr_T_20 = mux(_update_wdata_0_ctr_T_11, _update_wdata_0_ctr_T_15, _update_wdata_0_ctr_T_19)
node _update_wdata_0_ctr_T_21 = mux(wrbypass_hit, _update_wdata_0_ctr_T_10, _update_wdata_0_ctr_T_20)
node _update_wdata_0_ctr_T_22 = mux(io.update_alloc[0], _update_wdata_0_ctr_T, _update_wdata_0_ctr_T_21)
connect update_wdata[0].ctr, _update_wdata_0_ctr_T_22
connect update_wdata[0].valid, UInt<1>(0h1)
connect update_wdata[0].tag, update_tag
node _update_hi_wdata_0_T = bits(io.update_u[0], 1, 1)
connect update_hi_wdata[0], _update_hi_wdata_0_T
node _update_lo_wdata_0_T = bits(io.update_u[0], 0, 0)
connect update_lo_wdata[0], _update_lo_wdata_0_T
node _update_wdata_1_ctr_T = mux(io.update_taken[1], UInt<3>(0h4), UInt<2>(0h3))
node _update_wdata_1_ctr_T_1 = eq(io.update_taken[1], UInt<1>(0h0))
node _update_wdata_1_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][1], UInt<1>(0h0))
node _update_wdata_1_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][1], UInt<1>(0h1))
node _update_wdata_1_ctr_T_4 = tail(_update_wdata_1_ctr_T_3, 1)
node _update_wdata_1_ctr_T_5 = mux(_update_wdata_1_ctr_T_2, UInt<1>(0h0), _update_wdata_1_ctr_T_4)
node _update_wdata_1_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][1], UInt<3>(0h7))
node _update_wdata_1_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][1], UInt<1>(0h1))
node _update_wdata_1_ctr_T_8 = tail(_update_wdata_1_ctr_T_7, 1)
node _update_wdata_1_ctr_T_9 = mux(_update_wdata_1_ctr_T_6, UInt<3>(0h7), _update_wdata_1_ctr_T_8)
node _update_wdata_1_ctr_T_10 = mux(_update_wdata_1_ctr_T_1, _update_wdata_1_ctr_T_5, _update_wdata_1_ctr_T_9)
node _update_wdata_1_ctr_T_11 = eq(io.update_taken[1], UInt<1>(0h0))
node _update_wdata_1_ctr_T_12 = eq(io.update_old_ctr[1], UInt<1>(0h0))
node _update_wdata_1_ctr_T_13 = sub(io.update_old_ctr[1], UInt<1>(0h1))
node _update_wdata_1_ctr_T_14 = tail(_update_wdata_1_ctr_T_13, 1)
node _update_wdata_1_ctr_T_15 = mux(_update_wdata_1_ctr_T_12, UInt<1>(0h0), _update_wdata_1_ctr_T_14)
node _update_wdata_1_ctr_T_16 = eq(io.update_old_ctr[1], UInt<3>(0h7))
node _update_wdata_1_ctr_T_17 = add(io.update_old_ctr[1], UInt<1>(0h1))
node _update_wdata_1_ctr_T_18 = tail(_update_wdata_1_ctr_T_17, 1)
node _update_wdata_1_ctr_T_19 = mux(_update_wdata_1_ctr_T_16, UInt<3>(0h7), _update_wdata_1_ctr_T_18)
node _update_wdata_1_ctr_T_20 = mux(_update_wdata_1_ctr_T_11, _update_wdata_1_ctr_T_15, _update_wdata_1_ctr_T_19)
node _update_wdata_1_ctr_T_21 = mux(wrbypass_hit, _update_wdata_1_ctr_T_10, _update_wdata_1_ctr_T_20)
node _update_wdata_1_ctr_T_22 = mux(io.update_alloc[1], _update_wdata_1_ctr_T, _update_wdata_1_ctr_T_21)
connect update_wdata[1].ctr, _update_wdata_1_ctr_T_22
connect update_wdata[1].valid, UInt<1>(0h1)
connect update_wdata[1].tag, update_tag
node _update_hi_wdata_1_T = bits(io.update_u[1], 1, 1)
connect update_hi_wdata[1], _update_hi_wdata_1_T
node _update_lo_wdata_1_T = bits(io.update_u[1], 0, 0)
connect update_lo_wdata[1], _update_lo_wdata_1_T
node _update_wdata_2_ctr_T = mux(io.update_taken[2], UInt<3>(0h4), UInt<2>(0h3))
node _update_wdata_2_ctr_T_1 = eq(io.update_taken[2], UInt<1>(0h0))
node _update_wdata_2_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][2], UInt<1>(0h0))
node _update_wdata_2_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][2], UInt<1>(0h1))
node _update_wdata_2_ctr_T_4 = tail(_update_wdata_2_ctr_T_3, 1)
node _update_wdata_2_ctr_T_5 = mux(_update_wdata_2_ctr_T_2, UInt<1>(0h0), _update_wdata_2_ctr_T_4)
node _update_wdata_2_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][2], UInt<3>(0h7))
node _update_wdata_2_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][2], UInt<1>(0h1))
node _update_wdata_2_ctr_T_8 = tail(_update_wdata_2_ctr_T_7, 1)
node _update_wdata_2_ctr_T_9 = mux(_update_wdata_2_ctr_T_6, UInt<3>(0h7), _update_wdata_2_ctr_T_8)
node _update_wdata_2_ctr_T_10 = mux(_update_wdata_2_ctr_T_1, _update_wdata_2_ctr_T_5, _update_wdata_2_ctr_T_9)
node _update_wdata_2_ctr_T_11 = eq(io.update_taken[2], UInt<1>(0h0))
node _update_wdata_2_ctr_T_12 = eq(io.update_old_ctr[2], UInt<1>(0h0))
node _update_wdata_2_ctr_T_13 = sub(io.update_old_ctr[2], UInt<1>(0h1))
node _update_wdata_2_ctr_T_14 = tail(_update_wdata_2_ctr_T_13, 1)
node _update_wdata_2_ctr_T_15 = mux(_update_wdata_2_ctr_T_12, UInt<1>(0h0), _update_wdata_2_ctr_T_14)
node _update_wdata_2_ctr_T_16 = eq(io.update_old_ctr[2], UInt<3>(0h7))
node _update_wdata_2_ctr_T_17 = add(io.update_old_ctr[2], UInt<1>(0h1))
node _update_wdata_2_ctr_T_18 = tail(_update_wdata_2_ctr_T_17, 1)
node _update_wdata_2_ctr_T_19 = mux(_update_wdata_2_ctr_T_16, UInt<3>(0h7), _update_wdata_2_ctr_T_18)
node _update_wdata_2_ctr_T_20 = mux(_update_wdata_2_ctr_T_11, _update_wdata_2_ctr_T_15, _update_wdata_2_ctr_T_19)
node _update_wdata_2_ctr_T_21 = mux(wrbypass_hit, _update_wdata_2_ctr_T_10, _update_wdata_2_ctr_T_20)
node _update_wdata_2_ctr_T_22 = mux(io.update_alloc[2], _update_wdata_2_ctr_T, _update_wdata_2_ctr_T_21)
connect update_wdata[2].ctr, _update_wdata_2_ctr_T_22
connect update_wdata[2].valid, UInt<1>(0h1)
connect update_wdata[2].tag, update_tag
node _update_hi_wdata_2_T = bits(io.update_u[2], 1, 1)
connect update_hi_wdata[2], _update_hi_wdata_2_T
node _update_lo_wdata_2_T = bits(io.update_u[2], 0, 0)
connect update_lo_wdata[2], _update_lo_wdata_2_T
node _update_wdata_3_ctr_T = mux(io.update_taken[3], UInt<3>(0h4), UInt<2>(0h3))
node _update_wdata_3_ctr_T_1 = eq(io.update_taken[3], UInt<1>(0h0))
node _update_wdata_3_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][3], UInt<1>(0h0))
node _update_wdata_3_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][3], UInt<1>(0h1))
node _update_wdata_3_ctr_T_4 = tail(_update_wdata_3_ctr_T_3, 1)
node _update_wdata_3_ctr_T_5 = mux(_update_wdata_3_ctr_T_2, UInt<1>(0h0), _update_wdata_3_ctr_T_4)
node _update_wdata_3_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][3], UInt<3>(0h7))
node _update_wdata_3_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][3], UInt<1>(0h1))
node _update_wdata_3_ctr_T_8 = tail(_update_wdata_3_ctr_T_7, 1)
node _update_wdata_3_ctr_T_9 = mux(_update_wdata_3_ctr_T_6, UInt<3>(0h7), _update_wdata_3_ctr_T_8)
node _update_wdata_3_ctr_T_10 = mux(_update_wdata_3_ctr_T_1, _update_wdata_3_ctr_T_5, _update_wdata_3_ctr_T_9)
node _update_wdata_3_ctr_T_11 = eq(io.update_taken[3], UInt<1>(0h0))
node _update_wdata_3_ctr_T_12 = eq(io.update_old_ctr[3], UInt<1>(0h0))
node _update_wdata_3_ctr_T_13 = sub(io.update_old_ctr[3], UInt<1>(0h1))
node _update_wdata_3_ctr_T_14 = tail(_update_wdata_3_ctr_T_13, 1)
node _update_wdata_3_ctr_T_15 = mux(_update_wdata_3_ctr_T_12, UInt<1>(0h0), _update_wdata_3_ctr_T_14)
node _update_wdata_3_ctr_T_16 = eq(io.update_old_ctr[3], UInt<3>(0h7))
node _update_wdata_3_ctr_T_17 = add(io.update_old_ctr[3], UInt<1>(0h1))
node _update_wdata_3_ctr_T_18 = tail(_update_wdata_3_ctr_T_17, 1)
node _update_wdata_3_ctr_T_19 = mux(_update_wdata_3_ctr_T_16, UInt<3>(0h7), _update_wdata_3_ctr_T_18)
node _update_wdata_3_ctr_T_20 = mux(_update_wdata_3_ctr_T_11, _update_wdata_3_ctr_T_15, _update_wdata_3_ctr_T_19)
node _update_wdata_3_ctr_T_21 = mux(wrbypass_hit, _update_wdata_3_ctr_T_10, _update_wdata_3_ctr_T_20)
node _update_wdata_3_ctr_T_22 = mux(io.update_alloc[3], _update_wdata_3_ctr_T, _update_wdata_3_ctr_T_21)
connect update_wdata[3].ctr, _update_wdata_3_ctr_T_22
connect update_wdata[3].valid, UInt<1>(0h1)
connect update_wdata[3].tag, update_tag
node _update_hi_wdata_3_T = bits(io.update_u[3], 1, 1)
connect update_hi_wdata[3], _update_hi_wdata_3_T
node _update_lo_wdata_3_T = bits(io.update_u[3], 0, 0)
connect update_lo_wdata[3], _update_lo_wdata_3_T
node _T_42 = or(io.update_mask[0], io.update_mask[1])
node _T_43 = or(_T_42, io.update_mask[2])
node _T_44 = or(_T_43, io.update_mask[3])
when _T_44 :
node _T_45 = or(wrbypass_hits[0], wrbypass_hits[1])
when _T_45 :
wire _WIRE_4 : UInt<3>[4]
connect _WIRE_4[0], update_wdata[0].ctr
connect _WIRE_4[1], update_wdata[1].ctr
connect _WIRE_4[2], update_wdata[2].ctr
connect _WIRE_4[3], update_wdata[3].ctr
connect wrbypass[wrbypass_hit_idx], _WIRE_4
else :
wire _WIRE_5 : UInt<3>[4]
connect _WIRE_5[0], update_wdata[0].ctr
connect _WIRE_5[1], update_wdata[1].ctr
connect _WIRE_5[2], update_wdata[2].ctr
connect _WIRE_5[3], update_wdata[3].ctr
connect wrbypass[wrbypass_enq_idx], _WIRE_5
connect wrbypass_tags[wrbypass_enq_idx], update_tag
connect wrbypass_idxs[wrbypass_enq_idx], update_idx
node _wrbypass_enq_idx_T = add(wrbypass_enq_idx, UInt<1>(0h1))
node _wrbypass_enq_idx_T_1 = tail(_wrbypass_enq_idx_T, 1)
node _wrbypass_enq_idx_T_2 = bits(_wrbypass_enq_idx_T_1, 0, 0)
connect wrbypass_enq_idx, _wrbypass_enq_idx_T_2 | module TageTable_8( // @[tage.scala:24:7]
input clock, // @[tage.scala:24:7]
input reset, // @[tage.scala:24:7]
input io_f1_req_valid, // @[tage.scala:31:14]
input [39:0] io_f1_req_pc, // @[tage.scala:31:14]
input [63:0] io_f1_req_ghist, // @[tage.scala:31:14]
output io_f3_resp_0_valid, // @[tage.scala:31:14]
output [2:0] io_f3_resp_0_bits_ctr, // @[tage.scala:31:14]
output [1:0] io_f3_resp_0_bits_u, // @[tage.scala:31:14]
output io_f3_resp_1_valid, // @[tage.scala:31:14]
output [2:0] io_f3_resp_1_bits_ctr, // @[tage.scala:31:14]
output [1:0] io_f3_resp_1_bits_u, // @[tage.scala:31:14]
output io_f3_resp_2_valid, // @[tage.scala:31:14]
output [2:0] io_f3_resp_2_bits_ctr, // @[tage.scala:31:14]
output [1:0] io_f3_resp_2_bits_u, // @[tage.scala:31:14]
output io_f3_resp_3_valid, // @[tage.scala:31:14]
output [2:0] io_f3_resp_3_bits_ctr, // @[tage.scala:31:14]
output [1:0] io_f3_resp_3_bits_u, // @[tage.scala:31:14]
input io_update_mask_0, // @[tage.scala:31:14]
input io_update_mask_1, // @[tage.scala:31:14]
input io_update_mask_2, // @[tage.scala:31:14]
input io_update_mask_3, // @[tage.scala:31:14]
input io_update_taken_0, // @[tage.scala:31:14]
input io_update_taken_1, // @[tage.scala:31:14]
input io_update_taken_2, // @[tage.scala:31:14]
input io_update_taken_3, // @[tage.scala:31:14]
input io_update_alloc_0, // @[tage.scala:31:14]
input io_update_alloc_1, // @[tage.scala:31:14]
input io_update_alloc_2, // @[tage.scala:31:14]
input io_update_alloc_3, // @[tage.scala:31:14]
input [2:0] io_update_old_ctr_0, // @[tage.scala:31:14]
input [2:0] io_update_old_ctr_1, // @[tage.scala:31:14]
input [2:0] io_update_old_ctr_2, // @[tage.scala:31:14]
input [2:0] io_update_old_ctr_3, // @[tage.scala:31:14]
input [39:0] io_update_pc, // @[tage.scala:31:14]
input [63:0] io_update_hist, // @[tage.scala:31:14]
input io_update_u_mask_0, // @[tage.scala:31:14]
input io_update_u_mask_1, // @[tage.scala:31:14]
input io_update_u_mask_2, // @[tage.scala:31:14]
input io_update_u_mask_3, // @[tage.scala:31:14]
input [1:0] io_update_u_0, // @[tage.scala:31:14]
input [1:0] io_update_u_1, // @[tage.scala:31:14]
input [1:0] io_update_u_2, // @[tage.scala:31:14]
input [1:0] io_update_u_3 // @[tage.scala:31:14]
);
wire lo_us_MPORT_2_data_3; // @[tage.scala:137:8]
wire lo_us_MPORT_2_data_2; // @[tage.scala:137:8]
wire lo_us_MPORT_2_data_1; // @[tage.scala:137:8]
wire lo_us_MPORT_2_data_0; // @[tage.scala:137:8]
wire hi_us_MPORT_1_data_3; // @[tage.scala:130:8]
wire hi_us_MPORT_1_data_2; // @[tage.scala:130:8]
wire hi_us_MPORT_1_data_1; // @[tage.scala:130:8]
wire hi_us_MPORT_1_data_0; // @[tage.scala:130:8]
wire [11:0] table_MPORT_data_3; // @[tage.scala:123:8]
wire [11:0] table_MPORT_data_2; // @[tage.scala:123:8]
wire [11:0] table_MPORT_data_1; // @[tage.scala:123:8]
wire [11:0] table_MPORT_data_0; // @[tage.scala:123:8]
wire _s2_req_rtage_WIRE_7_valid; // @[tage.scala:97:87]
wire [7:0] _s2_req_rtage_WIRE_7_tag; // @[tage.scala:97:87]
wire [2:0] _s2_req_rtage_WIRE_7_ctr; // @[tage.scala:97:87]
wire _s2_req_rtage_WIRE_5_valid; // @[tage.scala:97:87]
wire [7:0] _s2_req_rtage_WIRE_5_tag; // @[tage.scala:97:87]
wire [2:0] _s2_req_rtage_WIRE_5_ctr; // @[tage.scala:97:87]
wire _s2_req_rtage_WIRE_3_valid; // @[tage.scala:97:87]
wire [7:0] _s2_req_rtage_WIRE_3_tag; // @[tage.scala:97:87]
wire [2:0] _s2_req_rtage_WIRE_3_ctr; // @[tage.scala:97:87]
wire _s2_req_rtage_WIRE_1_valid; // @[tage.scala:97:87]
wire [7:0] _s2_req_rtage_WIRE_1_tag; // @[tage.scala:97:87]
wire [2:0] _s2_req_rtage_WIRE_1_ctr; // @[tage.scala:97:87]
wire [47:0] _table_R0_data; // @[tage.scala:91:27]
wire [3:0] _lo_us_R0_data; // @[tage.scala:90:27]
wire [3:0] _hi_us_R0_data; // @[tage.scala:89:27]
wire io_f1_req_valid_0 = io_f1_req_valid; // @[tage.scala:24:7]
wire [39:0] io_f1_req_pc_0 = io_f1_req_pc; // @[tage.scala:24:7]
wire [63:0] io_f1_req_ghist_0 = io_f1_req_ghist; // @[tage.scala:24:7]
wire io_update_mask_0_0 = io_update_mask_0; // @[tage.scala:24:7]
wire io_update_mask_1_0 = io_update_mask_1; // @[tage.scala:24:7]
wire io_update_mask_2_0 = io_update_mask_2; // @[tage.scala:24:7]
wire io_update_mask_3_0 = io_update_mask_3; // @[tage.scala:24:7]
wire io_update_taken_0_0 = io_update_taken_0; // @[tage.scala:24:7]
wire io_update_taken_1_0 = io_update_taken_1; // @[tage.scala:24:7]
wire io_update_taken_2_0 = io_update_taken_2; // @[tage.scala:24:7]
wire io_update_taken_3_0 = io_update_taken_3; // @[tage.scala:24:7]
wire io_update_alloc_0_0 = io_update_alloc_0; // @[tage.scala:24:7]
wire io_update_alloc_1_0 = io_update_alloc_1; // @[tage.scala:24:7]
wire io_update_alloc_2_0 = io_update_alloc_2; // @[tage.scala:24:7]
wire io_update_alloc_3_0 = io_update_alloc_3; // @[tage.scala:24:7]
wire [2:0] io_update_old_ctr_0_0 = io_update_old_ctr_0; // @[tage.scala:24:7]
wire [2:0] io_update_old_ctr_1_0 = io_update_old_ctr_1; // @[tage.scala:24:7]
wire [2:0] io_update_old_ctr_2_0 = io_update_old_ctr_2; // @[tage.scala:24:7]
wire [2:0] io_update_old_ctr_3_0 = io_update_old_ctr_3; // @[tage.scala:24:7]
wire [39:0] io_update_pc_0 = io_update_pc; // @[tage.scala:24:7]
wire [63:0] io_update_hist_0 = io_update_hist; // @[tage.scala:24:7]
wire io_update_u_mask_0_0 = io_update_u_mask_0; // @[tage.scala:24:7]
wire io_update_u_mask_1_0 = io_update_u_mask_1; // @[tage.scala:24:7]
wire io_update_u_mask_2_0 = io_update_u_mask_2; // @[tage.scala:24:7]
wire io_update_u_mask_3_0 = io_update_u_mask_3; // @[tage.scala:24:7]
wire [1:0] io_update_u_0_0 = io_update_u_0; // @[tage.scala:24:7]
wire [1:0] io_update_u_1_0 = io_update_u_1; // @[tage.scala:24:7]
wire [1:0] io_update_u_2_0 = io_update_u_2; // @[tage.scala:24:7]
wire [1:0] io_update_u_3_0 = io_update_u_3; // @[tage.scala:24:7]
wire update_wdata_0_valid = 1'h1; // @[tage.scala:119:26]
wire update_wdata_1_valid = 1'h1; // @[tage.scala:119:26]
wire update_wdata_2_valid = 1'h1; // @[tage.scala:119:26]
wire update_wdata_3_valid = 1'h1; // @[tage.scala:119:26]
wire [2:0] io_f3_resp_0_bits_ctr_0; // @[tage.scala:24:7]
wire [1:0] io_f3_resp_0_bits_u_0; // @[tage.scala:24:7]
wire io_f3_resp_0_valid_0; // @[tage.scala:24:7]
wire [2:0] io_f3_resp_1_bits_ctr_0; // @[tage.scala:24:7]
wire [1:0] io_f3_resp_1_bits_u_0; // @[tage.scala:24:7]
wire io_f3_resp_1_valid_0; // @[tage.scala:24:7]
wire [2:0] io_f3_resp_2_bits_ctr_0; // @[tage.scala:24:7]
wire [1:0] io_f3_resp_2_bits_u_0; // @[tage.scala:24:7]
wire io_f3_resp_2_valid_0; // @[tage.scala:24:7]
wire [2:0] io_f3_resp_3_bits_ctr_0; // @[tage.scala:24:7]
wire [1:0] io_f3_resp_3_bits_u_0; // @[tage.scala:24:7]
wire io_f3_resp_3_valid_0; // @[tage.scala:24:7]
reg doing_reset; // @[tage.scala:72:28]
reg [7:0] reset_idx; // @[tage.scala:73:26]
wire [8:0] _reset_idx_T = {1'h0, reset_idx} + {8'h0, doing_reset}; // @[tage.scala:72:28, :73:26, :74:26]
wire [7:0] _reset_idx_T_1 = _reset_idx_T[7:0]; // @[tage.scala:74:26]
wire [7:0] idx_history = io_f1_req_ghist_0[7:0]; // @[tage.scala:24:7, :53:11]
wire [7:0] tag_history = io_f1_req_ghist_0[7:0]; // @[tage.scala:24:7, :53:11]
wire [27:0] _tag_T = io_f1_req_pc_0[39:12]; // @[frontend.scala:162:35]
wire [35:0] _idx_T = {_tag_T, io_f1_req_pc_0[11:4] ^ idx_history}; // @[frontend.scala:162:35]
wire [7:0] s1_hashed_idx = _idx_T[7:0]; // @[tage.scala:60:{29,43}]
wire [7:0] _s2_req_rtage_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :97:40]
wire [7:0] _s2_req_rhius_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :98:32]
wire [7:0] _s2_req_rlous_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :99:32]
wire [27:0] _tag_T_1 = {_tag_T[27:8], _tag_T[7:0] ^ tag_history}; // @[tage.scala:53:11, :62:{30,50}]
wire [7:0] s1_tag = _tag_T_1[7:0]; // @[tage.scala:62:{50,64}]
wire [11:0] _s2_req_rtage_WIRE_2 = _table_R0_data[11:0]; // @[tage.scala:91:27, :97:87]
wire [11:0] _s2_req_rtage_WIRE_4 = _table_R0_data[23:12]; // @[tage.scala:91:27, :97:87]
wire [11:0] _s2_req_rtage_WIRE_6 = _table_R0_data[35:24]; // @[tage.scala:91:27, :97:87]
wire [11:0] _s2_req_rtage_WIRE_8 = _table_R0_data[47:36]; // @[tage.scala:91:27, :97:87]
reg [7:0] s2_tag; // @[tage.scala:95:29]
wire _s2_req_rtage_T_2; // @[tage.scala:97:87]
wire [7:0] _s2_req_rtage_T_1; // @[tage.scala:97:87]
wire s2_req_rtage_0_valid = _s2_req_rtage_WIRE_1_valid; // @[tage.scala:97:{29,87}]
wire [2:0] _s2_req_rtage_T; // @[tage.scala:97:87]
wire [7:0] s2_req_rtage_0_tag = _s2_req_rtage_WIRE_1_tag; // @[tage.scala:97:{29,87}]
wire [2:0] s2_req_rtage_0_ctr = _s2_req_rtage_WIRE_1_ctr; // @[tage.scala:97:{29,87}]
assign _s2_req_rtage_T = _s2_req_rtage_WIRE_2[2:0]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_1_ctr = _s2_req_rtage_T; // @[tage.scala:97:87]
assign _s2_req_rtage_T_1 = _s2_req_rtage_WIRE_2[10:3]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_1_tag = _s2_req_rtage_T_1; // @[tage.scala:97:87]
assign _s2_req_rtage_T_2 = _s2_req_rtage_WIRE_2[11]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_1_valid = _s2_req_rtage_T_2; // @[tage.scala:97:87]
wire _s2_req_rtage_T_5; // @[tage.scala:97:87]
wire [7:0] _s2_req_rtage_T_4; // @[tage.scala:97:87]
wire s2_req_rtage_1_valid = _s2_req_rtage_WIRE_3_valid; // @[tage.scala:97:{29,87}]
wire [2:0] _s2_req_rtage_T_3; // @[tage.scala:97:87]
wire [7:0] s2_req_rtage_1_tag = _s2_req_rtage_WIRE_3_tag; // @[tage.scala:97:{29,87}]
wire [2:0] s2_req_rtage_1_ctr = _s2_req_rtage_WIRE_3_ctr; // @[tage.scala:97:{29,87}]
assign _s2_req_rtage_T_3 = _s2_req_rtage_WIRE_4[2:0]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_3_ctr = _s2_req_rtage_T_3; // @[tage.scala:97:87]
assign _s2_req_rtage_T_4 = _s2_req_rtage_WIRE_4[10:3]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_3_tag = _s2_req_rtage_T_4; // @[tage.scala:97:87]
assign _s2_req_rtage_T_5 = _s2_req_rtage_WIRE_4[11]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_3_valid = _s2_req_rtage_T_5; // @[tage.scala:97:87]
wire _s2_req_rtage_T_8; // @[tage.scala:97:87]
wire [7:0] _s2_req_rtage_T_7; // @[tage.scala:97:87]
wire s2_req_rtage_2_valid = _s2_req_rtage_WIRE_5_valid; // @[tage.scala:97:{29,87}]
wire [2:0] _s2_req_rtage_T_6; // @[tage.scala:97:87]
wire [7:0] s2_req_rtage_2_tag = _s2_req_rtage_WIRE_5_tag; // @[tage.scala:97:{29,87}]
wire [2:0] s2_req_rtage_2_ctr = _s2_req_rtage_WIRE_5_ctr; // @[tage.scala:97:{29,87}]
assign _s2_req_rtage_T_6 = _s2_req_rtage_WIRE_6[2:0]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_5_ctr = _s2_req_rtage_T_6; // @[tage.scala:97:87]
assign _s2_req_rtage_T_7 = _s2_req_rtage_WIRE_6[10:3]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_5_tag = _s2_req_rtage_T_7; // @[tage.scala:97:87]
assign _s2_req_rtage_T_8 = _s2_req_rtage_WIRE_6[11]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_5_valid = _s2_req_rtage_T_8; // @[tage.scala:97:87]
wire _s2_req_rtage_T_11; // @[tage.scala:97:87]
wire [7:0] _s2_req_rtage_T_10; // @[tage.scala:97:87]
wire s2_req_rtage_3_valid = _s2_req_rtage_WIRE_7_valid; // @[tage.scala:97:{29,87}]
wire [2:0] _s2_req_rtage_T_9; // @[tage.scala:97:87]
wire [7:0] s2_req_rtage_3_tag = _s2_req_rtage_WIRE_7_tag; // @[tage.scala:97:{29,87}]
wire [2:0] s2_req_rtage_3_ctr = _s2_req_rtage_WIRE_7_ctr; // @[tage.scala:97:{29,87}]
assign _s2_req_rtage_T_9 = _s2_req_rtage_WIRE_8[2:0]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_7_ctr = _s2_req_rtage_T_9; // @[tage.scala:97:87]
assign _s2_req_rtage_T_10 = _s2_req_rtage_WIRE_8[10:3]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_7_tag = _s2_req_rtage_T_10; // @[tage.scala:97:87]
assign _s2_req_rtage_T_11 = _s2_req_rtage_WIRE_8[11]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_7_valid = _s2_req_rtage_T_11; // @[tage.scala:97:87]
wire _s2_req_rhits_T = s2_req_rtage_0_tag == s2_tag; // @[tage.scala:95:29, :97:29, :100:69]
wire _s2_req_rhits_T_1 = s2_req_rtage_0_valid & _s2_req_rhits_T; // @[tage.scala:97:29, :100:{60,69}]
wire _s2_req_rhits_T_2 = ~doing_reset; // @[tage.scala:72:28, :100:83]
wire _s2_req_rhits_T_3 = _s2_req_rhits_T_1 & _s2_req_rhits_T_2; // @[tage.scala:100:{60,80,83}]
wire s2_req_rhits_0 = _s2_req_rhits_T_3; // @[tage.scala:100:{29,80}]
wire _s2_req_rhits_T_4 = s2_req_rtage_1_tag == s2_tag; // @[tage.scala:95:29, :97:29, :100:69]
wire _s2_req_rhits_T_5 = s2_req_rtage_1_valid & _s2_req_rhits_T_4; // @[tage.scala:97:29, :100:{60,69}]
wire _s2_req_rhits_T_6 = ~doing_reset; // @[tage.scala:72:28, :100:83]
wire _s2_req_rhits_T_7 = _s2_req_rhits_T_5 & _s2_req_rhits_T_6; // @[tage.scala:100:{60,80,83}]
wire s2_req_rhits_1 = _s2_req_rhits_T_7; // @[tage.scala:100:{29,80}]
wire _s2_req_rhits_T_8 = s2_req_rtage_2_tag == s2_tag; // @[tage.scala:95:29, :97:29, :100:69]
wire _s2_req_rhits_T_9 = s2_req_rtage_2_valid & _s2_req_rhits_T_8; // @[tage.scala:97:29, :100:{60,69}]
wire _s2_req_rhits_T_10 = ~doing_reset; // @[tage.scala:72:28, :100:83]
wire _s2_req_rhits_T_11 = _s2_req_rhits_T_9 & _s2_req_rhits_T_10; // @[tage.scala:100:{60,80,83}]
wire s2_req_rhits_2 = _s2_req_rhits_T_11; // @[tage.scala:100:{29,80}]
wire _s2_req_rhits_T_12 = s2_req_rtage_3_tag == s2_tag; // @[tage.scala:95:29, :97:29, :100:69]
wire _s2_req_rhits_T_13 = s2_req_rtage_3_valid & _s2_req_rhits_T_12; // @[tage.scala:97:29, :100:{60,69}]
wire _s2_req_rhits_T_14 = ~doing_reset; // @[tage.scala:72:28, :100:83]
wire _s2_req_rhits_T_15 = _s2_req_rhits_T_13 & _s2_req_rhits_T_14; // @[tage.scala:100:{60,80,83}]
wire s2_req_rhits_3 = _s2_req_rhits_T_15; // @[tage.scala:100:{29,80}]
reg io_f3_resp_0_valid_REG; // @[tage.scala:104:38]
assign io_f3_resp_0_valid_0 = io_f3_resp_0_valid_REG; // @[tage.scala:24:7, :104:38]
wire [1:0] _io_f3_resp_0_bits_u_T = {_hi_us_R0_data[0], _lo_us_R0_data[0]}; // @[tage.scala:89:27, :90:27, :105:42]
reg [1:0] io_f3_resp_0_bits_u_REG; // @[tage.scala:105:38]
assign io_f3_resp_0_bits_u_0 = io_f3_resp_0_bits_u_REG; // @[tage.scala:24:7, :105:38]
reg [2:0] io_f3_resp_0_bits_ctr_REG; // @[tage.scala:106:38]
assign io_f3_resp_0_bits_ctr_0 = io_f3_resp_0_bits_ctr_REG; // @[tage.scala:24:7, :106:38]
reg io_f3_resp_1_valid_REG; // @[tage.scala:104:38]
assign io_f3_resp_1_valid_0 = io_f3_resp_1_valid_REG; // @[tage.scala:24:7, :104:38]
wire [1:0] _io_f3_resp_1_bits_u_T = {_hi_us_R0_data[1], _lo_us_R0_data[1]}; // @[tage.scala:89:27, :90:27, :105:42]
reg [1:0] io_f3_resp_1_bits_u_REG; // @[tage.scala:105:38]
assign io_f3_resp_1_bits_u_0 = io_f3_resp_1_bits_u_REG; // @[tage.scala:24:7, :105:38]
reg [2:0] io_f3_resp_1_bits_ctr_REG; // @[tage.scala:106:38]
assign io_f3_resp_1_bits_ctr_0 = io_f3_resp_1_bits_ctr_REG; // @[tage.scala:24:7, :106:38]
reg io_f3_resp_2_valid_REG; // @[tage.scala:104:38]
assign io_f3_resp_2_valid_0 = io_f3_resp_2_valid_REG; // @[tage.scala:24:7, :104:38]
wire [1:0] _io_f3_resp_2_bits_u_T = {_hi_us_R0_data[2], _lo_us_R0_data[2]}; // @[tage.scala:89:27, :90:27, :105:42]
reg [1:0] io_f3_resp_2_bits_u_REG; // @[tage.scala:105:38]
assign io_f3_resp_2_bits_u_0 = io_f3_resp_2_bits_u_REG; // @[tage.scala:24:7, :105:38]
reg [2:0] io_f3_resp_2_bits_ctr_REG; // @[tage.scala:106:38]
assign io_f3_resp_2_bits_ctr_0 = io_f3_resp_2_bits_ctr_REG; // @[tage.scala:24:7, :106:38]
reg io_f3_resp_3_valid_REG; // @[tage.scala:104:38]
assign io_f3_resp_3_valid_0 = io_f3_resp_3_valid_REG; // @[tage.scala:24:7, :104:38]
wire [1:0] _io_f3_resp_3_bits_u_T = {_hi_us_R0_data[3], _lo_us_R0_data[3]}; // @[tage.scala:89:27, :90:27, :105:42]
reg [1:0] io_f3_resp_3_bits_u_REG; // @[tage.scala:105:38]
assign io_f3_resp_3_bits_u_0 = io_f3_resp_3_bits_u_REG; // @[tage.scala:24:7, :105:38]
reg [2:0] io_f3_resp_3_bits_ctr_REG; // @[tage.scala:106:38]
assign io_f3_resp_3_bits_ctr_0 = io_f3_resp_3_bits_ctr_REG; // @[tage.scala:24:7, :106:38]
reg [19:0] clear_u_ctr; // @[tage.scala:109:28]
wire [20:0] _clear_u_ctr_T = {1'h0, clear_u_ctr} + 21'h1; // @[tage.scala:109:28, :110:85]
wire [19:0] _clear_u_ctr_T_1 = _clear_u_ctr_T[19:0]; // @[tage.scala:110:85]
wire [10:0] _doing_clear_u_T = clear_u_ctr[10:0]; // @[tage.scala:109:28, :112:34]
wire doing_clear_u = _doing_clear_u_T == 11'h0; // @[tage.scala:112:{34,61}]
wire _doing_clear_u_hi_T = clear_u_ctr[19]; // @[tage.scala:109:28, :113:54]
wire _doing_clear_u_lo_T = clear_u_ctr[19]; // @[tage.scala:109:28, :113:54, :114:54]
wire _doing_clear_u_hi_T_1 = _doing_clear_u_hi_T; // @[tage.scala:113:{54,95}]
wire doing_clear_u_hi = doing_clear_u & _doing_clear_u_hi_T_1; // @[tage.scala:112:61, :113:{40,95}]
wire _doing_clear_u_lo_T_1 = ~_doing_clear_u_lo_T; // @[tage.scala:114:{54,95}]
wire doing_clear_u_lo = doing_clear_u & _doing_clear_u_lo_T_1; // @[tage.scala:112:61, :114:{40,95}]
wire [8:0] clear_u_idx = clear_u_ctr[19:11]; // @[tage.scala:109:28, :115:33]
wire [7:0] idx_history_1 = io_update_hist_0[7:0]; // @[tage.scala:24:7, :53:11]
wire [7:0] tag_history_1 = io_update_hist_0[7:0]; // @[tage.scala:24:7, :53:11]
wire [27:0] _tag_T_2 = io_update_pc_0[39:12]; // @[frontend.scala:162:35]
wire [35:0] _idx_T_1 = {_tag_T_2, io_update_pc_0[11:4] ^ idx_history_1}; // @[frontend.scala:162:35]
wire [7:0] update_idx = _idx_T_1[7:0]; // @[tage.scala:60:{29,43}]
wire [27:0] _tag_T_3 = {_tag_T_2[27:8], _tag_T_2[7:0] ^ tag_history_1}; // @[tage.scala:53:11, :62:{30,50}]
wire [7:0] update_tag = _tag_T_3[7:0]; // @[tage.scala:62:{50,64}]
wire [7:0] update_wdata_0_tag = update_tag; // @[tage.scala:62:64, :119:26]
wire [7:0] update_wdata_1_tag = update_tag; // @[tage.scala:62:64, :119:26]
wire [7:0] update_wdata_2_tag = update_tag; // @[tage.scala:62:64, :119:26]
wire [7:0] update_wdata_3_tag = update_tag; // @[tage.scala:62:64, :119:26]
wire [2:0] _update_wdata_0_ctr_T_22; // @[tage.scala:155:33]
wire [2:0] _update_wdata_1_ctr_T_22; // @[tage.scala:155:33]
wire [2:0] _update_wdata_2_ctr_T_22; // @[tage.scala:155:33]
wire [2:0] _update_wdata_3_ctr_T_22; // @[tage.scala:155:33]
wire [2:0] update_wdata_0_ctr; // @[tage.scala:119:26]
wire [2:0] update_wdata_1_ctr; // @[tage.scala:119:26]
wire [2:0] update_wdata_2_ctr; // @[tage.scala:119:26]
wire [2:0] update_wdata_3_ctr; // @[tage.scala:119:26]
wire [8:0] hi = {1'h1, update_wdata_0_tag}; // @[tage.scala:119:26, :123:102]
wire [8:0] hi_1 = {1'h1, update_wdata_1_tag}; // @[tage.scala:119:26, :123:102]
wire [8:0] hi_2 = {1'h1, update_wdata_2_tag}; // @[tage.scala:119:26, :123:102]
wire [8:0] hi_3 = {1'h1, update_wdata_3_tag}; // @[tage.scala:119:26, :123:102]
assign table_MPORT_data_0 = doing_reset ? 12'h0 : {hi, update_wdata_0_ctr}; // @[tage.scala:72:28, :119:26, :123:{8,102}]
assign table_MPORT_data_1 = doing_reset ? 12'h0 : {hi_1, update_wdata_1_ctr}; // @[tage.scala:72:28, :119:26, :123:{8,102}]
assign table_MPORT_data_2 = doing_reset ? 12'h0 : {hi_2, update_wdata_2_ctr}; // @[tage.scala:72:28, :119:26, :123:{8,102}]
assign table_MPORT_data_3 = doing_reset ? 12'h0 : {hi_3, update_wdata_3_ctr}; // @[tage.scala:72:28, :119:26, :123:{8,102}]
wire [1:0] lo = {io_update_mask_1_0, io_update_mask_0_0}; // @[tage.scala:24:7, :124:90]
wire [1:0] hi_4 = {io_update_mask_3_0, io_update_mask_2_0}; // @[tage.scala:24:7, :124:90]
wire _update_hi_wdata_0_T; // @[tage.scala:166:44]
wire _update_hi_wdata_1_T; // @[tage.scala:166:44]
wire _update_hi_wdata_2_T; // @[tage.scala:166:44]
wire _update_hi_wdata_3_T; // @[tage.scala:166:44]
wire update_hi_wdata_0; // @[tage.scala:127:29]
wire update_hi_wdata_1; // @[tage.scala:127:29]
wire update_hi_wdata_2; // @[tage.scala:127:29]
wire update_hi_wdata_3; // @[tage.scala:127:29]
wire _T_20 = doing_reset | doing_clear_u_hi; // @[tage.scala:72:28, :113:40, :130:21]
assign hi_us_MPORT_1_data_0 = ~_T_20 & update_hi_wdata_0; // @[tage.scala:127:29, :130:{8,21}]
assign hi_us_MPORT_1_data_1 = ~_T_20 & update_hi_wdata_1; // @[tage.scala:127:29, :130:{8,21}]
assign hi_us_MPORT_1_data_2 = ~_T_20 & update_hi_wdata_2; // @[tage.scala:127:29, :130:{8,21}]
assign hi_us_MPORT_1_data_3 = ~_T_20 & update_hi_wdata_3; // @[tage.scala:127:29, :130:{8,21}]
wire [1:0] _GEN = {io_update_u_mask_1_0, io_update_u_mask_0_0}; // @[tage.scala:24:7, :131:80]
wire [1:0] lo_1; // @[tage.scala:131:80]
assign lo_1 = _GEN; // @[tage.scala:131:80]
wire [1:0] lo_2; // @[tage.scala:138:80]
assign lo_2 = _GEN; // @[tage.scala:131:80, :138:80]
wire [1:0] _GEN_0 = {io_update_u_mask_3_0, io_update_u_mask_2_0}; // @[tage.scala:24:7, :131:80]
wire [1:0] hi_5; // @[tage.scala:131:80]
assign hi_5 = _GEN_0; // @[tage.scala:131:80]
wire [1:0] hi_6; // @[tage.scala:138:80]
assign hi_6 = _GEN_0; // @[tage.scala:131:80, :138:80]
wire _update_lo_wdata_0_T; // @[tage.scala:167:44]
wire _update_lo_wdata_1_T; // @[tage.scala:167:44]
wire _update_lo_wdata_2_T; // @[tage.scala:167:44]
wire _update_lo_wdata_3_T; // @[tage.scala:167:44]
wire update_lo_wdata_0; // @[tage.scala:134:29]
wire update_lo_wdata_1; // @[tage.scala:134:29]
wire update_lo_wdata_2; // @[tage.scala:134:29]
wire update_lo_wdata_3; // @[tage.scala:134:29]
wire _T_33 = doing_reset | doing_clear_u_lo; // @[tage.scala:72:28, :114:40, :137:21]
assign lo_us_MPORT_2_data_0 = ~_T_33 & update_lo_wdata_0; // @[tage.scala:134:29, :137:{8,21}]
assign lo_us_MPORT_2_data_1 = ~_T_33 & update_lo_wdata_1; // @[tage.scala:134:29, :137:{8,21}]
assign lo_us_MPORT_2_data_2 = ~_T_33 & update_lo_wdata_2; // @[tage.scala:134:29, :137:{8,21}]
assign lo_us_MPORT_2_data_3 = ~_T_33 & update_lo_wdata_3; // @[tage.scala:134:29, :137:{8,21}]
reg [7:0] wrbypass_tags_0; // @[tage.scala:141:29]
reg [7:0] wrbypass_tags_1; // @[tage.scala:141:29]
reg [7:0] wrbypass_idxs_0; // @[tage.scala:142:29]
reg [7:0] wrbypass_idxs_1; // @[tage.scala:142:29]
reg [2:0] wrbypass_0_0; // @[tage.scala:143:29]
reg [2:0] wrbypass_0_1; // @[tage.scala:143:29]
reg [2:0] wrbypass_0_2; // @[tage.scala:143:29]
reg [2:0] wrbypass_0_3; // @[tage.scala:143:29]
reg [2:0] wrbypass_1_0; // @[tage.scala:143:29]
reg [2:0] wrbypass_1_1; // @[tage.scala:143:29]
reg [2:0] wrbypass_1_2; // @[tage.scala:143:29]
reg [2:0] wrbypass_1_3; // @[tage.scala:143:29]
reg wrbypass_enq_idx; // @[tage.scala:144:33]
wire _wrbypass_hits_T = ~doing_reset; // @[tage.scala:72:28, :100:83, :147:5]
wire _wrbypass_hits_T_1 = wrbypass_tags_0 == update_tag; // @[tage.scala:62:64, :141:29, :148:22]
wire _wrbypass_hits_T_2 = _wrbypass_hits_T & _wrbypass_hits_T_1; // @[tage.scala:147:{5,18}, :148:22]
wire _wrbypass_hits_T_3 = wrbypass_idxs_0 == update_idx; // @[tage.scala:60:43, :142:29, :149:22]
wire _wrbypass_hits_T_4 = _wrbypass_hits_T_2 & _wrbypass_hits_T_3; // @[tage.scala:147:18, :148:37, :149:22]
wire wrbypass_hits_0 = _wrbypass_hits_T_4; // @[tage.scala:146:33, :148:37]
wire _wrbypass_hits_T_5 = ~doing_reset; // @[tage.scala:72:28, :100:83, :147:5]
wire _wrbypass_hits_T_6 = wrbypass_tags_1 == update_tag; // @[tage.scala:62:64, :141:29, :148:22]
wire _wrbypass_hits_T_7 = _wrbypass_hits_T_5 & _wrbypass_hits_T_6; // @[tage.scala:147:{5,18}, :148:22]
wire _wrbypass_hits_T_8 = wrbypass_idxs_1 == update_idx; // @[tage.scala:60:43, :142:29, :149:22]
wire _wrbypass_hits_T_9 = _wrbypass_hits_T_7 & _wrbypass_hits_T_8; // @[tage.scala:147:18, :148:37, :149:22]
wire wrbypass_hits_1 = _wrbypass_hits_T_9; // @[tage.scala:146:33, :148:37]
wire wrbypass_hit = wrbypass_hits_0 | wrbypass_hits_1; // @[tage.scala:146:33, :151:48]
wire wrbypass_hit_idx = ~wrbypass_hits_0; // @[Mux.scala:50:70]
wire [2:0] _update_wdata_0_ctr_T = io_update_taken_0_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :156:10]
wire _update_wdata_0_ctr_T_1 = ~io_update_taken_0_0; // @[tage.scala:24:7, :67:9]
wire [2:0] _GEN_1 = wrbypass_hit_idx ? wrbypass_1_0 : wrbypass_0_0; // @[Mux.scala:50:70]
wire [2:0] _GEN_2 = wrbypass_hit_idx ? wrbypass_1_1 : wrbypass_0_1; // @[Mux.scala:50:70]
wire [2:0] _GEN_3 = wrbypass_hit_idx ? wrbypass_1_2 : wrbypass_0_2; // @[Mux.scala:50:70]
wire [2:0] _GEN_4 = wrbypass_hit_idx ? wrbypass_1_3 : wrbypass_0_3; // @[Mux.scala:50:70]
wire _update_wdata_0_ctr_T_2 = _GEN_1 == 3'h0; // @[tage.scala:67:25]
wire [3:0] _GEN_5 = {1'h0, _GEN_1}; // @[tage.scala:67:{25,43}]
wire [3:0] _update_wdata_0_ctr_T_3 = _GEN_5 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_0_ctr_T_4 = _update_wdata_0_ctr_T_3[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_0_ctr_T_5 = _update_wdata_0_ctr_T_2 ? 3'h0 : _update_wdata_0_ctr_T_4; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_0_ctr_T_6 = &_GEN_1; // @[tage.scala:67:25, :68:25]
wire [3:0] _update_wdata_0_ctr_T_7 = _GEN_5 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_0_ctr_T_8 = _update_wdata_0_ctr_T_7[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_0_ctr_T_9 = _update_wdata_0_ctr_T_6 ? 3'h7 : _update_wdata_0_ctr_T_8; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_0_ctr_T_10 = _update_wdata_0_ctr_T_1 ? _update_wdata_0_ctr_T_5 : _update_wdata_0_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20]
wire _update_wdata_0_ctr_T_11 = ~io_update_taken_0_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_0_ctr_T_12 = io_update_old_ctr_0_0 == 3'h0; // @[tage.scala:24:7, :67:25]
wire [3:0] _GEN_6 = {1'h0, io_update_old_ctr_0_0}; // @[tage.scala:24:7, :67:43]
wire [3:0] _update_wdata_0_ctr_T_13 = _GEN_6 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_0_ctr_T_14 = _update_wdata_0_ctr_T_13[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_0_ctr_T_15 = _update_wdata_0_ctr_T_12 ? 3'h0 : _update_wdata_0_ctr_T_14; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_0_ctr_T_16 = &io_update_old_ctr_0_0; // @[tage.scala:24:7, :68:25]
wire [3:0] _update_wdata_0_ctr_T_17 = _GEN_6 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_0_ctr_T_18 = _update_wdata_0_ctr_T_17[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_0_ctr_T_19 = _update_wdata_0_ctr_T_16 ? 3'h7 : _update_wdata_0_ctr_T_18; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_0_ctr_T_20 = _update_wdata_0_ctr_T_11 ? _update_wdata_0_ctr_T_15 : _update_wdata_0_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20]
wire [2:0] _update_wdata_0_ctr_T_21 = wrbypass_hit ? _update_wdata_0_ctr_T_10 : _update_wdata_0_ctr_T_20; // @[tage.scala:67:8, :151:48, :159:10]
assign _update_wdata_0_ctr_T_22 = io_update_alloc_0_0 ? _update_wdata_0_ctr_T : _update_wdata_0_ctr_T_21; // @[tage.scala:24:7, :155:33, :156:10, :159:10]
assign update_wdata_0_ctr = _update_wdata_0_ctr_T_22; // @[tage.scala:119:26, :155:33]
assign _update_hi_wdata_0_T = io_update_u_0_0[1]; // @[tage.scala:24:7, :166:44]
assign update_hi_wdata_0 = _update_hi_wdata_0_T; // @[tage.scala:127:29, :166:44]
assign _update_lo_wdata_0_T = io_update_u_0_0[0]; // @[tage.scala:24:7, :167:44]
assign update_lo_wdata_0 = _update_lo_wdata_0_T; // @[tage.scala:134:29, :167:44]
wire [2:0] _update_wdata_1_ctr_T = io_update_taken_1_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :156:10]
wire _update_wdata_1_ctr_T_1 = ~io_update_taken_1_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_1_ctr_T_2 = _GEN_2 == 3'h0; // @[tage.scala:67:25]
wire [3:0] _GEN_7 = {1'h0, _GEN_2}; // @[tage.scala:67:{25,43}]
wire [3:0] _update_wdata_1_ctr_T_3 = _GEN_7 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_1_ctr_T_4 = _update_wdata_1_ctr_T_3[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_1_ctr_T_5 = _update_wdata_1_ctr_T_2 ? 3'h0 : _update_wdata_1_ctr_T_4; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_1_ctr_T_6 = &_GEN_2; // @[tage.scala:67:25, :68:25]
wire [3:0] _update_wdata_1_ctr_T_7 = _GEN_7 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_1_ctr_T_8 = _update_wdata_1_ctr_T_7[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_1_ctr_T_9 = _update_wdata_1_ctr_T_6 ? 3'h7 : _update_wdata_1_ctr_T_8; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_1_ctr_T_10 = _update_wdata_1_ctr_T_1 ? _update_wdata_1_ctr_T_5 : _update_wdata_1_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20]
wire _update_wdata_1_ctr_T_11 = ~io_update_taken_1_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_1_ctr_T_12 = io_update_old_ctr_1_0 == 3'h0; // @[tage.scala:24:7, :67:25]
wire [3:0] _GEN_8 = {1'h0, io_update_old_ctr_1_0}; // @[tage.scala:24:7, :67:43]
wire [3:0] _update_wdata_1_ctr_T_13 = _GEN_8 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_1_ctr_T_14 = _update_wdata_1_ctr_T_13[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_1_ctr_T_15 = _update_wdata_1_ctr_T_12 ? 3'h0 : _update_wdata_1_ctr_T_14; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_1_ctr_T_16 = &io_update_old_ctr_1_0; // @[tage.scala:24:7, :68:25]
wire [3:0] _update_wdata_1_ctr_T_17 = _GEN_8 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_1_ctr_T_18 = _update_wdata_1_ctr_T_17[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_1_ctr_T_19 = _update_wdata_1_ctr_T_16 ? 3'h7 : _update_wdata_1_ctr_T_18; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_1_ctr_T_20 = _update_wdata_1_ctr_T_11 ? _update_wdata_1_ctr_T_15 : _update_wdata_1_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20]
wire [2:0] _update_wdata_1_ctr_T_21 = wrbypass_hit ? _update_wdata_1_ctr_T_10 : _update_wdata_1_ctr_T_20; // @[tage.scala:67:8, :151:48, :159:10]
assign _update_wdata_1_ctr_T_22 = io_update_alloc_1_0 ? _update_wdata_1_ctr_T : _update_wdata_1_ctr_T_21; // @[tage.scala:24:7, :155:33, :156:10, :159:10]
assign update_wdata_1_ctr = _update_wdata_1_ctr_T_22; // @[tage.scala:119:26, :155:33]
assign _update_hi_wdata_1_T = io_update_u_1_0[1]; // @[tage.scala:24:7, :166:44]
assign update_hi_wdata_1 = _update_hi_wdata_1_T; // @[tage.scala:127:29, :166:44]
assign _update_lo_wdata_1_T = io_update_u_1_0[0]; // @[tage.scala:24:7, :167:44]
assign update_lo_wdata_1 = _update_lo_wdata_1_T; // @[tage.scala:134:29, :167:44]
wire [2:0] _update_wdata_2_ctr_T = io_update_taken_2_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :156:10]
wire _update_wdata_2_ctr_T_1 = ~io_update_taken_2_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_2_ctr_T_2 = _GEN_3 == 3'h0; // @[tage.scala:67:25]
wire [3:0] _GEN_9 = {1'h0, _GEN_3}; // @[tage.scala:67:{25,43}]
wire [3:0] _update_wdata_2_ctr_T_3 = _GEN_9 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_2_ctr_T_4 = _update_wdata_2_ctr_T_3[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_2_ctr_T_5 = _update_wdata_2_ctr_T_2 ? 3'h0 : _update_wdata_2_ctr_T_4; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_2_ctr_T_6 = &_GEN_3; // @[tage.scala:67:25, :68:25]
wire [3:0] _update_wdata_2_ctr_T_7 = _GEN_9 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_2_ctr_T_8 = _update_wdata_2_ctr_T_7[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_2_ctr_T_9 = _update_wdata_2_ctr_T_6 ? 3'h7 : _update_wdata_2_ctr_T_8; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_2_ctr_T_10 = _update_wdata_2_ctr_T_1 ? _update_wdata_2_ctr_T_5 : _update_wdata_2_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20]
wire _update_wdata_2_ctr_T_11 = ~io_update_taken_2_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_2_ctr_T_12 = io_update_old_ctr_2_0 == 3'h0; // @[tage.scala:24:7, :67:25]
wire [3:0] _GEN_10 = {1'h0, io_update_old_ctr_2_0}; // @[tage.scala:24:7, :67:43]
wire [3:0] _update_wdata_2_ctr_T_13 = _GEN_10 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_2_ctr_T_14 = _update_wdata_2_ctr_T_13[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_2_ctr_T_15 = _update_wdata_2_ctr_T_12 ? 3'h0 : _update_wdata_2_ctr_T_14; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_2_ctr_T_16 = &io_update_old_ctr_2_0; // @[tage.scala:24:7, :68:25]
wire [3:0] _update_wdata_2_ctr_T_17 = _GEN_10 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_2_ctr_T_18 = _update_wdata_2_ctr_T_17[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_2_ctr_T_19 = _update_wdata_2_ctr_T_16 ? 3'h7 : _update_wdata_2_ctr_T_18; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_2_ctr_T_20 = _update_wdata_2_ctr_T_11 ? _update_wdata_2_ctr_T_15 : _update_wdata_2_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20]
wire [2:0] _update_wdata_2_ctr_T_21 = wrbypass_hit ? _update_wdata_2_ctr_T_10 : _update_wdata_2_ctr_T_20; // @[tage.scala:67:8, :151:48, :159:10]
assign _update_wdata_2_ctr_T_22 = io_update_alloc_2_0 ? _update_wdata_2_ctr_T : _update_wdata_2_ctr_T_21; // @[tage.scala:24:7, :155:33, :156:10, :159:10]
assign update_wdata_2_ctr = _update_wdata_2_ctr_T_22; // @[tage.scala:119:26, :155:33]
assign _update_hi_wdata_2_T = io_update_u_2_0[1]; // @[tage.scala:24:7, :166:44]
assign update_hi_wdata_2 = _update_hi_wdata_2_T; // @[tage.scala:127:29, :166:44]
assign _update_lo_wdata_2_T = io_update_u_2_0[0]; // @[tage.scala:24:7, :167:44]
assign update_lo_wdata_2 = _update_lo_wdata_2_T; // @[tage.scala:134:29, :167:44]
wire [2:0] _update_wdata_3_ctr_T = io_update_taken_3_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :156:10]
wire _update_wdata_3_ctr_T_1 = ~io_update_taken_3_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_3_ctr_T_2 = _GEN_4 == 3'h0; // @[tage.scala:67:25]
wire [3:0] _GEN_11 = {1'h0, _GEN_4}; // @[tage.scala:67:{25,43}]
wire [3:0] _update_wdata_3_ctr_T_3 = _GEN_11 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_3_ctr_T_4 = _update_wdata_3_ctr_T_3[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_3_ctr_T_5 = _update_wdata_3_ctr_T_2 ? 3'h0 : _update_wdata_3_ctr_T_4; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_3_ctr_T_6 = &_GEN_4; // @[tage.scala:67:25, :68:25]
wire [3:0] _update_wdata_3_ctr_T_7 = _GEN_11 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_3_ctr_T_8 = _update_wdata_3_ctr_T_7[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_3_ctr_T_9 = _update_wdata_3_ctr_T_6 ? 3'h7 : _update_wdata_3_ctr_T_8; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_3_ctr_T_10 = _update_wdata_3_ctr_T_1 ? _update_wdata_3_ctr_T_5 : _update_wdata_3_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20]
wire _update_wdata_3_ctr_T_11 = ~io_update_taken_3_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_3_ctr_T_12 = io_update_old_ctr_3_0 == 3'h0; // @[tage.scala:24:7, :67:25]
wire [3:0] _GEN_12 = {1'h0, io_update_old_ctr_3_0}; // @[tage.scala:24:7, :67:43]
wire [3:0] _update_wdata_3_ctr_T_13 = _GEN_12 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_3_ctr_T_14 = _update_wdata_3_ctr_T_13[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_3_ctr_T_15 = _update_wdata_3_ctr_T_12 ? 3'h0 : _update_wdata_3_ctr_T_14; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_3_ctr_T_16 = &io_update_old_ctr_3_0; // @[tage.scala:24:7, :68:25]
wire [3:0] _update_wdata_3_ctr_T_17 = _GEN_12 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_3_ctr_T_18 = _update_wdata_3_ctr_T_17[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_3_ctr_T_19 = _update_wdata_3_ctr_T_16 ? 3'h7 : _update_wdata_3_ctr_T_18; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_3_ctr_T_20 = _update_wdata_3_ctr_T_11 ? _update_wdata_3_ctr_T_15 : _update_wdata_3_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20]
wire [2:0] _update_wdata_3_ctr_T_21 = wrbypass_hit ? _update_wdata_3_ctr_T_10 : _update_wdata_3_ctr_T_20; // @[tage.scala:67:8, :151:48, :159:10]
assign _update_wdata_3_ctr_T_22 = io_update_alloc_3_0 ? _update_wdata_3_ctr_T : _update_wdata_3_ctr_T_21; // @[tage.scala:24:7, :155:33, :156:10, :159:10]
assign update_wdata_3_ctr = _update_wdata_3_ctr_T_22; // @[tage.scala:119:26, :155:33]
assign _update_hi_wdata_3_T = io_update_u_3_0[1]; // @[tage.scala:24:7, :166:44]
assign update_hi_wdata_3 = _update_hi_wdata_3_T; // @[tage.scala:127:29, :166:44]
assign _update_lo_wdata_3_T = io_update_u_3_0[0]; // @[tage.scala:24:7, :167:44]
assign update_lo_wdata_3 = _update_lo_wdata_3_T; // @[tage.scala:134:29, :167:44]
wire [1:0] _wrbypass_enq_idx_T = {1'h0, wrbypass_enq_idx} + 2'h1; // @[util.scala:203:14]
wire _wrbypass_enq_idx_T_1 = _wrbypass_enq_idx_T[0]; // @[util.scala:203:14]
wire _wrbypass_enq_idx_T_2 = _wrbypass_enq_idx_T_1; // @[util.scala:203:{14,20}]
wire _T_44 = io_update_mask_0_0 | io_update_mask_1_0 | io_update_mask_2_0 | io_update_mask_3_0; // @[tage.scala:24:7, :170:32]
wire _GEN_13 = wrbypass_hit ? wrbypass_hit_idx : wrbypass_enq_idx; // @[Mux.scala:50:70]
wire _GEN_14 = ~_T_44 | wrbypass_hit | wrbypass_enq_idx; // @[tage.scala:141:29, :143:29, :144:33, :151:48, :170:{32,38}, :171:39, :175:39]
wire _GEN_15 = ~_T_44 | wrbypass_hit | ~wrbypass_enq_idx; // @[tage.scala:141:29, :143:29, :144:33, :151:48, :170:{32,38}, :171:39, :175:39]
always @(posedge clock) begin // @[tage.scala:24:7]
if (reset) begin // @[tage.scala:24:7]
doing_reset <= 1'h1; // @[tage.scala:72:28]
reset_idx <= 8'h0; // @[tage.scala:73:26]
clear_u_ctr <= 20'h0; // @[tage.scala:109:28]
wrbypass_enq_idx <= 1'h0; // @[tage.scala:144:33]
end
else begin // @[tage.scala:24:7]
doing_reset <= reset_idx != 8'hFF & doing_reset; // @[tage.scala:72:28, :73:26, :75:{19,36,50}]
reset_idx <= _reset_idx_T_1; // @[tage.scala:73:26, :74:26]
clear_u_ctr <= doing_reset ? 20'h1 : _clear_u_ctr_T_1; // @[tage.scala:72:28, :109:28, :110:{22,36,70,85}]
if (~_T_44 | wrbypass_hit) begin // @[tage.scala:143:29, :144:33, :151:48, :170:{32,38}, :171:39]
end
else // @[tage.scala:144:33, :170:38, :171:39]
wrbypass_enq_idx <= _wrbypass_enq_idx_T_2; // @[util.scala:203:20]
end
s2_tag <= s1_tag; // @[tage.scala:62:64, :95:29]
io_f3_resp_0_valid_REG <= s2_req_rhits_0; // @[tage.scala:100:29, :104:38]
io_f3_resp_0_bits_u_REG <= _io_f3_resp_0_bits_u_T; // @[tage.scala:105:{38,42}]
io_f3_resp_0_bits_ctr_REG <= s2_req_rtage_0_ctr; // @[tage.scala:97:29, :106:38]
io_f3_resp_1_valid_REG <= s2_req_rhits_1; // @[tage.scala:100:29, :104:38]
io_f3_resp_1_bits_u_REG <= _io_f3_resp_1_bits_u_T; // @[tage.scala:105:{38,42}]
io_f3_resp_1_bits_ctr_REG <= s2_req_rtage_1_ctr; // @[tage.scala:97:29, :106:38]
io_f3_resp_2_valid_REG <= s2_req_rhits_2; // @[tage.scala:100:29, :104:38]
io_f3_resp_2_bits_u_REG <= _io_f3_resp_2_bits_u_T; // @[tage.scala:105:{38,42}]
io_f3_resp_2_bits_ctr_REG <= s2_req_rtage_2_ctr; // @[tage.scala:97:29, :106:38]
io_f3_resp_3_valid_REG <= s2_req_rhits_3; // @[tage.scala:100:29, :104:38]
io_f3_resp_3_bits_u_REG <= _io_f3_resp_3_bits_u_T; // @[tage.scala:105:{38,42}]
io_f3_resp_3_bits_ctr_REG <= s2_req_rtage_3_ctr; // @[tage.scala:97:29, :106:38]
if (_GEN_14) begin // @[tage.scala:141:29, :170:38, :171:39, :175:39]
end
else // @[tage.scala:141:29, :170:38, :171:39, :175:39]
wrbypass_tags_0 <= update_tag; // @[tage.scala:62:64, :141:29]
if (_GEN_15) begin // @[tage.scala:141:29, :170:38, :171:39, :175:39]
end
else // @[tage.scala:141:29, :170:38, :171:39, :175:39]
wrbypass_tags_1 <= update_tag; // @[tage.scala:62:64, :141:29]
if (_GEN_14) begin // @[tage.scala:141:29, :142:29, :170:38, :171:39, :175:39, :176:39]
end
else // @[tage.scala:142:29, :170:38, :171:39, :176:39]
wrbypass_idxs_0 <= update_idx; // @[tage.scala:60:43, :142:29]
if (_GEN_15) begin // @[tage.scala:141:29, :142:29, :170:38, :171:39, :175:39, :176:39]
end
else // @[tage.scala:142:29, :170:38, :171:39, :176:39]
wrbypass_idxs_1 <= update_idx; // @[tage.scala:60:43, :142:29]
if (~_T_44 | _GEN_13) begin // @[tage.scala:143:29, :170:{32,38}, :171:39, :172:34, :174:39]
end
else begin // @[tage.scala:143:29, :170:38, :171:39]
wrbypass_0_0 <= update_wdata_0_ctr; // @[tage.scala:119:26, :143:29]
wrbypass_0_1 <= update_wdata_1_ctr; // @[tage.scala:119:26, :143:29]
wrbypass_0_2 <= update_wdata_2_ctr; // @[tage.scala:119:26, :143:29]
wrbypass_0_3 <= update_wdata_3_ctr; // @[tage.scala:119:26, :143:29]
end
if (_T_44 & _GEN_13) begin // @[tage.scala:143:29, :170:{32,38}, :171:39, :172:34, :174:39]
wrbypass_1_0 <= update_wdata_0_ctr; // @[tage.scala:119:26, :143:29]
wrbypass_1_1 <= update_wdata_1_ctr; // @[tage.scala:119:26, :143:29]
wrbypass_1_2 <= update_wdata_2_ctr; // @[tage.scala:119:26, :143:29]
wrbypass_1_3 <= update_wdata_3_ctr; // @[tage.scala:119:26, :143:29]
end
always @(posedge)
hi_us_7 hi_us ( // @[tage.scala:89:27]
.R0_addr (_s2_req_rhius_WIRE), // @[tage.scala:98:32]
.R0_en (io_f1_req_valid_0), // @[tage.scala:24:7]
.R0_clk (clock),
.R0_data (_hi_us_R0_data),
.W0_addr (doing_reset ? reset_idx : doing_clear_u_hi ? clear_u_idx[7:0] : update_idx), // @[tage.scala:60:43, :72:28, :73:26, :113:40, :115:33, :129:{8,36}]
.W0_clk (clock),
.W0_data ({hi_us_MPORT_1_data_3, hi_us_MPORT_1_data_2, hi_us_MPORT_1_data_1, hi_us_MPORT_1_data_0}), // @[tage.scala:89:27, :130:8]
.W0_mask (_T_20 ? 4'hF : {hi_5, lo_1}) // @[tage.scala:130:21, :131:{8,80}]
); // @[tage.scala:89:27]
lo_us_7 lo_us ( // @[tage.scala:90:27]
.R0_addr (_s2_req_rlous_WIRE), // @[tage.scala:99:32]
.R0_en (io_f1_req_valid_0), // @[tage.scala:24:7]
.R0_clk (clock),
.R0_data (_lo_us_R0_data),
.W0_addr (doing_reset ? reset_idx : doing_clear_u_lo ? clear_u_idx[7:0] : update_idx), // @[tage.scala:60:43, :72:28, :73:26, :114:40, :115:33, :136:{8,36}]
.W0_clk (clock),
.W0_data ({lo_us_MPORT_2_data_3, lo_us_MPORT_2_data_2, lo_us_MPORT_2_data_1, lo_us_MPORT_2_data_0}), // @[tage.scala:90:27, :137:8]
.W0_mask (_T_33 ? 4'hF : {hi_6, lo_2}) // @[tage.scala:137:21, :138:{8,80}]
); // @[tage.scala:90:27]
table_7 table_0 ( // @[tage.scala:91:27]
.R0_addr (_s2_req_rtage_WIRE), // @[tage.scala:97:40]
.R0_en (io_f1_req_valid_0), // @[tage.scala:24:7]
.R0_clk (clock),
.R0_data (_table_R0_data),
.W0_addr (doing_reset ? reset_idx : update_idx), // @[tage.scala:60:43, :72:28, :73:26, :122:8]
.W0_clk (clock),
.W0_data ({table_MPORT_data_3, table_MPORT_data_2, table_MPORT_data_1, table_MPORT_data_0}), // @[tage.scala:91:27, :123:8]
.W0_mask (doing_reset ? 4'hF : {hi_4, lo}) // @[tage.scala:72:28, :124:{8,90}]
); // @[tage.scala:91:27]
assign io_f3_resp_0_valid = io_f3_resp_0_valid_0; // @[tage.scala:24:7]
assign io_f3_resp_0_bits_ctr = io_f3_resp_0_bits_ctr_0; // @[tage.scala:24:7]
assign io_f3_resp_0_bits_u = io_f3_resp_0_bits_u_0; // @[tage.scala:24:7]
assign io_f3_resp_1_valid = io_f3_resp_1_valid_0; // @[tage.scala:24:7]
assign io_f3_resp_1_bits_ctr = io_f3_resp_1_bits_ctr_0; // @[tage.scala:24:7]
assign io_f3_resp_1_bits_u = io_f3_resp_1_bits_u_0; // @[tage.scala:24:7]
assign io_f3_resp_2_valid = io_f3_resp_2_valid_0; // @[tage.scala:24:7]
assign io_f3_resp_2_bits_ctr = io_f3_resp_2_bits_ctr_0; // @[tage.scala:24:7]
assign io_f3_resp_2_bits_u = io_f3_resp_2_bits_u_0; // @[tage.scala:24:7]
assign io_f3_resp_3_valid = io_f3_resp_3_valid_0; // @[tage.scala:24:7]
assign io_f3_resp_3_bits_ctr = io_f3_resp_3_bits_ctr_0; // @[tage.scala:24:7]
assign io_f3_resp_3_bits_u = io_f3_resp_3_bits_u_0; // @[tage.scala:24:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_85 :
input clock : Clock
input reset : Reset
output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, request_hp : UInt<1>, flip grant : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip kill : UInt<1>, flip clear : UInt<1>, flip ldspec_miss : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { pdst : UInt<7>, poisoned : UInt<1>}}[2], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip spec_ld_wakeup : { valid : UInt<1>, bits : UInt<7>}[1], flip in_uop : { valid : UInt<1>, bits : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}, out_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, debug : { p1 : UInt<1>, p2 : UInt<1>, p3 : UInt<1>, ppred : UInt<1>, state : UInt<2>}}
wire next_state : UInt
wire next_uopc : UInt
wire next_lrs1_rtype : UInt
wire next_lrs2_rtype : UInt
regreset state : UInt<2>, clock, reset, UInt<2>(0h0)
regreset p1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset p2 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset p3 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset ppred : UInt<1>, clock, reset, UInt<1>(0h0)
regreset p1_poisoned : UInt<1>, clock, reset, UInt<1>(0h0)
regreset p2_poisoned : UInt<1>, clock, reset, UInt<1>(0h0)
connect p1_poisoned, UInt<1>(0h0)
connect p2_poisoned, UInt<1>(0h0)
node next_p1_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned)
node next_p2_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned)
wire slot_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
invalidate slot_uop_uop.debug_tsrc
invalidate slot_uop_uop.debug_fsrc
invalidate slot_uop_uop.bp_xcpt_if
invalidate slot_uop_uop.bp_debug_if
invalidate slot_uop_uop.xcpt_ma_if
invalidate slot_uop_uop.xcpt_ae_if
invalidate slot_uop_uop.xcpt_pf_if
invalidate slot_uop_uop.fp_single
invalidate slot_uop_uop.fp_val
invalidate slot_uop_uop.frs3_en
invalidate slot_uop_uop.lrs2_rtype
invalidate slot_uop_uop.lrs1_rtype
invalidate slot_uop_uop.dst_rtype
invalidate slot_uop_uop.ldst_val
invalidate slot_uop_uop.lrs3
invalidate slot_uop_uop.lrs2
invalidate slot_uop_uop.lrs1
invalidate slot_uop_uop.ldst
invalidate slot_uop_uop.ldst_is_rs1
invalidate slot_uop_uop.flush_on_commit
invalidate slot_uop_uop.is_unique
invalidate slot_uop_uop.is_sys_pc2epc
invalidate slot_uop_uop.uses_stq
invalidate slot_uop_uop.uses_ldq
invalidate slot_uop_uop.is_amo
invalidate slot_uop_uop.is_fencei
invalidate slot_uop_uop.is_fence
invalidate slot_uop_uop.mem_signed
invalidate slot_uop_uop.mem_size
invalidate slot_uop_uop.mem_cmd
invalidate slot_uop_uop.bypassable
invalidate slot_uop_uop.exc_cause
invalidate slot_uop_uop.exception
invalidate slot_uop_uop.stale_pdst
invalidate slot_uop_uop.ppred_busy
invalidate slot_uop_uop.prs3_busy
invalidate slot_uop_uop.prs2_busy
invalidate slot_uop_uop.prs1_busy
invalidate slot_uop_uop.ppred
invalidate slot_uop_uop.prs3
invalidate slot_uop_uop.prs2
invalidate slot_uop_uop.prs1
invalidate slot_uop_uop.pdst
invalidate slot_uop_uop.rxq_idx
invalidate slot_uop_uop.stq_idx
invalidate slot_uop_uop.ldq_idx
invalidate slot_uop_uop.rob_idx
invalidate slot_uop_uop.csr_addr
invalidate slot_uop_uop.imm_packed
invalidate slot_uop_uop.taken
invalidate slot_uop_uop.pc_lob
invalidate slot_uop_uop.edge_inst
invalidate slot_uop_uop.ftq_idx
invalidate slot_uop_uop.br_tag
invalidate slot_uop_uop.br_mask
invalidate slot_uop_uop.is_sfb
invalidate slot_uop_uop.is_jal
invalidate slot_uop_uop.is_jalr
invalidate slot_uop_uop.is_br
invalidate slot_uop_uop.iw_p2_poisoned
invalidate slot_uop_uop.iw_p1_poisoned
invalidate slot_uop_uop.iw_state
invalidate slot_uop_uop.ctrl.is_std
invalidate slot_uop_uop.ctrl.is_sta
invalidate slot_uop_uop.ctrl.is_load
invalidate slot_uop_uop.ctrl.csr_cmd
invalidate slot_uop_uop.ctrl.fcn_dw
invalidate slot_uop_uop.ctrl.op_fcn
invalidate slot_uop_uop.ctrl.imm_sel
invalidate slot_uop_uop.ctrl.op2_sel
invalidate slot_uop_uop.ctrl.op1_sel
invalidate slot_uop_uop.ctrl.br_type
invalidate slot_uop_uop.fu_code
invalidate slot_uop_uop.iq_type
invalidate slot_uop_uop.debug_pc
invalidate slot_uop_uop.is_rvc
invalidate slot_uop_uop.debug_inst
invalidate slot_uop_uop.inst
invalidate slot_uop_uop.uopc
connect slot_uop_uop.uopc, UInt<7>(0h0)
connect slot_uop_uop.bypassable, UInt<1>(0h0)
connect slot_uop_uop.fp_val, UInt<1>(0h0)
connect slot_uop_uop.uses_stq, UInt<1>(0h0)
connect slot_uop_uop.uses_ldq, UInt<1>(0h0)
connect slot_uop_uop.pdst, UInt<1>(0h0)
connect slot_uop_uop.dst_rtype, UInt<2>(0h2)
wire slot_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}
invalidate slot_uop_cs.is_std
invalidate slot_uop_cs.is_sta
invalidate slot_uop_cs.is_load
invalidate slot_uop_cs.csr_cmd
invalidate slot_uop_cs.fcn_dw
invalidate slot_uop_cs.op_fcn
invalidate slot_uop_cs.imm_sel
invalidate slot_uop_cs.op2_sel
invalidate slot_uop_cs.op1_sel
invalidate slot_uop_cs.br_type
connect slot_uop_cs.br_type, UInt<4>(0h0)
connect slot_uop_cs.csr_cmd, UInt<3>(0h0)
connect slot_uop_cs.is_load, UInt<1>(0h0)
connect slot_uop_cs.is_sta, UInt<1>(0h0)
connect slot_uop_cs.is_std, UInt<1>(0h0)
connect slot_uop_uop.ctrl, slot_uop_cs
regreset slot_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock, reset, slot_uop_uop
node next_uop = mux(io.in_uop.valid, io.in_uop.bits, slot_uop)
when io.kill :
connect state, UInt<2>(0h0)
else :
when io.in_uop.valid :
connect state, io.in_uop.bits.iw_state
else :
when io.clear :
connect state, UInt<2>(0h0)
else :
connect state, next_state
connect next_state, state
connect next_uopc, slot_uop.uopc
connect next_lrs1_rtype, slot_uop.lrs1_rtype
connect next_lrs2_rtype, slot_uop.lrs2_rtype
when io.kill :
connect next_state, UInt<2>(0h0)
else :
node _T = eq(state, UInt<2>(0h1))
node _T_1 = and(io.grant, _T)
node _T_2 = eq(state, UInt<2>(0h2))
node _T_3 = and(io.grant, _T_2)
node _T_4 = and(_T_3, p1)
node _T_5 = and(_T_4, p2)
node _T_6 = and(_T_5, ppred)
node _T_7 = or(_T_1, _T_6)
when _T_7 :
node _T_8 = or(p1_poisoned, p2_poisoned)
node _T_9 = and(io.ldspec_miss, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
when _T_10 :
connect next_state, UInt<2>(0h0)
else :
node _T_11 = eq(state, UInt<2>(0h2))
node _T_12 = and(io.grant, _T_11)
when _T_12 :
node _T_13 = or(p1_poisoned, p2_poisoned)
node _T_14 = and(io.ldspec_miss, _T_13)
node _T_15 = eq(_T_14, UInt<1>(0h0))
when _T_15 :
connect next_state, UInt<2>(0h1)
when p1 :
connect slot_uop.uopc, UInt<7>(0h3)
connect next_uopc, UInt<7>(0h3)
connect slot_uop.lrs1_rtype, UInt<2>(0h2)
connect next_lrs1_rtype, UInt<2>(0h2)
else :
connect slot_uop.lrs2_rtype, UInt<2>(0h2)
connect next_lrs2_rtype, UInt<2>(0h2)
when io.in_uop.valid :
connect slot_uop, io.in_uop.bits
node _T_16 = eq(state, UInt<2>(0h0))
node _T_17 = or(_T_16, io.clear)
node _T_18 = or(_T_17, io.kill)
node _T_19 = asUInt(reset)
node _T_20 = eq(_T_19, UInt<1>(0h0))
when _T_20 :
node _T_21 = eq(_T_18, UInt<1>(0h0))
when _T_21 :
printf(clock, UInt<1>(0h1), "Assertion failed: trying to overwrite a valid issue slot.\n at issue-slot.scala:156 assert (is_invalid || io.clear || io.kill, \"trying to overwrite a valid issue slot.\")\n") : printf
assert(clock, _T_18, UInt<1>(0h1), "") : assert
wire next_p1 : UInt<1>
connect next_p1, p1
wire next_p2 : UInt<1>
connect next_p2, p2
wire next_p3 : UInt<1>
connect next_p3, p3
wire next_ppred : UInt<1>
connect next_ppred, ppred
when io.in_uop.valid :
node _p1_T = eq(io.in_uop.bits.prs1_busy, UInt<1>(0h0))
connect p1, _p1_T
node _p2_T = eq(io.in_uop.bits.prs2_busy, UInt<1>(0h0))
connect p2, _p2_T
node _p3_T = eq(io.in_uop.bits.prs3_busy, UInt<1>(0h0))
connect p3, _p3_T
node _ppred_T = eq(io.in_uop.bits.ppred_busy, UInt<1>(0h0))
connect ppred, _ppred_T
node _T_22 = and(io.ldspec_miss, next_p1_poisoned)
when _T_22 :
node _T_23 = neq(next_uop.prs1, UInt<1>(0h0))
node _T_24 = asUInt(reset)
node _T_25 = eq(_T_24, UInt<1>(0h0))
when _T_25 :
node _T_26 = eq(_T_23, UInt<1>(0h0))
when _T_26 :
printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs1=x0!\n at issue-slot.scala:176 assert(next_uop.prs1 =/= 0.U, \"Poison bit can't be set for prs1=x0!\")\n") : printf_1
assert(clock, _T_23, UInt<1>(0h1), "") : assert_1
connect p1, UInt<1>(0h0)
node _T_27 = and(io.ldspec_miss, next_p2_poisoned)
when _T_27 :
node _T_28 = neq(next_uop.prs2, UInt<1>(0h0))
node _T_29 = asUInt(reset)
node _T_30 = eq(_T_29, UInt<1>(0h0))
when _T_30 :
node _T_31 = eq(_T_28, UInt<1>(0h0))
when _T_31 :
printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs2=x0!\n at issue-slot.scala:180 assert(next_uop.prs2 =/= 0.U, \"Poison bit can't be set for prs2=x0!\")\n") : printf_2
assert(clock, _T_28, UInt<1>(0h1), "") : assert_2
connect p2, UInt<1>(0h0)
node _T_32 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs1)
node _T_33 = and(io.wakeup_ports[0].valid, _T_32)
when _T_33 :
connect p1, UInt<1>(0h1)
node _T_34 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs2)
node _T_35 = and(io.wakeup_ports[0].valid, _T_34)
when _T_35 :
connect p2, UInt<1>(0h1)
node _T_36 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs3)
node _T_37 = and(io.wakeup_ports[0].valid, _T_36)
when _T_37 :
connect p3, UInt<1>(0h1)
node _T_38 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs1)
node _T_39 = and(io.wakeup_ports[1].valid, _T_38)
when _T_39 :
connect p1, UInt<1>(0h1)
node _T_40 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs2)
node _T_41 = and(io.wakeup_ports[1].valid, _T_40)
when _T_41 :
connect p2, UInt<1>(0h1)
node _T_42 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs3)
node _T_43 = and(io.wakeup_ports[1].valid, _T_42)
when _T_43 :
connect p3, UInt<1>(0h1)
node _T_44 = eq(io.pred_wakeup_port.bits, next_uop.ppred)
node _T_45 = and(io.pred_wakeup_port.valid, _T_44)
when _T_45 :
connect ppred, UInt<1>(0h1)
node _T_46 = eq(io.spec_ld_wakeup[0].bits, UInt<1>(0h0))
node _T_47 = and(io.spec_ld_wakeup[0].valid, _T_46)
node _T_48 = eq(_T_47, UInt<1>(0h0))
node _T_49 = asUInt(reset)
node _T_50 = eq(_T_49, UInt<1>(0h0))
when _T_50 :
node _T_51 = eq(_T_48, UInt<1>(0h0))
when _T_51 :
printf(clock, UInt<1>(0h1), "Assertion failed: Loads to x0 should never speculatively wakeup other instructions\n at issue-slot.scala:203 assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),\n") : printf_3
assert(clock, _T_48, UInt<1>(0h1), "") : assert_3
node _T_52 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs1)
node _T_53 = and(io.spec_ld_wakeup[0].valid, _T_52)
node _T_54 = eq(next_uop.lrs1_rtype, UInt<2>(0h0))
node _T_55 = and(_T_53, _T_54)
when _T_55 :
connect p1, UInt<1>(0h1)
connect p1_poisoned, UInt<1>(0h1)
node _T_56 = eq(next_p1_poisoned, UInt<1>(0h0))
node _T_57 = asUInt(reset)
node _T_58 = eq(_T_57, UInt<1>(0h0))
when _T_58 :
node _T_59 = eq(_T_56, UInt<1>(0h0))
when _T_59 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:214 assert (!next_p1_poisoned)\n") : printf_4
assert(clock, _T_56, UInt<1>(0h1), "") : assert_4
node _T_60 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs2)
node _T_61 = and(io.spec_ld_wakeup[0].valid, _T_60)
node _T_62 = eq(next_uop.lrs2_rtype, UInt<2>(0h0))
node _T_63 = and(_T_61, _T_62)
when _T_63 :
connect p2, UInt<1>(0h1)
connect p2_poisoned, UInt<1>(0h1)
node _T_64 = eq(next_p2_poisoned, UInt<1>(0h0))
node _T_65 = asUInt(reset)
node _T_66 = eq(_T_65, UInt<1>(0h0))
when _T_66 :
node _T_67 = eq(_T_64, UInt<1>(0h0))
when _T_67 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:221 assert (!next_p2_poisoned)\n") : printf_5
assert(clock, _T_64, UInt<1>(0h1), "") : assert_5
node _next_br_mask_T = not(io.brupdate.b1.resolve_mask)
node next_br_mask = and(slot_uop.br_mask, _next_br_mask_T)
node _T_68 = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask)
node _T_69 = neq(_T_68, UInt<1>(0h0))
when _T_69 :
connect next_state, UInt<2>(0h0)
node _T_70 = eq(io.in_uop.valid, UInt<1>(0h0))
when _T_70 :
connect slot_uop.br_mask, next_br_mask
node _io_request_T = neq(state, UInt<2>(0h0))
node _io_request_T_1 = and(_io_request_T, p1)
node _io_request_T_2 = and(_io_request_T_1, p2)
node _io_request_T_3 = and(_io_request_T_2, p3)
node _io_request_T_4 = and(_io_request_T_3, ppred)
node _io_request_T_5 = eq(io.kill, UInt<1>(0h0))
node _io_request_T_6 = and(_io_request_T_4, _io_request_T_5)
connect io.request, _io_request_T_6
node _high_priority_T = or(slot_uop.is_br, slot_uop.is_jal)
node high_priority = or(_high_priority_T, slot_uop.is_jalr)
node _io_request_hp_T = and(io.request, high_priority)
connect io.request_hp, _io_request_hp_T
node _T_71 = eq(state, UInt<2>(0h1))
when _T_71 :
node _io_request_T_7 = and(p1, p2)
node _io_request_T_8 = and(_io_request_T_7, p3)
node _io_request_T_9 = and(_io_request_T_8, ppred)
node _io_request_T_10 = eq(io.kill, UInt<1>(0h0))
node _io_request_T_11 = and(_io_request_T_9, _io_request_T_10)
connect io.request, _io_request_T_11
else :
node _T_72 = eq(state, UInt<2>(0h2))
when _T_72 :
node _io_request_T_12 = or(p1, p2)
node _io_request_T_13 = and(_io_request_T_12, ppred)
node _io_request_T_14 = eq(io.kill, UInt<1>(0h0))
node _io_request_T_15 = and(_io_request_T_13, _io_request_T_14)
connect io.request, _io_request_T_15
else :
connect io.request, UInt<1>(0h0)
node _io_valid_T = neq(state, UInt<2>(0h0))
connect io.valid, _io_valid_T
connect io.uop, slot_uop
connect io.uop.iw_p1_poisoned, p1_poisoned
connect io.uop.iw_p2_poisoned, p2_poisoned
node _may_vacate_T = eq(state, UInt<2>(0h1))
node _may_vacate_T_1 = eq(state, UInt<2>(0h2))
node _may_vacate_T_2 = and(_may_vacate_T_1, p1)
node _may_vacate_T_3 = and(_may_vacate_T_2, p2)
node _may_vacate_T_4 = and(_may_vacate_T_3, ppred)
node _may_vacate_T_5 = or(_may_vacate_T, _may_vacate_T_4)
node may_vacate = and(io.grant, _may_vacate_T_5)
node _squash_grant_T = or(p1_poisoned, p2_poisoned)
node squash_grant = and(io.ldspec_miss, _squash_grant_T)
node _io_will_be_valid_T = neq(state, UInt<2>(0h0))
node _io_will_be_valid_T_1 = eq(squash_grant, UInt<1>(0h0))
node _io_will_be_valid_T_2 = and(may_vacate, _io_will_be_valid_T_1)
node _io_will_be_valid_T_3 = eq(_io_will_be_valid_T_2, UInt<1>(0h0))
node _io_will_be_valid_T_4 = and(_io_will_be_valid_T, _io_will_be_valid_T_3)
connect io.will_be_valid, _io_will_be_valid_T_4
connect io.out_uop, slot_uop
connect io.out_uop.iw_state, next_state
connect io.out_uop.uopc, next_uopc
connect io.out_uop.lrs1_rtype, next_lrs1_rtype
connect io.out_uop.lrs2_rtype, next_lrs2_rtype
connect io.out_uop.br_mask, next_br_mask
node _io_out_uop_prs1_busy_T = eq(p1, UInt<1>(0h0))
connect io.out_uop.prs1_busy, _io_out_uop_prs1_busy_T
node _io_out_uop_prs2_busy_T = eq(p2, UInt<1>(0h0))
connect io.out_uop.prs2_busy, _io_out_uop_prs2_busy_T
node _io_out_uop_prs3_busy_T = eq(p3, UInt<1>(0h0))
connect io.out_uop.prs3_busy, _io_out_uop_prs3_busy_T
node _io_out_uop_ppred_busy_T = eq(ppred, UInt<1>(0h0))
connect io.out_uop.ppred_busy, _io_out_uop_ppred_busy_T
connect io.out_uop.iw_p1_poisoned, p1_poisoned
connect io.out_uop.iw_p2_poisoned, p2_poisoned
node _T_73 = eq(state, UInt<2>(0h2))
when _T_73 :
node _T_74 = and(p1, p2)
node _T_75 = and(_T_74, ppred)
when _T_75 :
skip
else :
node _T_76 = and(p1, ppred)
when _T_76 :
connect io.uop.uopc, slot_uop.uopc
connect io.uop.lrs2_rtype, UInt<2>(0h2)
else :
node _T_77 = and(p2, ppred)
when _T_77 :
connect io.uop.uopc, UInt<7>(0h3)
connect io.uop.lrs1_rtype, UInt<2>(0h2)
connect io.debug.p1, p1
connect io.debug.p2, p2
connect io.debug.p3, p3
connect io.debug.ppred, ppred
connect io.debug.state, state | module IssueSlot_85( // @[issue-slot.scala:69:7]
input clock, // @[issue-slot.scala:69:7]
input reset, // @[issue-slot.scala:69:7]
output io_valid, // @[issue-slot.scala:73:14]
output io_will_be_valid, // @[issue-slot.scala:73:14]
output io_request, // @[issue-slot.scala:73:14]
output io_request_hp, // @[issue-slot.scala:73:14]
input io_grant, // @[issue-slot.scala:73:14]
input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14]
input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14]
input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14]
input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14]
input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14]
input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14]
input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14]
input io_brupdate_b2_valid, // @[issue-slot.scala:73:14]
input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14]
input io_brupdate_b2_taken, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14]
input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14]
input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14]
input io_kill, // @[issue-slot.scala:73:14]
input io_clear, // @[issue-slot.scala:73:14]
input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14]
input io_in_uop_valid, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14]
input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14]
input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14]
input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14]
input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14]
input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14]
input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14]
input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14]
input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14]
input io_in_uop_bits_taken, // @[issue-slot.scala:73:14]
input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14]
input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14]
input io_in_uop_bits_exception, // @[issue-slot.scala:73:14]
input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14]
input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14]
input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14]
input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14]
input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14]
input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14]
input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14]
input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14]
output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14]
output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14]
output io_out_uop_is_rvc, // @[issue-slot.scala:73:14]
output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14]
output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14]
output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14]
output io_out_uop_is_br, // @[issue-slot.scala:73:14]
output io_out_uop_is_jalr, // @[issue-slot.scala:73:14]
output io_out_uop_is_jal, // @[issue-slot.scala:73:14]
output io_out_uop_is_sfb, // @[issue-slot.scala:73:14]
output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14]
output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14]
output io_out_uop_edge_inst, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14]
output io_out_uop_taken, // @[issue-slot.scala:73:14]
output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14]
output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ppred, // @[issue-slot.scala:73:14]
output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14]
output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14]
output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14]
output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14]
output io_out_uop_exception, // @[issue-slot.scala:73:14]
output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14]
output io_out_uop_bypassable, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14]
output io_out_uop_mem_signed, // @[issue-slot.scala:73:14]
output io_out_uop_is_fence, // @[issue-slot.scala:73:14]
output io_out_uop_is_fencei, // @[issue-slot.scala:73:14]
output io_out_uop_is_amo, // @[issue-slot.scala:73:14]
output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14]
output io_out_uop_uses_stq, // @[issue-slot.scala:73:14]
output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
output io_out_uop_is_unique, // @[issue-slot.scala:73:14]
output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14]
output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14]
output io_out_uop_ldst_val, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
output io_out_uop_frs3_en, // @[issue-slot.scala:73:14]
output io_out_uop_fp_val, // @[issue-slot.scala:73:14]
output io_out_uop_fp_single, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14]
output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14]
output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14]
output [31:0] io_uop_inst, // @[issue-slot.scala:73:14]
output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14]
output io_uop_is_rvc, // @[issue-slot.scala:73:14]
output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14]
output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14]
output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14]
output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14]
output io_uop_is_br, // @[issue-slot.scala:73:14]
output io_uop_is_jalr, // @[issue-slot.scala:73:14]
output io_uop_is_jal, // @[issue-slot.scala:73:14]
output io_uop_is_sfb, // @[issue-slot.scala:73:14]
output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14]
output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14]
output io_uop_edge_inst, // @[issue-slot.scala:73:14]
output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14]
output io_uop_taken, // @[issue-slot.scala:73:14]
output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14]
output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14]
output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14]
output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14]
output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14]
output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14]
output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14]
output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14]
output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ppred, // @[issue-slot.scala:73:14]
output io_uop_prs1_busy, // @[issue-slot.scala:73:14]
output io_uop_prs2_busy, // @[issue-slot.scala:73:14]
output io_uop_prs3_busy, // @[issue-slot.scala:73:14]
output io_uop_ppred_busy, // @[issue-slot.scala:73:14]
output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14]
output io_uop_exception, // @[issue-slot.scala:73:14]
output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14]
output io_uop_bypassable, // @[issue-slot.scala:73:14]
output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14]
output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14]
output io_uop_mem_signed, // @[issue-slot.scala:73:14]
output io_uop_is_fence, // @[issue-slot.scala:73:14]
output io_uop_is_fencei, // @[issue-slot.scala:73:14]
output io_uop_is_amo, // @[issue-slot.scala:73:14]
output io_uop_uses_ldq, // @[issue-slot.scala:73:14]
output io_uop_uses_stq, // @[issue-slot.scala:73:14]
output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
output io_uop_is_unique, // @[issue-slot.scala:73:14]
output io_uop_flush_on_commit, // @[issue-slot.scala:73:14]
output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14]
output io_uop_ldst_val, // @[issue-slot.scala:73:14]
output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
output io_uop_frs3_en, // @[issue-slot.scala:73:14]
output io_uop_fp_val, // @[issue-slot.scala:73:14]
output io_uop_fp_single, // @[issue-slot.scala:73:14]
output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
output io_uop_bp_debug_if, // @[issue-slot.scala:73:14]
output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14]
output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14]
output io_debug_p1, // @[issue-slot.scala:73:14]
output io_debug_p2, // @[issue-slot.scala:73:14]
output io_debug_p3, // @[issue-slot.scala:73:14]
output io_debug_ppred, // @[issue-slot.scala:73:14]
output [1:0] io_debug_state // @[issue-slot.scala:73:14]
);
wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7]
wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7]
wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7]
wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7]
wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7]
wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7]
wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7]
wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7]
wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7]
wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7]
wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7]
wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7]
wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7]
wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7]
wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7]
wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7]
wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7]
wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7]
wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7]
wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7]
wire io_ldspec_miss = 1'h0; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_0_bits_poisoned = 1'h0; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_1_bits_poisoned = 1'h0; // @[issue-slot.scala:69:7]
wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7]
wire io_spec_ld_wakeup_0_valid = 1'h0; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7]
wire io_out_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7]
wire io_out_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7]
wire io_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7]
wire io_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7]
wire next_p1_poisoned = 1'h0; // @[issue-slot.scala:99:29]
wire next_p2_poisoned = 1'h0; // @[issue-slot.scala:100:29]
wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18]
wire _squash_grant_T = 1'h0; // @[issue-slot.scala:261:53]
wire squash_grant = 1'h0; // @[issue-slot.scala:261:37]
wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7]
wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [6:0] io_spec_ld_wakeup_0_bits = 7'h0; // @[issue-slot.scala:69:7]
wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19]
wire _io_will_be_valid_T_1 = 1'h1; // @[issue-slot.scala:262:51]
wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19]
wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18]
wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19]
wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19]
wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19]
wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19]
wire _io_valid_T; // @[issue-slot.scala:79:24]
wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32]
wire _io_request_hp_T; // @[issue-slot.scala:243:31]
wire [6:0] next_uopc; // @[issue-slot.scala:82:29]
wire [1:0] next_state; // @[issue-slot.scala:81:29]
wire [15:0] next_br_mask; // @[util.scala:85:25]
wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28]
wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28]
wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28]
wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28]
wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29]
wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29]
wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7]
wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7]
wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7]
wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7]
wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7]
wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7]
wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7]
wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7]
wire io_out_uop_taken_0; // @[issue-slot.scala:69:7]
wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7]
wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7]
wire io_out_uop_exception_0; // @[issue-slot.scala:69:7]
wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7]
wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7]
wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7]
wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7]
wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7]
wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7]
wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7]
wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7]
wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7]
wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7]
wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7]
wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7]
wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7]
wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7]
wire io_uop_is_br_0; // @[issue-slot.scala:69:7]
wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7]
wire io_uop_is_jal_0; // @[issue-slot.scala:69:7]
wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7]
wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7]
wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7]
wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7]
wire io_uop_taken_0; // @[issue-slot.scala:69:7]
wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7]
wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ppred_0; // @[issue-slot.scala:69:7]
wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7]
wire io_uop_exception_0; // @[issue-slot.scala:69:7]
wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7]
wire io_uop_bypassable_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7]
wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7]
wire io_uop_is_fence_0; // @[issue-slot.scala:69:7]
wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7]
wire io_uop_is_amo_0; // @[issue-slot.scala:69:7]
wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7]
wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7]
wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7]
wire io_uop_is_unique_0; // @[issue-slot.scala:69:7]
wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7]
wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7]
wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7]
wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7]
wire io_uop_fp_val_0; // @[issue-slot.scala:69:7]
wire io_uop_fp_single_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7]
wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7]
wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7]
wire io_debug_p1_0; // @[issue-slot.scala:69:7]
wire io_debug_p2_0; // @[issue-slot.scala:69:7]
wire io_debug_p3_0; // @[issue-slot.scala:69:7]
wire io_debug_ppred_0; // @[issue-slot.scala:69:7]
wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7]
wire io_valid_0; // @[issue-slot.scala:69:7]
wire io_will_be_valid_0; // @[issue-slot.scala:69:7]
wire io_request_0; // @[issue-slot.scala:69:7]
wire io_request_hp_0; // @[issue-slot.scala:69:7]
assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29]
assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29]
assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29]
assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29]
reg [1:0] state; // @[issue-slot.scala:86:22]
assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22]
reg p1; // @[issue-slot.scala:87:22]
assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22]
wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25]
reg p2; // @[issue-slot.scala:88:22]
assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22]
wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25]
reg p3; // @[issue-slot.scala:89:22]
assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22]
wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25]
reg ppred; // @[issue-slot.scala:90:22]
assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22]
wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28]
reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25]
reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25]
reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_rvc; // @[issue-slot.scala:102:25]
assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25]
reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25]
assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25]
reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25]
assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25]
reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25]
assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25]
reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25]
reg slot_uop_is_br; // @[issue-slot.scala:102:25]
assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_jalr; // @[issue-slot.scala:102:25]
assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_jal; // @[issue-slot.scala:102:25]
assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_sfb; // @[issue-slot.scala:102:25]
assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25]
reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25]
assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25]
reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25]
assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_edge_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25]
assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_taken; // @[issue-slot.scala:102:25]
assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25]
reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25]
assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25]
reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25]
assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25]
assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25]
assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25]
assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25]
assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ppred; // @[issue-slot.scala:102:25]
assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25]
assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25]
assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_exception; // @[issue-slot.scala:102:25]
assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25]
reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25]
assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bypassable; // @[issue-slot.scala:102:25]
assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_mem_signed; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_fence; // @[issue-slot.scala:102:25]
assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_fencei; // @[issue-slot.scala:102:25]
assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_amo; // @[issue-slot.scala:102:25]
assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25]
assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_uses_stq; // @[issue-slot.scala:102:25]
assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25]
assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_unique; // @[issue-slot.scala:102:25]
assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25]
assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ldst_val; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25]
assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25]
reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25]
reg slot_uop_frs3_en; // @[issue-slot.scala:102:25]
assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_fp_val; // @[issue-slot.scala:102:25]
assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_fp_single; // @[issue-slot.scala:102:25]
assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25]
assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25]
assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25]
wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_iw_p1_poisoned = ~io_in_uop_valid_0 & slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_iw_p2_poisoned = ~io_in_uop_valid_0 & slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25]
wire _T_7 = io_grant_0 & state == 2'h1 | io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}]
wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25]
wire _GEN = io_kill_0 | _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51]
wire _GEN_0 = _GEN | ~(_T_12 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:62, :142:17, :143:23]
assign next_uopc = _GEN_0 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51]
assign next_lrs1_rtype = _GEN_0 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51]
wire _GEN_1 = _GEN | ~_T_12 | p1; // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:62, :142:17]
assign next_lrs2_rtype = _GEN_1 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17] |
Generate the Verilog code corresponding to this FIRRTL code module EgressUnit :
input clock : Clock
input reset : Reset
output io : { flip in : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], credit_available : UInt<1>[1], channel_status : { occupied : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[1], flip allocs : { alloc : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[1], flip credit_alloc : { alloc : UInt<1>, tail : UInt<1>}[1], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, ingress_id : UInt}}}
regreset channel_empty : UInt<1>, clock, reset, UInt<1>(0h1)
reg flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, clock
inst q of Queue2_EgressFlit
connect q.clock, clock
connect q.reset, reset
connect q.io.enq.valid, io.in[0].valid
connect q.io.enq.bits.head, io.in[0].bits.head
connect q.io.enq.bits.tail, io.in[0].bits.tail
node _q_io_enq_bits_ingress_id_T = eq(UInt<3>(0h5), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_1 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_2 = and(_q_io_enq_bits_ingress_id_T, _q_io_enq_bits_ingress_id_T_1)
node _q_io_enq_bits_ingress_id_T_3 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_4 = eq(UInt<3>(0h4), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_5 = and(_q_io_enq_bits_ingress_id_T_3, _q_io_enq_bits_ingress_id_T_4)
node _q_io_enq_bits_ingress_id_T_6 = eq(UInt<4>(0h9), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_7 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_8 = and(_q_io_enq_bits_ingress_id_T_6, _q_io_enq_bits_ingress_id_T_7)
node _q_io_enq_bits_ingress_id_T_9 = eq(UInt<3>(0h6), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_10 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_11 = and(_q_io_enq_bits_ingress_id_T_9, _q_io_enq_bits_ingress_id_T_10)
node _q_io_enq_bits_ingress_id_T_12 = eq(UInt<4>(0ha), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_13 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_14 = and(_q_io_enq_bits_ingress_id_T_12, _q_io_enq_bits_ingress_id_T_13)
node _q_io_enq_bits_ingress_id_T_15 = mux(_q_io_enq_bits_ingress_id_T_2, UInt<5>(0h1b), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_16 = mux(_q_io_enq_bits_ingress_id_T_5, UInt<5>(0h1a), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_17 = mux(_q_io_enq_bits_ingress_id_T_8, UInt<5>(0h1d), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_18 = mux(_q_io_enq_bits_ingress_id_T_11, UInt<5>(0h1c), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_19 = mux(_q_io_enq_bits_ingress_id_T_14, UInt<5>(0h1e), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_20 = or(_q_io_enq_bits_ingress_id_T_15, _q_io_enq_bits_ingress_id_T_16)
node _q_io_enq_bits_ingress_id_T_21 = or(_q_io_enq_bits_ingress_id_T_20, _q_io_enq_bits_ingress_id_T_17)
node _q_io_enq_bits_ingress_id_T_22 = or(_q_io_enq_bits_ingress_id_T_21, _q_io_enq_bits_ingress_id_T_18)
node _q_io_enq_bits_ingress_id_T_23 = or(_q_io_enq_bits_ingress_id_T_22, _q_io_enq_bits_ingress_id_T_19)
wire _q_io_enq_bits_ingress_id_WIRE : UInt<5>
connect _q_io_enq_bits_ingress_id_WIRE, _q_io_enq_bits_ingress_id_T_23
connect q.io.enq.bits.ingress_id, _q_io_enq_bits_ingress_id_WIRE
connect q.io.enq.bits.payload, io.in[0].bits.payload
connect io.out.bits, q.io.deq.bits
connect io.out.valid, q.io.deq.valid
connect q.io.deq.ready, io.out.ready
node _T = eq(q.io.enq.ready, UInt<1>(0h0))
node _T_1 = and(q.io.enq.valid, _T)
node _T_2 = eq(_T_1, UInt<1>(0h0))
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
node _T_5 = eq(_T_2, UInt<1>(0h0))
when _T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at EgressUnit.scala:38 assert(!(q.io.enq.valid && !q.io.enq.ready))\n") : printf
assert(clock, _T_2, UInt<1>(0h1), "") : assert
node _io_credit_available_0_T = eq(q.io.count, UInt<1>(0h0))
connect io.credit_available[0], _io_credit_available_0_T
node _io_channel_status_0_occupied_T = eq(channel_empty, UInt<1>(0h0))
connect io.channel_status[0].occupied, _io_channel_status_0_occupied_T
connect io.channel_status[0].flow, flow
node _T_6 = and(io.credit_alloc[0].alloc, io.credit_alloc[0].tail)
when _T_6 :
connect channel_empty, UInt<1>(0h1)
when io.allocs[0].alloc :
connect channel_empty, UInt<1>(0h0)
connect flow, io.allocs[0].flow | module EgressUnit( // @[EgressUnit.scala:12:7]
input clock, // @[EgressUnit.scala:12:7]
input reset, // @[EgressUnit.scala:12:7]
input io_in_0_valid, // @[EgressUnit.scala:18:14]
input io_in_0_bits_head, // @[EgressUnit.scala:18:14]
input io_in_0_bits_tail, // @[EgressUnit.scala:18:14]
input [144:0] io_in_0_bits_payload, // @[EgressUnit.scala:18:14]
input [3:0] io_in_0_bits_flow_ingress_node, // @[EgressUnit.scala:18:14]
input [2:0] io_in_0_bits_flow_ingress_node_id, // @[EgressUnit.scala:18:14]
output io_credit_available_0, // @[EgressUnit.scala:18:14]
output io_channel_status_0_occupied, // @[EgressUnit.scala:18:14]
input io_allocs_0_alloc, // @[EgressUnit.scala:18:14]
input io_credit_alloc_0_alloc, // @[EgressUnit.scala:18:14]
input io_credit_alloc_0_tail, // @[EgressUnit.scala:18:14]
input io_out_ready, // @[EgressUnit.scala:18:14]
output io_out_valid, // @[EgressUnit.scala:18:14]
output io_out_bits_head, // @[EgressUnit.scala:18:14]
output io_out_bits_tail, // @[EgressUnit.scala:18:14]
output [144:0] io_out_bits_payload // @[EgressUnit.scala:18:14]
);
wire _q_io_enq_ready; // @[EgressUnit.scala:22:17]
wire [1:0] _q_io_count; // @[EgressUnit.scala:22:17]
reg channel_empty; // @[EgressUnit.scala:20:30]
wire _q_io_enq_bits_ingress_id_T_13 = io_in_0_bits_flow_ingress_node_id == 3'h0; // @[EgressUnit.scala:32:27] |
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_EntryData_45 :
input clock : Clock
input reset : Reset
output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}}
connect io.y, io.x | module OptimizationBarrier_EntryData_45( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_0 = io_x_ae; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae = io_x_ae_0; // @[package.scala:267:30]
wire io_y_sw = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr = io_x_sr_0; // @[package.scala:267:30]
wire io_y_pw = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr = io_x_pr_0; // @[package.scala:267:30]
wire io_y_pal = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_79 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_source_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_90
connect io_out_source_valid.clock, clock
connect io_out_source_valid.reset, reset
connect io_out_source_valid.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_source_valid.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_79( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_90 io_out_source_valid ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MSHR_5 :
input clock : Clock
input reset : Reset
output io : { flip allocate : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, repeat : UInt<1>}}, flip directory : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}}, status : { valid : UInt<1>, bits : { set : UInt<10>, tag : UInt<13>, way : UInt<3>, blockB : UInt<1>, nestB : UInt<1>, blockC : UInt<1>, nestC : UInt<1>}}, schedule : { flip ready : UInt<1>, valid : UInt<1>, bits : { a : { valid : UInt<1>, bits : { tag : UInt<13>, set : UInt<10>, param : UInt<3>, source : UInt<3>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<13>, set : UInt<10>, clients : UInt<1>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<3>, tag : UInt<13>, set : UInt<10>, way : UInt<3>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<10>, way : UInt<3>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>}}}, reload : UInt<1>}}, flip sinkc : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<10>, tag : UInt<13>, source : UInt<6>, param : UInt<3>, data : UInt<1>}}, flip sinkd : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>}}, flip sinke : { valid : UInt<1>, bits : { sink : UInt<3>}}, flip nestedwb : { set : UInt<10>, tag : UInt<13>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}}
regreset request_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg request : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>}, clock
regreset meta_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg meta : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}, clock
when meta_valid :
node _T = eq(meta.state, UInt<2>(0h0))
when _T :
node _T_1 = orr(meta.clients)
node _T_2 = eq(_T_1, UInt<1>(0h0))
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
node _T_5 = eq(_T_2, UInt<1>(0h0))
when _T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:105 assert (!meta.clients.orR)\n") : printf
assert(clock, _T_2, UInt<1>(0h1), "") : assert
node _T_6 = eq(meta.dirty, UInt<1>(0h0))
node _T_7 = asUInt(reset)
node _T_8 = eq(_T_7, UInt<1>(0h0))
when _T_8 :
node _T_9 = eq(_T_6, UInt<1>(0h0))
when _T_9 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:106 assert (!meta.dirty)\n") : printf_1
assert(clock, _T_6, UInt<1>(0h1), "") : assert_1
node _T_10 = eq(meta.state, UInt<2>(0h1))
when _T_10 :
node _T_11 = eq(meta.dirty, UInt<1>(0h0))
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:109 assert (!meta.dirty)\n") : printf_2
assert(clock, _T_11, UInt<1>(0h1), "") : assert_2
node _T_15 = eq(meta.state, UInt<2>(0h2))
when _T_15 :
node _T_16 = orr(meta.clients)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:112 assert (meta.clients.orR)\n") : printf_3
assert(clock, _T_16, UInt<1>(0h1), "") : assert_3
node _T_20 = sub(meta.clients, UInt<1>(0h1))
node _T_21 = tail(_T_20, 1)
node _T_22 = and(meta.clients, _T_21)
node _T_23 = eq(_T_22, UInt<1>(0h0))
node _T_24 = asUInt(reset)
node _T_25 = eq(_T_24, UInt<1>(0h0))
when _T_25 :
node _T_26 = eq(_T_23, UInt<1>(0h0))
when _T_26 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:113 assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one\n") : printf_4
assert(clock, _T_23, UInt<1>(0h1), "") : assert_4
node _T_27 = eq(meta.state, UInt<2>(0h3))
when _T_27 :
skip
regreset s_rprobe : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_rprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_rprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_release : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_releaseack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_pprobe : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_acquire : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_flush : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantlast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grant : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_probeack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_grantack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_execute : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_writeback : UInt<1>, clock, reset, UInt<1>(0h1)
reg sink : UInt<3>, clock
reg gotT : UInt<1>, clock
reg bad_grant : UInt<1>, clock
reg probes_done : UInt<1>, clock
reg probes_toN : UInt<1>, clock
reg probes_noT : UInt<1>, clock
node _T_28 = neq(meta.state, UInt<2>(0h0))
node _T_29 = and(meta_valid, _T_28)
node _T_30 = eq(io.nestedwb.set, request.set)
node _T_31 = and(_T_29, _T_30)
node _T_32 = eq(io.nestedwb.tag, meta.tag)
node _T_33 = and(_T_31, _T_32)
when _T_33 :
when io.nestedwb.b_clr_dirty :
connect meta.dirty, UInt<1>(0h0)
when io.nestedwb.c_set_dirty :
connect meta.dirty, UInt<1>(0h1)
when io.nestedwb.b_toB :
connect meta.state, UInt<2>(0h1)
when io.nestedwb.b_toN :
connect meta.hit, UInt<1>(0h0)
connect io.status.valid, request_valid
connect io.status.bits.set, request.set
connect io.status.bits.tag, request.tag
connect io.status.bits.way, meta.way
node _io_status_bits_blockB_T = eq(meta_valid, UInt<1>(0h0))
node _io_status_bits_blockB_T_1 = eq(w_releaseack, UInt<1>(0h0))
node _io_status_bits_blockB_T_2 = eq(w_rprobeacklast, UInt<1>(0h0))
node _io_status_bits_blockB_T_3 = or(_io_status_bits_blockB_T_1, _io_status_bits_blockB_T_2)
node _io_status_bits_blockB_T_4 = eq(w_pprobeacklast, UInt<1>(0h0))
node _io_status_bits_blockB_T_5 = or(_io_status_bits_blockB_T_3, _io_status_bits_blockB_T_4)
node _io_status_bits_blockB_T_6 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_blockB_T_7 = and(_io_status_bits_blockB_T_5, _io_status_bits_blockB_T_6)
node _io_status_bits_blockB_T_8 = or(_io_status_bits_blockB_T, _io_status_bits_blockB_T_7)
connect io.status.bits.blockB, _io_status_bits_blockB_T_8
node _io_status_bits_nestB_T = and(meta_valid, w_releaseack)
node _io_status_bits_nestB_T_1 = and(_io_status_bits_nestB_T, w_rprobeacklast)
node _io_status_bits_nestB_T_2 = and(_io_status_bits_nestB_T_1, w_pprobeacklast)
node _io_status_bits_nestB_T_3 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_nestB_T_4 = and(_io_status_bits_nestB_T_2, _io_status_bits_nestB_T_3)
connect io.status.bits.nestB, _io_status_bits_nestB_T_4
node _io_status_bits_blockC_T = eq(meta_valid, UInt<1>(0h0))
connect io.status.bits.blockC, _io_status_bits_blockC_T
node _io_status_bits_nestC_T = eq(w_rprobeackfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_1 = eq(w_pprobeackfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_2 = or(_io_status_bits_nestC_T, _io_status_bits_nestC_T_1)
node _io_status_bits_nestC_T_3 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_4 = or(_io_status_bits_nestC_T_2, _io_status_bits_nestC_T_3)
node _io_status_bits_nestC_T_5 = and(meta_valid, _io_status_bits_nestC_T_4)
connect io.status.bits.nestC, _io_status_bits_nestC_T_5
node _T_34 = eq(io.status.bits.nestB, UInt<1>(0h0))
node _T_35 = eq(io.status.bits.blockB, UInt<1>(0h0))
node _T_36 = or(_T_34, _T_35)
node _T_37 = asUInt(reset)
node _T_38 = eq(_T_37, UInt<1>(0h0))
when _T_38 :
node _T_39 = eq(_T_36, UInt<1>(0h0))
when _T_39 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:179 assert (!io.status.bits.nestB || !io.status.bits.blockB)\n") : printf_5
assert(clock, _T_36, UInt<1>(0h1), "") : assert_5
node _T_40 = eq(io.status.bits.nestC, UInt<1>(0h0))
node _T_41 = eq(io.status.bits.blockC, UInt<1>(0h0))
node _T_42 = or(_T_40, _T_41)
node _T_43 = asUInt(reset)
node _T_44 = eq(_T_43, UInt<1>(0h0))
when _T_44 :
node _T_45 = eq(_T_42, UInt<1>(0h0))
when _T_45 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:180 assert (!io.status.bits.nestC || !io.status.bits.blockC)\n") : printf_6
assert(clock, _T_42, UInt<1>(0h1), "") : assert_6
node _no_wait_T = and(w_rprobeacklast, w_releaseack)
node _no_wait_T_1 = and(_no_wait_T, w_grantlast)
node _no_wait_T_2 = and(_no_wait_T_1, w_pprobeacklast)
node no_wait = and(_no_wait_T_2, w_grantack)
node _io_schedule_bits_a_valid_T = eq(s_acquire, UInt<1>(0h0))
node _io_schedule_bits_a_valid_T_1 = and(_io_schedule_bits_a_valid_T, s_release)
node _io_schedule_bits_a_valid_T_2 = and(_io_schedule_bits_a_valid_T_1, s_pprobe)
connect io.schedule.bits.a.valid, _io_schedule_bits_a_valid_T_2
node _io_schedule_bits_b_valid_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_valid_T_1 = eq(s_pprobe, UInt<1>(0h0))
node _io_schedule_bits_b_valid_T_2 = or(_io_schedule_bits_b_valid_T, _io_schedule_bits_b_valid_T_1)
connect io.schedule.bits.b.valid, _io_schedule_bits_b_valid_T_2
node _io_schedule_bits_c_valid_T = eq(s_release, UInt<1>(0h0))
node _io_schedule_bits_c_valid_T_1 = and(_io_schedule_bits_c_valid_T, w_rprobeackfirst)
node _io_schedule_bits_c_valid_T_2 = eq(s_probeack, UInt<1>(0h0))
node _io_schedule_bits_c_valid_T_3 = and(_io_schedule_bits_c_valid_T_2, w_pprobeackfirst)
node _io_schedule_bits_c_valid_T_4 = or(_io_schedule_bits_c_valid_T_1, _io_schedule_bits_c_valid_T_3)
connect io.schedule.bits.c.valid, _io_schedule_bits_c_valid_T_4
node _io_schedule_bits_d_valid_T = eq(s_execute, UInt<1>(0h0))
node _io_schedule_bits_d_valid_T_1 = and(_io_schedule_bits_d_valid_T, w_pprobeack)
node _io_schedule_bits_d_valid_T_2 = and(_io_schedule_bits_d_valid_T_1, w_grant)
connect io.schedule.bits.d.valid, _io_schedule_bits_d_valid_T_2
node _io_schedule_bits_e_valid_T = eq(s_grantack, UInt<1>(0h0))
node _io_schedule_bits_e_valid_T_1 = and(_io_schedule_bits_e_valid_T, w_grantfirst)
connect io.schedule.bits.e.valid, _io_schedule_bits_e_valid_T_1
node _io_schedule_bits_x_valid_T = eq(s_flush, UInt<1>(0h0))
node _io_schedule_bits_x_valid_T_1 = and(_io_schedule_bits_x_valid_T, w_releaseack)
connect io.schedule.bits.x.valid, _io_schedule_bits_x_valid_T_1
node _io_schedule_bits_dir_valid_T = eq(s_release, UInt<1>(0h0))
node _io_schedule_bits_dir_valid_T_1 = and(_io_schedule_bits_dir_valid_T, w_rprobeackfirst)
node _io_schedule_bits_dir_valid_T_2 = eq(s_writeback, UInt<1>(0h0))
node _io_schedule_bits_dir_valid_T_3 = and(_io_schedule_bits_dir_valid_T_2, no_wait)
node _io_schedule_bits_dir_valid_T_4 = or(_io_schedule_bits_dir_valid_T_1, _io_schedule_bits_dir_valid_T_3)
connect io.schedule.bits.dir.valid, _io_schedule_bits_dir_valid_T_4
connect io.schedule.bits.reload, no_wait
node _io_schedule_valid_T = or(io.schedule.bits.a.valid, io.schedule.bits.b.valid)
node _io_schedule_valid_T_1 = or(_io_schedule_valid_T, io.schedule.bits.c.valid)
node _io_schedule_valid_T_2 = or(_io_schedule_valid_T_1, io.schedule.bits.d.valid)
node _io_schedule_valid_T_3 = or(_io_schedule_valid_T_2, io.schedule.bits.e.valid)
node _io_schedule_valid_T_4 = or(_io_schedule_valid_T_3, io.schedule.bits.x.valid)
node _io_schedule_valid_T_5 = or(_io_schedule_valid_T_4, io.schedule.bits.dir.valid)
connect io.schedule.valid, _io_schedule_valid_T_5
when io.schedule.ready :
connect s_rprobe, UInt<1>(0h1)
when w_rprobeackfirst :
connect s_release, UInt<1>(0h1)
connect s_pprobe, UInt<1>(0h1)
node _T_46 = and(s_release, s_pprobe)
when _T_46 :
connect s_acquire, UInt<1>(0h1)
when w_releaseack :
connect s_flush, UInt<1>(0h1)
when w_pprobeackfirst :
connect s_probeack, UInt<1>(0h1)
when w_grantfirst :
connect s_grantack, UInt<1>(0h1)
node _T_47 = and(w_pprobeack, w_grant)
when _T_47 :
connect s_execute, UInt<1>(0h1)
when no_wait :
connect s_writeback, UInt<1>(0h1)
when no_wait :
connect request_valid, UInt<1>(0h0)
connect meta_valid, UInt<1>(0h0)
wire final_meta_writeback : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}
connect final_meta_writeback, meta
node req_clientBit = eq(request.source, UInt<6>(0h20))
node _req_needT_T = bits(request.opcode, 2, 2)
node _req_needT_T_1 = eq(_req_needT_T, UInt<1>(0h0))
node _req_needT_T_2 = eq(request.opcode, UInt<3>(0h5))
node _req_needT_T_3 = eq(request.param, UInt<1>(0h1))
node _req_needT_T_4 = and(_req_needT_T_2, _req_needT_T_3)
node _req_needT_T_5 = or(_req_needT_T_1, _req_needT_T_4)
node _req_needT_T_6 = eq(request.opcode, UInt<3>(0h6))
node _req_needT_T_7 = eq(request.opcode, UInt<3>(0h7))
node _req_needT_T_8 = or(_req_needT_T_6, _req_needT_T_7)
node _req_needT_T_9 = neq(request.param, UInt<2>(0h0))
node _req_needT_T_10 = and(_req_needT_T_8, _req_needT_T_9)
node req_needT = or(_req_needT_T_5, _req_needT_T_10)
node _req_acquire_T = eq(request.opcode, UInt<3>(0h6))
node _req_acquire_T_1 = eq(request.opcode, UInt<3>(0h7))
node req_acquire = or(_req_acquire_T, _req_acquire_T_1)
node _meta_no_clients_T = orr(meta.clients)
node meta_no_clients = eq(_meta_no_clients_T, UInt<1>(0h0))
node _req_promoteT_T = eq(meta.state, UInt<2>(0h3))
node _req_promoteT_T_1 = and(meta_no_clients, _req_promoteT_T)
node _req_promoteT_T_2 = mux(meta.hit, _req_promoteT_T_1, gotT)
node req_promoteT = and(req_acquire, _req_promoteT_T_2)
node _T_48 = and(request.prio[2], UInt<1>(0h1))
when _T_48 :
node _final_meta_writeback_dirty_T = bits(request.opcode, 0, 0)
node _final_meta_writeback_dirty_T_1 = or(meta.dirty, _final_meta_writeback_dirty_T)
connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_1
node _final_meta_writeback_state_T = neq(request.param, UInt<3>(0h3))
node _final_meta_writeback_state_T_1 = eq(meta.state, UInt<2>(0h2))
node _final_meta_writeback_state_T_2 = and(_final_meta_writeback_state_T, _final_meta_writeback_state_T_1)
node _final_meta_writeback_state_T_3 = mux(_final_meta_writeback_state_T_2, UInt<2>(0h3), meta.state)
connect final_meta_writeback.state, _final_meta_writeback_state_T_3
node _final_meta_writeback_clients_T = eq(request.param, UInt<3>(0h1))
node _final_meta_writeback_clients_T_1 = eq(request.param, UInt<3>(0h2))
node _final_meta_writeback_clients_T_2 = or(_final_meta_writeback_clients_T, _final_meta_writeback_clients_T_1)
node _final_meta_writeback_clients_T_3 = eq(request.param, UInt<3>(0h5))
node _final_meta_writeback_clients_T_4 = or(_final_meta_writeback_clients_T_2, _final_meta_writeback_clients_T_3)
node _final_meta_writeback_clients_T_5 = mux(_final_meta_writeback_clients_T_4, req_clientBit, UInt<1>(0h0))
node _final_meta_writeback_clients_T_6 = not(_final_meta_writeback_clients_T_5)
node _final_meta_writeback_clients_T_7 = and(meta.clients, _final_meta_writeback_clients_T_6)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_7
connect final_meta_writeback.hit, UInt<1>(0h1)
else :
node _T_49 = and(request.control, UInt<1>(0h1))
when _T_49 :
when meta.hit :
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h0)
node _final_meta_writeback_clients_T_8 = not(probes_toN)
node _final_meta_writeback_clients_T_9 = and(meta.clients, _final_meta_writeback_clients_T_8)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_9
connect final_meta_writeback.hit, UInt<1>(0h0)
else :
node _final_meta_writeback_dirty_T_2 = and(meta.hit, meta.dirty)
node _final_meta_writeback_dirty_T_3 = bits(request.opcode, 2, 2)
node _final_meta_writeback_dirty_T_4 = eq(_final_meta_writeback_dirty_T_3, UInt<1>(0h0))
node _final_meta_writeback_dirty_T_5 = or(_final_meta_writeback_dirty_T_2, _final_meta_writeback_dirty_T_4)
connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_5
node _final_meta_writeback_state_T_4 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_5 = eq(meta.hit, UInt<1>(0h0))
node _final_meta_writeback_state_T_6 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_7 = mux(gotT, _final_meta_writeback_state_T_6, UInt<2>(0h1))
node _final_meta_writeback_state_T_8 = and(meta_no_clients, req_acquire)
node _final_meta_writeback_state_T_9 = mux(_final_meta_writeback_state_T_8, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_10 = eq(UInt<2>(0h1), meta.state)
node _final_meta_writeback_state_T_11 = mux(_final_meta_writeback_state_T_10, UInt<2>(0h1), UInt<2>(0h1))
node _final_meta_writeback_state_T_12 = eq(UInt<2>(0h2), meta.state)
node _final_meta_writeback_state_T_13 = mux(_final_meta_writeback_state_T_12, UInt<2>(0h3), _final_meta_writeback_state_T_11)
node _final_meta_writeback_state_T_14 = eq(UInt<2>(0h3), meta.state)
node _final_meta_writeback_state_T_15 = mux(_final_meta_writeback_state_T_14, _final_meta_writeback_state_T_9, _final_meta_writeback_state_T_13)
node _final_meta_writeback_state_T_16 = mux(_final_meta_writeback_state_T_5, _final_meta_writeback_state_T_7, _final_meta_writeback_state_T_15)
node _final_meta_writeback_state_T_17 = mux(req_needT, _final_meta_writeback_state_T_4, _final_meta_writeback_state_T_16)
connect final_meta_writeback.state, _final_meta_writeback_state_T_17
node _final_meta_writeback_clients_T_10 = not(probes_toN)
node _final_meta_writeback_clients_T_11 = and(meta.clients, _final_meta_writeback_clients_T_10)
node _final_meta_writeback_clients_T_12 = mux(meta.hit, _final_meta_writeback_clients_T_11, UInt<1>(0h0))
node _final_meta_writeback_clients_T_13 = mux(req_acquire, req_clientBit, UInt<1>(0h0))
node _final_meta_writeback_clients_T_14 = or(_final_meta_writeback_clients_T_12, _final_meta_writeback_clients_T_13)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_14
connect final_meta_writeback.tag, request.tag
connect final_meta_writeback.hit, UInt<1>(0h1)
when bad_grant :
when meta.hit :
node _T_50 = eq(meta_valid, UInt<1>(0h0))
node _T_51 = eq(meta.state, UInt<2>(0h1))
node _T_52 = or(_T_50, _T_51)
node _T_53 = asUInt(reset)
node _T_54 = eq(_T_53, UInt<1>(0h0))
when _T_54 :
node _T_55 = eq(_T_52, UInt<1>(0h0))
when _T_55 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:254 assert (!meta_valid || meta.state === BRANCH)\n") : printf_7
assert(clock, _T_52, UInt<1>(0h1), "") : assert_7
connect final_meta_writeback.hit, UInt<1>(0h1)
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h1)
node _final_meta_writeback_clients_T_15 = not(probes_toN)
node _final_meta_writeback_clients_T_16 = and(meta.clients, _final_meta_writeback_clients_T_15)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_16
else :
connect final_meta_writeback.hit, UInt<1>(0h0)
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h0)
connect final_meta_writeback.clients, UInt<1>(0h0)
wire invalid : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>}
connect invalid.dirty, UInt<1>(0h0)
connect invalid.state, UInt<2>(0h0)
connect invalid.clients, UInt<1>(0h0)
connect invalid.tag, UInt<1>(0h0)
node _honour_BtoT_T = and(meta.clients, req_clientBit)
node _honour_BtoT_T_1 = orr(_honour_BtoT_T)
node honour_BtoT = and(meta.hit, _honour_BtoT_T_1)
node _excluded_client_T = and(meta.hit, request.prio[0])
node _excluded_client_T_1 = eq(request.opcode, UInt<3>(0h6))
node _excluded_client_T_2 = eq(request.opcode, UInt<3>(0h7))
node _excluded_client_T_3 = or(_excluded_client_T_1, _excluded_client_T_2)
node _excluded_client_T_4 = eq(request.opcode, UInt<3>(0h4))
node _excluded_client_T_5 = or(_excluded_client_T_3, _excluded_client_T_4)
node _excluded_client_T_6 = eq(request.opcode, UInt<3>(0h5))
node _excluded_client_T_7 = and(_excluded_client_T_6, UInt<1>(0h0))
node _excluded_client_T_8 = or(_excluded_client_T_5, _excluded_client_T_7)
node _excluded_client_T_9 = and(_excluded_client_T, _excluded_client_T_8)
node excluded_client = mux(_excluded_client_T_9, req_clientBit, UInt<1>(0h0))
connect io.schedule.bits.a.bits.tag, request.tag
connect io.schedule.bits.a.bits.set, request.set
node _io_schedule_bits_a_bits_param_T = mux(meta.hit, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_a_bits_param_T_1 = mux(req_needT, _io_schedule_bits_a_bits_param_T, UInt<2>(0h0))
connect io.schedule.bits.a.bits.param, _io_schedule_bits_a_bits_param_T_1
node _io_schedule_bits_a_bits_block_T = neq(request.size, UInt<3>(0h6))
node _io_schedule_bits_a_bits_block_T_1 = eq(request.opcode, UInt<1>(0h0))
node _io_schedule_bits_a_bits_block_T_2 = eq(request.opcode, UInt<3>(0h7))
node _io_schedule_bits_a_bits_block_T_3 = or(_io_schedule_bits_a_bits_block_T_1, _io_schedule_bits_a_bits_block_T_2)
node _io_schedule_bits_a_bits_block_T_4 = eq(_io_schedule_bits_a_bits_block_T_3, UInt<1>(0h0))
node _io_schedule_bits_a_bits_block_T_5 = or(_io_schedule_bits_a_bits_block_T, _io_schedule_bits_a_bits_block_T_4)
connect io.schedule.bits.a.bits.block, _io_schedule_bits_a_bits_block_T_5
connect io.schedule.bits.a.bits.source, UInt<1>(0h0)
node _io_schedule_bits_b_bits_param_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_bits_param_T_1 = mux(req_needT, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_b_bits_param_T_2 = mux(request.prio[1], request.param, _io_schedule_bits_b_bits_param_T_1)
node _io_schedule_bits_b_bits_param_T_3 = mux(_io_schedule_bits_b_bits_param_T, UInt<2>(0h2), _io_schedule_bits_b_bits_param_T_2)
connect io.schedule.bits.b.bits.param, _io_schedule_bits_b_bits_param_T_3
node _io_schedule_bits_b_bits_tag_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_bits_tag_T_1 = mux(_io_schedule_bits_b_bits_tag_T, meta.tag, request.tag)
connect io.schedule.bits.b.bits.tag, _io_schedule_bits_b_bits_tag_T_1
connect io.schedule.bits.b.bits.set, request.set
node _io_schedule_bits_b_bits_clients_T = not(excluded_client)
node _io_schedule_bits_b_bits_clients_T_1 = and(meta.clients, _io_schedule_bits_b_bits_clients_T)
connect io.schedule.bits.b.bits.clients, _io_schedule_bits_b_bits_clients_T_1
node _io_schedule_bits_c_bits_opcode_T = mux(meta.dirty, UInt<3>(0h7), UInt<3>(0h6))
connect io.schedule.bits.c.bits.opcode, _io_schedule_bits_c_bits_opcode_T
node _io_schedule_bits_c_bits_param_T = eq(meta.state, UInt<2>(0h1))
node _io_schedule_bits_c_bits_param_T_1 = mux(_io_schedule_bits_c_bits_param_T, UInt<3>(0h2), UInt<3>(0h1))
connect io.schedule.bits.c.bits.param, _io_schedule_bits_c_bits_param_T_1
connect io.schedule.bits.c.bits.source, UInt<1>(0h0)
connect io.schedule.bits.c.bits.tag, meta.tag
connect io.schedule.bits.c.bits.set, request.set
connect io.schedule.bits.c.bits.way, meta.way
connect io.schedule.bits.c.bits.dirty, meta.dirty
connect io.schedule.bits.d.bits.set, request.set
connect io.schedule.bits.d.bits.put, request.put
connect io.schedule.bits.d.bits.offset, request.offset
connect io.schedule.bits.d.bits.tag, request.tag
connect io.schedule.bits.d.bits.source, request.source
connect io.schedule.bits.d.bits.size, request.size
connect io.schedule.bits.d.bits.param, request.param
connect io.schedule.bits.d.bits.opcode, request.opcode
connect io.schedule.bits.d.bits.control, request.control
connect io.schedule.bits.d.bits.prio, request.prio
node _io_schedule_bits_d_bits_param_T = eq(req_acquire, UInt<1>(0h0))
node _io_schedule_bits_d_bits_param_T_1 = mux(req_promoteT, UInt<2>(0h1), UInt<2>(0h0))
node _io_schedule_bits_d_bits_param_T_2 = mux(honour_BtoT, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_d_bits_param_T_3 = eq(UInt<2>(0h0), request.param)
node _io_schedule_bits_d_bits_param_T_4 = mux(_io_schedule_bits_d_bits_param_T_3, _io_schedule_bits_d_bits_param_T_1, request.param)
node _io_schedule_bits_d_bits_param_T_5 = eq(UInt<2>(0h2), request.param)
node _io_schedule_bits_d_bits_param_T_6 = mux(_io_schedule_bits_d_bits_param_T_5, _io_schedule_bits_d_bits_param_T_2, _io_schedule_bits_d_bits_param_T_4)
node _io_schedule_bits_d_bits_param_T_7 = eq(UInt<2>(0h1), request.param)
node _io_schedule_bits_d_bits_param_T_8 = mux(_io_schedule_bits_d_bits_param_T_7, UInt<2>(0h1), _io_schedule_bits_d_bits_param_T_6)
node _io_schedule_bits_d_bits_param_T_9 = mux(_io_schedule_bits_d_bits_param_T, request.param, _io_schedule_bits_d_bits_param_T_8)
connect io.schedule.bits.d.bits.param, _io_schedule_bits_d_bits_param_T_9
connect io.schedule.bits.d.bits.sink, UInt<1>(0h0)
connect io.schedule.bits.d.bits.way, meta.way
connect io.schedule.bits.d.bits.bad, bad_grant
connect io.schedule.bits.e.bits.sink, sink
connect io.schedule.bits.x.bits.fail, UInt<1>(0h0)
connect io.schedule.bits.dir.bits.set, request.set
connect io.schedule.bits.dir.bits.way, meta.way
node _io_schedule_bits_dir_bits_data_T = eq(s_release, UInt<1>(0h0))
wire _io_schedule_bits_dir_bits_data_WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>}
connect _io_schedule_bits_dir_bits_data_WIRE.tag, final_meta_writeback.tag
connect _io_schedule_bits_dir_bits_data_WIRE.clients, final_meta_writeback.clients
connect _io_schedule_bits_dir_bits_data_WIRE.state, final_meta_writeback.state
connect _io_schedule_bits_dir_bits_data_WIRE.dirty, final_meta_writeback.dirty
node _io_schedule_bits_dir_bits_data_T_1 = mux(_io_schedule_bits_dir_bits_data_T, invalid, _io_schedule_bits_dir_bits_data_WIRE)
connect io.schedule.bits.dir.bits.data, _io_schedule_bits_dir_bits_data_T_1
node _evict_T = eq(meta.hit, UInt<1>(0h0))
wire evict : UInt
connect evict, UInt<1>(0h0)
node evict_c = orr(meta.clients)
node _evict_T_1 = eq(UInt<2>(0h1), meta.state)
when _evict_T_1 :
node _evict_out_T = mux(evict_c, UInt<1>(0h0), UInt<1>(0h1))
connect evict, _evict_out_T
else :
node _evict_T_2 = eq(UInt<2>(0h2), meta.state)
when _evict_T_2 :
node _evict_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect evict, _evict_out_T_1
else :
node _evict_T_3 = eq(UInt<2>(0h3), meta.state)
when _evict_T_3 :
node _evict_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _evict_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _evict_out_T_4 = mux(evict_c, _evict_out_T_2, _evict_out_T_3)
connect evict, _evict_out_T_4
else :
node _evict_T_4 = eq(UInt<2>(0h0), meta.state)
when _evict_T_4 :
connect evict, UInt<4>(0h8)
node _evict_T_5 = eq(_evict_T, UInt<1>(0h0))
when _evict_T_5 :
connect evict, UInt<4>(0h8)
wire before : UInt
connect before, UInt<1>(0h0)
node before_c = orr(meta.clients)
node _before_T = eq(UInt<2>(0h1), meta.state)
when _before_T :
node _before_out_T = mux(before_c, UInt<1>(0h0), UInt<1>(0h1))
connect before, _before_out_T
else :
node _before_T_1 = eq(UInt<2>(0h2), meta.state)
when _before_T_1 :
node _before_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect before, _before_out_T_1
else :
node _before_T_2 = eq(UInt<2>(0h3), meta.state)
when _before_T_2 :
node _before_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _before_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _before_out_T_4 = mux(before_c, _before_out_T_2, _before_out_T_3)
connect before, _before_out_T_4
else :
node _before_T_3 = eq(UInt<2>(0h0), meta.state)
when _before_T_3 :
connect before, UInt<4>(0h8)
node _before_T_4 = eq(meta.hit, UInt<1>(0h0))
when _before_T_4 :
connect before, UInt<4>(0h8)
wire after : UInt
connect after, UInt<1>(0h0)
node after_c = orr(final_meta_writeback.clients)
node _after_T = eq(UInt<2>(0h1), final_meta_writeback.state)
when _after_T :
node _after_out_T = mux(after_c, UInt<1>(0h0), UInt<1>(0h1))
connect after, _after_out_T
else :
node _after_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state)
when _after_T_1 :
node _after_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect after, _after_out_T_1
else :
node _after_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state)
when _after_T_2 :
node _after_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _after_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _after_out_T_4 = mux(after_c, _after_out_T_2, _after_out_T_3)
connect after, _after_out_T_4
else :
node _after_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state)
when _after_T_3 :
connect after, UInt<4>(0h8)
node _after_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0))
when _after_T_4 :
connect after, UInt<4>(0h8)
node _T_56 = eq(s_release, UInt<1>(0h0))
node _T_57 = and(_T_56, w_rprobeackfirst)
node _T_58 = and(_T_57, io.schedule.ready)
when _T_58 :
node _T_59 = eq(evict, UInt<1>(0h1))
node _T_60 = eq(_T_59, UInt<1>(0h0))
node _T_61 = asUInt(reset)
node _T_62 = eq(_T_61, UInt<1>(0h0))
when _T_62 :
node _T_63 = eq(_T_60, UInt<1>(0h0))
when _T_63 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_8
assert(clock, _T_60, UInt<1>(0h1), "") : assert_8
node _T_64 = eq(before, UInt<1>(0h1))
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(_T_65, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_9
assert(clock, _T_65, UInt<1>(0h1), "") : assert_9
node _T_69 = eq(evict, UInt<1>(0h0))
node _T_70 = eq(_T_69, UInt<1>(0h0))
node _T_71 = asUInt(reset)
node _T_72 = eq(_T_71, UInt<1>(0h0))
when _T_72 :
node _T_73 = eq(_T_70, UInt<1>(0h0))
when _T_73 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_10
assert(clock, _T_70, UInt<1>(0h1), "") : assert_10
node _T_74 = eq(before, UInt<1>(0h0))
node _T_75 = eq(_T_74, UInt<1>(0h0))
node _T_76 = asUInt(reset)
node _T_77 = eq(_T_76, UInt<1>(0h0))
when _T_77 :
node _T_78 = eq(_T_75, UInt<1>(0h0))
when _T_78 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_11
assert(clock, _T_75, UInt<1>(0h1), "") : assert_11
node _T_79 = eq(evict, UInt<3>(0h7))
node _T_80 = eq(before, UInt<3>(0h7))
node _T_81 = eq(evict, UInt<3>(0h5))
node _T_82 = eq(before, UInt<3>(0h5))
node _T_83 = eq(evict, UInt<3>(0h4))
node _T_84 = eq(before, UInt<3>(0h4))
node _T_85 = eq(evict, UInt<3>(0h6))
node _T_86 = eq(before, UInt<3>(0h6))
node _T_87 = eq(evict, UInt<2>(0h3))
node _T_88 = eq(before, UInt<2>(0h3))
node _T_89 = eq(evict, UInt<2>(0h2))
node _T_90 = eq(before, UInt<2>(0h2))
node _T_91 = eq(s_writeback, UInt<1>(0h0))
node _T_92 = and(_T_91, no_wait)
node _T_93 = and(_T_92, io.schedule.ready)
when _T_93 :
node _T_94 = eq(before, UInt<4>(0h8))
node _T_95 = eq(after, UInt<1>(0h1))
node _T_96 = and(_T_94, _T_95)
node _T_97 = eq(_T_96, UInt<1>(0h0))
node _T_98 = asUInt(reset)
node _T_99 = eq(_T_98, UInt<1>(0h0))
when _T_99 :
node _T_100 = eq(_T_97, UInt<1>(0h0))
when _T_100 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_12
assert(clock, _T_97, UInt<1>(0h1), "") : assert_12
node _T_101 = eq(before, UInt<4>(0h8))
node _T_102 = eq(after, UInt<1>(0h0))
node _T_103 = and(_T_101, _T_102)
node _T_104 = eq(_T_103, UInt<1>(0h0))
node _T_105 = asUInt(reset)
node _T_106 = eq(_T_105, UInt<1>(0h0))
when _T_106 :
node _T_107 = eq(_T_104, UInt<1>(0h0))
when _T_107 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_13
assert(clock, _T_104, UInt<1>(0h1), "") : assert_13
node _T_108 = eq(before, UInt<4>(0h8))
node _T_109 = eq(after, UInt<3>(0h7))
node _T_110 = and(_T_108, _T_109)
node _T_111 = eq(before, UInt<4>(0h8))
node _T_112 = eq(after, UInt<3>(0h5))
node _T_113 = and(_T_111, _T_112)
node _T_114 = eq(_T_113, UInt<1>(0h0))
node _T_115 = asUInt(reset)
node _T_116 = eq(_T_115, UInt<1>(0h0))
when _T_116 :
node _T_117 = eq(_T_114, UInt<1>(0h0))
when _T_117 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_14
assert(clock, _T_114, UInt<1>(0h1), "") : assert_14
node _T_118 = eq(before, UInt<4>(0h8))
node _T_119 = eq(after, UInt<3>(0h4))
node _T_120 = and(_T_118, _T_119)
node _T_121 = eq(_T_120, UInt<1>(0h0))
node _T_122 = asUInt(reset)
node _T_123 = eq(_T_122, UInt<1>(0h0))
when _T_123 :
node _T_124 = eq(_T_121, UInt<1>(0h0))
when _T_124 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_15
assert(clock, _T_121, UInt<1>(0h1), "") : assert_15
node _T_125 = eq(before, UInt<4>(0h8))
node _T_126 = eq(after, UInt<3>(0h6))
node _T_127 = and(_T_125, _T_126)
node _T_128 = eq(before, UInt<4>(0h8))
node _T_129 = eq(after, UInt<2>(0h3))
node _T_130 = and(_T_128, _T_129)
node _T_131 = eq(before, UInt<4>(0h8))
node _T_132 = eq(after, UInt<2>(0h2))
node _T_133 = and(_T_131, _T_132)
node _T_134 = eq(_T_133, UInt<1>(0h0))
node _T_135 = asUInt(reset)
node _T_136 = eq(_T_135, UInt<1>(0h0))
when _T_136 :
node _T_137 = eq(_T_134, UInt<1>(0h0))
when _T_137 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_16
assert(clock, _T_134, UInt<1>(0h1), "") : assert_16
node _T_138 = eq(before, UInt<1>(0h1))
node _T_139 = eq(after, UInt<4>(0h8))
node _T_140 = and(_T_138, _T_139)
node _T_141 = eq(_T_140, UInt<1>(0h0))
node _T_142 = asUInt(reset)
node _T_143 = eq(_T_142, UInt<1>(0h0))
when _T_143 :
node _T_144 = eq(_T_141, UInt<1>(0h0))
when _T_144 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_17
assert(clock, _T_141, UInt<1>(0h1), "") : assert_17
node _T_145 = eq(before, UInt<1>(0h1))
node _T_146 = eq(after, UInt<1>(0h0))
node _T_147 = and(_T_145, _T_146)
node _T_148 = eq(_T_147, UInt<1>(0h0))
node _T_149 = asUInt(reset)
node _T_150 = eq(_T_149, UInt<1>(0h0))
when _T_150 :
node _T_151 = eq(_T_148, UInt<1>(0h0))
when _T_151 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_18
assert(clock, _T_148, UInt<1>(0h1), "") : assert_18
node _T_152 = eq(before, UInt<1>(0h1))
node _T_153 = eq(after, UInt<3>(0h7))
node _T_154 = and(_T_152, _T_153)
node _T_155 = eq(_T_154, UInt<1>(0h0))
node _T_156 = asUInt(reset)
node _T_157 = eq(_T_156, UInt<1>(0h0))
when _T_157 :
node _T_158 = eq(_T_155, UInt<1>(0h0))
when _T_158 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_19
assert(clock, _T_155, UInt<1>(0h1), "") : assert_19
node _T_159 = eq(before, UInt<1>(0h1))
node _T_160 = eq(after, UInt<3>(0h5))
node _T_161 = and(_T_159, _T_160)
node _T_162 = eq(_T_161, UInt<1>(0h0))
node _T_163 = asUInt(reset)
node _T_164 = eq(_T_163, UInt<1>(0h0))
when _T_164 :
node _T_165 = eq(_T_162, UInt<1>(0h0))
when _T_165 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_20
assert(clock, _T_162, UInt<1>(0h1), "") : assert_20
node _T_166 = eq(before, UInt<1>(0h1))
node _T_167 = eq(after, UInt<3>(0h4))
node _T_168 = and(_T_166, _T_167)
node _T_169 = eq(_T_168, UInt<1>(0h0))
node _T_170 = asUInt(reset)
node _T_171 = eq(_T_170, UInt<1>(0h0))
when _T_171 :
node _T_172 = eq(_T_169, UInt<1>(0h0))
when _T_172 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_21
assert(clock, _T_169, UInt<1>(0h1), "") : assert_21
node _T_173 = eq(before, UInt<1>(0h1))
node _T_174 = eq(after, UInt<3>(0h6))
node _T_175 = and(_T_173, _T_174)
node _T_176 = eq(_T_175, UInt<1>(0h0))
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(_T_176, UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_22
assert(clock, _T_176, UInt<1>(0h1), "") : assert_22
node _T_180 = eq(before, UInt<1>(0h1))
node _T_181 = eq(after, UInt<2>(0h3))
node _T_182 = and(_T_180, _T_181)
node _T_183 = eq(_T_182, UInt<1>(0h0))
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_23
assert(clock, _T_183, UInt<1>(0h1), "") : assert_23
node _T_187 = eq(before, UInt<1>(0h1))
node _T_188 = eq(after, UInt<2>(0h2))
node _T_189 = and(_T_187, _T_188)
node _T_190 = eq(_T_189, UInt<1>(0h0))
node _T_191 = asUInt(reset)
node _T_192 = eq(_T_191, UInt<1>(0h0))
when _T_192 :
node _T_193 = eq(_T_190, UInt<1>(0h0))
when _T_193 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_24
assert(clock, _T_190, UInt<1>(0h1), "") : assert_24
node _T_194 = eq(before, UInt<1>(0h0))
node _T_195 = eq(after, UInt<4>(0h8))
node _T_196 = and(_T_194, _T_195)
node _T_197 = eq(_T_196, UInt<1>(0h0))
node _T_198 = asUInt(reset)
node _T_199 = eq(_T_198, UInt<1>(0h0))
when _T_199 :
node _T_200 = eq(_T_197, UInt<1>(0h0))
when _T_200 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_25
assert(clock, _T_197, UInt<1>(0h1), "") : assert_25
node _T_201 = eq(before, UInt<1>(0h0))
node _T_202 = eq(after, UInt<1>(0h1))
node _T_203 = and(_T_201, _T_202)
node _T_204 = eq(_T_203, UInt<1>(0h0))
node _T_205 = asUInt(reset)
node _T_206 = eq(_T_205, UInt<1>(0h0))
when _T_206 :
node _T_207 = eq(_T_204, UInt<1>(0h0))
when _T_207 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_26
assert(clock, _T_204, UInt<1>(0h1), "") : assert_26
node _T_208 = eq(before, UInt<1>(0h0))
node _T_209 = eq(after, UInt<3>(0h7))
node _T_210 = and(_T_208, _T_209)
node _T_211 = eq(_T_210, UInt<1>(0h0))
node _T_212 = asUInt(reset)
node _T_213 = eq(_T_212, UInt<1>(0h0))
when _T_213 :
node _T_214 = eq(_T_211, UInt<1>(0h0))
when _T_214 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_27
assert(clock, _T_211, UInt<1>(0h1), "") : assert_27
node _T_215 = eq(before, UInt<1>(0h0))
node _T_216 = eq(after, UInt<3>(0h5))
node _T_217 = and(_T_215, _T_216)
node _T_218 = eq(_T_217, UInt<1>(0h0))
node _T_219 = asUInt(reset)
node _T_220 = eq(_T_219, UInt<1>(0h0))
when _T_220 :
node _T_221 = eq(_T_218, UInt<1>(0h0))
when _T_221 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_28
assert(clock, _T_218, UInt<1>(0h1), "") : assert_28
node _T_222 = eq(before, UInt<1>(0h0))
node _T_223 = eq(after, UInt<3>(0h6))
node _T_224 = and(_T_222, _T_223)
node _T_225 = eq(_T_224, UInt<1>(0h0))
node _T_226 = asUInt(reset)
node _T_227 = eq(_T_226, UInt<1>(0h0))
when _T_227 :
node _T_228 = eq(_T_225, UInt<1>(0h0))
when _T_228 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_29
assert(clock, _T_225, UInt<1>(0h1), "") : assert_29
node _T_229 = eq(before, UInt<1>(0h0))
node _T_230 = eq(after, UInt<3>(0h4))
node _T_231 = and(_T_229, _T_230)
node _T_232 = eq(_T_231, UInt<1>(0h0))
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_30
assert(clock, _T_232, UInt<1>(0h1), "") : assert_30
node _T_236 = eq(before, UInt<1>(0h0))
node _T_237 = eq(after, UInt<2>(0h3))
node _T_238 = and(_T_236, _T_237)
node _T_239 = eq(_T_238, UInt<1>(0h0))
node _T_240 = asUInt(reset)
node _T_241 = eq(_T_240, UInt<1>(0h0))
when _T_241 :
node _T_242 = eq(_T_239, UInt<1>(0h0))
when _T_242 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_31
assert(clock, _T_239, UInt<1>(0h1), "") : assert_31
node _T_243 = eq(before, UInt<1>(0h0))
node _T_244 = eq(after, UInt<2>(0h2))
node _T_245 = and(_T_243, _T_244)
node _T_246 = eq(_T_245, UInt<1>(0h0))
node _T_247 = asUInt(reset)
node _T_248 = eq(_T_247, UInt<1>(0h0))
when _T_248 :
node _T_249 = eq(_T_246, UInt<1>(0h0))
when _T_249 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_32
assert(clock, _T_246, UInt<1>(0h1), "") : assert_32
node _T_250 = eq(before, UInt<3>(0h7))
node _T_251 = eq(after, UInt<4>(0h8))
node _T_252 = and(_T_250, _T_251)
node _T_253 = eq(_T_252, UInt<1>(0h0))
node _T_254 = asUInt(reset)
node _T_255 = eq(_T_254, UInt<1>(0h0))
when _T_255 :
node _T_256 = eq(_T_253, UInt<1>(0h0))
when _T_256 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_33
assert(clock, _T_253, UInt<1>(0h1), "") : assert_33
node _T_257 = eq(before, UInt<3>(0h7))
node _T_258 = eq(after, UInt<1>(0h1))
node _T_259 = and(_T_257, _T_258)
node _T_260 = eq(_T_259, UInt<1>(0h0))
node _T_261 = asUInt(reset)
node _T_262 = eq(_T_261, UInt<1>(0h0))
when _T_262 :
node _T_263 = eq(_T_260, UInt<1>(0h0))
when _T_263 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_34
assert(clock, _T_260, UInt<1>(0h1), "") : assert_34
node _T_264 = eq(before, UInt<3>(0h7))
node _T_265 = eq(after, UInt<1>(0h0))
node _T_266 = and(_T_264, _T_265)
node _T_267 = eq(_T_266, UInt<1>(0h0))
node _T_268 = asUInt(reset)
node _T_269 = eq(_T_268, UInt<1>(0h0))
when _T_269 :
node _T_270 = eq(_T_267, UInt<1>(0h0))
when _T_270 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_35
assert(clock, _T_267, UInt<1>(0h1), "") : assert_35
node _T_271 = eq(before, UInt<3>(0h7))
node _T_272 = eq(after, UInt<3>(0h5))
node _T_273 = and(_T_271, _T_272)
node _T_274 = eq(_T_273, UInt<1>(0h0))
node _T_275 = asUInt(reset)
node _T_276 = eq(_T_275, UInt<1>(0h0))
when _T_276 :
node _T_277 = eq(_T_274, UInt<1>(0h0))
when _T_277 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_36
assert(clock, _T_274, UInt<1>(0h1), "") : assert_36
node _T_278 = eq(before, UInt<3>(0h7))
node _T_279 = eq(after, UInt<3>(0h6))
node _T_280 = and(_T_278, _T_279)
node _T_281 = eq(before, UInt<3>(0h7))
node _T_282 = eq(after, UInt<3>(0h4))
node _T_283 = and(_T_281, _T_282)
node _T_284 = eq(_T_283, UInt<1>(0h0))
node _T_285 = asUInt(reset)
node _T_286 = eq(_T_285, UInt<1>(0h0))
when _T_286 :
node _T_287 = eq(_T_284, UInt<1>(0h0))
when _T_287 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_37
assert(clock, _T_284, UInt<1>(0h1), "") : assert_37
node _T_288 = eq(before, UInt<3>(0h7))
node _T_289 = eq(after, UInt<2>(0h3))
node _T_290 = and(_T_288, _T_289)
node _T_291 = eq(before, UInt<3>(0h7))
node _T_292 = eq(after, UInt<2>(0h2))
node _T_293 = and(_T_291, _T_292)
node _T_294 = eq(_T_293, UInt<1>(0h0))
node _T_295 = asUInt(reset)
node _T_296 = eq(_T_295, UInt<1>(0h0))
when _T_296 :
node _T_297 = eq(_T_294, UInt<1>(0h0))
when _T_297 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_38
assert(clock, _T_294, UInt<1>(0h1), "") : assert_38
node _T_298 = eq(before, UInt<3>(0h5))
node _T_299 = eq(after, UInt<4>(0h8))
node _T_300 = and(_T_298, _T_299)
node _T_301 = eq(_T_300, UInt<1>(0h0))
node _T_302 = asUInt(reset)
node _T_303 = eq(_T_302, UInt<1>(0h0))
when _T_303 :
node _T_304 = eq(_T_301, UInt<1>(0h0))
when _T_304 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_39
assert(clock, _T_301, UInt<1>(0h1), "") : assert_39
node _T_305 = eq(before, UInt<3>(0h5))
node _T_306 = eq(after, UInt<1>(0h1))
node _T_307 = and(_T_305, _T_306)
node _T_308 = eq(_T_307, UInt<1>(0h0))
node _T_309 = asUInt(reset)
node _T_310 = eq(_T_309, UInt<1>(0h0))
when _T_310 :
node _T_311 = eq(_T_308, UInt<1>(0h0))
when _T_311 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_40
assert(clock, _T_308, UInt<1>(0h1), "") : assert_40
node _T_312 = eq(before, UInt<3>(0h5))
node _T_313 = eq(after, UInt<1>(0h0))
node _T_314 = and(_T_312, _T_313)
node _T_315 = eq(_T_314, UInt<1>(0h0))
node _T_316 = asUInt(reset)
node _T_317 = eq(_T_316, UInt<1>(0h0))
when _T_317 :
node _T_318 = eq(_T_315, UInt<1>(0h0))
when _T_318 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_41
assert(clock, _T_315, UInt<1>(0h1), "") : assert_41
node _T_319 = eq(before, UInt<3>(0h5))
node _T_320 = eq(after, UInt<3>(0h7))
node _T_321 = and(_T_319, _T_320)
node _T_322 = eq(before, UInt<3>(0h5))
node _T_323 = eq(after, UInt<3>(0h6))
node _T_324 = and(_T_322, _T_323)
node _T_325 = eq(before, UInt<3>(0h5))
node _T_326 = eq(after, UInt<3>(0h4))
node _T_327 = and(_T_325, _T_326)
node _T_328 = eq(_T_327, UInt<1>(0h0))
node _T_329 = asUInt(reset)
node _T_330 = eq(_T_329, UInt<1>(0h0))
when _T_330 :
node _T_331 = eq(_T_328, UInt<1>(0h0))
when _T_331 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_42
assert(clock, _T_328, UInt<1>(0h1), "") : assert_42
node _T_332 = eq(before, UInt<3>(0h5))
node _T_333 = eq(after, UInt<2>(0h3))
node _T_334 = and(_T_332, _T_333)
node _T_335 = eq(before, UInt<3>(0h5))
node _T_336 = eq(after, UInt<2>(0h2))
node _T_337 = and(_T_335, _T_336)
node _T_338 = eq(_T_337, UInt<1>(0h0))
node _T_339 = asUInt(reset)
node _T_340 = eq(_T_339, UInt<1>(0h0))
when _T_340 :
node _T_341 = eq(_T_338, UInt<1>(0h0))
when _T_341 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_43
assert(clock, _T_338, UInt<1>(0h1), "") : assert_43
node _T_342 = eq(before, UInt<3>(0h6))
node _T_343 = eq(after, UInt<4>(0h8))
node _T_344 = and(_T_342, _T_343)
node _T_345 = eq(_T_344, UInt<1>(0h0))
node _T_346 = asUInt(reset)
node _T_347 = eq(_T_346, UInt<1>(0h0))
when _T_347 :
node _T_348 = eq(_T_345, UInt<1>(0h0))
when _T_348 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_44
assert(clock, _T_345, UInt<1>(0h1), "") : assert_44
node _T_349 = eq(before, UInt<3>(0h6))
node _T_350 = eq(after, UInt<1>(0h1))
node _T_351 = and(_T_349, _T_350)
node _T_352 = eq(_T_351, UInt<1>(0h0))
node _T_353 = asUInt(reset)
node _T_354 = eq(_T_353, UInt<1>(0h0))
when _T_354 :
node _T_355 = eq(_T_352, UInt<1>(0h0))
when _T_355 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_45
assert(clock, _T_352, UInt<1>(0h1), "") : assert_45
node _T_356 = eq(before, UInt<3>(0h6))
node _T_357 = eq(after, UInt<1>(0h0))
node _T_358 = and(_T_356, _T_357)
node _T_359 = eq(_T_358, UInt<1>(0h0))
node _T_360 = asUInt(reset)
node _T_361 = eq(_T_360, UInt<1>(0h0))
when _T_361 :
node _T_362 = eq(_T_359, UInt<1>(0h0))
when _T_362 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_46
assert(clock, _T_359, UInt<1>(0h1), "") : assert_46
node _T_363 = eq(before, UInt<3>(0h6))
node _T_364 = eq(after, UInt<3>(0h7))
node _T_365 = and(_T_363, _T_364)
node _T_366 = eq(_T_365, UInt<1>(0h0))
node _T_367 = asUInt(reset)
node _T_368 = eq(_T_367, UInt<1>(0h0))
when _T_368 :
node _T_369 = eq(_T_366, UInt<1>(0h0))
when _T_369 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_47
assert(clock, _T_366, UInt<1>(0h1), "") : assert_47
node _T_370 = eq(before, UInt<3>(0h6))
node _T_371 = eq(after, UInt<3>(0h5))
node _T_372 = and(_T_370, _T_371)
node _T_373 = eq(_T_372, UInt<1>(0h0))
node _T_374 = asUInt(reset)
node _T_375 = eq(_T_374, UInt<1>(0h0))
when _T_375 :
node _T_376 = eq(_T_373, UInt<1>(0h0))
when _T_376 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_48
assert(clock, _T_373, UInt<1>(0h1), "") : assert_48
node _T_377 = eq(before, UInt<3>(0h6))
node _T_378 = eq(after, UInt<3>(0h4))
node _T_379 = and(_T_377, _T_378)
node _T_380 = eq(_T_379, UInt<1>(0h0))
node _T_381 = asUInt(reset)
node _T_382 = eq(_T_381, UInt<1>(0h0))
when _T_382 :
node _T_383 = eq(_T_380, UInt<1>(0h0))
when _T_383 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_49
assert(clock, _T_380, UInt<1>(0h1), "") : assert_49
node _T_384 = eq(before, UInt<3>(0h6))
node _T_385 = eq(after, UInt<2>(0h3))
node _T_386 = and(_T_384, _T_385)
node _T_387 = eq(_T_386, UInt<1>(0h0))
node _T_388 = asUInt(reset)
node _T_389 = eq(_T_388, UInt<1>(0h0))
when _T_389 :
node _T_390 = eq(_T_387, UInt<1>(0h0))
when _T_390 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_50
assert(clock, _T_387, UInt<1>(0h1), "") : assert_50
node _T_391 = eq(before, UInt<3>(0h6))
node _T_392 = eq(after, UInt<2>(0h2))
node _T_393 = and(_T_391, _T_392)
node _T_394 = eq(before, UInt<3>(0h4))
node _T_395 = eq(after, UInt<4>(0h8))
node _T_396 = and(_T_394, _T_395)
node _T_397 = eq(_T_396, UInt<1>(0h0))
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(_T_397, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_51
assert(clock, _T_397, UInt<1>(0h1), "") : assert_51
node _T_401 = eq(before, UInt<3>(0h4))
node _T_402 = eq(after, UInt<1>(0h1))
node _T_403 = and(_T_401, _T_402)
node _T_404 = eq(_T_403, UInt<1>(0h0))
node _T_405 = asUInt(reset)
node _T_406 = eq(_T_405, UInt<1>(0h0))
when _T_406 :
node _T_407 = eq(_T_404, UInt<1>(0h0))
when _T_407 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_52
assert(clock, _T_404, UInt<1>(0h1), "") : assert_52
node _T_408 = eq(before, UInt<3>(0h4))
node _T_409 = eq(after, UInt<1>(0h0))
node _T_410 = and(_T_408, _T_409)
node _T_411 = eq(_T_410, UInt<1>(0h0))
node _T_412 = asUInt(reset)
node _T_413 = eq(_T_412, UInt<1>(0h0))
when _T_413 :
node _T_414 = eq(_T_411, UInt<1>(0h0))
when _T_414 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_53
assert(clock, _T_411, UInt<1>(0h1), "") : assert_53
node _T_415 = eq(before, UInt<3>(0h4))
node _T_416 = eq(after, UInt<3>(0h7))
node _T_417 = and(_T_415, _T_416)
node _T_418 = eq(_T_417, UInt<1>(0h0))
node _T_419 = asUInt(reset)
node _T_420 = eq(_T_419, UInt<1>(0h0))
when _T_420 :
node _T_421 = eq(_T_418, UInt<1>(0h0))
when _T_421 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_54
assert(clock, _T_418, UInt<1>(0h1), "") : assert_54
node _T_422 = eq(before, UInt<3>(0h4))
node _T_423 = eq(after, UInt<3>(0h5))
node _T_424 = and(_T_422, _T_423)
node _T_425 = eq(_T_424, UInt<1>(0h0))
node _T_426 = asUInt(reset)
node _T_427 = eq(_T_426, UInt<1>(0h0))
when _T_427 :
node _T_428 = eq(_T_425, UInt<1>(0h0))
when _T_428 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_55
assert(clock, _T_425, UInt<1>(0h1), "") : assert_55
node _T_429 = eq(before, UInt<3>(0h4))
node _T_430 = eq(after, UInt<3>(0h6))
node _T_431 = and(_T_429, _T_430)
node _T_432 = eq(before, UInt<3>(0h4))
node _T_433 = eq(after, UInt<2>(0h3))
node _T_434 = and(_T_432, _T_433)
node _T_435 = eq(_T_434, UInt<1>(0h0))
node _T_436 = asUInt(reset)
node _T_437 = eq(_T_436, UInt<1>(0h0))
when _T_437 :
node _T_438 = eq(_T_435, UInt<1>(0h0))
when _T_438 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_56
assert(clock, _T_435, UInt<1>(0h1), "") : assert_56
node _T_439 = eq(before, UInt<3>(0h4))
node _T_440 = eq(after, UInt<2>(0h2))
node _T_441 = and(_T_439, _T_440)
node _T_442 = eq(before, UInt<2>(0h3))
node _T_443 = eq(after, UInt<4>(0h8))
node _T_444 = and(_T_442, _T_443)
node _T_445 = eq(_T_444, UInt<1>(0h0))
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_57
assert(clock, _T_445, UInt<1>(0h1), "") : assert_57
node _T_449 = eq(before, UInt<2>(0h3))
node _T_450 = eq(after, UInt<1>(0h1))
node _T_451 = and(_T_449, _T_450)
node _T_452 = eq(_T_451, UInt<1>(0h0))
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(_T_452, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_58
assert(clock, _T_452, UInt<1>(0h1), "") : assert_58
node _T_456 = eq(before, UInt<2>(0h3))
node _T_457 = eq(after, UInt<1>(0h0))
node _T_458 = and(_T_456, _T_457)
node _T_459 = eq(_T_458, UInt<1>(0h0))
node _T_460 = asUInt(reset)
node _T_461 = eq(_T_460, UInt<1>(0h0))
when _T_461 :
node _T_462 = eq(_T_459, UInt<1>(0h0))
when _T_462 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_59
assert(clock, _T_459, UInt<1>(0h1), "") : assert_59
node _T_463 = eq(before, UInt<2>(0h3))
node _T_464 = eq(after, UInt<3>(0h7))
node _T_465 = and(_T_463, _T_464)
node _T_466 = eq(before, UInt<2>(0h3))
node _T_467 = eq(after, UInt<3>(0h5))
node _T_468 = and(_T_466, _T_467)
node _T_469 = eq(before, UInt<2>(0h3))
node _T_470 = eq(after, UInt<3>(0h6))
node _T_471 = and(_T_469, _T_470)
node _T_472 = eq(before, UInt<2>(0h3))
node _T_473 = eq(after, UInt<3>(0h4))
node _T_474 = and(_T_472, _T_473)
node _T_475 = eq(before, UInt<2>(0h3))
node _T_476 = eq(after, UInt<2>(0h2))
node _T_477 = and(_T_475, _T_476)
node _T_478 = eq(before, UInt<2>(0h2))
node _T_479 = eq(after, UInt<4>(0h8))
node _T_480 = and(_T_478, _T_479)
node _T_481 = eq(_T_480, UInt<1>(0h0))
node _T_482 = asUInt(reset)
node _T_483 = eq(_T_482, UInt<1>(0h0))
when _T_483 :
node _T_484 = eq(_T_481, UInt<1>(0h0))
when _T_484 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_60
assert(clock, _T_481, UInt<1>(0h1), "") : assert_60
node _T_485 = eq(before, UInt<2>(0h2))
node _T_486 = eq(after, UInt<1>(0h1))
node _T_487 = and(_T_485, _T_486)
node _T_488 = eq(_T_487, UInt<1>(0h0))
node _T_489 = asUInt(reset)
node _T_490 = eq(_T_489, UInt<1>(0h0))
when _T_490 :
node _T_491 = eq(_T_488, UInt<1>(0h0))
when _T_491 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_61
assert(clock, _T_488, UInt<1>(0h1), "") : assert_61
node _T_492 = eq(before, UInt<2>(0h2))
node _T_493 = eq(after, UInt<1>(0h0))
node _T_494 = and(_T_492, _T_493)
node _T_495 = eq(_T_494, UInt<1>(0h0))
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(_T_495, UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_62
assert(clock, _T_495, UInt<1>(0h1), "") : assert_62
node _T_499 = eq(before, UInt<2>(0h2))
node _T_500 = eq(after, UInt<3>(0h7))
node _T_501 = and(_T_499, _T_500)
node _T_502 = eq(_T_501, UInt<1>(0h0))
node _T_503 = asUInt(reset)
node _T_504 = eq(_T_503, UInt<1>(0h0))
when _T_504 :
node _T_505 = eq(_T_502, UInt<1>(0h0))
when _T_505 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_63
assert(clock, _T_502, UInt<1>(0h1), "") : assert_63
node _T_506 = eq(before, UInt<2>(0h2))
node _T_507 = eq(after, UInt<3>(0h5))
node _T_508 = and(_T_506, _T_507)
node _T_509 = eq(_T_508, UInt<1>(0h0))
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_T_509, UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_64
assert(clock, _T_509, UInt<1>(0h1), "") : assert_64
node _T_513 = eq(before, UInt<2>(0h2))
node _T_514 = eq(after, UInt<3>(0h6))
node _T_515 = and(_T_513, _T_514)
node _T_516 = eq(before, UInt<2>(0h2))
node _T_517 = eq(after, UInt<3>(0h4))
node _T_518 = and(_T_516, _T_517)
node _T_519 = eq(before, UInt<2>(0h2))
node _T_520 = eq(after, UInt<2>(0h3))
node _T_521 = and(_T_519, _T_520)
node _T_522 = eq(_T_521, UInt<1>(0h0))
node _T_523 = asUInt(reset)
node _T_524 = eq(_T_523, UInt<1>(0h0))
when _T_524 :
node _T_525 = eq(_T_522, UInt<1>(0h0))
when _T_525 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_65
assert(clock, _T_522, UInt<1>(0h1), "") : assert_65
node probe_bit = eq(io.sinkc.bits.source, UInt<6>(0h20))
node _last_probe_T = or(probes_done, probe_bit)
node _last_probe_T_1 = not(excluded_client)
node _last_probe_T_2 = and(meta.clients, _last_probe_T_1)
node last_probe = eq(_last_probe_T, _last_probe_T_2)
node _probe_toN_T = eq(io.sinkc.bits.param, UInt<3>(0h1))
node _probe_toN_T_1 = eq(io.sinkc.bits.param, UInt<3>(0h2))
node _probe_toN_T_2 = or(_probe_toN_T, _probe_toN_T_1)
node _probe_toN_T_3 = eq(io.sinkc.bits.param, UInt<3>(0h5))
node probe_toN = or(_probe_toN_T_2, _probe_toN_T_3)
when io.sinkc.valid :
node _T_526 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1))
node _T_527 = and(probe_toN, _T_526)
node _T_528 = eq(probe_toN, UInt<1>(0h0))
node _T_529 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1))
node _T_530 = and(_T_528, _T_529)
node _probes_done_T = or(probes_done, probe_bit)
connect probes_done, _probes_done_T
node _probes_toN_T = mux(probe_toN, probe_bit, UInt<1>(0h0))
node _probes_toN_T_1 = or(probes_toN, _probes_toN_T)
connect probes_toN, _probes_toN_T_1
node _probes_noT_T = neq(io.sinkc.bits.param, UInt<3>(0h3))
node _probes_noT_T_1 = or(probes_noT, _probes_noT_T)
connect probes_noT, _probes_noT_T_1
node _w_rprobeackfirst_T = or(w_rprobeackfirst, last_probe)
connect w_rprobeackfirst, _w_rprobeackfirst_T
node _w_rprobeacklast_T = and(last_probe, io.sinkc.bits.last)
node _w_rprobeacklast_T_1 = or(w_rprobeacklast, _w_rprobeacklast_T)
connect w_rprobeacklast, _w_rprobeacklast_T_1
node _w_pprobeackfirst_T = or(w_pprobeackfirst, last_probe)
connect w_pprobeackfirst, _w_pprobeackfirst_T
node _w_pprobeacklast_T = and(last_probe, io.sinkc.bits.last)
node _w_pprobeacklast_T_1 = or(w_pprobeacklast, _w_pprobeacklast_T)
connect w_pprobeacklast, _w_pprobeacklast_T_1
node _set_pprobeack_T = eq(request.offset, UInt<1>(0h0))
node _set_pprobeack_T_1 = or(io.sinkc.bits.last, _set_pprobeack_T)
node set_pprobeack = and(last_probe, _set_pprobeack_T_1)
node _w_pprobeack_T = or(w_pprobeack, set_pprobeack)
connect w_pprobeack, _w_pprobeack_T
node _T_531 = eq(set_pprobeack, UInt<1>(0h0))
node _T_532 = and(_T_531, w_rprobeackfirst)
node _T_533 = and(set_pprobeack, w_rprobeackfirst)
node _T_534 = neq(meta.state, UInt<2>(0h0))
node _T_535 = eq(io.sinkc.bits.tag, meta.tag)
node _T_536 = and(_T_534, _T_535)
node _T_537 = and(_T_536, io.sinkc.bits.data)
when _T_537 :
connect meta.dirty, UInt<1>(0h1)
when io.sinkd.valid :
node _T_538 = eq(io.sinkd.bits.opcode, UInt<3>(0h4))
node _T_539 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_540 = or(_T_538, _T_539)
when _T_540 :
connect sink, io.sinkd.bits.sink
connect w_grantfirst, UInt<1>(0h1)
connect w_grantlast, io.sinkd.bits.last
connect bad_grant, io.sinkd.bits.denied
node _w_grant_T = eq(request.offset, UInt<1>(0h0))
node _w_grant_T_1 = or(_w_grant_T, io.sinkd.bits.last)
connect w_grant, _w_grant_T_1
node _T_541 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_542 = eq(request.offset, UInt<1>(0h0))
node _T_543 = and(_T_541, _T_542)
node _T_544 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_545 = neq(request.offset, UInt<1>(0h0))
node _T_546 = and(_T_544, _T_545)
node _gotT_T = eq(io.sinkd.bits.param, UInt<2>(0h0))
connect gotT, _gotT_T
else :
node _T_547 = eq(io.sinkd.bits.opcode, UInt<3>(0h6))
when _T_547 :
connect w_releaseack, UInt<1>(0h1)
when io.sinke.valid :
connect w_grantack, UInt<1>(0h1)
wire allocate_as_full : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>}
connect allocate_as_full.set, io.allocate.bits.set
connect allocate_as_full.put, io.allocate.bits.put
connect allocate_as_full.offset, io.allocate.bits.offset
connect allocate_as_full.tag, io.allocate.bits.tag
connect allocate_as_full.source, io.allocate.bits.source
connect allocate_as_full.size, io.allocate.bits.size
connect allocate_as_full.param, io.allocate.bits.param
connect allocate_as_full.opcode, io.allocate.bits.opcode
connect allocate_as_full.control, io.allocate.bits.control
connect allocate_as_full.prio, io.allocate.bits.prio
node _new_meta_T = and(io.allocate.valid, io.allocate.bits.repeat)
node new_meta = mux(_new_meta_T, final_meta_writeback, io.directory.bits)
node new_request = mux(io.allocate.valid, allocate_as_full, request)
node _new_needT_T = bits(new_request.opcode, 2, 2)
node _new_needT_T_1 = eq(_new_needT_T, UInt<1>(0h0))
node _new_needT_T_2 = eq(new_request.opcode, UInt<3>(0h5))
node _new_needT_T_3 = eq(new_request.param, UInt<1>(0h1))
node _new_needT_T_4 = and(_new_needT_T_2, _new_needT_T_3)
node _new_needT_T_5 = or(_new_needT_T_1, _new_needT_T_4)
node _new_needT_T_6 = eq(new_request.opcode, UInt<3>(0h6))
node _new_needT_T_7 = eq(new_request.opcode, UInt<3>(0h7))
node _new_needT_T_8 = or(_new_needT_T_6, _new_needT_T_7)
node _new_needT_T_9 = neq(new_request.param, UInt<2>(0h0))
node _new_needT_T_10 = and(_new_needT_T_8, _new_needT_T_9)
node new_needT = or(_new_needT_T_5, _new_needT_T_10)
node new_clientBit = eq(new_request.source, UInt<6>(0h20))
node _new_skipProbe_T = eq(new_request.opcode, UInt<3>(0h6))
node _new_skipProbe_T_1 = eq(new_request.opcode, UInt<3>(0h7))
node _new_skipProbe_T_2 = or(_new_skipProbe_T, _new_skipProbe_T_1)
node _new_skipProbe_T_3 = eq(new_request.opcode, UInt<3>(0h4))
node _new_skipProbe_T_4 = or(_new_skipProbe_T_2, _new_skipProbe_T_3)
node _new_skipProbe_T_5 = eq(new_request.opcode, UInt<3>(0h5))
node _new_skipProbe_T_6 = and(_new_skipProbe_T_5, UInt<1>(0h0))
node _new_skipProbe_T_7 = or(_new_skipProbe_T_4, _new_skipProbe_T_6)
node new_skipProbe = mux(_new_skipProbe_T_7, new_clientBit, UInt<1>(0h0))
wire prior : UInt
connect prior, UInt<1>(0h0)
node prior_c = orr(final_meta_writeback.clients)
node _prior_T = eq(UInt<2>(0h1), final_meta_writeback.state)
when _prior_T :
node _prior_out_T = mux(prior_c, UInt<1>(0h0), UInt<1>(0h1))
connect prior, _prior_out_T
else :
node _prior_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state)
when _prior_T_1 :
node _prior_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect prior, _prior_out_T_1
else :
node _prior_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state)
when _prior_T_2 :
node _prior_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _prior_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _prior_out_T_4 = mux(prior_c, _prior_out_T_2, _prior_out_T_3)
connect prior, _prior_out_T_4
else :
node _prior_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state)
when _prior_T_3 :
connect prior, UInt<4>(0h8)
node _prior_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0))
when _prior_T_4 :
connect prior, UInt<4>(0h8)
node _T_548 = and(io.allocate.valid, io.allocate.bits.repeat)
when _T_548 :
node _T_549 = eq(prior, UInt<4>(0h8))
node _T_550 = eq(prior, UInt<1>(0h1))
node _T_551 = eq(_T_550, UInt<1>(0h0))
node _T_552 = asUInt(reset)
node _T_553 = eq(_T_552, UInt<1>(0h0))
when _T_553 :
node _T_554 = eq(_T_551, UInt<1>(0h0))
when _T_554 :
printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_66
assert(clock, _T_551, UInt<1>(0h1), "") : assert_66
node _T_555 = eq(prior, UInt<1>(0h0))
node _T_556 = eq(_T_555, UInt<1>(0h0))
node _T_557 = asUInt(reset)
node _T_558 = eq(_T_557, UInt<1>(0h0))
when _T_558 :
node _T_559 = eq(_T_556, UInt<1>(0h0))
when _T_559 :
printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_67
assert(clock, _T_556, UInt<1>(0h1), "") : assert_67
node _T_560 = eq(prior, UInt<3>(0h7))
node _T_561 = eq(prior, UInt<3>(0h5))
node _T_562 = eq(prior, UInt<3>(0h4))
node _T_563 = eq(prior, UInt<3>(0h6))
node _T_564 = eq(prior, UInt<2>(0h3))
node _T_565 = eq(prior, UInt<2>(0h2))
when io.allocate.valid :
node _T_566 = eq(request_valid, UInt<1>(0h0))
node _T_567 = and(io.schedule.ready, io.schedule.valid)
node _T_568 = and(no_wait, _T_567)
node _T_569 = or(_T_566, _T_568)
node _T_570 = asUInt(reset)
node _T_571 = eq(_T_570, UInt<1>(0h0))
when _T_571 :
node _T_572 = eq(_T_569, UInt<1>(0h0))
when _T_572 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:533 assert (!request_valid || (no_wait && io.schedule.fire))\n") : printf_68
assert(clock, _T_569, UInt<1>(0h1), "") : assert_68
connect request_valid, UInt<1>(0h1)
connect request.set, io.allocate.bits.set
connect request.put, io.allocate.bits.put
connect request.offset, io.allocate.bits.offset
connect request.tag, io.allocate.bits.tag
connect request.source, io.allocate.bits.source
connect request.size, io.allocate.bits.size
connect request.param, io.allocate.bits.param
connect request.opcode, io.allocate.bits.opcode
connect request.control, io.allocate.bits.control
connect request.prio, io.allocate.bits.prio
node _T_573 = and(io.allocate.valid, io.allocate.bits.repeat)
node _T_574 = or(io.directory.valid, _T_573)
when _T_574 :
connect meta_valid, UInt<1>(0h1)
connect meta, new_meta
connect probes_done, UInt<1>(0h0)
connect probes_toN, UInt<1>(0h0)
connect probes_noT, UInt<1>(0h0)
connect gotT, UInt<1>(0h0)
connect bad_grant, UInt<1>(0h0)
connect s_rprobe, UInt<1>(0h1)
connect w_rprobeackfirst, UInt<1>(0h1)
connect w_rprobeacklast, UInt<1>(0h1)
connect s_release, UInt<1>(0h1)
connect w_releaseack, UInt<1>(0h1)
connect s_pprobe, UInt<1>(0h1)
connect s_acquire, UInt<1>(0h1)
connect s_flush, UInt<1>(0h1)
connect w_grantfirst, UInt<1>(0h1)
connect w_grantlast, UInt<1>(0h1)
connect w_grant, UInt<1>(0h1)
connect w_pprobeackfirst, UInt<1>(0h1)
connect w_pprobeacklast, UInt<1>(0h1)
connect w_pprobeack, UInt<1>(0h1)
connect s_probeack, UInt<1>(0h1)
connect s_grantack, UInt<1>(0h1)
connect s_execute, UInt<1>(0h1)
connect w_grantack, UInt<1>(0h1)
connect s_writeback, UInt<1>(0h1)
node _T_575 = and(new_request.prio[2], UInt<1>(0h1))
when _T_575 :
connect s_execute, UInt<1>(0h0)
node _T_576 = bits(new_request.opcode, 0, 0)
node _T_577 = eq(new_meta.dirty, UInt<1>(0h0))
node _T_578 = and(_T_576, _T_577)
when _T_578 :
connect s_writeback, UInt<1>(0h0)
node _T_579 = eq(new_request.param, UInt<3>(0h0))
node _T_580 = eq(new_request.param, UInt<3>(0h4))
node _T_581 = or(_T_579, _T_580)
node _T_582 = eq(new_meta.state, UInt<2>(0h2))
node _T_583 = and(_T_581, _T_582)
when _T_583 :
connect s_writeback, UInt<1>(0h0)
node _T_584 = eq(new_request.param, UInt<3>(0h1))
node _T_585 = eq(new_request.param, UInt<3>(0h2))
node _T_586 = or(_T_584, _T_585)
node _T_587 = eq(new_request.param, UInt<3>(0h5))
node _T_588 = or(_T_586, _T_587)
node _T_589 = and(new_meta.clients, new_clientBit)
node _T_590 = neq(_T_589, UInt<1>(0h0))
node _T_591 = and(_T_588, _T_590)
when _T_591 :
connect s_writeback, UInt<1>(0h0)
node _T_592 = asUInt(reset)
node _T_593 = eq(_T_592, UInt<1>(0h0))
when _T_593 :
node _T_594 = eq(new_meta.hit, UInt<1>(0h0))
when _T_594 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:585 assert (new_meta.hit)\n") : printf_69
assert(clock, new_meta.hit, UInt<1>(0h1), "") : assert_69
else :
node _T_595 = and(new_request.control, UInt<1>(0h1))
when _T_595 :
connect s_flush, UInt<1>(0h0)
when new_meta.hit :
connect s_release, UInt<1>(0h0)
connect w_releaseack, UInt<1>(0h0)
node _T_596 = neq(new_meta.clients, UInt<1>(0h0))
node _T_597 = and(UInt<1>(0h1), _T_596)
when _T_597 :
connect s_rprobe, UInt<1>(0h0)
connect w_rprobeackfirst, UInt<1>(0h0)
connect w_rprobeacklast, UInt<1>(0h0)
else :
connect s_execute, UInt<1>(0h0)
node _T_598 = eq(new_meta.hit, UInt<1>(0h0))
node _T_599 = neq(new_meta.state, UInt<2>(0h0))
node _T_600 = and(_T_598, _T_599)
when _T_600 :
connect s_release, UInt<1>(0h0)
connect w_releaseack, UInt<1>(0h0)
node _T_601 = neq(new_meta.clients, UInt<1>(0h0))
node _T_602 = and(UInt<1>(0h1), _T_601)
when _T_602 :
connect s_rprobe, UInt<1>(0h0)
connect w_rprobeackfirst, UInt<1>(0h0)
connect w_rprobeacklast, UInt<1>(0h0)
node _T_603 = eq(new_meta.hit, UInt<1>(0h0))
node _T_604 = eq(new_meta.state, UInt<2>(0h1))
node _T_605 = and(_T_604, new_needT)
node _T_606 = or(_T_603, _T_605)
when _T_606 :
connect s_acquire, UInt<1>(0h0)
connect w_grantfirst, UInt<1>(0h0)
connect w_grantlast, UInt<1>(0h0)
connect w_grant, UInt<1>(0h0)
connect s_grantack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_607 = eq(new_meta.state, UInt<2>(0h2))
node _T_608 = or(new_needT, _T_607)
node _T_609 = and(new_meta.hit, _T_608)
node _T_610 = not(new_skipProbe)
node _T_611 = and(new_meta.clients, _T_610)
node _T_612 = neq(_T_611, UInt<1>(0h0))
node _T_613 = and(_T_609, _T_612)
node _T_614 = and(UInt<1>(0h1), _T_613)
when _T_614 :
connect s_pprobe, UInt<1>(0h0)
connect w_pprobeackfirst, UInt<1>(0h0)
connect w_pprobeacklast, UInt<1>(0h0)
connect w_pprobeack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_615 = eq(new_request.opcode, UInt<3>(0h6))
node _T_616 = eq(new_request.opcode, UInt<3>(0h7))
node _T_617 = or(_T_615, _T_616)
when _T_617 :
connect w_grantack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_618 = bits(new_request.opcode, 2, 2)
node _T_619 = eq(_T_618, UInt<1>(0h0))
node _T_620 = and(_T_619, new_meta.hit)
node _T_621 = eq(new_meta.dirty, UInt<1>(0h0))
node _T_622 = and(_T_620, _T_621)
when _T_622 :
connect s_writeback, UInt<1>(0h0) | module MSHR_5( // @[MSHR.scala:84:7]
input clock, // @[MSHR.scala:84:7]
input reset, // @[MSHR.scala:84:7]
input io_allocate_valid, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_1, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_2, // @[MSHR.scala:86:14]
input io_allocate_bits_control, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14]
input [12:0] io_allocate_bits_tag, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14]
input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14]
input io_allocate_bits_repeat, // @[MSHR.scala:86:14]
input io_directory_valid, // @[MSHR.scala:86:14]
input io_directory_bits_dirty, // @[MSHR.scala:86:14]
input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14]
input io_directory_bits_clients, // @[MSHR.scala:86:14]
input [12:0] io_directory_bits_tag, // @[MSHR.scala:86:14]
input io_directory_bits_hit, // @[MSHR.scala:86:14]
input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14]
output io_status_valid, // @[MSHR.scala:86:14]
output [9:0] io_status_bits_set, // @[MSHR.scala:86:14]
output [12:0] io_status_bits_tag, // @[MSHR.scala:86:14]
output [2:0] io_status_bits_way, // @[MSHR.scala:86:14]
output io_status_bits_blockB, // @[MSHR.scala:86:14]
output io_status_bits_nestB, // @[MSHR.scala:86:14]
output io_status_bits_blockC, // @[MSHR.scala:86:14]
output io_status_bits_nestC, // @[MSHR.scala:86:14]
input io_schedule_ready, // @[MSHR.scala:86:14]
output io_schedule_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_a_valid, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14]
output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14]
output io_schedule_bits_b_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14]
output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14]
output io_schedule_bits_c_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14]
output io_schedule_bits_d_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14]
output io_schedule_bits_e_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14]
output io_schedule_bits_x_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14]
output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14]
output io_schedule_bits_reload, // @[MSHR.scala:86:14]
input io_sinkc_valid, // @[MSHR.scala:86:14]
input io_sinkc_bits_last, // @[MSHR.scala:86:14]
input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14]
input [12:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14]
input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14]
input io_sinkc_bits_data, // @[MSHR.scala:86:14]
input io_sinkd_valid, // @[MSHR.scala:86:14]
input io_sinkd_bits_last, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14]
input io_sinkd_bits_denied, // @[MSHR.scala:86:14]
input io_sinke_valid, // @[MSHR.scala:86:14]
input [2:0] io_sinke_bits_sink, // @[MSHR.scala:86:14]
input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14]
input [12:0] io_nestedwb_tag, // @[MSHR.scala:86:14]
input io_nestedwb_b_toN, // @[MSHR.scala:86:14]
input io_nestedwb_b_toB, // @[MSHR.scala:86:14]
input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14]
input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14]
);
wire [12:0] final_meta_writeback_tag; // @[MSHR.scala:215:38]
wire final_meta_writeback_clients; // @[MSHR.scala:215:38]
wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38]
wire final_meta_writeback_dirty; // @[MSHR.scala:215:38]
wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7]
wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7]
wire [12:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7]
wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7]
wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7]
wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7]
wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7]
wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7]
wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7]
wire [12:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7]
wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7]
wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7]
wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7]
wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7]
wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7]
wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7]
wire [12:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7]
wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7]
wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7]
wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7]
wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7]
wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7]
wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7]
wire [2:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7]
wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7]
wire [12:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7]
wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7]
wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_0 = 1'h0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_0 = 1'h0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7]
wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68]
wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80]
wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21]
wire invalid_clients = 1'h0; // @[MSHR.scala:268:21]
wire _excluded_client_T = 1'h0; // @[MSHR.scala:279:38]
wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137]
wire _excluded_client_T_9 = 1'h0; // @[MSHR.scala:279:57]
wire excluded_client = 1'h0; // @[MSHR.scala:279:28]
wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire allocate_as_full_prio_0 = 1'h0; // @[MSHR.scala:504:34]
wire new_request_prio_0 = 1'h0; // @[MSHR.scala:506:24]
wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137]
wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire _io_schedule_bits_b_bits_clients_T = 1'h1; // @[MSHR.scala:289:53]
wire _last_probe_T_1 = 1'h1; // @[MSHR.scala:459:66]
wire [2:0] io_schedule_bits_a_bits_source = 3'h0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_source = 3'h0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_sink = 3'h0; // @[MSHR.scala:84:7]
wire [12:0] invalid_tag = 13'h0; // @[MSHR.scala:268:21]
wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21]
wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70]
wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34]
wire [12:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34]
wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34]
wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40]
wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93]
wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28]
wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39]
wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105]
wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55]
wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91]
wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41]
wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41]
wire [12:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41]
wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51]
wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64]
wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41]
wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41]
wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57]
wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41]
wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43]
wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40]
wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66]
wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41]
wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41]
wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41]
wire [12:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41]
wire no_wait; // @[MSHR.scala:183:83]
wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7]
wire [12:0] io_status_bits_tag_0; // @[MSHR.scala:84:7]
wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockB_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestB_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockC_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestC_0; // @[MSHR.scala:84:7]
wire io_status_valid_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7]
wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7]
wire io_schedule_valid_0; // @[MSHR.scala:84:7]
reg request_valid; // @[MSHR.scala:97:30]
assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30]
reg request_prio_1; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20]
reg request_prio_2; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20]
reg request_control; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_opcode; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_param; // @[MSHR.scala:98:20]
reg [2:0] request_size; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_source; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20]
reg [12:0] request_tag; // @[MSHR.scala:98:20]
assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_offset; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_put; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20]
reg [9:0] request_set; // @[MSHR.scala:98:20]
assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
reg meta_valid; // @[MSHR.scala:99:27]
reg meta_dirty; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17]
reg [1:0] meta_state; // @[MSHR.scala:100:17]
reg meta_clients; // @[MSHR.scala:100:17]
wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39]
assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients; // @[MSHR.scala:100:17, :289:51]
wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27]
wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27]
wire _last_probe_T_2 = meta_clients; // @[MSHR.scala:100:17, :459:64]
reg [12:0] meta_tag; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17]
reg meta_hit; // @[MSHR.scala:100:17]
reg [2:0] meta_way; // @[MSHR.scala:100:17]
assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38]
reg s_rprobe; // @[MSHR.scala:121:33]
reg w_rprobeackfirst; // @[MSHR.scala:122:33]
reg w_rprobeacklast; // @[MSHR.scala:123:33]
reg s_release; // @[MSHR.scala:124:33]
reg w_releaseack; // @[MSHR.scala:125:33]
reg s_pprobe; // @[MSHR.scala:126:33]
reg s_acquire; // @[MSHR.scala:127:33]
reg s_flush; // @[MSHR.scala:128:33]
reg w_grantfirst; // @[MSHR.scala:129:33]
reg w_grantlast; // @[MSHR.scala:130:33]
reg w_grant; // @[MSHR.scala:131:33]
reg w_pprobeackfirst; // @[MSHR.scala:132:33]
reg w_pprobeacklast; // @[MSHR.scala:133:33]
reg w_pprobeack; // @[MSHR.scala:134:33]
reg s_grantack; // @[MSHR.scala:136:33]
reg s_execute; // @[MSHR.scala:137:33]
reg w_grantack; // @[MSHR.scala:138:33]
reg s_writeback; // @[MSHR.scala:139:33]
reg [2:0] sink; // @[MSHR.scala:147:17]
assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17]
reg gotT; // @[MSHR.scala:148:17]
reg bad_grant; // @[MSHR.scala:149:22]
assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22]
reg probes_done; // @[MSHR.scala:150:24]
reg probes_toN; // @[MSHR.scala:151:23]
reg probes_noT; // @[MSHR.scala:152:23]
wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28]
wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45]
wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62]
wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}]
wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82]
wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}]
wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103]
wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}]
assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}]
assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40]
wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39]
wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}]
wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}]
wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96]
assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}]
assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93]
assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28]
assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28]
wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43]
wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64]
wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}]
wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85]
wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}]
assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}]
assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39]
wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33]
wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}]
wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}]
assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}]
assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83]
wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31]
wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}]
assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}]
assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55]
wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31]
wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44]
assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}]
assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41]
wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32]
wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}]
assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}]
assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64]
wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31]
wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}]
assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}]
assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57]
wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31]
assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}]
assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43]
wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31]
assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}]
assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40]
wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34]
wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}]
wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70]
wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}]
assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}]
assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66]
wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49]
wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}]
wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}]
wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49]
wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}]
assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}]
assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105]
wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71]
wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71]
wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71]
wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire [12:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71]
wire final_meta_writeback_hit; // @[MSHR.scala:215:38]
wire req_clientBit = request_source == 6'h20; // @[Parameters.scala:46:9]
wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12]
wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12]
wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _req_needT_T_2; // @[Parameters.scala:270:13]
assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13]
wire _excluded_client_T_6; // @[Parameters.scala:279:117]
assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117]
wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42]
wire _req_needT_T_3; // @[Parameters.scala:270:42]
assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42]
wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11]
assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11]
wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42]
wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _req_needT_T_6; // @[Parameters.scala:271:14]
assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14]
wire _req_acquire_T; // @[MSHR.scala:219:36]
assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14]
wire _excluded_client_T_1; // @[Parameters.scala:279:12]
assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12]
wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52]
wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89]
wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52]
wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}]
wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}]
wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81]
wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}]
wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}]
wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}]
wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65]
wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}]
wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55]
wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78]
wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78]
assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78]
wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70]
wire _evict_T_2; // @[MSHR.scala:317:26]
assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _before_T_1; // @[MSHR.scala:317:26]
assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}]
wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}]
wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43]
assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43]
wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75]
wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}]
wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:46:9]
wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}]
wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}]
wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54]
wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}]
wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45]
wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}]
wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}]
wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40]
wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40]
assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40]
wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65]
assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65]
wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41]
wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}]
wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72]
wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}]
wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70]
wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70]
wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53]
assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53]
wire _evict_T_1; // @[MSHR.scala:317:26]
assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire _before_T; // @[MSHR.scala:317:26]
assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70]
wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70]
wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55]
wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70]
wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70]
wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66]
wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}]
wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}]
wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:46:9]
wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40]
assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30]
wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54]
wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}]
assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21]
assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21]
assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36]
assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36]
wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:46:9]
wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}]
wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}]
wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}]
wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}]
wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}]
wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56]
wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70]
assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}]
wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51]
wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55]
wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52]
wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}]
wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}]
assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38]
assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91]
wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42]
wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70]
wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}]
assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}]
assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41]
wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42]
assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}]
assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41]
assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51]
assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41]
assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41]
assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}]
assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41]
wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42]
wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53]
wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53]
wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89]
wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79]
assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41]
wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42]
assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 13'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}]
assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41]
wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32]
wire [3:0] evict; // @[MSHR.scala:314:26]
wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32]
wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32]
wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32]
assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32]
assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39]
wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39]
assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39]
assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76]
wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76]
assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76]
assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32]
assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] before_0; // @[MSHR.scala:314:26]
wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32]
wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11]
assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] after; // @[MSHR.scala:314:26]
wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26]
wire _after_T; // @[MSHR.scala:317:26]
assign _after_T = _GEN_9; // @[MSHR.scala:317:26]
wire _prior_T; // @[MSHR.scala:317:26]
assign _prior_T = _GEN_9; // @[MSHR.scala:317:26]
wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32]
wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26]
wire _after_T_1; // @[MSHR.scala:317:26]
assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire _prior_T_1; // @[MSHR.scala:317:26]
assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32]
wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32]
assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32]
assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39]
wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39]
assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39]
assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76]
wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76]
assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76]
assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26]
wire _after_T_3; // @[MSHR.scala:317:26]
assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26]
wire _prior_T_3; // @[MSHR.scala:317:26]
assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26]
assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire probe_bit = io_sinkc_bits_source_0 == 6'h20; // @[Parameters.scala:46:9]
wire _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:46:9]
wire _last_probe_T; // @[MSHR.scala:459:33]
assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33]
wire _probes_done_T; // @[MSHR.scala:467:32]
assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32]
wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}]
wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11]
wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43]
wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75]
wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}]
wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:46:9]
wire _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}]
wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53]
wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}]
wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42]
wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55]
wire _w_rprobeacklast_T; // @[MSHR.scala:471:55]
assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55]
wire _w_pprobeacklast_T; // @[MSHR.scala:473:55]
assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55]
wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}]
wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42]
wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}]
wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77]
wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}]
wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}]
wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32]
wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33]
wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}]
wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35]
wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40]
wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [12:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [12:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12]
wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _new_needT_T_2; // @[Parameters.scala:270:13]
assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13]
wire _new_skipProbe_T_5; // @[Parameters.scala:279:117]
assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117]
wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42]
wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _new_needT_T_6; // @[Parameters.scala:271:14]
assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14]
wire _new_skipProbe_T; // @[Parameters.scala:279:12]
assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12]
wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52]
wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89]
wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire new_clientBit = new_request_source == 6'h20; // @[Parameters.scala:46:9]
wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}]
wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}]
wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}]
wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:46:9]
wire [3:0] prior; // @[MSHR.scala:314:26]
wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32]
wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire _T_574 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28] |
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_preMul_e8_s24_4 :
output io : { flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, mulAddA : UInt<24>, mulAddB : UInt<24>, mulAddC : UInt<48>, toPostMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}}
node rawA_exp = bits(io.a, 31, 23)
node _rawA_isZero_T = bits(rawA_exp, 8, 6)
node rawA_isZero = eq(_rawA_isZero_T, UInt<1>(0h0))
node _rawA_isSpecial_T = bits(rawA_exp, 8, 7)
node rawA_isSpecial = eq(_rawA_isSpecial_T, UInt<2>(0h3))
wire rawA : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawA_out_isNaN_T = bits(rawA_exp, 6, 6)
node _rawA_out_isNaN_T_1 = and(rawA_isSpecial, _rawA_out_isNaN_T)
connect rawA.isNaN, _rawA_out_isNaN_T_1
node _rawA_out_isInf_T = bits(rawA_exp, 6, 6)
node _rawA_out_isInf_T_1 = eq(_rawA_out_isInf_T, UInt<1>(0h0))
node _rawA_out_isInf_T_2 = and(rawA_isSpecial, _rawA_out_isInf_T_1)
connect rawA.isInf, _rawA_out_isInf_T_2
connect rawA.isZero, rawA_isZero
node _rawA_out_sign_T = bits(io.a, 32, 32)
connect rawA.sign, _rawA_out_sign_T
node _rawA_out_sExp_T = cvt(rawA_exp)
connect rawA.sExp, _rawA_out_sExp_T
node _rawA_out_sig_T = eq(rawA_isZero, UInt<1>(0h0))
node _rawA_out_sig_T_1 = cat(UInt<1>(0h0), _rawA_out_sig_T)
node _rawA_out_sig_T_2 = bits(io.a, 22, 0)
node _rawA_out_sig_T_3 = cat(_rawA_out_sig_T_1, _rawA_out_sig_T_2)
connect rawA.sig, _rawA_out_sig_T_3
node rawB_exp = bits(io.b, 31, 23)
node _rawB_isZero_T = bits(rawB_exp, 8, 6)
node rawB_isZero = eq(_rawB_isZero_T, UInt<1>(0h0))
node _rawB_isSpecial_T = bits(rawB_exp, 8, 7)
node rawB_isSpecial = eq(_rawB_isSpecial_T, UInt<2>(0h3))
wire rawB : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawB_out_isNaN_T = bits(rawB_exp, 6, 6)
node _rawB_out_isNaN_T_1 = and(rawB_isSpecial, _rawB_out_isNaN_T)
connect rawB.isNaN, _rawB_out_isNaN_T_1
node _rawB_out_isInf_T = bits(rawB_exp, 6, 6)
node _rawB_out_isInf_T_1 = eq(_rawB_out_isInf_T, UInt<1>(0h0))
node _rawB_out_isInf_T_2 = and(rawB_isSpecial, _rawB_out_isInf_T_1)
connect rawB.isInf, _rawB_out_isInf_T_2
connect rawB.isZero, rawB_isZero
node _rawB_out_sign_T = bits(io.b, 32, 32)
connect rawB.sign, _rawB_out_sign_T
node _rawB_out_sExp_T = cvt(rawB_exp)
connect rawB.sExp, _rawB_out_sExp_T
node _rawB_out_sig_T = eq(rawB_isZero, UInt<1>(0h0))
node _rawB_out_sig_T_1 = cat(UInt<1>(0h0), _rawB_out_sig_T)
node _rawB_out_sig_T_2 = bits(io.b, 22, 0)
node _rawB_out_sig_T_3 = cat(_rawB_out_sig_T_1, _rawB_out_sig_T_2)
connect rawB.sig, _rawB_out_sig_T_3
node rawC_exp = bits(io.c, 31, 23)
node _rawC_isZero_T = bits(rawC_exp, 8, 6)
node rawC_isZero = eq(_rawC_isZero_T, UInt<1>(0h0))
node _rawC_isSpecial_T = bits(rawC_exp, 8, 7)
node rawC_isSpecial = eq(_rawC_isSpecial_T, UInt<2>(0h3))
wire rawC : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawC_out_isNaN_T = bits(rawC_exp, 6, 6)
node _rawC_out_isNaN_T_1 = and(rawC_isSpecial, _rawC_out_isNaN_T)
connect rawC.isNaN, _rawC_out_isNaN_T_1
node _rawC_out_isInf_T = bits(rawC_exp, 6, 6)
node _rawC_out_isInf_T_1 = eq(_rawC_out_isInf_T, UInt<1>(0h0))
node _rawC_out_isInf_T_2 = and(rawC_isSpecial, _rawC_out_isInf_T_1)
connect rawC.isInf, _rawC_out_isInf_T_2
connect rawC.isZero, rawC_isZero
node _rawC_out_sign_T = bits(io.c, 32, 32)
connect rawC.sign, _rawC_out_sign_T
node _rawC_out_sExp_T = cvt(rawC_exp)
connect rawC.sExp, _rawC_out_sExp_T
node _rawC_out_sig_T = eq(rawC_isZero, UInt<1>(0h0))
node _rawC_out_sig_T_1 = cat(UInt<1>(0h0), _rawC_out_sig_T)
node _rawC_out_sig_T_2 = bits(io.c, 22, 0)
node _rawC_out_sig_T_3 = cat(_rawC_out_sig_T_1, _rawC_out_sig_T_2)
connect rawC.sig, _rawC_out_sig_T_3
node _signProd_T = xor(rawA.sign, rawB.sign)
node _signProd_T_1 = bits(io.op, 1, 1)
node signProd = xor(_signProd_T, _signProd_T_1)
node _sExpAlignedProd_T = add(rawA.sExp, rawB.sExp)
node _sExpAlignedProd_T_1 = add(_sExpAlignedProd_T, asSInt(UInt<9>(0h11b)))
node _sExpAlignedProd_T_2 = tail(_sExpAlignedProd_T_1, 1)
node sExpAlignedProd = asSInt(_sExpAlignedProd_T_2)
node _doSubMags_T = xor(signProd, rawC.sign)
node _doSubMags_T_1 = bits(io.op, 0, 0)
node doSubMags = xor(_doSubMags_T, _doSubMags_T_1)
node _sNatCAlignDist_T = sub(sExpAlignedProd, rawC.sExp)
node _sNatCAlignDist_T_1 = tail(_sNatCAlignDist_T, 1)
node sNatCAlignDist = asSInt(_sNatCAlignDist_T_1)
node posNatCAlignDist = bits(sNatCAlignDist, 9, 0)
node _isMinCAlign_T = or(rawA.isZero, rawB.isZero)
node _isMinCAlign_T_1 = lt(sNatCAlignDist, asSInt(UInt<1>(0h0)))
node isMinCAlign = or(_isMinCAlign_T, _isMinCAlign_T_1)
node _CIsDominant_T = eq(rawC.isZero, UInt<1>(0h0))
node _CIsDominant_T_1 = leq(posNatCAlignDist, UInt<5>(0h18))
node _CIsDominant_T_2 = or(isMinCAlign, _CIsDominant_T_1)
node CIsDominant = and(_CIsDominant_T, _CIsDominant_T_2)
node _CAlignDist_T = lt(posNatCAlignDist, UInt<7>(0h4a))
node _CAlignDist_T_1 = bits(posNatCAlignDist, 6, 0)
node _CAlignDist_T_2 = mux(_CAlignDist_T, _CAlignDist_T_1, UInt<7>(0h4a))
node CAlignDist = mux(isMinCAlign, UInt<1>(0h0), _CAlignDist_T_2)
node _mainAlignedSigC_T = not(rawC.sig)
node _mainAlignedSigC_T_1 = mux(doSubMags, _mainAlignedSigC_T, rawC.sig)
node _mainAlignedSigC_T_2 = mux(doSubMags, UInt<53>(0h1fffffffffffff), UInt<53>(0h0))
node _mainAlignedSigC_T_3 = cat(_mainAlignedSigC_T_1, _mainAlignedSigC_T_2)
node _mainAlignedSigC_T_4 = asSInt(_mainAlignedSigC_T_3)
node mainAlignedSigC = dshr(_mainAlignedSigC_T_4, CAlignDist)
node _reduced4CExtra_T = shl(rawC.sig, 2)
wire reduced4CExtra_reducedVec : UInt<1>[7]
node _reduced4CExtra_reducedVec_0_T = bits(_reduced4CExtra_T, 3, 0)
node _reduced4CExtra_reducedVec_0_T_1 = orr(_reduced4CExtra_reducedVec_0_T)
connect reduced4CExtra_reducedVec[0], _reduced4CExtra_reducedVec_0_T_1
node _reduced4CExtra_reducedVec_1_T = bits(_reduced4CExtra_T, 7, 4)
node _reduced4CExtra_reducedVec_1_T_1 = orr(_reduced4CExtra_reducedVec_1_T)
connect reduced4CExtra_reducedVec[1], _reduced4CExtra_reducedVec_1_T_1
node _reduced4CExtra_reducedVec_2_T = bits(_reduced4CExtra_T, 11, 8)
node _reduced4CExtra_reducedVec_2_T_1 = orr(_reduced4CExtra_reducedVec_2_T)
connect reduced4CExtra_reducedVec[2], _reduced4CExtra_reducedVec_2_T_1
node _reduced4CExtra_reducedVec_3_T = bits(_reduced4CExtra_T, 15, 12)
node _reduced4CExtra_reducedVec_3_T_1 = orr(_reduced4CExtra_reducedVec_3_T)
connect reduced4CExtra_reducedVec[3], _reduced4CExtra_reducedVec_3_T_1
node _reduced4CExtra_reducedVec_4_T = bits(_reduced4CExtra_T, 19, 16)
node _reduced4CExtra_reducedVec_4_T_1 = orr(_reduced4CExtra_reducedVec_4_T)
connect reduced4CExtra_reducedVec[4], _reduced4CExtra_reducedVec_4_T_1
node _reduced4CExtra_reducedVec_5_T = bits(_reduced4CExtra_T, 23, 20)
node _reduced4CExtra_reducedVec_5_T_1 = orr(_reduced4CExtra_reducedVec_5_T)
connect reduced4CExtra_reducedVec[5], _reduced4CExtra_reducedVec_5_T_1
node _reduced4CExtra_reducedVec_6_T = bits(_reduced4CExtra_T, 26, 24)
node _reduced4CExtra_reducedVec_6_T_1 = orr(_reduced4CExtra_reducedVec_6_T)
connect reduced4CExtra_reducedVec[6], _reduced4CExtra_reducedVec_6_T_1
node reduced4CExtra_lo_hi = cat(reduced4CExtra_reducedVec[2], reduced4CExtra_reducedVec[1])
node reduced4CExtra_lo = cat(reduced4CExtra_lo_hi, reduced4CExtra_reducedVec[0])
node reduced4CExtra_hi_lo = cat(reduced4CExtra_reducedVec[4], reduced4CExtra_reducedVec[3])
node reduced4CExtra_hi_hi = cat(reduced4CExtra_reducedVec[6], reduced4CExtra_reducedVec[5])
node reduced4CExtra_hi = cat(reduced4CExtra_hi_hi, reduced4CExtra_hi_lo)
node _reduced4CExtra_T_1 = cat(reduced4CExtra_hi, reduced4CExtra_lo)
node _reduced4CExtra_T_2 = shr(CAlignDist, 2)
node reduced4CExtra_shift = dshr(asSInt(UInt<33>(0h100000000)), _reduced4CExtra_T_2)
node _reduced4CExtra_T_3 = bits(reduced4CExtra_shift, 19, 14)
node _reduced4CExtra_T_4 = bits(_reduced4CExtra_T_3, 3, 0)
node _reduced4CExtra_T_5 = bits(_reduced4CExtra_T_4, 1, 0)
node _reduced4CExtra_T_6 = bits(_reduced4CExtra_T_5, 0, 0)
node _reduced4CExtra_T_7 = bits(_reduced4CExtra_T_5, 1, 1)
node _reduced4CExtra_T_8 = cat(_reduced4CExtra_T_6, _reduced4CExtra_T_7)
node _reduced4CExtra_T_9 = bits(_reduced4CExtra_T_4, 3, 2)
node _reduced4CExtra_T_10 = bits(_reduced4CExtra_T_9, 0, 0)
node _reduced4CExtra_T_11 = bits(_reduced4CExtra_T_9, 1, 1)
node _reduced4CExtra_T_12 = cat(_reduced4CExtra_T_10, _reduced4CExtra_T_11)
node _reduced4CExtra_T_13 = cat(_reduced4CExtra_T_8, _reduced4CExtra_T_12)
node _reduced4CExtra_T_14 = bits(_reduced4CExtra_T_3, 5, 4)
node _reduced4CExtra_T_15 = bits(_reduced4CExtra_T_14, 0, 0)
node _reduced4CExtra_T_16 = bits(_reduced4CExtra_T_14, 1, 1)
node _reduced4CExtra_T_17 = cat(_reduced4CExtra_T_15, _reduced4CExtra_T_16)
node _reduced4CExtra_T_18 = cat(_reduced4CExtra_T_13, _reduced4CExtra_T_17)
node _reduced4CExtra_T_19 = and(_reduced4CExtra_T_1, _reduced4CExtra_T_18)
node reduced4CExtra = orr(_reduced4CExtra_T_19)
node _alignedSigC_T = shr(mainAlignedSigC, 3)
node _alignedSigC_T_1 = bits(mainAlignedSigC, 2, 0)
node _alignedSigC_T_2 = andr(_alignedSigC_T_1)
node _alignedSigC_T_3 = eq(reduced4CExtra, UInt<1>(0h0))
node _alignedSigC_T_4 = and(_alignedSigC_T_2, _alignedSigC_T_3)
node _alignedSigC_T_5 = bits(mainAlignedSigC, 2, 0)
node _alignedSigC_T_6 = orr(_alignedSigC_T_5)
node _alignedSigC_T_7 = or(_alignedSigC_T_6, reduced4CExtra)
node _alignedSigC_T_8 = mux(doSubMags, _alignedSigC_T_4, _alignedSigC_T_7)
node alignedSigC_hi = asUInt(_alignedSigC_T)
node alignedSigC = cat(alignedSigC_hi, _alignedSigC_T_8)
connect io.mulAddA, rawA.sig
connect io.mulAddB, rawB.sig
node _io_mulAddC_T = bits(alignedSigC, 48, 1)
connect io.mulAddC, _io_mulAddC_T
node _io_toPostMul_isSigNaNAny_T = bits(rawA.sig, 22, 22)
node _io_toPostMul_isSigNaNAny_T_1 = eq(_io_toPostMul_isSigNaNAny_T, UInt<1>(0h0))
node _io_toPostMul_isSigNaNAny_T_2 = and(rawA.isNaN, _io_toPostMul_isSigNaNAny_T_1)
node _io_toPostMul_isSigNaNAny_T_3 = bits(rawB.sig, 22, 22)
node _io_toPostMul_isSigNaNAny_T_4 = eq(_io_toPostMul_isSigNaNAny_T_3, UInt<1>(0h0))
node _io_toPostMul_isSigNaNAny_T_5 = and(rawB.isNaN, _io_toPostMul_isSigNaNAny_T_4)
node _io_toPostMul_isSigNaNAny_T_6 = or(_io_toPostMul_isSigNaNAny_T_2, _io_toPostMul_isSigNaNAny_T_5)
node _io_toPostMul_isSigNaNAny_T_7 = bits(rawC.sig, 22, 22)
node _io_toPostMul_isSigNaNAny_T_8 = eq(_io_toPostMul_isSigNaNAny_T_7, UInt<1>(0h0))
node _io_toPostMul_isSigNaNAny_T_9 = and(rawC.isNaN, _io_toPostMul_isSigNaNAny_T_8)
node _io_toPostMul_isSigNaNAny_T_10 = or(_io_toPostMul_isSigNaNAny_T_6, _io_toPostMul_isSigNaNAny_T_9)
connect io.toPostMul.isSigNaNAny, _io_toPostMul_isSigNaNAny_T_10
node _io_toPostMul_isNaNAOrB_T = or(rawA.isNaN, rawB.isNaN)
connect io.toPostMul.isNaNAOrB, _io_toPostMul_isNaNAOrB_T
connect io.toPostMul.isInfA, rawA.isInf
connect io.toPostMul.isZeroA, rawA.isZero
connect io.toPostMul.isInfB, rawB.isInf
connect io.toPostMul.isZeroB, rawB.isZero
connect io.toPostMul.signProd, signProd
connect io.toPostMul.isNaNC, rawC.isNaN
connect io.toPostMul.isInfC, rawC.isInf
connect io.toPostMul.isZeroC, rawC.isZero
node _io_toPostMul_sExpSum_T = sub(sExpAlignedProd, asSInt(UInt<6>(0h18)))
node _io_toPostMul_sExpSum_T_1 = tail(_io_toPostMul_sExpSum_T, 1)
node _io_toPostMul_sExpSum_T_2 = asSInt(_io_toPostMul_sExpSum_T_1)
node _io_toPostMul_sExpSum_T_3 = mux(CIsDominant, rawC.sExp, _io_toPostMul_sExpSum_T_2)
connect io.toPostMul.sExpSum, _io_toPostMul_sExpSum_T_3
connect io.toPostMul.doSubMags, doSubMags
connect io.toPostMul.CIsDominant, CIsDominant
node _io_toPostMul_CDom_CAlignDist_T = bits(CAlignDist, 4, 0)
connect io.toPostMul.CDom_CAlignDist, _io_toPostMul_CDom_CAlignDist_T
node _io_toPostMul_highAlignedSigC_T = bits(alignedSigC, 74, 49)
connect io.toPostMul.highAlignedSigC, _io_toPostMul_highAlignedSigC_T
node _io_toPostMul_bit0AlignedSigC_T = bits(alignedSigC, 0, 0)
connect io.toPostMul.bit0AlignedSigC, _io_toPostMul_bit0AlignedSigC_T | module MulAddRecFNToRaw_preMul_e8_s24_4( // @[MulAddRecFN.scala:71:7]
input [32:0] io_a, // @[MulAddRecFN.scala:74:16]
input [32:0] io_b, // @[MulAddRecFN.scala:74:16]
output [23:0] io_mulAddA, // @[MulAddRecFN.scala:74:16]
output [23:0] io_mulAddB, // @[MulAddRecFN.scala:74:16]
output [47:0] io_mulAddC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isSigNaNAny, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isNaNAOrB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfA, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroA, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_signProd, // @[MulAddRecFN.scala:74:16]
output [9:0] io_toPostMul_sExpSum, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_doSubMags, // @[MulAddRecFN.scala:74:16]
output [4:0] io_toPostMul_CDom_CAlignDist, // @[MulAddRecFN.scala:74:16]
output [25:0] io_toPostMul_highAlignedSigC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_bit0AlignedSigC // @[MulAddRecFN.scala:74:16]
);
wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:71:7]
wire [32:0] io_b_0 = io_b; // @[MulAddRecFN.scala:71:7]
wire [8:0] rawC_exp = 9'h0; // @[rawFloatFromRecFN.scala:51:21]
wire [9:0] rawC_sExp = 10'h0; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire [9:0] _rawC_out_sExp_T = 10'h0; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire [22:0] _rawC_out_sig_T_2 = 23'h0; // @[rawFloatFromRecFN.scala:61:49]
wire [24:0] rawC_sig = 25'h0; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [24:0] _rawC_out_sig_T_3 = 25'h0; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [24:0] _mainAlignedSigC_T = 25'h1FFFFFF; // @[MulAddRecFN.scala:120:25]
wire [26:0] _reduced4CExtra_T = 27'h0; // @[MulAddRecFN.scala:122:30]
wire [2:0] _rawC_isZero_T = 3'h0; // @[rawFloatFromRecFN.scala:52:28]
wire [2:0] _reduced4CExtra_reducedVec_6_T = 3'h0; // @[rawFloatFromRecFN.scala:52:28]
wire [2:0] reduced4CExtra_lo = 3'h0; // @[rawFloatFromRecFN.scala:52:28]
wire [3:0] _reduced4CExtra_reducedVec_0_T = 4'h0; // @[primitives.scala:120:33, :124:20]
wire [3:0] _reduced4CExtra_reducedVec_1_T = 4'h0; // @[primitives.scala:120:33, :124:20]
wire [3:0] _reduced4CExtra_reducedVec_2_T = 4'h0; // @[primitives.scala:120:33, :124:20]
wire [3:0] _reduced4CExtra_reducedVec_3_T = 4'h0; // @[primitives.scala:120:33, :124:20]
wire [3:0] _reduced4CExtra_reducedVec_4_T = 4'h0; // @[primitives.scala:120:33, :124:20]
wire [3:0] _reduced4CExtra_reducedVec_5_T = 4'h0; // @[primitives.scala:120:33, :124:20]
wire [3:0] reduced4CExtra_hi = 4'h0; // @[primitives.scala:120:33, :124:20]
wire [6:0] _reduced4CExtra_T_1 = 7'h0; // @[primitives.scala:124:20]
wire [6:0] _reduced4CExtra_T_19 = 7'h0; // @[MulAddRecFN.scala:122:68]
wire io_toPostMul_isZeroC = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36]
wire rawC_isZero = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36]
wire rawC_isZero_0 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36]
wire _rawC_out_isInf_T_1 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36]
wire _alignedSigC_T_3 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36]
wire _io_toPostMul_isSigNaNAny_T_8 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36]
wire io_toPostMul_isNaNC = 1'h0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfC = 1'h0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_CIsDominant = 1'h0; // @[MulAddRecFN.scala:71:7]
wire rawC_isSpecial = 1'h0; // @[rawFloatFromRecFN.scala:53:53]
wire rawC_isNaN = 1'h0; // @[rawFloatFromRecFN.scala:55:23]
wire rawC_isInf = 1'h0; // @[rawFloatFromRecFN.scala:55:23]
wire rawC_sign = 1'h0; // @[rawFloatFromRecFN.scala:55:23]
wire _rawC_out_isNaN_T = 1'h0; // @[rawFloatFromRecFN.scala:56:41]
wire _rawC_out_isNaN_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:56:33]
wire _rawC_out_isInf_T = 1'h0; // @[rawFloatFromRecFN.scala:57:41]
wire _rawC_out_isInf_T_2 = 1'h0; // @[rawFloatFromRecFN.scala:57:33]
wire _rawC_out_sign_T = 1'h0; // @[rawFloatFromRecFN.scala:59:25]
wire _rawC_out_sig_T = 1'h0; // @[rawFloatFromRecFN.scala:61:35]
wire _signProd_T_1 = 1'h0; // @[MulAddRecFN.scala:97:49]
wire _doSubMags_T_1 = 1'h0; // @[MulAddRecFN.scala:102:49]
wire _CIsDominant_T = 1'h0; // @[MulAddRecFN.scala:110:9]
wire CIsDominant = 1'h0; // @[MulAddRecFN.scala:110:23]
wire reduced4CExtra_reducedVec_0 = 1'h0; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_1 = 1'h0; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_2 = 1'h0; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_3 = 1'h0; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_4 = 1'h0; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_5 = 1'h0; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_6 = 1'h0; // @[primitives.scala:118:30]
wire _reduced4CExtra_reducedVec_0_T_1 = 1'h0; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_1_T_1 = 1'h0; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_2_T_1 = 1'h0; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_3_T_1 = 1'h0; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_4_T_1 = 1'h0; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_5_T_1 = 1'h0; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_6_T_1 = 1'h0; // @[primitives.scala:123:57]
wire reduced4CExtra = 1'h0; // @[MulAddRecFN.scala:130:11]
wire _io_toPostMul_isSigNaNAny_T_7 = 1'h0; // @[common.scala:82:56]
wire _io_toPostMul_isSigNaNAny_T_9 = 1'h0; // @[common.scala:82:46]
wire [32:0] io_c = 33'h0; // @[MulAddRecFN.scala:71:7, :74:16]
wire [1:0] io_op = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32]
wire [1:0] _rawC_isSpecial_T = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32]
wire [1:0] _rawC_out_sig_T_1 = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32]
wire [1:0] reduced4CExtra_lo_hi = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32]
wire [1:0] reduced4CExtra_hi_lo = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32]
wire [1:0] reduced4CExtra_hi_hi = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32]
wire [47:0] _io_mulAddC_T; // @[MulAddRecFN.scala:143:30]
wire _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:146:58]
wire _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:148:42]
wire rawA_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawA_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire signProd; // @[MulAddRecFN.scala:97:42]
wire doSubMags; // @[MulAddRecFN.scala:102:42]
wire [4:0] _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:161:47]
wire [25:0] _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:163:20]
wire _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:164:48]
wire io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7]
wire [9:0] io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7]
wire [4:0] io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7]
wire [25:0] io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7]
wire [23:0] io_mulAddA_0; // @[MulAddRecFN.scala:71:7]
wire [23:0] io_mulAddB_0; // @[MulAddRecFN.scala:71:7]
wire [47:0] io_mulAddC_0; // @[MulAddRecFN.scala:71:7]
wire [8:0] rawA_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawA_isZero_T = rawA_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawA_isZero_0 = _rawA_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
assign rawA_isZero = rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawA_isSpecial_T = rawA_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawA_isSpecial = &_rawA_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
assign io_toPostMul_isInfA_0 = rawA_isInf; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isZeroA_0 = rawA_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawA_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawA_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawA_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawA_out_isNaN_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawA_out_isInf_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawA_out_isNaN_T_1 = rawA_isSpecial & _rawA_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawA_isNaN = _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawA_out_isInf_T_1 = ~_rawA_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawA_out_isInf_T_2 = rawA_isSpecial & _rawA_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawA_isInf = _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawA_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawA_sign = _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawA_out_sExp_T = {1'h0, rawA_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawA_sExp = _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawA_out_sig_T = ~rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawA_out_sig_T_1 = {1'h0, _rawA_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawA_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawA_out_sig_T_3 = {_rawA_out_sig_T_1, _rawA_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawA_sig = _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [8:0] rawB_exp = io_b_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawB_isZero_T = rawB_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawB_isZero_0 = _rawB_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
assign rawB_isZero = rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawB_isSpecial_T = rawB_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawB_isSpecial = &_rawB_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
assign io_toPostMul_isInfB_0 = rawB_isInf; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isZeroB_0 = rawB_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawB_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawB_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawB_out_isNaN_T = rawB_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawB_out_isInf_T = rawB_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawB_out_isNaN_T_1 = rawB_isSpecial & _rawB_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawB_isNaN = _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawB_out_isInf_T_1 = ~_rawB_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawB_out_isInf_T_2 = rawB_isSpecial & _rawB_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawB_isInf = _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawB_out_sign_T = io_b_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawB_sign = _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawB_out_sExp_T = {1'h0, rawB_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawB_sExp = _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawB_out_sig_T = ~rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawB_out_sig_T_1 = {1'h0, _rawB_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawB_out_sig_T_2 = io_b_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawB_out_sig_T_3 = {_rawB_out_sig_T_1, _rawB_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawB_sig = _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire _signProd_T = rawA_sign ^ rawB_sign; // @[rawFloatFromRecFN.scala:55:23]
assign signProd = _signProd_T; // @[MulAddRecFN.scala:97:{30,42}]
assign io_toPostMul_signProd_0 = signProd; // @[MulAddRecFN.scala:71:7, :97:42]
wire _doSubMags_T = signProd; // @[MulAddRecFN.scala:97:42, :102:30]
wire [10:0] _sExpAlignedProd_T = {rawA_sExp[9], rawA_sExp} + {rawB_sExp[9], rawB_sExp}; // @[rawFloatFromRecFN.scala:55:23]
wire [11:0] _sExpAlignedProd_T_1 = {_sExpAlignedProd_T[10], _sExpAlignedProd_T} - 12'hE5; // @[MulAddRecFN.scala:100:{19,32}]
wire [10:0] _sExpAlignedProd_T_2 = _sExpAlignedProd_T_1[10:0]; // @[MulAddRecFN.scala:100:32]
wire [10:0] sExpAlignedProd = _sExpAlignedProd_T_2; // @[MulAddRecFN.scala:100:32]
assign doSubMags = _doSubMags_T; // @[MulAddRecFN.scala:102:{30,42}]
assign io_toPostMul_doSubMags_0 = doSubMags; // @[MulAddRecFN.scala:71:7, :102:42]
wire [11:0] _sNatCAlignDist_T = {sExpAlignedProd[10], sExpAlignedProd}; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire [10:0] _sNatCAlignDist_T_1 = _sNatCAlignDist_T[10:0]; // @[MulAddRecFN.scala:106:42]
wire [10:0] sNatCAlignDist = _sNatCAlignDist_T_1; // @[MulAddRecFN.scala:106:42]
wire [9:0] posNatCAlignDist = sNatCAlignDist[9:0]; // @[MulAddRecFN.scala:106:42, :107:42]
wire _isMinCAlign_T = rawA_isZero | rawB_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _isMinCAlign_T_1 = $signed(sNatCAlignDist) < 11'sh0; // @[MulAddRecFN.scala:106:42, :108:69]
wire isMinCAlign = _isMinCAlign_T | _isMinCAlign_T_1; // @[MulAddRecFN.scala:108:{35,50,69}]
wire _CIsDominant_T_1 = posNatCAlignDist < 10'h19; // @[MulAddRecFN.scala:107:42, :110:60]
wire _CIsDominant_T_2 = isMinCAlign | _CIsDominant_T_1; // @[MulAddRecFN.scala:108:50, :110:{39,60}]
wire _CAlignDist_T = posNatCAlignDist < 10'h4A; // @[MulAddRecFN.scala:107:42, :114:34]
wire [6:0] _CAlignDist_T_1 = posNatCAlignDist[6:0]; // @[MulAddRecFN.scala:107:42, :115:33]
wire [6:0] _CAlignDist_T_2 = _CAlignDist_T ? _CAlignDist_T_1 : 7'h4A; // @[MulAddRecFN.scala:114:{16,34}, :115:33]
wire [6:0] CAlignDist = isMinCAlign ? 7'h0 : _CAlignDist_T_2; // @[MulAddRecFN.scala:108:50, :112:12, :114:16]
wire [24:0] _mainAlignedSigC_T_1 = {25{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:13]
wire [52:0] _mainAlignedSigC_T_2 = {53{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:53]
wire [77:0] _mainAlignedSigC_T_3 = {_mainAlignedSigC_T_1, _mainAlignedSigC_T_2}; // @[MulAddRecFN.scala:120:{13,46,53}]
wire [77:0] _mainAlignedSigC_T_4 = _mainAlignedSigC_T_3; // @[MulAddRecFN.scala:120:{46,94}]
wire [77:0] mainAlignedSigC = $signed($signed(_mainAlignedSigC_T_4) >>> CAlignDist); // @[MulAddRecFN.scala:112:12, :120:{94,100}]
wire [4:0] _reduced4CExtra_T_2 = CAlignDist[6:2]; // @[MulAddRecFN.scala:112:12, :124:28]
wire [32:0] reduced4CExtra_shift = $signed(33'sh100000000 >>> _reduced4CExtra_T_2); // @[primitives.scala:76:56]
wire [5:0] _reduced4CExtra_T_3 = reduced4CExtra_shift[19:14]; // @[primitives.scala:76:56, :78:22]
wire [3:0] _reduced4CExtra_T_4 = _reduced4CExtra_T_3[3:0]; // @[primitives.scala:77:20, :78:22]
wire [1:0] _reduced4CExtra_T_5 = _reduced4CExtra_T_4[1:0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_6 = _reduced4CExtra_T_5[0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_7 = _reduced4CExtra_T_5[1]; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_8 = {_reduced4CExtra_T_6, _reduced4CExtra_T_7}; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_9 = _reduced4CExtra_T_4[3:2]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_10 = _reduced4CExtra_T_9[0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_11 = _reduced4CExtra_T_9[1]; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_12 = {_reduced4CExtra_T_10, _reduced4CExtra_T_11}; // @[primitives.scala:77:20]
wire [3:0] _reduced4CExtra_T_13 = {_reduced4CExtra_T_8, _reduced4CExtra_T_12}; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_14 = _reduced4CExtra_T_3[5:4]; // @[primitives.scala:77:20, :78:22]
wire _reduced4CExtra_T_15 = _reduced4CExtra_T_14[0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_16 = _reduced4CExtra_T_14[1]; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_17 = {_reduced4CExtra_T_15, _reduced4CExtra_T_16}; // @[primitives.scala:77:20]
wire [5:0] _reduced4CExtra_T_18 = {_reduced4CExtra_T_13, _reduced4CExtra_T_17}; // @[primitives.scala:77:20]
wire [74:0] _alignedSigC_T = mainAlignedSigC[77:3]; // @[MulAddRecFN.scala:120:100, :132:28]
wire [74:0] alignedSigC_hi = _alignedSigC_T; // @[MulAddRecFN.scala:132:{12,28}]
wire [2:0] _alignedSigC_T_1 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32]
wire [2:0] _alignedSigC_T_5 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32, :135:32]
wire _alignedSigC_T_2 = &_alignedSigC_T_1; // @[MulAddRecFN.scala:134:{32,39}]
wire _alignedSigC_T_4 = _alignedSigC_T_2; // @[MulAddRecFN.scala:134:{39,44}]
wire _alignedSigC_T_6 = |_alignedSigC_T_5; // @[MulAddRecFN.scala:135:{32,39}]
wire _alignedSigC_T_7 = _alignedSigC_T_6; // @[MulAddRecFN.scala:135:{39,44}]
wire _alignedSigC_T_8 = doSubMags ? _alignedSigC_T_4 : _alignedSigC_T_7; // @[MulAddRecFN.scala:102:42, :133:16, :134:44, :135:44]
wire [75:0] alignedSigC = {alignedSigC_hi, _alignedSigC_T_8}; // @[MulAddRecFN.scala:132:12, :133:16]
assign io_mulAddA_0 = rawA_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23]
assign io_mulAddB_0 = rawB_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23]
assign _io_mulAddC_T = alignedSigC[48:1]; // @[MulAddRecFN.scala:132:12, :143:30]
assign io_mulAddC_0 = _io_mulAddC_T; // @[MulAddRecFN.scala:71:7, :143:30]
wire _io_toPostMul_isSigNaNAny_T = rawA_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_1 = ~_io_toPostMul_isSigNaNAny_T; // @[common.scala:82:{49,56}]
wire _io_toPostMul_isSigNaNAny_T_2 = rawA_isNaN & _io_toPostMul_isSigNaNAny_T_1; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_3 = rawB_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_4 = ~_io_toPostMul_isSigNaNAny_T_3; // @[common.scala:82:{49,56}]
wire _io_toPostMul_isSigNaNAny_T_5 = rawB_isNaN & _io_toPostMul_isSigNaNAny_T_4; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_6 = _io_toPostMul_isSigNaNAny_T_2 | _io_toPostMul_isSigNaNAny_T_5; // @[common.scala:82:46]
assign _io_toPostMul_isSigNaNAny_T_10 = _io_toPostMul_isSigNaNAny_T_6; // @[MulAddRecFN.scala:146:{32,58}]
assign io_toPostMul_isSigNaNAny_0 = _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:71:7, :146:58]
assign _io_toPostMul_isNaNAOrB_T = rawA_isNaN | rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isNaNAOrB_0 = _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:71:7, :148:42]
wire [11:0] _io_toPostMul_sExpSum_T = _sNatCAlignDist_T - 12'h18; // @[MulAddRecFN.scala:106:42, :158:53]
wire [10:0] _io_toPostMul_sExpSum_T_1 = _io_toPostMul_sExpSum_T[10:0]; // @[MulAddRecFN.scala:158:53]
wire [10:0] _io_toPostMul_sExpSum_T_2 = _io_toPostMul_sExpSum_T_1; // @[MulAddRecFN.scala:158:53]
wire [10:0] _io_toPostMul_sExpSum_T_3 = _io_toPostMul_sExpSum_T_2; // @[MulAddRecFN.scala:158:{12,53}]
assign io_toPostMul_sExpSum_0 = _io_toPostMul_sExpSum_T_3[9:0]; // @[MulAddRecFN.scala:71:7, :157:28, :158:12]
assign _io_toPostMul_CDom_CAlignDist_T = CAlignDist[4:0]; // @[MulAddRecFN.scala:112:12, :161:47]
assign io_toPostMul_CDom_CAlignDist_0 = _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:71:7, :161:47]
assign _io_toPostMul_highAlignedSigC_T = alignedSigC[74:49]; // @[MulAddRecFN.scala:132:12, :163:20]
assign io_toPostMul_highAlignedSigC_0 = _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:71:7, :163:20]
assign _io_toPostMul_bit0AlignedSigC_T = alignedSigC[0]; // @[MulAddRecFN.scala:132:12, :164:48]
assign io_toPostMul_bit0AlignedSigC_0 = _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:71:7, :164:48]
assign io_mulAddA = io_mulAddA_0; // @[MulAddRecFN.scala:71:7]
assign io_mulAddB = io_mulAddB_0; // @[MulAddRecFN.scala:71:7]
assign io_mulAddC = io_mulAddC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isSigNaNAny = io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isNaNAOrB = io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isInfA = io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isZeroA = io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isInfB = io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isZeroB = io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_signProd = io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_sExpSum = io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_doSubMags = io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_CDom_CAlignDist = io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_highAlignedSigC = io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_bit0AlignedSigC = io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module BoomTile :
input clock : Clock
input reset : Reset
output auto : { buffer_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}, wfi_out : UInt<1>[1], cease_out : UInt<1>[1], halt_out : UInt<1>[1], flip int_local_in_3 : UInt<1>[1], flip int_local_in_2 : UInt<1>[1], flip int_local_in_1 : UInt<1>[2], flip int_local_in_0 : UInt<1>[1], trace_core_source_out : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, tval : UInt<32>, cause : UInt<32>}, trace_source_out : { insns : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[3], time : UInt<64>, custom : { rob_empty : UInt<1>}}, flip reset_vector_in : UInt<32>, flip hartid_in : UInt<1>}
inst tlMasterXbar of TLXbar_MasterXbar_BoomTile_i2_o1_a32d128s4k4z4c
connect tlMasterXbar.clock, clock
connect tlMasterXbar.reset, reset
inst tlSlaveXbar of TLXbar_SlaveXbar_BoomTile_i0_o0_a1d8s1k1z1u
connect tlSlaveXbar.clock, clock
connect tlSlaveXbar.reset, reset
inst intXbar of IntXbar_i4_o1
inst broadcast of BundleBridgeNexus_UInt1
inst broadcast_1 of BundleBridgeNexus_UInt32
inst nexus of BundleBridgeNexus_NoOutput_6
inst nexus_1 of BundleBridgeNexus_TraceAux
inst broadcast_2 of BundleBridgeNexus_NoOutput_7
inst widget of TLWidthWidget16_2
connect widget.clock, clock
connect widget.reset, reset
inst dcache of BoomNonBlockingDCache
connect dcache.clock, clock
connect dcache.reset, reset
inst frontend of BoomFrontend
connect frontend.clock, clock
connect frontend.reset, reset
inst widget_1 of TLWidthWidget16_3
connect widget_1.clock, clock
connect widget_1.reset, reset
inst buffer of TLBuffer_a32d128s4k4z4c
connect buffer.clock, clock
connect buffer.reset, reset
inst buffer_1 of TLBuffer_1
connect buffer_1.clock, clock
connect buffer_1.reset, reset
wire tlOtherMastersNodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}
invalidate tlOtherMastersNodeOut.e.bits.sink
invalidate tlOtherMastersNodeOut.e.valid
invalidate tlOtherMastersNodeOut.e.ready
invalidate tlOtherMastersNodeOut.d.bits.corrupt
invalidate tlOtherMastersNodeOut.d.bits.data
invalidate tlOtherMastersNodeOut.d.bits.denied
invalidate tlOtherMastersNodeOut.d.bits.sink
invalidate tlOtherMastersNodeOut.d.bits.source
invalidate tlOtherMastersNodeOut.d.bits.size
invalidate tlOtherMastersNodeOut.d.bits.param
invalidate tlOtherMastersNodeOut.d.bits.opcode
invalidate tlOtherMastersNodeOut.d.valid
invalidate tlOtherMastersNodeOut.d.ready
invalidate tlOtherMastersNodeOut.c.bits.corrupt
invalidate tlOtherMastersNodeOut.c.bits.data
invalidate tlOtherMastersNodeOut.c.bits.address
invalidate tlOtherMastersNodeOut.c.bits.source
invalidate tlOtherMastersNodeOut.c.bits.size
invalidate tlOtherMastersNodeOut.c.bits.param
invalidate tlOtherMastersNodeOut.c.bits.opcode
invalidate tlOtherMastersNodeOut.c.valid
invalidate tlOtherMastersNodeOut.c.ready
invalidate tlOtherMastersNodeOut.b.bits.corrupt
invalidate tlOtherMastersNodeOut.b.bits.data
invalidate tlOtherMastersNodeOut.b.bits.mask
invalidate tlOtherMastersNodeOut.b.bits.address
invalidate tlOtherMastersNodeOut.b.bits.source
invalidate tlOtherMastersNodeOut.b.bits.size
invalidate tlOtherMastersNodeOut.b.bits.param
invalidate tlOtherMastersNodeOut.b.bits.opcode
invalidate tlOtherMastersNodeOut.b.valid
invalidate tlOtherMastersNodeOut.b.ready
invalidate tlOtherMastersNodeOut.a.bits.corrupt
invalidate tlOtherMastersNodeOut.a.bits.data
invalidate tlOtherMastersNodeOut.a.bits.mask
invalidate tlOtherMastersNodeOut.a.bits.address
invalidate tlOtherMastersNodeOut.a.bits.source
invalidate tlOtherMastersNodeOut.a.bits.size
invalidate tlOtherMastersNodeOut.a.bits.param
invalidate tlOtherMastersNodeOut.a.bits.opcode
invalidate tlOtherMastersNodeOut.a.valid
invalidate tlOtherMastersNodeOut.a.ready
wire tlOtherMastersNodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}
invalidate tlOtherMastersNodeIn.e.bits.sink
invalidate tlOtherMastersNodeIn.e.valid
invalidate tlOtherMastersNodeIn.e.ready
invalidate tlOtherMastersNodeIn.d.bits.corrupt
invalidate tlOtherMastersNodeIn.d.bits.data
invalidate tlOtherMastersNodeIn.d.bits.denied
invalidate tlOtherMastersNodeIn.d.bits.sink
invalidate tlOtherMastersNodeIn.d.bits.source
invalidate tlOtherMastersNodeIn.d.bits.size
invalidate tlOtherMastersNodeIn.d.bits.param
invalidate tlOtherMastersNodeIn.d.bits.opcode
invalidate tlOtherMastersNodeIn.d.valid
invalidate tlOtherMastersNodeIn.d.ready
invalidate tlOtherMastersNodeIn.c.bits.corrupt
invalidate tlOtherMastersNodeIn.c.bits.data
invalidate tlOtherMastersNodeIn.c.bits.address
invalidate tlOtherMastersNodeIn.c.bits.source
invalidate tlOtherMastersNodeIn.c.bits.size
invalidate tlOtherMastersNodeIn.c.bits.param
invalidate tlOtherMastersNodeIn.c.bits.opcode
invalidate tlOtherMastersNodeIn.c.valid
invalidate tlOtherMastersNodeIn.c.ready
invalidate tlOtherMastersNodeIn.b.bits.corrupt
invalidate tlOtherMastersNodeIn.b.bits.data
invalidate tlOtherMastersNodeIn.b.bits.mask
invalidate tlOtherMastersNodeIn.b.bits.address
invalidate tlOtherMastersNodeIn.b.bits.source
invalidate tlOtherMastersNodeIn.b.bits.size
invalidate tlOtherMastersNodeIn.b.bits.param
invalidate tlOtherMastersNodeIn.b.bits.opcode
invalidate tlOtherMastersNodeIn.b.valid
invalidate tlOtherMastersNodeIn.b.ready
invalidate tlOtherMastersNodeIn.a.bits.corrupt
invalidate tlOtherMastersNodeIn.a.bits.data
invalidate tlOtherMastersNodeIn.a.bits.mask
invalidate tlOtherMastersNodeIn.a.bits.address
invalidate tlOtherMastersNodeIn.a.bits.source
invalidate tlOtherMastersNodeIn.a.bits.size
invalidate tlOtherMastersNodeIn.a.bits.param
invalidate tlOtherMastersNodeIn.a.bits.opcode
invalidate tlOtherMastersNodeIn.a.valid
invalidate tlOtherMastersNodeIn.a.ready
connect tlOtherMastersNodeOut, tlOtherMastersNodeIn
wire hartIdSinkNodeIn : UInt<1>
invalidate hartIdSinkNodeIn
wire hartidOut : UInt<1>
invalidate hartidOut
wire hartidIn : UInt<1>
invalidate hartidIn
connect hartidOut, hartidIn
wire resetVectorSinkNodeIn : UInt<32>
invalidate resetVectorSinkNodeIn
wire reset_vectorOut : UInt<32>
invalidate reset_vectorOut
wire reset_vectorIn : UInt<32>
invalidate reset_vectorIn
connect reset_vectorOut, reset_vectorIn
wire traceSourceNodeOut : { insns : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[3], time : UInt<64>, custom : { rob_empty : UInt<1>}}
invalidate traceSourceNodeOut.custom.rob_empty
invalidate traceSourceNodeOut.time
invalidate traceSourceNodeOut.insns[0].tval
invalidate traceSourceNodeOut.insns[0].cause
invalidate traceSourceNodeOut.insns[0].interrupt
invalidate traceSourceNodeOut.insns[0].exception
invalidate traceSourceNodeOut.insns[0].priv
invalidate traceSourceNodeOut.insns[0].insn
invalidate traceSourceNodeOut.insns[0].iaddr
invalidate traceSourceNodeOut.insns[0].valid
invalidate traceSourceNodeOut.insns[1].tval
invalidate traceSourceNodeOut.insns[1].cause
invalidate traceSourceNodeOut.insns[1].interrupt
invalidate traceSourceNodeOut.insns[1].exception
invalidate traceSourceNodeOut.insns[1].priv
invalidate traceSourceNodeOut.insns[1].insn
invalidate traceSourceNodeOut.insns[1].iaddr
invalidate traceSourceNodeOut.insns[1].valid
invalidate traceSourceNodeOut.insns[2].tval
invalidate traceSourceNodeOut.insns[2].cause
invalidate traceSourceNodeOut.insns[2].interrupt
invalidate traceSourceNodeOut.insns[2].exception
invalidate traceSourceNodeOut.insns[2].priv
invalidate traceSourceNodeOut.insns[2].insn
invalidate traceSourceNodeOut.insns[2].iaddr
invalidate traceSourceNodeOut.insns[2].valid
wire traceCoreSourceNodeOut : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, tval : UInt<32>, cause : UInt<32>}
invalidate traceCoreSourceNodeOut.cause
invalidate traceCoreSourceNodeOut.tval
invalidate traceCoreSourceNodeOut.priv
invalidate traceCoreSourceNodeOut.group[0].ilastsize
invalidate traceCoreSourceNodeOut.group[0].itype
invalidate traceCoreSourceNodeOut.group[0].iaddr
invalidate traceCoreSourceNodeOut.group[0].iretire
wire bundleIn_x_sourceOpt : { enable : UInt<1>, stall : UInt<1>}
connect bundleIn_x_sourceOpt.stall, UInt<1>(0h0)
connect bundleIn_x_sourceOpt.enable, UInt<1>(0h0)
wire traceAuxSinkNodeIn : { enable : UInt<1>, stall : UInt<1>}
invalidate traceAuxSinkNodeIn.stall
invalidate traceAuxSinkNodeIn.enable
wire bpwatchSourceNodeOut : { valid : UInt<1>[3], rvalid : UInt<1>[3], wvalid : UInt<1>[3], ivalid : UInt<1>[3], action : UInt<3>}[0]
wire int_localOut : UInt<1>[1]
invalidate int_localOut[0]
wire x1_int_localOut : UInt<1>[2]
invalidate x1_int_localOut[0]
invalidate x1_int_localOut[1]
wire x1_int_localOut_1 : UInt<1>[1]
invalidate x1_int_localOut_1[0]
wire x1_int_localOut_2 : UInt<1>[1]
invalidate x1_int_localOut_2[0]
wire int_localIn : UInt<1>[1]
invalidate int_localIn[0]
wire x1_int_localIn : UInt<1>[2]
invalidate x1_int_localIn[0]
invalidate x1_int_localIn[1]
wire x1_int_localIn_1 : UInt<1>[1]
invalidate x1_int_localIn_1[0]
wire x1_int_localIn_2 : UInt<1>[1]
invalidate x1_int_localIn_2[0]
connect int_localOut, int_localIn
connect x1_int_localOut, x1_int_localIn
connect x1_int_localOut_1, x1_int_localIn_1
connect x1_int_localOut_2, x1_int_localIn_2
wire intSinkNodeIn : UInt<1>[5]
invalidate intSinkNodeIn[0]
invalidate intSinkNodeIn[1]
invalidate intSinkNodeIn[2]
invalidate intSinkNodeIn[3]
invalidate intSinkNodeIn[4]
wire haltNodeOut : UInt<1>[1]
invalidate haltNodeOut[0]
wire ceaseNodeOut : UInt<1>[1]
invalidate ceaseNodeOut[0]
wire wfiNodeOut : UInt<1>[1]
invalidate wfiNodeOut[0]
wire masterNodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}
invalidate masterNodeOut.e.bits.sink
invalidate masterNodeOut.e.valid
invalidate masterNodeOut.e.ready
invalidate masterNodeOut.d.bits.corrupt
invalidate masterNodeOut.d.bits.data
invalidate masterNodeOut.d.bits.denied
invalidate masterNodeOut.d.bits.sink
invalidate masterNodeOut.d.bits.source
invalidate masterNodeOut.d.bits.size
invalidate masterNodeOut.d.bits.param
invalidate masterNodeOut.d.bits.opcode
invalidate masterNodeOut.d.valid
invalidate masterNodeOut.d.ready
invalidate masterNodeOut.c.bits.corrupt
invalidate masterNodeOut.c.bits.data
invalidate masterNodeOut.c.bits.address
invalidate masterNodeOut.c.bits.source
invalidate masterNodeOut.c.bits.size
invalidate masterNodeOut.c.bits.param
invalidate masterNodeOut.c.bits.opcode
invalidate masterNodeOut.c.valid
invalidate masterNodeOut.c.ready
invalidate masterNodeOut.b.bits.corrupt
invalidate masterNodeOut.b.bits.data
invalidate masterNodeOut.b.bits.mask
invalidate masterNodeOut.b.bits.address
invalidate masterNodeOut.b.bits.source
invalidate masterNodeOut.b.bits.size
invalidate masterNodeOut.b.bits.param
invalidate masterNodeOut.b.bits.opcode
invalidate masterNodeOut.b.valid
invalidate masterNodeOut.b.ready
invalidate masterNodeOut.a.bits.corrupt
invalidate masterNodeOut.a.bits.data
invalidate masterNodeOut.a.bits.mask
invalidate masterNodeOut.a.bits.address
invalidate masterNodeOut.a.bits.source
invalidate masterNodeOut.a.bits.size
invalidate masterNodeOut.a.bits.param
invalidate masterNodeOut.a.bits.opcode
invalidate masterNodeOut.a.valid
invalidate masterNodeOut.a.ready
wire masterNodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}
invalidate masterNodeIn.e.bits.sink
invalidate masterNodeIn.e.valid
invalidate masterNodeIn.e.ready
invalidate masterNodeIn.d.bits.corrupt
invalidate masterNodeIn.d.bits.data
invalidate masterNodeIn.d.bits.denied
invalidate masterNodeIn.d.bits.sink
invalidate masterNodeIn.d.bits.source
invalidate masterNodeIn.d.bits.size
invalidate masterNodeIn.d.bits.param
invalidate masterNodeIn.d.bits.opcode
invalidate masterNodeIn.d.valid
invalidate masterNodeIn.d.ready
invalidate masterNodeIn.c.bits.corrupt
invalidate masterNodeIn.c.bits.data
invalidate masterNodeIn.c.bits.address
invalidate masterNodeIn.c.bits.source
invalidate masterNodeIn.c.bits.size
invalidate masterNodeIn.c.bits.param
invalidate masterNodeIn.c.bits.opcode
invalidate masterNodeIn.c.valid
invalidate masterNodeIn.c.ready
invalidate masterNodeIn.b.bits.corrupt
invalidate masterNodeIn.b.bits.data
invalidate masterNodeIn.b.bits.mask
invalidate masterNodeIn.b.bits.address
invalidate masterNodeIn.b.bits.source
invalidate masterNodeIn.b.bits.size
invalidate masterNodeIn.b.bits.param
invalidate masterNodeIn.b.bits.opcode
invalidate masterNodeIn.b.valid
invalidate masterNodeIn.b.ready
invalidate masterNodeIn.a.bits.corrupt
invalidate masterNodeIn.a.bits.data
invalidate masterNodeIn.a.bits.mask
invalidate masterNodeIn.a.bits.address
invalidate masterNodeIn.a.bits.source
invalidate masterNodeIn.a.bits.size
invalidate masterNodeIn.a.bits.param
invalidate masterNodeIn.a.bits.opcode
invalidate masterNodeIn.a.valid
invalidate masterNodeIn.a.ready
connect masterNodeOut, masterNodeIn
wire dCacheTapOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}
invalidate dCacheTapOut.e.bits.sink
invalidate dCacheTapOut.e.valid
invalidate dCacheTapOut.e.ready
invalidate dCacheTapOut.d.bits.corrupt
invalidate dCacheTapOut.d.bits.data
invalidate dCacheTapOut.d.bits.denied
invalidate dCacheTapOut.d.bits.sink
invalidate dCacheTapOut.d.bits.source
invalidate dCacheTapOut.d.bits.size
invalidate dCacheTapOut.d.bits.param
invalidate dCacheTapOut.d.bits.opcode
invalidate dCacheTapOut.d.valid
invalidate dCacheTapOut.d.ready
invalidate dCacheTapOut.c.bits.corrupt
invalidate dCacheTapOut.c.bits.data
invalidate dCacheTapOut.c.bits.address
invalidate dCacheTapOut.c.bits.source
invalidate dCacheTapOut.c.bits.size
invalidate dCacheTapOut.c.bits.param
invalidate dCacheTapOut.c.bits.opcode
invalidate dCacheTapOut.c.valid
invalidate dCacheTapOut.c.ready
invalidate dCacheTapOut.b.bits.corrupt
invalidate dCacheTapOut.b.bits.data
invalidate dCacheTapOut.b.bits.mask
invalidate dCacheTapOut.b.bits.address
invalidate dCacheTapOut.b.bits.source
invalidate dCacheTapOut.b.bits.size
invalidate dCacheTapOut.b.bits.param
invalidate dCacheTapOut.b.bits.opcode
invalidate dCacheTapOut.b.valid
invalidate dCacheTapOut.b.ready
invalidate dCacheTapOut.a.bits.corrupt
invalidate dCacheTapOut.a.bits.data
invalidate dCacheTapOut.a.bits.mask
invalidate dCacheTapOut.a.bits.address
invalidate dCacheTapOut.a.bits.source
invalidate dCacheTapOut.a.bits.size
invalidate dCacheTapOut.a.bits.param
invalidate dCacheTapOut.a.bits.opcode
invalidate dCacheTapOut.a.valid
invalidate dCacheTapOut.a.ready
wire dCacheTapIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}
invalidate dCacheTapIn.e.bits.sink
invalidate dCacheTapIn.e.valid
invalidate dCacheTapIn.e.ready
invalidate dCacheTapIn.d.bits.corrupt
invalidate dCacheTapIn.d.bits.data
invalidate dCacheTapIn.d.bits.denied
invalidate dCacheTapIn.d.bits.sink
invalidate dCacheTapIn.d.bits.source
invalidate dCacheTapIn.d.bits.size
invalidate dCacheTapIn.d.bits.param
invalidate dCacheTapIn.d.bits.opcode
invalidate dCacheTapIn.d.valid
invalidate dCacheTapIn.d.ready
invalidate dCacheTapIn.c.bits.corrupt
invalidate dCacheTapIn.c.bits.data
invalidate dCacheTapIn.c.bits.address
invalidate dCacheTapIn.c.bits.source
invalidate dCacheTapIn.c.bits.size
invalidate dCacheTapIn.c.bits.param
invalidate dCacheTapIn.c.bits.opcode
invalidate dCacheTapIn.c.valid
invalidate dCacheTapIn.c.ready
invalidate dCacheTapIn.b.bits.corrupt
invalidate dCacheTapIn.b.bits.data
invalidate dCacheTapIn.b.bits.mask
invalidate dCacheTapIn.b.bits.address
invalidate dCacheTapIn.b.bits.source
invalidate dCacheTapIn.b.bits.size
invalidate dCacheTapIn.b.bits.param
invalidate dCacheTapIn.b.bits.opcode
invalidate dCacheTapIn.b.valid
invalidate dCacheTapIn.b.ready
invalidate dCacheTapIn.a.bits.corrupt
invalidate dCacheTapIn.a.bits.data
invalidate dCacheTapIn.a.bits.mask
invalidate dCacheTapIn.a.bits.address
invalidate dCacheTapIn.a.bits.source
invalidate dCacheTapIn.a.bits.size
invalidate dCacheTapIn.a.bits.param
invalidate dCacheTapIn.a.bits.opcode
invalidate dCacheTapIn.a.valid
invalidate dCacheTapIn.a.ready
connect dCacheTapOut, dCacheTapIn
connect masterNodeIn, tlOtherMastersNodeOut
connect tlOtherMastersNodeIn.e.bits, tlMasterXbar.auto.anon_out.e.bits
connect tlOtherMastersNodeIn.e.valid, tlMasterXbar.auto.anon_out.e.valid
connect tlMasterXbar.auto.anon_out.e.ready, tlOtherMastersNodeIn.e.ready
connect tlMasterXbar.auto.anon_out.d, tlOtherMastersNodeIn.d
connect tlOtherMastersNodeIn.c.bits, tlMasterXbar.auto.anon_out.c.bits
connect tlOtherMastersNodeIn.c.valid, tlMasterXbar.auto.anon_out.c.valid
connect tlMasterXbar.auto.anon_out.c.ready, tlOtherMastersNodeIn.c.ready
connect tlMasterXbar.auto.anon_out.b, tlOtherMastersNodeIn.b
connect tlOtherMastersNodeIn.a.bits, tlMasterXbar.auto.anon_out.a.bits
connect tlOtherMastersNodeIn.a.valid, tlMasterXbar.auto.anon_out.a.valid
connect tlMasterXbar.auto.anon_out.a.ready, tlOtherMastersNodeIn.a.ready
connect intSinkNodeIn, intXbar.auto.anon_out
connect hartIdSinkNodeIn, broadcast.auto.out
connect broadcast.auto.in, hartidOut
connect resetVectorSinkNodeIn, broadcast_1.auto.out_0
connect frontend.auto.reset_vector_sink_in, broadcast_1.auto.out_1
connect broadcast_1.auto.in, reset_vectorOut
connect traceAuxSinkNodeIn, nexus_1.auto.out
connect intXbar.auto.anon_in_0[0], int_localOut[0]
connect intXbar.auto.anon_in_1[0], x1_int_localOut[0]
connect intXbar.auto.anon_in_1[1], x1_int_localOut[1]
connect intXbar.auto.anon_in_2[0], x1_int_localOut_1[0]
connect intXbar.auto.anon_in_3[0], x1_int_localOut_2[0]
connect buffer.auto.in, masterNodeOut
connect tlMasterXbar.auto.anon_in_0, dCacheTapOut
connect dCacheTapIn.e.bits, widget.auto.anon_out.e.bits
connect dCacheTapIn.e.valid, widget.auto.anon_out.e.valid
connect widget.auto.anon_out.e.ready, dCacheTapIn.e.ready
connect widget.auto.anon_out.d, dCacheTapIn.d
connect dCacheTapIn.c.bits, widget.auto.anon_out.c.bits
connect dCacheTapIn.c.valid, widget.auto.anon_out.c.valid
connect widget.auto.anon_out.c.ready, dCacheTapIn.c.ready
connect widget.auto.anon_out.b, dCacheTapIn.b
connect dCacheTapIn.a.bits, widget.auto.anon_out.a.bits
connect dCacheTapIn.a.valid, widget.auto.anon_out.a.valid
connect widget.auto.anon_out.a.ready, dCacheTapIn.a.ready
connect widget.auto.anon_in, dcache.auto.out
connect widget_1.auto.anon_in, frontend.auto.icache_master_out
connect tlMasterXbar.auto.anon_in_1, widget_1.auto.anon_out
connect hartidIn, auto.hartid_in
connect reset_vectorIn, auto.reset_vector_in
connect auto.trace_source_out, traceSourceNodeOut
connect auto.trace_core_source_out, traceCoreSourceNodeOut
connect int_localIn, auto.int_local_in_0
connect x1_int_localIn, auto.int_local_in_1
connect x1_int_localIn_1, auto.int_local_in_2
connect x1_int_localIn_2, auto.int_local_in_3
connect auto.halt_out, haltNodeOut
connect auto.cease_out, ceaseNodeOut
connect auto.wfi_out, wfiNodeOut
connect auto.buffer_out.e.bits, buffer.auto.out.e.bits
connect auto.buffer_out.e.valid, buffer.auto.out.e.valid
connect buffer.auto.out.e.ready, auto.buffer_out.e.ready
connect buffer.auto.out.d, auto.buffer_out.d
connect auto.buffer_out.c.bits, buffer.auto.out.c.bits
connect auto.buffer_out.c.valid, buffer.auto.out.c.valid
connect buffer.auto.out.c.ready, auto.buffer_out.c.ready
connect buffer.auto.out.b, auto.buffer_out.b
connect auto.buffer_out.a.bits, buffer.auto.out.a.bits
connect auto.buffer_out.a.valid, buffer.auto.out.a.valid
connect buffer.auto.out.a.ready, auto.buffer_out.a.ready
inst core of BoomCore
connect core.clock, clock
connect core.reset, reset
inst lsu of LSU
connect lsu.clock, clock
connect lsu.reset, reset
connect wfiNodeOut[0], UInt<1>(0h0)
connect core.io.interrupts.debug, intSinkNodeIn[0]
connect core.io.interrupts.msip, intSinkNodeIn[1]
connect core.io.interrupts.mtip, intSinkNodeIn[2]
connect core.io.interrupts.meip, intSinkNodeIn[3]
connect core.io.interrupts.seip, intSinkNodeIn[4]
connect traceSourceNodeOut, core.io.trace
connect core.io.hartid, hartIdSinkNodeIn
connect frontend.io.cpu, core.io.ifu
connect core.io.lsu, lsu.io.core
invalidate core.io.rocc.exception
invalidate core.io.rocc.interrupt
invalidate core.io.rocc.busy
invalidate core.io.rocc.mem.clock_enabled
invalidate core.io.rocc.mem.keep_clock_enabled
invalidate core.io.rocc.mem.perf.storeBufferEmptyAfterStore
invalidate core.io.rocc.mem.perf.storeBufferEmptyAfterLoad
invalidate core.io.rocc.mem.perf.canAcceptLoadThenLoad
invalidate core.io.rocc.mem.perf.canAcceptStoreThenRMW
invalidate core.io.rocc.mem.perf.canAcceptStoreThenLoad
invalidate core.io.rocc.mem.perf.blocked
invalidate core.io.rocc.mem.perf.tlbMiss
invalidate core.io.rocc.mem.perf.grant
invalidate core.io.rocc.mem.perf.release
invalidate core.io.rocc.mem.perf.acquire
invalidate core.io.rocc.mem.store_pending
invalidate core.io.rocc.mem.ordered
invalidate core.io.rocc.mem.s2_gpa_is_pte
invalidate core.io.rocc.mem.s2_gpa
invalidate core.io.rocc.mem.s2_xcpt.ae.st
invalidate core.io.rocc.mem.s2_xcpt.ae.ld
invalidate core.io.rocc.mem.s2_xcpt.gf.st
invalidate core.io.rocc.mem.s2_xcpt.gf.ld
invalidate core.io.rocc.mem.s2_xcpt.pf.st
invalidate core.io.rocc.mem.s2_xcpt.pf.ld
invalidate core.io.rocc.mem.s2_xcpt.ma.st
invalidate core.io.rocc.mem.s2_xcpt.ma.ld
invalidate core.io.rocc.mem.replay_next
invalidate core.io.rocc.mem.resp.bits.store_data
invalidate core.io.rocc.mem.resp.bits.data_raw
invalidate core.io.rocc.mem.resp.bits.data_word_bypass
invalidate core.io.rocc.mem.resp.bits.has_data
invalidate core.io.rocc.mem.resp.bits.replay
invalidate core.io.rocc.mem.resp.bits.mask
invalidate core.io.rocc.mem.resp.bits.data
invalidate core.io.rocc.mem.resp.bits.dv
invalidate core.io.rocc.mem.resp.bits.dprv
invalidate core.io.rocc.mem.resp.bits.signed
invalidate core.io.rocc.mem.resp.bits.size
invalidate core.io.rocc.mem.resp.bits.cmd
invalidate core.io.rocc.mem.resp.bits.tag
invalidate core.io.rocc.mem.resp.bits.addr
invalidate core.io.rocc.mem.resp.valid
invalidate core.io.rocc.mem.s2_paddr
invalidate core.io.rocc.mem.s2_uncached
invalidate core.io.rocc.mem.s2_kill
invalidate core.io.rocc.mem.s2_nack_cause_raw
invalidate core.io.rocc.mem.s2_nack
invalidate core.io.rocc.mem.s1_data.mask
invalidate core.io.rocc.mem.s1_data.data
invalidate core.io.rocc.mem.s1_kill
invalidate core.io.rocc.mem.req.bits.mask
invalidate core.io.rocc.mem.req.bits.data
invalidate core.io.rocc.mem.req.bits.no_xcpt
invalidate core.io.rocc.mem.req.bits.no_alloc
invalidate core.io.rocc.mem.req.bits.no_resp
invalidate core.io.rocc.mem.req.bits.phys
invalidate core.io.rocc.mem.req.bits.dv
invalidate core.io.rocc.mem.req.bits.dprv
invalidate core.io.rocc.mem.req.bits.signed
invalidate core.io.rocc.mem.req.bits.size
invalidate core.io.rocc.mem.req.bits.cmd
invalidate core.io.rocc.mem.req.bits.tag
invalidate core.io.rocc.mem.req.bits.addr
invalidate core.io.rocc.mem.req.valid
invalidate core.io.rocc.mem.req.ready
invalidate core.io.rocc.resp.bits.data
invalidate core.io.rocc.resp.bits.rd
invalidate core.io.rocc.resp.valid
invalidate core.io.rocc.resp.ready
invalidate core.io.rocc.cmd.bits.status.uie
invalidate core.io.rocc.cmd.bits.status.sie
invalidate core.io.rocc.cmd.bits.status.hie
invalidate core.io.rocc.cmd.bits.status.mie
invalidate core.io.rocc.cmd.bits.status.upie
invalidate core.io.rocc.cmd.bits.status.spie
invalidate core.io.rocc.cmd.bits.status.ube
invalidate core.io.rocc.cmd.bits.status.mpie
invalidate core.io.rocc.cmd.bits.status.spp
invalidate core.io.rocc.cmd.bits.status.vs
invalidate core.io.rocc.cmd.bits.status.mpp
invalidate core.io.rocc.cmd.bits.status.fs
invalidate core.io.rocc.cmd.bits.status.xs
invalidate core.io.rocc.cmd.bits.status.mprv
invalidate core.io.rocc.cmd.bits.status.sum
invalidate core.io.rocc.cmd.bits.status.mxr
invalidate core.io.rocc.cmd.bits.status.tvm
invalidate core.io.rocc.cmd.bits.status.tw
invalidate core.io.rocc.cmd.bits.status.tsr
invalidate core.io.rocc.cmd.bits.status.zero1
invalidate core.io.rocc.cmd.bits.status.sd_rv32
invalidate core.io.rocc.cmd.bits.status.uxl
invalidate core.io.rocc.cmd.bits.status.sxl
invalidate core.io.rocc.cmd.bits.status.sbe
invalidate core.io.rocc.cmd.bits.status.mbe
invalidate core.io.rocc.cmd.bits.status.gva
invalidate core.io.rocc.cmd.bits.status.mpv
invalidate core.io.rocc.cmd.bits.status.zero2
invalidate core.io.rocc.cmd.bits.status.sd
invalidate core.io.rocc.cmd.bits.status.v
invalidate core.io.rocc.cmd.bits.status.prv
invalidate core.io.rocc.cmd.bits.status.dv
invalidate core.io.rocc.cmd.bits.status.dprv
invalidate core.io.rocc.cmd.bits.status.isa
invalidate core.io.rocc.cmd.bits.status.wfi
invalidate core.io.rocc.cmd.bits.status.cease
invalidate core.io.rocc.cmd.bits.status.debug
invalidate core.io.rocc.cmd.bits.rs2
invalidate core.io.rocc.cmd.bits.rs1
invalidate core.io.rocc.cmd.bits.inst.opcode
invalidate core.io.rocc.cmd.bits.inst.rd
invalidate core.io.rocc.cmd.bits.inst.xs2
invalidate core.io.rocc.cmd.bits.inst.xs1
invalidate core.io.rocc.cmd.bits.inst.xd
invalidate core.io.rocc.cmd.bits.inst.rs1
invalidate core.io.rocc.cmd.bits.inst.rs2
invalidate core.io.rocc.cmd.bits.inst.funct
invalidate core.io.rocc.cmd.valid
invalidate core.io.rocc.cmd.ready
inst ptw of PTW
connect ptw.clock, clock
connect ptw.reset, reset
connect core.io.ptw, ptw.io.dpath
connect ptw.io.requestor[0], lsu.io.ptw
connect ptw.io.requestor[1], frontend.io.ptw
connect ptw.io.requestor[2], core.io.ptw_tlb
inst hellaCacheArb of HellaCacheArbiter
connect hellaCacheArb.clock, clock
connect hellaCacheArb.reset, reset
connect hellaCacheArb.io.requestor[0], ptw.io.mem
connect lsu.io.hellacache, hellaCacheArb.io.mem
connect dcache.io.lsu, lsu.io.dmem | module BoomTile( // @[tile.scala:155:7]
input clock, // @[tile.scala:155:7]
input reset, // @[tile.scala:155:7]
input auto_buffer_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_buffer_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_buffer_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_buffer_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_buffer_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_buffer_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_buffer_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [15:0] auto_buffer_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_buffer_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_buffer_out_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_buffer_out_b_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_buffer_out_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_buffer_out_b_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_buffer_out_b_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_buffer_out_b_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_buffer_out_b_bits_address, // @[LazyModuleImp.scala:107:25]
input [15:0] auto_buffer_out_b_bits_mask, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_buffer_out_b_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_buffer_out_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_buffer_out_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_buffer_out_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_buffer_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_buffer_out_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_buffer_out_c_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_buffer_out_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_buffer_out_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_buffer_out_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_buffer_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_buffer_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_buffer_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_buffer_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_buffer_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_buffer_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_buffer_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_buffer_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_buffer_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_buffer_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_buffer_out_e_ready, // @[LazyModuleImp.scala:107:25]
output auto_buffer_out_e_valid, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_buffer_out_e_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_int_local_in_3_0, // @[LazyModuleImp.scala:107:25]
input auto_int_local_in_2_0, // @[LazyModuleImp.scala:107:25]
input auto_int_local_in_1_0, // @[LazyModuleImp.scala:107:25]
input auto_int_local_in_1_1, // @[LazyModuleImp.scala:107:25]
input auto_int_local_in_0_0, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_trace_source_out_time, // @[LazyModuleImp.scala:107:25]
output auto_trace_source_out_custom_rob_empty, // @[LazyModuleImp.scala:107:25]
input auto_hartid_in // @[LazyModuleImp.scala:107:25]
);
wire dCacheTapOut_e_ready; // @[MixedNode.scala:542:17]
wire dCacheTapOut_d_valid; // @[MixedNode.scala:542:17]
wire dCacheTapOut_d_bits_corrupt; // @[MixedNode.scala:542:17]
wire [127:0] dCacheTapOut_d_bits_data; // @[MixedNode.scala:542:17]
wire dCacheTapOut_d_bits_denied; // @[MixedNode.scala:542:17]
wire [3:0] dCacheTapOut_d_bits_sink; // @[MixedNode.scala:542:17]
wire [2:0] dCacheTapOut_d_bits_source; // @[MixedNode.scala:542:17]
wire [3:0] dCacheTapOut_d_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] dCacheTapOut_d_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] dCacheTapOut_d_bits_opcode; // @[MixedNode.scala:542:17]
wire dCacheTapOut_c_ready; // @[MixedNode.scala:542:17]
wire dCacheTapOut_b_valid; // @[MixedNode.scala:542:17]
wire dCacheTapOut_b_bits_corrupt; // @[MixedNode.scala:542:17]
wire [127:0] dCacheTapOut_b_bits_data; // @[MixedNode.scala:542:17]
wire [15:0] dCacheTapOut_b_bits_mask; // @[MixedNode.scala:542:17]
wire [31:0] dCacheTapOut_b_bits_address; // @[MixedNode.scala:542:17]
wire [2:0] dCacheTapOut_b_bits_source; // @[MixedNode.scala:542:17]
wire [3:0] dCacheTapOut_b_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] dCacheTapOut_b_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] dCacheTapOut_b_bits_opcode; // @[MixedNode.scala:542:17]
wire dCacheTapOut_a_ready; // @[MixedNode.scala:542:17]
wire tlOtherMastersNodeOut_e_valid; // @[MixedNode.scala:542:17]
wire tlOtherMastersNodeOut_e_ready; // @[MixedNode.scala:542:17]
wire [3:0] tlOtherMastersNodeOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire tlOtherMastersNodeOut_d_valid; // @[MixedNode.scala:542:17]
wire tlOtherMastersNodeOut_d_ready; // @[MixedNode.scala:542:17]
wire tlOtherMastersNodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17]
wire [127:0] tlOtherMastersNodeOut_d_bits_data; // @[MixedNode.scala:542:17]
wire tlOtherMastersNodeOut_d_bits_denied; // @[MixedNode.scala:542:17]
wire [3:0] tlOtherMastersNodeOut_d_bits_sink; // @[MixedNode.scala:542:17]
wire [3:0] tlOtherMastersNodeOut_d_bits_source; // @[MixedNode.scala:542:17]
wire [3:0] tlOtherMastersNodeOut_d_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] tlOtherMastersNodeOut_d_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] tlOtherMastersNodeOut_d_bits_opcode; // @[MixedNode.scala:542:17]
wire tlOtherMastersNodeOut_c_valid; // @[MixedNode.scala:542:17]
wire tlOtherMastersNodeOut_c_ready; // @[MixedNode.scala:542:17]
wire [127:0] tlOtherMastersNodeOut_c_bits_data; // @[MixedNode.scala:542:17]
wire [31:0] tlOtherMastersNodeOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [3:0] tlOtherMastersNodeOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [3:0] tlOtherMastersNodeOut_c_bits_size; // @[MixedNode.scala:542:17]
wire [2:0] tlOtherMastersNodeOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] tlOtherMastersNodeOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire tlOtherMastersNodeOut_b_valid; // @[MixedNode.scala:542:17]
wire tlOtherMastersNodeOut_b_ready; // @[MixedNode.scala:542:17]
wire tlOtherMastersNodeOut_b_bits_corrupt; // @[MixedNode.scala:542:17]
wire [127:0] tlOtherMastersNodeOut_b_bits_data; // @[MixedNode.scala:542:17]
wire [15:0] tlOtherMastersNodeOut_b_bits_mask; // @[MixedNode.scala:542:17]
wire [31:0] tlOtherMastersNodeOut_b_bits_address; // @[MixedNode.scala:542:17]
wire [3:0] tlOtherMastersNodeOut_b_bits_source; // @[MixedNode.scala:542:17]
wire [3:0] tlOtherMastersNodeOut_b_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] tlOtherMastersNodeOut_b_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] tlOtherMastersNodeOut_b_bits_opcode; // @[MixedNode.scala:542:17]
wire tlOtherMastersNodeOut_a_valid; // @[MixedNode.scala:542:17]
wire tlOtherMastersNodeOut_a_ready; // @[MixedNode.scala:542:17]
wire [127:0] tlOtherMastersNodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire [15:0] tlOtherMastersNodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [31:0] tlOtherMastersNodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [3:0] tlOtherMastersNodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [3:0] tlOtherMastersNodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [2:0] tlOtherMastersNodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] tlOtherMastersNodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire buffer_auto_in_e_valid; // @[Buffer.scala:40:9]
wire buffer_auto_in_e_ready; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_in_e_bits_sink; // @[Buffer.scala:40:9]
wire buffer_auto_in_d_valid; // @[Buffer.scala:40:9]
wire buffer_auto_in_d_ready; // @[Buffer.scala:40:9]
wire buffer_auto_in_d_bits_corrupt; // @[Buffer.scala:40:9]
wire [127:0] buffer_auto_in_d_bits_data; // @[Buffer.scala:40:9]
wire buffer_auto_in_d_bits_denied; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_in_d_bits_sink; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_in_d_bits_source; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_in_d_bits_size; // @[Buffer.scala:40:9]
wire [1:0] buffer_auto_in_d_bits_param; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala:40:9]
wire buffer_auto_in_c_valid; // @[Buffer.scala:40:9]
wire buffer_auto_in_c_ready; // @[Buffer.scala:40:9]
wire [127:0] buffer_auto_in_c_bits_data; // @[Buffer.scala:40:9]
wire [31:0] buffer_auto_in_c_bits_address; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_in_c_bits_source; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_in_c_bits_size; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_in_c_bits_param; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_in_c_bits_opcode; // @[Buffer.scala:40:9]
wire buffer_auto_in_b_valid; // @[Buffer.scala:40:9]
wire buffer_auto_in_b_ready; // @[Buffer.scala:40:9]
wire buffer_auto_in_b_bits_corrupt; // @[Buffer.scala:40:9]
wire [127:0] buffer_auto_in_b_bits_data; // @[Buffer.scala:40:9]
wire [15:0] buffer_auto_in_b_bits_mask; // @[Buffer.scala:40:9]
wire [31:0] buffer_auto_in_b_bits_address; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_in_b_bits_source; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_in_b_bits_size; // @[Buffer.scala:40:9]
wire [1:0] buffer_auto_in_b_bits_param; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_in_b_bits_opcode; // @[Buffer.scala:40:9]
wire buffer_auto_in_a_valid; // @[Buffer.scala:40:9]
wire buffer_auto_in_a_ready; // @[Buffer.scala:40:9]
wire [127:0] buffer_auto_in_a_bits_data; // @[Buffer.scala:40:9]
wire [15:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala:40:9]
wire [31:0] buffer_auto_in_a_bits_address; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_in_a_bits_source; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_in_a_bits_size; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala:40:9]
wire widget_1_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire [127:0] widget_1_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [3:0] widget_1_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9]
wire [3:0] widget_1_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9]
wire [1:0] widget_1_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] widget_1_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9]
wire [31:0] widget_1_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_e_valid; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_e_ready; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_out_e_bits_sink; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire [127:0] widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9]
wire [1:0] widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_c_valid; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_c_ready; // @[WidthWidget.scala:27:9]
wire [127:0] widget_auto_anon_out_c_bits_data; // @[WidthWidget.scala:27:9]
wire [31:0] widget_auto_anon_out_c_bits_address; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_out_c_bits_source; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_out_c_bits_size; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_out_c_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_out_c_bits_opcode; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_b_valid; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_b_ready; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_b_bits_corrupt; // @[WidthWidget.scala:27:9]
wire [127:0] widget_auto_anon_out_b_bits_data; // @[WidthWidget.scala:27:9]
wire [15:0] widget_auto_anon_out_b_bits_mask; // @[WidthWidget.scala:27:9]
wire [31:0] widget_auto_anon_out_b_bits_address; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_out_b_bits_source; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_out_b_bits_size; // @[WidthWidget.scala:27:9]
wire [1:0] widget_auto_anon_out_b_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_out_b_bits_opcode; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9]
wire [127:0] widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9]
wire [15:0] widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [31:0] widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_e_valid; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_in_e_bits_sink; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_d_ready; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_c_valid; // @[WidthWidget.scala:27:9]
wire [127:0] widget_auto_anon_in_c_bits_data; // @[WidthWidget.scala:27:9]
wire [31:0] widget_auto_anon_in_c_bits_address; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_in_c_bits_source; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_in_c_bits_size; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_in_c_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_in_c_bits_opcode; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_b_ready; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9]
wire [127:0] widget_auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9]
wire [15:0] widget_auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [31:0] widget_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire broadcast_auto_in; // @[BundleBridgeNexus.scala:20:9]
wire _hellaCacheArb_io_requestor_0_req_ready; // @[tile.scala:243:29]
wire _hellaCacheArb_io_requestor_0_s2_nack; // @[tile.scala:243:29]
wire _hellaCacheArb_io_requestor_0_resp_valid; // @[tile.scala:243:29]
wire [39:0] _hellaCacheArb_io_requestor_0_resp_bits_addr; // @[tile.scala:243:29]
wire [63:0] _hellaCacheArb_io_requestor_0_resp_bits_data; // @[tile.scala:243:29]
wire _hellaCacheArb_io_requestor_0_s2_xcpt_ma_ld; // @[tile.scala:243:29]
wire _hellaCacheArb_io_requestor_0_s2_xcpt_ma_st; // @[tile.scala:243:29]
wire _hellaCacheArb_io_requestor_0_s2_xcpt_pf_ld; // @[tile.scala:243:29]
wire _hellaCacheArb_io_requestor_0_s2_xcpt_pf_st; // @[tile.scala:243:29]
wire _hellaCacheArb_io_requestor_0_s2_xcpt_gf_ld; // @[tile.scala:243:29]
wire _hellaCacheArb_io_requestor_0_s2_xcpt_gf_st; // @[tile.scala:243:29]
wire _hellaCacheArb_io_requestor_0_s2_xcpt_ae_ld; // @[tile.scala:243:29]
wire _hellaCacheArb_io_requestor_0_s2_xcpt_ae_st; // @[tile.scala:243:29]
wire _hellaCacheArb_io_requestor_0_store_pending; // @[tile.scala:243:29]
wire _hellaCacheArb_io_mem_req_valid; // @[tile.scala:243:29]
wire [39:0] _hellaCacheArb_io_mem_req_bits_addr; // @[tile.scala:243:29]
wire _hellaCacheArb_io_mem_req_bits_dv; // @[tile.scala:243:29]
wire _hellaCacheArb_io_mem_s1_kill; // @[tile.scala:243:29]
wire _ptw_io_requestor_0_req_ready; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_resp_valid; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_resp_bits_ae_ptw; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_resp_bits_ae_final; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_resp_bits_pf; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_resp_bits_gf; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_resp_bits_hr; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_resp_bits_hw; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_resp_bits_hx; // @[tile.scala:237:20]
wire [9:0] _ptw_io_requestor_0_resp_bits_pte_reserved_for_future; // @[tile.scala:237:20]
wire [43:0] _ptw_io_requestor_0_resp_bits_pte_ppn; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_0_resp_bits_pte_reserved_for_software; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_resp_bits_pte_d; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_resp_bits_pte_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_resp_bits_pte_g; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_resp_bits_pte_u; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_resp_bits_pte_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_resp_bits_pte_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_resp_bits_pte_r; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_resp_bits_pte_v; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_0_resp_bits_level; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_resp_bits_homogeneous; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_resp_bits_gpa_valid; // @[tile.scala:237:20]
wire [38:0] _ptw_io_requestor_0_resp_bits_gpa_bits; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_resp_bits_gpa_is_pte; // @[tile.scala:237:20]
wire [3:0] _ptw_io_requestor_0_ptbr_mode; // @[tile.scala:237:20]
wire [43:0] _ptw_io_requestor_0_ptbr_ppn; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_status_debug; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_status_cease; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_status_wfi; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_0_status_dprv; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_status_dv; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_0_status_prv; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_status_v; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_status_sd; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_status_mpv; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_status_gva; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_status_tsr; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_status_tw; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_status_tvm; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_status_mxr; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_status_sum; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_status_mprv; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_0_status_fs; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_0_status_mpp; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_status_spp; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_status_mpie; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_status_spie; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_status_mie; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_status_sie; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_0_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_0_pmp_0_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_0_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_0_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_0_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_0_pmp_0_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_0_pmp_0_mask; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_1_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_0_pmp_1_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_1_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_1_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_1_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_0_pmp_1_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_0_pmp_1_mask; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_2_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_0_pmp_2_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_2_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_2_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_2_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_0_pmp_2_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_0_pmp_2_mask; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_3_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_0_pmp_3_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_3_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_3_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_3_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_0_pmp_3_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_0_pmp_3_mask; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_4_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_0_pmp_4_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_4_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_4_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_4_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_0_pmp_4_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_0_pmp_4_mask; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_5_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_0_pmp_5_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_5_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_5_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_5_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_0_pmp_5_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_0_pmp_5_mask; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_6_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_0_pmp_6_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_6_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_6_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_6_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_0_pmp_6_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_0_pmp_6_mask; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_7_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_0_pmp_7_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_7_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_7_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_7_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_0_pmp_7_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_0_pmp_7_mask; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_req_ready; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_resp_valid; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_resp_bits_ae_ptw; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_resp_bits_ae_final; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_resp_bits_pf; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_resp_bits_gf; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_resp_bits_hr; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_resp_bits_hw; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_resp_bits_hx; // @[tile.scala:237:20]
wire [9:0] _ptw_io_requestor_1_resp_bits_pte_reserved_for_future; // @[tile.scala:237:20]
wire [43:0] _ptw_io_requestor_1_resp_bits_pte_ppn; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_1_resp_bits_pte_reserved_for_software; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_resp_bits_pte_d; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_resp_bits_pte_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_resp_bits_pte_g; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_resp_bits_pte_u; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_resp_bits_pte_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_resp_bits_pte_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_resp_bits_pte_r; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_resp_bits_pte_v; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_1_resp_bits_level; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_resp_bits_homogeneous; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_resp_bits_gpa_valid; // @[tile.scala:237:20]
wire [38:0] _ptw_io_requestor_1_resp_bits_gpa_bits; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_resp_bits_gpa_is_pte; // @[tile.scala:237:20]
wire [3:0] _ptw_io_requestor_1_ptbr_mode; // @[tile.scala:237:20]
wire [43:0] _ptw_io_requestor_1_ptbr_ppn; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_status_debug; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_status_cease; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_status_wfi; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_1_status_dprv; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_status_dv; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_1_status_prv; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_status_v; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_status_sd; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_status_mpv; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_status_gva; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_status_tsr; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_status_tw; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_status_tvm; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_status_mxr; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_status_sum; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_status_mprv; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_1_status_fs; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_1_status_mpp; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_status_spp; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_status_mpie; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_status_spie; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_status_mie; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_status_sie; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_0_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_1_pmp_0_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_0_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_0_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_0_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_1_pmp_0_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_1_pmp_0_mask; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_1_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_1_pmp_1_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_1_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_1_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_1_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_1_pmp_1_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_1_pmp_1_mask; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_2_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_1_pmp_2_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_2_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_2_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_2_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_1_pmp_2_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_1_pmp_2_mask; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_3_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_1_pmp_3_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_3_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_3_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_3_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_1_pmp_3_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_1_pmp_3_mask; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_4_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_1_pmp_4_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_4_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_4_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_4_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_1_pmp_4_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_1_pmp_4_mask; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_5_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_1_pmp_5_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_5_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_5_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_5_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_1_pmp_5_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_1_pmp_5_mask; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_6_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_1_pmp_6_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_6_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_6_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_6_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_1_pmp_6_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_1_pmp_6_mask; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_7_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_1_pmp_7_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_7_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_7_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_7_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_1_pmp_7_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_1_pmp_7_mask; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_req_ready; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_resp_valid; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_resp_bits_ae_ptw; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_resp_bits_ae_final; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_resp_bits_pf; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_resp_bits_gf; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_resp_bits_hr; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_resp_bits_hw; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_resp_bits_hx; // @[tile.scala:237:20]
wire [9:0] _ptw_io_requestor_2_resp_bits_pte_reserved_for_future; // @[tile.scala:237:20]
wire [43:0] _ptw_io_requestor_2_resp_bits_pte_ppn; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_2_resp_bits_pte_reserved_for_software; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_resp_bits_pte_d; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_resp_bits_pte_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_resp_bits_pte_g; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_resp_bits_pte_u; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_resp_bits_pte_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_resp_bits_pte_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_resp_bits_pte_r; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_resp_bits_pte_v; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_2_resp_bits_level; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_resp_bits_homogeneous; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_resp_bits_gpa_valid; // @[tile.scala:237:20]
wire [38:0] _ptw_io_requestor_2_resp_bits_gpa_bits; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_resp_bits_gpa_is_pte; // @[tile.scala:237:20]
wire [3:0] _ptw_io_requestor_2_ptbr_mode; // @[tile.scala:237:20]
wire [43:0] _ptw_io_requestor_2_ptbr_ppn; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_status_debug; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_status_cease; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_status_wfi; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_2_status_dprv; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_status_dv; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_2_status_prv; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_status_v; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_status_sd; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_status_mpv; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_status_gva; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_status_tsr; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_status_tw; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_status_tvm; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_status_mxr; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_status_sum; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_status_mprv; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_2_status_fs; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_2_status_mpp; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_status_spp; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_status_mpie; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_status_spie; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_status_mie; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_status_sie; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_0_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_2_pmp_0_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_0_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_0_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_0_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_2_pmp_0_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_2_pmp_0_mask; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_1_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_2_pmp_1_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_1_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_1_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_1_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_2_pmp_1_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_2_pmp_1_mask; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_2_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_2_pmp_2_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_2_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_2_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_2_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_2_pmp_2_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_2_pmp_2_mask; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_3_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_2_pmp_3_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_3_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_3_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_3_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_2_pmp_3_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_2_pmp_3_mask; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_4_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_2_pmp_4_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_4_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_4_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_4_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_2_pmp_4_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_2_pmp_4_mask; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_5_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_2_pmp_5_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_5_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_5_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_5_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_2_pmp_5_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_2_pmp_5_mask; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_6_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_2_pmp_6_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_6_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_6_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_6_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_2_pmp_6_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_2_pmp_6_mask; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_7_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_2_pmp_7_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_7_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_7_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_7_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_2_pmp_7_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_2_pmp_7_mask; // @[tile.scala:237:20]
wire _ptw_io_mem_req_valid; // @[tile.scala:237:20]
wire [39:0] _ptw_io_mem_req_bits_addr; // @[tile.scala:237:20]
wire _ptw_io_mem_req_bits_dv; // @[tile.scala:237:20]
wire _ptw_io_mem_s1_kill; // @[tile.scala:237:20]
wire _ptw_io_dpath_perf_l2miss; // @[tile.scala:237:20]
wire _ptw_io_dpath_perf_l2hit; // @[tile.scala:237:20]
wire _ptw_io_dpath_perf_pte_miss; // @[tile.scala:237:20]
wire _ptw_io_dpath_perf_pte_hit; // @[tile.scala:237:20]
wire _ptw_io_dpath_clock_enabled; // @[tile.scala:237:20]
wire _lsu_io_ptw_req_valid; // @[tile.scala:160:20]
wire _lsu_io_ptw_req_bits_valid; // @[tile.scala:160:20]
wire [26:0] _lsu_io_ptw_req_bits_bits_addr; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_valid; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_exe_0_iresp_bits_uop_uopc; // @[tile.scala:160:20]
wire [31:0] _lsu_io_core_exe_0_iresp_bits_uop_inst; // @[tile.scala:160:20]
wire [31:0] _lsu_io_core_exe_0_iresp_bits_uop_debug_inst; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_is_rvc; // @[tile.scala:160:20]
wire [39:0] _lsu_io_core_exe_0_iresp_bits_uop_debug_pc; // @[tile.scala:160:20]
wire [2:0] _lsu_io_core_exe_0_iresp_bits_uop_iq_type; // @[tile.scala:160:20]
wire [9:0] _lsu_io_core_exe_0_iresp_bits_uop_fu_code; // @[tile.scala:160:20]
wire [3:0] _lsu_io_core_exe_0_iresp_bits_uop_ctrl_br_type; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_exe_0_iresp_bits_uop_ctrl_op1_sel; // @[tile.scala:160:20]
wire [2:0] _lsu_io_core_exe_0_iresp_bits_uop_ctrl_op2_sel; // @[tile.scala:160:20]
wire [2:0] _lsu_io_core_exe_0_iresp_bits_uop_ctrl_imm_sel; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_exe_0_iresp_bits_uop_ctrl_op_fcn; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_ctrl_fcn_dw; // @[tile.scala:160:20]
wire [2:0] _lsu_io_core_exe_0_iresp_bits_uop_ctrl_csr_cmd; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_ctrl_is_load; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_ctrl_is_sta; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_ctrl_is_std; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_exe_0_iresp_bits_uop_iw_state; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_iw_p1_poisoned; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_iw_p2_poisoned; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_is_br; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_is_jalr; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_is_jal; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_is_sfb; // @[tile.scala:160:20]
wire [15:0] _lsu_io_core_exe_0_iresp_bits_uop_br_mask; // @[tile.scala:160:20]
wire [3:0] _lsu_io_core_exe_0_iresp_bits_uop_br_tag; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_exe_0_iresp_bits_uop_ftq_idx; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_edge_inst; // @[tile.scala:160:20]
wire [5:0] _lsu_io_core_exe_0_iresp_bits_uop_pc_lob; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_taken; // @[tile.scala:160:20]
wire [19:0] _lsu_io_core_exe_0_iresp_bits_uop_imm_packed; // @[tile.scala:160:20]
wire [11:0] _lsu_io_core_exe_0_iresp_bits_uop_csr_addr; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_exe_0_iresp_bits_uop_rob_idx; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_exe_0_iresp_bits_uop_ldq_idx; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_exe_0_iresp_bits_uop_stq_idx; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_exe_0_iresp_bits_uop_rxq_idx; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_exe_0_iresp_bits_uop_pdst; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_exe_0_iresp_bits_uop_prs1; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_exe_0_iresp_bits_uop_prs2; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_exe_0_iresp_bits_uop_prs3; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_exe_0_iresp_bits_uop_ppred; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_prs1_busy; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_prs2_busy; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_prs3_busy; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_ppred_busy; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_exe_0_iresp_bits_uop_stale_pdst; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_exception; // @[tile.scala:160:20]
wire [63:0] _lsu_io_core_exe_0_iresp_bits_uop_exc_cause; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_bypassable; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_exe_0_iresp_bits_uop_mem_cmd; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_exe_0_iresp_bits_uop_mem_size; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_mem_signed; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_is_fence; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_is_fencei; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_is_amo; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_uses_ldq; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_uses_stq; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_is_sys_pc2epc; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_is_unique; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_flush_on_commit; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_ldst_is_rs1; // @[tile.scala:160:20]
wire [5:0] _lsu_io_core_exe_0_iresp_bits_uop_ldst; // @[tile.scala:160:20]
wire [5:0] _lsu_io_core_exe_0_iresp_bits_uop_lrs1; // @[tile.scala:160:20]
wire [5:0] _lsu_io_core_exe_0_iresp_bits_uop_lrs2; // @[tile.scala:160:20]
wire [5:0] _lsu_io_core_exe_0_iresp_bits_uop_lrs3; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_ldst_val; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_exe_0_iresp_bits_uop_dst_rtype; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_exe_0_iresp_bits_uop_lrs1_rtype; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_exe_0_iresp_bits_uop_lrs2_rtype; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_frs3_en; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_fp_val; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_fp_single; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_xcpt_pf_if; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_xcpt_ae_if; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_xcpt_ma_if; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_bp_debug_if; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_bp_xcpt_if; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_exe_0_iresp_bits_uop_debug_fsrc; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_exe_0_iresp_bits_uop_debug_tsrc; // @[tile.scala:160:20]
wire [63:0] _lsu_io_core_exe_0_iresp_bits_data; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_valid; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_exe_0_fresp_bits_uop_uopc; // @[tile.scala:160:20]
wire [31:0] _lsu_io_core_exe_0_fresp_bits_uop_inst; // @[tile.scala:160:20]
wire [31:0] _lsu_io_core_exe_0_fresp_bits_uop_debug_inst; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_is_rvc; // @[tile.scala:160:20]
wire [39:0] _lsu_io_core_exe_0_fresp_bits_uop_debug_pc; // @[tile.scala:160:20]
wire [2:0] _lsu_io_core_exe_0_fresp_bits_uop_iq_type; // @[tile.scala:160:20]
wire [9:0] _lsu_io_core_exe_0_fresp_bits_uop_fu_code; // @[tile.scala:160:20]
wire [3:0] _lsu_io_core_exe_0_fresp_bits_uop_ctrl_br_type; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_exe_0_fresp_bits_uop_ctrl_op1_sel; // @[tile.scala:160:20]
wire [2:0] _lsu_io_core_exe_0_fresp_bits_uop_ctrl_op2_sel; // @[tile.scala:160:20]
wire [2:0] _lsu_io_core_exe_0_fresp_bits_uop_ctrl_imm_sel; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_exe_0_fresp_bits_uop_ctrl_op_fcn; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_ctrl_fcn_dw; // @[tile.scala:160:20]
wire [2:0] _lsu_io_core_exe_0_fresp_bits_uop_ctrl_csr_cmd; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_ctrl_is_load; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_ctrl_is_sta; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_ctrl_is_std; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_exe_0_fresp_bits_uop_iw_state; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_iw_p1_poisoned; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_iw_p2_poisoned; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_is_br; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_is_jalr; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_is_jal; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_is_sfb; // @[tile.scala:160:20]
wire [15:0] _lsu_io_core_exe_0_fresp_bits_uop_br_mask; // @[tile.scala:160:20]
wire [3:0] _lsu_io_core_exe_0_fresp_bits_uop_br_tag; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_exe_0_fresp_bits_uop_ftq_idx; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_edge_inst; // @[tile.scala:160:20]
wire [5:0] _lsu_io_core_exe_0_fresp_bits_uop_pc_lob; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_taken; // @[tile.scala:160:20]
wire [19:0] _lsu_io_core_exe_0_fresp_bits_uop_imm_packed; // @[tile.scala:160:20]
wire [11:0] _lsu_io_core_exe_0_fresp_bits_uop_csr_addr; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_exe_0_fresp_bits_uop_rob_idx; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_exe_0_fresp_bits_uop_ldq_idx; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_exe_0_fresp_bits_uop_stq_idx; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_exe_0_fresp_bits_uop_rxq_idx; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_exe_0_fresp_bits_uop_pdst; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_exe_0_fresp_bits_uop_prs1; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_exe_0_fresp_bits_uop_prs2; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_exe_0_fresp_bits_uop_prs3; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_exe_0_fresp_bits_uop_ppred; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_prs1_busy; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_prs2_busy; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_prs3_busy; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_ppred_busy; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_exe_0_fresp_bits_uop_stale_pdst; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_exception; // @[tile.scala:160:20]
wire [63:0] _lsu_io_core_exe_0_fresp_bits_uop_exc_cause; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_bypassable; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_exe_0_fresp_bits_uop_mem_cmd; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_exe_0_fresp_bits_uop_mem_size; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_mem_signed; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_is_fence; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_is_fencei; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_is_amo; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_uses_ldq; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_uses_stq; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_is_sys_pc2epc; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_is_unique; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_flush_on_commit; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_ldst_is_rs1; // @[tile.scala:160:20]
wire [5:0] _lsu_io_core_exe_0_fresp_bits_uop_ldst; // @[tile.scala:160:20]
wire [5:0] _lsu_io_core_exe_0_fresp_bits_uop_lrs1; // @[tile.scala:160:20]
wire [5:0] _lsu_io_core_exe_0_fresp_bits_uop_lrs2; // @[tile.scala:160:20]
wire [5:0] _lsu_io_core_exe_0_fresp_bits_uop_lrs3; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_ldst_val; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_exe_0_fresp_bits_uop_dst_rtype; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_exe_0_fresp_bits_uop_lrs1_rtype; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_exe_0_fresp_bits_uop_lrs2_rtype; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_frs3_en; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_fp_val; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_fp_single; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_xcpt_pf_if; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_xcpt_ae_if; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_xcpt_ma_if; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_bp_debug_if; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_bp_xcpt_if; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_exe_0_fresp_bits_uop_debug_fsrc; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_exe_0_fresp_bits_uop_debug_tsrc; // @[tile.scala:160:20]
wire [64:0] _lsu_io_core_exe_0_fresp_bits_data; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_dis_ldq_idx_0; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_dis_ldq_idx_1; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_dis_ldq_idx_2; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_dis_stq_idx_0; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_dis_stq_idx_1; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_dis_stq_idx_2; // @[tile.scala:160:20]
wire _lsu_io_core_ldq_full_0; // @[tile.scala:160:20]
wire _lsu_io_core_ldq_full_1; // @[tile.scala:160:20]
wire _lsu_io_core_ldq_full_2; // @[tile.scala:160:20]
wire _lsu_io_core_stq_full_0; // @[tile.scala:160:20]
wire _lsu_io_core_stq_full_1; // @[tile.scala:160:20]
wire _lsu_io_core_stq_full_2; // @[tile.scala:160:20]
wire _lsu_io_core_fp_stdata_ready; // @[tile.scala:160:20]
wire _lsu_io_core_clr_bsy_0_valid; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_clr_bsy_0_bits; // @[tile.scala:160:20]
wire _lsu_io_core_clr_bsy_1_valid; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_clr_bsy_1_bits; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_clr_unsafe_0_bits; // @[tile.scala:160:20]
wire _lsu_io_core_spec_ld_wakeup_0_valid; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_spec_ld_wakeup_0_bits; // @[tile.scala:160:20]
wire _lsu_io_core_ld_miss; // @[tile.scala:160:20]
wire _lsu_io_core_fencei_rdy; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_valid; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_lxcpt_bits_uop_uopc; // @[tile.scala:160:20]
wire [31:0] _lsu_io_core_lxcpt_bits_uop_inst; // @[tile.scala:160:20]
wire [31:0] _lsu_io_core_lxcpt_bits_uop_debug_inst; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_is_rvc; // @[tile.scala:160:20]
wire [39:0] _lsu_io_core_lxcpt_bits_uop_debug_pc; // @[tile.scala:160:20]
wire [2:0] _lsu_io_core_lxcpt_bits_uop_iq_type; // @[tile.scala:160:20]
wire [9:0] _lsu_io_core_lxcpt_bits_uop_fu_code; // @[tile.scala:160:20]
wire [3:0] _lsu_io_core_lxcpt_bits_uop_ctrl_br_type; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_lxcpt_bits_uop_ctrl_op1_sel; // @[tile.scala:160:20]
wire [2:0] _lsu_io_core_lxcpt_bits_uop_ctrl_op2_sel; // @[tile.scala:160:20]
wire [2:0] _lsu_io_core_lxcpt_bits_uop_ctrl_imm_sel; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_lxcpt_bits_uop_ctrl_op_fcn; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_ctrl_fcn_dw; // @[tile.scala:160:20]
wire [2:0] _lsu_io_core_lxcpt_bits_uop_ctrl_csr_cmd; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_ctrl_is_load; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_ctrl_is_sta; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_ctrl_is_std; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_lxcpt_bits_uop_iw_state; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_iw_p1_poisoned; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_iw_p2_poisoned; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_is_br; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_is_jalr; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_is_jal; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_is_sfb; // @[tile.scala:160:20]
wire [15:0] _lsu_io_core_lxcpt_bits_uop_br_mask; // @[tile.scala:160:20]
wire [3:0] _lsu_io_core_lxcpt_bits_uop_br_tag; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_lxcpt_bits_uop_ftq_idx; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_edge_inst; // @[tile.scala:160:20]
wire [5:0] _lsu_io_core_lxcpt_bits_uop_pc_lob; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_taken; // @[tile.scala:160:20]
wire [19:0] _lsu_io_core_lxcpt_bits_uop_imm_packed; // @[tile.scala:160:20]
wire [11:0] _lsu_io_core_lxcpt_bits_uop_csr_addr; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_lxcpt_bits_uop_rob_idx; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_lxcpt_bits_uop_ldq_idx; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_lxcpt_bits_uop_stq_idx; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_lxcpt_bits_uop_rxq_idx; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_lxcpt_bits_uop_pdst; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_lxcpt_bits_uop_prs1; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_lxcpt_bits_uop_prs2; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_lxcpt_bits_uop_prs3; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_lxcpt_bits_uop_ppred; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_prs1_busy; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_prs2_busy; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_prs3_busy; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_ppred_busy; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_lxcpt_bits_uop_stale_pdst; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_exception; // @[tile.scala:160:20]
wire [63:0] _lsu_io_core_lxcpt_bits_uop_exc_cause; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_bypassable; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_lxcpt_bits_uop_mem_cmd; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_lxcpt_bits_uop_mem_size; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_mem_signed; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_is_fence; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_is_fencei; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_is_amo; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_uses_ldq; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_uses_stq; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_is_sys_pc2epc; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_is_unique; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_flush_on_commit; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_ldst_is_rs1; // @[tile.scala:160:20]
wire [5:0] _lsu_io_core_lxcpt_bits_uop_ldst; // @[tile.scala:160:20]
wire [5:0] _lsu_io_core_lxcpt_bits_uop_lrs1; // @[tile.scala:160:20]
wire [5:0] _lsu_io_core_lxcpt_bits_uop_lrs2; // @[tile.scala:160:20]
wire [5:0] _lsu_io_core_lxcpt_bits_uop_lrs3; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_ldst_val; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_lxcpt_bits_uop_dst_rtype; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_lxcpt_bits_uop_lrs1_rtype; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_lxcpt_bits_uop_lrs2_rtype; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_frs3_en; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_fp_val; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_fp_single; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_xcpt_pf_if; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_xcpt_ae_if; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_xcpt_ma_if; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_bp_debug_if; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_bp_xcpt_if; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_lxcpt_bits_uop_debug_fsrc; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_lxcpt_bits_uop_debug_tsrc; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_lxcpt_bits_cause; // @[tile.scala:160:20]
wire [39:0] _lsu_io_core_lxcpt_bits_badvaddr; // @[tile.scala:160:20]
wire _lsu_io_core_perf_acquire; // @[tile.scala:160:20]
wire _lsu_io_core_perf_release; // @[tile.scala:160:20]
wire _lsu_io_core_perf_tlbMiss; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_valid; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_valid; // @[tile.scala:160:20]
wire [6:0] _lsu_io_dmem_req_bits_0_bits_uop_uopc; // @[tile.scala:160:20]
wire [31:0] _lsu_io_dmem_req_bits_0_bits_uop_inst; // @[tile.scala:160:20]
wire [31:0] _lsu_io_dmem_req_bits_0_bits_uop_debug_inst; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_is_rvc; // @[tile.scala:160:20]
wire [39:0] _lsu_io_dmem_req_bits_0_bits_uop_debug_pc; // @[tile.scala:160:20]
wire [2:0] _lsu_io_dmem_req_bits_0_bits_uop_iq_type; // @[tile.scala:160:20]
wire [9:0] _lsu_io_dmem_req_bits_0_bits_uop_fu_code; // @[tile.scala:160:20]
wire [3:0] _lsu_io_dmem_req_bits_0_bits_uop_ctrl_br_type; // @[tile.scala:160:20]
wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_ctrl_op1_sel; // @[tile.scala:160:20]
wire [2:0] _lsu_io_dmem_req_bits_0_bits_uop_ctrl_op2_sel; // @[tile.scala:160:20]
wire [2:0] _lsu_io_dmem_req_bits_0_bits_uop_ctrl_imm_sel; // @[tile.scala:160:20]
wire [4:0] _lsu_io_dmem_req_bits_0_bits_uop_ctrl_op_fcn; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_ctrl_fcn_dw; // @[tile.scala:160:20]
wire [2:0] _lsu_io_dmem_req_bits_0_bits_uop_ctrl_csr_cmd; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_ctrl_is_load; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_ctrl_is_sta; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_ctrl_is_std; // @[tile.scala:160:20]
wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_iw_state; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_iw_p1_poisoned; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_iw_p2_poisoned; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_is_br; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_is_jalr; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_is_jal; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_is_sfb; // @[tile.scala:160:20]
wire [15:0] _lsu_io_dmem_req_bits_0_bits_uop_br_mask; // @[tile.scala:160:20]
wire [3:0] _lsu_io_dmem_req_bits_0_bits_uop_br_tag; // @[tile.scala:160:20]
wire [4:0] _lsu_io_dmem_req_bits_0_bits_uop_ftq_idx; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_edge_inst; // @[tile.scala:160:20]
wire [5:0] _lsu_io_dmem_req_bits_0_bits_uop_pc_lob; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_taken; // @[tile.scala:160:20]
wire [19:0] _lsu_io_dmem_req_bits_0_bits_uop_imm_packed; // @[tile.scala:160:20]
wire [11:0] _lsu_io_dmem_req_bits_0_bits_uop_csr_addr; // @[tile.scala:160:20]
wire [6:0] _lsu_io_dmem_req_bits_0_bits_uop_rob_idx; // @[tile.scala:160:20]
wire [4:0] _lsu_io_dmem_req_bits_0_bits_uop_ldq_idx; // @[tile.scala:160:20]
wire [4:0] _lsu_io_dmem_req_bits_0_bits_uop_stq_idx; // @[tile.scala:160:20]
wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_rxq_idx; // @[tile.scala:160:20]
wire [6:0] _lsu_io_dmem_req_bits_0_bits_uop_pdst; // @[tile.scala:160:20]
wire [6:0] _lsu_io_dmem_req_bits_0_bits_uop_prs1; // @[tile.scala:160:20]
wire [6:0] _lsu_io_dmem_req_bits_0_bits_uop_prs2; // @[tile.scala:160:20]
wire [6:0] _lsu_io_dmem_req_bits_0_bits_uop_prs3; // @[tile.scala:160:20]
wire [4:0] _lsu_io_dmem_req_bits_0_bits_uop_ppred; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_prs1_busy; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_prs2_busy; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_prs3_busy; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_ppred_busy; // @[tile.scala:160:20]
wire [6:0] _lsu_io_dmem_req_bits_0_bits_uop_stale_pdst; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_exception; // @[tile.scala:160:20]
wire [63:0] _lsu_io_dmem_req_bits_0_bits_uop_exc_cause; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_bypassable; // @[tile.scala:160:20]
wire [4:0] _lsu_io_dmem_req_bits_0_bits_uop_mem_cmd; // @[tile.scala:160:20]
wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_mem_size; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_mem_signed; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_is_fence; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_is_fencei; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_is_amo; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_uses_ldq; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_uses_stq; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_is_sys_pc2epc; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_is_unique; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_flush_on_commit; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_ldst_is_rs1; // @[tile.scala:160:20]
wire [5:0] _lsu_io_dmem_req_bits_0_bits_uop_ldst; // @[tile.scala:160:20]
wire [5:0] _lsu_io_dmem_req_bits_0_bits_uop_lrs1; // @[tile.scala:160:20]
wire [5:0] _lsu_io_dmem_req_bits_0_bits_uop_lrs2; // @[tile.scala:160:20]
wire [5:0] _lsu_io_dmem_req_bits_0_bits_uop_lrs3; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_ldst_val; // @[tile.scala:160:20]
wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_dst_rtype; // @[tile.scala:160:20]
wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_lrs1_rtype; // @[tile.scala:160:20]
wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_lrs2_rtype; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_frs3_en; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_fp_val; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_fp_single; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_xcpt_pf_if; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_xcpt_ae_if; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_xcpt_ma_if; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_bp_debug_if; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_bp_xcpt_if; // @[tile.scala:160:20]
wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_debug_fsrc; // @[tile.scala:160:20]
wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_debug_tsrc; // @[tile.scala:160:20]
wire [39:0] _lsu_io_dmem_req_bits_0_bits_addr; // @[tile.scala:160:20]
wire [63:0] _lsu_io_dmem_req_bits_0_bits_data; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_is_hella; // @[tile.scala:160:20]
wire _lsu_io_dmem_s1_kill_0; // @[tile.scala:160:20]
wire [15:0] _lsu_io_dmem_brupdate_b1_resolve_mask; // @[tile.scala:160:20]
wire [15:0] _lsu_io_dmem_brupdate_b1_mispredict_mask; // @[tile.scala:160:20]
wire [6:0] _lsu_io_dmem_brupdate_b2_uop_uopc; // @[tile.scala:160:20]
wire [31:0] _lsu_io_dmem_brupdate_b2_uop_inst; // @[tile.scala:160:20]
wire [31:0] _lsu_io_dmem_brupdate_b2_uop_debug_inst; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_is_rvc; // @[tile.scala:160:20]
wire [39:0] _lsu_io_dmem_brupdate_b2_uop_debug_pc; // @[tile.scala:160:20]
wire [2:0] _lsu_io_dmem_brupdate_b2_uop_iq_type; // @[tile.scala:160:20]
wire [9:0] _lsu_io_dmem_brupdate_b2_uop_fu_code; // @[tile.scala:160:20]
wire [3:0] _lsu_io_dmem_brupdate_b2_uop_ctrl_br_type; // @[tile.scala:160:20]
wire [1:0] _lsu_io_dmem_brupdate_b2_uop_ctrl_op1_sel; // @[tile.scala:160:20]
wire [2:0] _lsu_io_dmem_brupdate_b2_uop_ctrl_op2_sel; // @[tile.scala:160:20]
wire [2:0] _lsu_io_dmem_brupdate_b2_uop_ctrl_imm_sel; // @[tile.scala:160:20]
wire [4:0] _lsu_io_dmem_brupdate_b2_uop_ctrl_op_fcn; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_ctrl_fcn_dw; // @[tile.scala:160:20]
wire [2:0] _lsu_io_dmem_brupdate_b2_uop_ctrl_csr_cmd; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_ctrl_is_load; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_ctrl_is_sta; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_ctrl_is_std; // @[tile.scala:160:20]
wire [1:0] _lsu_io_dmem_brupdate_b2_uop_iw_state; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_iw_p1_poisoned; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_iw_p2_poisoned; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_is_br; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_is_jalr; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_is_jal; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_is_sfb; // @[tile.scala:160:20]
wire [15:0] _lsu_io_dmem_brupdate_b2_uop_br_mask; // @[tile.scala:160:20]
wire [3:0] _lsu_io_dmem_brupdate_b2_uop_br_tag; // @[tile.scala:160:20]
wire [4:0] _lsu_io_dmem_brupdate_b2_uop_ftq_idx; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_edge_inst; // @[tile.scala:160:20]
wire [5:0] _lsu_io_dmem_brupdate_b2_uop_pc_lob; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_taken; // @[tile.scala:160:20]
wire [19:0] _lsu_io_dmem_brupdate_b2_uop_imm_packed; // @[tile.scala:160:20]
wire [11:0] _lsu_io_dmem_brupdate_b2_uop_csr_addr; // @[tile.scala:160:20]
wire [6:0] _lsu_io_dmem_brupdate_b2_uop_rob_idx; // @[tile.scala:160:20]
wire [4:0] _lsu_io_dmem_brupdate_b2_uop_ldq_idx; // @[tile.scala:160:20]
wire [4:0] _lsu_io_dmem_brupdate_b2_uop_stq_idx; // @[tile.scala:160:20]
wire [1:0] _lsu_io_dmem_brupdate_b2_uop_rxq_idx; // @[tile.scala:160:20]
wire [6:0] _lsu_io_dmem_brupdate_b2_uop_pdst; // @[tile.scala:160:20]
wire [6:0] _lsu_io_dmem_brupdate_b2_uop_prs1; // @[tile.scala:160:20]
wire [6:0] _lsu_io_dmem_brupdate_b2_uop_prs2; // @[tile.scala:160:20]
wire [6:0] _lsu_io_dmem_brupdate_b2_uop_prs3; // @[tile.scala:160:20]
wire [4:0] _lsu_io_dmem_brupdate_b2_uop_ppred; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_prs1_busy; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_prs2_busy; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_prs3_busy; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_ppred_busy; // @[tile.scala:160:20]
wire [6:0] _lsu_io_dmem_brupdate_b2_uop_stale_pdst; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_exception; // @[tile.scala:160:20]
wire [63:0] _lsu_io_dmem_brupdate_b2_uop_exc_cause; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_bypassable; // @[tile.scala:160:20]
wire [4:0] _lsu_io_dmem_brupdate_b2_uop_mem_cmd; // @[tile.scala:160:20]
wire [1:0] _lsu_io_dmem_brupdate_b2_uop_mem_size; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_mem_signed; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_is_fence; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_is_fencei; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_is_amo; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_uses_ldq; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_uses_stq; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_is_sys_pc2epc; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_is_unique; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_flush_on_commit; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_ldst_is_rs1; // @[tile.scala:160:20]
wire [5:0] _lsu_io_dmem_brupdate_b2_uop_ldst; // @[tile.scala:160:20]
wire [5:0] _lsu_io_dmem_brupdate_b2_uop_lrs1; // @[tile.scala:160:20]
wire [5:0] _lsu_io_dmem_brupdate_b2_uop_lrs2; // @[tile.scala:160:20]
wire [5:0] _lsu_io_dmem_brupdate_b2_uop_lrs3; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_ldst_val; // @[tile.scala:160:20]
wire [1:0] _lsu_io_dmem_brupdate_b2_uop_dst_rtype; // @[tile.scala:160:20]
wire [1:0] _lsu_io_dmem_brupdate_b2_uop_lrs1_rtype; // @[tile.scala:160:20]
wire [1:0] _lsu_io_dmem_brupdate_b2_uop_lrs2_rtype; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_frs3_en; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_fp_val; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_fp_single; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_xcpt_pf_if; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_xcpt_ae_if; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_xcpt_ma_if; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_bp_debug_if; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_bp_xcpt_if; // @[tile.scala:160:20]
wire [1:0] _lsu_io_dmem_brupdate_b2_uop_debug_fsrc; // @[tile.scala:160:20]
wire [1:0] _lsu_io_dmem_brupdate_b2_uop_debug_tsrc; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_valid; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_mispredict; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_taken; // @[tile.scala:160:20]
wire [2:0] _lsu_io_dmem_brupdate_b2_cfi_type; // @[tile.scala:160:20]
wire [1:0] _lsu_io_dmem_brupdate_b2_pc_sel; // @[tile.scala:160:20]
wire [39:0] _lsu_io_dmem_brupdate_b2_jalr_target; // @[tile.scala:160:20]
wire [20:0] _lsu_io_dmem_brupdate_b2_target_offset; // @[tile.scala:160:20]
wire _lsu_io_dmem_exception; // @[tile.scala:160:20]
wire [6:0] _lsu_io_dmem_rob_pnr_idx; // @[tile.scala:160:20]
wire [6:0] _lsu_io_dmem_rob_head_idx; // @[tile.scala:160:20]
wire _lsu_io_dmem_release_ready; // @[tile.scala:160:20]
wire _lsu_io_dmem_force_order; // @[tile.scala:160:20]
wire _lsu_io_hellacache_req_ready; // @[tile.scala:160:20]
wire _lsu_io_hellacache_s2_nack; // @[tile.scala:160:20]
wire _lsu_io_hellacache_resp_valid; // @[tile.scala:160:20]
wire [39:0] _lsu_io_hellacache_resp_bits_addr; // @[tile.scala:160:20]
wire [63:0] _lsu_io_hellacache_resp_bits_data; // @[tile.scala:160:20]
wire _lsu_io_hellacache_s2_xcpt_ma_ld; // @[tile.scala:160:20]
wire _lsu_io_hellacache_s2_xcpt_ma_st; // @[tile.scala:160:20]
wire _lsu_io_hellacache_s2_xcpt_pf_ld; // @[tile.scala:160:20]
wire _lsu_io_hellacache_s2_xcpt_pf_st; // @[tile.scala:160:20]
wire _lsu_io_hellacache_s2_xcpt_gf_ld; // @[tile.scala:160:20]
wire _lsu_io_hellacache_s2_xcpt_gf_st; // @[tile.scala:160:20]
wire _lsu_io_hellacache_s2_xcpt_ae_ld; // @[tile.scala:160:20]
wire _lsu_io_hellacache_s2_xcpt_ae_st; // @[tile.scala:160:20]
wire _lsu_io_hellacache_store_pending; // @[tile.scala:160:20]
wire _core_io_ifu_fetchpacket_ready; // @[tile.scala:159:20]
wire [4:0] _core_io_ifu_get_pc_0_ftq_idx; // @[tile.scala:159:20]
wire [4:0] _core_io_ifu_get_pc_1_ftq_idx; // @[tile.scala:159:20]
wire _core_io_ifu_status_debug; // @[tile.scala:159:20]
wire _core_io_ifu_status_cease; // @[tile.scala:159:20]
wire _core_io_ifu_status_wfi; // @[tile.scala:159:20]
wire [1:0] _core_io_ifu_status_dprv; // @[tile.scala:159:20]
wire _core_io_ifu_status_dv; // @[tile.scala:159:20]
wire [1:0] _core_io_ifu_status_prv; // @[tile.scala:159:20]
wire _core_io_ifu_status_v; // @[tile.scala:159:20]
wire _core_io_ifu_status_sd; // @[tile.scala:159:20]
wire _core_io_ifu_status_mpv; // @[tile.scala:159:20]
wire _core_io_ifu_status_gva; // @[tile.scala:159:20]
wire _core_io_ifu_status_tsr; // @[tile.scala:159:20]
wire _core_io_ifu_status_tw; // @[tile.scala:159:20]
wire _core_io_ifu_status_tvm; // @[tile.scala:159:20]
wire _core_io_ifu_status_mxr; // @[tile.scala:159:20]
wire _core_io_ifu_status_sum; // @[tile.scala:159:20]
wire _core_io_ifu_status_mprv; // @[tile.scala:159:20]
wire [1:0] _core_io_ifu_status_fs; // @[tile.scala:159:20]
wire [1:0] _core_io_ifu_status_mpp; // @[tile.scala:159:20]
wire _core_io_ifu_status_spp; // @[tile.scala:159:20]
wire _core_io_ifu_status_mpie; // @[tile.scala:159:20]
wire _core_io_ifu_status_spie; // @[tile.scala:159:20]
wire _core_io_ifu_status_mie; // @[tile.scala:159:20]
wire _core_io_ifu_status_sie; // @[tile.scala:159:20]
wire _core_io_ifu_sfence_valid; // @[tile.scala:159:20]
wire _core_io_ifu_sfence_bits_rs1; // @[tile.scala:159:20]
wire _core_io_ifu_sfence_bits_rs2; // @[tile.scala:159:20]
wire [38:0] _core_io_ifu_sfence_bits_addr; // @[tile.scala:159:20]
wire _core_io_ifu_sfence_bits_asid; // @[tile.scala:159:20]
wire [15:0] _core_io_ifu_brupdate_b1_resolve_mask; // @[tile.scala:159:20]
wire [15:0] _core_io_ifu_brupdate_b1_mispredict_mask; // @[tile.scala:159:20]
wire [6:0] _core_io_ifu_brupdate_b2_uop_uopc; // @[tile.scala:159:20]
wire [31:0] _core_io_ifu_brupdate_b2_uop_inst; // @[tile.scala:159:20]
wire [31:0] _core_io_ifu_brupdate_b2_uop_debug_inst; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_is_rvc; // @[tile.scala:159:20]
wire [39:0] _core_io_ifu_brupdate_b2_uop_debug_pc; // @[tile.scala:159:20]
wire [2:0] _core_io_ifu_brupdate_b2_uop_iq_type; // @[tile.scala:159:20]
wire [9:0] _core_io_ifu_brupdate_b2_uop_fu_code; // @[tile.scala:159:20]
wire [3:0] _core_io_ifu_brupdate_b2_uop_ctrl_br_type; // @[tile.scala:159:20]
wire [1:0] _core_io_ifu_brupdate_b2_uop_ctrl_op1_sel; // @[tile.scala:159:20]
wire [2:0] _core_io_ifu_brupdate_b2_uop_ctrl_op2_sel; // @[tile.scala:159:20]
wire [2:0] _core_io_ifu_brupdate_b2_uop_ctrl_imm_sel; // @[tile.scala:159:20]
wire [4:0] _core_io_ifu_brupdate_b2_uop_ctrl_op_fcn; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_ctrl_fcn_dw; // @[tile.scala:159:20]
wire [2:0] _core_io_ifu_brupdate_b2_uop_ctrl_csr_cmd; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_ctrl_is_load; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_ctrl_is_sta; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_ctrl_is_std; // @[tile.scala:159:20]
wire [1:0] _core_io_ifu_brupdate_b2_uop_iw_state; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_iw_p1_poisoned; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_iw_p2_poisoned; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_is_br; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_is_jalr; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_is_jal; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_is_sfb; // @[tile.scala:159:20]
wire [15:0] _core_io_ifu_brupdate_b2_uop_br_mask; // @[tile.scala:159:20]
wire [3:0] _core_io_ifu_brupdate_b2_uop_br_tag; // @[tile.scala:159:20]
wire [4:0] _core_io_ifu_brupdate_b2_uop_ftq_idx; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_edge_inst; // @[tile.scala:159:20]
wire [5:0] _core_io_ifu_brupdate_b2_uop_pc_lob; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_taken; // @[tile.scala:159:20]
wire [19:0] _core_io_ifu_brupdate_b2_uop_imm_packed; // @[tile.scala:159:20]
wire [11:0] _core_io_ifu_brupdate_b2_uop_csr_addr; // @[tile.scala:159:20]
wire [6:0] _core_io_ifu_brupdate_b2_uop_rob_idx; // @[tile.scala:159:20]
wire [4:0] _core_io_ifu_brupdate_b2_uop_ldq_idx; // @[tile.scala:159:20]
wire [4:0] _core_io_ifu_brupdate_b2_uop_stq_idx; // @[tile.scala:159:20]
wire [1:0] _core_io_ifu_brupdate_b2_uop_rxq_idx; // @[tile.scala:159:20]
wire [6:0] _core_io_ifu_brupdate_b2_uop_pdst; // @[tile.scala:159:20]
wire [6:0] _core_io_ifu_brupdate_b2_uop_prs1; // @[tile.scala:159:20]
wire [6:0] _core_io_ifu_brupdate_b2_uop_prs2; // @[tile.scala:159:20]
wire [6:0] _core_io_ifu_brupdate_b2_uop_prs3; // @[tile.scala:159:20]
wire [4:0] _core_io_ifu_brupdate_b2_uop_ppred; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_prs1_busy; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_prs2_busy; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_prs3_busy; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_ppred_busy; // @[tile.scala:159:20]
wire [6:0] _core_io_ifu_brupdate_b2_uop_stale_pdst; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_exception; // @[tile.scala:159:20]
wire [63:0] _core_io_ifu_brupdate_b2_uop_exc_cause; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_bypassable; // @[tile.scala:159:20]
wire [4:0] _core_io_ifu_brupdate_b2_uop_mem_cmd; // @[tile.scala:159:20]
wire [1:0] _core_io_ifu_brupdate_b2_uop_mem_size; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_mem_signed; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_is_fence; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_is_fencei; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_is_amo; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_uses_ldq; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_uses_stq; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_is_sys_pc2epc; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_is_unique; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_flush_on_commit; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_ldst_is_rs1; // @[tile.scala:159:20]
wire [5:0] _core_io_ifu_brupdate_b2_uop_ldst; // @[tile.scala:159:20]
wire [5:0] _core_io_ifu_brupdate_b2_uop_lrs1; // @[tile.scala:159:20]
wire [5:0] _core_io_ifu_brupdate_b2_uop_lrs2; // @[tile.scala:159:20]
wire [5:0] _core_io_ifu_brupdate_b2_uop_lrs3; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_ldst_val; // @[tile.scala:159:20]
wire [1:0] _core_io_ifu_brupdate_b2_uop_dst_rtype; // @[tile.scala:159:20]
wire [1:0] _core_io_ifu_brupdate_b2_uop_lrs1_rtype; // @[tile.scala:159:20]
wire [1:0] _core_io_ifu_brupdate_b2_uop_lrs2_rtype; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_frs3_en; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_fp_val; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_fp_single; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_xcpt_pf_if; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_xcpt_ae_if; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_xcpt_ma_if; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_bp_debug_if; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_bp_xcpt_if; // @[tile.scala:159:20]
wire [1:0] _core_io_ifu_brupdate_b2_uop_debug_fsrc; // @[tile.scala:159:20]
wire [1:0] _core_io_ifu_brupdate_b2_uop_debug_tsrc; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_valid; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_mispredict; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_taken; // @[tile.scala:159:20]
wire [2:0] _core_io_ifu_brupdate_b2_cfi_type; // @[tile.scala:159:20]
wire [1:0] _core_io_ifu_brupdate_b2_pc_sel; // @[tile.scala:159:20]
wire [39:0] _core_io_ifu_brupdate_b2_jalr_target; // @[tile.scala:159:20]
wire [20:0] _core_io_ifu_brupdate_b2_target_offset; // @[tile.scala:159:20]
wire _core_io_ifu_redirect_flush; // @[tile.scala:159:20]
wire _core_io_ifu_redirect_val; // @[tile.scala:159:20]
wire [39:0] _core_io_ifu_redirect_pc; // @[tile.scala:159:20]
wire [4:0] _core_io_ifu_redirect_ftq_idx; // @[tile.scala:159:20]
wire [63:0] _core_io_ifu_redirect_ghist_old_history; // @[tile.scala:159:20]
wire _core_io_ifu_redirect_ghist_current_saw_branch_not_taken; // @[tile.scala:159:20]
wire _core_io_ifu_redirect_ghist_new_saw_branch_not_taken; // @[tile.scala:159:20]
wire _core_io_ifu_redirect_ghist_new_saw_branch_taken; // @[tile.scala:159:20]
wire [4:0] _core_io_ifu_redirect_ghist_ras_idx; // @[tile.scala:159:20]
wire _core_io_ifu_commit_valid; // @[tile.scala:159:20]
wire [31:0] _core_io_ifu_commit_bits; // @[tile.scala:159:20]
wire _core_io_ifu_flush_icache; // @[tile.scala:159:20]
wire [3:0] _core_io_ptw_ptbr_mode; // @[tile.scala:159:20]
wire [43:0] _core_io_ptw_ptbr_ppn; // @[tile.scala:159:20]
wire _core_io_ptw_sfence_valid; // @[tile.scala:159:20]
wire _core_io_ptw_sfence_bits_rs1; // @[tile.scala:159:20]
wire _core_io_ptw_sfence_bits_rs2; // @[tile.scala:159:20]
wire [38:0] _core_io_ptw_sfence_bits_addr; // @[tile.scala:159:20]
wire _core_io_ptw_sfence_bits_asid; // @[tile.scala:159:20]
wire _core_io_ptw_status_debug; // @[tile.scala:159:20]
wire _core_io_ptw_status_cease; // @[tile.scala:159:20]
wire _core_io_ptw_status_wfi; // @[tile.scala:159:20]
wire [1:0] _core_io_ptw_status_dprv; // @[tile.scala:159:20]
wire _core_io_ptw_status_dv; // @[tile.scala:159:20]
wire [1:0] _core_io_ptw_status_prv; // @[tile.scala:159:20]
wire _core_io_ptw_status_v; // @[tile.scala:159:20]
wire _core_io_ptw_status_sd; // @[tile.scala:159:20]
wire _core_io_ptw_status_mpv; // @[tile.scala:159:20]
wire _core_io_ptw_status_gva; // @[tile.scala:159:20]
wire _core_io_ptw_status_tsr; // @[tile.scala:159:20]
wire _core_io_ptw_status_tw; // @[tile.scala:159:20]
wire _core_io_ptw_status_tvm; // @[tile.scala:159:20]
wire _core_io_ptw_status_mxr; // @[tile.scala:159:20]
wire _core_io_ptw_status_sum; // @[tile.scala:159:20]
wire _core_io_ptw_status_mprv; // @[tile.scala:159:20]
wire [1:0] _core_io_ptw_status_fs; // @[tile.scala:159:20]
wire [1:0] _core_io_ptw_status_mpp; // @[tile.scala:159:20]
wire _core_io_ptw_status_spp; // @[tile.scala:159:20]
wire _core_io_ptw_status_mpie; // @[tile.scala:159:20]
wire _core_io_ptw_status_spie; // @[tile.scala:159:20]
wire _core_io_ptw_status_mie; // @[tile.scala:159:20]
wire _core_io_ptw_status_sie; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_0_cfg_l; // @[tile.scala:159:20]
wire [1:0] _core_io_ptw_pmp_0_cfg_a; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_0_cfg_x; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_0_cfg_w; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_0_cfg_r; // @[tile.scala:159:20]
wire [29:0] _core_io_ptw_pmp_0_addr; // @[tile.scala:159:20]
wire [31:0] _core_io_ptw_pmp_0_mask; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_1_cfg_l; // @[tile.scala:159:20]
wire [1:0] _core_io_ptw_pmp_1_cfg_a; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_1_cfg_x; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_1_cfg_w; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_1_cfg_r; // @[tile.scala:159:20]
wire [29:0] _core_io_ptw_pmp_1_addr; // @[tile.scala:159:20]
wire [31:0] _core_io_ptw_pmp_1_mask; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_2_cfg_l; // @[tile.scala:159:20]
wire [1:0] _core_io_ptw_pmp_2_cfg_a; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_2_cfg_x; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_2_cfg_w; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_2_cfg_r; // @[tile.scala:159:20]
wire [29:0] _core_io_ptw_pmp_2_addr; // @[tile.scala:159:20]
wire [31:0] _core_io_ptw_pmp_2_mask; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_3_cfg_l; // @[tile.scala:159:20]
wire [1:0] _core_io_ptw_pmp_3_cfg_a; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_3_cfg_x; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_3_cfg_w; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_3_cfg_r; // @[tile.scala:159:20]
wire [29:0] _core_io_ptw_pmp_3_addr; // @[tile.scala:159:20]
wire [31:0] _core_io_ptw_pmp_3_mask; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_4_cfg_l; // @[tile.scala:159:20]
wire [1:0] _core_io_ptw_pmp_4_cfg_a; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_4_cfg_x; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_4_cfg_w; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_4_cfg_r; // @[tile.scala:159:20]
wire [29:0] _core_io_ptw_pmp_4_addr; // @[tile.scala:159:20]
wire [31:0] _core_io_ptw_pmp_4_mask; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_5_cfg_l; // @[tile.scala:159:20]
wire [1:0] _core_io_ptw_pmp_5_cfg_a; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_5_cfg_x; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_5_cfg_w; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_5_cfg_r; // @[tile.scala:159:20]
wire [29:0] _core_io_ptw_pmp_5_addr; // @[tile.scala:159:20]
wire [31:0] _core_io_ptw_pmp_5_mask; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_6_cfg_l; // @[tile.scala:159:20]
wire [1:0] _core_io_ptw_pmp_6_cfg_a; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_6_cfg_x; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_6_cfg_w; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_6_cfg_r; // @[tile.scala:159:20]
wire [29:0] _core_io_ptw_pmp_6_addr; // @[tile.scala:159:20]
wire [31:0] _core_io_ptw_pmp_6_mask; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_7_cfg_l; // @[tile.scala:159:20]
wire [1:0] _core_io_ptw_pmp_7_cfg_a; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_7_cfg_x; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_7_cfg_w; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_7_cfg_r; // @[tile.scala:159:20]
wire [29:0] _core_io_ptw_pmp_7_addr; // @[tile.scala:159:20]
wire [31:0] _core_io_ptw_pmp_7_mask; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_valid; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_exe_0_req_bits_uop_uopc; // @[tile.scala:159:20]
wire [31:0] _core_io_lsu_exe_0_req_bits_uop_inst; // @[tile.scala:159:20]
wire [31:0] _core_io_lsu_exe_0_req_bits_uop_debug_inst; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_is_rvc; // @[tile.scala:159:20]
wire [39:0] _core_io_lsu_exe_0_req_bits_uop_debug_pc; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_exe_0_req_bits_uop_iq_type; // @[tile.scala:159:20]
wire [9:0] _core_io_lsu_exe_0_req_bits_uop_fu_code; // @[tile.scala:159:20]
wire [3:0] _core_io_lsu_exe_0_req_bits_uop_ctrl_br_type; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_exe_0_req_bits_uop_ctrl_op1_sel; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_exe_0_req_bits_uop_ctrl_op2_sel; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_exe_0_req_bits_uop_ctrl_imm_sel; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_exe_0_req_bits_uop_ctrl_op_fcn; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_ctrl_fcn_dw; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_exe_0_req_bits_uop_ctrl_csr_cmd; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_ctrl_is_load; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_ctrl_is_sta; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_ctrl_is_std; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_exe_0_req_bits_uop_iw_state; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_iw_p1_poisoned; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_iw_p2_poisoned; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_is_br; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_is_jalr; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_is_jal; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_is_sfb; // @[tile.scala:159:20]
wire [15:0] _core_io_lsu_exe_0_req_bits_uop_br_mask; // @[tile.scala:159:20]
wire [3:0] _core_io_lsu_exe_0_req_bits_uop_br_tag; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_exe_0_req_bits_uop_ftq_idx; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_edge_inst; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_exe_0_req_bits_uop_pc_lob; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_taken; // @[tile.scala:159:20]
wire [19:0] _core_io_lsu_exe_0_req_bits_uop_imm_packed; // @[tile.scala:159:20]
wire [11:0] _core_io_lsu_exe_0_req_bits_uop_csr_addr; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_exe_0_req_bits_uop_rob_idx; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_exe_0_req_bits_uop_ldq_idx; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_exe_0_req_bits_uop_stq_idx; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_exe_0_req_bits_uop_rxq_idx; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_exe_0_req_bits_uop_pdst; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_exe_0_req_bits_uop_prs1; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_exe_0_req_bits_uop_prs2; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_exe_0_req_bits_uop_prs3; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_exe_0_req_bits_uop_ppred; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_prs1_busy; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_prs2_busy; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_prs3_busy; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_ppred_busy; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_exe_0_req_bits_uop_stale_pdst; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_exception; // @[tile.scala:159:20]
wire [63:0] _core_io_lsu_exe_0_req_bits_uop_exc_cause; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_bypassable; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_exe_0_req_bits_uop_mem_cmd; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_exe_0_req_bits_uop_mem_size; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_mem_signed; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_is_fence; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_is_fencei; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_is_amo; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_uses_ldq; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_uses_stq; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_is_sys_pc2epc; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_is_unique; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_flush_on_commit; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_ldst_is_rs1; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_exe_0_req_bits_uop_ldst; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_exe_0_req_bits_uop_lrs1; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_exe_0_req_bits_uop_lrs2; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_exe_0_req_bits_uop_lrs3; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_ldst_val; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_exe_0_req_bits_uop_dst_rtype; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_exe_0_req_bits_uop_lrs1_rtype; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_exe_0_req_bits_uop_lrs2_rtype; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_frs3_en; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_fp_val; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_fp_single; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_xcpt_pf_if; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_xcpt_ae_if; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_xcpt_ma_if; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_bp_debug_if; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_bp_xcpt_if; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_exe_0_req_bits_uop_debug_fsrc; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_exe_0_req_bits_uop_debug_tsrc; // @[tile.scala:159:20]
wire [63:0] _core_io_lsu_exe_0_req_bits_data; // @[tile.scala:159:20]
wire [39:0] _core_io_lsu_exe_0_req_bits_addr; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_mxcpt_valid; // @[tile.scala:159:20]
wire [24:0] _core_io_lsu_exe_0_req_bits_mxcpt_bits; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_sfence_valid; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_sfence_bits_rs1; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_sfence_bits_rs2; // @[tile.scala:159:20]
wire [38:0] _core_io_lsu_exe_0_req_bits_sfence_bits_addr; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_sfence_bits_asid; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_valid; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_dis_uops_0_bits_uopc; // @[tile.scala:159:20]
wire [31:0] _core_io_lsu_dis_uops_0_bits_inst; // @[tile.scala:159:20]
wire [31:0] _core_io_lsu_dis_uops_0_bits_debug_inst; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_is_rvc; // @[tile.scala:159:20]
wire [39:0] _core_io_lsu_dis_uops_0_bits_debug_pc; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_dis_uops_0_bits_iq_type; // @[tile.scala:159:20]
wire [9:0] _core_io_lsu_dis_uops_0_bits_fu_code; // @[tile.scala:159:20]
wire [3:0] _core_io_lsu_dis_uops_0_bits_ctrl_br_type; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_0_bits_ctrl_op1_sel; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_dis_uops_0_bits_ctrl_op2_sel; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_dis_uops_0_bits_ctrl_imm_sel; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_dis_uops_0_bits_ctrl_op_fcn; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_ctrl_fcn_dw; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_dis_uops_0_bits_ctrl_csr_cmd; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_ctrl_is_load; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_ctrl_is_sta; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_ctrl_is_std; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_0_bits_iw_state; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_iw_p1_poisoned; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_iw_p2_poisoned; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_is_br; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_is_jalr; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_is_jal; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_is_sfb; // @[tile.scala:159:20]
wire [15:0] _core_io_lsu_dis_uops_0_bits_br_mask; // @[tile.scala:159:20]
wire [3:0] _core_io_lsu_dis_uops_0_bits_br_tag; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_dis_uops_0_bits_ftq_idx; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_edge_inst; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_dis_uops_0_bits_pc_lob; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_taken; // @[tile.scala:159:20]
wire [19:0] _core_io_lsu_dis_uops_0_bits_imm_packed; // @[tile.scala:159:20]
wire [11:0] _core_io_lsu_dis_uops_0_bits_csr_addr; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_dis_uops_0_bits_rob_idx; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_dis_uops_0_bits_ldq_idx; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_dis_uops_0_bits_stq_idx; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_0_bits_rxq_idx; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_dis_uops_0_bits_pdst; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_dis_uops_0_bits_prs1; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_dis_uops_0_bits_prs2; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_dis_uops_0_bits_prs3; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_prs1_busy; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_prs2_busy; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_prs3_busy; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_dis_uops_0_bits_stale_pdst; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_exception; // @[tile.scala:159:20]
wire [63:0] _core_io_lsu_dis_uops_0_bits_exc_cause; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_bypassable; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_dis_uops_0_bits_mem_cmd; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_0_bits_mem_size; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_mem_signed; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_is_fence; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_is_fencei; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_is_amo; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_uses_ldq; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_uses_stq; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_is_sys_pc2epc; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_is_unique; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_flush_on_commit; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_ldst_is_rs1; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_dis_uops_0_bits_ldst; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_dis_uops_0_bits_lrs1; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_dis_uops_0_bits_lrs2; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_dis_uops_0_bits_lrs3; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_ldst_val; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_0_bits_dst_rtype; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_0_bits_lrs1_rtype; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_0_bits_lrs2_rtype; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_frs3_en; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_fp_val; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_fp_single; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_xcpt_pf_if; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_xcpt_ae_if; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_xcpt_ma_if; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_bp_debug_if; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_bp_xcpt_if; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_0_bits_debug_fsrc; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_0_bits_debug_tsrc; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_valid; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_dis_uops_1_bits_uopc; // @[tile.scala:159:20]
wire [31:0] _core_io_lsu_dis_uops_1_bits_inst; // @[tile.scala:159:20]
wire [31:0] _core_io_lsu_dis_uops_1_bits_debug_inst; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_is_rvc; // @[tile.scala:159:20]
wire [39:0] _core_io_lsu_dis_uops_1_bits_debug_pc; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_dis_uops_1_bits_iq_type; // @[tile.scala:159:20]
wire [9:0] _core_io_lsu_dis_uops_1_bits_fu_code; // @[tile.scala:159:20]
wire [3:0] _core_io_lsu_dis_uops_1_bits_ctrl_br_type; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_1_bits_ctrl_op1_sel; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_dis_uops_1_bits_ctrl_op2_sel; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_dis_uops_1_bits_ctrl_imm_sel; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_dis_uops_1_bits_ctrl_op_fcn; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_ctrl_fcn_dw; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_dis_uops_1_bits_ctrl_csr_cmd; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_ctrl_is_load; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_ctrl_is_sta; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_ctrl_is_std; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_1_bits_iw_state; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_iw_p1_poisoned; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_iw_p2_poisoned; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_is_br; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_is_jalr; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_is_jal; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_is_sfb; // @[tile.scala:159:20]
wire [15:0] _core_io_lsu_dis_uops_1_bits_br_mask; // @[tile.scala:159:20]
wire [3:0] _core_io_lsu_dis_uops_1_bits_br_tag; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_dis_uops_1_bits_ftq_idx; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_edge_inst; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_dis_uops_1_bits_pc_lob; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_taken; // @[tile.scala:159:20]
wire [19:0] _core_io_lsu_dis_uops_1_bits_imm_packed; // @[tile.scala:159:20]
wire [11:0] _core_io_lsu_dis_uops_1_bits_csr_addr; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_dis_uops_1_bits_rob_idx; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_dis_uops_1_bits_ldq_idx; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_dis_uops_1_bits_stq_idx; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_1_bits_rxq_idx; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_dis_uops_1_bits_pdst; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_dis_uops_1_bits_prs1; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_dis_uops_1_bits_prs2; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_dis_uops_1_bits_prs3; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_prs1_busy; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_prs2_busy; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_prs3_busy; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_dis_uops_1_bits_stale_pdst; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_exception; // @[tile.scala:159:20]
wire [63:0] _core_io_lsu_dis_uops_1_bits_exc_cause; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_bypassable; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_dis_uops_1_bits_mem_cmd; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_1_bits_mem_size; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_mem_signed; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_is_fence; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_is_fencei; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_is_amo; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_uses_ldq; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_uses_stq; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_is_sys_pc2epc; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_is_unique; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_flush_on_commit; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_ldst_is_rs1; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_dis_uops_1_bits_ldst; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_dis_uops_1_bits_lrs1; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_dis_uops_1_bits_lrs2; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_dis_uops_1_bits_lrs3; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_ldst_val; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_1_bits_dst_rtype; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_1_bits_lrs1_rtype; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_1_bits_lrs2_rtype; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_frs3_en; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_fp_val; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_fp_single; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_xcpt_pf_if; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_xcpt_ae_if; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_xcpt_ma_if; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_bp_debug_if; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_bp_xcpt_if; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_1_bits_debug_fsrc; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_1_bits_debug_tsrc; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_valid; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_dis_uops_2_bits_uopc; // @[tile.scala:159:20]
wire [31:0] _core_io_lsu_dis_uops_2_bits_inst; // @[tile.scala:159:20]
wire [31:0] _core_io_lsu_dis_uops_2_bits_debug_inst; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_is_rvc; // @[tile.scala:159:20]
wire [39:0] _core_io_lsu_dis_uops_2_bits_debug_pc; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_dis_uops_2_bits_iq_type; // @[tile.scala:159:20]
wire [9:0] _core_io_lsu_dis_uops_2_bits_fu_code; // @[tile.scala:159:20]
wire [3:0] _core_io_lsu_dis_uops_2_bits_ctrl_br_type; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_2_bits_ctrl_op1_sel; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_dis_uops_2_bits_ctrl_op2_sel; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_dis_uops_2_bits_ctrl_imm_sel; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_dis_uops_2_bits_ctrl_op_fcn; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_ctrl_fcn_dw; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_dis_uops_2_bits_ctrl_csr_cmd; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_ctrl_is_load; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_ctrl_is_sta; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_ctrl_is_std; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_2_bits_iw_state; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_iw_p1_poisoned; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_iw_p2_poisoned; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_is_br; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_is_jalr; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_is_jal; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_is_sfb; // @[tile.scala:159:20]
wire [15:0] _core_io_lsu_dis_uops_2_bits_br_mask; // @[tile.scala:159:20]
wire [3:0] _core_io_lsu_dis_uops_2_bits_br_tag; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_dis_uops_2_bits_ftq_idx; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_edge_inst; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_dis_uops_2_bits_pc_lob; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_taken; // @[tile.scala:159:20]
wire [19:0] _core_io_lsu_dis_uops_2_bits_imm_packed; // @[tile.scala:159:20]
wire [11:0] _core_io_lsu_dis_uops_2_bits_csr_addr; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_dis_uops_2_bits_rob_idx; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_dis_uops_2_bits_ldq_idx; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_dis_uops_2_bits_stq_idx; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_2_bits_rxq_idx; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_dis_uops_2_bits_pdst; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_dis_uops_2_bits_prs1; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_dis_uops_2_bits_prs2; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_dis_uops_2_bits_prs3; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_prs1_busy; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_prs2_busy; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_prs3_busy; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_dis_uops_2_bits_stale_pdst; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_exception; // @[tile.scala:159:20]
wire [63:0] _core_io_lsu_dis_uops_2_bits_exc_cause; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_bypassable; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_dis_uops_2_bits_mem_cmd; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_2_bits_mem_size; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_mem_signed; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_is_fence; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_is_fencei; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_is_amo; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_uses_ldq; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_uses_stq; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_is_sys_pc2epc; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_is_unique; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_flush_on_commit; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_ldst_is_rs1; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_dis_uops_2_bits_ldst; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_dis_uops_2_bits_lrs1; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_dis_uops_2_bits_lrs2; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_dis_uops_2_bits_lrs3; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_ldst_val; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_2_bits_dst_rtype; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_2_bits_lrs1_rtype; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_2_bits_lrs2_rtype; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_frs3_en; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_fp_val; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_fp_single; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_xcpt_pf_if; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_xcpt_ae_if; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_xcpt_ma_if; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_bp_debug_if; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_bp_xcpt_if; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_2_bits_debug_fsrc; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_2_bits_debug_tsrc; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_valid; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_fp_stdata_bits_uop_uopc; // @[tile.scala:159:20]
wire [31:0] _core_io_lsu_fp_stdata_bits_uop_inst; // @[tile.scala:159:20]
wire [31:0] _core_io_lsu_fp_stdata_bits_uop_debug_inst; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_is_rvc; // @[tile.scala:159:20]
wire [39:0] _core_io_lsu_fp_stdata_bits_uop_debug_pc; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_fp_stdata_bits_uop_iq_type; // @[tile.scala:159:20]
wire [9:0] _core_io_lsu_fp_stdata_bits_uop_fu_code; // @[tile.scala:159:20]
wire [3:0] _core_io_lsu_fp_stdata_bits_uop_ctrl_br_type; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_fp_stdata_bits_uop_ctrl_op1_sel; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_fp_stdata_bits_uop_ctrl_op2_sel; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_fp_stdata_bits_uop_ctrl_imm_sel; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_fp_stdata_bits_uop_ctrl_op_fcn; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_ctrl_fcn_dw; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_fp_stdata_bits_uop_ctrl_csr_cmd; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_ctrl_is_load; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_ctrl_is_sta; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_ctrl_is_std; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_fp_stdata_bits_uop_iw_state; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_iw_p1_poisoned; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_iw_p2_poisoned; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_is_br; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_is_jalr; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_is_jal; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_is_sfb; // @[tile.scala:159:20]
wire [15:0] _core_io_lsu_fp_stdata_bits_uop_br_mask; // @[tile.scala:159:20]
wire [3:0] _core_io_lsu_fp_stdata_bits_uop_br_tag; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_fp_stdata_bits_uop_ftq_idx; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_edge_inst; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_fp_stdata_bits_uop_pc_lob; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_taken; // @[tile.scala:159:20]
wire [19:0] _core_io_lsu_fp_stdata_bits_uop_imm_packed; // @[tile.scala:159:20]
wire [11:0] _core_io_lsu_fp_stdata_bits_uop_csr_addr; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_fp_stdata_bits_uop_rob_idx; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_fp_stdata_bits_uop_ldq_idx; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_fp_stdata_bits_uop_stq_idx; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_fp_stdata_bits_uop_rxq_idx; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_fp_stdata_bits_uop_pdst; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_fp_stdata_bits_uop_prs1; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_fp_stdata_bits_uop_prs2; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_fp_stdata_bits_uop_prs3; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_fp_stdata_bits_uop_ppred; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_prs1_busy; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_prs2_busy; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_prs3_busy; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_ppred_busy; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_fp_stdata_bits_uop_stale_pdst; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_exception; // @[tile.scala:159:20]
wire [63:0] _core_io_lsu_fp_stdata_bits_uop_exc_cause; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_bypassable; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_fp_stdata_bits_uop_mem_cmd; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_fp_stdata_bits_uop_mem_size; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_mem_signed; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_is_fence; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_is_fencei; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_is_amo; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_uses_ldq; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_uses_stq; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_is_sys_pc2epc; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_is_unique; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_flush_on_commit; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_ldst_is_rs1; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_fp_stdata_bits_uop_ldst; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_fp_stdata_bits_uop_lrs1; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_fp_stdata_bits_uop_lrs2; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_fp_stdata_bits_uop_lrs3; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_ldst_val; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_fp_stdata_bits_uop_dst_rtype; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_fp_stdata_bits_uop_lrs1_rtype; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_fp_stdata_bits_uop_lrs2_rtype; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_frs3_en; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_fp_val; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_fp_single; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_xcpt_pf_if; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_xcpt_ae_if; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_xcpt_ma_if; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_bp_debug_if; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_bp_xcpt_if; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_fp_stdata_bits_uop_debug_fsrc; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_fp_stdata_bits_uop_debug_tsrc; // @[tile.scala:159:20]
wire [63:0] _core_io_lsu_fp_stdata_bits_data; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_predicated; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_valid; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_uopc; // @[tile.scala:159:20]
wire [31:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_inst; // @[tile.scala:159:20]
wire [31:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_debug_inst; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_rvc; // @[tile.scala:159:20]
wire [39:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_debug_pc; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_iq_type; // @[tile.scala:159:20]
wire [9:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_fu_code; // @[tile.scala:159:20]
wire [3:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_br_type; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op1_sel; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op2_sel; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_imm_sel; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op_fcn; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_fcn_dw; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_csr_cmd; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_load; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_sta; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_std; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_iw_state; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_iw_p1_poisoned; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_iw_p2_poisoned; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_br; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_jalr; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_jal; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_sfb; // @[tile.scala:159:20]
wire [15:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_br_mask; // @[tile.scala:159:20]
wire [3:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_br_tag; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_ftq_idx; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_edge_inst; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_pc_lob; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_taken; // @[tile.scala:159:20]
wire [19:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_imm_packed; // @[tile.scala:159:20]
wire [11:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_csr_addr; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_rob_idx; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_ldq_idx; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_stq_idx; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_rxq_idx; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_pdst; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_prs1; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_prs2; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_prs3; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_ppred; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_prs1_busy; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_prs2_busy; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_prs3_busy; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_ppred_busy; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_stale_pdst; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_exception; // @[tile.scala:159:20]
wire [63:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_exc_cause; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_bypassable; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_mem_cmd; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_mem_size; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_mem_signed; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_fence; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_fencei; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_amo; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_uses_ldq; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_uses_stq; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_sys_pc2epc; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_unique; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_flush_on_commit; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_ldst_is_rs1; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_ldst; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_lrs1; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_lrs2; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_lrs3; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_ldst_val; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_dst_rtype; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_lrs1_rtype; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_lrs2_rtype; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_frs3_en; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_fp_val; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_fp_single; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_pf_if; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_ae_if; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_ma_if; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_bp_debug_if; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_bp_xcpt_if; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_debug_fsrc; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_debug_tsrc; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_fp_stdata_bits_fflags_bits_flags; // @[tile.scala:159:20]
wire _core_io_lsu_commit_valids_0; // @[tile.scala:159:20]
wire _core_io_lsu_commit_valids_1; // @[tile.scala:159:20]
wire _core_io_lsu_commit_valids_2; // @[tile.scala:159:20]
wire _core_io_lsu_commit_arch_valids_0; // @[tile.scala:159:20]
wire _core_io_lsu_commit_arch_valids_1; // @[tile.scala:159:20]
wire _core_io_lsu_commit_arch_valids_2; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_commit_uops_0_uopc; // @[tile.scala:159:20]
wire [31:0] _core_io_lsu_commit_uops_0_inst; // @[tile.scala:159:20]
wire [31:0] _core_io_lsu_commit_uops_0_debug_inst; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_is_rvc; // @[tile.scala:159:20]
wire [39:0] _core_io_lsu_commit_uops_0_debug_pc; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_commit_uops_0_iq_type; // @[tile.scala:159:20]
wire [9:0] _core_io_lsu_commit_uops_0_fu_code; // @[tile.scala:159:20]
wire [3:0] _core_io_lsu_commit_uops_0_ctrl_br_type; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_0_ctrl_op1_sel; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_commit_uops_0_ctrl_op2_sel; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_commit_uops_0_ctrl_imm_sel; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_commit_uops_0_ctrl_op_fcn; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_ctrl_fcn_dw; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_commit_uops_0_ctrl_csr_cmd; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_ctrl_is_load; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_ctrl_is_sta; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_ctrl_is_std; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_0_iw_state; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_iw_p1_poisoned; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_iw_p2_poisoned; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_is_br; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_is_jalr; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_is_jal; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_is_sfb; // @[tile.scala:159:20]
wire [15:0] _core_io_lsu_commit_uops_0_br_mask; // @[tile.scala:159:20]
wire [3:0] _core_io_lsu_commit_uops_0_br_tag; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_commit_uops_0_ftq_idx; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_edge_inst; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_commit_uops_0_pc_lob; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_taken; // @[tile.scala:159:20]
wire [19:0] _core_io_lsu_commit_uops_0_imm_packed; // @[tile.scala:159:20]
wire [11:0] _core_io_lsu_commit_uops_0_csr_addr; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_commit_uops_0_rob_idx; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_commit_uops_0_ldq_idx; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_commit_uops_0_stq_idx; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_0_rxq_idx; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_commit_uops_0_pdst; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_commit_uops_0_prs1; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_commit_uops_0_prs2; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_commit_uops_0_prs3; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_commit_uops_0_ppred; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_prs1_busy; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_prs2_busy; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_prs3_busy; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_ppred_busy; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_commit_uops_0_stale_pdst; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_exception; // @[tile.scala:159:20]
wire [63:0] _core_io_lsu_commit_uops_0_exc_cause; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_bypassable; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_commit_uops_0_mem_cmd; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_0_mem_size; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_mem_signed; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_is_fence; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_is_fencei; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_is_amo; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_uses_ldq; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_uses_stq; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_is_sys_pc2epc; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_is_unique; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_flush_on_commit; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_ldst_is_rs1; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_commit_uops_0_ldst; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_commit_uops_0_lrs1; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_commit_uops_0_lrs2; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_commit_uops_0_lrs3; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_ldst_val; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_0_dst_rtype; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_0_lrs1_rtype; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_0_lrs2_rtype; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_frs3_en; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_fp_val; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_fp_single; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_xcpt_pf_if; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_xcpt_ae_if; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_xcpt_ma_if; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_bp_debug_if; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_bp_xcpt_if; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_0_debug_fsrc; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_0_debug_tsrc; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_commit_uops_1_uopc; // @[tile.scala:159:20]
wire [31:0] _core_io_lsu_commit_uops_1_inst; // @[tile.scala:159:20]
wire [31:0] _core_io_lsu_commit_uops_1_debug_inst; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_is_rvc; // @[tile.scala:159:20]
wire [39:0] _core_io_lsu_commit_uops_1_debug_pc; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_commit_uops_1_iq_type; // @[tile.scala:159:20]
wire [9:0] _core_io_lsu_commit_uops_1_fu_code; // @[tile.scala:159:20]
wire [3:0] _core_io_lsu_commit_uops_1_ctrl_br_type; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_1_ctrl_op1_sel; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_commit_uops_1_ctrl_op2_sel; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_commit_uops_1_ctrl_imm_sel; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_commit_uops_1_ctrl_op_fcn; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_ctrl_fcn_dw; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_commit_uops_1_ctrl_csr_cmd; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_ctrl_is_load; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_ctrl_is_sta; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_ctrl_is_std; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_1_iw_state; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_iw_p1_poisoned; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_iw_p2_poisoned; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_is_br; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_is_jalr; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_is_jal; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_is_sfb; // @[tile.scala:159:20]
wire [15:0] _core_io_lsu_commit_uops_1_br_mask; // @[tile.scala:159:20]
wire [3:0] _core_io_lsu_commit_uops_1_br_tag; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_commit_uops_1_ftq_idx; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_edge_inst; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_commit_uops_1_pc_lob; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_taken; // @[tile.scala:159:20]
wire [19:0] _core_io_lsu_commit_uops_1_imm_packed; // @[tile.scala:159:20]
wire [11:0] _core_io_lsu_commit_uops_1_csr_addr; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_commit_uops_1_rob_idx; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_commit_uops_1_ldq_idx; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_commit_uops_1_stq_idx; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_1_rxq_idx; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_commit_uops_1_pdst; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_commit_uops_1_prs1; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_commit_uops_1_prs2; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_commit_uops_1_prs3; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_commit_uops_1_ppred; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_prs1_busy; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_prs2_busy; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_prs3_busy; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_ppred_busy; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_commit_uops_1_stale_pdst; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_exception; // @[tile.scala:159:20]
wire [63:0] _core_io_lsu_commit_uops_1_exc_cause; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_bypassable; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_commit_uops_1_mem_cmd; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_1_mem_size; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_mem_signed; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_is_fence; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_is_fencei; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_is_amo; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_uses_ldq; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_uses_stq; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_is_sys_pc2epc; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_is_unique; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_flush_on_commit; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_ldst_is_rs1; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_commit_uops_1_ldst; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_commit_uops_1_lrs1; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_commit_uops_1_lrs2; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_commit_uops_1_lrs3; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_ldst_val; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_1_dst_rtype; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_1_lrs1_rtype; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_1_lrs2_rtype; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_frs3_en; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_fp_val; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_fp_single; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_xcpt_pf_if; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_xcpt_ae_if; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_xcpt_ma_if; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_bp_debug_if; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_bp_xcpt_if; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_1_debug_fsrc; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_1_debug_tsrc; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_commit_uops_2_uopc; // @[tile.scala:159:20]
wire [31:0] _core_io_lsu_commit_uops_2_inst; // @[tile.scala:159:20]
wire [31:0] _core_io_lsu_commit_uops_2_debug_inst; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_is_rvc; // @[tile.scala:159:20]
wire [39:0] _core_io_lsu_commit_uops_2_debug_pc; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_commit_uops_2_iq_type; // @[tile.scala:159:20]
wire [9:0] _core_io_lsu_commit_uops_2_fu_code; // @[tile.scala:159:20]
wire [3:0] _core_io_lsu_commit_uops_2_ctrl_br_type; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_2_ctrl_op1_sel; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_commit_uops_2_ctrl_op2_sel; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_commit_uops_2_ctrl_imm_sel; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_commit_uops_2_ctrl_op_fcn; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_ctrl_fcn_dw; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_commit_uops_2_ctrl_csr_cmd; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_ctrl_is_load; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_ctrl_is_sta; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_ctrl_is_std; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_2_iw_state; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_iw_p1_poisoned; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_iw_p2_poisoned; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_is_br; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_is_jalr; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_is_jal; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_is_sfb; // @[tile.scala:159:20]
wire [15:0] _core_io_lsu_commit_uops_2_br_mask; // @[tile.scala:159:20]
wire [3:0] _core_io_lsu_commit_uops_2_br_tag; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_commit_uops_2_ftq_idx; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_edge_inst; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_commit_uops_2_pc_lob; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_taken; // @[tile.scala:159:20]
wire [19:0] _core_io_lsu_commit_uops_2_imm_packed; // @[tile.scala:159:20]
wire [11:0] _core_io_lsu_commit_uops_2_csr_addr; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_commit_uops_2_rob_idx; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_commit_uops_2_ldq_idx; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_commit_uops_2_stq_idx; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_2_rxq_idx; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_commit_uops_2_pdst; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_commit_uops_2_prs1; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_commit_uops_2_prs2; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_commit_uops_2_prs3; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_commit_uops_2_ppred; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_prs1_busy; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_prs2_busy; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_prs3_busy; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_ppred_busy; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_commit_uops_2_stale_pdst; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_exception; // @[tile.scala:159:20]
wire [63:0] _core_io_lsu_commit_uops_2_exc_cause; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_bypassable; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_commit_uops_2_mem_cmd; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_2_mem_size; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_mem_signed; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_is_fence; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_is_fencei; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_is_amo; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_uses_ldq; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_uses_stq; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_is_sys_pc2epc; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_is_unique; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_flush_on_commit; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_ldst_is_rs1; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_commit_uops_2_ldst; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_commit_uops_2_lrs1; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_commit_uops_2_lrs2; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_commit_uops_2_lrs3; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_ldst_val; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_2_dst_rtype; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_2_lrs1_rtype; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_2_lrs2_rtype; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_frs3_en; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_fp_val; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_fp_single; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_xcpt_pf_if; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_xcpt_ae_if; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_xcpt_ma_if; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_bp_debug_if; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_bp_xcpt_if; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_2_debug_fsrc; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_2_debug_tsrc; // @[tile.scala:159:20]
wire _core_io_lsu_commit_fflags_valid; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_commit_fflags_bits; // @[tile.scala:159:20]
wire [31:0] _core_io_lsu_commit_debug_insts_0; // @[tile.scala:159:20]
wire [31:0] _core_io_lsu_commit_debug_insts_1; // @[tile.scala:159:20]
wire [31:0] _core_io_lsu_commit_debug_insts_2; // @[tile.scala:159:20]
wire _core_io_lsu_commit_rbk_valids_0; // @[tile.scala:159:20]
wire _core_io_lsu_commit_rbk_valids_1; // @[tile.scala:159:20]
wire _core_io_lsu_commit_rbk_valids_2; // @[tile.scala:159:20]
wire _core_io_lsu_commit_rollback; // @[tile.scala:159:20]
wire [63:0] _core_io_lsu_commit_debug_wdata_0; // @[tile.scala:159:20]
wire [63:0] _core_io_lsu_commit_debug_wdata_1; // @[tile.scala:159:20]
wire [63:0] _core_io_lsu_commit_debug_wdata_2; // @[tile.scala:159:20]
wire _core_io_lsu_commit_load_at_rob_head; // @[tile.scala:159:20]
wire _core_io_lsu_fence_dmem; // @[tile.scala:159:20]
wire [15:0] _core_io_lsu_brupdate_b1_resolve_mask; // @[tile.scala:159:20]
wire [15:0] _core_io_lsu_brupdate_b1_mispredict_mask; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_brupdate_b2_uop_uopc; // @[tile.scala:159:20]
wire [31:0] _core_io_lsu_brupdate_b2_uop_inst; // @[tile.scala:159:20]
wire [31:0] _core_io_lsu_brupdate_b2_uop_debug_inst; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_is_rvc; // @[tile.scala:159:20]
wire [39:0] _core_io_lsu_brupdate_b2_uop_debug_pc; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_brupdate_b2_uop_iq_type; // @[tile.scala:159:20]
wire [9:0] _core_io_lsu_brupdate_b2_uop_fu_code; // @[tile.scala:159:20]
wire [3:0] _core_io_lsu_brupdate_b2_uop_ctrl_br_type; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_brupdate_b2_uop_ctrl_op1_sel; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_brupdate_b2_uop_ctrl_op2_sel; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_brupdate_b2_uop_ctrl_imm_sel; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_brupdate_b2_uop_ctrl_op_fcn; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_ctrl_fcn_dw; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_brupdate_b2_uop_ctrl_csr_cmd; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_ctrl_is_load; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_ctrl_is_sta; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_ctrl_is_std; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_brupdate_b2_uop_iw_state; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_iw_p1_poisoned; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_iw_p2_poisoned; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_is_br; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_is_jalr; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_is_jal; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_is_sfb; // @[tile.scala:159:20]
wire [15:0] _core_io_lsu_brupdate_b2_uop_br_mask; // @[tile.scala:159:20]
wire [3:0] _core_io_lsu_brupdate_b2_uop_br_tag; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_brupdate_b2_uop_ftq_idx; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_edge_inst; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_brupdate_b2_uop_pc_lob; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_taken; // @[tile.scala:159:20]
wire [19:0] _core_io_lsu_brupdate_b2_uop_imm_packed; // @[tile.scala:159:20]
wire [11:0] _core_io_lsu_brupdate_b2_uop_csr_addr; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_brupdate_b2_uop_rob_idx; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_brupdate_b2_uop_ldq_idx; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_brupdate_b2_uop_stq_idx; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_brupdate_b2_uop_rxq_idx; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_brupdate_b2_uop_pdst; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_brupdate_b2_uop_prs1; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_brupdate_b2_uop_prs2; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_brupdate_b2_uop_prs3; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_brupdate_b2_uop_ppred; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_prs1_busy; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_prs2_busy; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_prs3_busy; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_ppred_busy; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_brupdate_b2_uop_stale_pdst; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_exception; // @[tile.scala:159:20]
wire [63:0] _core_io_lsu_brupdate_b2_uop_exc_cause; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_bypassable; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_brupdate_b2_uop_mem_cmd; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_brupdate_b2_uop_mem_size; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_mem_signed; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_is_fence; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_is_fencei; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_is_amo; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_uses_ldq; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_uses_stq; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_is_sys_pc2epc; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_is_unique; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_flush_on_commit; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_ldst_is_rs1; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_brupdate_b2_uop_ldst; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_brupdate_b2_uop_lrs1; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_brupdate_b2_uop_lrs2; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_brupdate_b2_uop_lrs3; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_ldst_val; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_brupdate_b2_uop_dst_rtype; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_brupdate_b2_uop_lrs1_rtype; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_brupdate_b2_uop_lrs2_rtype; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_frs3_en; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_fp_val; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_fp_single; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_xcpt_pf_if; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_xcpt_ae_if; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_xcpt_ma_if; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_bp_debug_if; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_bp_xcpt_if; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_brupdate_b2_uop_debug_fsrc; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_brupdate_b2_uop_debug_tsrc; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_valid; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_mispredict; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_taken; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_brupdate_b2_cfi_type; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_brupdate_b2_pc_sel; // @[tile.scala:159:20]
wire [39:0] _core_io_lsu_brupdate_b2_jalr_target; // @[tile.scala:159:20]
wire [20:0] _core_io_lsu_brupdate_b2_target_offset; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_rob_pnr_idx; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_rob_head_idx; // @[tile.scala:159:20]
wire _core_io_lsu_exception; // @[tile.scala:159:20]
wire [63:0] _core_io_lsu_tsc_reg; // @[tile.scala:159:20]
wire _frontend_io_cpu_fetchpacket_valid; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_0_valid; // @[tile.scala:138:28]
wire [31:0] _frontend_io_cpu_fetchpacket_bits_uops_0_bits_inst; // @[tile.scala:138:28]
wire [31:0] _frontend_io_cpu_fetchpacket_bits_uops_0_bits_debug_inst; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_0_bits_is_rvc; // @[tile.scala:138:28]
wire [39:0] _frontend_io_cpu_fetchpacket_bits_uops_0_bits_debug_pc; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_0_bits_is_sfb; // @[tile.scala:138:28]
wire [4:0] _frontend_io_cpu_fetchpacket_bits_uops_0_bits_ftq_idx; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_0_bits_edge_inst; // @[tile.scala:138:28]
wire [5:0] _frontend_io_cpu_fetchpacket_bits_uops_0_bits_pc_lob; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_0_bits_taken; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_0_bits_xcpt_pf_if; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_0_bits_xcpt_ae_if; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_0_bits_bp_debug_if; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_0_bits_bp_xcpt_if; // @[tile.scala:138:28]
wire [1:0] _frontend_io_cpu_fetchpacket_bits_uops_0_bits_debug_fsrc; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_1_valid; // @[tile.scala:138:28]
wire [31:0] _frontend_io_cpu_fetchpacket_bits_uops_1_bits_inst; // @[tile.scala:138:28]
wire [31:0] _frontend_io_cpu_fetchpacket_bits_uops_1_bits_debug_inst; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_1_bits_is_rvc; // @[tile.scala:138:28]
wire [39:0] _frontend_io_cpu_fetchpacket_bits_uops_1_bits_debug_pc; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_1_bits_is_sfb; // @[tile.scala:138:28]
wire [4:0] _frontend_io_cpu_fetchpacket_bits_uops_1_bits_ftq_idx; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_1_bits_edge_inst; // @[tile.scala:138:28]
wire [5:0] _frontend_io_cpu_fetchpacket_bits_uops_1_bits_pc_lob; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_1_bits_taken; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_1_bits_xcpt_pf_if; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_1_bits_xcpt_ae_if; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_1_bits_bp_debug_if; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_1_bits_bp_xcpt_if; // @[tile.scala:138:28]
wire [1:0] _frontend_io_cpu_fetchpacket_bits_uops_1_bits_debug_fsrc; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_2_valid; // @[tile.scala:138:28]
wire [31:0] _frontend_io_cpu_fetchpacket_bits_uops_2_bits_inst; // @[tile.scala:138:28]
wire [31:0] _frontend_io_cpu_fetchpacket_bits_uops_2_bits_debug_inst; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_2_bits_is_rvc; // @[tile.scala:138:28]
wire [39:0] _frontend_io_cpu_fetchpacket_bits_uops_2_bits_debug_pc; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_2_bits_is_sfb; // @[tile.scala:138:28]
wire [4:0] _frontend_io_cpu_fetchpacket_bits_uops_2_bits_ftq_idx; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_2_bits_edge_inst; // @[tile.scala:138:28]
wire [5:0] _frontend_io_cpu_fetchpacket_bits_uops_2_bits_pc_lob; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_2_bits_taken; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_2_bits_xcpt_pf_if; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_2_bits_xcpt_ae_if; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_2_bits_bp_debug_if; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_2_bits_bp_xcpt_if; // @[tile.scala:138:28]
wire [1:0] _frontend_io_cpu_fetchpacket_bits_uops_2_bits_debug_fsrc; // @[tile.scala:138:28]
wire _frontend_io_cpu_get_pc_0_entry_cfi_idx_valid; // @[tile.scala:138:28]
wire [2:0] _frontend_io_cpu_get_pc_0_entry_cfi_idx_bits; // @[tile.scala:138:28]
wire _frontend_io_cpu_get_pc_0_entry_cfi_taken; // @[tile.scala:138:28]
wire _frontend_io_cpu_get_pc_0_entry_cfi_mispredicted; // @[tile.scala:138:28]
wire [2:0] _frontend_io_cpu_get_pc_0_entry_cfi_type; // @[tile.scala:138:28]
wire [7:0] _frontend_io_cpu_get_pc_0_entry_br_mask; // @[tile.scala:138:28]
wire _frontend_io_cpu_get_pc_0_entry_cfi_is_call; // @[tile.scala:138:28]
wire _frontend_io_cpu_get_pc_0_entry_cfi_is_ret; // @[tile.scala:138:28]
wire _frontend_io_cpu_get_pc_0_entry_cfi_npc_plus4; // @[tile.scala:138:28]
wire [39:0] _frontend_io_cpu_get_pc_0_entry_ras_top; // @[tile.scala:138:28]
wire [4:0] _frontend_io_cpu_get_pc_0_entry_ras_idx; // @[tile.scala:138:28]
wire _frontend_io_cpu_get_pc_0_entry_start_bank; // @[tile.scala:138:28]
wire [39:0] _frontend_io_cpu_get_pc_0_pc; // @[tile.scala:138:28]
wire [39:0] _frontend_io_cpu_get_pc_0_com_pc; // @[tile.scala:138:28]
wire _frontend_io_cpu_get_pc_0_next_val; // @[tile.scala:138:28]
wire [39:0] _frontend_io_cpu_get_pc_0_next_pc; // @[tile.scala:138:28]
wire _frontend_io_cpu_get_pc_1_entry_cfi_idx_valid; // @[tile.scala:138:28]
wire [2:0] _frontend_io_cpu_get_pc_1_entry_cfi_idx_bits; // @[tile.scala:138:28]
wire _frontend_io_cpu_get_pc_1_entry_cfi_taken; // @[tile.scala:138:28]
wire _frontend_io_cpu_get_pc_1_entry_cfi_mispredicted; // @[tile.scala:138:28]
wire [2:0] _frontend_io_cpu_get_pc_1_entry_cfi_type; // @[tile.scala:138:28]
wire [7:0] _frontend_io_cpu_get_pc_1_entry_br_mask; // @[tile.scala:138:28]
wire _frontend_io_cpu_get_pc_1_entry_cfi_is_call; // @[tile.scala:138:28]
wire _frontend_io_cpu_get_pc_1_entry_cfi_is_ret; // @[tile.scala:138:28]
wire _frontend_io_cpu_get_pc_1_entry_cfi_npc_plus4; // @[tile.scala:138:28]
wire [39:0] _frontend_io_cpu_get_pc_1_entry_ras_top; // @[tile.scala:138:28]
wire [4:0] _frontend_io_cpu_get_pc_1_entry_ras_idx; // @[tile.scala:138:28]
wire _frontend_io_cpu_get_pc_1_entry_start_bank; // @[tile.scala:138:28]
wire [63:0] _frontend_io_cpu_get_pc_1_ghist_old_history; // @[tile.scala:138:28]
wire _frontend_io_cpu_get_pc_1_ghist_current_saw_branch_not_taken; // @[tile.scala:138:28]
wire _frontend_io_cpu_get_pc_1_ghist_new_saw_branch_not_taken; // @[tile.scala:138:28]
wire _frontend_io_cpu_get_pc_1_ghist_new_saw_branch_taken; // @[tile.scala:138:28]
wire [4:0] _frontend_io_cpu_get_pc_1_ghist_ras_idx; // @[tile.scala:138:28]
wire [39:0] _frontend_io_cpu_get_pc_1_pc; // @[tile.scala:138:28]
wire [39:0] _frontend_io_cpu_get_pc_1_com_pc; // @[tile.scala:138:28]
wire _frontend_io_cpu_get_pc_1_next_val; // @[tile.scala:138:28]
wire [39:0] _frontend_io_cpu_get_pc_1_next_pc; // @[tile.scala:138:28]
wire [39:0] _frontend_io_cpu_debug_fetch_pc_0; // @[tile.scala:138:28]
wire [39:0] _frontend_io_cpu_debug_fetch_pc_1; // @[tile.scala:138:28]
wire [39:0] _frontend_io_cpu_debug_fetch_pc_2; // @[tile.scala:138:28]
wire _frontend_io_cpu_perf_acquire; // @[tile.scala:138:28]
wire _frontend_io_cpu_perf_tlbMiss; // @[tile.scala:138:28]
wire _frontend_io_ptw_req_valid; // @[tile.scala:138:28]
wire [26:0] _frontend_io_ptw_req_bits_bits_addr; // @[tile.scala:138:28]
wire _frontend_io_ptw_req_bits_bits_need_gpa; // @[tile.scala:138:28]
wire _dcache_io_lsu_req_ready; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_valid; // @[tile.scala:132:54]
wire [6:0] _dcache_io_lsu_resp_0_bits_uop_uopc; // @[tile.scala:132:54]
wire [31:0] _dcache_io_lsu_resp_0_bits_uop_inst; // @[tile.scala:132:54]
wire [31:0] _dcache_io_lsu_resp_0_bits_uop_debug_inst; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_is_rvc; // @[tile.scala:132:54]
wire [39:0] _dcache_io_lsu_resp_0_bits_uop_debug_pc; // @[tile.scala:132:54]
wire [2:0] _dcache_io_lsu_resp_0_bits_uop_iq_type; // @[tile.scala:132:54]
wire [9:0] _dcache_io_lsu_resp_0_bits_uop_fu_code; // @[tile.scala:132:54]
wire [3:0] _dcache_io_lsu_resp_0_bits_uop_ctrl_br_type; // @[tile.scala:132:54]
wire [1:0] _dcache_io_lsu_resp_0_bits_uop_ctrl_op1_sel; // @[tile.scala:132:54]
wire [2:0] _dcache_io_lsu_resp_0_bits_uop_ctrl_op2_sel; // @[tile.scala:132:54]
wire [2:0] _dcache_io_lsu_resp_0_bits_uop_ctrl_imm_sel; // @[tile.scala:132:54]
wire [4:0] _dcache_io_lsu_resp_0_bits_uop_ctrl_op_fcn; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_ctrl_fcn_dw; // @[tile.scala:132:54]
wire [2:0] _dcache_io_lsu_resp_0_bits_uop_ctrl_csr_cmd; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_ctrl_is_load; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_ctrl_is_sta; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_ctrl_is_std; // @[tile.scala:132:54]
wire [1:0] _dcache_io_lsu_resp_0_bits_uop_iw_state; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_iw_p1_poisoned; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_iw_p2_poisoned; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_is_br; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_is_jalr; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_is_jal; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_is_sfb; // @[tile.scala:132:54]
wire [15:0] _dcache_io_lsu_resp_0_bits_uop_br_mask; // @[tile.scala:132:54]
wire [3:0] _dcache_io_lsu_resp_0_bits_uop_br_tag; // @[tile.scala:132:54]
wire [4:0] _dcache_io_lsu_resp_0_bits_uop_ftq_idx; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_edge_inst; // @[tile.scala:132:54]
wire [5:0] _dcache_io_lsu_resp_0_bits_uop_pc_lob; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_taken; // @[tile.scala:132:54]
wire [19:0] _dcache_io_lsu_resp_0_bits_uop_imm_packed; // @[tile.scala:132:54]
wire [11:0] _dcache_io_lsu_resp_0_bits_uop_csr_addr; // @[tile.scala:132:54]
wire [6:0] _dcache_io_lsu_resp_0_bits_uop_rob_idx; // @[tile.scala:132:54]
wire [4:0] _dcache_io_lsu_resp_0_bits_uop_ldq_idx; // @[tile.scala:132:54]
wire [4:0] _dcache_io_lsu_resp_0_bits_uop_stq_idx; // @[tile.scala:132:54]
wire [1:0] _dcache_io_lsu_resp_0_bits_uop_rxq_idx; // @[tile.scala:132:54]
wire [6:0] _dcache_io_lsu_resp_0_bits_uop_pdst; // @[tile.scala:132:54]
wire [6:0] _dcache_io_lsu_resp_0_bits_uop_prs1; // @[tile.scala:132:54]
wire [6:0] _dcache_io_lsu_resp_0_bits_uop_prs2; // @[tile.scala:132:54]
wire [6:0] _dcache_io_lsu_resp_0_bits_uop_prs3; // @[tile.scala:132:54]
wire [4:0] _dcache_io_lsu_resp_0_bits_uop_ppred; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_prs1_busy; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_prs2_busy; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_prs3_busy; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_ppred_busy; // @[tile.scala:132:54]
wire [6:0] _dcache_io_lsu_resp_0_bits_uop_stale_pdst; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_exception; // @[tile.scala:132:54]
wire [63:0] _dcache_io_lsu_resp_0_bits_uop_exc_cause; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_bypassable; // @[tile.scala:132:54]
wire [4:0] _dcache_io_lsu_resp_0_bits_uop_mem_cmd; // @[tile.scala:132:54]
wire [1:0] _dcache_io_lsu_resp_0_bits_uop_mem_size; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_mem_signed; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_is_fence; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_is_fencei; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_is_amo; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_uses_ldq; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_uses_stq; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_is_sys_pc2epc; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_is_unique; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_flush_on_commit; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_ldst_is_rs1; // @[tile.scala:132:54]
wire [5:0] _dcache_io_lsu_resp_0_bits_uop_ldst; // @[tile.scala:132:54]
wire [5:0] _dcache_io_lsu_resp_0_bits_uop_lrs1; // @[tile.scala:132:54]
wire [5:0] _dcache_io_lsu_resp_0_bits_uop_lrs2; // @[tile.scala:132:54]
wire [5:0] _dcache_io_lsu_resp_0_bits_uop_lrs3; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_ldst_val; // @[tile.scala:132:54]
wire [1:0] _dcache_io_lsu_resp_0_bits_uop_dst_rtype; // @[tile.scala:132:54]
wire [1:0] _dcache_io_lsu_resp_0_bits_uop_lrs1_rtype; // @[tile.scala:132:54]
wire [1:0] _dcache_io_lsu_resp_0_bits_uop_lrs2_rtype; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_frs3_en; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_fp_val; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_fp_single; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_xcpt_pf_if; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_xcpt_ae_if; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_xcpt_ma_if; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_bp_debug_if; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_bp_xcpt_if; // @[tile.scala:132:54]
wire [1:0] _dcache_io_lsu_resp_0_bits_uop_debug_fsrc; // @[tile.scala:132:54]
wire [1:0] _dcache_io_lsu_resp_0_bits_uop_debug_tsrc; // @[tile.scala:132:54]
wire [63:0] _dcache_io_lsu_resp_0_bits_data; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_is_hella; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_valid; // @[tile.scala:132:54]
wire [6:0] _dcache_io_lsu_nack_0_bits_uop_uopc; // @[tile.scala:132:54]
wire [31:0] _dcache_io_lsu_nack_0_bits_uop_inst; // @[tile.scala:132:54]
wire [31:0] _dcache_io_lsu_nack_0_bits_uop_debug_inst; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_is_rvc; // @[tile.scala:132:54]
wire [39:0] _dcache_io_lsu_nack_0_bits_uop_debug_pc; // @[tile.scala:132:54]
wire [2:0] _dcache_io_lsu_nack_0_bits_uop_iq_type; // @[tile.scala:132:54]
wire [9:0] _dcache_io_lsu_nack_0_bits_uop_fu_code; // @[tile.scala:132:54]
wire [3:0] _dcache_io_lsu_nack_0_bits_uop_ctrl_br_type; // @[tile.scala:132:54]
wire [1:0] _dcache_io_lsu_nack_0_bits_uop_ctrl_op1_sel; // @[tile.scala:132:54]
wire [2:0] _dcache_io_lsu_nack_0_bits_uop_ctrl_op2_sel; // @[tile.scala:132:54]
wire [2:0] _dcache_io_lsu_nack_0_bits_uop_ctrl_imm_sel; // @[tile.scala:132:54]
wire [4:0] _dcache_io_lsu_nack_0_bits_uop_ctrl_op_fcn; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_ctrl_fcn_dw; // @[tile.scala:132:54]
wire [2:0] _dcache_io_lsu_nack_0_bits_uop_ctrl_csr_cmd; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_ctrl_is_load; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_ctrl_is_sta; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_ctrl_is_std; // @[tile.scala:132:54]
wire [1:0] _dcache_io_lsu_nack_0_bits_uop_iw_state; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_iw_p1_poisoned; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_iw_p2_poisoned; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_is_br; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_is_jalr; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_is_jal; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_is_sfb; // @[tile.scala:132:54]
wire [15:0] _dcache_io_lsu_nack_0_bits_uop_br_mask; // @[tile.scala:132:54]
wire [3:0] _dcache_io_lsu_nack_0_bits_uop_br_tag; // @[tile.scala:132:54]
wire [4:0] _dcache_io_lsu_nack_0_bits_uop_ftq_idx; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_edge_inst; // @[tile.scala:132:54]
wire [5:0] _dcache_io_lsu_nack_0_bits_uop_pc_lob; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_taken; // @[tile.scala:132:54]
wire [19:0] _dcache_io_lsu_nack_0_bits_uop_imm_packed; // @[tile.scala:132:54]
wire [11:0] _dcache_io_lsu_nack_0_bits_uop_csr_addr; // @[tile.scala:132:54]
wire [6:0] _dcache_io_lsu_nack_0_bits_uop_rob_idx; // @[tile.scala:132:54]
wire [4:0] _dcache_io_lsu_nack_0_bits_uop_ldq_idx; // @[tile.scala:132:54]
wire [4:0] _dcache_io_lsu_nack_0_bits_uop_stq_idx; // @[tile.scala:132:54]
wire [1:0] _dcache_io_lsu_nack_0_bits_uop_rxq_idx; // @[tile.scala:132:54]
wire [6:0] _dcache_io_lsu_nack_0_bits_uop_pdst; // @[tile.scala:132:54]
wire [6:0] _dcache_io_lsu_nack_0_bits_uop_prs1; // @[tile.scala:132:54]
wire [6:0] _dcache_io_lsu_nack_0_bits_uop_prs2; // @[tile.scala:132:54]
wire [6:0] _dcache_io_lsu_nack_0_bits_uop_prs3; // @[tile.scala:132:54]
wire [4:0] _dcache_io_lsu_nack_0_bits_uop_ppred; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_prs1_busy; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_prs2_busy; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_prs3_busy; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_ppred_busy; // @[tile.scala:132:54]
wire [6:0] _dcache_io_lsu_nack_0_bits_uop_stale_pdst; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_exception; // @[tile.scala:132:54]
wire [63:0] _dcache_io_lsu_nack_0_bits_uop_exc_cause; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_bypassable; // @[tile.scala:132:54]
wire [4:0] _dcache_io_lsu_nack_0_bits_uop_mem_cmd; // @[tile.scala:132:54]
wire [1:0] _dcache_io_lsu_nack_0_bits_uop_mem_size; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_mem_signed; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_is_fence; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_is_fencei; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_is_amo; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_uses_ldq; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_uses_stq; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_is_sys_pc2epc; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_is_unique; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_flush_on_commit; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_ldst_is_rs1; // @[tile.scala:132:54]
wire [5:0] _dcache_io_lsu_nack_0_bits_uop_ldst; // @[tile.scala:132:54]
wire [5:0] _dcache_io_lsu_nack_0_bits_uop_lrs1; // @[tile.scala:132:54]
wire [5:0] _dcache_io_lsu_nack_0_bits_uop_lrs2; // @[tile.scala:132:54]
wire [5:0] _dcache_io_lsu_nack_0_bits_uop_lrs3; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_ldst_val; // @[tile.scala:132:54]
wire [1:0] _dcache_io_lsu_nack_0_bits_uop_dst_rtype; // @[tile.scala:132:54]
wire [1:0] _dcache_io_lsu_nack_0_bits_uop_lrs1_rtype; // @[tile.scala:132:54]
wire [1:0] _dcache_io_lsu_nack_0_bits_uop_lrs2_rtype; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_frs3_en; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_fp_val; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_fp_single; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_xcpt_pf_if; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_xcpt_ae_if; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_xcpt_ma_if; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_bp_debug_if; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_bp_xcpt_if; // @[tile.scala:132:54]
wire [1:0] _dcache_io_lsu_nack_0_bits_uop_debug_fsrc; // @[tile.scala:132:54]
wire [1:0] _dcache_io_lsu_nack_0_bits_uop_debug_tsrc; // @[tile.scala:132:54]
wire [39:0] _dcache_io_lsu_nack_0_bits_addr; // @[tile.scala:132:54]
wire [63:0] _dcache_io_lsu_nack_0_bits_data; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_is_hella; // @[tile.scala:132:54]
wire _dcache_io_lsu_release_valid; // @[tile.scala:132:54]
wire [2:0] _dcache_io_lsu_release_bits_opcode; // @[tile.scala:132:54]
wire [2:0] _dcache_io_lsu_release_bits_param; // @[tile.scala:132:54]
wire [3:0] _dcache_io_lsu_release_bits_size; // @[tile.scala:132:54]
wire [2:0] _dcache_io_lsu_release_bits_source; // @[tile.scala:132:54]
wire [31:0] _dcache_io_lsu_release_bits_address; // @[tile.scala:132:54]
wire [127:0] _dcache_io_lsu_release_bits_data; // @[tile.scala:132:54]
wire _dcache_io_lsu_ordered; // @[tile.scala:132:54]
wire _dcache_io_lsu_perf_acquire; // @[tile.scala:132:54]
wire _dcache_io_lsu_perf_release; // @[tile.scala:132:54]
wire auto_buffer_out_a_ready_0 = auto_buffer_out_a_ready; // @[tile.scala:155:7]
wire auto_buffer_out_b_valid_0 = auto_buffer_out_b_valid; // @[tile.scala:155:7]
wire [2:0] auto_buffer_out_b_bits_opcode_0 = auto_buffer_out_b_bits_opcode; // @[tile.scala:155:7]
wire [1:0] auto_buffer_out_b_bits_param_0 = auto_buffer_out_b_bits_param; // @[tile.scala:155:7]
wire [3:0] auto_buffer_out_b_bits_size_0 = auto_buffer_out_b_bits_size; // @[tile.scala:155:7]
wire [3:0] auto_buffer_out_b_bits_source_0 = auto_buffer_out_b_bits_source; // @[tile.scala:155:7]
wire [31:0] auto_buffer_out_b_bits_address_0 = auto_buffer_out_b_bits_address; // @[tile.scala:155:7]
wire [15:0] auto_buffer_out_b_bits_mask_0 = auto_buffer_out_b_bits_mask; // @[tile.scala:155:7]
wire [127:0] auto_buffer_out_b_bits_data_0 = auto_buffer_out_b_bits_data; // @[tile.scala:155:7]
wire auto_buffer_out_b_bits_corrupt_0 = auto_buffer_out_b_bits_corrupt; // @[tile.scala:155:7]
wire auto_buffer_out_c_ready_0 = auto_buffer_out_c_ready; // @[tile.scala:155:7]
wire auto_buffer_out_d_valid_0 = auto_buffer_out_d_valid; // @[tile.scala:155:7]
wire [2:0] auto_buffer_out_d_bits_opcode_0 = auto_buffer_out_d_bits_opcode; // @[tile.scala:155:7]
wire [1:0] auto_buffer_out_d_bits_param_0 = auto_buffer_out_d_bits_param; // @[tile.scala:155:7]
wire [3:0] auto_buffer_out_d_bits_size_0 = auto_buffer_out_d_bits_size; // @[tile.scala:155:7]
wire [3:0] auto_buffer_out_d_bits_source_0 = auto_buffer_out_d_bits_source; // @[tile.scala:155:7]
wire [3:0] auto_buffer_out_d_bits_sink_0 = auto_buffer_out_d_bits_sink; // @[tile.scala:155:7]
wire auto_buffer_out_d_bits_denied_0 = auto_buffer_out_d_bits_denied; // @[tile.scala:155:7]
wire [127:0] auto_buffer_out_d_bits_data_0 = auto_buffer_out_d_bits_data; // @[tile.scala:155:7]
wire auto_buffer_out_d_bits_corrupt_0 = auto_buffer_out_d_bits_corrupt; // @[tile.scala:155:7]
wire auto_buffer_out_e_ready_0 = auto_buffer_out_e_ready; // @[tile.scala:155:7]
wire auto_int_local_in_3_0_0 = auto_int_local_in_3_0; // @[tile.scala:155:7]
wire auto_int_local_in_2_0_0 = auto_int_local_in_2_0; // @[tile.scala:155:7]
wire auto_int_local_in_1_0_0 = auto_int_local_in_1_0; // @[tile.scala:155:7]
wire auto_int_local_in_1_1_0 = auto_int_local_in_1_1; // @[tile.scala:155:7]
wire auto_int_local_in_0_0_0 = auto_int_local_in_0_0; // @[tile.scala:155:7]
wire auto_hartid_in_0 = auto_hartid_in; // @[tile.scala:155:7]
wire auto_buffer_out_a_bits_corrupt = 1'h0; // @[tile.scala:155:7]
wire auto_buffer_out_c_bits_corrupt = 1'h0; // @[tile.scala:155:7]
wire auto_wfi_out_0 = 1'h0; // @[tile.scala:155:7]
wire auto_cease_out_0 = 1'h0; // @[tile.scala:155:7]
wire auto_halt_out_0 = 1'h0; // @[tile.scala:155:7]
wire auto_trace_core_source_out_group_0_iretire = 1'h0; // @[tile.scala:155:7]
wire auto_trace_core_source_out_group_0_ilastsize = 1'h0; // @[tile.scala:155:7]
wire auto_trace_source_out_insns_0_valid = 1'h0; // @[tile.scala:155:7]
wire auto_trace_source_out_insns_0_exception = 1'h0; // @[tile.scala:155:7]
wire auto_trace_source_out_insns_0_interrupt = 1'h0; // @[tile.scala:155:7]
wire auto_trace_source_out_insns_1_valid = 1'h0; // @[tile.scala:155:7]
wire auto_trace_source_out_insns_1_exception = 1'h0; // @[tile.scala:155:7]
wire auto_trace_source_out_insns_1_interrupt = 1'h0; // @[tile.scala:155:7]
wire auto_trace_source_out_insns_2_valid = 1'h0; // @[tile.scala:155:7]
wire auto_trace_source_out_insns_2_exception = 1'h0; // @[tile.scala:155:7]
wire auto_trace_source_out_insns_2_interrupt = 1'h0; // @[tile.scala:155:7]
wire broadcast_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire broadcast_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire broadcast__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire broadcast_1_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire broadcast_1_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire broadcast_1__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire nexus_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire nexus_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire nexus__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire nexus_1_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire nexus_1_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire nexus_1__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire nexus_1_x1_bundleOut_x_sourceOpt_enable = 1'h0; // @[BaseTile.scala:305:19]
wire nexus_1_x1_bundleOut_x_sourceOpt_stall = 1'h0; // @[BaseTile.scala:305:19]
wire nexus_1_nodeOut_enable = 1'h0; // @[MixedNode.scala:542:17]
wire nexus_1_nodeOut_stall = 1'h0; // @[MixedNode.scala:542:17]
wire nexus_1_defaultWireOpt_enable = 1'h0; // @[BaseTile.scala:305:19]
wire nexus_1_defaultWireOpt_stall = 1'h0; // @[BaseTile.scala:305:19]
wire broadcast_2_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire broadcast_2_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire broadcast_2__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire widget_auto_anon_in_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_c_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_c_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9]
wire widget_anonOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire widget_anonOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire widget_anonIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire widget_anonIn_c_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire widget_1_auto_anon_in_a_bits_source = 1'h0; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_in_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_in_d_bits_source = 1'h0; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_out_a_bits_source = 1'h0; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_out_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_out_d_bits_source = 1'h0; // @[WidthWidget.scala:27:9]
wire widget_1_anonOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17]
wire widget_1_anonOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire widget_1_anonOut_d_bits_source = 1'h0; // @[MixedNode.scala:542:17]
wire widget_1_anonIn_a_bits_source = 1'h0; // @[MixedNode.scala:551:17]
wire widget_1_anonIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire widget_1_anonIn_d_bits_source = 1'h0; // @[MixedNode.scala:551:17]
wire buffer_auto_in_a_bits_corrupt = 1'h0; // @[Buffer.scala:40:9]
wire buffer_auto_in_c_bits_corrupt = 1'h0; // @[Buffer.scala:40:9]
wire buffer_auto_out_a_bits_corrupt = 1'h0; // @[Buffer.scala:40:9]
wire buffer_auto_out_c_bits_corrupt = 1'h0; // @[Buffer.scala:40:9]
wire buffer_nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire buffer_nodeOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire buffer_nodeIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire buffer_nodeIn_c_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire tlOtherMastersNodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire tlOtherMastersNodeOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire tlOtherMastersNodeIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire tlOtherMastersNodeIn_c_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire traceSourceNodeOut_insns_0_valid = 1'h0; // @[MixedNode.scala:542:17]
wire traceSourceNodeOut_insns_0_exception = 1'h0; // @[MixedNode.scala:542:17]
wire traceSourceNodeOut_insns_0_interrupt = 1'h0; // @[MixedNode.scala:542:17]
wire traceSourceNodeOut_insns_1_valid = 1'h0; // @[MixedNode.scala:542:17]
wire traceSourceNodeOut_insns_1_exception = 1'h0; // @[MixedNode.scala:542:17]
wire traceSourceNodeOut_insns_1_interrupt = 1'h0; // @[MixedNode.scala:542:17]
wire traceSourceNodeOut_insns_2_valid = 1'h0; // @[MixedNode.scala:542:17]
wire traceSourceNodeOut_insns_2_exception = 1'h0; // @[MixedNode.scala:542:17]
wire traceSourceNodeOut_insns_2_interrupt = 1'h0; // @[MixedNode.scala:542:17]
wire traceCoreSourceNodeOut_group_0_iretire = 1'h0; // @[MixedNode.scala:542:17]
wire traceCoreSourceNodeOut_group_0_ilastsize = 1'h0; // @[MixedNode.scala:542:17]
wire bundleIn_x_sourceOpt_enable = 1'h0; // @[BaseTile.scala:305:19]
wire bundleIn_x_sourceOpt_stall = 1'h0; // @[BaseTile.scala:305:19]
wire traceAuxSinkNodeIn_enable = 1'h0; // @[MixedNode.scala:551:17]
wire traceAuxSinkNodeIn_stall = 1'h0; // @[MixedNode.scala:551:17]
wire haltNodeOut_0 = 1'h0; // @[MixedNode.scala:542:17]
wire ceaseNodeOut_0 = 1'h0; // @[MixedNode.scala:542:17]
wire wfiNodeOut_0 = 1'h0; // @[MixedNode.scala:542:17]
wire masterNodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire masterNodeOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire masterNodeIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire masterNodeIn_c_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire dCacheTapOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire dCacheTapOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire dCacheTapIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire dCacheTapIn_c_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire [2:0] widget_1_auto_anon_in_a_bits_opcode = 3'h4; // @[WidthWidget.scala:27:9]
wire [2:0] widget_1_auto_anon_out_a_bits_opcode = 3'h4; // @[WidthWidget.scala:27:9]
wire [2:0] widget_1_anonOut_a_bits_opcode = 3'h4; // @[WidthWidget.scala:27:9]
wire [2:0] widget_1_anonIn_a_bits_opcode = 3'h4; // @[WidthWidget.scala:27:9]
wire [3:0] widget_1_auto_anon_in_a_bits_size = 4'h6; // @[WidthWidget.scala:27:9]
wire [3:0] widget_1_auto_anon_out_a_bits_size = 4'h6; // @[WidthWidget.scala:27:9]
wire [3:0] widget_1_anonOut_a_bits_size = 4'h6; // @[WidthWidget.scala:27:9]
wire [3:0] widget_1_anonIn_a_bits_size = 4'h6; // @[WidthWidget.scala:27:9]
wire [15:0] widget_1_auto_anon_in_a_bits_mask = 16'hFFFF; // @[WidthWidget.scala:27:9]
wire [15:0] widget_1_auto_anon_out_a_bits_mask = 16'hFFFF; // @[WidthWidget.scala:27:9]
wire [15:0] widget_1_anonOut_a_bits_mask = 16'hFFFF; // @[WidthWidget.scala:27:9]
wire [15:0] widget_1_anonIn_a_bits_mask = 16'hFFFF; // @[WidthWidget.scala:27:9]
wire [127:0] widget_1_auto_anon_in_a_bits_data = 128'h0; // @[WidthWidget.scala:27:9]
wire [127:0] widget_1_auto_anon_out_a_bits_data = 128'h0; // @[WidthWidget.scala:27:9]
wire [127:0] widget_1_anonOut_a_bits_data = 128'h0; // @[WidthWidget.scala:27:9]
wire [127:0] widget_1_anonIn_a_bits_data = 128'h0; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_in_d_ready = 1'h1; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_out_d_ready = 1'h1; // @[WidthWidget.scala:27:9]
wire widget_1_anonOut_d_ready = 1'h1; // @[WidthWidget.scala:27:9]
wire widget_1_anonIn_d_ready = 1'h1; // @[WidthWidget.scala:27:9]
wire [31:0] auto_reset_vector_in = 32'h10000; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] broadcast_1_auto_in = 32'h10000; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] broadcast_1_auto_out_1 = 32'h10000; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] broadcast_1_auto_out_0 = 32'h10000; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] broadcast_1_nodeIn = 32'h10000; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] broadcast_1_nodeOut = 32'h10000; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] broadcast_1_x1_nodeOut = 32'h10000; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] resetVectorSinkNodeIn = 32'h10000; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] reset_vectorOut = 32'h10000; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] reset_vectorIn = 32'h10000; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] auto_trace_source_out_insns_0_cause = 64'h0; // @[MixedNode.scala:542:17]
wire [63:0] auto_trace_source_out_insns_1_cause = 64'h0; // @[MixedNode.scala:542:17]
wire [63:0] auto_trace_source_out_insns_2_cause = 64'h0; // @[MixedNode.scala:542:17]
wire [63:0] traceSourceNodeOut_insns_0_cause = 64'h0; // @[MixedNode.scala:542:17]
wire [63:0] traceSourceNodeOut_insns_1_cause = 64'h0; // @[MixedNode.scala:542:17]
wire [63:0] traceSourceNodeOut_insns_2_cause = 64'h0; // @[MixedNode.scala:542:17]
wire [2:0] auto_trace_source_out_insns_0_priv = 3'h0; // @[WidthWidget.scala:27:9]
wire [2:0] auto_trace_source_out_insns_1_priv = 3'h0; // @[WidthWidget.scala:27:9]
wire [2:0] auto_trace_source_out_insns_2_priv = 3'h0; // @[WidthWidget.scala:27:9]
wire [2:0] widget_1_auto_anon_in_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9]
wire [2:0] widget_1_auto_anon_out_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9]
wire [2:0] widget_1_anonOut_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9]
wire [2:0] widget_1_anonIn_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9]
wire [2:0] traceSourceNodeOut_insns_0_priv = 3'h0; // @[WidthWidget.scala:27:9]
wire [2:0] traceSourceNodeOut_insns_1_priv = 3'h0; // @[WidthWidget.scala:27:9]
wire [2:0] traceSourceNodeOut_insns_2_priv = 3'h0; // @[WidthWidget.scala:27:9]
wire [39:0] auto_trace_source_out_insns_0_iaddr = 40'h0; // @[MixedNode.scala:542:17]
wire [39:0] auto_trace_source_out_insns_0_tval = 40'h0; // @[MixedNode.scala:542:17]
wire [39:0] auto_trace_source_out_insns_1_iaddr = 40'h0; // @[MixedNode.scala:542:17]
wire [39:0] auto_trace_source_out_insns_1_tval = 40'h0; // @[MixedNode.scala:542:17]
wire [39:0] auto_trace_source_out_insns_2_iaddr = 40'h0; // @[MixedNode.scala:542:17]
wire [39:0] auto_trace_source_out_insns_2_tval = 40'h0; // @[MixedNode.scala:542:17]
wire [39:0] traceSourceNodeOut_insns_0_iaddr = 40'h0; // @[MixedNode.scala:542:17]
wire [39:0] traceSourceNodeOut_insns_0_tval = 40'h0; // @[MixedNode.scala:542:17]
wire [39:0] traceSourceNodeOut_insns_1_iaddr = 40'h0; // @[MixedNode.scala:542:17]
wire [39:0] traceSourceNodeOut_insns_1_tval = 40'h0; // @[MixedNode.scala:542:17]
wire [39:0] traceSourceNodeOut_insns_2_iaddr = 40'h0; // @[MixedNode.scala:542:17]
wire [39:0] traceSourceNodeOut_insns_2_tval = 40'h0; // @[MixedNode.scala:542:17]
wire [3:0] auto_trace_core_source_out_group_0_itype = 4'h0; // @[tile.scala:155:7]
wire [3:0] auto_trace_core_source_out_priv = 4'h0; // @[tile.scala:155:7]
wire [3:0] traceCoreSourceNodeOut_group_0_itype = 4'h0; // @[MixedNode.scala:542:17]
wire [3:0] traceCoreSourceNodeOut_priv = 4'h0; // @[MixedNode.scala:542:17]
wire [31:0] auto_trace_core_source_out_group_0_iaddr = 32'h0; // @[tile.scala:155:7]
wire [31:0] auto_trace_core_source_out_tval = 32'h0; // @[tile.scala:155:7]
wire [31:0] auto_trace_core_source_out_cause = 32'h0; // @[tile.scala:155:7]
wire [31:0] auto_trace_source_out_insns_0_insn = 32'h0; // @[tile.scala:155:7]
wire [31:0] auto_trace_source_out_insns_1_insn = 32'h0; // @[tile.scala:155:7]
wire [31:0] auto_trace_source_out_insns_2_insn = 32'h0; // @[tile.scala:155:7]
wire [31:0] traceSourceNodeOut_insns_0_insn = 32'h0; // @[MixedNode.scala:542:17]
wire [31:0] traceSourceNodeOut_insns_1_insn = 32'h0; // @[MixedNode.scala:542:17]
wire [31:0] traceSourceNodeOut_insns_2_insn = 32'h0; // @[MixedNode.scala:542:17]
wire [31:0] traceCoreSourceNodeOut_group_0_iaddr = 32'h0; // @[MixedNode.scala:542:17]
wire [31:0] traceCoreSourceNodeOut_tval = 32'h0; // @[MixedNode.scala:542:17]
wire [31:0] traceCoreSourceNodeOut_cause = 32'h0; // @[MixedNode.scala:542:17]
wire buffer_auto_out_a_ready = auto_buffer_out_a_ready_0; // @[Buffer.scala:40:9]
wire buffer_auto_out_a_valid; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_out_a_bits_size; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_out_a_bits_source; // @[Buffer.scala:40:9]
wire [31:0] buffer_auto_out_a_bits_address; // @[Buffer.scala:40:9]
wire [15:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala:40:9]
wire [127:0] buffer_auto_out_a_bits_data; // @[Buffer.scala:40:9]
wire buffer_auto_out_b_ready; // @[Buffer.scala:40:9]
wire buffer_auto_out_b_valid = auto_buffer_out_b_valid_0; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_out_b_bits_opcode = auto_buffer_out_b_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] buffer_auto_out_b_bits_param = auto_buffer_out_b_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_out_b_bits_size = auto_buffer_out_b_bits_size_0; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_out_b_bits_source = auto_buffer_out_b_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] buffer_auto_out_b_bits_address = auto_buffer_out_b_bits_address_0; // @[Buffer.scala:40:9]
wire [15:0] buffer_auto_out_b_bits_mask = auto_buffer_out_b_bits_mask_0; // @[Buffer.scala:40:9]
wire [127:0] buffer_auto_out_b_bits_data = auto_buffer_out_b_bits_data_0; // @[Buffer.scala:40:9]
wire buffer_auto_out_b_bits_corrupt = auto_buffer_out_b_bits_corrupt_0; // @[Buffer.scala:40:9]
wire buffer_auto_out_c_ready = auto_buffer_out_c_ready_0; // @[Buffer.scala:40:9]
wire buffer_auto_out_c_valid; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_out_c_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_out_c_bits_param; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_out_c_bits_size; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_out_c_bits_source; // @[Buffer.scala:40:9]
wire [31:0] buffer_auto_out_c_bits_address; // @[Buffer.scala:40:9]
wire [127:0] buffer_auto_out_c_bits_data; // @[Buffer.scala:40:9]
wire buffer_auto_out_d_ready; // @[Buffer.scala:40:9]
wire buffer_auto_out_d_valid = auto_buffer_out_d_valid_0; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_out_d_bits_opcode = auto_buffer_out_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] buffer_auto_out_d_bits_param = auto_buffer_out_d_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_out_d_bits_size = auto_buffer_out_d_bits_size_0; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_out_d_bits_source = auto_buffer_out_d_bits_source_0; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_out_d_bits_sink = auto_buffer_out_d_bits_sink_0; // @[Buffer.scala:40:9]
wire buffer_auto_out_d_bits_denied = auto_buffer_out_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [127:0] buffer_auto_out_d_bits_data = auto_buffer_out_d_bits_data_0; // @[Buffer.scala:40:9]
wire buffer_auto_out_d_bits_corrupt = auto_buffer_out_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire buffer_auto_out_e_ready = auto_buffer_out_e_ready_0; // @[Buffer.scala:40:9]
wire buffer_auto_out_e_valid; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_out_e_bits_sink; // @[Buffer.scala:40:9]
wire x1_int_localIn_2_0 = auto_int_local_in_3_0_0; // @[MixedNode.scala:551:17]
wire x1_int_localIn_1_0 = auto_int_local_in_2_0_0; // @[MixedNode.scala:551:17]
wire x1_int_localIn_0 = auto_int_local_in_1_0_0; // @[MixedNode.scala:551:17]
wire x1_int_localIn_1 = auto_int_local_in_1_1_0; // @[MixedNode.scala:551:17]
wire int_localIn_0 = auto_int_local_in_0_0_0; // @[MixedNode.scala:551:17]
wire [63:0] traceSourceNodeOut_time; // @[MixedNode.scala:542:17]
wire traceSourceNodeOut_custom_rob_empty; // @[MixedNode.scala:542:17]
wire hartidIn = auto_hartid_in_0; // @[MixedNode.scala:551:17]
wire [2:0] auto_buffer_out_a_bits_opcode_0; // @[tile.scala:155:7]
wire [2:0] auto_buffer_out_a_bits_param_0; // @[tile.scala:155:7]
wire [3:0] auto_buffer_out_a_bits_size_0; // @[tile.scala:155:7]
wire [3:0] auto_buffer_out_a_bits_source_0; // @[tile.scala:155:7]
wire [31:0] auto_buffer_out_a_bits_address_0; // @[tile.scala:155:7]
wire [15:0] auto_buffer_out_a_bits_mask_0; // @[tile.scala:155:7]
wire [127:0] auto_buffer_out_a_bits_data_0; // @[tile.scala:155:7]
wire auto_buffer_out_a_valid_0; // @[tile.scala:155:7]
wire auto_buffer_out_b_ready_0; // @[tile.scala:155:7]
wire [2:0] auto_buffer_out_c_bits_opcode_0; // @[tile.scala:155:7]
wire [2:0] auto_buffer_out_c_bits_param_0; // @[tile.scala:155:7]
wire [3:0] auto_buffer_out_c_bits_size_0; // @[tile.scala:155:7]
wire [3:0] auto_buffer_out_c_bits_source_0; // @[tile.scala:155:7]
wire [31:0] auto_buffer_out_c_bits_address_0; // @[tile.scala:155:7]
wire [127:0] auto_buffer_out_c_bits_data_0; // @[tile.scala:155:7]
wire auto_buffer_out_c_valid_0; // @[tile.scala:155:7]
wire auto_buffer_out_d_ready_0; // @[tile.scala:155:7]
wire [3:0] auto_buffer_out_e_bits_sink_0; // @[tile.scala:155:7]
wire auto_buffer_out_e_valid_0; // @[tile.scala:155:7]
wire auto_trace_source_out_custom_rob_empty_0; // @[tile.scala:155:7]
wire [63:0] auto_trace_source_out_time_0; // @[tile.scala:155:7]
wire hartidOut; // @[MixedNode.scala:542:17]
wire broadcast_nodeIn = broadcast_auto_in; // @[MixedNode.scala:551:17]
wire broadcast_nodeOut; // @[MixedNode.scala:542:17]
wire broadcast_auto_out; // @[BundleBridgeNexus.scala:20:9]
wire hartIdSinkNodeIn = broadcast_auto_out; // @[MixedNode.scala:551:17]
assign broadcast_nodeOut = broadcast_nodeIn; // @[MixedNode.scala:542:17, :551:17]
assign broadcast_auto_out = broadcast_nodeOut; // @[MixedNode.scala:542:17]
wire widget_anonIn_a_ready; // @[MixedNode.scala:551:17]
wire widget_anonIn_a_valid = widget_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] widget_anonIn_a_bits_opcode = widget_auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] widget_anonIn_a_bits_param = widget_auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] widget_anonIn_a_bits_size = widget_auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9]
wire [2:0] widget_anonIn_a_bits_source = widget_auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] widget_anonIn_a_bits_address = widget_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9]
wire [15:0] widget_anonIn_a_bits_mask = widget_auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [127:0] widget_anonIn_a_bits_data = widget_auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9]
wire widget_anonIn_b_ready = widget_auto_anon_in_b_ready; // @[WidthWidget.scala:27:9]
wire widget_anonIn_b_valid; // @[MixedNode.scala:551:17]
wire [2:0] widget_anonIn_b_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] widget_anonIn_b_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] widget_anonIn_b_bits_size; // @[MixedNode.scala:551:17]
wire [2:0] widget_anonIn_b_bits_source; // @[MixedNode.scala:551:17]
wire [31:0] widget_anonIn_b_bits_address; // @[MixedNode.scala:551:17]
wire [15:0] widget_anonIn_b_bits_mask; // @[MixedNode.scala:551:17]
wire [127:0] widget_anonIn_b_bits_data; // @[MixedNode.scala:551:17]
wire widget_anonIn_b_bits_corrupt; // @[MixedNode.scala:551:17]
wire widget_anonIn_c_ready; // @[MixedNode.scala:551:17]
wire widget_anonIn_c_valid = widget_auto_anon_in_c_valid; // @[WidthWidget.scala:27:9]
wire [2:0] widget_anonIn_c_bits_opcode = widget_auto_anon_in_c_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] widget_anonIn_c_bits_param = widget_auto_anon_in_c_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] widget_anonIn_c_bits_size = widget_auto_anon_in_c_bits_size; // @[WidthWidget.scala:27:9]
wire [2:0] widget_anonIn_c_bits_source = widget_auto_anon_in_c_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] widget_anonIn_c_bits_address = widget_auto_anon_in_c_bits_address; // @[WidthWidget.scala:27:9]
wire [127:0] widget_anonIn_c_bits_data = widget_auto_anon_in_c_bits_data; // @[WidthWidget.scala:27:9]
wire widget_anonIn_d_ready = widget_auto_anon_in_d_ready; // @[WidthWidget.scala:27:9]
wire widget_anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] widget_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] widget_anonIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] widget_anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [2:0] widget_anonIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [3:0] widget_anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire widget_anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [127:0] widget_anonIn_d_bits_data; // @[MixedNode.scala:551:17]
wire widget_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire widget_anonIn_e_ready; // @[MixedNode.scala:551:17]
wire widget_anonIn_e_valid = widget_auto_anon_in_e_valid; // @[WidthWidget.scala:27:9]
wire [3:0] widget_anonIn_e_bits_sink = widget_auto_anon_in_e_bits_sink; // @[WidthWidget.scala:27:9]
wire dCacheTapIn_a_ready; // @[MixedNode.scala:551:17]
wire widget_anonOut_a_ready = widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9]
wire widget_anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] widget_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire dCacheTapIn_a_valid = widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] widget_anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] dCacheTapIn_a_bits_opcode = widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [3:0] widget_anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [2:0] dCacheTapIn_a_bits_param = widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] widget_anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [3:0] dCacheTapIn_a_bits_size = widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9]
wire [31:0] widget_anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [2:0] dCacheTapIn_a_bits_source = widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9]
wire [15:0] widget_anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [31:0] dCacheTapIn_a_bits_address = widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9]
wire [127:0] widget_anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire [15:0] dCacheTapIn_a_bits_mask = widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [127:0] dCacheTapIn_a_bits_data = widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9]
wire widget_anonOut_b_ready; // @[MixedNode.scala:542:17]
wire dCacheTapIn_b_ready = widget_auto_anon_out_b_ready; // @[WidthWidget.scala:27:9]
wire dCacheTapIn_b_valid; // @[MixedNode.scala:551:17]
wire widget_anonOut_b_valid = widget_auto_anon_out_b_valid; // @[WidthWidget.scala:27:9]
wire [2:0] dCacheTapIn_b_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] widget_anonOut_b_bits_opcode = widget_auto_anon_out_b_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] dCacheTapIn_b_bits_param; // @[MixedNode.scala:551:17]
wire [1:0] widget_anonOut_b_bits_param = widget_auto_anon_out_b_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] dCacheTapIn_b_bits_size; // @[MixedNode.scala:551:17]
wire [3:0] widget_anonOut_b_bits_size = widget_auto_anon_out_b_bits_size; // @[WidthWidget.scala:27:9]
wire [2:0] dCacheTapIn_b_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] widget_anonOut_b_bits_source = widget_auto_anon_out_b_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] dCacheTapIn_b_bits_address; // @[MixedNode.scala:551:17]
wire [31:0] widget_anonOut_b_bits_address = widget_auto_anon_out_b_bits_address; // @[WidthWidget.scala:27:9]
wire [15:0] dCacheTapIn_b_bits_mask; // @[MixedNode.scala:551:17]
wire [15:0] widget_anonOut_b_bits_mask = widget_auto_anon_out_b_bits_mask; // @[WidthWidget.scala:27:9]
wire [127:0] dCacheTapIn_b_bits_data; // @[MixedNode.scala:551:17]
wire [127:0] widget_anonOut_b_bits_data = widget_auto_anon_out_b_bits_data; // @[WidthWidget.scala:27:9]
wire dCacheTapIn_b_bits_corrupt; // @[MixedNode.scala:551:17]
wire widget_anonOut_b_bits_corrupt = widget_auto_anon_out_b_bits_corrupt; // @[WidthWidget.scala:27:9]
wire dCacheTapIn_c_ready; // @[MixedNode.scala:551:17]
wire widget_anonOut_c_ready = widget_auto_anon_out_c_ready; // @[WidthWidget.scala:27:9]
wire widget_anonOut_c_valid; // @[MixedNode.scala:542:17]
wire [2:0] widget_anonOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire dCacheTapIn_c_valid = widget_auto_anon_out_c_valid; // @[WidthWidget.scala:27:9]
wire [2:0] widget_anonOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] dCacheTapIn_c_bits_opcode = widget_auto_anon_out_c_bits_opcode; // @[WidthWidget.scala:27:9]
wire [3:0] widget_anonOut_c_bits_size; // @[MixedNode.scala:542:17]
wire [2:0] dCacheTapIn_c_bits_param = widget_auto_anon_out_c_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] widget_anonOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [3:0] dCacheTapIn_c_bits_size = widget_auto_anon_out_c_bits_size; // @[WidthWidget.scala:27:9]
wire [31:0] widget_anonOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [2:0] dCacheTapIn_c_bits_source = widget_auto_anon_out_c_bits_source; // @[WidthWidget.scala:27:9]
wire [127:0] widget_anonOut_c_bits_data; // @[MixedNode.scala:542:17]
wire [31:0] dCacheTapIn_c_bits_address = widget_auto_anon_out_c_bits_address; // @[WidthWidget.scala:27:9]
wire [127:0] dCacheTapIn_c_bits_data = widget_auto_anon_out_c_bits_data; // @[WidthWidget.scala:27:9]
wire widget_anonOut_d_ready; // @[MixedNode.scala:542:17]
wire dCacheTapIn_d_ready = widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9]
wire dCacheTapIn_d_valid; // @[MixedNode.scala:551:17]
wire widget_anonOut_d_valid = widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] dCacheTapIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] widget_anonOut_d_bits_opcode = widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] dCacheTapIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [1:0] widget_anonOut_d_bits_param = widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] dCacheTapIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [3:0] widget_anonOut_d_bits_size = widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9]
wire [2:0] dCacheTapIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] widget_anonOut_d_bits_source = widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9]
wire [3:0] dCacheTapIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire [3:0] widget_anonOut_d_bits_sink = widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9]
wire dCacheTapIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire widget_anonOut_d_bits_denied = widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [127:0] dCacheTapIn_d_bits_data; // @[MixedNode.scala:551:17]
wire [127:0] widget_anonOut_d_bits_data = widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9]
wire dCacheTapIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire widget_anonOut_d_bits_corrupt = widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire dCacheTapIn_e_ready; // @[MixedNode.scala:551:17]
wire widget_anonOut_e_ready = widget_auto_anon_out_e_ready; // @[WidthWidget.scala:27:9]
wire widget_anonOut_e_valid; // @[MixedNode.scala:542:17]
wire [3:0] widget_anonOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire dCacheTapIn_e_valid = widget_auto_anon_out_e_valid; // @[WidthWidget.scala:27:9]
wire [3:0] dCacheTapIn_e_bits_sink = widget_auto_anon_out_e_bits_sink; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_in_b_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] widget_auto_anon_in_b_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_in_b_bits_size; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_in_b_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] widget_auto_anon_in_b_bits_address; // @[WidthWidget.scala:27:9]
wire [15:0] widget_auto_anon_in_b_bits_mask; // @[WidthWidget.scala:27:9]
wire [127:0] widget_auto_anon_in_b_bits_data; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_b_bits_corrupt; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_b_valid; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_c_ready; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] widget_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [127:0] widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_e_ready; // @[WidthWidget.scala:27:9]
assign widget_anonIn_a_ready = widget_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign widget_auto_anon_out_a_valid = widget_anonOut_a_valid; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_a_bits_opcode = widget_anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_a_bits_param = widget_anonOut_a_bits_param; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_a_bits_size = widget_anonOut_a_bits_size; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_a_bits_source = widget_anonOut_a_bits_source; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_a_bits_address = widget_anonOut_a_bits_address; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_a_bits_mask = widget_anonOut_a_bits_mask; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_a_bits_data = widget_anonOut_a_bits_data; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_b_ready = widget_anonOut_b_ready; // @[WidthWidget.scala:27:9]
assign widget_anonIn_b_valid = widget_anonOut_b_valid; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_b_bits_opcode = widget_anonOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_b_bits_param = widget_anonOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_b_bits_size = widget_anonOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_b_bits_source = widget_anonOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_b_bits_address = widget_anonOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_b_bits_mask = widget_anonOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_b_bits_data = widget_anonOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_b_bits_corrupt = widget_anonOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_c_ready = widget_anonOut_c_ready; // @[MixedNode.scala:542:17, :551:17]
assign widget_auto_anon_out_c_valid = widget_anonOut_c_valid; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_c_bits_opcode = widget_anonOut_c_bits_opcode; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_c_bits_param = widget_anonOut_c_bits_param; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_c_bits_size = widget_anonOut_c_bits_size; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_c_bits_source = widget_anonOut_c_bits_source; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_c_bits_address = widget_anonOut_c_bits_address; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_c_bits_data = widget_anonOut_c_bits_data; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_d_ready = widget_anonOut_d_ready; // @[WidthWidget.scala:27:9]
assign widget_anonIn_d_valid = widget_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_d_bits_opcode = widget_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_d_bits_param = widget_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_d_bits_size = widget_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_d_bits_source = widget_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_d_bits_sink = widget_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_d_bits_denied = widget_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_d_bits_data = widget_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_d_bits_corrupt = widget_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_e_ready = widget_anonOut_e_ready; // @[MixedNode.scala:542:17, :551:17]
assign widget_auto_anon_out_e_valid = widget_anonOut_e_valid; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_e_bits_sink = widget_anonOut_e_bits_sink; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_a_ready = widget_anonIn_a_ready; // @[WidthWidget.scala:27:9]
assign widget_anonOut_a_valid = widget_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_a_bits_opcode = widget_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_a_bits_param = widget_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_a_bits_size = widget_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_a_bits_source = widget_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_a_bits_address = widget_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_a_bits_mask = widget_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_a_bits_data = widget_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_b_ready = widget_anonIn_b_ready; // @[MixedNode.scala:542:17, :551:17]
assign widget_auto_anon_in_b_valid = widget_anonIn_b_valid; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_b_bits_opcode = widget_anonIn_b_bits_opcode; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_b_bits_param = widget_anonIn_b_bits_param; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_b_bits_size = widget_anonIn_b_bits_size; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_b_bits_source = widget_anonIn_b_bits_source; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_b_bits_address = widget_anonIn_b_bits_address; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_b_bits_mask = widget_anonIn_b_bits_mask; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_b_bits_data = widget_anonIn_b_bits_data; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_b_bits_corrupt = widget_anonIn_b_bits_corrupt; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_c_ready = widget_anonIn_c_ready; // @[WidthWidget.scala:27:9]
assign widget_anonOut_c_valid = widget_anonIn_c_valid; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_c_bits_opcode = widget_anonIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_c_bits_param = widget_anonIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_c_bits_size = widget_anonIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_c_bits_source = widget_anonIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_c_bits_address = widget_anonIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_c_bits_data = widget_anonIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_d_ready = widget_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign widget_auto_anon_in_d_valid = widget_anonIn_d_valid; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_d_bits_opcode = widget_anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_d_bits_param = widget_anonIn_d_bits_param; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_d_bits_size = widget_anonIn_d_bits_size; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_d_bits_source = widget_anonIn_d_bits_source; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_d_bits_sink = widget_anonIn_d_bits_sink; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_d_bits_denied = widget_anonIn_d_bits_denied; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_d_bits_data = widget_anonIn_d_bits_data; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_d_bits_corrupt = widget_anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_e_ready = widget_anonIn_e_ready; // @[WidthWidget.scala:27:9]
assign widget_anonOut_e_valid = widget_anonIn_e_valid; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_e_bits_sink = widget_anonIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire widget_1_anonIn_a_ready; // @[MixedNode.scala:551:17]
wire widget_1_anonIn_a_valid = widget_1_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9]
wire [31:0] widget_1_anonIn_a_bits_address = widget_1_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9]
wire widget_1_anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] widget_1_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] widget_1_anonIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] widget_1_anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [3:0] widget_1_anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire widget_1_anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [127:0] widget_1_anonIn_d_bits_data; // @[MixedNode.scala:551:17]
wire widget_1_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire widget_1_anonOut_a_ready = widget_1_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9]
wire widget_1_anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [31:0] widget_1_anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire widget_1_anonOut_d_valid = widget_1_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] widget_1_anonOut_d_bits_opcode = widget_1_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] widget_1_anonOut_d_bits_param = widget_1_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] widget_1_anonOut_d_bits_size = widget_1_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9]
wire [3:0] widget_1_anonOut_d_bits_sink = widget_1_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9]
wire widget_1_anonOut_d_bits_denied = widget_1_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [127:0] widget_1_anonOut_d_bits_data = widget_1_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9]
wire widget_1_anonOut_d_bits_corrupt = widget_1_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9]
wire [2:0] widget_1_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] widget_1_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] widget_1_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9]
wire [3:0] widget_1_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [127:0] widget_1_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9]
wire [31:0] widget_1_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9]
assign widget_1_anonIn_a_ready = widget_1_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_auto_anon_out_a_valid = widget_1_anonOut_a_valid; // @[WidthWidget.scala:27:9]
assign widget_1_auto_anon_out_a_bits_address = widget_1_anonOut_a_bits_address; // @[WidthWidget.scala:27:9]
assign widget_1_anonIn_d_valid = widget_1_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_anonIn_d_bits_opcode = widget_1_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_anonIn_d_bits_param = widget_1_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_anonIn_d_bits_size = widget_1_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_anonIn_d_bits_sink = widget_1_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_anonIn_d_bits_denied = widget_1_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_anonIn_d_bits_data = widget_1_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_anonIn_d_bits_corrupt = widget_1_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_auto_anon_in_a_ready = widget_1_anonIn_a_ready; // @[WidthWidget.scala:27:9]
assign widget_1_anonOut_a_valid = widget_1_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_anonOut_a_bits_address = widget_1_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_auto_anon_in_d_valid = widget_1_anonIn_d_valid; // @[WidthWidget.scala:27:9]
assign widget_1_auto_anon_in_d_bits_opcode = widget_1_anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9]
assign widget_1_auto_anon_in_d_bits_param = widget_1_anonIn_d_bits_param; // @[WidthWidget.scala:27:9]
assign widget_1_auto_anon_in_d_bits_size = widget_1_anonIn_d_bits_size; // @[WidthWidget.scala:27:9]
assign widget_1_auto_anon_in_d_bits_sink = widget_1_anonIn_d_bits_sink; // @[WidthWidget.scala:27:9]
assign widget_1_auto_anon_in_d_bits_denied = widget_1_anonIn_d_bits_denied; // @[WidthWidget.scala:27:9]
assign widget_1_auto_anon_in_d_bits_data = widget_1_anonIn_d_bits_data; // @[WidthWidget.scala:27:9]
assign widget_1_auto_anon_in_d_bits_corrupt = widget_1_anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire buffer_nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire masterNodeOut_a_ready = buffer_auto_in_a_ready; // @[Buffer.scala:40:9]
wire masterNodeOut_a_valid; // @[MixedNode.scala:542:17]
wire buffer_nodeIn_a_valid = buffer_auto_in_a_valid; // @[Buffer.scala:40:9]
wire [2:0] masterNodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] buffer_nodeIn_a_bits_opcode = buffer_auto_in_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] masterNodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] buffer_nodeIn_a_bits_param = buffer_auto_in_a_bits_param; // @[Buffer.scala:40:9]
wire [3:0] masterNodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [3:0] buffer_nodeIn_a_bits_size = buffer_auto_in_a_bits_size; // @[Buffer.scala:40:9]
wire [3:0] masterNodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [3:0] buffer_nodeIn_a_bits_source = buffer_auto_in_a_bits_source; // @[Buffer.scala:40:9]
wire [31:0] masterNodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [31:0] buffer_nodeIn_a_bits_address = buffer_auto_in_a_bits_address; // @[Buffer.scala:40:9]
wire [15:0] masterNodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [15:0] buffer_nodeIn_a_bits_mask = buffer_auto_in_a_bits_mask; // @[Buffer.scala:40:9]
wire [127:0] masterNodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire [127:0] buffer_nodeIn_a_bits_data = buffer_auto_in_a_bits_data; // @[Buffer.scala:40:9]
wire masterNodeOut_b_ready; // @[MixedNode.scala:542:17]
wire buffer_nodeIn_b_ready = buffer_auto_in_b_ready; // @[Buffer.scala:40:9]
wire buffer_nodeIn_b_valid; // @[MixedNode.scala:551:17]
wire [2:0] buffer_nodeIn_b_bits_opcode; // @[MixedNode.scala:551:17]
wire masterNodeOut_b_valid = buffer_auto_in_b_valid; // @[Buffer.scala:40:9]
wire [1:0] buffer_nodeIn_b_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] masterNodeOut_b_bits_opcode = buffer_auto_in_b_bits_opcode; // @[Buffer.scala:40:9]
wire [3:0] buffer_nodeIn_b_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] masterNodeOut_b_bits_param = buffer_auto_in_b_bits_param; // @[Buffer.scala:40:9]
wire [3:0] buffer_nodeIn_b_bits_source; // @[MixedNode.scala:551:17]
wire [3:0] masterNodeOut_b_bits_size = buffer_auto_in_b_bits_size; // @[Buffer.scala:40:9]
wire [31:0] buffer_nodeIn_b_bits_address; // @[MixedNode.scala:551:17]
wire [3:0] masterNodeOut_b_bits_source = buffer_auto_in_b_bits_source; // @[Buffer.scala:40:9]
wire [15:0] buffer_nodeIn_b_bits_mask; // @[MixedNode.scala:551:17]
wire [31:0] masterNodeOut_b_bits_address = buffer_auto_in_b_bits_address; // @[Buffer.scala:40:9]
wire [127:0] buffer_nodeIn_b_bits_data; // @[MixedNode.scala:551:17]
wire [15:0] masterNodeOut_b_bits_mask = buffer_auto_in_b_bits_mask; // @[Buffer.scala:40:9]
wire buffer_nodeIn_b_bits_corrupt; // @[MixedNode.scala:551:17]
wire [127:0] masterNodeOut_b_bits_data = buffer_auto_in_b_bits_data; // @[Buffer.scala:40:9]
wire buffer_nodeIn_c_ready; // @[MixedNode.scala:551:17]
wire masterNodeOut_b_bits_corrupt = buffer_auto_in_b_bits_corrupt; // @[Buffer.scala:40:9]
wire masterNodeOut_c_ready = buffer_auto_in_c_ready; // @[Buffer.scala:40:9]
wire masterNodeOut_c_valid; // @[MixedNode.scala:542:17]
wire buffer_nodeIn_c_valid = buffer_auto_in_c_valid; // @[Buffer.scala:40:9]
wire [2:0] masterNodeOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] buffer_nodeIn_c_bits_opcode = buffer_auto_in_c_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] masterNodeOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] buffer_nodeIn_c_bits_param = buffer_auto_in_c_bits_param; // @[Buffer.scala:40:9]
wire [3:0] masterNodeOut_c_bits_size; // @[MixedNode.scala:542:17]
wire [3:0] buffer_nodeIn_c_bits_size = buffer_auto_in_c_bits_size; // @[Buffer.scala:40:9]
wire [3:0] masterNodeOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [3:0] buffer_nodeIn_c_bits_source = buffer_auto_in_c_bits_source; // @[Buffer.scala:40:9]
wire [31:0] masterNodeOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [31:0] buffer_nodeIn_c_bits_address = buffer_auto_in_c_bits_address; // @[Buffer.scala:40:9]
wire [127:0] masterNodeOut_c_bits_data; // @[MixedNode.scala:542:17]
wire [127:0] buffer_nodeIn_c_bits_data = buffer_auto_in_c_bits_data; // @[Buffer.scala:40:9]
wire masterNodeOut_d_ready; // @[MixedNode.scala:542:17]
wire buffer_nodeIn_d_ready = buffer_auto_in_d_ready; // @[Buffer.scala:40:9]
wire buffer_nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] buffer_nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire masterNodeOut_d_valid = buffer_auto_in_d_valid; // @[Buffer.scala:40:9]
wire [1:0] buffer_nodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] masterNodeOut_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[Buffer.scala:40:9]
wire [3:0] buffer_nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] masterNodeOut_d_bits_param = buffer_auto_in_d_bits_param; // @[Buffer.scala:40:9]
wire [3:0] buffer_nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [3:0] masterNodeOut_d_bits_size = buffer_auto_in_d_bits_size; // @[Buffer.scala:40:9]
wire [3:0] buffer_nodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire [3:0] masterNodeOut_d_bits_source = buffer_auto_in_d_bits_source; // @[Buffer.scala:40:9]
wire buffer_nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [3:0] masterNodeOut_d_bits_sink = buffer_auto_in_d_bits_sink; // @[Buffer.scala:40:9]
wire [127:0] buffer_nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire masterNodeOut_d_bits_denied = buffer_auto_in_d_bits_denied; // @[Buffer.scala:40:9]
wire buffer_nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire [127:0] masterNodeOut_d_bits_data = buffer_auto_in_d_bits_data; // @[Buffer.scala:40:9]
wire buffer_nodeIn_e_ready; // @[MixedNode.scala:551:17]
wire masterNodeOut_d_bits_corrupt = buffer_auto_in_d_bits_corrupt; // @[Buffer.scala:40:9]
wire masterNodeOut_e_ready = buffer_auto_in_e_ready; // @[Buffer.scala:40:9]
wire masterNodeOut_e_valid; // @[MixedNode.scala:542:17]
wire buffer_nodeIn_e_valid = buffer_auto_in_e_valid; // @[Buffer.scala:40:9]
wire [3:0] masterNodeOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire [3:0] buffer_nodeIn_e_bits_sink = buffer_auto_in_e_bits_sink; // @[Buffer.scala:40:9]
wire buffer_nodeOut_a_ready = buffer_auto_out_a_ready; // @[Buffer.scala:40:9]
wire buffer_nodeOut_a_valid; // @[MixedNode.scala:542:17]
assign auto_buffer_out_a_valid_0 = buffer_auto_out_a_valid; // @[Buffer.scala:40:9]
wire [2:0] buffer_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
assign auto_buffer_out_a_bits_opcode_0 = buffer_auto_out_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] buffer_nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
assign auto_buffer_out_a_bits_param_0 = buffer_auto_out_a_bits_param; // @[Buffer.scala:40:9]
wire [3:0] buffer_nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
assign auto_buffer_out_a_bits_size_0 = buffer_auto_out_a_bits_size; // @[Buffer.scala:40:9]
wire [3:0] buffer_nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
assign auto_buffer_out_a_bits_source_0 = buffer_auto_out_a_bits_source; // @[Buffer.scala:40:9]
wire [31:0] buffer_nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
assign auto_buffer_out_a_bits_address_0 = buffer_auto_out_a_bits_address; // @[Buffer.scala:40:9]
wire [15:0] buffer_nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
assign auto_buffer_out_a_bits_mask_0 = buffer_auto_out_a_bits_mask; // @[Buffer.scala:40:9]
wire [127:0] buffer_nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
assign auto_buffer_out_a_bits_data_0 = buffer_auto_out_a_bits_data; // @[Buffer.scala:40:9]
wire buffer_nodeOut_b_ready; // @[MixedNode.scala:542:17]
assign auto_buffer_out_b_ready_0 = buffer_auto_out_b_ready; // @[Buffer.scala:40:9]
wire buffer_nodeOut_b_valid = buffer_auto_out_b_valid; // @[Buffer.scala:40:9]
wire [2:0] buffer_nodeOut_b_bits_opcode = buffer_auto_out_b_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] buffer_nodeOut_b_bits_param = buffer_auto_out_b_bits_param; // @[Buffer.scala:40:9]
wire [3:0] buffer_nodeOut_b_bits_size = buffer_auto_out_b_bits_size; // @[Buffer.scala:40:9]
wire [3:0] buffer_nodeOut_b_bits_source = buffer_auto_out_b_bits_source; // @[Buffer.scala:40:9]
wire [31:0] buffer_nodeOut_b_bits_address = buffer_auto_out_b_bits_address; // @[Buffer.scala:40:9]
wire [15:0] buffer_nodeOut_b_bits_mask = buffer_auto_out_b_bits_mask; // @[Buffer.scala:40:9]
wire [127:0] buffer_nodeOut_b_bits_data = buffer_auto_out_b_bits_data; // @[Buffer.scala:40:9]
wire buffer_nodeOut_b_bits_corrupt = buffer_auto_out_b_bits_corrupt; // @[Buffer.scala:40:9]
wire buffer_nodeOut_c_ready = buffer_auto_out_c_ready; // @[Buffer.scala:40:9]
wire buffer_nodeOut_c_valid; // @[MixedNode.scala:542:17]
assign auto_buffer_out_c_valid_0 = buffer_auto_out_c_valid; // @[Buffer.scala:40:9]
wire [2:0] buffer_nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17]
assign auto_buffer_out_c_bits_opcode_0 = buffer_auto_out_c_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] buffer_nodeOut_c_bits_param; // @[MixedNode.scala:542:17]
assign auto_buffer_out_c_bits_param_0 = buffer_auto_out_c_bits_param; // @[Buffer.scala:40:9]
wire [3:0] buffer_nodeOut_c_bits_size; // @[MixedNode.scala:542:17]
assign auto_buffer_out_c_bits_size_0 = buffer_auto_out_c_bits_size; // @[Buffer.scala:40:9]
wire [3:0] buffer_nodeOut_c_bits_source; // @[MixedNode.scala:542:17]
assign auto_buffer_out_c_bits_source_0 = buffer_auto_out_c_bits_source; // @[Buffer.scala:40:9]
wire [31:0] buffer_nodeOut_c_bits_address; // @[MixedNode.scala:542:17]
assign auto_buffer_out_c_bits_address_0 = buffer_auto_out_c_bits_address; // @[Buffer.scala:40:9]
wire [127:0] buffer_nodeOut_c_bits_data; // @[MixedNode.scala:542:17]
assign auto_buffer_out_c_bits_data_0 = buffer_auto_out_c_bits_data; // @[Buffer.scala:40:9]
wire buffer_nodeOut_d_ready; // @[MixedNode.scala:542:17]
assign auto_buffer_out_d_ready_0 = buffer_auto_out_d_ready; // @[Buffer.scala:40:9]
wire buffer_nodeOut_d_valid = buffer_auto_out_d_valid; // @[Buffer.scala:40:9]
wire [2:0] buffer_nodeOut_d_bits_opcode = buffer_auto_out_d_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] buffer_nodeOut_d_bits_param = buffer_auto_out_d_bits_param; // @[Buffer.scala:40:9]
wire [3:0] buffer_nodeOut_d_bits_size = buffer_auto_out_d_bits_size; // @[Buffer.scala:40:9]
wire [3:0] buffer_nodeOut_d_bits_source = buffer_auto_out_d_bits_source; // @[Buffer.scala:40:9]
wire [3:0] buffer_nodeOut_d_bits_sink = buffer_auto_out_d_bits_sink; // @[Buffer.scala:40:9]
wire buffer_nodeOut_d_bits_denied = buffer_auto_out_d_bits_denied; // @[Buffer.scala:40:9]
wire [127:0] buffer_nodeOut_d_bits_data = buffer_auto_out_d_bits_data; // @[Buffer.scala:40:9]
wire buffer_nodeOut_d_bits_corrupt = buffer_auto_out_d_bits_corrupt; // @[Buffer.scala:40:9]
wire buffer_nodeOut_e_ready = buffer_auto_out_e_ready; // @[Buffer.scala:40:9]
wire buffer_nodeOut_e_valid; // @[MixedNode.scala:542:17]
assign auto_buffer_out_e_valid_0 = buffer_auto_out_e_valid; // @[Buffer.scala:40:9]
wire [3:0] buffer_nodeOut_e_bits_sink; // @[MixedNode.scala:542:17]
assign auto_buffer_out_e_bits_sink_0 = buffer_auto_out_e_bits_sink; // @[Buffer.scala:40:9]
assign buffer_nodeIn_a_ready = buffer_nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign buffer_auto_out_a_valid = buffer_nodeOut_a_valid; // @[Buffer.scala:40:9]
assign buffer_auto_out_a_bits_opcode = buffer_nodeOut_a_bits_opcode; // @[Buffer.scala:40:9]
assign buffer_auto_out_a_bits_param = buffer_nodeOut_a_bits_param; // @[Buffer.scala:40:9]
assign buffer_auto_out_a_bits_size = buffer_nodeOut_a_bits_size; // @[Buffer.scala:40:9]
assign buffer_auto_out_a_bits_source = buffer_nodeOut_a_bits_source; // @[Buffer.scala:40:9]
assign buffer_auto_out_a_bits_address = buffer_nodeOut_a_bits_address; // @[Buffer.scala:40:9]
assign buffer_auto_out_a_bits_mask = buffer_nodeOut_a_bits_mask; // @[Buffer.scala:40:9]
assign buffer_auto_out_a_bits_data = buffer_nodeOut_a_bits_data; // @[Buffer.scala:40:9]
assign buffer_auto_out_b_ready = buffer_nodeOut_b_ready; // @[Buffer.scala:40:9]
assign buffer_nodeIn_b_valid = buffer_nodeOut_b_valid; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_b_bits_opcode = buffer_nodeOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_b_bits_param = buffer_nodeOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_b_bits_size = buffer_nodeOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_b_bits_source = buffer_nodeOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_b_bits_address = buffer_nodeOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_b_bits_mask = buffer_nodeOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_b_bits_data = buffer_nodeOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_b_bits_corrupt = buffer_nodeOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_c_ready = buffer_nodeOut_c_ready; // @[MixedNode.scala:542:17, :551:17]
assign buffer_auto_out_c_valid = buffer_nodeOut_c_valid; // @[Buffer.scala:40:9]
assign buffer_auto_out_c_bits_opcode = buffer_nodeOut_c_bits_opcode; // @[Buffer.scala:40:9]
assign buffer_auto_out_c_bits_param = buffer_nodeOut_c_bits_param; // @[Buffer.scala:40:9]
assign buffer_auto_out_c_bits_size = buffer_nodeOut_c_bits_size; // @[Buffer.scala:40:9]
assign buffer_auto_out_c_bits_source = buffer_nodeOut_c_bits_source; // @[Buffer.scala:40:9]
assign buffer_auto_out_c_bits_address = buffer_nodeOut_c_bits_address; // @[Buffer.scala:40:9]
assign buffer_auto_out_c_bits_data = buffer_nodeOut_c_bits_data; // @[Buffer.scala:40:9]
assign buffer_auto_out_d_ready = buffer_nodeOut_d_ready; // @[Buffer.scala:40:9]
assign buffer_nodeIn_d_valid = buffer_nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_d_bits_opcode = buffer_nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_d_bits_param = buffer_nodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_d_bits_size = buffer_nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_d_bits_source = buffer_nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_d_bits_sink = buffer_nodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_d_bits_denied = buffer_nodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_d_bits_data = buffer_nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_d_bits_corrupt = buffer_nodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_e_ready = buffer_nodeOut_e_ready; // @[MixedNode.scala:542:17, :551:17]
assign buffer_auto_out_e_valid = buffer_nodeOut_e_valid; // @[Buffer.scala:40:9]
assign buffer_auto_out_e_bits_sink = buffer_nodeOut_e_bits_sink; // @[Buffer.scala:40:9]
assign buffer_auto_in_a_ready = buffer_nodeIn_a_ready; // @[Buffer.scala:40:9]
assign buffer_nodeOut_a_valid = buffer_nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_opcode = buffer_nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_param = buffer_nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_size = buffer_nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_source = buffer_nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_address = buffer_nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_mask = buffer_nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_data = buffer_nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_b_ready = buffer_nodeIn_b_ready; // @[MixedNode.scala:542:17, :551:17]
assign buffer_auto_in_b_valid = buffer_nodeIn_b_valid; // @[Buffer.scala:40:9]
assign buffer_auto_in_b_bits_opcode = buffer_nodeIn_b_bits_opcode; // @[Buffer.scala:40:9]
assign buffer_auto_in_b_bits_param = buffer_nodeIn_b_bits_param; // @[Buffer.scala:40:9]
assign buffer_auto_in_b_bits_size = buffer_nodeIn_b_bits_size; // @[Buffer.scala:40:9]
assign buffer_auto_in_b_bits_source = buffer_nodeIn_b_bits_source; // @[Buffer.scala:40:9]
assign buffer_auto_in_b_bits_address = buffer_nodeIn_b_bits_address; // @[Buffer.scala:40:9]
assign buffer_auto_in_b_bits_mask = buffer_nodeIn_b_bits_mask; // @[Buffer.scala:40:9]
assign buffer_auto_in_b_bits_data = buffer_nodeIn_b_bits_data; // @[Buffer.scala:40:9]
assign buffer_auto_in_b_bits_corrupt = buffer_nodeIn_b_bits_corrupt; // @[Buffer.scala:40:9]
assign buffer_auto_in_c_ready = buffer_nodeIn_c_ready; // @[Buffer.scala:40:9]
assign buffer_nodeOut_c_valid = buffer_nodeIn_c_valid; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_c_bits_opcode = buffer_nodeIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_c_bits_param = buffer_nodeIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_c_bits_size = buffer_nodeIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_c_bits_source = buffer_nodeIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_c_bits_address = buffer_nodeIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_c_bits_data = buffer_nodeIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_d_ready = buffer_nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign buffer_auto_in_d_valid = buffer_nodeIn_d_valid; // @[Buffer.scala:40:9]
assign buffer_auto_in_d_bits_opcode = buffer_nodeIn_d_bits_opcode; // @[Buffer.scala:40:9]
assign buffer_auto_in_d_bits_param = buffer_nodeIn_d_bits_param; // @[Buffer.scala:40:9]
assign buffer_auto_in_d_bits_size = buffer_nodeIn_d_bits_size; // @[Buffer.scala:40:9]
assign buffer_auto_in_d_bits_source = buffer_nodeIn_d_bits_source; // @[Buffer.scala:40:9]
assign buffer_auto_in_d_bits_sink = buffer_nodeIn_d_bits_sink; // @[Buffer.scala:40:9]
assign buffer_auto_in_d_bits_denied = buffer_nodeIn_d_bits_denied; // @[Buffer.scala:40:9]
assign buffer_auto_in_d_bits_data = buffer_nodeIn_d_bits_data; // @[Buffer.scala:40:9]
assign buffer_auto_in_d_bits_corrupt = buffer_nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9]
assign buffer_auto_in_e_ready = buffer_nodeIn_e_ready; // @[Buffer.scala:40:9]
assign buffer_nodeOut_e_valid = buffer_nodeIn_e_valid; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_e_bits_sink = buffer_nodeIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire masterNodeIn_a_ready; // @[MixedNode.scala:551:17]
wire tlOtherMastersNodeIn_a_ready = tlOtherMastersNodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire tlOtherMastersNodeIn_a_valid; // @[MixedNode.scala:551:17]
wire [2:0] tlOtherMastersNodeIn_a_bits_opcode; // @[MixedNode.scala:551:17]
wire masterNodeIn_a_valid = tlOtherMastersNodeOut_a_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] tlOtherMastersNodeIn_a_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] masterNodeIn_a_bits_opcode = tlOtherMastersNodeOut_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] tlOtherMastersNodeIn_a_bits_size; // @[MixedNode.scala:551:17]
wire [2:0] masterNodeIn_a_bits_param = tlOtherMastersNodeOut_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] tlOtherMastersNodeIn_a_bits_source; // @[MixedNode.scala:551:17]
wire [3:0] masterNodeIn_a_bits_size = tlOtherMastersNodeOut_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] tlOtherMastersNodeIn_a_bits_address; // @[MixedNode.scala:551:17]
wire [3:0] masterNodeIn_a_bits_source = tlOtherMastersNodeOut_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [15:0] tlOtherMastersNodeIn_a_bits_mask; // @[MixedNode.scala:551:17]
wire [31:0] masterNodeIn_a_bits_address = tlOtherMastersNodeOut_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [127:0] tlOtherMastersNodeIn_a_bits_data; // @[MixedNode.scala:551:17]
wire [15:0] masterNodeIn_a_bits_mask = tlOtherMastersNodeOut_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
wire [127:0] masterNodeIn_a_bits_data = tlOtherMastersNodeOut_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire tlOtherMastersNodeIn_b_ready; // @[MixedNode.scala:551:17]
wire masterNodeIn_b_ready = tlOtherMastersNodeOut_b_ready; // @[MixedNode.scala:542:17, :551:17]
wire masterNodeIn_b_valid; // @[MixedNode.scala:551:17]
wire tlOtherMastersNodeIn_b_valid = tlOtherMastersNodeOut_b_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] masterNodeIn_b_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] tlOtherMastersNodeIn_b_bits_opcode = tlOtherMastersNodeOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] masterNodeIn_b_bits_param; // @[MixedNode.scala:551:17]
wire [1:0] tlOtherMastersNodeIn_b_bits_param = tlOtherMastersNodeOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] masterNodeIn_b_bits_size; // @[MixedNode.scala:551:17]
wire [3:0] tlOtherMastersNodeIn_b_bits_size = tlOtherMastersNodeOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] masterNodeIn_b_bits_source; // @[MixedNode.scala:551:17]
wire [3:0] tlOtherMastersNodeIn_b_bits_source = tlOtherMastersNodeOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] masterNodeIn_b_bits_address; // @[MixedNode.scala:551:17]
wire [31:0] tlOtherMastersNodeIn_b_bits_address = tlOtherMastersNodeOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [15:0] masterNodeIn_b_bits_mask; // @[MixedNode.scala:551:17]
wire [15:0] tlOtherMastersNodeIn_b_bits_mask = tlOtherMastersNodeOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17]
wire [127:0] masterNodeIn_b_bits_data; // @[MixedNode.scala:551:17]
wire [127:0] tlOtherMastersNodeIn_b_bits_data = tlOtherMastersNodeOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire masterNodeIn_b_bits_corrupt; // @[MixedNode.scala:551:17]
wire tlOtherMastersNodeIn_b_bits_corrupt = tlOtherMastersNodeOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire masterNodeIn_c_ready; // @[MixedNode.scala:551:17]
wire tlOtherMastersNodeIn_c_ready = tlOtherMastersNodeOut_c_ready; // @[MixedNode.scala:542:17, :551:17]
wire tlOtherMastersNodeIn_c_valid; // @[MixedNode.scala:551:17]
wire [2:0] tlOtherMastersNodeIn_c_bits_opcode; // @[MixedNode.scala:551:17]
wire masterNodeIn_c_valid = tlOtherMastersNodeOut_c_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] tlOtherMastersNodeIn_c_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] masterNodeIn_c_bits_opcode = tlOtherMastersNodeOut_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] tlOtherMastersNodeIn_c_bits_size; // @[MixedNode.scala:551:17]
wire [2:0] masterNodeIn_c_bits_param = tlOtherMastersNodeOut_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] tlOtherMastersNodeIn_c_bits_source; // @[MixedNode.scala:551:17]
wire [3:0] masterNodeIn_c_bits_size = tlOtherMastersNodeOut_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] tlOtherMastersNodeIn_c_bits_address; // @[MixedNode.scala:551:17]
wire [3:0] masterNodeIn_c_bits_source = tlOtherMastersNodeOut_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [127:0] tlOtherMastersNodeIn_c_bits_data; // @[MixedNode.scala:551:17]
wire [31:0] masterNodeIn_c_bits_address = tlOtherMastersNodeOut_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [127:0] masterNodeIn_c_bits_data = tlOtherMastersNodeOut_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire tlOtherMastersNodeIn_d_ready; // @[MixedNode.scala:551:17]
wire masterNodeIn_d_ready = tlOtherMastersNodeOut_d_ready; // @[MixedNode.scala:542:17, :551:17]
wire masterNodeIn_d_valid; // @[MixedNode.scala:551:17]
wire tlOtherMastersNodeIn_d_valid = tlOtherMastersNodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] masterNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] tlOtherMastersNodeIn_d_bits_opcode = tlOtherMastersNodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] masterNodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [1:0] tlOtherMastersNodeIn_d_bits_param = tlOtherMastersNodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] masterNodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [3:0] tlOtherMastersNodeIn_d_bits_size = tlOtherMastersNodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] masterNodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [3:0] tlOtherMastersNodeIn_d_bits_source = tlOtherMastersNodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] masterNodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire [3:0] tlOtherMastersNodeIn_d_bits_sink = tlOtherMastersNodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire masterNodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire tlOtherMastersNodeIn_d_bits_denied = tlOtherMastersNodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [127:0] masterNodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire [127:0] tlOtherMastersNodeIn_d_bits_data = tlOtherMastersNodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire masterNodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire tlOtherMastersNodeIn_d_bits_corrupt = tlOtherMastersNodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire masterNodeIn_e_ready; // @[MixedNode.scala:551:17]
wire tlOtherMastersNodeIn_e_ready = tlOtherMastersNodeOut_e_ready; // @[MixedNode.scala:542:17, :551:17]
wire tlOtherMastersNodeIn_e_valid; // @[MixedNode.scala:551:17]
wire [3:0] tlOtherMastersNodeIn_e_bits_sink; // @[MixedNode.scala:551:17]
wire masterNodeIn_e_valid = tlOtherMastersNodeOut_e_valid; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] masterNodeIn_e_bits_sink = tlOtherMastersNodeOut_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_a_valid = tlOtherMastersNodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_a_bits_opcode = tlOtherMastersNodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_a_bits_param = tlOtherMastersNodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_a_bits_size = tlOtherMastersNodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_a_bits_source = tlOtherMastersNodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_a_bits_address = tlOtherMastersNodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_a_bits_mask = tlOtherMastersNodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_a_bits_data = tlOtherMastersNodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_b_ready = tlOtherMastersNodeIn_b_ready; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_c_valid = tlOtherMastersNodeIn_c_valid; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_c_bits_opcode = tlOtherMastersNodeIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_c_bits_param = tlOtherMastersNodeIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_c_bits_size = tlOtherMastersNodeIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_c_bits_source = tlOtherMastersNodeIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_c_bits_address = tlOtherMastersNodeIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_c_bits_data = tlOtherMastersNodeIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_d_ready = tlOtherMastersNodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_e_valid = tlOtherMastersNodeIn_e_valid; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_e_bits_sink = tlOtherMastersNodeIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign broadcast_auto_in = hartidOut; // @[MixedNode.scala:542:17]
assign hartidOut = hartidIn; // @[MixedNode.scala:542:17, :551:17]
assign auto_trace_source_out_time_0 = traceSourceNodeOut_time; // @[MixedNode.scala:542:17]
assign auto_trace_source_out_custom_rob_empty_0 = traceSourceNodeOut_custom_rob_empty; // @[MixedNode.scala:542:17]
wire int_localOut_0; // @[MixedNode.scala:542:17]
wire x1_int_localOut_0; // @[MixedNode.scala:542:17]
wire x1_int_localOut_1; // @[MixedNode.scala:542:17]
wire x1_int_localOut_1_0; // @[MixedNode.scala:542:17]
wire x1_int_localOut_2_0; // @[MixedNode.scala:542:17]
assign int_localOut_0 = int_localIn_0; // @[MixedNode.scala:542:17, :551:17]
assign x1_int_localOut_0 = x1_int_localIn_0; // @[MixedNode.scala:542:17, :551:17]
assign x1_int_localOut_1 = x1_int_localIn_1; // @[MixedNode.scala:542:17, :551:17]
assign x1_int_localOut_1_0 = x1_int_localIn_1_0; // @[MixedNode.scala:542:17, :551:17]
assign x1_int_localOut_2_0 = x1_int_localIn_2_0; // @[MixedNode.scala:542:17, :551:17]
wire intSinkNodeIn_0; // @[MixedNode.scala:551:17]
wire intSinkNodeIn_1; // @[MixedNode.scala:551:17]
wire intSinkNodeIn_2; // @[MixedNode.scala:551:17]
wire intSinkNodeIn_3; // @[MixedNode.scala:551:17]
wire intSinkNodeIn_4; // @[MixedNode.scala:551:17]
assign masterNodeIn_a_ready = masterNodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign buffer_auto_in_a_valid = masterNodeOut_a_valid; // @[Buffer.scala:40:9]
assign buffer_auto_in_a_bits_opcode = masterNodeOut_a_bits_opcode; // @[Buffer.scala:40:9]
assign buffer_auto_in_a_bits_param = masterNodeOut_a_bits_param; // @[Buffer.scala:40:9]
assign buffer_auto_in_a_bits_size = masterNodeOut_a_bits_size; // @[Buffer.scala:40:9]
assign buffer_auto_in_a_bits_source = masterNodeOut_a_bits_source; // @[Buffer.scala:40:9]
assign buffer_auto_in_a_bits_address = masterNodeOut_a_bits_address; // @[Buffer.scala:40:9]
assign buffer_auto_in_a_bits_mask = masterNodeOut_a_bits_mask; // @[Buffer.scala:40:9]
assign buffer_auto_in_a_bits_data = masterNodeOut_a_bits_data; // @[Buffer.scala:40:9]
assign buffer_auto_in_b_ready = masterNodeOut_b_ready; // @[Buffer.scala:40:9]
assign masterNodeIn_b_valid = masterNodeOut_b_valid; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeIn_b_bits_opcode = masterNodeOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeIn_b_bits_param = masterNodeOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeIn_b_bits_size = masterNodeOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeIn_b_bits_source = masterNodeOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeIn_b_bits_address = masterNodeOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeIn_b_bits_mask = masterNodeOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeIn_b_bits_data = masterNodeOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeIn_b_bits_corrupt = masterNodeOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeIn_c_ready = masterNodeOut_c_ready; // @[MixedNode.scala:542:17, :551:17]
assign buffer_auto_in_c_valid = masterNodeOut_c_valid; // @[Buffer.scala:40:9]
assign buffer_auto_in_c_bits_opcode = masterNodeOut_c_bits_opcode; // @[Buffer.scala:40:9]
assign buffer_auto_in_c_bits_param = masterNodeOut_c_bits_param; // @[Buffer.scala:40:9]
assign buffer_auto_in_c_bits_size = masterNodeOut_c_bits_size; // @[Buffer.scala:40:9]
assign buffer_auto_in_c_bits_source = masterNodeOut_c_bits_source; // @[Buffer.scala:40:9]
assign buffer_auto_in_c_bits_address = masterNodeOut_c_bits_address; // @[Buffer.scala:40:9]
assign buffer_auto_in_c_bits_data = masterNodeOut_c_bits_data; // @[Buffer.scala:40:9]
assign buffer_auto_in_d_ready = masterNodeOut_d_ready; // @[Buffer.scala:40:9]
assign masterNodeIn_d_valid = masterNodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeIn_d_bits_opcode = masterNodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeIn_d_bits_param = masterNodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeIn_d_bits_size = masterNodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeIn_d_bits_source = masterNodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeIn_d_bits_sink = masterNodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeIn_d_bits_denied = masterNodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeIn_d_bits_data = masterNodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeIn_d_bits_corrupt = masterNodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeIn_e_ready = masterNodeOut_e_ready; // @[MixedNode.scala:542:17, :551:17]
assign buffer_auto_in_e_valid = masterNodeOut_e_valid; // @[Buffer.scala:40:9]
assign buffer_auto_in_e_bits_sink = masterNodeOut_e_bits_sink; // @[Buffer.scala:40:9]
assign tlOtherMastersNodeOut_a_ready = masterNodeIn_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeOut_a_valid = masterNodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeOut_a_bits_opcode = masterNodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeOut_a_bits_param = masterNodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeOut_a_bits_size = masterNodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeOut_a_bits_source = masterNodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeOut_a_bits_address = masterNodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeOut_a_bits_mask = masterNodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeOut_a_bits_data = masterNodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeOut_b_ready = masterNodeIn_b_ready; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_b_valid = masterNodeIn_b_valid; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_b_bits_opcode = masterNodeIn_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_b_bits_param = masterNodeIn_b_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_b_bits_size = masterNodeIn_b_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_b_bits_source = masterNodeIn_b_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_b_bits_address = masterNodeIn_b_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_b_bits_mask = masterNodeIn_b_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_b_bits_data = masterNodeIn_b_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_b_bits_corrupt = masterNodeIn_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_c_ready = masterNodeIn_c_ready; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeOut_c_valid = masterNodeIn_c_valid; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeOut_c_bits_opcode = masterNodeIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeOut_c_bits_param = masterNodeIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeOut_c_bits_size = masterNodeIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeOut_c_bits_source = masterNodeIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeOut_c_bits_address = masterNodeIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeOut_c_bits_data = masterNodeIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeOut_d_ready = masterNodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_d_valid = masterNodeIn_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_d_bits_opcode = masterNodeIn_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_d_bits_param = masterNodeIn_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_d_bits_size = masterNodeIn_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_d_bits_source = masterNodeIn_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_d_bits_sink = masterNodeIn_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_d_bits_denied = masterNodeIn_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_d_bits_data = masterNodeIn_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_d_bits_corrupt = masterNodeIn_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_e_ready = masterNodeIn_e_ready; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeOut_e_valid = masterNodeIn_e_valid; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeOut_e_bits_sink = masterNodeIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapIn_a_ready = dCacheTapOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapIn_b_valid = dCacheTapOut_b_valid; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapIn_b_bits_opcode = dCacheTapOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapIn_b_bits_param = dCacheTapOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapIn_b_bits_size = dCacheTapOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapIn_b_bits_source = dCacheTapOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapIn_b_bits_address = dCacheTapOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapIn_b_bits_mask = dCacheTapOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapIn_b_bits_data = dCacheTapOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapIn_b_bits_corrupt = dCacheTapOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapIn_c_ready = dCacheTapOut_c_ready; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapIn_d_valid = dCacheTapOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapIn_d_bits_opcode = dCacheTapOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapIn_d_bits_param = dCacheTapOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapIn_d_bits_size = dCacheTapOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapIn_d_bits_source = dCacheTapOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapIn_d_bits_sink = dCacheTapOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapIn_d_bits_denied = dCacheTapOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapIn_d_bits_data = dCacheTapOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapIn_d_bits_corrupt = dCacheTapOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapIn_e_ready = dCacheTapOut_e_ready; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] dCacheTapOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] dCacheTapOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] dCacheTapOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [2:0] dCacheTapOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] dCacheTapOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [15:0] dCacheTapOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [127:0] dCacheTapOut_a_bits_data; // @[MixedNode.scala:542:17]
wire dCacheTapOut_a_valid; // @[MixedNode.scala:542:17]
wire dCacheTapOut_b_ready; // @[MixedNode.scala:542:17]
wire [2:0] dCacheTapOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] dCacheTapOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] dCacheTapOut_c_bits_size; // @[MixedNode.scala:542:17]
wire [2:0] dCacheTapOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] dCacheTapOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [127:0] dCacheTapOut_c_bits_data; // @[MixedNode.scala:542:17]
wire dCacheTapOut_c_valid; // @[MixedNode.scala:542:17]
wire dCacheTapOut_d_ready; // @[MixedNode.scala:542:17]
wire [3:0] dCacheTapOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire dCacheTapOut_e_valid; // @[MixedNode.scala:542:17]
assign widget_auto_anon_out_a_ready = dCacheTapIn_a_ready; // @[WidthWidget.scala:27:9]
assign dCacheTapOut_a_valid = dCacheTapIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapOut_a_bits_opcode = dCacheTapIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapOut_a_bits_param = dCacheTapIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapOut_a_bits_size = dCacheTapIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapOut_a_bits_source = dCacheTapIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapOut_a_bits_address = dCacheTapIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapOut_a_bits_mask = dCacheTapIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapOut_a_bits_data = dCacheTapIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapOut_b_ready = dCacheTapIn_b_ready; // @[MixedNode.scala:542:17, :551:17]
assign widget_auto_anon_out_b_valid = dCacheTapIn_b_valid; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_b_bits_opcode = dCacheTapIn_b_bits_opcode; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_b_bits_param = dCacheTapIn_b_bits_param; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_b_bits_size = dCacheTapIn_b_bits_size; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_b_bits_source = dCacheTapIn_b_bits_source; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_b_bits_address = dCacheTapIn_b_bits_address; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_b_bits_mask = dCacheTapIn_b_bits_mask; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_b_bits_data = dCacheTapIn_b_bits_data; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_b_bits_corrupt = dCacheTapIn_b_bits_corrupt; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_c_ready = dCacheTapIn_c_ready; // @[WidthWidget.scala:27:9]
assign dCacheTapOut_c_valid = dCacheTapIn_c_valid; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapOut_c_bits_opcode = dCacheTapIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapOut_c_bits_param = dCacheTapIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapOut_c_bits_size = dCacheTapIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapOut_c_bits_source = dCacheTapIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapOut_c_bits_address = dCacheTapIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapOut_c_bits_data = dCacheTapIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapOut_d_ready = dCacheTapIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign widget_auto_anon_out_d_valid = dCacheTapIn_d_valid; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_d_bits_opcode = dCacheTapIn_d_bits_opcode; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_d_bits_param = dCacheTapIn_d_bits_param; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_d_bits_size = dCacheTapIn_d_bits_size; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_d_bits_source = dCacheTapIn_d_bits_source; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_d_bits_sink = dCacheTapIn_d_bits_sink; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_d_bits_denied = dCacheTapIn_d_bits_denied; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_d_bits_data = dCacheTapIn_d_bits_data; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_d_bits_corrupt = dCacheTapIn_d_bits_corrupt; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_e_ready = dCacheTapIn_e_ready; // @[WidthWidget.scala:27:9]
assign dCacheTapOut_e_valid = dCacheTapIn_e_valid; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapOut_e_bits_sink = dCacheTapIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
TLXbar_MasterXbar_BoomTile_i2_o1_a32d128s4k4z4c tlMasterXbar ( // @[HierarchicalElement.scala:55:42]
.clock (clock),
.reset (reset),
.auto_anon_in_1_a_ready (widget_1_auto_anon_out_a_ready),
.auto_anon_in_1_a_valid (widget_1_auto_anon_out_a_valid), // @[WidthWidget.scala:27:9]
.auto_anon_in_1_a_bits_address (widget_1_auto_anon_out_a_bits_address), // @[WidthWidget.scala:27:9]
.auto_anon_in_1_d_valid (widget_1_auto_anon_out_d_valid),
.auto_anon_in_1_d_bits_opcode (widget_1_auto_anon_out_d_bits_opcode),
.auto_anon_in_1_d_bits_param (widget_1_auto_anon_out_d_bits_param),
.auto_anon_in_1_d_bits_size (widget_1_auto_anon_out_d_bits_size),
.auto_anon_in_1_d_bits_sink (widget_1_auto_anon_out_d_bits_sink),
.auto_anon_in_1_d_bits_denied (widget_1_auto_anon_out_d_bits_denied),
.auto_anon_in_1_d_bits_data (widget_1_auto_anon_out_d_bits_data),
.auto_anon_in_1_d_bits_corrupt (widget_1_auto_anon_out_d_bits_corrupt),
.auto_anon_in_0_a_ready (dCacheTapOut_a_ready),
.auto_anon_in_0_a_valid (dCacheTapOut_a_valid), // @[MixedNode.scala:542:17]
.auto_anon_in_0_a_bits_opcode (dCacheTapOut_a_bits_opcode), // @[MixedNode.scala:542:17]
.auto_anon_in_0_a_bits_param (dCacheTapOut_a_bits_param), // @[MixedNode.scala:542:17]
.auto_anon_in_0_a_bits_size (dCacheTapOut_a_bits_size), // @[MixedNode.scala:542:17]
.auto_anon_in_0_a_bits_source (dCacheTapOut_a_bits_source), // @[MixedNode.scala:542:17]
.auto_anon_in_0_a_bits_address (dCacheTapOut_a_bits_address), // @[MixedNode.scala:542:17]
.auto_anon_in_0_a_bits_mask (dCacheTapOut_a_bits_mask), // @[MixedNode.scala:542:17]
.auto_anon_in_0_a_bits_data (dCacheTapOut_a_bits_data), // @[MixedNode.scala:542:17]
.auto_anon_in_0_b_ready (dCacheTapOut_b_ready), // @[MixedNode.scala:542:17]
.auto_anon_in_0_b_valid (dCacheTapOut_b_valid),
.auto_anon_in_0_b_bits_opcode (dCacheTapOut_b_bits_opcode),
.auto_anon_in_0_b_bits_param (dCacheTapOut_b_bits_param),
.auto_anon_in_0_b_bits_size (dCacheTapOut_b_bits_size),
.auto_anon_in_0_b_bits_source (dCacheTapOut_b_bits_source),
.auto_anon_in_0_b_bits_address (dCacheTapOut_b_bits_address),
.auto_anon_in_0_b_bits_mask (dCacheTapOut_b_bits_mask),
.auto_anon_in_0_b_bits_data (dCacheTapOut_b_bits_data),
.auto_anon_in_0_b_bits_corrupt (dCacheTapOut_b_bits_corrupt),
.auto_anon_in_0_c_ready (dCacheTapOut_c_ready),
.auto_anon_in_0_c_valid (dCacheTapOut_c_valid), // @[MixedNode.scala:542:17]
.auto_anon_in_0_c_bits_opcode (dCacheTapOut_c_bits_opcode), // @[MixedNode.scala:542:17]
.auto_anon_in_0_c_bits_param (dCacheTapOut_c_bits_param), // @[MixedNode.scala:542:17]
.auto_anon_in_0_c_bits_size (dCacheTapOut_c_bits_size), // @[MixedNode.scala:542:17]
.auto_anon_in_0_c_bits_source (dCacheTapOut_c_bits_source), // @[MixedNode.scala:542:17]
.auto_anon_in_0_c_bits_address (dCacheTapOut_c_bits_address), // @[MixedNode.scala:542:17]
.auto_anon_in_0_c_bits_data (dCacheTapOut_c_bits_data), // @[MixedNode.scala:542:17]
.auto_anon_in_0_d_ready (dCacheTapOut_d_ready), // @[MixedNode.scala:542:17]
.auto_anon_in_0_d_valid (dCacheTapOut_d_valid),
.auto_anon_in_0_d_bits_opcode (dCacheTapOut_d_bits_opcode),
.auto_anon_in_0_d_bits_param (dCacheTapOut_d_bits_param),
.auto_anon_in_0_d_bits_size (dCacheTapOut_d_bits_size),
.auto_anon_in_0_d_bits_source (dCacheTapOut_d_bits_source),
.auto_anon_in_0_d_bits_sink (dCacheTapOut_d_bits_sink),
.auto_anon_in_0_d_bits_denied (dCacheTapOut_d_bits_denied),
.auto_anon_in_0_d_bits_data (dCacheTapOut_d_bits_data),
.auto_anon_in_0_d_bits_corrupt (dCacheTapOut_d_bits_corrupt),
.auto_anon_in_0_e_ready (dCacheTapOut_e_ready),
.auto_anon_in_0_e_valid (dCacheTapOut_e_valid), // @[MixedNode.scala:542:17]
.auto_anon_in_0_e_bits_sink (dCacheTapOut_e_bits_sink), // @[MixedNode.scala:542:17]
.auto_anon_out_a_ready (tlOtherMastersNodeIn_a_ready), // @[MixedNode.scala:551:17]
.auto_anon_out_a_valid (tlOtherMastersNodeIn_a_valid),
.auto_anon_out_a_bits_opcode (tlOtherMastersNodeIn_a_bits_opcode),
.auto_anon_out_a_bits_param (tlOtherMastersNodeIn_a_bits_param),
.auto_anon_out_a_bits_size (tlOtherMastersNodeIn_a_bits_size),
.auto_anon_out_a_bits_source (tlOtherMastersNodeIn_a_bits_source),
.auto_anon_out_a_bits_address (tlOtherMastersNodeIn_a_bits_address),
.auto_anon_out_a_bits_mask (tlOtherMastersNodeIn_a_bits_mask),
.auto_anon_out_a_bits_data (tlOtherMastersNodeIn_a_bits_data),
.auto_anon_out_b_ready (tlOtherMastersNodeIn_b_ready),
.auto_anon_out_b_valid (tlOtherMastersNodeIn_b_valid), // @[MixedNode.scala:551:17]
.auto_anon_out_b_bits_opcode (tlOtherMastersNodeIn_b_bits_opcode), // @[MixedNode.scala:551:17]
.auto_anon_out_b_bits_param (tlOtherMastersNodeIn_b_bits_param), // @[MixedNode.scala:551:17]
.auto_anon_out_b_bits_size (tlOtherMastersNodeIn_b_bits_size), // @[MixedNode.scala:551:17]
.auto_anon_out_b_bits_source (tlOtherMastersNodeIn_b_bits_source), // @[MixedNode.scala:551:17]
.auto_anon_out_b_bits_address (tlOtherMastersNodeIn_b_bits_address), // @[MixedNode.scala:551:17]
.auto_anon_out_b_bits_mask (tlOtherMastersNodeIn_b_bits_mask), // @[MixedNode.scala:551:17]
.auto_anon_out_b_bits_data (tlOtherMastersNodeIn_b_bits_data), // @[MixedNode.scala:551:17]
.auto_anon_out_b_bits_corrupt (tlOtherMastersNodeIn_b_bits_corrupt), // @[MixedNode.scala:551:17]
.auto_anon_out_c_ready (tlOtherMastersNodeIn_c_ready), // @[MixedNode.scala:551:17]
.auto_anon_out_c_valid (tlOtherMastersNodeIn_c_valid),
.auto_anon_out_c_bits_opcode (tlOtherMastersNodeIn_c_bits_opcode),
.auto_anon_out_c_bits_param (tlOtherMastersNodeIn_c_bits_param),
.auto_anon_out_c_bits_size (tlOtherMastersNodeIn_c_bits_size),
.auto_anon_out_c_bits_source (tlOtherMastersNodeIn_c_bits_source),
.auto_anon_out_c_bits_address (tlOtherMastersNodeIn_c_bits_address),
.auto_anon_out_c_bits_data (tlOtherMastersNodeIn_c_bits_data),
.auto_anon_out_d_ready (tlOtherMastersNodeIn_d_ready),
.auto_anon_out_d_valid (tlOtherMastersNodeIn_d_valid), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_opcode (tlOtherMastersNodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_param (tlOtherMastersNodeIn_d_bits_param), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_size (tlOtherMastersNodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_source (tlOtherMastersNodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_sink (tlOtherMastersNodeIn_d_bits_sink), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_denied (tlOtherMastersNodeIn_d_bits_denied), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_data (tlOtherMastersNodeIn_d_bits_data), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_corrupt (tlOtherMastersNodeIn_d_bits_corrupt), // @[MixedNode.scala:551:17]
.auto_anon_out_e_ready (tlOtherMastersNodeIn_e_ready), // @[MixedNode.scala:551:17]
.auto_anon_out_e_valid (tlOtherMastersNodeIn_e_valid),
.auto_anon_out_e_bits_sink (tlOtherMastersNodeIn_e_bits_sink)
); // @[HierarchicalElement.scala:55:42]
TLXbar_SlaveXbar_BoomTile_i0_o0_a1d8s1k1z1u tlSlaveXbar ( // @[HierarchicalElement.scala:56:41]
.clock (clock),
.reset (reset)
); // @[HierarchicalElement.scala:56:41]
IntXbar_i4_o1 intXbar ( // @[HierarchicalElement.scala:57:37]
.auto_anon_in_3_0 (x1_int_localOut_2_0), // @[MixedNode.scala:542:17]
.auto_anon_in_2_0 (x1_int_localOut_1_0), // @[MixedNode.scala:542:17]
.auto_anon_in_1_0 (x1_int_localOut_0), // @[MixedNode.scala:542:17]
.auto_anon_in_1_1 (x1_int_localOut_1), // @[MixedNode.scala:542:17]
.auto_anon_in_0_0 (int_localOut_0), // @[MixedNode.scala:542:17]
.auto_anon_out_0 (intSinkNodeIn_0),
.auto_anon_out_1 (intSinkNodeIn_1),
.auto_anon_out_2 (intSinkNodeIn_2),
.auto_anon_out_3 (intSinkNodeIn_3),
.auto_anon_out_4 (intSinkNodeIn_4)
); // @[HierarchicalElement.scala:57:37]
BoomNonBlockingDCache dcache ( // @[tile.scala:132:54]
.clock (clock),
.reset (reset),
.auto_out_a_ready (widget_auto_anon_in_a_ready), // @[WidthWidget.scala:27:9]
.auto_out_a_valid (widget_auto_anon_in_a_valid),
.auto_out_a_bits_opcode (widget_auto_anon_in_a_bits_opcode),
.auto_out_a_bits_param (widget_auto_anon_in_a_bits_param),
.auto_out_a_bits_size (widget_auto_anon_in_a_bits_size),
.auto_out_a_bits_source (widget_auto_anon_in_a_bits_source),
.auto_out_a_bits_address (widget_auto_anon_in_a_bits_address),
.auto_out_a_bits_mask (widget_auto_anon_in_a_bits_mask),
.auto_out_a_bits_data (widget_auto_anon_in_a_bits_data),
.auto_out_b_ready (widget_auto_anon_in_b_ready),
.auto_out_b_valid (widget_auto_anon_in_b_valid), // @[WidthWidget.scala:27:9]
.auto_out_b_bits_opcode (widget_auto_anon_in_b_bits_opcode), // @[WidthWidget.scala:27:9]
.auto_out_b_bits_param (widget_auto_anon_in_b_bits_param), // @[WidthWidget.scala:27:9]
.auto_out_b_bits_size (widget_auto_anon_in_b_bits_size), // @[WidthWidget.scala:27:9]
.auto_out_b_bits_source (widget_auto_anon_in_b_bits_source), // @[WidthWidget.scala:27:9]
.auto_out_b_bits_address (widget_auto_anon_in_b_bits_address), // @[WidthWidget.scala:27:9]
.auto_out_b_bits_mask (widget_auto_anon_in_b_bits_mask), // @[WidthWidget.scala:27:9]
.auto_out_b_bits_data (widget_auto_anon_in_b_bits_data), // @[WidthWidget.scala:27:9]
.auto_out_b_bits_corrupt (widget_auto_anon_in_b_bits_corrupt), // @[WidthWidget.scala:27:9]
.auto_out_c_ready (widget_auto_anon_in_c_ready), // @[WidthWidget.scala:27:9]
.auto_out_c_valid (widget_auto_anon_in_c_valid),
.auto_out_c_bits_opcode (widget_auto_anon_in_c_bits_opcode),
.auto_out_c_bits_param (widget_auto_anon_in_c_bits_param),
.auto_out_c_bits_size (widget_auto_anon_in_c_bits_size),
.auto_out_c_bits_source (widget_auto_anon_in_c_bits_source),
.auto_out_c_bits_address (widget_auto_anon_in_c_bits_address),
.auto_out_c_bits_data (widget_auto_anon_in_c_bits_data),
.auto_out_d_ready (widget_auto_anon_in_d_ready),
.auto_out_d_valid (widget_auto_anon_in_d_valid), // @[WidthWidget.scala:27:9]
.auto_out_d_bits_opcode (widget_auto_anon_in_d_bits_opcode), // @[WidthWidget.scala:27:9]
.auto_out_d_bits_param (widget_auto_anon_in_d_bits_param), // @[WidthWidget.scala:27:9]
.auto_out_d_bits_size (widget_auto_anon_in_d_bits_size), // @[WidthWidget.scala:27:9]
.auto_out_d_bits_source (widget_auto_anon_in_d_bits_source), // @[WidthWidget.scala:27:9]
.auto_out_d_bits_sink (widget_auto_anon_in_d_bits_sink), // @[WidthWidget.scala:27:9]
.auto_out_d_bits_denied (widget_auto_anon_in_d_bits_denied), // @[WidthWidget.scala:27:9]
.auto_out_d_bits_data (widget_auto_anon_in_d_bits_data), // @[WidthWidget.scala:27:9]
.auto_out_d_bits_corrupt (widget_auto_anon_in_d_bits_corrupt), // @[WidthWidget.scala:27:9]
.auto_out_e_ready (widget_auto_anon_in_e_ready), // @[WidthWidget.scala:27:9]
.auto_out_e_valid (widget_auto_anon_in_e_valid),
.auto_out_e_bits_sink (widget_auto_anon_in_e_bits_sink),
.io_lsu_req_ready (_dcache_io_lsu_req_ready),
.io_lsu_req_valid (_lsu_io_dmem_req_valid), // @[tile.scala:160:20]
.io_lsu_req_bits_0_valid (_lsu_io_dmem_req_bits_0_valid), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_uopc (_lsu_io_dmem_req_bits_0_bits_uop_uopc), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_inst (_lsu_io_dmem_req_bits_0_bits_uop_inst), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_debug_inst (_lsu_io_dmem_req_bits_0_bits_uop_debug_inst), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_is_rvc (_lsu_io_dmem_req_bits_0_bits_uop_is_rvc), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_debug_pc (_lsu_io_dmem_req_bits_0_bits_uop_debug_pc), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_iq_type (_lsu_io_dmem_req_bits_0_bits_uop_iq_type), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_fu_code (_lsu_io_dmem_req_bits_0_bits_uop_fu_code), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_ctrl_br_type (_lsu_io_dmem_req_bits_0_bits_uop_ctrl_br_type), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_ctrl_op1_sel (_lsu_io_dmem_req_bits_0_bits_uop_ctrl_op1_sel), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_ctrl_op2_sel (_lsu_io_dmem_req_bits_0_bits_uop_ctrl_op2_sel), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_ctrl_imm_sel (_lsu_io_dmem_req_bits_0_bits_uop_ctrl_imm_sel), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_ctrl_op_fcn (_lsu_io_dmem_req_bits_0_bits_uop_ctrl_op_fcn), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_ctrl_fcn_dw (_lsu_io_dmem_req_bits_0_bits_uop_ctrl_fcn_dw), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_ctrl_csr_cmd (_lsu_io_dmem_req_bits_0_bits_uop_ctrl_csr_cmd), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_ctrl_is_load (_lsu_io_dmem_req_bits_0_bits_uop_ctrl_is_load), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_ctrl_is_sta (_lsu_io_dmem_req_bits_0_bits_uop_ctrl_is_sta), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_ctrl_is_std (_lsu_io_dmem_req_bits_0_bits_uop_ctrl_is_std), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_iw_state (_lsu_io_dmem_req_bits_0_bits_uop_iw_state), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_iw_p1_poisoned (_lsu_io_dmem_req_bits_0_bits_uop_iw_p1_poisoned), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_iw_p2_poisoned (_lsu_io_dmem_req_bits_0_bits_uop_iw_p2_poisoned), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_is_br (_lsu_io_dmem_req_bits_0_bits_uop_is_br), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_is_jalr (_lsu_io_dmem_req_bits_0_bits_uop_is_jalr), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_is_jal (_lsu_io_dmem_req_bits_0_bits_uop_is_jal), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_is_sfb (_lsu_io_dmem_req_bits_0_bits_uop_is_sfb), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_br_mask (_lsu_io_dmem_req_bits_0_bits_uop_br_mask), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_br_tag (_lsu_io_dmem_req_bits_0_bits_uop_br_tag), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_ftq_idx (_lsu_io_dmem_req_bits_0_bits_uop_ftq_idx), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_edge_inst (_lsu_io_dmem_req_bits_0_bits_uop_edge_inst), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_pc_lob (_lsu_io_dmem_req_bits_0_bits_uop_pc_lob), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_taken (_lsu_io_dmem_req_bits_0_bits_uop_taken), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_imm_packed (_lsu_io_dmem_req_bits_0_bits_uop_imm_packed), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_csr_addr (_lsu_io_dmem_req_bits_0_bits_uop_csr_addr), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_rob_idx (_lsu_io_dmem_req_bits_0_bits_uop_rob_idx), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_ldq_idx (_lsu_io_dmem_req_bits_0_bits_uop_ldq_idx), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_stq_idx (_lsu_io_dmem_req_bits_0_bits_uop_stq_idx), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_rxq_idx (_lsu_io_dmem_req_bits_0_bits_uop_rxq_idx), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_pdst (_lsu_io_dmem_req_bits_0_bits_uop_pdst), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_prs1 (_lsu_io_dmem_req_bits_0_bits_uop_prs1), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_prs2 (_lsu_io_dmem_req_bits_0_bits_uop_prs2), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_prs3 (_lsu_io_dmem_req_bits_0_bits_uop_prs3), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_ppred (_lsu_io_dmem_req_bits_0_bits_uop_ppred), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_prs1_busy (_lsu_io_dmem_req_bits_0_bits_uop_prs1_busy), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_prs2_busy (_lsu_io_dmem_req_bits_0_bits_uop_prs2_busy), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_prs3_busy (_lsu_io_dmem_req_bits_0_bits_uop_prs3_busy), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_ppred_busy (_lsu_io_dmem_req_bits_0_bits_uop_ppred_busy), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_stale_pdst (_lsu_io_dmem_req_bits_0_bits_uop_stale_pdst), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_exception (_lsu_io_dmem_req_bits_0_bits_uop_exception), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_exc_cause (_lsu_io_dmem_req_bits_0_bits_uop_exc_cause), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_bypassable (_lsu_io_dmem_req_bits_0_bits_uop_bypassable), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_mem_cmd (_lsu_io_dmem_req_bits_0_bits_uop_mem_cmd), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_mem_size (_lsu_io_dmem_req_bits_0_bits_uop_mem_size), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_mem_signed (_lsu_io_dmem_req_bits_0_bits_uop_mem_signed), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_is_fence (_lsu_io_dmem_req_bits_0_bits_uop_is_fence), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_is_fencei (_lsu_io_dmem_req_bits_0_bits_uop_is_fencei), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_is_amo (_lsu_io_dmem_req_bits_0_bits_uop_is_amo), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_uses_ldq (_lsu_io_dmem_req_bits_0_bits_uop_uses_ldq), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_uses_stq (_lsu_io_dmem_req_bits_0_bits_uop_uses_stq), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_is_sys_pc2epc (_lsu_io_dmem_req_bits_0_bits_uop_is_sys_pc2epc), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_is_unique (_lsu_io_dmem_req_bits_0_bits_uop_is_unique), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_flush_on_commit (_lsu_io_dmem_req_bits_0_bits_uop_flush_on_commit), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_ldst_is_rs1 (_lsu_io_dmem_req_bits_0_bits_uop_ldst_is_rs1), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_ldst (_lsu_io_dmem_req_bits_0_bits_uop_ldst), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_lrs1 (_lsu_io_dmem_req_bits_0_bits_uop_lrs1), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_lrs2 (_lsu_io_dmem_req_bits_0_bits_uop_lrs2), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_lrs3 (_lsu_io_dmem_req_bits_0_bits_uop_lrs3), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_ldst_val (_lsu_io_dmem_req_bits_0_bits_uop_ldst_val), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_dst_rtype (_lsu_io_dmem_req_bits_0_bits_uop_dst_rtype), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_lrs1_rtype (_lsu_io_dmem_req_bits_0_bits_uop_lrs1_rtype), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_lrs2_rtype (_lsu_io_dmem_req_bits_0_bits_uop_lrs2_rtype), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_frs3_en (_lsu_io_dmem_req_bits_0_bits_uop_frs3_en), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_fp_val (_lsu_io_dmem_req_bits_0_bits_uop_fp_val), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_fp_single (_lsu_io_dmem_req_bits_0_bits_uop_fp_single), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_xcpt_pf_if (_lsu_io_dmem_req_bits_0_bits_uop_xcpt_pf_if), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_xcpt_ae_if (_lsu_io_dmem_req_bits_0_bits_uop_xcpt_ae_if), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_xcpt_ma_if (_lsu_io_dmem_req_bits_0_bits_uop_xcpt_ma_if), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_bp_debug_if (_lsu_io_dmem_req_bits_0_bits_uop_bp_debug_if), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_bp_xcpt_if (_lsu_io_dmem_req_bits_0_bits_uop_bp_xcpt_if), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_debug_fsrc (_lsu_io_dmem_req_bits_0_bits_uop_debug_fsrc), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_debug_tsrc (_lsu_io_dmem_req_bits_0_bits_uop_debug_tsrc), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_addr (_lsu_io_dmem_req_bits_0_bits_addr), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_data (_lsu_io_dmem_req_bits_0_bits_data), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_is_hella (_lsu_io_dmem_req_bits_0_bits_is_hella), // @[tile.scala:160:20]
.io_lsu_s1_kill_0 (_lsu_io_dmem_s1_kill_0), // @[tile.scala:160:20]
.io_lsu_resp_0_valid (_dcache_io_lsu_resp_0_valid),
.io_lsu_resp_0_bits_uop_uopc (_dcache_io_lsu_resp_0_bits_uop_uopc),
.io_lsu_resp_0_bits_uop_inst (_dcache_io_lsu_resp_0_bits_uop_inst),
.io_lsu_resp_0_bits_uop_debug_inst (_dcache_io_lsu_resp_0_bits_uop_debug_inst),
.io_lsu_resp_0_bits_uop_is_rvc (_dcache_io_lsu_resp_0_bits_uop_is_rvc),
.io_lsu_resp_0_bits_uop_debug_pc (_dcache_io_lsu_resp_0_bits_uop_debug_pc),
.io_lsu_resp_0_bits_uop_iq_type (_dcache_io_lsu_resp_0_bits_uop_iq_type),
.io_lsu_resp_0_bits_uop_fu_code (_dcache_io_lsu_resp_0_bits_uop_fu_code),
.io_lsu_resp_0_bits_uop_ctrl_br_type (_dcache_io_lsu_resp_0_bits_uop_ctrl_br_type),
.io_lsu_resp_0_bits_uop_ctrl_op1_sel (_dcache_io_lsu_resp_0_bits_uop_ctrl_op1_sel),
.io_lsu_resp_0_bits_uop_ctrl_op2_sel (_dcache_io_lsu_resp_0_bits_uop_ctrl_op2_sel),
.io_lsu_resp_0_bits_uop_ctrl_imm_sel (_dcache_io_lsu_resp_0_bits_uop_ctrl_imm_sel),
.io_lsu_resp_0_bits_uop_ctrl_op_fcn (_dcache_io_lsu_resp_0_bits_uop_ctrl_op_fcn),
.io_lsu_resp_0_bits_uop_ctrl_fcn_dw (_dcache_io_lsu_resp_0_bits_uop_ctrl_fcn_dw),
.io_lsu_resp_0_bits_uop_ctrl_csr_cmd (_dcache_io_lsu_resp_0_bits_uop_ctrl_csr_cmd),
.io_lsu_resp_0_bits_uop_ctrl_is_load (_dcache_io_lsu_resp_0_bits_uop_ctrl_is_load),
.io_lsu_resp_0_bits_uop_ctrl_is_sta (_dcache_io_lsu_resp_0_bits_uop_ctrl_is_sta),
.io_lsu_resp_0_bits_uop_ctrl_is_std (_dcache_io_lsu_resp_0_bits_uop_ctrl_is_std),
.io_lsu_resp_0_bits_uop_iw_state (_dcache_io_lsu_resp_0_bits_uop_iw_state),
.io_lsu_resp_0_bits_uop_iw_p1_poisoned (_dcache_io_lsu_resp_0_bits_uop_iw_p1_poisoned),
.io_lsu_resp_0_bits_uop_iw_p2_poisoned (_dcache_io_lsu_resp_0_bits_uop_iw_p2_poisoned),
.io_lsu_resp_0_bits_uop_is_br (_dcache_io_lsu_resp_0_bits_uop_is_br),
.io_lsu_resp_0_bits_uop_is_jalr (_dcache_io_lsu_resp_0_bits_uop_is_jalr),
.io_lsu_resp_0_bits_uop_is_jal (_dcache_io_lsu_resp_0_bits_uop_is_jal),
.io_lsu_resp_0_bits_uop_is_sfb (_dcache_io_lsu_resp_0_bits_uop_is_sfb),
.io_lsu_resp_0_bits_uop_br_mask (_dcache_io_lsu_resp_0_bits_uop_br_mask),
.io_lsu_resp_0_bits_uop_br_tag (_dcache_io_lsu_resp_0_bits_uop_br_tag),
.io_lsu_resp_0_bits_uop_ftq_idx (_dcache_io_lsu_resp_0_bits_uop_ftq_idx),
.io_lsu_resp_0_bits_uop_edge_inst (_dcache_io_lsu_resp_0_bits_uop_edge_inst),
.io_lsu_resp_0_bits_uop_pc_lob (_dcache_io_lsu_resp_0_bits_uop_pc_lob),
.io_lsu_resp_0_bits_uop_taken (_dcache_io_lsu_resp_0_bits_uop_taken),
.io_lsu_resp_0_bits_uop_imm_packed (_dcache_io_lsu_resp_0_bits_uop_imm_packed),
.io_lsu_resp_0_bits_uop_csr_addr (_dcache_io_lsu_resp_0_bits_uop_csr_addr),
.io_lsu_resp_0_bits_uop_rob_idx (_dcache_io_lsu_resp_0_bits_uop_rob_idx),
.io_lsu_resp_0_bits_uop_ldq_idx (_dcache_io_lsu_resp_0_bits_uop_ldq_idx),
.io_lsu_resp_0_bits_uop_stq_idx (_dcache_io_lsu_resp_0_bits_uop_stq_idx),
.io_lsu_resp_0_bits_uop_rxq_idx (_dcache_io_lsu_resp_0_bits_uop_rxq_idx),
.io_lsu_resp_0_bits_uop_pdst (_dcache_io_lsu_resp_0_bits_uop_pdst),
.io_lsu_resp_0_bits_uop_prs1 (_dcache_io_lsu_resp_0_bits_uop_prs1),
.io_lsu_resp_0_bits_uop_prs2 (_dcache_io_lsu_resp_0_bits_uop_prs2),
.io_lsu_resp_0_bits_uop_prs3 (_dcache_io_lsu_resp_0_bits_uop_prs3),
.io_lsu_resp_0_bits_uop_ppred (_dcache_io_lsu_resp_0_bits_uop_ppred),
.io_lsu_resp_0_bits_uop_prs1_busy (_dcache_io_lsu_resp_0_bits_uop_prs1_busy),
.io_lsu_resp_0_bits_uop_prs2_busy (_dcache_io_lsu_resp_0_bits_uop_prs2_busy),
.io_lsu_resp_0_bits_uop_prs3_busy (_dcache_io_lsu_resp_0_bits_uop_prs3_busy),
.io_lsu_resp_0_bits_uop_ppred_busy (_dcache_io_lsu_resp_0_bits_uop_ppred_busy),
.io_lsu_resp_0_bits_uop_stale_pdst (_dcache_io_lsu_resp_0_bits_uop_stale_pdst),
.io_lsu_resp_0_bits_uop_exception (_dcache_io_lsu_resp_0_bits_uop_exception),
.io_lsu_resp_0_bits_uop_exc_cause (_dcache_io_lsu_resp_0_bits_uop_exc_cause),
.io_lsu_resp_0_bits_uop_bypassable (_dcache_io_lsu_resp_0_bits_uop_bypassable),
.io_lsu_resp_0_bits_uop_mem_cmd (_dcache_io_lsu_resp_0_bits_uop_mem_cmd),
.io_lsu_resp_0_bits_uop_mem_size (_dcache_io_lsu_resp_0_bits_uop_mem_size),
.io_lsu_resp_0_bits_uop_mem_signed (_dcache_io_lsu_resp_0_bits_uop_mem_signed),
.io_lsu_resp_0_bits_uop_is_fence (_dcache_io_lsu_resp_0_bits_uop_is_fence),
.io_lsu_resp_0_bits_uop_is_fencei (_dcache_io_lsu_resp_0_bits_uop_is_fencei),
.io_lsu_resp_0_bits_uop_is_amo (_dcache_io_lsu_resp_0_bits_uop_is_amo),
.io_lsu_resp_0_bits_uop_uses_ldq (_dcache_io_lsu_resp_0_bits_uop_uses_ldq),
.io_lsu_resp_0_bits_uop_uses_stq (_dcache_io_lsu_resp_0_bits_uop_uses_stq),
.io_lsu_resp_0_bits_uop_is_sys_pc2epc (_dcache_io_lsu_resp_0_bits_uop_is_sys_pc2epc),
.io_lsu_resp_0_bits_uop_is_unique (_dcache_io_lsu_resp_0_bits_uop_is_unique),
.io_lsu_resp_0_bits_uop_flush_on_commit (_dcache_io_lsu_resp_0_bits_uop_flush_on_commit),
.io_lsu_resp_0_bits_uop_ldst_is_rs1 (_dcache_io_lsu_resp_0_bits_uop_ldst_is_rs1),
.io_lsu_resp_0_bits_uop_ldst (_dcache_io_lsu_resp_0_bits_uop_ldst),
.io_lsu_resp_0_bits_uop_lrs1 (_dcache_io_lsu_resp_0_bits_uop_lrs1),
.io_lsu_resp_0_bits_uop_lrs2 (_dcache_io_lsu_resp_0_bits_uop_lrs2),
.io_lsu_resp_0_bits_uop_lrs3 (_dcache_io_lsu_resp_0_bits_uop_lrs3),
.io_lsu_resp_0_bits_uop_ldst_val (_dcache_io_lsu_resp_0_bits_uop_ldst_val),
.io_lsu_resp_0_bits_uop_dst_rtype (_dcache_io_lsu_resp_0_bits_uop_dst_rtype),
.io_lsu_resp_0_bits_uop_lrs1_rtype (_dcache_io_lsu_resp_0_bits_uop_lrs1_rtype),
.io_lsu_resp_0_bits_uop_lrs2_rtype (_dcache_io_lsu_resp_0_bits_uop_lrs2_rtype),
.io_lsu_resp_0_bits_uop_frs3_en (_dcache_io_lsu_resp_0_bits_uop_frs3_en),
.io_lsu_resp_0_bits_uop_fp_val (_dcache_io_lsu_resp_0_bits_uop_fp_val),
.io_lsu_resp_0_bits_uop_fp_single (_dcache_io_lsu_resp_0_bits_uop_fp_single),
.io_lsu_resp_0_bits_uop_xcpt_pf_if (_dcache_io_lsu_resp_0_bits_uop_xcpt_pf_if),
.io_lsu_resp_0_bits_uop_xcpt_ae_if (_dcache_io_lsu_resp_0_bits_uop_xcpt_ae_if),
.io_lsu_resp_0_bits_uop_xcpt_ma_if (_dcache_io_lsu_resp_0_bits_uop_xcpt_ma_if),
.io_lsu_resp_0_bits_uop_bp_debug_if (_dcache_io_lsu_resp_0_bits_uop_bp_debug_if),
.io_lsu_resp_0_bits_uop_bp_xcpt_if (_dcache_io_lsu_resp_0_bits_uop_bp_xcpt_if),
.io_lsu_resp_0_bits_uop_debug_fsrc (_dcache_io_lsu_resp_0_bits_uop_debug_fsrc),
.io_lsu_resp_0_bits_uop_debug_tsrc (_dcache_io_lsu_resp_0_bits_uop_debug_tsrc),
.io_lsu_resp_0_bits_data (_dcache_io_lsu_resp_0_bits_data),
.io_lsu_resp_0_bits_is_hella (_dcache_io_lsu_resp_0_bits_is_hella),
.io_lsu_nack_0_valid (_dcache_io_lsu_nack_0_valid),
.io_lsu_nack_0_bits_uop_uopc (_dcache_io_lsu_nack_0_bits_uop_uopc),
.io_lsu_nack_0_bits_uop_inst (_dcache_io_lsu_nack_0_bits_uop_inst),
.io_lsu_nack_0_bits_uop_debug_inst (_dcache_io_lsu_nack_0_bits_uop_debug_inst),
.io_lsu_nack_0_bits_uop_is_rvc (_dcache_io_lsu_nack_0_bits_uop_is_rvc),
.io_lsu_nack_0_bits_uop_debug_pc (_dcache_io_lsu_nack_0_bits_uop_debug_pc),
.io_lsu_nack_0_bits_uop_iq_type (_dcache_io_lsu_nack_0_bits_uop_iq_type),
.io_lsu_nack_0_bits_uop_fu_code (_dcache_io_lsu_nack_0_bits_uop_fu_code),
.io_lsu_nack_0_bits_uop_ctrl_br_type (_dcache_io_lsu_nack_0_bits_uop_ctrl_br_type),
.io_lsu_nack_0_bits_uop_ctrl_op1_sel (_dcache_io_lsu_nack_0_bits_uop_ctrl_op1_sel),
.io_lsu_nack_0_bits_uop_ctrl_op2_sel (_dcache_io_lsu_nack_0_bits_uop_ctrl_op2_sel),
.io_lsu_nack_0_bits_uop_ctrl_imm_sel (_dcache_io_lsu_nack_0_bits_uop_ctrl_imm_sel),
.io_lsu_nack_0_bits_uop_ctrl_op_fcn (_dcache_io_lsu_nack_0_bits_uop_ctrl_op_fcn),
.io_lsu_nack_0_bits_uop_ctrl_fcn_dw (_dcache_io_lsu_nack_0_bits_uop_ctrl_fcn_dw),
.io_lsu_nack_0_bits_uop_ctrl_csr_cmd (_dcache_io_lsu_nack_0_bits_uop_ctrl_csr_cmd),
.io_lsu_nack_0_bits_uop_ctrl_is_load (_dcache_io_lsu_nack_0_bits_uop_ctrl_is_load),
.io_lsu_nack_0_bits_uop_ctrl_is_sta (_dcache_io_lsu_nack_0_bits_uop_ctrl_is_sta),
.io_lsu_nack_0_bits_uop_ctrl_is_std (_dcache_io_lsu_nack_0_bits_uop_ctrl_is_std),
.io_lsu_nack_0_bits_uop_iw_state (_dcache_io_lsu_nack_0_bits_uop_iw_state),
.io_lsu_nack_0_bits_uop_iw_p1_poisoned (_dcache_io_lsu_nack_0_bits_uop_iw_p1_poisoned),
.io_lsu_nack_0_bits_uop_iw_p2_poisoned (_dcache_io_lsu_nack_0_bits_uop_iw_p2_poisoned),
.io_lsu_nack_0_bits_uop_is_br (_dcache_io_lsu_nack_0_bits_uop_is_br),
.io_lsu_nack_0_bits_uop_is_jalr (_dcache_io_lsu_nack_0_bits_uop_is_jalr),
.io_lsu_nack_0_bits_uop_is_jal (_dcache_io_lsu_nack_0_bits_uop_is_jal),
.io_lsu_nack_0_bits_uop_is_sfb (_dcache_io_lsu_nack_0_bits_uop_is_sfb),
.io_lsu_nack_0_bits_uop_br_mask (_dcache_io_lsu_nack_0_bits_uop_br_mask),
.io_lsu_nack_0_bits_uop_br_tag (_dcache_io_lsu_nack_0_bits_uop_br_tag),
.io_lsu_nack_0_bits_uop_ftq_idx (_dcache_io_lsu_nack_0_bits_uop_ftq_idx),
.io_lsu_nack_0_bits_uop_edge_inst (_dcache_io_lsu_nack_0_bits_uop_edge_inst),
.io_lsu_nack_0_bits_uop_pc_lob (_dcache_io_lsu_nack_0_bits_uop_pc_lob),
.io_lsu_nack_0_bits_uop_taken (_dcache_io_lsu_nack_0_bits_uop_taken),
.io_lsu_nack_0_bits_uop_imm_packed (_dcache_io_lsu_nack_0_bits_uop_imm_packed),
.io_lsu_nack_0_bits_uop_csr_addr (_dcache_io_lsu_nack_0_bits_uop_csr_addr),
.io_lsu_nack_0_bits_uop_rob_idx (_dcache_io_lsu_nack_0_bits_uop_rob_idx),
.io_lsu_nack_0_bits_uop_ldq_idx (_dcache_io_lsu_nack_0_bits_uop_ldq_idx),
.io_lsu_nack_0_bits_uop_stq_idx (_dcache_io_lsu_nack_0_bits_uop_stq_idx),
.io_lsu_nack_0_bits_uop_rxq_idx (_dcache_io_lsu_nack_0_bits_uop_rxq_idx),
.io_lsu_nack_0_bits_uop_pdst (_dcache_io_lsu_nack_0_bits_uop_pdst),
.io_lsu_nack_0_bits_uop_prs1 (_dcache_io_lsu_nack_0_bits_uop_prs1),
.io_lsu_nack_0_bits_uop_prs2 (_dcache_io_lsu_nack_0_bits_uop_prs2),
.io_lsu_nack_0_bits_uop_prs3 (_dcache_io_lsu_nack_0_bits_uop_prs3),
.io_lsu_nack_0_bits_uop_ppred (_dcache_io_lsu_nack_0_bits_uop_ppred),
.io_lsu_nack_0_bits_uop_prs1_busy (_dcache_io_lsu_nack_0_bits_uop_prs1_busy),
.io_lsu_nack_0_bits_uop_prs2_busy (_dcache_io_lsu_nack_0_bits_uop_prs2_busy),
.io_lsu_nack_0_bits_uop_prs3_busy (_dcache_io_lsu_nack_0_bits_uop_prs3_busy),
.io_lsu_nack_0_bits_uop_ppred_busy (_dcache_io_lsu_nack_0_bits_uop_ppred_busy),
.io_lsu_nack_0_bits_uop_stale_pdst (_dcache_io_lsu_nack_0_bits_uop_stale_pdst),
.io_lsu_nack_0_bits_uop_exception (_dcache_io_lsu_nack_0_bits_uop_exception),
.io_lsu_nack_0_bits_uop_exc_cause (_dcache_io_lsu_nack_0_bits_uop_exc_cause),
.io_lsu_nack_0_bits_uop_bypassable (_dcache_io_lsu_nack_0_bits_uop_bypassable),
.io_lsu_nack_0_bits_uop_mem_cmd (_dcache_io_lsu_nack_0_bits_uop_mem_cmd),
.io_lsu_nack_0_bits_uop_mem_size (_dcache_io_lsu_nack_0_bits_uop_mem_size),
.io_lsu_nack_0_bits_uop_mem_signed (_dcache_io_lsu_nack_0_bits_uop_mem_signed),
.io_lsu_nack_0_bits_uop_is_fence (_dcache_io_lsu_nack_0_bits_uop_is_fence),
.io_lsu_nack_0_bits_uop_is_fencei (_dcache_io_lsu_nack_0_bits_uop_is_fencei),
.io_lsu_nack_0_bits_uop_is_amo (_dcache_io_lsu_nack_0_bits_uop_is_amo),
.io_lsu_nack_0_bits_uop_uses_ldq (_dcache_io_lsu_nack_0_bits_uop_uses_ldq),
.io_lsu_nack_0_bits_uop_uses_stq (_dcache_io_lsu_nack_0_bits_uop_uses_stq),
.io_lsu_nack_0_bits_uop_is_sys_pc2epc (_dcache_io_lsu_nack_0_bits_uop_is_sys_pc2epc),
.io_lsu_nack_0_bits_uop_is_unique (_dcache_io_lsu_nack_0_bits_uop_is_unique),
.io_lsu_nack_0_bits_uop_flush_on_commit (_dcache_io_lsu_nack_0_bits_uop_flush_on_commit),
.io_lsu_nack_0_bits_uop_ldst_is_rs1 (_dcache_io_lsu_nack_0_bits_uop_ldst_is_rs1),
.io_lsu_nack_0_bits_uop_ldst (_dcache_io_lsu_nack_0_bits_uop_ldst),
.io_lsu_nack_0_bits_uop_lrs1 (_dcache_io_lsu_nack_0_bits_uop_lrs1),
.io_lsu_nack_0_bits_uop_lrs2 (_dcache_io_lsu_nack_0_bits_uop_lrs2),
.io_lsu_nack_0_bits_uop_lrs3 (_dcache_io_lsu_nack_0_bits_uop_lrs3),
.io_lsu_nack_0_bits_uop_ldst_val (_dcache_io_lsu_nack_0_bits_uop_ldst_val),
.io_lsu_nack_0_bits_uop_dst_rtype (_dcache_io_lsu_nack_0_bits_uop_dst_rtype),
.io_lsu_nack_0_bits_uop_lrs1_rtype (_dcache_io_lsu_nack_0_bits_uop_lrs1_rtype),
.io_lsu_nack_0_bits_uop_lrs2_rtype (_dcache_io_lsu_nack_0_bits_uop_lrs2_rtype),
.io_lsu_nack_0_bits_uop_frs3_en (_dcache_io_lsu_nack_0_bits_uop_frs3_en),
.io_lsu_nack_0_bits_uop_fp_val (_dcache_io_lsu_nack_0_bits_uop_fp_val),
.io_lsu_nack_0_bits_uop_fp_single (_dcache_io_lsu_nack_0_bits_uop_fp_single),
.io_lsu_nack_0_bits_uop_xcpt_pf_if (_dcache_io_lsu_nack_0_bits_uop_xcpt_pf_if),
.io_lsu_nack_0_bits_uop_xcpt_ae_if (_dcache_io_lsu_nack_0_bits_uop_xcpt_ae_if),
.io_lsu_nack_0_bits_uop_xcpt_ma_if (_dcache_io_lsu_nack_0_bits_uop_xcpt_ma_if),
.io_lsu_nack_0_bits_uop_bp_debug_if (_dcache_io_lsu_nack_0_bits_uop_bp_debug_if),
.io_lsu_nack_0_bits_uop_bp_xcpt_if (_dcache_io_lsu_nack_0_bits_uop_bp_xcpt_if),
.io_lsu_nack_0_bits_uop_debug_fsrc (_dcache_io_lsu_nack_0_bits_uop_debug_fsrc),
.io_lsu_nack_0_bits_uop_debug_tsrc (_dcache_io_lsu_nack_0_bits_uop_debug_tsrc),
.io_lsu_nack_0_bits_addr (_dcache_io_lsu_nack_0_bits_addr),
.io_lsu_nack_0_bits_data (_dcache_io_lsu_nack_0_bits_data),
.io_lsu_nack_0_bits_is_hella (_dcache_io_lsu_nack_0_bits_is_hella),
.io_lsu_brupdate_b1_resolve_mask (_lsu_io_dmem_brupdate_b1_resolve_mask), // @[tile.scala:160:20]
.io_lsu_brupdate_b1_mispredict_mask (_lsu_io_dmem_brupdate_b1_mispredict_mask), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_uopc (_lsu_io_dmem_brupdate_b2_uop_uopc), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_inst (_lsu_io_dmem_brupdate_b2_uop_inst), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_debug_inst (_lsu_io_dmem_brupdate_b2_uop_debug_inst), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_is_rvc (_lsu_io_dmem_brupdate_b2_uop_is_rvc), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_debug_pc (_lsu_io_dmem_brupdate_b2_uop_debug_pc), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_iq_type (_lsu_io_dmem_brupdate_b2_uop_iq_type), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_fu_code (_lsu_io_dmem_brupdate_b2_uop_fu_code), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_ctrl_br_type (_lsu_io_dmem_brupdate_b2_uop_ctrl_br_type), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_ctrl_op1_sel (_lsu_io_dmem_brupdate_b2_uop_ctrl_op1_sel), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_ctrl_op2_sel (_lsu_io_dmem_brupdate_b2_uop_ctrl_op2_sel), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_ctrl_imm_sel (_lsu_io_dmem_brupdate_b2_uop_ctrl_imm_sel), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_ctrl_op_fcn (_lsu_io_dmem_brupdate_b2_uop_ctrl_op_fcn), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_ctrl_fcn_dw (_lsu_io_dmem_brupdate_b2_uop_ctrl_fcn_dw), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_ctrl_csr_cmd (_lsu_io_dmem_brupdate_b2_uop_ctrl_csr_cmd), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_ctrl_is_load (_lsu_io_dmem_brupdate_b2_uop_ctrl_is_load), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_ctrl_is_sta (_lsu_io_dmem_brupdate_b2_uop_ctrl_is_sta), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_ctrl_is_std (_lsu_io_dmem_brupdate_b2_uop_ctrl_is_std), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_iw_state (_lsu_io_dmem_brupdate_b2_uop_iw_state), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_iw_p1_poisoned (_lsu_io_dmem_brupdate_b2_uop_iw_p1_poisoned), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_iw_p2_poisoned (_lsu_io_dmem_brupdate_b2_uop_iw_p2_poisoned), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_is_br (_lsu_io_dmem_brupdate_b2_uop_is_br), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_is_jalr (_lsu_io_dmem_brupdate_b2_uop_is_jalr), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_is_jal (_lsu_io_dmem_brupdate_b2_uop_is_jal), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_is_sfb (_lsu_io_dmem_brupdate_b2_uop_is_sfb), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_br_mask (_lsu_io_dmem_brupdate_b2_uop_br_mask), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_br_tag (_lsu_io_dmem_brupdate_b2_uop_br_tag), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_ftq_idx (_lsu_io_dmem_brupdate_b2_uop_ftq_idx), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_edge_inst (_lsu_io_dmem_brupdate_b2_uop_edge_inst), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_pc_lob (_lsu_io_dmem_brupdate_b2_uop_pc_lob), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_taken (_lsu_io_dmem_brupdate_b2_uop_taken), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_imm_packed (_lsu_io_dmem_brupdate_b2_uop_imm_packed), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_csr_addr (_lsu_io_dmem_brupdate_b2_uop_csr_addr), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_rob_idx (_lsu_io_dmem_brupdate_b2_uop_rob_idx), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_ldq_idx (_lsu_io_dmem_brupdate_b2_uop_ldq_idx), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_stq_idx (_lsu_io_dmem_brupdate_b2_uop_stq_idx), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_rxq_idx (_lsu_io_dmem_brupdate_b2_uop_rxq_idx), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_pdst (_lsu_io_dmem_brupdate_b2_uop_pdst), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_prs1 (_lsu_io_dmem_brupdate_b2_uop_prs1), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_prs2 (_lsu_io_dmem_brupdate_b2_uop_prs2), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_prs3 (_lsu_io_dmem_brupdate_b2_uop_prs3), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_ppred (_lsu_io_dmem_brupdate_b2_uop_ppred), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_prs1_busy (_lsu_io_dmem_brupdate_b2_uop_prs1_busy), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_prs2_busy (_lsu_io_dmem_brupdate_b2_uop_prs2_busy), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_prs3_busy (_lsu_io_dmem_brupdate_b2_uop_prs3_busy), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_ppred_busy (_lsu_io_dmem_brupdate_b2_uop_ppred_busy), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_stale_pdst (_lsu_io_dmem_brupdate_b2_uop_stale_pdst), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_exception (_lsu_io_dmem_brupdate_b2_uop_exception), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_exc_cause (_lsu_io_dmem_brupdate_b2_uop_exc_cause), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_bypassable (_lsu_io_dmem_brupdate_b2_uop_bypassable), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_mem_cmd (_lsu_io_dmem_brupdate_b2_uop_mem_cmd), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_mem_size (_lsu_io_dmem_brupdate_b2_uop_mem_size), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_mem_signed (_lsu_io_dmem_brupdate_b2_uop_mem_signed), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_is_fence (_lsu_io_dmem_brupdate_b2_uop_is_fence), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_is_fencei (_lsu_io_dmem_brupdate_b2_uop_is_fencei), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_is_amo (_lsu_io_dmem_brupdate_b2_uop_is_amo), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_uses_ldq (_lsu_io_dmem_brupdate_b2_uop_uses_ldq), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_uses_stq (_lsu_io_dmem_brupdate_b2_uop_uses_stq), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_is_sys_pc2epc (_lsu_io_dmem_brupdate_b2_uop_is_sys_pc2epc), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_is_unique (_lsu_io_dmem_brupdate_b2_uop_is_unique), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_flush_on_commit (_lsu_io_dmem_brupdate_b2_uop_flush_on_commit), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_ldst_is_rs1 (_lsu_io_dmem_brupdate_b2_uop_ldst_is_rs1), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_ldst (_lsu_io_dmem_brupdate_b2_uop_ldst), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_lrs1 (_lsu_io_dmem_brupdate_b2_uop_lrs1), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_lrs2 (_lsu_io_dmem_brupdate_b2_uop_lrs2), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_lrs3 (_lsu_io_dmem_brupdate_b2_uop_lrs3), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_ldst_val (_lsu_io_dmem_brupdate_b2_uop_ldst_val), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_dst_rtype (_lsu_io_dmem_brupdate_b2_uop_dst_rtype), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_lrs1_rtype (_lsu_io_dmem_brupdate_b2_uop_lrs1_rtype), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_lrs2_rtype (_lsu_io_dmem_brupdate_b2_uop_lrs2_rtype), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_frs3_en (_lsu_io_dmem_brupdate_b2_uop_frs3_en), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_fp_val (_lsu_io_dmem_brupdate_b2_uop_fp_val), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_fp_single (_lsu_io_dmem_brupdate_b2_uop_fp_single), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_xcpt_pf_if (_lsu_io_dmem_brupdate_b2_uop_xcpt_pf_if), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_xcpt_ae_if (_lsu_io_dmem_brupdate_b2_uop_xcpt_ae_if), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_xcpt_ma_if (_lsu_io_dmem_brupdate_b2_uop_xcpt_ma_if), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_bp_debug_if (_lsu_io_dmem_brupdate_b2_uop_bp_debug_if), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_bp_xcpt_if (_lsu_io_dmem_brupdate_b2_uop_bp_xcpt_if), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_debug_fsrc (_lsu_io_dmem_brupdate_b2_uop_debug_fsrc), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_debug_tsrc (_lsu_io_dmem_brupdate_b2_uop_debug_tsrc), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_valid (_lsu_io_dmem_brupdate_b2_valid), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_mispredict (_lsu_io_dmem_brupdate_b2_mispredict), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_taken (_lsu_io_dmem_brupdate_b2_taken), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_cfi_type (_lsu_io_dmem_brupdate_b2_cfi_type), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_pc_sel (_lsu_io_dmem_brupdate_b2_pc_sel), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_jalr_target (_lsu_io_dmem_brupdate_b2_jalr_target), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_target_offset (_lsu_io_dmem_brupdate_b2_target_offset), // @[tile.scala:160:20]
.io_lsu_exception (_lsu_io_dmem_exception), // @[tile.scala:160:20]
.io_lsu_rob_pnr_idx (_lsu_io_dmem_rob_pnr_idx), // @[tile.scala:160:20]
.io_lsu_rob_head_idx (_lsu_io_dmem_rob_head_idx), // @[tile.scala:160:20]
.io_lsu_release_ready (_lsu_io_dmem_release_ready), // @[tile.scala:160:20]
.io_lsu_release_valid (_dcache_io_lsu_release_valid),
.io_lsu_release_bits_opcode (_dcache_io_lsu_release_bits_opcode),
.io_lsu_release_bits_param (_dcache_io_lsu_release_bits_param),
.io_lsu_release_bits_size (_dcache_io_lsu_release_bits_size),
.io_lsu_release_bits_source (_dcache_io_lsu_release_bits_source),
.io_lsu_release_bits_address (_dcache_io_lsu_release_bits_address),
.io_lsu_release_bits_data (_dcache_io_lsu_release_bits_data),
.io_lsu_force_order (_lsu_io_dmem_force_order), // @[tile.scala:160:20]
.io_lsu_ordered (_dcache_io_lsu_ordered),
.io_lsu_perf_acquire (_dcache_io_lsu_perf_acquire),
.io_lsu_perf_release (_dcache_io_lsu_perf_release)
); // @[tile.scala:132:54]
BoomFrontend frontend ( // @[tile.scala:138:28]
.clock (clock),
.reset (reset),
.auto_icache_master_out_a_ready (widget_1_auto_anon_in_a_ready), // @[WidthWidget.scala:27:9]
.auto_icache_master_out_a_valid (widget_1_auto_anon_in_a_valid),
.auto_icache_master_out_a_bits_address (widget_1_auto_anon_in_a_bits_address),
.auto_icache_master_out_d_valid (widget_1_auto_anon_in_d_valid), // @[WidthWidget.scala:27:9]
.auto_icache_master_out_d_bits_opcode (widget_1_auto_anon_in_d_bits_opcode), // @[WidthWidget.scala:27:9]
.auto_icache_master_out_d_bits_param (widget_1_auto_anon_in_d_bits_param), // @[WidthWidget.scala:27:9]
.auto_icache_master_out_d_bits_size (widget_1_auto_anon_in_d_bits_size), // @[WidthWidget.scala:27:9]
.auto_icache_master_out_d_bits_sink (widget_1_auto_anon_in_d_bits_sink), // @[WidthWidget.scala:27:9]
.auto_icache_master_out_d_bits_denied (widget_1_auto_anon_in_d_bits_denied), // @[WidthWidget.scala:27:9]
.auto_icache_master_out_d_bits_data (widget_1_auto_anon_in_d_bits_data), // @[WidthWidget.scala:27:9]
.auto_icache_master_out_d_bits_corrupt (widget_1_auto_anon_in_d_bits_corrupt), // @[WidthWidget.scala:27:9]
.io_cpu_fetchpacket_ready (_core_io_ifu_fetchpacket_ready), // @[tile.scala:159:20]
.io_cpu_fetchpacket_valid (_frontend_io_cpu_fetchpacket_valid),
.io_cpu_fetchpacket_bits_uops_0_valid (_frontend_io_cpu_fetchpacket_bits_uops_0_valid),
.io_cpu_fetchpacket_bits_uops_0_bits_inst (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_inst),
.io_cpu_fetchpacket_bits_uops_0_bits_debug_inst (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_debug_inst),
.io_cpu_fetchpacket_bits_uops_0_bits_is_rvc (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_is_rvc),
.io_cpu_fetchpacket_bits_uops_0_bits_debug_pc (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_debug_pc),
.io_cpu_fetchpacket_bits_uops_0_bits_is_sfb (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_is_sfb),
.io_cpu_fetchpacket_bits_uops_0_bits_ftq_idx (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_ftq_idx),
.io_cpu_fetchpacket_bits_uops_0_bits_edge_inst (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_edge_inst),
.io_cpu_fetchpacket_bits_uops_0_bits_pc_lob (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_pc_lob),
.io_cpu_fetchpacket_bits_uops_0_bits_taken (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_taken),
.io_cpu_fetchpacket_bits_uops_0_bits_xcpt_pf_if (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_xcpt_pf_if),
.io_cpu_fetchpacket_bits_uops_0_bits_xcpt_ae_if (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_xcpt_ae_if),
.io_cpu_fetchpacket_bits_uops_0_bits_bp_debug_if (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_bp_debug_if),
.io_cpu_fetchpacket_bits_uops_0_bits_bp_xcpt_if (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_bp_xcpt_if),
.io_cpu_fetchpacket_bits_uops_0_bits_debug_fsrc (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_debug_fsrc),
.io_cpu_fetchpacket_bits_uops_1_valid (_frontend_io_cpu_fetchpacket_bits_uops_1_valid),
.io_cpu_fetchpacket_bits_uops_1_bits_inst (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_inst),
.io_cpu_fetchpacket_bits_uops_1_bits_debug_inst (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_debug_inst),
.io_cpu_fetchpacket_bits_uops_1_bits_is_rvc (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_is_rvc),
.io_cpu_fetchpacket_bits_uops_1_bits_debug_pc (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_debug_pc),
.io_cpu_fetchpacket_bits_uops_1_bits_is_sfb (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_is_sfb),
.io_cpu_fetchpacket_bits_uops_1_bits_ftq_idx (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_ftq_idx),
.io_cpu_fetchpacket_bits_uops_1_bits_edge_inst (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_edge_inst),
.io_cpu_fetchpacket_bits_uops_1_bits_pc_lob (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_pc_lob),
.io_cpu_fetchpacket_bits_uops_1_bits_taken (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_taken),
.io_cpu_fetchpacket_bits_uops_1_bits_xcpt_pf_if (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_xcpt_pf_if),
.io_cpu_fetchpacket_bits_uops_1_bits_xcpt_ae_if (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_xcpt_ae_if),
.io_cpu_fetchpacket_bits_uops_1_bits_bp_debug_if (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_bp_debug_if),
.io_cpu_fetchpacket_bits_uops_1_bits_bp_xcpt_if (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_bp_xcpt_if),
.io_cpu_fetchpacket_bits_uops_1_bits_debug_fsrc (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_debug_fsrc),
.io_cpu_fetchpacket_bits_uops_2_valid (_frontend_io_cpu_fetchpacket_bits_uops_2_valid),
.io_cpu_fetchpacket_bits_uops_2_bits_inst (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_inst),
.io_cpu_fetchpacket_bits_uops_2_bits_debug_inst (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_debug_inst),
.io_cpu_fetchpacket_bits_uops_2_bits_is_rvc (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_is_rvc),
.io_cpu_fetchpacket_bits_uops_2_bits_debug_pc (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_debug_pc),
.io_cpu_fetchpacket_bits_uops_2_bits_is_sfb (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_is_sfb),
.io_cpu_fetchpacket_bits_uops_2_bits_ftq_idx (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_ftq_idx),
.io_cpu_fetchpacket_bits_uops_2_bits_edge_inst (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_edge_inst),
.io_cpu_fetchpacket_bits_uops_2_bits_pc_lob (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_pc_lob),
.io_cpu_fetchpacket_bits_uops_2_bits_taken (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_taken),
.io_cpu_fetchpacket_bits_uops_2_bits_xcpt_pf_if (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_xcpt_pf_if),
.io_cpu_fetchpacket_bits_uops_2_bits_xcpt_ae_if (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_xcpt_ae_if),
.io_cpu_fetchpacket_bits_uops_2_bits_bp_debug_if (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_bp_debug_if),
.io_cpu_fetchpacket_bits_uops_2_bits_bp_xcpt_if (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_bp_xcpt_if),
.io_cpu_fetchpacket_bits_uops_2_bits_debug_fsrc (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_debug_fsrc),
.io_cpu_get_pc_0_ftq_idx (_core_io_ifu_get_pc_0_ftq_idx), // @[tile.scala:159:20]
.io_cpu_get_pc_0_entry_cfi_idx_valid (_frontend_io_cpu_get_pc_0_entry_cfi_idx_valid),
.io_cpu_get_pc_0_entry_cfi_idx_bits (_frontend_io_cpu_get_pc_0_entry_cfi_idx_bits),
.io_cpu_get_pc_0_entry_cfi_taken (_frontend_io_cpu_get_pc_0_entry_cfi_taken),
.io_cpu_get_pc_0_entry_cfi_mispredicted (_frontend_io_cpu_get_pc_0_entry_cfi_mispredicted),
.io_cpu_get_pc_0_entry_cfi_type (_frontend_io_cpu_get_pc_0_entry_cfi_type),
.io_cpu_get_pc_0_entry_br_mask (_frontend_io_cpu_get_pc_0_entry_br_mask),
.io_cpu_get_pc_0_entry_cfi_is_call (_frontend_io_cpu_get_pc_0_entry_cfi_is_call),
.io_cpu_get_pc_0_entry_cfi_is_ret (_frontend_io_cpu_get_pc_0_entry_cfi_is_ret),
.io_cpu_get_pc_0_entry_cfi_npc_plus4 (_frontend_io_cpu_get_pc_0_entry_cfi_npc_plus4),
.io_cpu_get_pc_0_entry_ras_top (_frontend_io_cpu_get_pc_0_entry_ras_top),
.io_cpu_get_pc_0_entry_ras_idx (_frontend_io_cpu_get_pc_0_entry_ras_idx),
.io_cpu_get_pc_0_entry_start_bank (_frontend_io_cpu_get_pc_0_entry_start_bank),
.io_cpu_get_pc_0_pc (_frontend_io_cpu_get_pc_0_pc),
.io_cpu_get_pc_0_com_pc (_frontend_io_cpu_get_pc_0_com_pc),
.io_cpu_get_pc_0_next_val (_frontend_io_cpu_get_pc_0_next_val),
.io_cpu_get_pc_0_next_pc (_frontend_io_cpu_get_pc_0_next_pc),
.io_cpu_get_pc_1_ftq_idx (_core_io_ifu_get_pc_1_ftq_idx), // @[tile.scala:159:20]
.io_cpu_get_pc_1_entry_cfi_idx_valid (_frontend_io_cpu_get_pc_1_entry_cfi_idx_valid),
.io_cpu_get_pc_1_entry_cfi_idx_bits (_frontend_io_cpu_get_pc_1_entry_cfi_idx_bits),
.io_cpu_get_pc_1_entry_cfi_taken (_frontend_io_cpu_get_pc_1_entry_cfi_taken),
.io_cpu_get_pc_1_entry_cfi_mispredicted (_frontend_io_cpu_get_pc_1_entry_cfi_mispredicted),
.io_cpu_get_pc_1_entry_cfi_type (_frontend_io_cpu_get_pc_1_entry_cfi_type),
.io_cpu_get_pc_1_entry_br_mask (_frontend_io_cpu_get_pc_1_entry_br_mask),
.io_cpu_get_pc_1_entry_cfi_is_call (_frontend_io_cpu_get_pc_1_entry_cfi_is_call),
.io_cpu_get_pc_1_entry_cfi_is_ret (_frontend_io_cpu_get_pc_1_entry_cfi_is_ret),
.io_cpu_get_pc_1_entry_cfi_npc_plus4 (_frontend_io_cpu_get_pc_1_entry_cfi_npc_plus4),
.io_cpu_get_pc_1_entry_ras_top (_frontend_io_cpu_get_pc_1_entry_ras_top),
.io_cpu_get_pc_1_entry_ras_idx (_frontend_io_cpu_get_pc_1_entry_ras_idx),
.io_cpu_get_pc_1_entry_start_bank (_frontend_io_cpu_get_pc_1_entry_start_bank),
.io_cpu_get_pc_1_ghist_old_history (_frontend_io_cpu_get_pc_1_ghist_old_history),
.io_cpu_get_pc_1_ghist_current_saw_branch_not_taken (_frontend_io_cpu_get_pc_1_ghist_current_saw_branch_not_taken),
.io_cpu_get_pc_1_ghist_new_saw_branch_not_taken (_frontend_io_cpu_get_pc_1_ghist_new_saw_branch_not_taken),
.io_cpu_get_pc_1_ghist_new_saw_branch_taken (_frontend_io_cpu_get_pc_1_ghist_new_saw_branch_taken),
.io_cpu_get_pc_1_ghist_ras_idx (_frontend_io_cpu_get_pc_1_ghist_ras_idx),
.io_cpu_get_pc_1_pc (_frontend_io_cpu_get_pc_1_pc),
.io_cpu_get_pc_1_com_pc (_frontend_io_cpu_get_pc_1_com_pc),
.io_cpu_get_pc_1_next_val (_frontend_io_cpu_get_pc_1_next_val),
.io_cpu_get_pc_1_next_pc (_frontend_io_cpu_get_pc_1_next_pc),
.io_cpu_debug_fetch_pc_0 (_frontend_io_cpu_debug_fetch_pc_0),
.io_cpu_debug_fetch_pc_1 (_frontend_io_cpu_debug_fetch_pc_1),
.io_cpu_debug_fetch_pc_2 (_frontend_io_cpu_debug_fetch_pc_2),
.io_cpu_status_debug (_core_io_ifu_status_debug), // @[tile.scala:159:20]
.io_cpu_status_cease (_core_io_ifu_status_cease), // @[tile.scala:159:20]
.io_cpu_status_wfi (_core_io_ifu_status_wfi), // @[tile.scala:159:20]
.io_cpu_status_dprv (_core_io_ifu_status_dprv), // @[tile.scala:159:20]
.io_cpu_status_dv (_core_io_ifu_status_dv), // @[tile.scala:159:20]
.io_cpu_status_prv (_core_io_ifu_status_prv), // @[tile.scala:159:20]
.io_cpu_status_v (_core_io_ifu_status_v), // @[tile.scala:159:20]
.io_cpu_status_sd (_core_io_ifu_status_sd), // @[tile.scala:159:20]
.io_cpu_status_mpv (_core_io_ifu_status_mpv), // @[tile.scala:159:20]
.io_cpu_status_gva (_core_io_ifu_status_gva), // @[tile.scala:159:20]
.io_cpu_status_tsr (_core_io_ifu_status_tsr), // @[tile.scala:159:20]
.io_cpu_status_tw (_core_io_ifu_status_tw), // @[tile.scala:159:20]
.io_cpu_status_tvm (_core_io_ifu_status_tvm), // @[tile.scala:159:20]
.io_cpu_status_mxr (_core_io_ifu_status_mxr), // @[tile.scala:159:20]
.io_cpu_status_sum (_core_io_ifu_status_sum), // @[tile.scala:159:20]
.io_cpu_status_mprv (_core_io_ifu_status_mprv), // @[tile.scala:159:20]
.io_cpu_status_fs (_core_io_ifu_status_fs), // @[tile.scala:159:20]
.io_cpu_status_mpp (_core_io_ifu_status_mpp), // @[tile.scala:159:20]
.io_cpu_status_spp (_core_io_ifu_status_spp), // @[tile.scala:159:20]
.io_cpu_status_mpie (_core_io_ifu_status_mpie), // @[tile.scala:159:20]
.io_cpu_status_spie (_core_io_ifu_status_spie), // @[tile.scala:159:20]
.io_cpu_status_mie (_core_io_ifu_status_mie), // @[tile.scala:159:20]
.io_cpu_status_sie (_core_io_ifu_status_sie), // @[tile.scala:159:20]
.io_cpu_sfence_valid (_core_io_ifu_sfence_valid), // @[tile.scala:159:20]
.io_cpu_sfence_bits_rs1 (_core_io_ifu_sfence_bits_rs1), // @[tile.scala:159:20]
.io_cpu_sfence_bits_rs2 (_core_io_ifu_sfence_bits_rs2), // @[tile.scala:159:20]
.io_cpu_sfence_bits_addr (_core_io_ifu_sfence_bits_addr), // @[tile.scala:159:20]
.io_cpu_sfence_bits_asid (_core_io_ifu_sfence_bits_asid), // @[tile.scala:159:20]
.io_cpu_brupdate_b1_resolve_mask (_core_io_ifu_brupdate_b1_resolve_mask), // @[tile.scala:159:20]
.io_cpu_brupdate_b1_mispredict_mask (_core_io_ifu_brupdate_b1_mispredict_mask), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_uopc (_core_io_ifu_brupdate_b2_uop_uopc), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_inst (_core_io_ifu_brupdate_b2_uop_inst), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_debug_inst (_core_io_ifu_brupdate_b2_uop_debug_inst), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_is_rvc (_core_io_ifu_brupdate_b2_uop_is_rvc), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_debug_pc (_core_io_ifu_brupdate_b2_uop_debug_pc), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_iq_type (_core_io_ifu_brupdate_b2_uop_iq_type), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_fu_code (_core_io_ifu_brupdate_b2_uop_fu_code), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_ctrl_br_type (_core_io_ifu_brupdate_b2_uop_ctrl_br_type), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_ctrl_op1_sel (_core_io_ifu_brupdate_b2_uop_ctrl_op1_sel), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_ctrl_op2_sel (_core_io_ifu_brupdate_b2_uop_ctrl_op2_sel), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_ctrl_imm_sel (_core_io_ifu_brupdate_b2_uop_ctrl_imm_sel), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_ctrl_op_fcn (_core_io_ifu_brupdate_b2_uop_ctrl_op_fcn), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_ctrl_fcn_dw (_core_io_ifu_brupdate_b2_uop_ctrl_fcn_dw), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_ctrl_csr_cmd (_core_io_ifu_brupdate_b2_uop_ctrl_csr_cmd), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_ctrl_is_load (_core_io_ifu_brupdate_b2_uop_ctrl_is_load), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_ctrl_is_sta (_core_io_ifu_brupdate_b2_uop_ctrl_is_sta), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_ctrl_is_std (_core_io_ifu_brupdate_b2_uop_ctrl_is_std), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_iw_state (_core_io_ifu_brupdate_b2_uop_iw_state), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_iw_p1_poisoned (_core_io_ifu_brupdate_b2_uop_iw_p1_poisoned), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_iw_p2_poisoned (_core_io_ifu_brupdate_b2_uop_iw_p2_poisoned), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_is_br (_core_io_ifu_brupdate_b2_uop_is_br), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_is_jalr (_core_io_ifu_brupdate_b2_uop_is_jalr), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_is_jal (_core_io_ifu_brupdate_b2_uop_is_jal), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_is_sfb (_core_io_ifu_brupdate_b2_uop_is_sfb), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_br_mask (_core_io_ifu_brupdate_b2_uop_br_mask), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_br_tag (_core_io_ifu_brupdate_b2_uop_br_tag), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_ftq_idx (_core_io_ifu_brupdate_b2_uop_ftq_idx), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_edge_inst (_core_io_ifu_brupdate_b2_uop_edge_inst), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_pc_lob (_core_io_ifu_brupdate_b2_uop_pc_lob), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_taken (_core_io_ifu_brupdate_b2_uop_taken), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_imm_packed (_core_io_ifu_brupdate_b2_uop_imm_packed), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_csr_addr (_core_io_ifu_brupdate_b2_uop_csr_addr), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_rob_idx (_core_io_ifu_brupdate_b2_uop_rob_idx), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_ldq_idx (_core_io_ifu_brupdate_b2_uop_ldq_idx), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_stq_idx (_core_io_ifu_brupdate_b2_uop_stq_idx), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_rxq_idx (_core_io_ifu_brupdate_b2_uop_rxq_idx), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_pdst (_core_io_ifu_brupdate_b2_uop_pdst), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_prs1 (_core_io_ifu_brupdate_b2_uop_prs1), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_prs2 (_core_io_ifu_brupdate_b2_uop_prs2), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_prs3 (_core_io_ifu_brupdate_b2_uop_prs3), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_ppred (_core_io_ifu_brupdate_b2_uop_ppred), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_prs1_busy (_core_io_ifu_brupdate_b2_uop_prs1_busy), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_prs2_busy (_core_io_ifu_brupdate_b2_uop_prs2_busy), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_prs3_busy (_core_io_ifu_brupdate_b2_uop_prs3_busy), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_ppred_busy (_core_io_ifu_brupdate_b2_uop_ppred_busy), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_stale_pdst (_core_io_ifu_brupdate_b2_uop_stale_pdst), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_exception (_core_io_ifu_brupdate_b2_uop_exception), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_exc_cause (_core_io_ifu_brupdate_b2_uop_exc_cause), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_bypassable (_core_io_ifu_brupdate_b2_uop_bypassable), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_mem_cmd (_core_io_ifu_brupdate_b2_uop_mem_cmd), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_mem_size (_core_io_ifu_brupdate_b2_uop_mem_size), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_mem_signed (_core_io_ifu_brupdate_b2_uop_mem_signed), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_is_fence (_core_io_ifu_brupdate_b2_uop_is_fence), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_is_fencei (_core_io_ifu_brupdate_b2_uop_is_fencei), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_is_amo (_core_io_ifu_brupdate_b2_uop_is_amo), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_uses_ldq (_core_io_ifu_brupdate_b2_uop_uses_ldq), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_uses_stq (_core_io_ifu_brupdate_b2_uop_uses_stq), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_is_sys_pc2epc (_core_io_ifu_brupdate_b2_uop_is_sys_pc2epc), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_is_unique (_core_io_ifu_brupdate_b2_uop_is_unique), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_flush_on_commit (_core_io_ifu_brupdate_b2_uop_flush_on_commit), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_ldst_is_rs1 (_core_io_ifu_brupdate_b2_uop_ldst_is_rs1), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_ldst (_core_io_ifu_brupdate_b2_uop_ldst), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_lrs1 (_core_io_ifu_brupdate_b2_uop_lrs1), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_lrs2 (_core_io_ifu_brupdate_b2_uop_lrs2), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_lrs3 (_core_io_ifu_brupdate_b2_uop_lrs3), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_ldst_val (_core_io_ifu_brupdate_b2_uop_ldst_val), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_dst_rtype (_core_io_ifu_brupdate_b2_uop_dst_rtype), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_lrs1_rtype (_core_io_ifu_brupdate_b2_uop_lrs1_rtype), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_lrs2_rtype (_core_io_ifu_brupdate_b2_uop_lrs2_rtype), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_frs3_en (_core_io_ifu_brupdate_b2_uop_frs3_en), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_fp_val (_core_io_ifu_brupdate_b2_uop_fp_val), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_fp_single (_core_io_ifu_brupdate_b2_uop_fp_single), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_xcpt_pf_if (_core_io_ifu_brupdate_b2_uop_xcpt_pf_if), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_xcpt_ae_if (_core_io_ifu_brupdate_b2_uop_xcpt_ae_if), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_xcpt_ma_if (_core_io_ifu_brupdate_b2_uop_xcpt_ma_if), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_bp_debug_if (_core_io_ifu_brupdate_b2_uop_bp_debug_if), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_bp_xcpt_if (_core_io_ifu_brupdate_b2_uop_bp_xcpt_if), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_debug_fsrc (_core_io_ifu_brupdate_b2_uop_debug_fsrc), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_debug_tsrc (_core_io_ifu_brupdate_b2_uop_debug_tsrc), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_valid (_core_io_ifu_brupdate_b2_valid), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_mispredict (_core_io_ifu_brupdate_b2_mispredict), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_taken (_core_io_ifu_brupdate_b2_taken), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_cfi_type (_core_io_ifu_brupdate_b2_cfi_type), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_pc_sel (_core_io_ifu_brupdate_b2_pc_sel), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_jalr_target (_core_io_ifu_brupdate_b2_jalr_target), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_target_offset (_core_io_ifu_brupdate_b2_target_offset), // @[tile.scala:159:20]
.io_cpu_redirect_flush (_core_io_ifu_redirect_flush), // @[tile.scala:159:20]
.io_cpu_redirect_val (_core_io_ifu_redirect_val), // @[tile.scala:159:20]
.io_cpu_redirect_pc (_core_io_ifu_redirect_pc), // @[tile.scala:159:20]
.io_cpu_redirect_ftq_idx (_core_io_ifu_redirect_ftq_idx), // @[tile.scala:159:20]
.io_cpu_redirect_ghist_old_history (_core_io_ifu_redirect_ghist_old_history), // @[tile.scala:159:20]
.io_cpu_redirect_ghist_current_saw_branch_not_taken (_core_io_ifu_redirect_ghist_current_saw_branch_not_taken), // @[tile.scala:159:20]
.io_cpu_redirect_ghist_new_saw_branch_not_taken (_core_io_ifu_redirect_ghist_new_saw_branch_not_taken), // @[tile.scala:159:20]
.io_cpu_redirect_ghist_new_saw_branch_taken (_core_io_ifu_redirect_ghist_new_saw_branch_taken), // @[tile.scala:159:20]
.io_cpu_redirect_ghist_ras_idx (_core_io_ifu_redirect_ghist_ras_idx), // @[tile.scala:159:20]
.io_cpu_commit_valid (_core_io_ifu_commit_valid), // @[tile.scala:159:20]
.io_cpu_commit_bits (_core_io_ifu_commit_bits), // @[tile.scala:159:20]
.io_cpu_flush_icache (_core_io_ifu_flush_icache), // @[tile.scala:159:20]
.io_cpu_perf_acquire (_frontend_io_cpu_perf_acquire),
.io_cpu_perf_tlbMiss (_frontend_io_cpu_perf_tlbMiss),
.io_ptw_req_ready (_ptw_io_requestor_1_req_ready), // @[tile.scala:237:20]
.io_ptw_req_valid (_frontend_io_ptw_req_valid),
.io_ptw_req_bits_bits_addr (_frontend_io_ptw_req_bits_bits_addr),
.io_ptw_req_bits_bits_need_gpa (_frontend_io_ptw_req_bits_bits_need_gpa),
.io_ptw_resp_valid (_ptw_io_requestor_1_resp_valid), // @[tile.scala:237:20]
.io_ptw_resp_bits_ae_ptw (_ptw_io_requestor_1_resp_bits_ae_ptw), // @[tile.scala:237:20]
.io_ptw_resp_bits_ae_final (_ptw_io_requestor_1_resp_bits_ae_final), // @[tile.scala:237:20]
.io_ptw_resp_bits_pf (_ptw_io_requestor_1_resp_bits_pf), // @[tile.scala:237:20]
.io_ptw_resp_bits_gf (_ptw_io_requestor_1_resp_bits_gf), // @[tile.scala:237:20]
.io_ptw_resp_bits_hr (_ptw_io_requestor_1_resp_bits_hr), // @[tile.scala:237:20]
.io_ptw_resp_bits_hw (_ptw_io_requestor_1_resp_bits_hw), // @[tile.scala:237:20]
.io_ptw_resp_bits_hx (_ptw_io_requestor_1_resp_bits_hx), // @[tile.scala:237:20]
.io_ptw_resp_bits_pte_reserved_for_future (_ptw_io_requestor_1_resp_bits_pte_reserved_for_future), // @[tile.scala:237:20]
.io_ptw_resp_bits_pte_ppn (_ptw_io_requestor_1_resp_bits_pte_ppn), // @[tile.scala:237:20]
.io_ptw_resp_bits_pte_reserved_for_software (_ptw_io_requestor_1_resp_bits_pte_reserved_for_software), // @[tile.scala:237:20]
.io_ptw_resp_bits_pte_d (_ptw_io_requestor_1_resp_bits_pte_d), // @[tile.scala:237:20]
.io_ptw_resp_bits_pte_a (_ptw_io_requestor_1_resp_bits_pte_a), // @[tile.scala:237:20]
.io_ptw_resp_bits_pte_g (_ptw_io_requestor_1_resp_bits_pte_g), // @[tile.scala:237:20]
.io_ptw_resp_bits_pte_u (_ptw_io_requestor_1_resp_bits_pte_u), // @[tile.scala:237:20]
.io_ptw_resp_bits_pte_x (_ptw_io_requestor_1_resp_bits_pte_x), // @[tile.scala:237:20]
.io_ptw_resp_bits_pte_w (_ptw_io_requestor_1_resp_bits_pte_w), // @[tile.scala:237:20]
.io_ptw_resp_bits_pte_r (_ptw_io_requestor_1_resp_bits_pte_r), // @[tile.scala:237:20]
.io_ptw_resp_bits_pte_v (_ptw_io_requestor_1_resp_bits_pte_v), // @[tile.scala:237:20]
.io_ptw_resp_bits_level (_ptw_io_requestor_1_resp_bits_level), // @[tile.scala:237:20]
.io_ptw_resp_bits_homogeneous (_ptw_io_requestor_1_resp_bits_homogeneous), // @[tile.scala:237:20]
.io_ptw_resp_bits_gpa_valid (_ptw_io_requestor_1_resp_bits_gpa_valid), // @[tile.scala:237:20]
.io_ptw_resp_bits_gpa_bits (_ptw_io_requestor_1_resp_bits_gpa_bits), // @[tile.scala:237:20]
.io_ptw_resp_bits_gpa_is_pte (_ptw_io_requestor_1_resp_bits_gpa_is_pte), // @[tile.scala:237:20]
.io_ptw_ptbr_mode (_ptw_io_requestor_1_ptbr_mode), // @[tile.scala:237:20]
.io_ptw_ptbr_ppn (_ptw_io_requestor_1_ptbr_ppn), // @[tile.scala:237:20]
.io_ptw_status_debug (_ptw_io_requestor_1_status_debug), // @[tile.scala:237:20]
.io_ptw_status_cease (_ptw_io_requestor_1_status_cease), // @[tile.scala:237:20]
.io_ptw_status_wfi (_ptw_io_requestor_1_status_wfi), // @[tile.scala:237:20]
.io_ptw_status_dprv (_ptw_io_requestor_1_status_dprv), // @[tile.scala:237:20]
.io_ptw_status_dv (_ptw_io_requestor_1_status_dv), // @[tile.scala:237:20]
.io_ptw_status_prv (_ptw_io_requestor_1_status_prv), // @[tile.scala:237:20]
.io_ptw_status_v (_ptw_io_requestor_1_status_v), // @[tile.scala:237:20]
.io_ptw_status_sd (_ptw_io_requestor_1_status_sd), // @[tile.scala:237:20]
.io_ptw_status_mpv (_ptw_io_requestor_1_status_mpv), // @[tile.scala:237:20]
.io_ptw_status_gva (_ptw_io_requestor_1_status_gva), // @[tile.scala:237:20]
.io_ptw_status_tsr (_ptw_io_requestor_1_status_tsr), // @[tile.scala:237:20]
.io_ptw_status_tw (_ptw_io_requestor_1_status_tw), // @[tile.scala:237:20]
.io_ptw_status_tvm (_ptw_io_requestor_1_status_tvm), // @[tile.scala:237:20]
.io_ptw_status_mxr (_ptw_io_requestor_1_status_mxr), // @[tile.scala:237:20]
.io_ptw_status_sum (_ptw_io_requestor_1_status_sum), // @[tile.scala:237:20]
.io_ptw_status_mprv (_ptw_io_requestor_1_status_mprv), // @[tile.scala:237:20]
.io_ptw_status_fs (_ptw_io_requestor_1_status_fs), // @[tile.scala:237:20]
.io_ptw_status_mpp (_ptw_io_requestor_1_status_mpp), // @[tile.scala:237:20]
.io_ptw_status_spp (_ptw_io_requestor_1_status_spp), // @[tile.scala:237:20]
.io_ptw_status_mpie (_ptw_io_requestor_1_status_mpie), // @[tile.scala:237:20]
.io_ptw_status_spie (_ptw_io_requestor_1_status_spie), // @[tile.scala:237:20]
.io_ptw_status_mie (_ptw_io_requestor_1_status_mie), // @[tile.scala:237:20]
.io_ptw_status_sie (_ptw_io_requestor_1_status_sie), // @[tile.scala:237:20]
.io_ptw_pmp_0_cfg_l (_ptw_io_requestor_1_pmp_0_cfg_l), // @[tile.scala:237:20]
.io_ptw_pmp_0_cfg_a (_ptw_io_requestor_1_pmp_0_cfg_a), // @[tile.scala:237:20]
.io_ptw_pmp_0_cfg_x (_ptw_io_requestor_1_pmp_0_cfg_x), // @[tile.scala:237:20]
.io_ptw_pmp_0_cfg_w (_ptw_io_requestor_1_pmp_0_cfg_w), // @[tile.scala:237:20]
.io_ptw_pmp_0_cfg_r (_ptw_io_requestor_1_pmp_0_cfg_r), // @[tile.scala:237:20]
.io_ptw_pmp_0_addr (_ptw_io_requestor_1_pmp_0_addr), // @[tile.scala:237:20]
.io_ptw_pmp_0_mask (_ptw_io_requestor_1_pmp_0_mask), // @[tile.scala:237:20]
.io_ptw_pmp_1_cfg_l (_ptw_io_requestor_1_pmp_1_cfg_l), // @[tile.scala:237:20]
.io_ptw_pmp_1_cfg_a (_ptw_io_requestor_1_pmp_1_cfg_a), // @[tile.scala:237:20]
.io_ptw_pmp_1_cfg_x (_ptw_io_requestor_1_pmp_1_cfg_x), // @[tile.scala:237:20]
.io_ptw_pmp_1_cfg_w (_ptw_io_requestor_1_pmp_1_cfg_w), // @[tile.scala:237:20]
.io_ptw_pmp_1_cfg_r (_ptw_io_requestor_1_pmp_1_cfg_r), // @[tile.scala:237:20]
.io_ptw_pmp_1_addr (_ptw_io_requestor_1_pmp_1_addr), // @[tile.scala:237:20]
.io_ptw_pmp_1_mask (_ptw_io_requestor_1_pmp_1_mask), // @[tile.scala:237:20]
.io_ptw_pmp_2_cfg_l (_ptw_io_requestor_1_pmp_2_cfg_l), // @[tile.scala:237:20]
.io_ptw_pmp_2_cfg_a (_ptw_io_requestor_1_pmp_2_cfg_a), // @[tile.scala:237:20]
.io_ptw_pmp_2_cfg_x (_ptw_io_requestor_1_pmp_2_cfg_x), // @[tile.scala:237:20]
.io_ptw_pmp_2_cfg_w (_ptw_io_requestor_1_pmp_2_cfg_w), // @[tile.scala:237:20]
.io_ptw_pmp_2_cfg_r (_ptw_io_requestor_1_pmp_2_cfg_r), // @[tile.scala:237:20]
.io_ptw_pmp_2_addr (_ptw_io_requestor_1_pmp_2_addr), // @[tile.scala:237:20]
.io_ptw_pmp_2_mask (_ptw_io_requestor_1_pmp_2_mask), // @[tile.scala:237:20]
.io_ptw_pmp_3_cfg_l (_ptw_io_requestor_1_pmp_3_cfg_l), // @[tile.scala:237:20]
.io_ptw_pmp_3_cfg_a (_ptw_io_requestor_1_pmp_3_cfg_a), // @[tile.scala:237:20]
.io_ptw_pmp_3_cfg_x (_ptw_io_requestor_1_pmp_3_cfg_x), // @[tile.scala:237:20]
.io_ptw_pmp_3_cfg_w (_ptw_io_requestor_1_pmp_3_cfg_w), // @[tile.scala:237:20]
.io_ptw_pmp_3_cfg_r (_ptw_io_requestor_1_pmp_3_cfg_r), // @[tile.scala:237:20]
.io_ptw_pmp_3_addr (_ptw_io_requestor_1_pmp_3_addr), // @[tile.scala:237:20]
.io_ptw_pmp_3_mask (_ptw_io_requestor_1_pmp_3_mask), // @[tile.scala:237:20]
.io_ptw_pmp_4_cfg_l (_ptw_io_requestor_1_pmp_4_cfg_l), // @[tile.scala:237:20]
.io_ptw_pmp_4_cfg_a (_ptw_io_requestor_1_pmp_4_cfg_a), // @[tile.scala:237:20]
.io_ptw_pmp_4_cfg_x (_ptw_io_requestor_1_pmp_4_cfg_x), // @[tile.scala:237:20]
.io_ptw_pmp_4_cfg_w (_ptw_io_requestor_1_pmp_4_cfg_w), // @[tile.scala:237:20]
.io_ptw_pmp_4_cfg_r (_ptw_io_requestor_1_pmp_4_cfg_r), // @[tile.scala:237:20]
.io_ptw_pmp_4_addr (_ptw_io_requestor_1_pmp_4_addr), // @[tile.scala:237:20]
.io_ptw_pmp_4_mask (_ptw_io_requestor_1_pmp_4_mask), // @[tile.scala:237:20]
.io_ptw_pmp_5_cfg_l (_ptw_io_requestor_1_pmp_5_cfg_l), // @[tile.scala:237:20]
.io_ptw_pmp_5_cfg_a (_ptw_io_requestor_1_pmp_5_cfg_a), // @[tile.scala:237:20]
.io_ptw_pmp_5_cfg_x (_ptw_io_requestor_1_pmp_5_cfg_x), // @[tile.scala:237:20]
.io_ptw_pmp_5_cfg_w (_ptw_io_requestor_1_pmp_5_cfg_w), // @[tile.scala:237:20]
.io_ptw_pmp_5_cfg_r (_ptw_io_requestor_1_pmp_5_cfg_r), // @[tile.scala:237:20]
.io_ptw_pmp_5_addr (_ptw_io_requestor_1_pmp_5_addr), // @[tile.scala:237:20]
.io_ptw_pmp_5_mask (_ptw_io_requestor_1_pmp_5_mask), // @[tile.scala:237:20]
.io_ptw_pmp_6_cfg_l (_ptw_io_requestor_1_pmp_6_cfg_l), // @[tile.scala:237:20]
.io_ptw_pmp_6_cfg_a (_ptw_io_requestor_1_pmp_6_cfg_a), // @[tile.scala:237:20]
.io_ptw_pmp_6_cfg_x (_ptw_io_requestor_1_pmp_6_cfg_x), // @[tile.scala:237:20]
.io_ptw_pmp_6_cfg_w (_ptw_io_requestor_1_pmp_6_cfg_w), // @[tile.scala:237:20]
.io_ptw_pmp_6_cfg_r (_ptw_io_requestor_1_pmp_6_cfg_r), // @[tile.scala:237:20]
.io_ptw_pmp_6_addr (_ptw_io_requestor_1_pmp_6_addr), // @[tile.scala:237:20]
.io_ptw_pmp_6_mask (_ptw_io_requestor_1_pmp_6_mask), // @[tile.scala:237:20]
.io_ptw_pmp_7_cfg_l (_ptw_io_requestor_1_pmp_7_cfg_l), // @[tile.scala:237:20]
.io_ptw_pmp_7_cfg_a (_ptw_io_requestor_1_pmp_7_cfg_a), // @[tile.scala:237:20]
.io_ptw_pmp_7_cfg_x (_ptw_io_requestor_1_pmp_7_cfg_x), // @[tile.scala:237:20]
.io_ptw_pmp_7_cfg_w (_ptw_io_requestor_1_pmp_7_cfg_w), // @[tile.scala:237:20]
.io_ptw_pmp_7_cfg_r (_ptw_io_requestor_1_pmp_7_cfg_r), // @[tile.scala:237:20]
.io_ptw_pmp_7_addr (_ptw_io_requestor_1_pmp_7_addr), // @[tile.scala:237:20]
.io_ptw_pmp_7_mask (_ptw_io_requestor_1_pmp_7_mask) // @[tile.scala:237:20]
); // @[tile.scala:138:28]
BoomCore core ( // @[tile.scala:159:20]
.clock (clock),
.reset (reset),
.io_hartid (hartIdSinkNodeIn), // @[MixedNode.scala:551:17]
.io_interrupts_debug (intSinkNodeIn_0), // @[MixedNode.scala:551:17]
.io_interrupts_mtip (intSinkNodeIn_2), // @[MixedNode.scala:551:17]
.io_interrupts_msip (intSinkNodeIn_1), // @[MixedNode.scala:551:17]
.io_interrupts_meip (intSinkNodeIn_3), // @[MixedNode.scala:551:17]
.io_interrupts_seip (intSinkNodeIn_4), // @[MixedNode.scala:551:17]
.io_ifu_fetchpacket_ready (_core_io_ifu_fetchpacket_ready),
.io_ifu_fetchpacket_valid (_frontend_io_cpu_fetchpacket_valid), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_0_valid (_frontend_io_cpu_fetchpacket_bits_uops_0_valid), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_0_bits_inst (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_inst), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_0_bits_debug_inst (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_debug_inst), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_0_bits_is_rvc (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_is_rvc), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_0_bits_debug_pc (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_debug_pc), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_0_bits_is_sfb (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_is_sfb), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_0_bits_ftq_idx (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_ftq_idx), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_0_bits_edge_inst (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_edge_inst), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_0_bits_pc_lob (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_pc_lob), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_0_bits_taken (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_taken), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_0_bits_xcpt_pf_if (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_xcpt_pf_if), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_0_bits_xcpt_ae_if (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_xcpt_ae_if), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_0_bits_bp_debug_if (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_bp_debug_if), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_0_bits_bp_xcpt_if (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_bp_xcpt_if), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_0_bits_debug_fsrc (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_debug_fsrc), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_1_valid (_frontend_io_cpu_fetchpacket_bits_uops_1_valid), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_1_bits_inst (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_inst), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_1_bits_debug_inst (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_debug_inst), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_1_bits_is_rvc (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_is_rvc), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_1_bits_debug_pc (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_debug_pc), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_1_bits_is_sfb (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_is_sfb), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_1_bits_ftq_idx (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_ftq_idx), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_1_bits_edge_inst (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_edge_inst), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_1_bits_pc_lob (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_pc_lob), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_1_bits_taken (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_taken), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_1_bits_xcpt_pf_if (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_xcpt_pf_if), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_1_bits_xcpt_ae_if (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_xcpt_ae_if), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_1_bits_bp_debug_if (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_bp_debug_if), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_1_bits_bp_xcpt_if (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_bp_xcpt_if), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_1_bits_debug_fsrc (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_debug_fsrc), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_2_valid (_frontend_io_cpu_fetchpacket_bits_uops_2_valid), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_2_bits_inst (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_inst), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_2_bits_debug_inst (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_debug_inst), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_2_bits_is_rvc (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_is_rvc), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_2_bits_debug_pc (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_debug_pc), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_2_bits_is_sfb (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_is_sfb), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_2_bits_ftq_idx (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_ftq_idx), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_2_bits_edge_inst (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_edge_inst), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_2_bits_pc_lob (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_pc_lob), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_2_bits_taken (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_taken), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_2_bits_xcpt_pf_if (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_xcpt_pf_if), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_2_bits_xcpt_ae_if (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_xcpt_ae_if), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_2_bits_bp_debug_if (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_bp_debug_if), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_2_bits_bp_xcpt_if (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_bp_xcpt_if), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_2_bits_debug_fsrc (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_debug_fsrc), // @[tile.scala:138:28]
.io_ifu_get_pc_0_ftq_idx (_core_io_ifu_get_pc_0_ftq_idx),
.io_ifu_get_pc_0_entry_cfi_idx_valid (_frontend_io_cpu_get_pc_0_entry_cfi_idx_valid), // @[tile.scala:138:28]
.io_ifu_get_pc_0_entry_cfi_idx_bits (_frontend_io_cpu_get_pc_0_entry_cfi_idx_bits), // @[tile.scala:138:28]
.io_ifu_get_pc_0_entry_cfi_taken (_frontend_io_cpu_get_pc_0_entry_cfi_taken), // @[tile.scala:138:28]
.io_ifu_get_pc_0_entry_cfi_mispredicted (_frontend_io_cpu_get_pc_0_entry_cfi_mispredicted), // @[tile.scala:138:28]
.io_ifu_get_pc_0_entry_cfi_type (_frontend_io_cpu_get_pc_0_entry_cfi_type), // @[tile.scala:138:28]
.io_ifu_get_pc_0_entry_br_mask (_frontend_io_cpu_get_pc_0_entry_br_mask), // @[tile.scala:138:28]
.io_ifu_get_pc_0_entry_cfi_is_call (_frontend_io_cpu_get_pc_0_entry_cfi_is_call), // @[tile.scala:138:28]
.io_ifu_get_pc_0_entry_cfi_is_ret (_frontend_io_cpu_get_pc_0_entry_cfi_is_ret), // @[tile.scala:138:28]
.io_ifu_get_pc_0_entry_cfi_npc_plus4 (_frontend_io_cpu_get_pc_0_entry_cfi_npc_plus4), // @[tile.scala:138:28]
.io_ifu_get_pc_0_entry_ras_top (_frontend_io_cpu_get_pc_0_entry_ras_top), // @[tile.scala:138:28]
.io_ifu_get_pc_0_entry_ras_idx (_frontend_io_cpu_get_pc_0_entry_ras_idx), // @[tile.scala:138:28]
.io_ifu_get_pc_0_entry_start_bank (_frontend_io_cpu_get_pc_0_entry_start_bank), // @[tile.scala:138:28]
.io_ifu_get_pc_0_pc (_frontend_io_cpu_get_pc_0_pc), // @[tile.scala:138:28]
.io_ifu_get_pc_0_com_pc (_frontend_io_cpu_get_pc_0_com_pc), // @[tile.scala:138:28]
.io_ifu_get_pc_0_next_val (_frontend_io_cpu_get_pc_0_next_val), // @[tile.scala:138:28]
.io_ifu_get_pc_0_next_pc (_frontend_io_cpu_get_pc_0_next_pc), // @[tile.scala:138:28]
.io_ifu_get_pc_1_ftq_idx (_core_io_ifu_get_pc_1_ftq_idx),
.io_ifu_get_pc_1_entry_cfi_idx_valid (_frontend_io_cpu_get_pc_1_entry_cfi_idx_valid), // @[tile.scala:138:28]
.io_ifu_get_pc_1_entry_cfi_idx_bits (_frontend_io_cpu_get_pc_1_entry_cfi_idx_bits), // @[tile.scala:138:28]
.io_ifu_get_pc_1_entry_cfi_taken (_frontend_io_cpu_get_pc_1_entry_cfi_taken), // @[tile.scala:138:28]
.io_ifu_get_pc_1_entry_cfi_mispredicted (_frontend_io_cpu_get_pc_1_entry_cfi_mispredicted), // @[tile.scala:138:28]
.io_ifu_get_pc_1_entry_cfi_type (_frontend_io_cpu_get_pc_1_entry_cfi_type), // @[tile.scala:138:28]
.io_ifu_get_pc_1_entry_br_mask (_frontend_io_cpu_get_pc_1_entry_br_mask), // @[tile.scala:138:28]
.io_ifu_get_pc_1_entry_cfi_is_call (_frontend_io_cpu_get_pc_1_entry_cfi_is_call), // @[tile.scala:138:28]
.io_ifu_get_pc_1_entry_cfi_is_ret (_frontend_io_cpu_get_pc_1_entry_cfi_is_ret), // @[tile.scala:138:28]
.io_ifu_get_pc_1_entry_cfi_npc_plus4 (_frontend_io_cpu_get_pc_1_entry_cfi_npc_plus4), // @[tile.scala:138:28]
.io_ifu_get_pc_1_entry_ras_top (_frontend_io_cpu_get_pc_1_entry_ras_top), // @[tile.scala:138:28]
.io_ifu_get_pc_1_entry_ras_idx (_frontend_io_cpu_get_pc_1_entry_ras_idx), // @[tile.scala:138:28]
.io_ifu_get_pc_1_entry_start_bank (_frontend_io_cpu_get_pc_1_entry_start_bank), // @[tile.scala:138:28]
.io_ifu_get_pc_1_ghist_old_history (_frontend_io_cpu_get_pc_1_ghist_old_history), // @[tile.scala:138:28]
.io_ifu_get_pc_1_ghist_current_saw_branch_not_taken (_frontend_io_cpu_get_pc_1_ghist_current_saw_branch_not_taken), // @[tile.scala:138:28]
.io_ifu_get_pc_1_ghist_new_saw_branch_not_taken (_frontend_io_cpu_get_pc_1_ghist_new_saw_branch_not_taken), // @[tile.scala:138:28]
.io_ifu_get_pc_1_ghist_new_saw_branch_taken (_frontend_io_cpu_get_pc_1_ghist_new_saw_branch_taken), // @[tile.scala:138:28]
.io_ifu_get_pc_1_ghist_ras_idx (_frontend_io_cpu_get_pc_1_ghist_ras_idx), // @[tile.scala:138:28]
.io_ifu_get_pc_1_pc (_frontend_io_cpu_get_pc_1_pc), // @[tile.scala:138:28]
.io_ifu_get_pc_1_com_pc (_frontend_io_cpu_get_pc_1_com_pc), // @[tile.scala:138:28]
.io_ifu_get_pc_1_next_val (_frontend_io_cpu_get_pc_1_next_val), // @[tile.scala:138:28]
.io_ifu_get_pc_1_next_pc (_frontend_io_cpu_get_pc_1_next_pc), // @[tile.scala:138:28]
.io_ifu_debug_fetch_pc_0 (_frontend_io_cpu_debug_fetch_pc_0), // @[tile.scala:138:28]
.io_ifu_debug_fetch_pc_1 (_frontend_io_cpu_debug_fetch_pc_1), // @[tile.scala:138:28]
.io_ifu_debug_fetch_pc_2 (_frontend_io_cpu_debug_fetch_pc_2), // @[tile.scala:138:28]
.io_ifu_status_debug (_core_io_ifu_status_debug),
.io_ifu_status_cease (_core_io_ifu_status_cease),
.io_ifu_status_wfi (_core_io_ifu_status_wfi),
.io_ifu_status_dprv (_core_io_ifu_status_dprv),
.io_ifu_status_dv (_core_io_ifu_status_dv),
.io_ifu_status_prv (_core_io_ifu_status_prv),
.io_ifu_status_v (_core_io_ifu_status_v),
.io_ifu_status_sd (_core_io_ifu_status_sd),
.io_ifu_status_mpv (_core_io_ifu_status_mpv),
.io_ifu_status_gva (_core_io_ifu_status_gva),
.io_ifu_status_tsr (_core_io_ifu_status_tsr),
.io_ifu_status_tw (_core_io_ifu_status_tw),
.io_ifu_status_tvm (_core_io_ifu_status_tvm),
.io_ifu_status_mxr (_core_io_ifu_status_mxr),
.io_ifu_status_sum (_core_io_ifu_status_sum),
.io_ifu_status_mprv (_core_io_ifu_status_mprv),
.io_ifu_status_fs (_core_io_ifu_status_fs),
.io_ifu_status_mpp (_core_io_ifu_status_mpp),
.io_ifu_status_spp (_core_io_ifu_status_spp),
.io_ifu_status_mpie (_core_io_ifu_status_mpie),
.io_ifu_status_spie (_core_io_ifu_status_spie),
.io_ifu_status_mie (_core_io_ifu_status_mie),
.io_ifu_status_sie (_core_io_ifu_status_sie),
.io_ifu_sfence_valid (_core_io_ifu_sfence_valid),
.io_ifu_sfence_bits_rs1 (_core_io_ifu_sfence_bits_rs1),
.io_ifu_sfence_bits_rs2 (_core_io_ifu_sfence_bits_rs2),
.io_ifu_sfence_bits_addr (_core_io_ifu_sfence_bits_addr),
.io_ifu_sfence_bits_asid (_core_io_ifu_sfence_bits_asid),
.io_ifu_brupdate_b1_resolve_mask (_core_io_ifu_brupdate_b1_resolve_mask),
.io_ifu_brupdate_b1_mispredict_mask (_core_io_ifu_brupdate_b1_mispredict_mask),
.io_ifu_brupdate_b2_uop_uopc (_core_io_ifu_brupdate_b2_uop_uopc),
.io_ifu_brupdate_b2_uop_inst (_core_io_ifu_brupdate_b2_uop_inst),
.io_ifu_brupdate_b2_uop_debug_inst (_core_io_ifu_brupdate_b2_uop_debug_inst),
.io_ifu_brupdate_b2_uop_is_rvc (_core_io_ifu_brupdate_b2_uop_is_rvc),
.io_ifu_brupdate_b2_uop_debug_pc (_core_io_ifu_brupdate_b2_uop_debug_pc),
.io_ifu_brupdate_b2_uop_iq_type (_core_io_ifu_brupdate_b2_uop_iq_type),
.io_ifu_brupdate_b2_uop_fu_code (_core_io_ifu_brupdate_b2_uop_fu_code),
.io_ifu_brupdate_b2_uop_ctrl_br_type (_core_io_ifu_brupdate_b2_uop_ctrl_br_type),
.io_ifu_brupdate_b2_uop_ctrl_op1_sel (_core_io_ifu_brupdate_b2_uop_ctrl_op1_sel),
.io_ifu_brupdate_b2_uop_ctrl_op2_sel (_core_io_ifu_brupdate_b2_uop_ctrl_op2_sel),
.io_ifu_brupdate_b2_uop_ctrl_imm_sel (_core_io_ifu_brupdate_b2_uop_ctrl_imm_sel),
.io_ifu_brupdate_b2_uop_ctrl_op_fcn (_core_io_ifu_brupdate_b2_uop_ctrl_op_fcn),
.io_ifu_brupdate_b2_uop_ctrl_fcn_dw (_core_io_ifu_brupdate_b2_uop_ctrl_fcn_dw),
.io_ifu_brupdate_b2_uop_ctrl_csr_cmd (_core_io_ifu_brupdate_b2_uop_ctrl_csr_cmd),
.io_ifu_brupdate_b2_uop_ctrl_is_load (_core_io_ifu_brupdate_b2_uop_ctrl_is_load),
.io_ifu_brupdate_b2_uop_ctrl_is_sta (_core_io_ifu_brupdate_b2_uop_ctrl_is_sta),
.io_ifu_brupdate_b2_uop_ctrl_is_std (_core_io_ifu_brupdate_b2_uop_ctrl_is_std),
.io_ifu_brupdate_b2_uop_iw_state (_core_io_ifu_brupdate_b2_uop_iw_state),
.io_ifu_brupdate_b2_uop_iw_p1_poisoned (_core_io_ifu_brupdate_b2_uop_iw_p1_poisoned),
.io_ifu_brupdate_b2_uop_iw_p2_poisoned (_core_io_ifu_brupdate_b2_uop_iw_p2_poisoned),
.io_ifu_brupdate_b2_uop_is_br (_core_io_ifu_brupdate_b2_uop_is_br),
.io_ifu_brupdate_b2_uop_is_jalr (_core_io_ifu_brupdate_b2_uop_is_jalr),
.io_ifu_brupdate_b2_uop_is_jal (_core_io_ifu_brupdate_b2_uop_is_jal),
.io_ifu_brupdate_b2_uop_is_sfb (_core_io_ifu_brupdate_b2_uop_is_sfb),
.io_ifu_brupdate_b2_uop_br_mask (_core_io_ifu_brupdate_b2_uop_br_mask),
.io_ifu_brupdate_b2_uop_br_tag (_core_io_ifu_brupdate_b2_uop_br_tag),
.io_ifu_brupdate_b2_uop_ftq_idx (_core_io_ifu_brupdate_b2_uop_ftq_idx),
.io_ifu_brupdate_b2_uop_edge_inst (_core_io_ifu_brupdate_b2_uop_edge_inst),
.io_ifu_brupdate_b2_uop_pc_lob (_core_io_ifu_brupdate_b2_uop_pc_lob),
.io_ifu_brupdate_b2_uop_taken (_core_io_ifu_brupdate_b2_uop_taken),
.io_ifu_brupdate_b2_uop_imm_packed (_core_io_ifu_brupdate_b2_uop_imm_packed),
.io_ifu_brupdate_b2_uop_csr_addr (_core_io_ifu_brupdate_b2_uop_csr_addr),
.io_ifu_brupdate_b2_uop_rob_idx (_core_io_ifu_brupdate_b2_uop_rob_idx),
.io_ifu_brupdate_b2_uop_ldq_idx (_core_io_ifu_brupdate_b2_uop_ldq_idx),
.io_ifu_brupdate_b2_uop_stq_idx (_core_io_ifu_brupdate_b2_uop_stq_idx),
.io_ifu_brupdate_b2_uop_rxq_idx (_core_io_ifu_brupdate_b2_uop_rxq_idx),
.io_ifu_brupdate_b2_uop_pdst (_core_io_ifu_brupdate_b2_uop_pdst),
.io_ifu_brupdate_b2_uop_prs1 (_core_io_ifu_brupdate_b2_uop_prs1),
.io_ifu_brupdate_b2_uop_prs2 (_core_io_ifu_brupdate_b2_uop_prs2),
.io_ifu_brupdate_b2_uop_prs3 (_core_io_ifu_brupdate_b2_uop_prs3),
.io_ifu_brupdate_b2_uop_ppred (_core_io_ifu_brupdate_b2_uop_ppred),
.io_ifu_brupdate_b2_uop_prs1_busy (_core_io_ifu_brupdate_b2_uop_prs1_busy),
.io_ifu_brupdate_b2_uop_prs2_busy (_core_io_ifu_brupdate_b2_uop_prs2_busy),
.io_ifu_brupdate_b2_uop_prs3_busy (_core_io_ifu_brupdate_b2_uop_prs3_busy),
.io_ifu_brupdate_b2_uop_ppred_busy (_core_io_ifu_brupdate_b2_uop_ppred_busy),
.io_ifu_brupdate_b2_uop_stale_pdst (_core_io_ifu_brupdate_b2_uop_stale_pdst),
.io_ifu_brupdate_b2_uop_exception (_core_io_ifu_brupdate_b2_uop_exception),
.io_ifu_brupdate_b2_uop_exc_cause (_core_io_ifu_brupdate_b2_uop_exc_cause),
.io_ifu_brupdate_b2_uop_bypassable (_core_io_ifu_brupdate_b2_uop_bypassable),
.io_ifu_brupdate_b2_uop_mem_cmd (_core_io_ifu_brupdate_b2_uop_mem_cmd),
.io_ifu_brupdate_b2_uop_mem_size (_core_io_ifu_brupdate_b2_uop_mem_size),
.io_ifu_brupdate_b2_uop_mem_signed (_core_io_ifu_brupdate_b2_uop_mem_signed),
.io_ifu_brupdate_b2_uop_is_fence (_core_io_ifu_brupdate_b2_uop_is_fence),
.io_ifu_brupdate_b2_uop_is_fencei (_core_io_ifu_brupdate_b2_uop_is_fencei),
.io_ifu_brupdate_b2_uop_is_amo (_core_io_ifu_brupdate_b2_uop_is_amo),
.io_ifu_brupdate_b2_uop_uses_ldq (_core_io_ifu_brupdate_b2_uop_uses_ldq),
.io_ifu_brupdate_b2_uop_uses_stq (_core_io_ifu_brupdate_b2_uop_uses_stq),
.io_ifu_brupdate_b2_uop_is_sys_pc2epc (_core_io_ifu_brupdate_b2_uop_is_sys_pc2epc),
.io_ifu_brupdate_b2_uop_is_unique (_core_io_ifu_brupdate_b2_uop_is_unique),
.io_ifu_brupdate_b2_uop_flush_on_commit (_core_io_ifu_brupdate_b2_uop_flush_on_commit),
.io_ifu_brupdate_b2_uop_ldst_is_rs1 (_core_io_ifu_brupdate_b2_uop_ldst_is_rs1),
.io_ifu_brupdate_b2_uop_ldst (_core_io_ifu_brupdate_b2_uop_ldst),
.io_ifu_brupdate_b2_uop_lrs1 (_core_io_ifu_brupdate_b2_uop_lrs1),
.io_ifu_brupdate_b2_uop_lrs2 (_core_io_ifu_brupdate_b2_uop_lrs2),
.io_ifu_brupdate_b2_uop_lrs3 (_core_io_ifu_brupdate_b2_uop_lrs3),
.io_ifu_brupdate_b2_uop_ldst_val (_core_io_ifu_brupdate_b2_uop_ldst_val),
.io_ifu_brupdate_b2_uop_dst_rtype (_core_io_ifu_brupdate_b2_uop_dst_rtype),
.io_ifu_brupdate_b2_uop_lrs1_rtype (_core_io_ifu_brupdate_b2_uop_lrs1_rtype),
.io_ifu_brupdate_b2_uop_lrs2_rtype (_core_io_ifu_brupdate_b2_uop_lrs2_rtype),
.io_ifu_brupdate_b2_uop_frs3_en (_core_io_ifu_brupdate_b2_uop_frs3_en),
.io_ifu_brupdate_b2_uop_fp_val (_core_io_ifu_brupdate_b2_uop_fp_val),
.io_ifu_brupdate_b2_uop_fp_single (_core_io_ifu_brupdate_b2_uop_fp_single),
.io_ifu_brupdate_b2_uop_xcpt_pf_if (_core_io_ifu_brupdate_b2_uop_xcpt_pf_if),
.io_ifu_brupdate_b2_uop_xcpt_ae_if (_core_io_ifu_brupdate_b2_uop_xcpt_ae_if),
.io_ifu_brupdate_b2_uop_xcpt_ma_if (_core_io_ifu_brupdate_b2_uop_xcpt_ma_if),
.io_ifu_brupdate_b2_uop_bp_debug_if (_core_io_ifu_brupdate_b2_uop_bp_debug_if),
.io_ifu_brupdate_b2_uop_bp_xcpt_if (_core_io_ifu_brupdate_b2_uop_bp_xcpt_if),
.io_ifu_brupdate_b2_uop_debug_fsrc (_core_io_ifu_brupdate_b2_uop_debug_fsrc),
.io_ifu_brupdate_b2_uop_debug_tsrc (_core_io_ifu_brupdate_b2_uop_debug_tsrc),
.io_ifu_brupdate_b2_valid (_core_io_ifu_brupdate_b2_valid),
.io_ifu_brupdate_b2_mispredict (_core_io_ifu_brupdate_b2_mispredict),
.io_ifu_brupdate_b2_taken (_core_io_ifu_brupdate_b2_taken),
.io_ifu_brupdate_b2_cfi_type (_core_io_ifu_brupdate_b2_cfi_type),
.io_ifu_brupdate_b2_pc_sel (_core_io_ifu_brupdate_b2_pc_sel),
.io_ifu_brupdate_b2_jalr_target (_core_io_ifu_brupdate_b2_jalr_target),
.io_ifu_brupdate_b2_target_offset (_core_io_ifu_brupdate_b2_target_offset),
.io_ifu_redirect_flush (_core_io_ifu_redirect_flush),
.io_ifu_redirect_val (_core_io_ifu_redirect_val),
.io_ifu_redirect_pc (_core_io_ifu_redirect_pc),
.io_ifu_redirect_ftq_idx (_core_io_ifu_redirect_ftq_idx),
.io_ifu_redirect_ghist_old_history (_core_io_ifu_redirect_ghist_old_history),
.io_ifu_redirect_ghist_current_saw_branch_not_taken (_core_io_ifu_redirect_ghist_current_saw_branch_not_taken),
.io_ifu_redirect_ghist_new_saw_branch_not_taken (_core_io_ifu_redirect_ghist_new_saw_branch_not_taken),
.io_ifu_redirect_ghist_new_saw_branch_taken (_core_io_ifu_redirect_ghist_new_saw_branch_taken),
.io_ifu_redirect_ghist_ras_idx (_core_io_ifu_redirect_ghist_ras_idx),
.io_ifu_commit_valid (_core_io_ifu_commit_valid),
.io_ifu_commit_bits (_core_io_ifu_commit_bits),
.io_ifu_flush_icache (_core_io_ifu_flush_icache),
.io_ifu_perf_acquire (_frontend_io_cpu_perf_acquire), // @[tile.scala:138:28]
.io_ifu_perf_tlbMiss (_frontend_io_cpu_perf_tlbMiss), // @[tile.scala:138:28]
.io_ptw_ptbr_mode (_core_io_ptw_ptbr_mode),
.io_ptw_ptbr_ppn (_core_io_ptw_ptbr_ppn),
.io_ptw_sfence_valid (_core_io_ptw_sfence_valid),
.io_ptw_sfence_bits_rs1 (_core_io_ptw_sfence_bits_rs1),
.io_ptw_sfence_bits_rs2 (_core_io_ptw_sfence_bits_rs2),
.io_ptw_sfence_bits_addr (_core_io_ptw_sfence_bits_addr),
.io_ptw_sfence_bits_asid (_core_io_ptw_sfence_bits_asid),
.io_ptw_status_debug (_core_io_ptw_status_debug),
.io_ptw_status_cease (_core_io_ptw_status_cease),
.io_ptw_status_wfi (_core_io_ptw_status_wfi),
.io_ptw_status_dprv (_core_io_ptw_status_dprv),
.io_ptw_status_dv (_core_io_ptw_status_dv),
.io_ptw_status_prv (_core_io_ptw_status_prv),
.io_ptw_status_v (_core_io_ptw_status_v),
.io_ptw_status_sd (_core_io_ptw_status_sd),
.io_ptw_status_mpv (_core_io_ptw_status_mpv),
.io_ptw_status_gva (_core_io_ptw_status_gva),
.io_ptw_status_tsr (_core_io_ptw_status_tsr),
.io_ptw_status_tw (_core_io_ptw_status_tw),
.io_ptw_status_tvm (_core_io_ptw_status_tvm),
.io_ptw_status_mxr (_core_io_ptw_status_mxr),
.io_ptw_status_sum (_core_io_ptw_status_sum),
.io_ptw_status_mprv (_core_io_ptw_status_mprv),
.io_ptw_status_fs (_core_io_ptw_status_fs),
.io_ptw_status_mpp (_core_io_ptw_status_mpp),
.io_ptw_status_spp (_core_io_ptw_status_spp),
.io_ptw_status_mpie (_core_io_ptw_status_mpie),
.io_ptw_status_spie (_core_io_ptw_status_spie),
.io_ptw_status_mie (_core_io_ptw_status_mie),
.io_ptw_status_sie (_core_io_ptw_status_sie),
.io_ptw_pmp_0_cfg_l (_core_io_ptw_pmp_0_cfg_l),
.io_ptw_pmp_0_cfg_a (_core_io_ptw_pmp_0_cfg_a),
.io_ptw_pmp_0_cfg_x (_core_io_ptw_pmp_0_cfg_x),
.io_ptw_pmp_0_cfg_w (_core_io_ptw_pmp_0_cfg_w),
.io_ptw_pmp_0_cfg_r (_core_io_ptw_pmp_0_cfg_r),
.io_ptw_pmp_0_addr (_core_io_ptw_pmp_0_addr),
.io_ptw_pmp_0_mask (_core_io_ptw_pmp_0_mask),
.io_ptw_pmp_1_cfg_l (_core_io_ptw_pmp_1_cfg_l),
.io_ptw_pmp_1_cfg_a (_core_io_ptw_pmp_1_cfg_a),
.io_ptw_pmp_1_cfg_x (_core_io_ptw_pmp_1_cfg_x),
.io_ptw_pmp_1_cfg_w (_core_io_ptw_pmp_1_cfg_w),
.io_ptw_pmp_1_cfg_r (_core_io_ptw_pmp_1_cfg_r),
.io_ptw_pmp_1_addr (_core_io_ptw_pmp_1_addr),
.io_ptw_pmp_1_mask (_core_io_ptw_pmp_1_mask),
.io_ptw_pmp_2_cfg_l (_core_io_ptw_pmp_2_cfg_l),
.io_ptw_pmp_2_cfg_a (_core_io_ptw_pmp_2_cfg_a),
.io_ptw_pmp_2_cfg_x (_core_io_ptw_pmp_2_cfg_x),
.io_ptw_pmp_2_cfg_w (_core_io_ptw_pmp_2_cfg_w),
.io_ptw_pmp_2_cfg_r (_core_io_ptw_pmp_2_cfg_r),
.io_ptw_pmp_2_addr (_core_io_ptw_pmp_2_addr),
.io_ptw_pmp_2_mask (_core_io_ptw_pmp_2_mask),
.io_ptw_pmp_3_cfg_l (_core_io_ptw_pmp_3_cfg_l),
.io_ptw_pmp_3_cfg_a (_core_io_ptw_pmp_3_cfg_a),
.io_ptw_pmp_3_cfg_x (_core_io_ptw_pmp_3_cfg_x),
.io_ptw_pmp_3_cfg_w (_core_io_ptw_pmp_3_cfg_w),
.io_ptw_pmp_3_cfg_r (_core_io_ptw_pmp_3_cfg_r),
.io_ptw_pmp_3_addr (_core_io_ptw_pmp_3_addr),
.io_ptw_pmp_3_mask (_core_io_ptw_pmp_3_mask),
.io_ptw_pmp_4_cfg_l (_core_io_ptw_pmp_4_cfg_l),
.io_ptw_pmp_4_cfg_a (_core_io_ptw_pmp_4_cfg_a),
.io_ptw_pmp_4_cfg_x (_core_io_ptw_pmp_4_cfg_x),
.io_ptw_pmp_4_cfg_w (_core_io_ptw_pmp_4_cfg_w),
.io_ptw_pmp_4_cfg_r (_core_io_ptw_pmp_4_cfg_r),
.io_ptw_pmp_4_addr (_core_io_ptw_pmp_4_addr),
.io_ptw_pmp_4_mask (_core_io_ptw_pmp_4_mask),
.io_ptw_pmp_5_cfg_l (_core_io_ptw_pmp_5_cfg_l),
.io_ptw_pmp_5_cfg_a (_core_io_ptw_pmp_5_cfg_a),
.io_ptw_pmp_5_cfg_x (_core_io_ptw_pmp_5_cfg_x),
.io_ptw_pmp_5_cfg_w (_core_io_ptw_pmp_5_cfg_w),
.io_ptw_pmp_5_cfg_r (_core_io_ptw_pmp_5_cfg_r),
.io_ptw_pmp_5_addr (_core_io_ptw_pmp_5_addr),
.io_ptw_pmp_5_mask (_core_io_ptw_pmp_5_mask),
.io_ptw_pmp_6_cfg_l (_core_io_ptw_pmp_6_cfg_l),
.io_ptw_pmp_6_cfg_a (_core_io_ptw_pmp_6_cfg_a),
.io_ptw_pmp_6_cfg_x (_core_io_ptw_pmp_6_cfg_x),
.io_ptw_pmp_6_cfg_w (_core_io_ptw_pmp_6_cfg_w),
.io_ptw_pmp_6_cfg_r (_core_io_ptw_pmp_6_cfg_r),
.io_ptw_pmp_6_addr (_core_io_ptw_pmp_6_addr),
.io_ptw_pmp_6_mask (_core_io_ptw_pmp_6_mask),
.io_ptw_pmp_7_cfg_l (_core_io_ptw_pmp_7_cfg_l),
.io_ptw_pmp_7_cfg_a (_core_io_ptw_pmp_7_cfg_a),
.io_ptw_pmp_7_cfg_x (_core_io_ptw_pmp_7_cfg_x),
.io_ptw_pmp_7_cfg_w (_core_io_ptw_pmp_7_cfg_w),
.io_ptw_pmp_7_cfg_r (_core_io_ptw_pmp_7_cfg_r),
.io_ptw_pmp_7_addr (_core_io_ptw_pmp_7_addr),
.io_ptw_pmp_7_mask (_core_io_ptw_pmp_7_mask),
.io_ptw_perf_l2miss (_ptw_io_dpath_perf_l2miss), // @[tile.scala:237:20]
.io_ptw_perf_l2hit (_ptw_io_dpath_perf_l2hit), // @[tile.scala:237:20]
.io_ptw_perf_pte_miss (_ptw_io_dpath_perf_pte_miss), // @[tile.scala:237:20]
.io_ptw_perf_pte_hit (_ptw_io_dpath_perf_pte_hit), // @[tile.scala:237:20]
.io_ptw_clock_enabled (_ptw_io_dpath_clock_enabled), // @[tile.scala:237:20]
.io_lsu_exe_0_req_valid (_core_io_lsu_exe_0_req_valid),
.io_lsu_exe_0_req_bits_uop_uopc (_core_io_lsu_exe_0_req_bits_uop_uopc),
.io_lsu_exe_0_req_bits_uop_inst (_core_io_lsu_exe_0_req_bits_uop_inst),
.io_lsu_exe_0_req_bits_uop_debug_inst (_core_io_lsu_exe_0_req_bits_uop_debug_inst),
.io_lsu_exe_0_req_bits_uop_is_rvc (_core_io_lsu_exe_0_req_bits_uop_is_rvc),
.io_lsu_exe_0_req_bits_uop_debug_pc (_core_io_lsu_exe_0_req_bits_uop_debug_pc),
.io_lsu_exe_0_req_bits_uop_iq_type (_core_io_lsu_exe_0_req_bits_uop_iq_type),
.io_lsu_exe_0_req_bits_uop_fu_code (_core_io_lsu_exe_0_req_bits_uop_fu_code),
.io_lsu_exe_0_req_bits_uop_ctrl_br_type (_core_io_lsu_exe_0_req_bits_uop_ctrl_br_type),
.io_lsu_exe_0_req_bits_uop_ctrl_op1_sel (_core_io_lsu_exe_0_req_bits_uop_ctrl_op1_sel),
.io_lsu_exe_0_req_bits_uop_ctrl_op2_sel (_core_io_lsu_exe_0_req_bits_uop_ctrl_op2_sel),
.io_lsu_exe_0_req_bits_uop_ctrl_imm_sel (_core_io_lsu_exe_0_req_bits_uop_ctrl_imm_sel),
.io_lsu_exe_0_req_bits_uop_ctrl_op_fcn (_core_io_lsu_exe_0_req_bits_uop_ctrl_op_fcn),
.io_lsu_exe_0_req_bits_uop_ctrl_fcn_dw (_core_io_lsu_exe_0_req_bits_uop_ctrl_fcn_dw),
.io_lsu_exe_0_req_bits_uop_ctrl_csr_cmd (_core_io_lsu_exe_0_req_bits_uop_ctrl_csr_cmd),
.io_lsu_exe_0_req_bits_uop_ctrl_is_load (_core_io_lsu_exe_0_req_bits_uop_ctrl_is_load),
.io_lsu_exe_0_req_bits_uop_ctrl_is_sta (_core_io_lsu_exe_0_req_bits_uop_ctrl_is_sta),
.io_lsu_exe_0_req_bits_uop_ctrl_is_std (_core_io_lsu_exe_0_req_bits_uop_ctrl_is_std),
.io_lsu_exe_0_req_bits_uop_iw_state (_core_io_lsu_exe_0_req_bits_uop_iw_state),
.io_lsu_exe_0_req_bits_uop_iw_p1_poisoned (_core_io_lsu_exe_0_req_bits_uop_iw_p1_poisoned),
.io_lsu_exe_0_req_bits_uop_iw_p2_poisoned (_core_io_lsu_exe_0_req_bits_uop_iw_p2_poisoned),
.io_lsu_exe_0_req_bits_uop_is_br (_core_io_lsu_exe_0_req_bits_uop_is_br),
.io_lsu_exe_0_req_bits_uop_is_jalr (_core_io_lsu_exe_0_req_bits_uop_is_jalr),
.io_lsu_exe_0_req_bits_uop_is_jal (_core_io_lsu_exe_0_req_bits_uop_is_jal),
.io_lsu_exe_0_req_bits_uop_is_sfb (_core_io_lsu_exe_0_req_bits_uop_is_sfb),
.io_lsu_exe_0_req_bits_uop_br_mask (_core_io_lsu_exe_0_req_bits_uop_br_mask),
.io_lsu_exe_0_req_bits_uop_br_tag (_core_io_lsu_exe_0_req_bits_uop_br_tag),
.io_lsu_exe_0_req_bits_uop_ftq_idx (_core_io_lsu_exe_0_req_bits_uop_ftq_idx),
.io_lsu_exe_0_req_bits_uop_edge_inst (_core_io_lsu_exe_0_req_bits_uop_edge_inst),
.io_lsu_exe_0_req_bits_uop_pc_lob (_core_io_lsu_exe_0_req_bits_uop_pc_lob),
.io_lsu_exe_0_req_bits_uop_taken (_core_io_lsu_exe_0_req_bits_uop_taken),
.io_lsu_exe_0_req_bits_uop_imm_packed (_core_io_lsu_exe_0_req_bits_uop_imm_packed),
.io_lsu_exe_0_req_bits_uop_csr_addr (_core_io_lsu_exe_0_req_bits_uop_csr_addr),
.io_lsu_exe_0_req_bits_uop_rob_idx (_core_io_lsu_exe_0_req_bits_uop_rob_idx),
.io_lsu_exe_0_req_bits_uop_ldq_idx (_core_io_lsu_exe_0_req_bits_uop_ldq_idx),
.io_lsu_exe_0_req_bits_uop_stq_idx (_core_io_lsu_exe_0_req_bits_uop_stq_idx),
.io_lsu_exe_0_req_bits_uop_rxq_idx (_core_io_lsu_exe_0_req_bits_uop_rxq_idx),
.io_lsu_exe_0_req_bits_uop_pdst (_core_io_lsu_exe_0_req_bits_uop_pdst),
.io_lsu_exe_0_req_bits_uop_prs1 (_core_io_lsu_exe_0_req_bits_uop_prs1),
.io_lsu_exe_0_req_bits_uop_prs2 (_core_io_lsu_exe_0_req_bits_uop_prs2),
.io_lsu_exe_0_req_bits_uop_prs3 (_core_io_lsu_exe_0_req_bits_uop_prs3),
.io_lsu_exe_0_req_bits_uop_ppred (_core_io_lsu_exe_0_req_bits_uop_ppred),
.io_lsu_exe_0_req_bits_uop_prs1_busy (_core_io_lsu_exe_0_req_bits_uop_prs1_busy),
.io_lsu_exe_0_req_bits_uop_prs2_busy (_core_io_lsu_exe_0_req_bits_uop_prs2_busy),
.io_lsu_exe_0_req_bits_uop_prs3_busy (_core_io_lsu_exe_0_req_bits_uop_prs3_busy),
.io_lsu_exe_0_req_bits_uop_ppred_busy (_core_io_lsu_exe_0_req_bits_uop_ppred_busy),
.io_lsu_exe_0_req_bits_uop_stale_pdst (_core_io_lsu_exe_0_req_bits_uop_stale_pdst),
.io_lsu_exe_0_req_bits_uop_exception (_core_io_lsu_exe_0_req_bits_uop_exception),
.io_lsu_exe_0_req_bits_uop_exc_cause (_core_io_lsu_exe_0_req_bits_uop_exc_cause),
.io_lsu_exe_0_req_bits_uop_bypassable (_core_io_lsu_exe_0_req_bits_uop_bypassable),
.io_lsu_exe_0_req_bits_uop_mem_cmd (_core_io_lsu_exe_0_req_bits_uop_mem_cmd),
.io_lsu_exe_0_req_bits_uop_mem_size (_core_io_lsu_exe_0_req_bits_uop_mem_size),
.io_lsu_exe_0_req_bits_uop_mem_signed (_core_io_lsu_exe_0_req_bits_uop_mem_signed),
.io_lsu_exe_0_req_bits_uop_is_fence (_core_io_lsu_exe_0_req_bits_uop_is_fence),
.io_lsu_exe_0_req_bits_uop_is_fencei (_core_io_lsu_exe_0_req_bits_uop_is_fencei),
.io_lsu_exe_0_req_bits_uop_is_amo (_core_io_lsu_exe_0_req_bits_uop_is_amo),
.io_lsu_exe_0_req_bits_uop_uses_ldq (_core_io_lsu_exe_0_req_bits_uop_uses_ldq),
.io_lsu_exe_0_req_bits_uop_uses_stq (_core_io_lsu_exe_0_req_bits_uop_uses_stq),
.io_lsu_exe_0_req_bits_uop_is_sys_pc2epc (_core_io_lsu_exe_0_req_bits_uop_is_sys_pc2epc),
.io_lsu_exe_0_req_bits_uop_is_unique (_core_io_lsu_exe_0_req_bits_uop_is_unique),
.io_lsu_exe_0_req_bits_uop_flush_on_commit (_core_io_lsu_exe_0_req_bits_uop_flush_on_commit),
.io_lsu_exe_0_req_bits_uop_ldst_is_rs1 (_core_io_lsu_exe_0_req_bits_uop_ldst_is_rs1),
.io_lsu_exe_0_req_bits_uop_ldst (_core_io_lsu_exe_0_req_bits_uop_ldst),
.io_lsu_exe_0_req_bits_uop_lrs1 (_core_io_lsu_exe_0_req_bits_uop_lrs1),
.io_lsu_exe_0_req_bits_uop_lrs2 (_core_io_lsu_exe_0_req_bits_uop_lrs2),
.io_lsu_exe_0_req_bits_uop_lrs3 (_core_io_lsu_exe_0_req_bits_uop_lrs3),
.io_lsu_exe_0_req_bits_uop_ldst_val (_core_io_lsu_exe_0_req_bits_uop_ldst_val),
.io_lsu_exe_0_req_bits_uop_dst_rtype (_core_io_lsu_exe_0_req_bits_uop_dst_rtype),
.io_lsu_exe_0_req_bits_uop_lrs1_rtype (_core_io_lsu_exe_0_req_bits_uop_lrs1_rtype),
.io_lsu_exe_0_req_bits_uop_lrs2_rtype (_core_io_lsu_exe_0_req_bits_uop_lrs2_rtype),
.io_lsu_exe_0_req_bits_uop_frs3_en (_core_io_lsu_exe_0_req_bits_uop_frs3_en),
.io_lsu_exe_0_req_bits_uop_fp_val (_core_io_lsu_exe_0_req_bits_uop_fp_val),
.io_lsu_exe_0_req_bits_uop_fp_single (_core_io_lsu_exe_0_req_bits_uop_fp_single),
.io_lsu_exe_0_req_bits_uop_xcpt_pf_if (_core_io_lsu_exe_0_req_bits_uop_xcpt_pf_if),
.io_lsu_exe_0_req_bits_uop_xcpt_ae_if (_core_io_lsu_exe_0_req_bits_uop_xcpt_ae_if),
.io_lsu_exe_0_req_bits_uop_xcpt_ma_if (_core_io_lsu_exe_0_req_bits_uop_xcpt_ma_if),
.io_lsu_exe_0_req_bits_uop_bp_debug_if (_core_io_lsu_exe_0_req_bits_uop_bp_debug_if),
.io_lsu_exe_0_req_bits_uop_bp_xcpt_if (_core_io_lsu_exe_0_req_bits_uop_bp_xcpt_if),
.io_lsu_exe_0_req_bits_uop_debug_fsrc (_core_io_lsu_exe_0_req_bits_uop_debug_fsrc),
.io_lsu_exe_0_req_bits_uop_debug_tsrc (_core_io_lsu_exe_0_req_bits_uop_debug_tsrc),
.io_lsu_exe_0_req_bits_data (_core_io_lsu_exe_0_req_bits_data),
.io_lsu_exe_0_req_bits_addr (_core_io_lsu_exe_0_req_bits_addr),
.io_lsu_exe_0_req_bits_mxcpt_valid (_core_io_lsu_exe_0_req_bits_mxcpt_valid),
.io_lsu_exe_0_req_bits_mxcpt_bits (_core_io_lsu_exe_0_req_bits_mxcpt_bits),
.io_lsu_exe_0_req_bits_sfence_valid (_core_io_lsu_exe_0_req_bits_sfence_valid),
.io_lsu_exe_0_req_bits_sfence_bits_rs1 (_core_io_lsu_exe_0_req_bits_sfence_bits_rs1),
.io_lsu_exe_0_req_bits_sfence_bits_rs2 (_core_io_lsu_exe_0_req_bits_sfence_bits_rs2),
.io_lsu_exe_0_req_bits_sfence_bits_addr (_core_io_lsu_exe_0_req_bits_sfence_bits_addr),
.io_lsu_exe_0_req_bits_sfence_bits_asid (_core_io_lsu_exe_0_req_bits_sfence_bits_asid),
.io_lsu_exe_0_iresp_valid (_lsu_io_core_exe_0_iresp_valid), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_uopc (_lsu_io_core_exe_0_iresp_bits_uop_uopc), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_inst (_lsu_io_core_exe_0_iresp_bits_uop_inst), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_debug_inst (_lsu_io_core_exe_0_iresp_bits_uop_debug_inst), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_is_rvc (_lsu_io_core_exe_0_iresp_bits_uop_is_rvc), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_debug_pc (_lsu_io_core_exe_0_iresp_bits_uop_debug_pc), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_iq_type (_lsu_io_core_exe_0_iresp_bits_uop_iq_type), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_fu_code (_lsu_io_core_exe_0_iresp_bits_uop_fu_code), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_ctrl_br_type (_lsu_io_core_exe_0_iresp_bits_uop_ctrl_br_type), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_ctrl_op1_sel (_lsu_io_core_exe_0_iresp_bits_uop_ctrl_op1_sel), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_ctrl_op2_sel (_lsu_io_core_exe_0_iresp_bits_uop_ctrl_op2_sel), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_ctrl_imm_sel (_lsu_io_core_exe_0_iresp_bits_uop_ctrl_imm_sel), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_ctrl_op_fcn (_lsu_io_core_exe_0_iresp_bits_uop_ctrl_op_fcn), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_ctrl_fcn_dw (_lsu_io_core_exe_0_iresp_bits_uop_ctrl_fcn_dw), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_ctrl_csr_cmd (_lsu_io_core_exe_0_iresp_bits_uop_ctrl_csr_cmd), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_ctrl_is_load (_lsu_io_core_exe_0_iresp_bits_uop_ctrl_is_load), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_ctrl_is_sta (_lsu_io_core_exe_0_iresp_bits_uop_ctrl_is_sta), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_ctrl_is_std (_lsu_io_core_exe_0_iresp_bits_uop_ctrl_is_std), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_iw_state (_lsu_io_core_exe_0_iresp_bits_uop_iw_state), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_iw_p1_poisoned (_lsu_io_core_exe_0_iresp_bits_uop_iw_p1_poisoned), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_iw_p2_poisoned (_lsu_io_core_exe_0_iresp_bits_uop_iw_p2_poisoned), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_is_br (_lsu_io_core_exe_0_iresp_bits_uop_is_br), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_is_jalr (_lsu_io_core_exe_0_iresp_bits_uop_is_jalr), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_is_jal (_lsu_io_core_exe_0_iresp_bits_uop_is_jal), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_is_sfb (_lsu_io_core_exe_0_iresp_bits_uop_is_sfb), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_br_mask (_lsu_io_core_exe_0_iresp_bits_uop_br_mask), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_br_tag (_lsu_io_core_exe_0_iresp_bits_uop_br_tag), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_ftq_idx (_lsu_io_core_exe_0_iresp_bits_uop_ftq_idx), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_edge_inst (_lsu_io_core_exe_0_iresp_bits_uop_edge_inst), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_pc_lob (_lsu_io_core_exe_0_iresp_bits_uop_pc_lob), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_taken (_lsu_io_core_exe_0_iresp_bits_uop_taken), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_imm_packed (_lsu_io_core_exe_0_iresp_bits_uop_imm_packed), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_csr_addr (_lsu_io_core_exe_0_iresp_bits_uop_csr_addr), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_rob_idx (_lsu_io_core_exe_0_iresp_bits_uop_rob_idx), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_ldq_idx (_lsu_io_core_exe_0_iresp_bits_uop_ldq_idx), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_stq_idx (_lsu_io_core_exe_0_iresp_bits_uop_stq_idx), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_rxq_idx (_lsu_io_core_exe_0_iresp_bits_uop_rxq_idx), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_pdst (_lsu_io_core_exe_0_iresp_bits_uop_pdst), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_prs1 (_lsu_io_core_exe_0_iresp_bits_uop_prs1), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_prs2 (_lsu_io_core_exe_0_iresp_bits_uop_prs2), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_prs3 (_lsu_io_core_exe_0_iresp_bits_uop_prs3), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_ppred (_lsu_io_core_exe_0_iresp_bits_uop_ppred), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_prs1_busy (_lsu_io_core_exe_0_iresp_bits_uop_prs1_busy), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_prs2_busy (_lsu_io_core_exe_0_iresp_bits_uop_prs2_busy), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_prs3_busy (_lsu_io_core_exe_0_iresp_bits_uop_prs3_busy), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_ppred_busy (_lsu_io_core_exe_0_iresp_bits_uop_ppred_busy), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_stale_pdst (_lsu_io_core_exe_0_iresp_bits_uop_stale_pdst), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_exception (_lsu_io_core_exe_0_iresp_bits_uop_exception), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_exc_cause (_lsu_io_core_exe_0_iresp_bits_uop_exc_cause), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_bypassable (_lsu_io_core_exe_0_iresp_bits_uop_bypassable), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_mem_cmd (_lsu_io_core_exe_0_iresp_bits_uop_mem_cmd), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_mem_size (_lsu_io_core_exe_0_iresp_bits_uop_mem_size), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_mem_signed (_lsu_io_core_exe_0_iresp_bits_uop_mem_signed), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_is_fence (_lsu_io_core_exe_0_iresp_bits_uop_is_fence), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_is_fencei (_lsu_io_core_exe_0_iresp_bits_uop_is_fencei), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_is_amo (_lsu_io_core_exe_0_iresp_bits_uop_is_amo), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_uses_ldq (_lsu_io_core_exe_0_iresp_bits_uop_uses_ldq), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_uses_stq (_lsu_io_core_exe_0_iresp_bits_uop_uses_stq), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_is_sys_pc2epc (_lsu_io_core_exe_0_iresp_bits_uop_is_sys_pc2epc), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_is_unique (_lsu_io_core_exe_0_iresp_bits_uop_is_unique), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_flush_on_commit (_lsu_io_core_exe_0_iresp_bits_uop_flush_on_commit), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_ldst_is_rs1 (_lsu_io_core_exe_0_iresp_bits_uop_ldst_is_rs1), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_ldst (_lsu_io_core_exe_0_iresp_bits_uop_ldst), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_lrs1 (_lsu_io_core_exe_0_iresp_bits_uop_lrs1), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_lrs2 (_lsu_io_core_exe_0_iresp_bits_uop_lrs2), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_lrs3 (_lsu_io_core_exe_0_iresp_bits_uop_lrs3), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_ldst_val (_lsu_io_core_exe_0_iresp_bits_uop_ldst_val), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_dst_rtype (_lsu_io_core_exe_0_iresp_bits_uop_dst_rtype), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_lrs1_rtype (_lsu_io_core_exe_0_iresp_bits_uop_lrs1_rtype), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_lrs2_rtype (_lsu_io_core_exe_0_iresp_bits_uop_lrs2_rtype), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_frs3_en (_lsu_io_core_exe_0_iresp_bits_uop_frs3_en), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_fp_val (_lsu_io_core_exe_0_iresp_bits_uop_fp_val), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_fp_single (_lsu_io_core_exe_0_iresp_bits_uop_fp_single), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_xcpt_pf_if (_lsu_io_core_exe_0_iresp_bits_uop_xcpt_pf_if), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_xcpt_ae_if (_lsu_io_core_exe_0_iresp_bits_uop_xcpt_ae_if), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_xcpt_ma_if (_lsu_io_core_exe_0_iresp_bits_uop_xcpt_ma_if), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_bp_debug_if (_lsu_io_core_exe_0_iresp_bits_uop_bp_debug_if), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_bp_xcpt_if (_lsu_io_core_exe_0_iresp_bits_uop_bp_xcpt_if), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_debug_fsrc (_lsu_io_core_exe_0_iresp_bits_uop_debug_fsrc), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_debug_tsrc (_lsu_io_core_exe_0_iresp_bits_uop_debug_tsrc), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_data (_lsu_io_core_exe_0_iresp_bits_data), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_valid (_lsu_io_core_exe_0_fresp_valid), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_uopc (_lsu_io_core_exe_0_fresp_bits_uop_uopc), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_inst (_lsu_io_core_exe_0_fresp_bits_uop_inst), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_debug_inst (_lsu_io_core_exe_0_fresp_bits_uop_debug_inst), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_is_rvc (_lsu_io_core_exe_0_fresp_bits_uop_is_rvc), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_debug_pc (_lsu_io_core_exe_0_fresp_bits_uop_debug_pc), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_iq_type (_lsu_io_core_exe_0_fresp_bits_uop_iq_type), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_fu_code (_lsu_io_core_exe_0_fresp_bits_uop_fu_code), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_ctrl_br_type (_lsu_io_core_exe_0_fresp_bits_uop_ctrl_br_type), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_ctrl_op1_sel (_lsu_io_core_exe_0_fresp_bits_uop_ctrl_op1_sel), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_ctrl_op2_sel (_lsu_io_core_exe_0_fresp_bits_uop_ctrl_op2_sel), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_ctrl_imm_sel (_lsu_io_core_exe_0_fresp_bits_uop_ctrl_imm_sel), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_ctrl_op_fcn (_lsu_io_core_exe_0_fresp_bits_uop_ctrl_op_fcn), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_ctrl_fcn_dw (_lsu_io_core_exe_0_fresp_bits_uop_ctrl_fcn_dw), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_ctrl_csr_cmd (_lsu_io_core_exe_0_fresp_bits_uop_ctrl_csr_cmd), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_ctrl_is_load (_lsu_io_core_exe_0_fresp_bits_uop_ctrl_is_load), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_ctrl_is_sta (_lsu_io_core_exe_0_fresp_bits_uop_ctrl_is_sta), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_ctrl_is_std (_lsu_io_core_exe_0_fresp_bits_uop_ctrl_is_std), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_iw_state (_lsu_io_core_exe_0_fresp_bits_uop_iw_state), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_iw_p1_poisoned (_lsu_io_core_exe_0_fresp_bits_uop_iw_p1_poisoned), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_iw_p2_poisoned (_lsu_io_core_exe_0_fresp_bits_uop_iw_p2_poisoned), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_is_br (_lsu_io_core_exe_0_fresp_bits_uop_is_br), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_is_jalr (_lsu_io_core_exe_0_fresp_bits_uop_is_jalr), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_is_jal (_lsu_io_core_exe_0_fresp_bits_uop_is_jal), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_is_sfb (_lsu_io_core_exe_0_fresp_bits_uop_is_sfb), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_br_mask (_lsu_io_core_exe_0_fresp_bits_uop_br_mask), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_br_tag (_lsu_io_core_exe_0_fresp_bits_uop_br_tag), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_ftq_idx (_lsu_io_core_exe_0_fresp_bits_uop_ftq_idx), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_edge_inst (_lsu_io_core_exe_0_fresp_bits_uop_edge_inst), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_pc_lob (_lsu_io_core_exe_0_fresp_bits_uop_pc_lob), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_taken (_lsu_io_core_exe_0_fresp_bits_uop_taken), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_imm_packed (_lsu_io_core_exe_0_fresp_bits_uop_imm_packed), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_csr_addr (_lsu_io_core_exe_0_fresp_bits_uop_csr_addr), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_rob_idx (_lsu_io_core_exe_0_fresp_bits_uop_rob_idx), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_ldq_idx (_lsu_io_core_exe_0_fresp_bits_uop_ldq_idx), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_stq_idx (_lsu_io_core_exe_0_fresp_bits_uop_stq_idx), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_rxq_idx (_lsu_io_core_exe_0_fresp_bits_uop_rxq_idx), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_pdst (_lsu_io_core_exe_0_fresp_bits_uop_pdst), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_prs1 (_lsu_io_core_exe_0_fresp_bits_uop_prs1), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_prs2 (_lsu_io_core_exe_0_fresp_bits_uop_prs2), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_prs3 (_lsu_io_core_exe_0_fresp_bits_uop_prs3), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_ppred (_lsu_io_core_exe_0_fresp_bits_uop_ppred), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_prs1_busy (_lsu_io_core_exe_0_fresp_bits_uop_prs1_busy), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_prs2_busy (_lsu_io_core_exe_0_fresp_bits_uop_prs2_busy), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_prs3_busy (_lsu_io_core_exe_0_fresp_bits_uop_prs3_busy), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_ppred_busy (_lsu_io_core_exe_0_fresp_bits_uop_ppred_busy), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_stale_pdst (_lsu_io_core_exe_0_fresp_bits_uop_stale_pdst), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_exception (_lsu_io_core_exe_0_fresp_bits_uop_exception), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_exc_cause (_lsu_io_core_exe_0_fresp_bits_uop_exc_cause), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_bypassable (_lsu_io_core_exe_0_fresp_bits_uop_bypassable), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_mem_cmd (_lsu_io_core_exe_0_fresp_bits_uop_mem_cmd), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_mem_size (_lsu_io_core_exe_0_fresp_bits_uop_mem_size), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_mem_signed (_lsu_io_core_exe_0_fresp_bits_uop_mem_signed), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_is_fence (_lsu_io_core_exe_0_fresp_bits_uop_is_fence), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_is_fencei (_lsu_io_core_exe_0_fresp_bits_uop_is_fencei), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_is_amo (_lsu_io_core_exe_0_fresp_bits_uop_is_amo), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_uses_ldq (_lsu_io_core_exe_0_fresp_bits_uop_uses_ldq), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_uses_stq (_lsu_io_core_exe_0_fresp_bits_uop_uses_stq), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_is_sys_pc2epc (_lsu_io_core_exe_0_fresp_bits_uop_is_sys_pc2epc), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_is_unique (_lsu_io_core_exe_0_fresp_bits_uop_is_unique), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_flush_on_commit (_lsu_io_core_exe_0_fresp_bits_uop_flush_on_commit), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_ldst_is_rs1 (_lsu_io_core_exe_0_fresp_bits_uop_ldst_is_rs1), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_ldst (_lsu_io_core_exe_0_fresp_bits_uop_ldst), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_lrs1 (_lsu_io_core_exe_0_fresp_bits_uop_lrs1), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_lrs2 (_lsu_io_core_exe_0_fresp_bits_uop_lrs2), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_lrs3 (_lsu_io_core_exe_0_fresp_bits_uop_lrs3), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_ldst_val (_lsu_io_core_exe_0_fresp_bits_uop_ldst_val), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_dst_rtype (_lsu_io_core_exe_0_fresp_bits_uop_dst_rtype), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_lrs1_rtype (_lsu_io_core_exe_0_fresp_bits_uop_lrs1_rtype), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_lrs2_rtype (_lsu_io_core_exe_0_fresp_bits_uop_lrs2_rtype), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_frs3_en (_lsu_io_core_exe_0_fresp_bits_uop_frs3_en), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_fp_val (_lsu_io_core_exe_0_fresp_bits_uop_fp_val), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_fp_single (_lsu_io_core_exe_0_fresp_bits_uop_fp_single), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_xcpt_pf_if (_lsu_io_core_exe_0_fresp_bits_uop_xcpt_pf_if), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_xcpt_ae_if (_lsu_io_core_exe_0_fresp_bits_uop_xcpt_ae_if), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_xcpt_ma_if (_lsu_io_core_exe_0_fresp_bits_uop_xcpt_ma_if), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_bp_debug_if (_lsu_io_core_exe_0_fresp_bits_uop_bp_debug_if), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_bp_xcpt_if (_lsu_io_core_exe_0_fresp_bits_uop_bp_xcpt_if), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_debug_fsrc (_lsu_io_core_exe_0_fresp_bits_uop_debug_fsrc), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_debug_tsrc (_lsu_io_core_exe_0_fresp_bits_uop_debug_tsrc), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_data (_lsu_io_core_exe_0_fresp_bits_data), // @[tile.scala:160:20]
.io_lsu_dis_uops_0_valid (_core_io_lsu_dis_uops_0_valid),
.io_lsu_dis_uops_0_bits_uopc (_core_io_lsu_dis_uops_0_bits_uopc),
.io_lsu_dis_uops_0_bits_inst (_core_io_lsu_dis_uops_0_bits_inst),
.io_lsu_dis_uops_0_bits_debug_inst (_core_io_lsu_dis_uops_0_bits_debug_inst),
.io_lsu_dis_uops_0_bits_is_rvc (_core_io_lsu_dis_uops_0_bits_is_rvc),
.io_lsu_dis_uops_0_bits_debug_pc (_core_io_lsu_dis_uops_0_bits_debug_pc),
.io_lsu_dis_uops_0_bits_iq_type (_core_io_lsu_dis_uops_0_bits_iq_type),
.io_lsu_dis_uops_0_bits_fu_code (_core_io_lsu_dis_uops_0_bits_fu_code),
.io_lsu_dis_uops_0_bits_ctrl_br_type (_core_io_lsu_dis_uops_0_bits_ctrl_br_type),
.io_lsu_dis_uops_0_bits_ctrl_op1_sel (_core_io_lsu_dis_uops_0_bits_ctrl_op1_sel),
.io_lsu_dis_uops_0_bits_ctrl_op2_sel (_core_io_lsu_dis_uops_0_bits_ctrl_op2_sel),
.io_lsu_dis_uops_0_bits_ctrl_imm_sel (_core_io_lsu_dis_uops_0_bits_ctrl_imm_sel),
.io_lsu_dis_uops_0_bits_ctrl_op_fcn (_core_io_lsu_dis_uops_0_bits_ctrl_op_fcn),
.io_lsu_dis_uops_0_bits_ctrl_fcn_dw (_core_io_lsu_dis_uops_0_bits_ctrl_fcn_dw),
.io_lsu_dis_uops_0_bits_ctrl_csr_cmd (_core_io_lsu_dis_uops_0_bits_ctrl_csr_cmd),
.io_lsu_dis_uops_0_bits_ctrl_is_load (_core_io_lsu_dis_uops_0_bits_ctrl_is_load),
.io_lsu_dis_uops_0_bits_ctrl_is_sta (_core_io_lsu_dis_uops_0_bits_ctrl_is_sta),
.io_lsu_dis_uops_0_bits_ctrl_is_std (_core_io_lsu_dis_uops_0_bits_ctrl_is_std),
.io_lsu_dis_uops_0_bits_iw_state (_core_io_lsu_dis_uops_0_bits_iw_state),
.io_lsu_dis_uops_0_bits_iw_p1_poisoned (_core_io_lsu_dis_uops_0_bits_iw_p1_poisoned),
.io_lsu_dis_uops_0_bits_iw_p2_poisoned (_core_io_lsu_dis_uops_0_bits_iw_p2_poisoned),
.io_lsu_dis_uops_0_bits_is_br (_core_io_lsu_dis_uops_0_bits_is_br),
.io_lsu_dis_uops_0_bits_is_jalr (_core_io_lsu_dis_uops_0_bits_is_jalr),
.io_lsu_dis_uops_0_bits_is_jal (_core_io_lsu_dis_uops_0_bits_is_jal),
.io_lsu_dis_uops_0_bits_is_sfb (_core_io_lsu_dis_uops_0_bits_is_sfb),
.io_lsu_dis_uops_0_bits_br_mask (_core_io_lsu_dis_uops_0_bits_br_mask),
.io_lsu_dis_uops_0_bits_br_tag (_core_io_lsu_dis_uops_0_bits_br_tag),
.io_lsu_dis_uops_0_bits_ftq_idx (_core_io_lsu_dis_uops_0_bits_ftq_idx),
.io_lsu_dis_uops_0_bits_edge_inst (_core_io_lsu_dis_uops_0_bits_edge_inst),
.io_lsu_dis_uops_0_bits_pc_lob (_core_io_lsu_dis_uops_0_bits_pc_lob),
.io_lsu_dis_uops_0_bits_taken (_core_io_lsu_dis_uops_0_bits_taken),
.io_lsu_dis_uops_0_bits_imm_packed (_core_io_lsu_dis_uops_0_bits_imm_packed),
.io_lsu_dis_uops_0_bits_csr_addr (_core_io_lsu_dis_uops_0_bits_csr_addr),
.io_lsu_dis_uops_0_bits_rob_idx (_core_io_lsu_dis_uops_0_bits_rob_idx),
.io_lsu_dis_uops_0_bits_ldq_idx (_core_io_lsu_dis_uops_0_bits_ldq_idx),
.io_lsu_dis_uops_0_bits_stq_idx (_core_io_lsu_dis_uops_0_bits_stq_idx),
.io_lsu_dis_uops_0_bits_rxq_idx (_core_io_lsu_dis_uops_0_bits_rxq_idx),
.io_lsu_dis_uops_0_bits_pdst (_core_io_lsu_dis_uops_0_bits_pdst),
.io_lsu_dis_uops_0_bits_prs1 (_core_io_lsu_dis_uops_0_bits_prs1),
.io_lsu_dis_uops_0_bits_prs2 (_core_io_lsu_dis_uops_0_bits_prs2),
.io_lsu_dis_uops_0_bits_prs3 (_core_io_lsu_dis_uops_0_bits_prs3),
.io_lsu_dis_uops_0_bits_prs1_busy (_core_io_lsu_dis_uops_0_bits_prs1_busy),
.io_lsu_dis_uops_0_bits_prs2_busy (_core_io_lsu_dis_uops_0_bits_prs2_busy),
.io_lsu_dis_uops_0_bits_prs3_busy (_core_io_lsu_dis_uops_0_bits_prs3_busy),
.io_lsu_dis_uops_0_bits_stale_pdst (_core_io_lsu_dis_uops_0_bits_stale_pdst),
.io_lsu_dis_uops_0_bits_exception (_core_io_lsu_dis_uops_0_bits_exception),
.io_lsu_dis_uops_0_bits_exc_cause (_core_io_lsu_dis_uops_0_bits_exc_cause),
.io_lsu_dis_uops_0_bits_bypassable (_core_io_lsu_dis_uops_0_bits_bypassable),
.io_lsu_dis_uops_0_bits_mem_cmd (_core_io_lsu_dis_uops_0_bits_mem_cmd),
.io_lsu_dis_uops_0_bits_mem_size (_core_io_lsu_dis_uops_0_bits_mem_size),
.io_lsu_dis_uops_0_bits_mem_signed (_core_io_lsu_dis_uops_0_bits_mem_signed),
.io_lsu_dis_uops_0_bits_is_fence (_core_io_lsu_dis_uops_0_bits_is_fence),
.io_lsu_dis_uops_0_bits_is_fencei (_core_io_lsu_dis_uops_0_bits_is_fencei),
.io_lsu_dis_uops_0_bits_is_amo (_core_io_lsu_dis_uops_0_bits_is_amo),
.io_lsu_dis_uops_0_bits_uses_ldq (_core_io_lsu_dis_uops_0_bits_uses_ldq),
.io_lsu_dis_uops_0_bits_uses_stq (_core_io_lsu_dis_uops_0_bits_uses_stq),
.io_lsu_dis_uops_0_bits_is_sys_pc2epc (_core_io_lsu_dis_uops_0_bits_is_sys_pc2epc),
.io_lsu_dis_uops_0_bits_is_unique (_core_io_lsu_dis_uops_0_bits_is_unique),
.io_lsu_dis_uops_0_bits_flush_on_commit (_core_io_lsu_dis_uops_0_bits_flush_on_commit),
.io_lsu_dis_uops_0_bits_ldst_is_rs1 (_core_io_lsu_dis_uops_0_bits_ldst_is_rs1),
.io_lsu_dis_uops_0_bits_ldst (_core_io_lsu_dis_uops_0_bits_ldst),
.io_lsu_dis_uops_0_bits_lrs1 (_core_io_lsu_dis_uops_0_bits_lrs1),
.io_lsu_dis_uops_0_bits_lrs2 (_core_io_lsu_dis_uops_0_bits_lrs2),
.io_lsu_dis_uops_0_bits_lrs3 (_core_io_lsu_dis_uops_0_bits_lrs3),
.io_lsu_dis_uops_0_bits_ldst_val (_core_io_lsu_dis_uops_0_bits_ldst_val),
.io_lsu_dis_uops_0_bits_dst_rtype (_core_io_lsu_dis_uops_0_bits_dst_rtype),
.io_lsu_dis_uops_0_bits_lrs1_rtype (_core_io_lsu_dis_uops_0_bits_lrs1_rtype),
.io_lsu_dis_uops_0_bits_lrs2_rtype (_core_io_lsu_dis_uops_0_bits_lrs2_rtype),
.io_lsu_dis_uops_0_bits_frs3_en (_core_io_lsu_dis_uops_0_bits_frs3_en),
.io_lsu_dis_uops_0_bits_fp_val (_core_io_lsu_dis_uops_0_bits_fp_val),
.io_lsu_dis_uops_0_bits_fp_single (_core_io_lsu_dis_uops_0_bits_fp_single),
.io_lsu_dis_uops_0_bits_xcpt_pf_if (_core_io_lsu_dis_uops_0_bits_xcpt_pf_if),
.io_lsu_dis_uops_0_bits_xcpt_ae_if (_core_io_lsu_dis_uops_0_bits_xcpt_ae_if),
.io_lsu_dis_uops_0_bits_xcpt_ma_if (_core_io_lsu_dis_uops_0_bits_xcpt_ma_if),
.io_lsu_dis_uops_0_bits_bp_debug_if (_core_io_lsu_dis_uops_0_bits_bp_debug_if),
.io_lsu_dis_uops_0_bits_bp_xcpt_if (_core_io_lsu_dis_uops_0_bits_bp_xcpt_if),
.io_lsu_dis_uops_0_bits_debug_fsrc (_core_io_lsu_dis_uops_0_bits_debug_fsrc),
.io_lsu_dis_uops_0_bits_debug_tsrc (_core_io_lsu_dis_uops_0_bits_debug_tsrc),
.io_lsu_dis_uops_1_valid (_core_io_lsu_dis_uops_1_valid),
.io_lsu_dis_uops_1_bits_uopc (_core_io_lsu_dis_uops_1_bits_uopc),
.io_lsu_dis_uops_1_bits_inst (_core_io_lsu_dis_uops_1_bits_inst),
.io_lsu_dis_uops_1_bits_debug_inst (_core_io_lsu_dis_uops_1_bits_debug_inst),
.io_lsu_dis_uops_1_bits_is_rvc (_core_io_lsu_dis_uops_1_bits_is_rvc),
.io_lsu_dis_uops_1_bits_debug_pc (_core_io_lsu_dis_uops_1_bits_debug_pc),
.io_lsu_dis_uops_1_bits_iq_type (_core_io_lsu_dis_uops_1_bits_iq_type),
.io_lsu_dis_uops_1_bits_fu_code (_core_io_lsu_dis_uops_1_bits_fu_code),
.io_lsu_dis_uops_1_bits_ctrl_br_type (_core_io_lsu_dis_uops_1_bits_ctrl_br_type),
.io_lsu_dis_uops_1_bits_ctrl_op1_sel (_core_io_lsu_dis_uops_1_bits_ctrl_op1_sel),
.io_lsu_dis_uops_1_bits_ctrl_op2_sel (_core_io_lsu_dis_uops_1_bits_ctrl_op2_sel),
.io_lsu_dis_uops_1_bits_ctrl_imm_sel (_core_io_lsu_dis_uops_1_bits_ctrl_imm_sel),
.io_lsu_dis_uops_1_bits_ctrl_op_fcn (_core_io_lsu_dis_uops_1_bits_ctrl_op_fcn),
.io_lsu_dis_uops_1_bits_ctrl_fcn_dw (_core_io_lsu_dis_uops_1_bits_ctrl_fcn_dw),
.io_lsu_dis_uops_1_bits_ctrl_csr_cmd (_core_io_lsu_dis_uops_1_bits_ctrl_csr_cmd),
.io_lsu_dis_uops_1_bits_ctrl_is_load (_core_io_lsu_dis_uops_1_bits_ctrl_is_load),
.io_lsu_dis_uops_1_bits_ctrl_is_sta (_core_io_lsu_dis_uops_1_bits_ctrl_is_sta),
.io_lsu_dis_uops_1_bits_ctrl_is_std (_core_io_lsu_dis_uops_1_bits_ctrl_is_std),
.io_lsu_dis_uops_1_bits_iw_state (_core_io_lsu_dis_uops_1_bits_iw_state),
.io_lsu_dis_uops_1_bits_iw_p1_poisoned (_core_io_lsu_dis_uops_1_bits_iw_p1_poisoned),
.io_lsu_dis_uops_1_bits_iw_p2_poisoned (_core_io_lsu_dis_uops_1_bits_iw_p2_poisoned),
.io_lsu_dis_uops_1_bits_is_br (_core_io_lsu_dis_uops_1_bits_is_br),
.io_lsu_dis_uops_1_bits_is_jalr (_core_io_lsu_dis_uops_1_bits_is_jalr),
.io_lsu_dis_uops_1_bits_is_jal (_core_io_lsu_dis_uops_1_bits_is_jal),
.io_lsu_dis_uops_1_bits_is_sfb (_core_io_lsu_dis_uops_1_bits_is_sfb),
.io_lsu_dis_uops_1_bits_br_mask (_core_io_lsu_dis_uops_1_bits_br_mask),
.io_lsu_dis_uops_1_bits_br_tag (_core_io_lsu_dis_uops_1_bits_br_tag),
.io_lsu_dis_uops_1_bits_ftq_idx (_core_io_lsu_dis_uops_1_bits_ftq_idx),
.io_lsu_dis_uops_1_bits_edge_inst (_core_io_lsu_dis_uops_1_bits_edge_inst),
.io_lsu_dis_uops_1_bits_pc_lob (_core_io_lsu_dis_uops_1_bits_pc_lob),
.io_lsu_dis_uops_1_bits_taken (_core_io_lsu_dis_uops_1_bits_taken),
.io_lsu_dis_uops_1_bits_imm_packed (_core_io_lsu_dis_uops_1_bits_imm_packed),
.io_lsu_dis_uops_1_bits_csr_addr (_core_io_lsu_dis_uops_1_bits_csr_addr),
.io_lsu_dis_uops_1_bits_rob_idx (_core_io_lsu_dis_uops_1_bits_rob_idx),
.io_lsu_dis_uops_1_bits_ldq_idx (_core_io_lsu_dis_uops_1_bits_ldq_idx),
.io_lsu_dis_uops_1_bits_stq_idx (_core_io_lsu_dis_uops_1_bits_stq_idx),
.io_lsu_dis_uops_1_bits_rxq_idx (_core_io_lsu_dis_uops_1_bits_rxq_idx),
.io_lsu_dis_uops_1_bits_pdst (_core_io_lsu_dis_uops_1_bits_pdst),
.io_lsu_dis_uops_1_bits_prs1 (_core_io_lsu_dis_uops_1_bits_prs1),
.io_lsu_dis_uops_1_bits_prs2 (_core_io_lsu_dis_uops_1_bits_prs2),
.io_lsu_dis_uops_1_bits_prs3 (_core_io_lsu_dis_uops_1_bits_prs3),
.io_lsu_dis_uops_1_bits_prs1_busy (_core_io_lsu_dis_uops_1_bits_prs1_busy),
.io_lsu_dis_uops_1_bits_prs2_busy (_core_io_lsu_dis_uops_1_bits_prs2_busy),
.io_lsu_dis_uops_1_bits_prs3_busy (_core_io_lsu_dis_uops_1_bits_prs3_busy),
.io_lsu_dis_uops_1_bits_stale_pdst (_core_io_lsu_dis_uops_1_bits_stale_pdst),
.io_lsu_dis_uops_1_bits_exception (_core_io_lsu_dis_uops_1_bits_exception),
.io_lsu_dis_uops_1_bits_exc_cause (_core_io_lsu_dis_uops_1_bits_exc_cause),
.io_lsu_dis_uops_1_bits_bypassable (_core_io_lsu_dis_uops_1_bits_bypassable),
.io_lsu_dis_uops_1_bits_mem_cmd (_core_io_lsu_dis_uops_1_bits_mem_cmd),
.io_lsu_dis_uops_1_bits_mem_size (_core_io_lsu_dis_uops_1_bits_mem_size),
.io_lsu_dis_uops_1_bits_mem_signed (_core_io_lsu_dis_uops_1_bits_mem_signed),
.io_lsu_dis_uops_1_bits_is_fence (_core_io_lsu_dis_uops_1_bits_is_fence),
.io_lsu_dis_uops_1_bits_is_fencei (_core_io_lsu_dis_uops_1_bits_is_fencei),
.io_lsu_dis_uops_1_bits_is_amo (_core_io_lsu_dis_uops_1_bits_is_amo),
.io_lsu_dis_uops_1_bits_uses_ldq (_core_io_lsu_dis_uops_1_bits_uses_ldq),
.io_lsu_dis_uops_1_bits_uses_stq (_core_io_lsu_dis_uops_1_bits_uses_stq),
.io_lsu_dis_uops_1_bits_is_sys_pc2epc (_core_io_lsu_dis_uops_1_bits_is_sys_pc2epc),
.io_lsu_dis_uops_1_bits_is_unique (_core_io_lsu_dis_uops_1_bits_is_unique),
.io_lsu_dis_uops_1_bits_flush_on_commit (_core_io_lsu_dis_uops_1_bits_flush_on_commit),
.io_lsu_dis_uops_1_bits_ldst_is_rs1 (_core_io_lsu_dis_uops_1_bits_ldst_is_rs1),
.io_lsu_dis_uops_1_bits_ldst (_core_io_lsu_dis_uops_1_bits_ldst),
.io_lsu_dis_uops_1_bits_lrs1 (_core_io_lsu_dis_uops_1_bits_lrs1),
.io_lsu_dis_uops_1_bits_lrs2 (_core_io_lsu_dis_uops_1_bits_lrs2),
.io_lsu_dis_uops_1_bits_lrs3 (_core_io_lsu_dis_uops_1_bits_lrs3),
.io_lsu_dis_uops_1_bits_ldst_val (_core_io_lsu_dis_uops_1_bits_ldst_val),
.io_lsu_dis_uops_1_bits_dst_rtype (_core_io_lsu_dis_uops_1_bits_dst_rtype),
.io_lsu_dis_uops_1_bits_lrs1_rtype (_core_io_lsu_dis_uops_1_bits_lrs1_rtype),
.io_lsu_dis_uops_1_bits_lrs2_rtype (_core_io_lsu_dis_uops_1_bits_lrs2_rtype),
.io_lsu_dis_uops_1_bits_frs3_en (_core_io_lsu_dis_uops_1_bits_frs3_en),
.io_lsu_dis_uops_1_bits_fp_val (_core_io_lsu_dis_uops_1_bits_fp_val),
.io_lsu_dis_uops_1_bits_fp_single (_core_io_lsu_dis_uops_1_bits_fp_single),
.io_lsu_dis_uops_1_bits_xcpt_pf_if (_core_io_lsu_dis_uops_1_bits_xcpt_pf_if),
.io_lsu_dis_uops_1_bits_xcpt_ae_if (_core_io_lsu_dis_uops_1_bits_xcpt_ae_if),
.io_lsu_dis_uops_1_bits_xcpt_ma_if (_core_io_lsu_dis_uops_1_bits_xcpt_ma_if),
.io_lsu_dis_uops_1_bits_bp_debug_if (_core_io_lsu_dis_uops_1_bits_bp_debug_if),
.io_lsu_dis_uops_1_bits_bp_xcpt_if (_core_io_lsu_dis_uops_1_bits_bp_xcpt_if),
.io_lsu_dis_uops_1_bits_debug_fsrc (_core_io_lsu_dis_uops_1_bits_debug_fsrc),
.io_lsu_dis_uops_1_bits_debug_tsrc (_core_io_lsu_dis_uops_1_bits_debug_tsrc),
.io_lsu_dis_uops_2_valid (_core_io_lsu_dis_uops_2_valid),
.io_lsu_dis_uops_2_bits_uopc (_core_io_lsu_dis_uops_2_bits_uopc),
.io_lsu_dis_uops_2_bits_inst (_core_io_lsu_dis_uops_2_bits_inst),
.io_lsu_dis_uops_2_bits_debug_inst (_core_io_lsu_dis_uops_2_bits_debug_inst),
.io_lsu_dis_uops_2_bits_is_rvc (_core_io_lsu_dis_uops_2_bits_is_rvc),
.io_lsu_dis_uops_2_bits_debug_pc (_core_io_lsu_dis_uops_2_bits_debug_pc),
.io_lsu_dis_uops_2_bits_iq_type (_core_io_lsu_dis_uops_2_bits_iq_type),
.io_lsu_dis_uops_2_bits_fu_code (_core_io_lsu_dis_uops_2_bits_fu_code),
.io_lsu_dis_uops_2_bits_ctrl_br_type (_core_io_lsu_dis_uops_2_bits_ctrl_br_type),
.io_lsu_dis_uops_2_bits_ctrl_op1_sel (_core_io_lsu_dis_uops_2_bits_ctrl_op1_sel),
.io_lsu_dis_uops_2_bits_ctrl_op2_sel (_core_io_lsu_dis_uops_2_bits_ctrl_op2_sel),
.io_lsu_dis_uops_2_bits_ctrl_imm_sel (_core_io_lsu_dis_uops_2_bits_ctrl_imm_sel),
.io_lsu_dis_uops_2_bits_ctrl_op_fcn (_core_io_lsu_dis_uops_2_bits_ctrl_op_fcn),
.io_lsu_dis_uops_2_bits_ctrl_fcn_dw (_core_io_lsu_dis_uops_2_bits_ctrl_fcn_dw),
.io_lsu_dis_uops_2_bits_ctrl_csr_cmd (_core_io_lsu_dis_uops_2_bits_ctrl_csr_cmd),
.io_lsu_dis_uops_2_bits_ctrl_is_load (_core_io_lsu_dis_uops_2_bits_ctrl_is_load),
.io_lsu_dis_uops_2_bits_ctrl_is_sta (_core_io_lsu_dis_uops_2_bits_ctrl_is_sta),
.io_lsu_dis_uops_2_bits_ctrl_is_std (_core_io_lsu_dis_uops_2_bits_ctrl_is_std),
.io_lsu_dis_uops_2_bits_iw_state (_core_io_lsu_dis_uops_2_bits_iw_state),
.io_lsu_dis_uops_2_bits_iw_p1_poisoned (_core_io_lsu_dis_uops_2_bits_iw_p1_poisoned),
.io_lsu_dis_uops_2_bits_iw_p2_poisoned (_core_io_lsu_dis_uops_2_bits_iw_p2_poisoned),
.io_lsu_dis_uops_2_bits_is_br (_core_io_lsu_dis_uops_2_bits_is_br),
.io_lsu_dis_uops_2_bits_is_jalr (_core_io_lsu_dis_uops_2_bits_is_jalr),
.io_lsu_dis_uops_2_bits_is_jal (_core_io_lsu_dis_uops_2_bits_is_jal),
.io_lsu_dis_uops_2_bits_is_sfb (_core_io_lsu_dis_uops_2_bits_is_sfb),
.io_lsu_dis_uops_2_bits_br_mask (_core_io_lsu_dis_uops_2_bits_br_mask),
.io_lsu_dis_uops_2_bits_br_tag (_core_io_lsu_dis_uops_2_bits_br_tag),
.io_lsu_dis_uops_2_bits_ftq_idx (_core_io_lsu_dis_uops_2_bits_ftq_idx),
.io_lsu_dis_uops_2_bits_edge_inst (_core_io_lsu_dis_uops_2_bits_edge_inst),
.io_lsu_dis_uops_2_bits_pc_lob (_core_io_lsu_dis_uops_2_bits_pc_lob),
.io_lsu_dis_uops_2_bits_taken (_core_io_lsu_dis_uops_2_bits_taken),
.io_lsu_dis_uops_2_bits_imm_packed (_core_io_lsu_dis_uops_2_bits_imm_packed),
.io_lsu_dis_uops_2_bits_csr_addr (_core_io_lsu_dis_uops_2_bits_csr_addr),
.io_lsu_dis_uops_2_bits_rob_idx (_core_io_lsu_dis_uops_2_bits_rob_idx),
.io_lsu_dis_uops_2_bits_ldq_idx (_core_io_lsu_dis_uops_2_bits_ldq_idx),
.io_lsu_dis_uops_2_bits_stq_idx (_core_io_lsu_dis_uops_2_bits_stq_idx),
.io_lsu_dis_uops_2_bits_rxq_idx (_core_io_lsu_dis_uops_2_bits_rxq_idx),
.io_lsu_dis_uops_2_bits_pdst (_core_io_lsu_dis_uops_2_bits_pdst),
.io_lsu_dis_uops_2_bits_prs1 (_core_io_lsu_dis_uops_2_bits_prs1),
.io_lsu_dis_uops_2_bits_prs2 (_core_io_lsu_dis_uops_2_bits_prs2),
.io_lsu_dis_uops_2_bits_prs3 (_core_io_lsu_dis_uops_2_bits_prs3),
.io_lsu_dis_uops_2_bits_prs1_busy (_core_io_lsu_dis_uops_2_bits_prs1_busy),
.io_lsu_dis_uops_2_bits_prs2_busy (_core_io_lsu_dis_uops_2_bits_prs2_busy),
.io_lsu_dis_uops_2_bits_prs3_busy (_core_io_lsu_dis_uops_2_bits_prs3_busy),
.io_lsu_dis_uops_2_bits_stale_pdst (_core_io_lsu_dis_uops_2_bits_stale_pdst),
.io_lsu_dis_uops_2_bits_exception (_core_io_lsu_dis_uops_2_bits_exception),
.io_lsu_dis_uops_2_bits_exc_cause (_core_io_lsu_dis_uops_2_bits_exc_cause),
.io_lsu_dis_uops_2_bits_bypassable (_core_io_lsu_dis_uops_2_bits_bypassable),
.io_lsu_dis_uops_2_bits_mem_cmd (_core_io_lsu_dis_uops_2_bits_mem_cmd),
.io_lsu_dis_uops_2_bits_mem_size (_core_io_lsu_dis_uops_2_bits_mem_size),
.io_lsu_dis_uops_2_bits_mem_signed (_core_io_lsu_dis_uops_2_bits_mem_signed),
.io_lsu_dis_uops_2_bits_is_fence (_core_io_lsu_dis_uops_2_bits_is_fence),
.io_lsu_dis_uops_2_bits_is_fencei (_core_io_lsu_dis_uops_2_bits_is_fencei),
.io_lsu_dis_uops_2_bits_is_amo (_core_io_lsu_dis_uops_2_bits_is_amo),
.io_lsu_dis_uops_2_bits_uses_ldq (_core_io_lsu_dis_uops_2_bits_uses_ldq),
.io_lsu_dis_uops_2_bits_uses_stq (_core_io_lsu_dis_uops_2_bits_uses_stq),
.io_lsu_dis_uops_2_bits_is_sys_pc2epc (_core_io_lsu_dis_uops_2_bits_is_sys_pc2epc),
.io_lsu_dis_uops_2_bits_is_unique (_core_io_lsu_dis_uops_2_bits_is_unique),
.io_lsu_dis_uops_2_bits_flush_on_commit (_core_io_lsu_dis_uops_2_bits_flush_on_commit),
.io_lsu_dis_uops_2_bits_ldst_is_rs1 (_core_io_lsu_dis_uops_2_bits_ldst_is_rs1),
.io_lsu_dis_uops_2_bits_ldst (_core_io_lsu_dis_uops_2_bits_ldst),
.io_lsu_dis_uops_2_bits_lrs1 (_core_io_lsu_dis_uops_2_bits_lrs1),
.io_lsu_dis_uops_2_bits_lrs2 (_core_io_lsu_dis_uops_2_bits_lrs2),
.io_lsu_dis_uops_2_bits_lrs3 (_core_io_lsu_dis_uops_2_bits_lrs3),
.io_lsu_dis_uops_2_bits_ldst_val (_core_io_lsu_dis_uops_2_bits_ldst_val),
.io_lsu_dis_uops_2_bits_dst_rtype (_core_io_lsu_dis_uops_2_bits_dst_rtype),
.io_lsu_dis_uops_2_bits_lrs1_rtype (_core_io_lsu_dis_uops_2_bits_lrs1_rtype),
.io_lsu_dis_uops_2_bits_lrs2_rtype (_core_io_lsu_dis_uops_2_bits_lrs2_rtype),
.io_lsu_dis_uops_2_bits_frs3_en (_core_io_lsu_dis_uops_2_bits_frs3_en),
.io_lsu_dis_uops_2_bits_fp_val (_core_io_lsu_dis_uops_2_bits_fp_val),
.io_lsu_dis_uops_2_bits_fp_single (_core_io_lsu_dis_uops_2_bits_fp_single),
.io_lsu_dis_uops_2_bits_xcpt_pf_if (_core_io_lsu_dis_uops_2_bits_xcpt_pf_if),
.io_lsu_dis_uops_2_bits_xcpt_ae_if (_core_io_lsu_dis_uops_2_bits_xcpt_ae_if),
.io_lsu_dis_uops_2_bits_xcpt_ma_if (_core_io_lsu_dis_uops_2_bits_xcpt_ma_if),
.io_lsu_dis_uops_2_bits_bp_debug_if (_core_io_lsu_dis_uops_2_bits_bp_debug_if),
.io_lsu_dis_uops_2_bits_bp_xcpt_if (_core_io_lsu_dis_uops_2_bits_bp_xcpt_if),
.io_lsu_dis_uops_2_bits_debug_fsrc (_core_io_lsu_dis_uops_2_bits_debug_fsrc),
.io_lsu_dis_uops_2_bits_debug_tsrc (_core_io_lsu_dis_uops_2_bits_debug_tsrc),
.io_lsu_dis_ldq_idx_0 (_lsu_io_core_dis_ldq_idx_0), // @[tile.scala:160:20]
.io_lsu_dis_ldq_idx_1 (_lsu_io_core_dis_ldq_idx_1), // @[tile.scala:160:20]
.io_lsu_dis_ldq_idx_2 (_lsu_io_core_dis_ldq_idx_2), // @[tile.scala:160:20]
.io_lsu_dis_stq_idx_0 (_lsu_io_core_dis_stq_idx_0), // @[tile.scala:160:20]
.io_lsu_dis_stq_idx_1 (_lsu_io_core_dis_stq_idx_1), // @[tile.scala:160:20]
.io_lsu_dis_stq_idx_2 (_lsu_io_core_dis_stq_idx_2), // @[tile.scala:160:20]
.io_lsu_ldq_full_0 (_lsu_io_core_ldq_full_0), // @[tile.scala:160:20]
.io_lsu_ldq_full_1 (_lsu_io_core_ldq_full_1), // @[tile.scala:160:20]
.io_lsu_ldq_full_2 (_lsu_io_core_ldq_full_2), // @[tile.scala:160:20]
.io_lsu_stq_full_0 (_lsu_io_core_stq_full_0), // @[tile.scala:160:20]
.io_lsu_stq_full_1 (_lsu_io_core_stq_full_1), // @[tile.scala:160:20]
.io_lsu_stq_full_2 (_lsu_io_core_stq_full_2), // @[tile.scala:160:20]
.io_lsu_fp_stdata_ready (_lsu_io_core_fp_stdata_ready), // @[tile.scala:160:20]
.io_lsu_fp_stdata_valid (_core_io_lsu_fp_stdata_valid),
.io_lsu_fp_stdata_bits_uop_uopc (_core_io_lsu_fp_stdata_bits_uop_uopc),
.io_lsu_fp_stdata_bits_uop_inst (_core_io_lsu_fp_stdata_bits_uop_inst),
.io_lsu_fp_stdata_bits_uop_debug_inst (_core_io_lsu_fp_stdata_bits_uop_debug_inst),
.io_lsu_fp_stdata_bits_uop_is_rvc (_core_io_lsu_fp_stdata_bits_uop_is_rvc),
.io_lsu_fp_stdata_bits_uop_debug_pc (_core_io_lsu_fp_stdata_bits_uop_debug_pc),
.io_lsu_fp_stdata_bits_uop_iq_type (_core_io_lsu_fp_stdata_bits_uop_iq_type),
.io_lsu_fp_stdata_bits_uop_fu_code (_core_io_lsu_fp_stdata_bits_uop_fu_code),
.io_lsu_fp_stdata_bits_uop_ctrl_br_type (_core_io_lsu_fp_stdata_bits_uop_ctrl_br_type),
.io_lsu_fp_stdata_bits_uop_ctrl_op1_sel (_core_io_lsu_fp_stdata_bits_uop_ctrl_op1_sel),
.io_lsu_fp_stdata_bits_uop_ctrl_op2_sel (_core_io_lsu_fp_stdata_bits_uop_ctrl_op2_sel),
.io_lsu_fp_stdata_bits_uop_ctrl_imm_sel (_core_io_lsu_fp_stdata_bits_uop_ctrl_imm_sel),
.io_lsu_fp_stdata_bits_uop_ctrl_op_fcn (_core_io_lsu_fp_stdata_bits_uop_ctrl_op_fcn),
.io_lsu_fp_stdata_bits_uop_ctrl_fcn_dw (_core_io_lsu_fp_stdata_bits_uop_ctrl_fcn_dw),
.io_lsu_fp_stdata_bits_uop_ctrl_csr_cmd (_core_io_lsu_fp_stdata_bits_uop_ctrl_csr_cmd),
.io_lsu_fp_stdata_bits_uop_ctrl_is_load (_core_io_lsu_fp_stdata_bits_uop_ctrl_is_load),
.io_lsu_fp_stdata_bits_uop_ctrl_is_sta (_core_io_lsu_fp_stdata_bits_uop_ctrl_is_sta),
.io_lsu_fp_stdata_bits_uop_ctrl_is_std (_core_io_lsu_fp_stdata_bits_uop_ctrl_is_std),
.io_lsu_fp_stdata_bits_uop_iw_state (_core_io_lsu_fp_stdata_bits_uop_iw_state),
.io_lsu_fp_stdata_bits_uop_iw_p1_poisoned (_core_io_lsu_fp_stdata_bits_uop_iw_p1_poisoned),
.io_lsu_fp_stdata_bits_uop_iw_p2_poisoned (_core_io_lsu_fp_stdata_bits_uop_iw_p2_poisoned),
.io_lsu_fp_stdata_bits_uop_is_br (_core_io_lsu_fp_stdata_bits_uop_is_br),
.io_lsu_fp_stdata_bits_uop_is_jalr (_core_io_lsu_fp_stdata_bits_uop_is_jalr),
.io_lsu_fp_stdata_bits_uop_is_jal (_core_io_lsu_fp_stdata_bits_uop_is_jal),
.io_lsu_fp_stdata_bits_uop_is_sfb (_core_io_lsu_fp_stdata_bits_uop_is_sfb),
.io_lsu_fp_stdata_bits_uop_br_mask (_core_io_lsu_fp_stdata_bits_uop_br_mask),
.io_lsu_fp_stdata_bits_uop_br_tag (_core_io_lsu_fp_stdata_bits_uop_br_tag),
.io_lsu_fp_stdata_bits_uop_ftq_idx (_core_io_lsu_fp_stdata_bits_uop_ftq_idx),
.io_lsu_fp_stdata_bits_uop_edge_inst (_core_io_lsu_fp_stdata_bits_uop_edge_inst),
.io_lsu_fp_stdata_bits_uop_pc_lob (_core_io_lsu_fp_stdata_bits_uop_pc_lob),
.io_lsu_fp_stdata_bits_uop_taken (_core_io_lsu_fp_stdata_bits_uop_taken),
.io_lsu_fp_stdata_bits_uop_imm_packed (_core_io_lsu_fp_stdata_bits_uop_imm_packed),
.io_lsu_fp_stdata_bits_uop_csr_addr (_core_io_lsu_fp_stdata_bits_uop_csr_addr),
.io_lsu_fp_stdata_bits_uop_rob_idx (_core_io_lsu_fp_stdata_bits_uop_rob_idx),
.io_lsu_fp_stdata_bits_uop_ldq_idx (_core_io_lsu_fp_stdata_bits_uop_ldq_idx),
.io_lsu_fp_stdata_bits_uop_stq_idx (_core_io_lsu_fp_stdata_bits_uop_stq_idx),
.io_lsu_fp_stdata_bits_uop_rxq_idx (_core_io_lsu_fp_stdata_bits_uop_rxq_idx),
.io_lsu_fp_stdata_bits_uop_pdst (_core_io_lsu_fp_stdata_bits_uop_pdst),
.io_lsu_fp_stdata_bits_uop_prs1 (_core_io_lsu_fp_stdata_bits_uop_prs1),
.io_lsu_fp_stdata_bits_uop_prs2 (_core_io_lsu_fp_stdata_bits_uop_prs2),
.io_lsu_fp_stdata_bits_uop_prs3 (_core_io_lsu_fp_stdata_bits_uop_prs3),
.io_lsu_fp_stdata_bits_uop_ppred (_core_io_lsu_fp_stdata_bits_uop_ppred),
.io_lsu_fp_stdata_bits_uop_prs1_busy (_core_io_lsu_fp_stdata_bits_uop_prs1_busy),
.io_lsu_fp_stdata_bits_uop_prs2_busy (_core_io_lsu_fp_stdata_bits_uop_prs2_busy),
.io_lsu_fp_stdata_bits_uop_prs3_busy (_core_io_lsu_fp_stdata_bits_uop_prs3_busy),
.io_lsu_fp_stdata_bits_uop_ppred_busy (_core_io_lsu_fp_stdata_bits_uop_ppred_busy),
.io_lsu_fp_stdata_bits_uop_stale_pdst (_core_io_lsu_fp_stdata_bits_uop_stale_pdst),
.io_lsu_fp_stdata_bits_uop_exception (_core_io_lsu_fp_stdata_bits_uop_exception),
.io_lsu_fp_stdata_bits_uop_exc_cause (_core_io_lsu_fp_stdata_bits_uop_exc_cause),
.io_lsu_fp_stdata_bits_uop_bypassable (_core_io_lsu_fp_stdata_bits_uop_bypassable),
.io_lsu_fp_stdata_bits_uop_mem_cmd (_core_io_lsu_fp_stdata_bits_uop_mem_cmd),
.io_lsu_fp_stdata_bits_uop_mem_size (_core_io_lsu_fp_stdata_bits_uop_mem_size),
.io_lsu_fp_stdata_bits_uop_mem_signed (_core_io_lsu_fp_stdata_bits_uop_mem_signed),
.io_lsu_fp_stdata_bits_uop_is_fence (_core_io_lsu_fp_stdata_bits_uop_is_fence),
.io_lsu_fp_stdata_bits_uop_is_fencei (_core_io_lsu_fp_stdata_bits_uop_is_fencei),
.io_lsu_fp_stdata_bits_uop_is_amo (_core_io_lsu_fp_stdata_bits_uop_is_amo),
.io_lsu_fp_stdata_bits_uop_uses_ldq (_core_io_lsu_fp_stdata_bits_uop_uses_ldq),
.io_lsu_fp_stdata_bits_uop_uses_stq (_core_io_lsu_fp_stdata_bits_uop_uses_stq),
.io_lsu_fp_stdata_bits_uop_is_sys_pc2epc (_core_io_lsu_fp_stdata_bits_uop_is_sys_pc2epc),
.io_lsu_fp_stdata_bits_uop_is_unique (_core_io_lsu_fp_stdata_bits_uop_is_unique),
.io_lsu_fp_stdata_bits_uop_flush_on_commit (_core_io_lsu_fp_stdata_bits_uop_flush_on_commit),
.io_lsu_fp_stdata_bits_uop_ldst_is_rs1 (_core_io_lsu_fp_stdata_bits_uop_ldst_is_rs1),
.io_lsu_fp_stdata_bits_uop_ldst (_core_io_lsu_fp_stdata_bits_uop_ldst),
.io_lsu_fp_stdata_bits_uop_lrs1 (_core_io_lsu_fp_stdata_bits_uop_lrs1),
.io_lsu_fp_stdata_bits_uop_lrs2 (_core_io_lsu_fp_stdata_bits_uop_lrs2),
.io_lsu_fp_stdata_bits_uop_lrs3 (_core_io_lsu_fp_stdata_bits_uop_lrs3),
.io_lsu_fp_stdata_bits_uop_ldst_val (_core_io_lsu_fp_stdata_bits_uop_ldst_val),
.io_lsu_fp_stdata_bits_uop_dst_rtype (_core_io_lsu_fp_stdata_bits_uop_dst_rtype),
.io_lsu_fp_stdata_bits_uop_lrs1_rtype (_core_io_lsu_fp_stdata_bits_uop_lrs1_rtype),
.io_lsu_fp_stdata_bits_uop_lrs2_rtype (_core_io_lsu_fp_stdata_bits_uop_lrs2_rtype),
.io_lsu_fp_stdata_bits_uop_frs3_en (_core_io_lsu_fp_stdata_bits_uop_frs3_en),
.io_lsu_fp_stdata_bits_uop_fp_val (_core_io_lsu_fp_stdata_bits_uop_fp_val),
.io_lsu_fp_stdata_bits_uop_fp_single (_core_io_lsu_fp_stdata_bits_uop_fp_single),
.io_lsu_fp_stdata_bits_uop_xcpt_pf_if (_core_io_lsu_fp_stdata_bits_uop_xcpt_pf_if),
.io_lsu_fp_stdata_bits_uop_xcpt_ae_if (_core_io_lsu_fp_stdata_bits_uop_xcpt_ae_if),
.io_lsu_fp_stdata_bits_uop_xcpt_ma_if (_core_io_lsu_fp_stdata_bits_uop_xcpt_ma_if),
.io_lsu_fp_stdata_bits_uop_bp_debug_if (_core_io_lsu_fp_stdata_bits_uop_bp_debug_if),
.io_lsu_fp_stdata_bits_uop_bp_xcpt_if (_core_io_lsu_fp_stdata_bits_uop_bp_xcpt_if),
.io_lsu_fp_stdata_bits_uop_debug_fsrc (_core_io_lsu_fp_stdata_bits_uop_debug_fsrc),
.io_lsu_fp_stdata_bits_uop_debug_tsrc (_core_io_lsu_fp_stdata_bits_uop_debug_tsrc),
.io_lsu_fp_stdata_bits_data (_core_io_lsu_fp_stdata_bits_data),
.io_lsu_fp_stdata_bits_predicated (_core_io_lsu_fp_stdata_bits_predicated),
.io_lsu_fp_stdata_bits_fflags_valid (_core_io_lsu_fp_stdata_bits_fflags_valid),
.io_lsu_fp_stdata_bits_fflags_bits_uop_uopc (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_uopc),
.io_lsu_fp_stdata_bits_fflags_bits_uop_inst (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_inst),
.io_lsu_fp_stdata_bits_fflags_bits_uop_debug_inst (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_debug_inst),
.io_lsu_fp_stdata_bits_fflags_bits_uop_is_rvc (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_rvc),
.io_lsu_fp_stdata_bits_fflags_bits_uop_debug_pc (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_debug_pc),
.io_lsu_fp_stdata_bits_fflags_bits_uop_iq_type (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_iq_type),
.io_lsu_fp_stdata_bits_fflags_bits_uop_fu_code (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_fu_code),
.io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_br_type (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_br_type),
.io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op1_sel (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op1_sel),
.io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op2_sel (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op2_sel),
.io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_imm_sel (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_imm_sel),
.io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op_fcn (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op_fcn),
.io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_fcn_dw (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_fcn_dw),
.io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_csr_cmd (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_csr_cmd),
.io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_load (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_load),
.io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_sta (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_sta),
.io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_std (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_std),
.io_lsu_fp_stdata_bits_fflags_bits_uop_iw_state (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_iw_state),
.io_lsu_fp_stdata_bits_fflags_bits_uop_iw_p1_poisoned (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_iw_p1_poisoned),
.io_lsu_fp_stdata_bits_fflags_bits_uop_iw_p2_poisoned (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_iw_p2_poisoned),
.io_lsu_fp_stdata_bits_fflags_bits_uop_is_br (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_br),
.io_lsu_fp_stdata_bits_fflags_bits_uop_is_jalr (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_jalr),
.io_lsu_fp_stdata_bits_fflags_bits_uop_is_jal (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_jal),
.io_lsu_fp_stdata_bits_fflags_bits_uop_is_sfb (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_sfb),
.io_lsu_fp_stdata_bits_fflags_bits_uop_br_mask (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_br_mask),
.io_lsu_fp_stdata_bits_fflags_bits_uop_br_tag (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_br_tag),
.io_lsu_fp_stdata_bits_fflags_bits_uop_ftq_idx (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ftq_idx),
.io_lsu_fp_stdata_bits_fflags_bits_uop_edge_inst (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_edge_inst),
.io_lsu_fp_stdata_bits_fflags_bits_uop_pc_lob (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_pc_lob),
.io_lsu_fp_stdata_bits_fflags_bits_uop_taken (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_taken),
.io_lsu_fp_stdata_bits_fflags_bits_uop_imm_packed (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_imm_packed),
.io_lsu_fp_stdata_bits_fflags_bits_uop_csr_addr (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_csr_addr),
.io_lsu_fp_stdata_bits_fflags_bits_uop_rob_idx (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_rob_idx),
.io_lsu_fp_stdata_bits_fflags_bits_uop_ldq_idx (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ldq_idx),
.io_lsu_fp_stdata_bits_fflags_bits_uop_stq_idx (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_stq_idx),
.io_lsu_fp_stdata_bits_fflags_bits_uop_rxq_idx (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_rxq_idx),
.io_lsu_fp_stdata_bits_fflags_bits_uop_pdst (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_pdst),
.io_lsu_fp_stdata_bits_fflags_bits_uop_prs1 (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_prs1),
.io_lsu_fp_stdata_bits_fflags_bits_uop_prs2 (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_prs2),
.io_lsu_fp_stdata_bits_fflags_bits_uop_prs3 (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_prs3),
.io_lsu_fp_stdata_bits_fflags_bits_uop_ppred (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ppred),
.io_lsu_fp_stdata_bits_fflags_bits_uop_prs1_busy (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_prs1_busy),
.io_lsu_fp_stdata_bits_fflags_bits_uop_prs2_busy (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_prs2_busy),
.io_lsu_fp_stdata_bits_fflags_bits_uop_prs3_busy (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_prs3_busy),
.io_lsu_fp_stdata_bits_fflags_bits_uop_ppred_busy (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ppred_busy),
.io_lsu_fp_stdata_bits_fflags_bits_uop_stale_pdst (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_stale_pdst),
.io_lsu_fp_stdata_bits_fflags_bits_uop_exception (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_exception),
.io_lsu_fp_stdata_bits_fflags_bits_uop_exc_cause (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_exc_cause),
.io_lsu_fp_stdata_bits_fflags_bits_uop_bypassable (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_bypassable),
.io_lsu_fp_stdata_bits_fflags_bits_uop_mem_cmd (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_mem_cmd),
.io_lsu_fp_stdata_bits_fflags_bits_uop_mem_size (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_mem_size),
.io_lsu_fp_stdata_bits_fflags_bits_uop_mem_signed (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_mem_signed),
.io_lsu_fp_stdata_bits_fflags_bits_uop_is_fence (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_fence),
.io_lsu_fp_stdata_bits_fflags_bits_uop_is_fencei (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_fencei),
.io_lsu_fp_stdata_bits_fflags_bits_uop_is_amo (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_amo),
.io_lsu_fp_stdata_bits_fflags_bits_uop_uses_ldq (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_uses_ldq),
.io_lsu_fp_stdata_bits_fflags_bits_uop_uses_stq (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_uses_stq),
.io_lsu_fp_stdata_bits_fflags_bits_uop_is_sys_pc2epc (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_sys_pc2epc),
.io_lsu_fp_stdata_bits_fflags_bits_uop_is_unique (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_unique),
.io_lsu_fp_stdata_bits_fflags_bits_uop_flush_on_commit (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_flush_on_commit),
.io_lsu_fp_stdata_bits_fflags_bits_uop_ldst_is_rs1 (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ldst_is_rs1),
.io_lsu_fp_stdata_bits_fflags_bits_uop_ldst (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ldst),
.io_lsu_fp_stdata_bits_fflags_bits_uop_lrs1 (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_lrs1),
.io_lsu_fp_stdata_bits_fflags_bits_uop_lrs2 (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_lrs2),
.io_lsu_fp_stdata_bits_fflags_bits_uop_lrs3 (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_lrs3),
.io_lsu_fp_stdata_bits_fflags_bits_uop_ldst_val (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ldst_val),
.io_lsu_fp_stdata_bits_fflags_bits_uop_dst_rtype (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_dst_rtype),
.io_lsu_fp_stdata_bits_fflags_bits_uop_lrs1_rtype (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_lrs1_rtype),
.io_lsu_fp_stdata_bits_fflags_bits_uop_lrs2_rtype (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_lrs2_rtype),
.io_lsu_fp_stdata_bits_fflags_bits_uop_frs3_en (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_frs3_en),
.io_lsu_fp_stdata_bits_fflags_bits_uop_fp_val (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_fp_val),
.io_lsu_fp_stdata_bits_fflags_bits_uop_fp_single (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_fp_single),
.io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_pf_if (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_pf_if),
.io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_ae_if (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_ae_if),
.io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_ma_if (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_ma_if),
.io_lsu_fp_stdata_bits_fflags_bits_uop_bp_debug_if (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_bp_debug_if),
.io_lsu_fp_stdata_bits_fflags_bits_uop_bp_xcpt_if (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_bp_xcpt_if),
.io_lsu_fp_stdata_bits_fflags_bits_uop_debug_fsrc (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_debug_fsrc),
.io_lsu_fp_stdata_bits_fflags_bits_uop_debug_tsrc (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_debug_tsrc),
.io_lsu_fp_stdata_bits_fflags_bits_flags (_core_io_lsu_fp_stdata_bits_fflags_bits_flags),
.io_lsu_commit_valids_0 (_core_io_lsu_commit_valids_0),
.io_lsu_commit_valids_1 (_core_io_lsu_commit_valids_1),
.io_lsu_commit_valids_2 (_core_io_lsu_commit_valids_2),
.io_lsu_commit_arch_valids_0 (_core_io_lsu_commit_arch_valids_0),
.io_lsu_commit_arch_valids_1 (_core_io_lsu_commit_arch_valids_1),
.io_lsu_commit_arch_valids_2 (_core_io_lsu_commit_arch_valids_2),
.io_lsu_commit_uops_0_uopc (_core_io_lsu_commit_uops_0_uopc),
.io_lsu_commit_uops_0_inst (_core_io_lsu_commit_uops_0_inst),
.io_lsu_commit_uops_0_debug_inst (_core_io_lsu_commit_uops_0_debug_inst),
.io_lsu_commit_uops_0_is_rvc (_core_io_lsu_commit_uops_0_is_rvc),
.io_lsu_commit_uops_0_debug_pc (_core_io_lsu_commit_uops_0_debug_pc),
.io_lsu_commit_uops_0_iq_type (_core_io_lsu_commit_uops_0_iq_type),
.io_lsu_commit_uops_0_fu_code (_core_io_lsu_commit_uops_0_fu_code),
.io_lsu_commit_uops_0_ctrl_br_type (_core_io_lsu_commit_uops_0_ctrl_br_type),
.io_lsu_commit_uops_0_ctrl_op1_sel (_core_io_lsu_commit_uops_0_ctrl_op1_sel),
.io_lsu_commit_uops_0_ctrl_op2_sel (_core_io_lsu_commit_uops_0_ctrl_op2_sel),
.io_lsu_commit_uops_0_ctrl_imm_sel (_core_io_lsu_commit_uops_0_ctrl_imm_sel),
.io_lsu_commit_uops_0_ctrl_op_fcn (_core_io_lsu_commit_uops_0_ctrl_op_fcn),
.io_lsu_commit_uops_0_ctrl_fcn_dw (_core_io_lsu_commit_uops_0_ctrl_fcn_dw),
.io_lsu_commit_uops_0_ctrl_csr_cmd (_core_io_lsu_commit_uops_0_ctrl_csr_cmd),
.io_lsu_commit_uops_0_ctrl_is_load (_core_io_lsu_commit_uops_0_ctrl_is_load),
.io_lsu_commit_uops_0_ctrl_is_sta (_core_io_lsu_commit_uops_0_ctrl_is_sta),
.io_lsu_commit_uops_0_ctrl_is_std (_core_io_lsu_commit_uops_0_ctrl_is_std),
.io_lsu_commit_uops_0_iw_state (_core_io_lsu_commit_uops_0_iw_state),
.io_lsu_commit_uops_0_iw_p1_poisoned (_core_io_lsu_commit_uops_0_iw_p1_poisoned),
.io_lsu_commit_uops_0_iw_p2_poisoned (_core_io_lsu_commit_uops_0_iw_p2_poisoned),
.io_lsu_commit_uops_0_is_br (_core_io_lsu_commit_uops_0_is_br),
.io_lsu_commit_uops_0_is_jalr (_core_io_lsu_commit_uops_0_is_jalr),
.io_lsu_commit_uops_0_is_jal (_core_io_lsu_commit_uops_0_is_jal),
.io_lsu_commit_uops_0_is_sfb (_core_io_lsu_commit_uops_0_is_sfb),
.io_lsu_commit_uops_0_br_mask (_core_io_lsu_commit_uops_0_br_mask),
.io_lsu_commit_uops_0_br_tag (_core_io_lsu_commit_uops_0_br_tag),
.io_lsu_commit_uops_0_ftq_idx (_core_io_lsu_commit_uops_0_ftq_idx),
.io_lsu_commit_uops_0_edge_inst (_core_io_lsu_commit_uops_0_edge_inst),
.io_lsu_commit_uops_0_pc_lob (_core_io_lsu_commit_uops_0_pc_lob),
.io_lsu_commit_uops_0_taken (_core_io_lsu_commit_uops_0_taken),
.io_lsu_commit_uops_0_imm_packed (_core_io_lsu_commit_uops_0_imm_packed),
.io_lsu_commit_uops_0_csr_addr (_core_io_lsu_commit_uops_0_csr_addr),
.io_lsu_commit_uops_0_rob_idx (_core_io_lsu_commit_uops_0_rob_idx),
.io_lsu_commit_uops_0_ldq_idx (_core_io_lsu_commit_uops_0_ldq_idx),
.io_lsu_commit_uops_0_stq_idx (_core_io_lsu_commit_uops_0_stq_idx),
.io_lsu_commit_uops_0_rxq_idx (_core_io_lsu_commit_uops_0_rxq_idx),
.io_lsu_commit_uops_0_pdst (_core_io_lsu_commit_uops_0_pdst),
.io_lsu_commit_uops_0_prs1 (_core_io_lsu_commit_uops_0_prs1),
.io_lsu_commit_uops_0_prs2 (_core_io_lsu_commit_uops_0_prs2),
.io_lsu_commit_uops_0_prs3 (_core_io_lsu_commit_uops_0_prs3),
.io_lsu_commit_uops_0_ppred (_core_io_lsu_commit_uops_0_ppred),
.io_lsu_commit_uops_0_prs1_busy (_core_io_lsu_commit_uops_0_prs1_busy),
.io_lsu_commit_uops_0_prs2_busy (_core_io_lsu_commit_uops_0_prs2_busy),
.io_lsu_commit_uops_0_prs3_busy (_core_io_lsu_commit_uops_0_prs3_busy),
.io_lsu_commit_uops_0_ppred_busy (_core_io_lsu_commit_uops_0_ppred_busy),
.io_lsu_commit_uops_0_stale_pdst (_core_io_lsu_commit_uops_0_stale_pdst),
.io_lsu_commit_uops_0_exception (_core_io_lsu_commit_uops_0_exception),
.io_lsu_commit_uops_0_exc_cause (_core_io_lsu_commit_uops_0_exc_cause),
.io_lsu_commit_uops_0_bypassable (_core_io_lsu_commit_uops_0_bypassable),
.io_lsu_commit_uops_0_mem_cmd (_core_io_lsu_commit_uops_0_mem_cmd),
.io_lsu_commit_uops_0_mem_size (_core_io_lsu_commit_uops_0_mem_size),
.io_lsu_commit_uops_0_mem_signed (_core_io_lsu_commit_uops_0_mem_signed),
.io_lsu_commit_uops_0_is_fence (_core_io_lsu_commit_uops_0_is_fence),
.io_lsu_commit_uops_0_is_fencei (_core_io_lsu_commit_uops_0_is_fencei),
.io_lsu_commit_uops_0_is_amo (_core_io_lsu_commit_uops_0_is_amo),
.io_lsu_commit_uops_0_uses_ldq (_core_io_lsu_commit_uops_0_uses_ldq),
.io_lsu_commit_uops_0_uses_stq (_core_io_lsu_commit_uops_0_uses_stq),
.io_lsu_commit_uops_0_is_sys_pc2epc (_core_io_lsu_commit_uops_0_is_sys_pc2epc),
.io_lsu_commit_uops_0_is_unique (_core_io_lsu_commit_uops_0_is_unique),
.io_lsu_commit_uops_0_flush_on_commit (_core_io_lsu_commit_uops_0_flush_on_commit),
.io_lsu_commit_uops_0_ldst_is_rs1 (_core_io_lsu_commit_uops_0_ldst_is_rs1),
.io_lsu_commit_uops_0_ldst (_core_io_lsu_commit_uops_0_ldst),
.io_lsu_commit_uops_0_lrs1 (_core_io_lsu_commit_uops_0_lrs1),
.io_lsu_commit_uops_0_lrs2 (_core_io_lsu_commit_uops_0_lrs2),
.io_lsu_commit_uops_0_lrs3 (_core_io_lsu_commit_uops_0_lrs3),
.io_lsu_commit_uops_0_ldst_val (_core_io_lsu_commit_uops_0_ldst_val),
.io_lsu_commit_uops_0_dst_rtype (_core_io_lsu_commit_uops_0_dst_rtype),
.io_lsu_commit_uops_0_lrs1_rtype (_core_io_lsu_commit_uops_0_lrs1_rtype),
.io_lsu_commit_uops_0_lrs2_rtype (_core_io_lsu_commit_uops_0_lrs2_rtype),
.io_lsu_commit_uops_0_frs3_en (_core_io_lsu_commit_uops_0_frs3_en),
.io_lsu_commit_uops_0_fp_val (_core_io_lsu_commit_uops_0_fp_val),
.io_lsu_commit_uops_0_fp_single (_core_io_lsu_commit_uops_0_fp_single),
.io_lsu_commit_uops_0_xcpt_pf_if (_core_io_lsu_commit_uops_0_xcpt_pf_if),
.io_lsu_commit_uops_0_xcpt_ae_if (_core_io_lsu_commit_uops_0_xcpt_ae_if),
.io_lsu_commit_uops_0_xcpt_ma_if (_core_io_lsu_commit_uops_0_xcpt_ma_if),
.io_lsu_commit_uops_0_bp_debug_if (_core_io_lsu_commit_uops_0_bp_debug_if),
.io_lsu_commit_uops_0_bp_xcpt_if (_core_io_lsu_commit_uops_0_bp_xcpt_if),
.io_lsu_commit_uops_0_debug_fsrc (_core_io_lsu_commit_uops_0_debug_fsrc),
.io_lsu_commit_uops_0_debug_tsrc (_core_io_lsu_commit_uops_0_debug_tsrc),
.io_lsu_commit_uops_1_uopc (_core_io_lsu_commit_uops_1_uopc),
.io_lsu_commit_uops_1_inst (_core_io_lsu_commit_uops_1_inst),
.io_lsu_commit_uops_1_debug_inst (_core_io_lsu_commit_uops_1_debug_inst),
.io_lsu_commit_uops_1_is_rvc (_core_io_lsu_commit_uops_1_is_rvc),
.io_lsu_commit_uops_1_debug_pc (_core_io_lsu_commit_uops_1_debug_pc),
.io_lsu_commit_uops_1_iq_type (_core_io_lsu_commit_uops_1_iq_type),
.io_lsu_commit_uops_1_fu_code (_core_io_lsu_commit_uops_1_fu_code),
.io_lsu_commit_uops_1_ctrl_br_type (_core_io_lsu_commit_uops_1_ctrl_br_type),
.io_lsu_commit_uops_1_ctrl_op1_sel (_core_io_lsu_commit_uops_1_ctrl_op1_sel),
.io_lsu_commit_uops_1_ctrl_op2_sel (_core_io_lsu_commit_uops_1_ctrl_op2_sel),
.io_lsu_commit_uops_1_ctrl_imm_sel (_core_io_lsu_commit_uops_1_ctrl_imm_sel),
.io_lsu_commit_uops_1_ctrl_op_fcn (_core_io_lsu_commit_uops_1_ctrl_op_fcn),
.io_lsu_commit_uops_1_ctrl_fcn_dw (_core_io_lsu_commit_uops_1_ctrl_fcn_dw),
.io_lsu_commit_uops_1_ctrl_csr_cmd (_core_io_lsu_commit_uops_1_ctrl_csr_cmd),
.io_lsu_commit_uops_1_ctrl_is_load (_core_io_lsu_commit_uops_1_ctrl_is_load),
.io_lsu_commit_uops_1_ctrl_is_sta (_core_io_lsu_commit_uops_1_ctrl_is_sta),
.io_lsu_commit_uops_1_ctrl_is_std (_core_io_lsu_commit_uops_1_ctrl_is_std),
.io_lsu_commit_uops_1_iw_state (_core_io_lsu_commit_uops_1_iw_state),
.io_lsu_commit_uops_1_iw_p1_poisoned (_core_io_lsu_commit_uops_1_iw_p1_poisoned),
.io_lsu_commit_uops_1_iw_p2_poisoned (_core_io_lsu_commit_uops_1_iw_p2_poisoned),
.io_lsu_commit_uops_1_is_br (_core_io_lsu_commit_uops_1_is_br),
.io_lsu_commit_uops_1_is_jalr (_core_io_lsu_commit_uops_1_is_jalr),
.io_lsu_commit_uops_1_is_jal (_core_io_lsu_commit_uops_1_is_jal),
.io_lsu_commit_uops_1_is_sfb (_core_io_lsu_commit_uops_1_is_sfb),
.io_lsu_commit_uops_1_br_mask (_core_io_lsu_commit_uops_1_br_mask),
.io_lsu_commit_uops_1_br_tag (_core_io_lsu_commit_uops_1_br_tag),
.io_lsu_commit_uops_1_ftq_idx (_core_io_lsu_commit_uops_1_ftq_idx),
.io_lsu_commit_uops_1_edge_inst (_core_io_lsu_commit_uops_1_edge_inst),
.io_lsu_commit_uops_1_pc_lob (_core_io_lsu_commit_uops_1_pc_lob),
.io_lsu_commit_uops_1_taken (_core_io_lsu_commit_uops_1_taken),
.io_lsu_commit_uops_1_imm_packed (_core_io_lsu_commit_uops_1_imm_packed),
.io_lsu_commit_uops_1_csr_addr (_core_io_lsu_commit_uops_1_csr_addr),
.io_lsu_commit_uops_1_rob_idx (_core_io_lsu_commit_uops_1_rob_idx),
.io_lsu_commit_uops_1_ldq_idx (_core_io_lsu_commit_uops_1_ldq_idx),
.io_lsu_commit_uops_1_stq_idx (_core_io_lsu_commit_uops_1_stq_idx),
.io_lsu_commit_uops_1_rxq_idx (_core_io_lsu_commit_uops_1_rxq_idx),
.io_lsu_commit_uops_1_pdst (_core_io_lsu_commit_uops_1_pdst),
.io_lsu_commit_uops_1_prs1 (_core_io_lsu_commit_uops_1_prs1),
.io_lsu_commit_uops_1_prs2 (_core_io_lsu_commit_uops_1_prs2),
.io_lsu_commit_uops_1_prs3 (_core_io_lsu_commit_uops_1_prs3),
.io_lsu_commit_uops_1_ppred (_core_io_lsu_commit_uops_1_ppred),
.io_lsu_commit_uops_1_prs1_busy (_core_io_lsu_commit_uops_1_prs1_busy),
.io_lsu_commit_uops_1_prs2_busy (_core_io_lsu_commit_uops_1_prs2_busy),
.io_lsu_commit_uops_1_prs3_busy (_core_io_lsu_commit_uops_1_prs3_busy),
.io_lsu_commit_uops_1_ppred_busy (_core_io_lsu_commit_uops_1_ppred_busy),
.io_lsu_commit_uops_1_stale_pdst (_core_io_lsu_commit_uops_1_stale_pdst),
.io_lsu_commit_uops_1_exception (_core_io_lsu_commit_uops_1_exception),
.io_lsu_commit_uops_1_exc_cause (_core_io_lsu_commit_uops_1_exc_cause),
.io_lsu_commit_uops_1_bypassable (_core_io_lsu_commit_uops_1_bypassable),
.io_lsu_commit_uops_1_mem_cmd (_core_io_lsu_commit_uops_1_mem_cmd),
.io_lsu_commit_uops_1_mem_size (_core_io_lsu_commit_uops_1_mem_size),
.io_lsu_commit_uops_1_mem_signed (_core_io_lsu_commit_uops_1_mem_signed),
.io_lsu_commit_uops_1_is_fence (_core_io_lsu_commit_uops_1_is_fence),
.io_lsu_commit_uops_1_is_fencei (_core_io_lsu_commit_uops_1_is_fencei),
.io_lsu_commit_uops_1_is_amo (_core_io_lsu_commit_uops_1_is_amo),
.io_lsu_commit_uops_1_uses_ldq (_core_io_lsu_commit_uops_1_uses_ldq),
.io_lsu_commit_uops_1_uses_stq (_core_io_lsu_commit_uops_1_uses_stq),
.io_lsu_commit_uops_1_is_sys_pc2epc (_core_io_lsu_commit_uops_1_is_sys_pc2epc),
.io_lsu_commit_uops_1_is_unique (_core_io_lsu_commit_uops_1_is_unique),
.io_lsu_commit_uops_1_flush_on_commit (_core_io_lsu_commit_uops_1_flush_on_commit),
.io_lsu_commit_uops_1_ldst_is_rs1 (_core_io_lsu_commit_uops_1_ldst_is_rs1),
.io_lsu_commit_uops_1_ldst (_core_io_lsu_commit_uops_1_ldst),
.io_lsu_commit_uops_1_lrs1 (_core_io_lsu_commit_uops_1_lrs1),
.io_lsu_commit_uops_1_lrs2 (_core_io_lsu_commit_uops_1_lrs2),
.io_lsu_commit_uops_1_lrs3 (_core_io_lsu_commit_uops_1_lrs3),
.io_lsu_commit_uops_1_ldst_val (_core_io_lsu_commit_uops_1_ldst_val),
.io_lsu_commit_uops_1_dst_rtype (_core_io_lsu_commit_uops_1_dst_rtype),
.io_lsu_commit_uops_1_lrs1_rtype (_core_io_lsu_commit_uops_1_lrs1_rtype),
.io_lsu_commit_uops_1_lrs2_rtype (_core_io_lsu_commit_uops_1_lrs2_rtype),
.io_lsu_commit_uops_1_frs3_en (_core_io_lsu_commit_uops_1_frs3_en),
.io_lsu_commit_uops_1_fp_val (_core_io_lsu_commit_uops_1_fp_val),
.io_lsu_commit_uops_1_fp_single (_core_io_lsu_commit_uops_1_fp_single),
.io_lsu_commit_uops_1_xcpt_pf_if (_core_io_lsu_commit_uops_1_xcpt_pf_if),
.io_lsu_commit_uops_1_xcpt_ae_if (_core_io_lsu_commit_uops_1_xcpt_ae_if),
.io_lsu_commit_uops_1_xcpt_ma_if (_core_io_lsu_commit_uops_1_xcpt_ma_if),
.io_lsu_commit_uops_1_bp_debug_if (_core_io_lsu_commit_uops_1_bp_debug_if),
.io_lsu_commit_uops_1_bp_xcpt_if (_core_io_lsu_commit_uops_1_bp_xcpt_if),
.io_lsu_commit_uops_1_debug_fsrc (_core_io_lsu_commit_uops_1_debug_fsrc),
.io_lsu_commit_uops_1_debug_tsrc (_core_io_lsu_commit_uops_1_debug_tsrc),
.io_lsu_commit_uops_2_uopc (_core_io_lsu_commit_uops_2_uopc),
.io_lsu_commit_uops_2_inst (_core_io_lsu_commit_uops_2_inst),
.io_lsu_commit_uops_2_debug_inst (_core_io_lsu_commit_uops_2_debug_inst),
.io_lsu_commit_uops_2_is_rvc (_core_io_lsu_commit_uops_2_is_rvc),
.io_lsu_commit_uops_2_debug_pc (_core_io_lsu_commit_uops_2_debug_pc),
.io_lsu_commit_uops_2_iq_type (_core_io_lsu_commit_uops_2_iq_type),
.io_lsu_commit_uops_2_fu_code (_core_io_lsu_commit_uops_2_fu_code),
.io_lsu_commit_uops_2_ctrl_br_type (_core_io_lsu_commit_uops_2_ctrl_br_type),
.io_lsu_commit_uops_2_ctrl_op1_sel (_core_io_lsu_commit_uops_2_ctrl_op1_sel),
.io_lsu_commit_uops_2_ctrl_op2_sel (_core_io_lsu_commit_uops_2_ctrl_op2_sel),
.io_lsu_commit_uops_2_ctrl_imm_sel (_core_io_lsu_commit_uops_2_ctrl_imm_sel),
.io_lsu_commit_uops_2_ctrl_op_fcn (_core_io_lsu_commit_uops_2_ctrl_op_fcn),
.io_lsu_commit_uops_2_ctrl_fcn_dw (_core_io_lsu_commit_uops_2_ctrl_fcn_dw),
.io_lsu_commit_uops_2_ctrl_csr_cmd (_core_io_lsu_commit_uops_2_ctrl_csr_cmd),
.io_lsu_commit_uops_2_ctrl_is_load (_core_io_lsu_commit_uops_2_ctrl_is_load),
.io_lsu_commit_uops_2_ctrl_is_sta (_core_io_lsu_commit_uops_2_ctrl_is_sta),
.io_lsu_commit_uops_2_ctrl_is_std (_core_io_lsu_commit_uops_2_ctrl_is_std),
.io_lsu_commit_uops_2_iw_state (_core_io_lsu_commit_uops_2_iw_state),
.io_lsu_commit_uops_2_iw_p1_poisoned (_core_io_lsu_commit_uops_2_iw_p1_poisoned),
.io_lsu_commit_uops_2_iw_p2_poisoned (_core_io_lsu_commit_uops_2_iw_p2_poisoned),
.io_lsu_commit_uops_2_is_br (_core_io_lsu_commit_uops_2_is_br),
.io_lsu_commit_uops_2_is_jalr (_core_io_lsu_commit_uops_2_is_jalr),
.io_lsu_commit_uops_2_is_jal (_core_io_lsu_commit_uops_2_is_jal),
.io_lsu_commit_uops_2_is_sfb (_core_io_lsu_commit_uops_2_is_sfb),
.io_lsu_commit_uops_2_br_mask (_core_io_lsu_commit_uops_2_br_mask),
.io_lsu_commit_uops_2_br_tag (_core_io_lsu_commit_uops_2_br_tag),
.io_lsu_commit_uops_2_ftq_idx (_core_io_lsu_commit_uops_2_ftq_idx),
.io_lsu_commit_uops_2_edge_inst (_core_io_lsu_commit_uops_2_edge_inst),
.io_lsu_commit_uops_2_pc_lob (_core_io_lsu_commit_uops_2_pc_lob),
.io_lsu_commit_uops_2_taken (_core_io_lsu_commit_uops_2_taken),
.io_lsu_commit_uops_2_imm_packed (_core_io_lsu_commit_uops_2_imm_packed),
.io_lsu_commit_uops_2_csr_addr (_core_io_lsu_commit_uops_2_csr_addr),
.io_lsu_commit_uops_2_rob_idx (_core_io_lsu_commit_uops_2_rob_idx),
.io_lsu_commit_uops_2_ldq_idx (_core_io_lsu_commit_uops_2_ldq_idx),
.io_lsu_commit_uops_2_stq_idx (_core_io_lsu_commit_uops_2_stq_idx),
.io_lsu_commit_uops_2_rxq_idx (_core_io_lsu_commit_uops_2_rxq_idx),
.io_lsu_commit_uops_2_pdst (_core_io_lsu_commit_uops_2_pdst),
.io_lsu_commit_uops_2_prs1 (_core_io_lsu_commit_uops_2_prs1),
.io_lsu_commit_uops_2_prs2 (_core_io_lsu_commit_uops_2_prs2),
.io_lsu_commit_uops_2_prs3 (_core_io_lsu_commit_uops_2_prs3),
.io_lsu_commit_uops_2_ppred (_core_io_lsu_commit_uops_2_ppred),
.io_lsu_commit_uops_2_prs1_busy (_core_io_lsu_commit_uops_2_prs1_busy),
.io_lsu_commit_uops_2_prs2_busy (_core_io_lsu_commit_uops_2_prs2_busy),
.io_lsu_commit_uops_2_prs3_busy (_core_io_lsu_commit_uops_2_prs3_busy),
.io_lsu_commit_uops_2_ppred_busy (_core_io_lsu_commit_uops_2_ppred_busy),
.io_lsu_commit_uops_2_stale_pdst (_core_io_lsu_commit_uops_2_stale_pdst),
.io_lsu_commit_uops_2_exception (_core_io_lsu_commit_uops_2_exception),
.io_lsu_commit_uops_2_exc_cause (_core_io_lsu_commit_uops_2_exc_cause),
.io_lsu_commit_uops_2_bypassable (_core_io_lsu_commit_uops_2_bypassable),
.io_lsu_commit_uops_2_mem_cmd (_core_io_lsu_commit_uops_2_mem_cmd),
.io_lsu_commit_uops_2_mem_size (_core_io_lsu_commit_uops_2_mem_size),
.io_lsu_commit_uops_2_mem_signed (_core_io_lsu_commit_uops_2_mem_signed),
.io_lsu_commit_uops_2_is_fence (_core_io_lsu_commit_uops_2_is_fence),
.io_lsu_commit_uops_2_is_fencei (_core_io_lsu_commit_uops_2_is_fencei),
.io_lsu_commit_uops_2_is_amo (_core_io_lsu_commit_uops_2_is_amo),
.io_lsu_commit_uops_2_uses_ldq (_core_io_lsu_commit_uops_2_uses_ldq),
.io_lsu_commit_uops_2_uses_stq (_core_io_lsu_commit_uops_2_uses_stq),
.io_lsu_commit_uops_2_is_sys_pc2epc (_core_io_lsu_commit_uops_2_is_sys_pc2epc),
.io_lsu_commit_uops_2_is_unique (_core_io_lsu_commit_uops_2_is_unique),
.io_lsu_commit_uops_2_flush_on_commit (_core_io_lsu_commit_uops_2_flush_on_commit),
.io_lsu_commit_uops_2_ldst_is_rs1 (_core_io_lsu_commit_uops_2_ldst_is_rs1),
.io_lsu_commit_uops_2_ldst (_core_io_lsu_commit_uops_2_ldst),
.io_lsu_commit_uops_2_lrs1 (_core_io_lsu_commit_uops_2_lrs1),
.io_lsu_commit_uops_2_lrs2 (_core_io_lsu_commit_uops_2_lrs2),
.io_lsu_commit_uops_2_lrs3 (_core_io_lsu_commit_uops_2_lrs3),
.io_lsu_commit_uops_2_ldst_val (_core_io_lsu_commit_uops_2_ldst_val),
.io_lsu_commit_uops_2_dst_rtype (_core_io_lsu_commit_uops_2_dst_rtype),
.io_lsu_commit_uops_2_lrs1_rtype (_core_io_lsu_commit_uops_2_lrs1_rtype),
.io_lsu_commit_uops_2_lrs2_rtype (_core_io_lsu_commit_uops_2_lrs2_rtype),
.io_lsu_commit_uops_2_frs3_en (_core_io_lsu_commit_uops_2_frs3_en),
.io_lsu_commit_uops_2_fp_val (_core_io_lsu_commit_uops_2_fp_val),
.io_lsu_commit_uops_2_fp_single (_core_io_lsu_commit_uops_2_fp_single),
.io_lsu_commit_uops_2_xcpt_pf_if (_core_io_lsu_commit_uops_2_xcpt_pf_if),
.io_lsu_commit_uops_2_xcpt_ae_if (_core_io_lsu_commit_uops_2_xcpt_ae_if),
.io_lsu_commit_uops_2_xcpt_ma_if (_core_io_lsu_commit_uops_2_xcpt_ma_if),
.io_lsu_commit_uops_2_bp_debug_if (_core_io_lsu_commit_uops_2_bp_debug_if),
.io_lsu_commit_uops_2_bp_xcpt_if (_core_io_lsu_commit_uops_2_bp_xcpt_if),
.io_lsu_commit_uops_2_debug_fsrc (_core_io_lsu_commit_uops_2_debug_fsrc),
.io_lsu_commit_uops_2_debug_tsrc (_core_io_lsu_commit_uops_2_debug_tsrc),
.io_lsu_commit_fflags_valid (_core_io_lsu_commit_fflags_valid),
.io_lsu_commit_fflags_bits (_core_io_lsu_commit_fflags_bits),
.io_lsu_commit_debug_insts_0 (_core_io_lsu_commit_debug_insts_0),
.io_lsu_commit_debug_insts_1 (_core_io_lsu_commit_debug_insts_1),
.io_lsu_commit_debug_insts_2 (_core_io_lsu_commit_debug_insts_2),
.io_lsu_commit_rbk_valids_0 (_core_io_lsu_commit_rbk_valids_0),
.io_lsu_commit_rbk_valids_1 (_core_io_lsu_commit_rbk_valids_1),
.io_lsu_commit_rbk_valids_2 (_core_io_lsu_commit_rbk_valids_2),
.io_lsu_commit_rollback (_core_io_lsu_commit_rollback),
.io_lsu_commit_debug_wdata_0 (_core_io_lsu_commit_debug_wdata_0),
.io_lsu_commit_debug_wdata_1 (_core_io_lsu_commit_debug_wdata_1),
.io_lsu_commit_debug_wdata_2 (_core_io_lsu_commit_debug_wdata_2),
.io_lsu_commit_load_at_rob_head (_core_io_lsu_commit_load_at_rob_head),
.io_lsu_clr_bsy_0_valid (_lsu_io_core_clr_bsy_0_valid), // @[tile.scala:160:20]
.io_lsu_clr_bsy_0_bits (_lsu_io_core_clr_bsy_0_bits), // @[tile.scala:160:20]
.io_lsu_clr_bsy_1_valid (_lsu_io_core_clr_bsy_1_valid), // @[tile.scala:160:20]
.io_lsu_clr_bsy_1_bits (_lsu_io_core_clr_bsy_1_bits), // @[tile.scala:160:20]
.io_lsu_clr_unsafe_0_bits (_lsu_io_core_clr_unsafe_0_bits), // @[tile.scala:160:20]
.io_lsu_fence_dmem (_core_io_lsu_fence_dmem),
.io_lsu_spec_ld_wakeup_0_valid (_lsu_io_core_spec_ld_wakeup_0_valid), // @[tile.scala:160:20]
.io_lsu_spec_ld_wakeup_0_bits (_lsu_io_core_spec_ld_wakeup_0_bits), // @[tile.scala:160:20]
.io_lsu_ld_miss (_lsu_io_core_ld_miss), // @[tile.scala:160:20]
.io_lsu_brupdate_b1_resolve_mask (_core_io_lsu_brupdate_b1_resolve_mask),
.io_lsu_brupdate_b1_mispredict_mask (_core_io_lsu_brupdate_b1_mispredict_mask),
.io_lsu_brupdate_b2_uop_uopc (_core_io_lsu_brupdate_b2_uop_uopc),
.io_lsu_brupdate_b2_uop_inst (_core_io_lsu_brupdate_b2_uop_inst),
.io_lsu_brupdate_b2_uop_debug_inst (_core_io_lsu_brupdate_b2_uop_debug_inst),
.io_lsu_brupdate_b2_uop_is_rvc (_core_io_lsu_brupdate_b2_uop_is_rvc),
.io_lsu_brupdate_b2_uop_debug_pc (_core_io_lsu_brupdate_b2_uop_debug_pc),
.io_lsu_brupdate_b2_uop_iq_type (_core_io_lsu_brupdate_b2_uop_iq_type),
.io_lsu_brupdate_b2_uop_fu_code (_core_io_lsu_brupdate_b2_uop_fu_code),
.io_lsu_brupdate_b2_uop_ctrl_br_type (_core_io_lsu_brupdate_b2_uop_ctrl_br_type),
.io_lsu_brupdate_b2_uop_ctrl_op1_sel (_core_io_lsu_brupdate_b2_uop_ctrl_op1_sel),
.io_lsu_brupdate_b2_uop_ctrl_op2_sel (_core_io_lsu_brupdate_b2_uop_ctrl_op2_sel),
.io_lsu_brupdate_b2_uop_ctrl_imm_sel (_core_io_lsu_brupdate_b2_uop_ctrl_imm_sel),
.io_lsu_brupdate_b2_uop_ctrl_op_fcn (_core_io_lsu_brupdate_b2_uop_ctrl_op_fcn),
.io_lsu_brupdate_b2_uop_ctrl_fcn_dw (_core_io_lsu_brupdate_b2_uop_ctrl_fcn_dw),
.io_lsu_brupdate_b2_uop_ctrl_csr_cmd (_core_io_lsu_brupdate_b2_uop_ctrl_csr_cmd),
.io_lsu_brupdate_b2_uop_ctrl_is_load (_core_io_lsu_brupdate_b2_uop_ctrl_is_load),
.io_lsu_brupdate_b2_uop_ctrl_is_sta (_core_io_lsu_brupdate_b2_uop_ctrl_is_sta),
.io_lsu_brupdate_b2_uop_ctrl_is_std (_core_io_lsu_brupdate_b2_uop_ctrl_is_std),
.io_lsu_brupdate_b2_uop_iw_state (_core_io_lsu_brupdate_b2_uop_iw_state),
.io_lsu_brupdate_b2_uop_iw_p1_poisoned (_core_io_lsu_brupdate_b2_uop_iw_p1_poisoned),
.io_lsu_brupdate_b2_uop_iw_p2_poisoned (_core_io_lsu_brupdate_b2_uop_iw_p2_poisoned),
.io_lsu_brupdate_b2_uop_is_br (_core_io_lsu_brupdate_b2_uop_is_br),
.io_lsu_brupdate_b2_uop_is_jalr (_core_io_lsu_brupdate_b2_uop_is_jalr),
.io_lsu_brupdate_b2_uop_is_jal (_core_io_lsu_brupdate_b2_uop_is_jal),
.io_lsu_brupdate_b2_uop_is_sfb (_core_io_lsu_brupdate_b2_uop_is_sfb),
.io_lsu_brupdate_b2_uop_br_mask (_core_io_lsu_brupdate_b2_uop_br_mask),
.io_lsu_brupdate_b2_uop_br_tag (_core_io_lsu_brupdate_b2_uop_br_tag),
.io_lsu_brupdate_b2_uop_ftq_idx (_core_io_lsu_brupdate_b2_uop_ftq_idx),
.io_lsu_brupdate_b2_uop_edge_inst (_core_io_lsu_brupdate_b2_uop_edge_inst),
.io_lsu_brupdate_b2_uop_pc_lob (_core_io_lsu_brupdate_b2_uop_pc_lob),
.io_lsu_brupdate_b2_uop_taken (_core_io_lsu_brupdate_b2_uop_taken),
.io_lsu_brupdate_b2_uop_imm_packed (_core_io_lsu_brupdate_b2_uop_imm_packed),
.io_lsu_brupdate_b2_uop_csr_addr (_core_io_lsu_brupdate_b2_uop_csr_addr),
.io_lsu_brupdate_b2_uop_rob_idx (_core_io_lsu_brupdate_b2_uop_rob_idx),
.io_lsu_brupdate_b2_uop_ldq_idx (_core_io_lsu_brupdate_b2_uop_ldq_idx),
.io_lsu_brupdate_b2_uop_stq_idx (_core_io_lsu_brupdate_b2_uop_stq_idx),
.io_lsu_brupdate_b2_uop_rxq_idx (_core_io_lsu_brupdate_b2_uop_rxq_idx),
.io_lsu_brupdate_b2_uop_pdst (_core_io_lsu_brupdate_b2_uop_pdst),
.io_lsu_brupdate_b2_uop_prs1 (_core_io_lsu_brupdate_b2_uop_prs1),
.io_lsu_brupdate_b2_uop_prs2 (_core_io_lsu_brupdate_b2_uop_prs2),
.io_lsu_brupdate_b2_uop_prs3 (_core_io_lsu_brupdate_b2_uop_prs3),
.io_lsu_brupdate_b2_uop_ppred (_core_io_lsu_brupdate_b2_uop_ppred),
.io_lsu_brupdate_b2_uop_prs1_busy (_core_io_lsu_brupdate_b2_uop_prs1_busy),
.io_lsu_brupdate_b2_uop_prs2_busy (_core_io_lsu_brupdate_b2_uop_prs2_busy),
.io_lsu_brupdate_b2_uop_prs3_busy (_core_io_lsu_brupdate_b2_uop_prs3_busy),
.io_lsu_brupdate_b2_uop_ppred_busy (_core_io_lsu_brupdate_b2_uop_ppred_busy),
.io_lsu_brupdate_b2_uop_stale_pdst (_core_io_lsu_brupdate_b2_uop_stale_pdst),
.io_lsu_brupdate_b2_uop_exception (_core_io_lsu_brupdate_b2_uop_exception),
.io_lsu_brupdate_b2_uop_exc_cause (_core_io_lsu_brupdate_b2_uop_exc_cause),
.io_lsu_brupdate_b2_uop_bypassable (_core_io_lsu_brupdate_b2_uop_bypassable),
.io_lsu_brupdate_b2_uop_mem_cmd (_core_io_lsu_brupdate_b2_uop_mem_cmd),
.io_lsu_brupdate_b2_uop_mem_size (_core_io_lsu_brupdate_b2_uop_mem_size),
.io_lsu_brupdate_b2_uop_mem_signed (_core_io_lsu_brupdate_b2_uop_mem_signed),
.io_lsu_brupdate_b2_uop_is_fence (_core_io_lsu_brupdate_b2_uop_is_fence),
.io_lsu_brupdate_b2_uop_is_fencei (_core_io_lsu_brupdate_b2_uop_is_fencei),
.io_lsu_brupdate_b2_uop_is_amo (_core_io_lsu_brupdate_b2_uop_is_amo),
.io_lsu_brupdate_b2_uop_uses_ldq (_core_io_lsu_brupdate_b2_uop_uses_ldq),
.io_lsu_brupdate_b2_uop_uses_stq (_core_io_lsu_brupdate_b2_uop_uses_stq),
.io_lsu_brupdate_b2_uop_is_sys_pc2epc (_core_io_lsu_brupdate_b2_uop_is_sys_pc2epc),
.io_lsu_brupdate_b2_uop_is_unique (_core_io_lsu_brupdate_b2_uop_is_unique),
.io_lsu_brupdate_b2_uop_flush_on_commit (_core_io_lsu_brupdate_b2_uop_flush_on_commit),
.io_lsu_brupdate_b2_uop_ldst_is_rs1 (_core_io_lsu_brupdate_b2_uop_ldst_is_rs1),
.io_lsu_brupdate_b2_uop_ldst (_core_io_lsu_brupdate_b2_uop_ldst),
.io_lsu_brupdate_b2_uop_lrs1 (_core_io_lsu_brupdate_b2_uop_lrs1),
.io_lsu_brupdate_b2_uop_lrs2 (_core_io_lsu_brupdate_b2_uop_lrs2),
.io_lsu_brupdate_b2_uop_lrs3 (_core_io_lsu_brupdate_b2_uop_lrs3),
.io_lsu_brupdate_b2_uop_ldst_val (_core_io_lsu_brupdate_b2_uop_ldst_val),
.io_lsu_brupdate_b2_uop_dst_rtype (_core_io_lsu_brupdate_b2_uop_dst_rtype),
.io_lsu_brupdate_b2_uop_lrs1_rtype (_core_io_lsu_brupdate_b2_uop_lrs1_rtype),
.io_lsu_brupdate_b2_uop_lrs2_rtype (_core_io_lsu_brupdate_b2_uop_lrs2_rtype),
.io_lsu_brupdate_b2_uop_frs3_en (_core_io_lsu_brupdate_b2_uop_frs3_en),
.io_lsu_brupdate_b2_uop_fp_val (_core_io_lsu_brupdate_b2_uop_fp_val),
.io_lsu_brupdate_b2_uop_fp_single (_core_io_lsu_brupdate_b2_uop_fp_single),
.io_lsu_brupdate_b2_uop_xcpt_pf_if (_core_io_lsu_brupdate_b2_uop_xcpt_pf_if),
.io_lsu_brupdate_b2_uop_xcpt_ae_if (_core_io_lsu_brupdate_b2_uop_xcpt_ae_if),
.io_lsu_brupdate_b2_uop_xcpt_ma_if (_core_io_lsu_brupdate_b2_uop_xcpt_ma_if),
.io_lsu_brupdate_b2_uop_bp_debug_if (_core_io_lsu_brupdate_b2_uop_bp_debug_if),
.io_lsu_brupdate_b2_uop_bp_xcpt_if (_core_io_lsu_brupdate_b2_uop_bp_xcpt_if),
.io_lsu_brupdate_b2_uop_debug_fsrc (_core_io_lsu_brupdate_b2_uop_debug_fsrc),
.io_lsu_brupdate_b2_uop_debug_tsrc (_core_io_lsu_brupdate_b2_uop_debug_tsrc),
.io_lsu_brupdate_b2_valid (_core_io_lsu_brupdate_b2_valid),
.io_lsu_brupdate_b2_mispredict (_core_io_lsu_brupdate_b2_mispredict),
.io_lsu_brupdate_b2_taken (_core_io_lsu_brupdate_b2_taken),
.io_lsu_brupdate_b2_cfi_type (_core_io_lsu_brupdate_b2_cfi_type),
.io_lsu_brupdate_b2_pc_sel (_core_io_lsu_brupdate_b2_pc_sel),
.io_lsu_brupdate_b2_jalr_target (_core_io_lsu_brupdate_b2_jalr_target),
.io_lsu_brupdate_b2_target_offset (_core_io_lsu_brupdate_b2_target_offset),
.io_lsu_rob_pnr_idx (_core_io_lsu_rob_pnr_idx),
.io_lsu_rob_head_idx (_core_io_lsu_rob_head_idx),
.io_lsu_exception (_core_io_lsu_exception),
.io_lsu_fencei_rdy (_lsu_io_core_fencei_rdy), // @[tile.scala:160:20]
.io_lsu_lxcpt_valid (_lsu_io_core_lxcpt_valid), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_uopc (_lsu_io_core_lxcpt_bits_uop_uopc), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_inst (_lsu_io_core_lxcpt_bits_uop_inst), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_debug_inst (_lsu_io_core_lxcpt_bits_uop_debug_inst), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_is_rvc (_lsu_io_core_lxcpt_bits_uop_is_rvc), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_debug_pc (_lsu_io_core_lxcpt_bits_uop_debug_pc), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_iq_type (_lsu_io_core_lxcpt_bits_uop_iq_type), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_fu_code (_lsu_io_core_lxcpt_bits_uop_fu_code), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_ctrl_br_type (_lsu_io_core_lxcpt_bits_uop_ctrl_br_type), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_ctrl_op1_sel (_lsu_io_core_lxcpt_bits_uop_ctrl_op1_sel), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_ctrl_op2_sel (_lsu_io_core_lxcpt_bits_uop_ctrl_op2_sel), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_ctrl_imm_sel (_lsu_io_core_lxcpt_bits_uop_ctrl_imm_sel), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_ctrl_op_fcn (_lsu_io_core_lxcpt_bits_uop_ctrl_op_fcn), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_ctrl_fcn_dw (_lsu_io_core_lxcpt_bits_uop_ctrl_fcn_dw), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_ctrl_csr_cmd (_lsu_io_core_lxcpt_bits_uop_ctrl_csr_cmd), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_ctrl_is_load (_lsu_io_core_lxcpt_bits_uop_ctrl_is_load), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_ctrl_is_sta (_lsu_io_core_lxcpt_bits_uop_ctrl_is_sta), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_ctrl_is_std (_lsu_io_core_lxcpt_bits_uop_ctrl_is_std), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_iw_state (_lsu_io_core_lxcpt_bits_uop_iw_state), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_iw_p1_poisoned (_lsu_io_core_lxcpt_bits_uop_iw_p1_poisoned), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_iw_p2_poisoned (_lsu_io_core_lxcpt_bits_uop_iw_p2_poisoned), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_is_br (_lsu_io_core_lxcpt_bits_uop_is_br), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_is_jalr (_lsu_io_core_lxcpt_bits_uop_is_jalr), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_is_jal (_lsu_io_core_lxcpt_bits_uop_is_jal), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_is_sfb (_lsu_io_core_lxcpt_bits_uop_is_sfb), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_br_mask (_lsu_io_core_lxcpt_bits_uop_br_mask), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_br_tag (_lsu_io_core_lxcpt_bits_uop_br_tag), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_ftq_idx (_lsu_io_core_lxcpt_bits_uop_ftq_idx), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_edge_inst (_lsu_io_core_lxcpt_bits_uop_edge_inst), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_pc_lob (_lsu_io_core_lxcpt_bits_uop_pc_lob), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_taken (_lsu_io_core_lxcpt_bits_uop_taken), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_imm_packed (_lsu_io_core_lxcpt_bits_uop_imm_packed), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_csr_addr (_lsu_io_core_lxcpt_bits_uop_csr_addr), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_rob_idx (_lsu_io_core_lxcpt_bits_uop_rob_idx), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_ldq_idx (_lsu_io_core_lxcpt_bits_uop_ldq_idx), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_stq_idx (_lsu_io_core_lxcpt_bits_uop_stq_idx), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_rxq_idx (_lsu_io_core_lxcpt_bits_uop_rxq_idx), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_pdst (_lsu_io_core_lxcpt_bits_uop_pdst), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_prs1 (_lsu_io_core_lxcpt_bits_uop_prs1), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_prs2 (_lsu_io_core_lxcpt_bits_uop_prs2), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_prs3 (_lsu_io_core_lxcpt_bits_uop_prs3), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_ppred (_lsu_io_core_lxcpt_bits_uop_ppred), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_prs1_busy (_lsu_io_core_lxcpt_bits_uop_prs1_busy), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_prs2_busy (_lsu_io_core_lxcpt_bits_uop_prs2_busy), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_prs3_busy (_lsu_io_core_lxcpt_bits_uop_prs3_busy), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_ppred_busy (_lsu_io_core_lxcpt_bits_uop_ppred_busy), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_stale_pdst (_lsu_io_core_lxcpt_bits_uop_stale_pdst), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_exception (_lsu_io_core_lxcpt_bits_uop_exception), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_exc_cause (_lsu_io_core_lxcpt_bits_uop_exc_cause), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_bypassable (_lsu_io_core_lxcpt_bits_uop_bypassable), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_mem_cmd (_lsu_io_core_lxcpt_bits_uop_mem_cmd), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_mem_size (_lsu_io_core_lxcpt_bits_uop_mem_size), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_mem_signed (_lsu_io_core_lxcpt_bits_uop_mem_signed), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_is_fence (_lsu_io_core_lxcpt_bits_uop_is_fence), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_is_fencei (_lsu_io_core_lxcpt_bits_uop_is_fencei), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_is_amo (_lsu_io_core_lxcpt_bits_uop_is_amo), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_uses_ldq (_lsu_io_core_lxcpt_bits_uop_uses_ldq), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_uses_stq (_lsu_io_core_lxcpt_bits_uop_uses_stq), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_is_sys_pc2epc (_lsu_io_core_lxcpt_bits_uop_is_sys_pc2epc), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_is_unique (_lsu_io_core_lxcpt_bits_uop_is_unique), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_flush_on_commit (_lsu_io_core_lxcpt_bits_uop_flush_on_commit), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_ldst_is_rs1 (_lsu_io_core_lxcpt_bits_uop_ldst_is_rs1), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_ldst (_lsu_io_core_lxcpt_bits_uop_ldst), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_lrs1 (_lsu_io_core_lxcpt_bits_uop_lrs1), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_lrs2 (_lsu_io_core_lxcpt_bits_uop_lrs2), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_lrs3 (_lsu_io_core_lxcpt_bits_uop_lrs3), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_ldst_val (_lsu_io_core_lxcpt_bits_uop_ldst_val), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_dst_rtype (_lsu_io_core_lxcpt_bits_uop_dst_rtype), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_lrs1_rtype (_lsu_io_core_lxcpt_bits_uop_lrs1_rtype), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_lrs2_rtype (_lsu_io_core_lxcpt_bits_uop_lrs2_rtype), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_frs3_en (_lsu_io_core_lxcpt_bits_uop_frs3_en), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_fp_val (_lsu_io_core_lxcpt_bits_uop_fp_val), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_fp_single (_lsu_io_core_lxcpt_bits_uop_fp_single), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_xcpt_pf_if (_lsu_io_core_lxcpt_bits_uop_xcpt_pf_if), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_xcpt_ae_if (_lsu_io_core_lxcpt_bits_uop_xcpt_ae_if), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_xcpt_ma_if (_lsu_io_core_lxcpt_bits_uop_xcpt_ma_if), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_bp_debug_if (_lsu_io_core_lxcpt_bits_uop_bp_debug_if), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_bp_xcpt_if (_lsu_io_core_lxcpt_bits_uop_bp_xcpt_if), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_debug_fsrc (_lsu_io_core_lxcpt_bits_uop_debug_fsrc), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_debug_tsrc (_lsu_io_core_lxcpt_bits_uop_debug_tsrc), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_cause (_lsu_io_core_lxcpt_bits_cause), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_badvaddr (_lsu_io_core_lxcpt_bits_badvaddr), // @[tile.scala:160:20]
.io_lsu_tsc_reg (_core_io_lsu_tsc_reg),
.io_lsu_perf_acquire (_lsu_io_core_perf_acquire), // @[tile.scala:160:20]
.io_lsu_perf_release (_lsu_io_core_perf_release), // @[tile.scala:160:20]
.io_lsu_perf_tlbMiss (_lsu_io_core_perf_tlbMiss), // @[tile.scala:160:20]
.io_ptw_tlb_req_ready (_ptw_io_requestor_2_req_ready), // @[tile.scala:237:20]
.io_ptw_tlb_resp_valid (_ptw_io_requestor_2_resp_valid), // @[tile.scala:237:20]
.io_ptw_tlb_resp_bits_ae_ptw (_ptw_io_requestor_2_resp_bits_ae_ptw), // @[tile.scala:237:20]
.io_ptw_tlb_resp_bits_ae_final (_ptw_io_requestor_2_resp_bits_ae_final), // @[tile.scala:237:20]
.io_ptw_tlb_resp_bits_pf (_ptw_io_requestor_2_resp_bits_pf), // @[tile.scala:237:20]
.io_ptw_tlb_resp_bits_gf (_ptw_io_requestor_2_resp_bits_gf), // @[tile.scala:237:20]
.io_ptw_tlb_resp_bits_hr (_ptw_io_requestor_2_resp_bits_hr), // @[tile.scala:237:20]
.io_ptw_tlb_resp_bits_hw (_ptw_io_requestor_2_resp_bits_hw), // @[tile.scala:237:20]
.io_ptw_tlb_resp_bits_hx (_ptw_io_requestor_2_resp_bits_hx), // @[tile.scala:237:20]
.io_ptw_tlb_resp_bits_pte_reserved_for_future (_ptw_io_requestor_2_resp_bits_pte_reserved_for_future), // @[tile.scala:237:20]
.io_ptw_tlb_resp_bits_pte_ppn (_ptw_io_requestor_2_resp_bits_pte_ppn), // @[tile.scala:237:20]
.io_ptw_tlb_resp_bits_pte_reserved_for_software (_ptw_io_requestor_2_resp_bits_pte_reserved_for_software), // @[tile.scala:237:20]
.io_ptw_tlb_resp_bits_pte_d (_ptw_io_requestor_2_resp_bits_pte_d), // @[tile.scala:237:20]
.io_ptw_tlb_resp_bits_pte_a (_ptw_io_requestor_2_resp_bits_pte_a), // @[tile.scala:237:20]
.io_ptw_tlb_resp_bits_pte_g (_ptw_io_requestor_2_resp_bits_pte_g), // @[tile.scala:237:20]
.io_ptw_tlb_resp_bits_pte_u (_ptw_io_requestor_2_resp_bits_pte_u), // @[tile.scala:237:20]
.io_ptw_tlb_resp_bits_pte_x (_ptw_io_requestor_2_resp_bits_pte_x), // @[tile.scala:237:20]
.io_ptw_tlb_resp_bits_pte_w (_ptw_io_requestor_2_resp_bits_pte_w), // @[tile.scala:237:20]
.io_ptw_tlb_resp_bits_pte_r (_ptw_io_requestor_2_resp_bits_pte_r), // @[tile.scala:237:20]
.io_ptw_tlb_resp_bits_pte_v (_ptw_io_requestor_2_resp_bits_pte_v), // @[tile.scala:237:20]
.io_ptw_tlb_resp_bits_level (_ptw_io_requestor_2_resp_bits_level), // @[tile.scala:237:20]
.io_ptw_tlb_resp_bits_homogeneous (_ptw_io_requestor_2_resp_bits_homogeneous), // @[tile.scala:237:20]
.io_ptw_tlb_resp_bits_gpa_valid (_ptw_io_requestor_2_resp_bits_gpa_valid), // @[tile.scala:237:20]
.io_ptw_tlb_resp_bits_gpa_bits (_ptw_io_requestor_2_resp_bits_gpa_bits), // @[tile.scala:237:20]
.io_ptw_tlb_resp_bits_gpa_is_pte (_ptw_io_requestor_2_resp_bits_gpa_is_pte), // @[tile.scala:237:20]
.io_ptw_tlb_ptbr_mode (_ptw_io_requestor_2_ptbr_mode), // @[tile.scala:237:20]
.io_ptw_tlb_ptbr_ppn (_ptw_io_requestor_2_ptbr_ppn), // @[tile.scala:237:20]
.io_ptw_tlb_status_debug (_ptw_io_requestor_2_status_debug), // @[tile.scala:237:20]
.io_ptw_tlb_status_cease (_ptw_io_requestor_2_status_cease), // @[tile.scala:237:20]
.io_ptw_tlb_status_wfi (_ptw_io_requestor_2_status_wfi), // @[tile.scala:237:20]
.io_ptw_tlb_status_dprv (_ptw_io_requestor_2_status_dprv), // @[tile.scala:237:20]
.io_ptw_tlb_status_dv (_ptw_io_requestor_2_status_dv), // @[tile.scala:237:20]
.io_ptw_tlb_status_prv (_ptw_io_requestor_2_status_prv), // @[tile.scala:237:20]
.io_ptw_tlb_status_v (_ptw_io_requestor_2_status_v), // @[tile.scala:237:20]
.io_ptw_tlb_status_sd (_ptw_io_requestor_2_status_sd), // @[tile.scala:237:20]
.io_ptw_tlb_status_mpv (_ptw_io_requestor_2_status_mpv), // @[tile.scala:237:20]
.io_ptw_tlb_status_gva (_ptw_io_requestor_2_status_gva), // @[tile.scala:237:20]
.io_ptw_tlb_status_tsr (_ptw_io_requestor_2_status_tsr), // @[tile.scala:237:20]
.io_ptw_tlb_status_tw (_ptw_io_requestor_2_status_tw), // @[tile.scala:237:20]
.io_ptw_tlb_status_tvm (_ptw_io_requestor_2_status_tvm), // @[tile.scala:237:20]
.io_ptw_tlb_status_mxr (_ptw_io_requestor_2_status_mxr), // @[tile.scala:237:20]
.io_ptw_tlb_status_sum (_ptw_io_requestor_2_status_sum), // @[tile.scala:237:20]
.io_ptw_tlb_status_mprv (_ptw_io_requestor_2_status_mprv), // @[tile.scala:237:20]
.io_ptw_tlb_status_fs (_ptw_io_requestor_2_status_fs), // @[tile.scala:237:20]
.io_ptw_tlb_status_mpp (_ptw_io_requestor_2_status_mpp), // @[tile.scala:237:20]
.io_ptw_tlb_status_spp (_ptw_io_requestor_2_status_spp), // @[tile.scala:237:20]
.io_ptw_tlb_status_mpie (_ptw_io_requestor_2_status_mpie), // @[tile.scala:237:20]
.io_ptw_tlb_status_spie (_ptw_io_requestor_2_status_spie), // @[tile.scala:237:20]
.io_ptw_tlb_status_mie (_ptw_io_requestor_2_status_mie), // @[tile.scala:237:20]
.io_ptw_tlb_status_sie (_ptw_io_requestor_2_status_sie), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_0_cfg_l (_ptw_io_requestor_2_pmp_0_cfg_l), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_0_cfg_a (_ptw_io_requestor_2_pmp_0_cfg_a), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_0_cfg_x (_ptw_io_requestor_2_pmp_0_cfg_x), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_0_cfg_w (_ptw_io_requestor_2_pmp_0_cfg_w), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_0_cfg_r (_ptw_io_requestor_2_pmp_0_cfg_r), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_0_addr (_ptw_io_requestor_2_pmp_0_addr), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_0_mask (_ptw_io_requestor_2_pmp_0_mask), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_1_cfg_l (_ptw_io_requestor_2_pmp_1_cfg_l), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_1_cfg_a (_ptw_io_requestor_2_pmp_1_cfg_a), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_1_cfg_x (_ptw_io_requestor_2_pmp_1_cfg_x), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_1_cfg_w (_ptw_io_requestor_2_pmp_1_cfg_w), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_1_cfg_r (_ptw_io_requestor_2_pmp_1_cfg_r), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_1_addr (_ptw_io_requestor_2_pmp_1_addr), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_1_mask (_ptw_io_requestor_2_pmp_1_mask), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_2_cfg_l (_ptw_io_requestor_2_pmp_2_cfg_l), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_2_cfg_a (_ptw_io_requestor_2_pmp_2_cfg_a), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_2_cfg_x (_ptw_io_requestor_2_pmp_2_cfg_x), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_2_cfg_w (_ptw_io_requestor_2_pmp_2_cfg_w), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_2_cfg_r (_ptw_io_requestor_2_pmp_2_cfg_r), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_2_addr (_ptw_io_requestor_2_pmp_2_addr), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_2_mask (_ptw_io_requestor_2_pmp_2_mask), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_3_cfg_l (_ptw_io_requestor_2_pmp_3_cfg_l), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_3_cfg_a (_ptw_io_requestor_2_pmp_3_cfg_a), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_3_cfg_x (_ptw_io_requestor_2_pmp_3_cfg_x), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_3_cfg_w (_ptw_io_requestor_2_pmp_3_cfg_w), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_3_cfg_r (_ptw_io_requestor_2_pmp_3_cfg_r), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_3_addr (_ptw_io_requestor_2_pmp_3_addr), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_3_mask (_ptw_io_requestor_2_pmp_3_mask), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_4_cfg_l (_ptw_io_requestor_2_pmp_4_cfg_l), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_4_cfg_a (_ptw_io_requestor_2_pmp_4_cfg_a), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_4_cfg_x (_ptw_io_requestor_2_pmp_4_cfg_x), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_4_cfg_w (_ptw_io_requestor_2_pmp_4_cfg_w), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_4_cfg_r (_ptw_io_requestor_2_pmp_4_cfg_r), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_4_addr (_ptw_io_requestor_2_pmp_4_addr), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_4_mask (_ptw_io_requestor_2_pmp_4_mask), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_5_cfg_l (_ptw_io_requestor_2_pmp_5_cfg_l), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_5_cfg_a (_ptw_io_requestor_2_pmp_5_cfg_a), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_5_cfg_x (_ptw_io_requestor_2_pmp_5_cfg_x), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_5_cfg_w (_ptw_io_requestor_2_pmp_5_cfg_w), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_5_cfg_r (_ptw_io_requestor_2_pmp_5_cfg_r), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_5_addr (_ptw_io_requestor_2_pmp_5_addr), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_5_mask (_ptw_io_requestor_2_pmp_5_mask), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_6_cfg_l (_ptw_io_requestor_2_pmp_6_cfg_l), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_6_cfg_a (_ptw_io_requestor_2_pmp_6_cfg_a), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_6_cfg_x (_ptw_io_requestor_2_pmp_6_cfg_x), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_6_cfg_w (_ptw_io_requestor_2_pmp_6_cfg_w), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_6_cfg_r (_ptw_io_requestor_2_pmp_6_cfg_r), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_6_addr (_ptw_io_requestor_2_pmp_6_addr), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_6_mask (_ptw_io_requestor_2_pmp_6_mask), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_7_cfg_l (_ptw_io_requestor_2_pmp_7_cfg_l), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_7_cfg_a (_ptw_io_requestor_2_pmp_7_cfg_a), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_7_cfg_x (_ptw_io_requestor_2_pmp_7_cfg_x), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_7_cfg_w (_ptw_io_requestor_2_pmp_7_cfg_w), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_7_cfg_r (_ptw_io_requestor_2_pmp_7_cfg_r), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_7_addr (_ptw_io_requestor_2_pmp_7_addr), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_7_mask (_ptw_io_requestor_2_pmp_7_mask), // @[tile.scala:237:20]
.io_trace_time (traceSourceNodeOut_time),
.io_trace_custom_rob_empty (traceSourceNodeOut_custom_rob_empty)
); // @[tile.scala:159:20]
LSU lsu ( // @[tile.scala:160:20]
.clock (clock),
.reset (reset),
.io_ptw_req_ready (_ptw_io_requestor_0_req_ready), // @[tile.scala:237:20]
.io_ptw_req_valid (_lsu_io_ptw_req_valid),
.io_ptw_req_bits_valid (_lsu_io_ptw_req_bits_valid),
.io_ptw_req_bits_bits_addr (_lsu_io_ptw_req_bits_bits_addr),
.io_ptw_resp_valid (_ptw_io_requestor_0_resp_valid), // @[tile.scala:237:20]
.io_ptw_resp_bits_ae_ptw (_ptw_io_requestor_0_resp_bits_ae_ptw), // @[tile.scala:237:20]
.io_ptw_resp_bits_ae_final (_ptw_io_requestor_0_resp_bits_ae_final), // @[tile.scala:237:20]
.io_ptw_resp_bits_pf (_ptw_io_requestor_0_resp_bits_pf), // @[tile.scala:237:20]
.io_ptw_resp_bits_gf (_ptw_io_requestor_0_resp_bits_gf), // @[tile.scala:237:20]
.io_ptw_resp_bits_hr (_ptw_io_requestor_0_resp_bits_hr), // @[tile.scala:237:20]
.io_ptw_resp_bits_hw (_ptw_io_requestor_0_resp_bits_hw), // @[tile.scala:237:20]
.io_ptw_resp_bits_hx (_ptw_io_requestor_0_resp_bits_hx), // @[tile.scala:237:20]
.io_ptw_resp_bits_pte_reserved_for_future (_ptw_io_requestor_0_resp_bits_pte_reserved_for_future), // @[tile.scala:237:20]
.io_ptw_resp_bits_pte_ppn (_ptw_io_requestor_0_resp_bits_pte_ppn), // @[tile.scala:237:20]
.io_ptw_resp_bits_pte_reserved_for_software (_ptw_io_requestor_0_resp_bits_pte_reserved_for_software), // @[tile.scala:237:20]
.io_ptw_resp_bits_pte_d (_ptw_io_requestor_0_resp_bits_pte_d), // @[tile.scala:237:20]
.io_ptw_resp_bits_pte_a (_ptw_io_requestor_0_resp_bits_pte_a), // @[tile.scala:237:20]
.io_ptw_resp_bits_pte_g (_ptw_io_requestor_0_resp_bits_pte_g), // @[tile.scala:237:20]
.io_ptw_resp_bits_pte_u (_ptw_io_requestor_0_resp_bits_pte_u), // @[tile.scala:237:20]
.io_ptw_resp_bits_pte_x (_ptw_io_requestor_0_resp_bits_pte_x), // @[tile.scala:237:20]
.io_ptw_resp_bits_pte_w (_ptw_io_requestor_0_resp_bits_pte_w), // @[tile.scala:237:20]
.io_ptw_resp_bits_pte_r (_ptw_io_requestor_0_resp_bits_pte_r), // @[tile.scala:237:20]
.io_ptw_resp_bits_pte_v (_ptw_io_requestor_0_resp_bits_pte_v), // @[tile.scala:237:20]
.io_ptw_resp_bits_level (_ptw_io_requestor_0_resp_bits_level), // @[tile.scala:237:20]
.io_ptw_resp_bits_homogeneous (_ptw_io_requestor_0_resp_bits_homogeneous), // @[tile.scala:237:20]
.io_ptw_resp_bits_gpa_valid (_ptw_io_requestor_0_resp_bits_gpa_valid), // @[tile.scala:237:20]
.io_ptw_resp_bits_gpa_bits (_ptw_io_requestor_0_resp_bits_gpa_bits), // @[tile.scala:237:20]
.io_ptw_resp_bits_gpa_is_pte (_ptw_io_requestor_0_resp_bits_gpa_is_pte), // @[tile.scala:237:20]
.io_ptw_ptbr_mode (_ptw_io_requestor_0_ptbr_mode), // @[tile.scala:237:20]
.io_ptw_ptbr_ppn (_ptw_io_requestor_0_ptbr_ppn), // @[tile.scala:237:20]
.io_ptw_status_debug (_ptw_io_requestor_0_status_debug), // @[tile.scala:237:20]
.io_ptw_status_cease (_ptw_io_requestor_0_status_cease), // @[tile.scala:237:20]
.io_ptw_status_wfi (_ptw_io_requestor_0_status_wfi), // @[tile.scala:237:20]
.io_ptw_status_dprv (_ptw_io_requestor_0_status_dprv), // @[tile.scala:237:20]
.io_ptw_status_dv (_ptw_io_requestor_0_status_dv), // @[tile.scala:237:20]
.io_ptw_status_prv (_ptw_io_requestor_0_status_prv), // @[tile.scala:237:20]
.io_ptw_status_v (_ptw_io_requestor_0_status_v), // @[tile.scala:237:20]
.io_ptw_status_sd (_ptw_io_requestor_0_status_sd), // @[tile.scala:237:20]
.io_ptw_status_mpv (_ptw_io_requestor_0_status_mpv), // @[tile.scala:237:20]
.io_ptw_status_gva (_ptw_io_requestor_0_status_gva), // @[tile.scala:237:20]
.io_ptw_status_tsr (_ptw_io_requestor_0_status_tsr), // @[tile.scala:237:20]
.io_ptw_status_tw (_ptw_io_requestor_0_status_tw), // @[tile.scala:237:20]
.io_ptw_status_tvm (_ptw_io_requestor_0_status_tvm), // @[tile.scala:237:20]
.io_ptw_status_mxr (_ptw_io_requestor_0_status_mxr), // @[tile.scala:237:20]
.io_ptw_status_sum (_ptw_io_requestor_0_status_sum), // @[tile.scala:237:20]
.io_ptw_status_mprv (_ptw_io_requestor_0_status_mprv), // @[tile.scala:237:20]
.io_ptw_status_fs (_ptw_io_requestor_0_status_fs), // @[tile.scala:237:20]
.io_ptw_status_mpp (_ptw_io_requestor_0_status_mpp), // @[tile.scala:237:20]
.io_ptw_status_spp (_ptw_io_requestor_0_status_spp), // @[tile.scala:237:20]
.io_ptw_status_mpie (_ptw_io_requestor_0_status_mpie), // @[tile.scala:237:20]
.io_ptw_status_spie (_ptw_io_requestor_0_status_spie), // @[tile.scala:237:20]
.io_ptw_status_mie (_ptw_io_requestor_0_status_mie), // @[tile.scala:237:20]
.io_ptw_status_sie (_ptw_io_requestor_0_status_sie), // @[tile.scala:237:20]
.io_ptw_pmp_0_cfg_l (_ptw_io_requestor_0_pmp_0_cfg_l), // @[tile.scala:237:20]
.io_ptw_pmp_0_cfg_a (_ptw_io_requestor_0_pmp_0_cfg_a), // @[tile.scala:237:20]
.io_ptw_pmp_0_cfg_x (_ptw_io_requestor_0_pmp_0_cfg_x), // @[tile.scala:237:20]
.io_ptw_pmp_0_cfg_w (_ptw_io_requestor_0_pmp_0_cfg_w), // @[tile.scala:237:20]
.io_ptw_pmp_0_cfg_r (_ptw_io_requestor_0_pmp_0_cfg_r), // @[tile.scala:237:20]
.io_ptw_pmp_0_addr (_ptw_io_requestor_0_pmp_0_addr), // @[tile.scala:237:20]
.io_ptw_pmp_0_mask (_ptw_io_requestor_0_pmp_0_mask), // @[tile.scala:237:20]
.io_ptw_pmp_1_cfg_l (_ptw_io_requestor_0_pmp_1_cfg_l), // @[tile.scala:237:20]
.io_ptw_pmp_1_cfg_a (_ptw_io_requestor_0_pmp_1_cfg_a), // @[tile.scala:237:20]
.io_ptw_pmp_1_cfg_x (_ptw_io_requestor_0_pmp_1_cfg_x), // @[tile.scala:237:20]
.io_ptw_pmp_1_cfg_w (_ptw_io_requestor_0_pmp_1_cfg_w), // @[tile.scala:237:20]
.io_ptw_pmp_1_cfg_r (_ptw_io_requestor_0_pmp_1_cfg_r), // @[tile.scala:237:20]
.io_ptw_pmp_1_addr (_ptw_io_requestor_0_pmp_1_addr), // @[tile.scala:237:20]
.io_ptw_pmp_1_mask (_ptw_io_requestor_0_pmp_1_mask), // @[tile.scala:237:20]
.io_ptw_pmp_2_cfg_l (_ptw_io_requestor_0_pmp_2_cfg_l), // @[tile.scala:237:20]
.io_ptw_pmp_2_cfg_a (_ptw_io_requestor_0_pmp_2_cfg_a), // @[tile.scala:237:20]
.io_ptw_pmp_2_cfg_x (_ptw_io_requestor_0_pmp_2_cfg_x), // @[tile.scala:237:20]
.io_ptw_pmp_2_cfg_w (_ptw_io_requestor_0_pmp_2_cfg_w), // @[tile.scala:237:20]
.io_ptw_pmp_2_cfg_r (_ptw_io_requestor_0_pmp_2_cfg_r), // @[tile.scala:237:20]
.io_ptw_pmp_2_addr (_ptw_io_requestor_0_pmp_2_addr), // @[tile.scala:237:20]
.io_ptw_pmp_2_mask (_ptw_io_requestor_0_pmp_2_mask), // @[tile.scala:237:20]
.io_ptw_pmp_3_cfg_l (_ptw_io_requestor_0_pmp_3_cfg_l), // @[tile.scala:237:20]
.io_ptw_pmp_3_cfg_a (_ptw_io_requestor_0_pmp_3_cfg_a), // @[tile.scala:237:20]
.io_ptw_pmp_3_cfg_x (_ptw_io_requestor_0_pmp_3_cfg_x), // @[tile.scala:237:20]
.io_ptw_pmp_3_cfg_w (_ptw_io_requestor_0_pmp_3_cfg_w), // @[tile.scala:237:20]
.io_ptw_pmp_3_cfg_r (_ptw_io_requestor_0_pmp_3_cfg_r), // @[tile.scala:237:20]
.io_ptw_pmp_3_addr (_ptw_io_requestor_0_pmp_3_addr), // @[tile.scala:237:20]
.io_ptw_pmp_3_mask (_ptw_io_requestor_0_pmp_3_mask), // @[tile.scala:237:20]
.io_ptw_pmp_4_cfg_l (_ptw_io_requestor_0_pmp_4_cfg_l), // @[tile.scala:237:20]
.io_ptw_pmp_4_cfg_a (_ptw_io_requestor_0_pmp_4_cfg_a), // @[tile.scala:237:20]
.io_ptw_pmp_4_cfg_x (_ptw_io_requestor_0_pmp_4_cfg_x), // @[tile.scala:237:20]
.io_ptw_pmp_4_cfg_w (_ptw_io_requestor_0_pmp_4_cfg_w), // @[tile.scala:237:20]
.io_ptw_pmp_4_cfg_r (_ptw_io_requestor_0_pmp_4_cfg_r), // @[tile.scala:237:20]
.io_ptw_pmp_4_addr (_ptw_io_requestor_0_pmp_4_addr), // @[tile.scala:237:20]
.io_ptw_pmp_4_mask (_ptw_io_requestor_0_pmp_4_mask), // @[tile.scala:237:20]
.io_ptw_pmp_5_cfg_l (_ptw_io_requestor_0_pmp_5_cfg_l), // @[tile.scala:237:20]
.io_ptw_pmp_5_cfg_a (_ptw_io_requestor_0_pmp_5_cfg_a), // @[tile.scala:237:20]
.io_ptw_pmp_5_cfg_x (_ptw_io_requestor_0_pmp_5_cfg_x), // @[tile.scala:237:20]
.io_ptw_pmp_5_cfg_w (_ptw_io_requestor_0_pmp_5_cfg_w), // @[tile.scala:237:20]
.io_ptw_pmp_5_cfg_r (_ptw_io_requestor_0_pmp_5_cfg_r), // @[tile.scala:237:20]
.io_ptw_pmp_5_addr (_ptw_io_requestor_0_pmp_5_addr), // @[tile.scala:237:20]
.io_ptw_pmp_5_mask (_ptw_io_requestor_0_pmp_5_mask), // @[tile.scala:237:20]
.io_ptw_pmp_6_cfg_l (_ptw_io_requestor_0_pmp_6_cfg_l), // @[tile.scala:237:20]
.io_ptw_pmp_6_cfg_a (_ptw_io_requestor_0_pmp_6_cfg_a), // @[tile.scala:237:20]
.io_ptw_pmp_6_cfg_x (_ptw_io_requestor_0_pmp_6_cfg_x), // @[tile.scala:237:20]
.io_ptw_pmp_6_cfg_w (_ptw_io_requestor_0_pmp_6_cfg_w), // @[tile.scala:237:20]
.io_ptw_pmp_6_cfg_r (_ptw_io_requestor_0_pmp_6_cfg_r), // @[tile.scala:237:20]
.io_ptw_pmp_6_addr (_ptw_io_requestor_0_pmp_6_addr), // @[tile.scala:237:20]
.io_ptw_pmp_6_mask (_ptw_io_requestor_0_pmp_6_mask), // @[tile.scala:237:20]
.io_ptw_pmp_7_cfg_l (_ptw_io_requestor_0_pmp_7_cfg_l), // @[tile.scala:237:20]
.io_ptw_pmp_7_cfg_a (_ptw_io_requestor_0_pmp_7_cfg_a), // @[tile.scala:237:20]
.io_ptw_pmp_7_cfg_x (_ptw_io_requestor_0_pmp_7_cfg_x), // @[tile.scala:237:20]
.io_ptw_pmp_7_cfg_w (_ptw_io_requestor_0_pmp_7_cfg_w), // @[tile.scala:237:20]
.io_ptw_pmp_7_cfg_r (_ptw_io_requestor_0_pmp_7_cfg_r), // @[tile.scala:237:20]
.io_ptw_pmp_7_addr (_ptw_io_requestor_0_pmp_7_addr), // @[tile.scala:237:20]
.io_ptw_pmp_7_mask (_ptw_io_requestor_0_pmp_7_mask), // @[tile.scala:237:20]
.io_core_exe_0_req_valid (_core_io_lsu_exe_0_req_valid), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_uopc (_core_io_lsu_exe_0_req_bits_uop_uopc), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_inst (_core_io_lsu_exe_0_req_bits_uop_inst), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_debug_inst (_core_io_lsu_exe_0_req_bits_uop_debug_inst), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_is_rvc (_core_io_lsu_exe_0_req_bits_uop_is_rvc), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_debug_pc (_core_io_lsu_exe_0_req_bits_uop_debug_pc), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_iq_type (_core_io_lsu_exe_0_req_bits_uop_iq_type), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_fu_code (_core_io_lsu_exe_0_req_bits_uop_fu_code), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_ctrl_br_type (_core_io_lsu_exe_0_req_bits_uop_ctrl_br_type), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_ctrl_op1_sel (_core_io_lsu_exe_0_req_bits_uop_ctrl_op1_sel), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_ctrl_op2_sel (_core_io_lsu_exe_0_req_bits_uop_ctrl_op2_sel), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_ctrl_imm_sel (_core_io_lsu_exe_0_req_bits_uop_ctrl_imm_sel), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_ctrl_op_fcn (_core_io_lsu_exe_0_req_bits_uop_ctrl_op_fcn), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_ctrl_fcn_dw (_core_io_lsu_exe_0_req_bits_uop_ctrl_fcn_dw), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_ctrl_csr_cmd (_core_io_lsu_exe_0_req_bits_uop_ctrl_csr_cmd), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_ctrl_is_load (_core_io_lsu_exe_0_req_bits_uop_ctrl_is_load), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_ctrl_is_sta (_core_io_lsu_exe_0_req_bits_uop_ctrl_is_sta), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_ctrl_is_std (_core_io_lsu_exe_0_req_bits_uop_ctrl_is_std), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_iw_state (_core_io_lsu_exe_0_req_bits_uop_iw_state), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_iw_p1_poisoned (_core_io_lsu_exe_0_req_bits_uop_iw_p1_poisoned), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_iw_p2_poisoned (_core_io_lsu_exe_0_req_bits_uop_iw_p2_poisoned), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_is_br (_core_io_lsu_exe_0_req_bits_uop_is_br), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_is_jalr (_core_io_lsu_exe_0_req_bits_uop_is_jalr), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_is_jal (_core_io_lsu_exe_0_req_bits_uop_is_jal), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_is_sfb (_core_io_lsu_exe_0_req_bits_uop_is_sfb), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_br_mask (_core_io_lsu_exe_0_req_bits_uop_br_mask), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_br_tag (_core_io_lsu_exe_0_req_bits_uop_br_tag), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_ftq_idx (_core_io_lsu_exe_0_req_bits_uop_ftq_idx), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_edge_inst (_core_io_lsu_exe_0_req_bits_uop_edge_inst), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_pc_lob (_core_io_lsu_exe_0_req_bits_uop_pc_lob), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_taken (_core_io_lsu_exe_0_req_bits_uop_taken), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_imm_packed (_core_io_lsu_exe_0_req_bits_uop_imm_packed), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_csr_addr (_core_io_lsu_exe_0_req_bits_uop_csr_addr), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_rob_idx (_core_io_lsu_exe_0_req_bits_uop_rob_idx), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_ldq_idx (_core_io_lsu_exe_0_req_bits_uop_ldq_idx), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_stq_idx (_core_io_lsu_exe_0_req_bits_uop_stq_idx), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_rxq_idx (_core_io_lsu_exe_0_req_bits_uop_rxq_idx), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_pdst (_core_io_lsu_exe_0_req_bits_uop_pdst), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_prs1 (_core_io_lsu_exe_0_req_bits_uop_prs1), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_prs2 (_core_io_lsu_exe_0_req_bits_uop_prs2), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_prs3 (_core_io_lsu_exe_0_req_bits_uop_prs3), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_ppred (_core_io_lsu_exe_0_req_bits_uop_ppred), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_prs1_busy (_core_io_lsu_exe_0_req_bits_uop_prs1_busy), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_prs2_busy (_core_io_lsu_exe_0_req_bits_uop_prs2_busy), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_prs3_busy (_core_io_lsu_exe_0_req_bits_uop_prs3_busy), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_ppred_busy (_core_io_lsu_exe_0_req_bits_uop_ppred_busy), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_stale_pdst (_core_io_lsu_exe_0_req_bits_uop_stale_pdst), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_exception (_core_io_lsu_exe_0_req_bits_uop_exception), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_exc_cause (_core_io_lsu_exe_0_req_bits_uop_exc_cause), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_bypassable (_core_io_lsu_exe_0_req_bits_uop_bypassable), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_mem_cmd (_core_io_lsu_exe_0_req_bits_uop_mem_cmd), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_mem_size (_core_io_lsu_exe_0_req_bits_uop_mem_size), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_mem_signed (_core_io_lsu_exe_0_req_bits_uop_mem_signed), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_is_fence (_core_io_lsu_exe_0_req_bits_uop_is_fence), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_is_fencei (_core_io_lsu_exe_0_req_bits_uop_is_fencei), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_is_amo (_core_io_lsu_exe_0_req_bits_uop_is_amo), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_uses_ldq (_core_io_lsu_exe_0_req_bits_uop_uses_ldq), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_uses_stq (_core_io_lsu_exe_0_req_bits_uop_uses_stq), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_is_sys_pc2epc (_core_io_lsu_exe_0_req_bits_uop_is_sys_pc2epc), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_is_unique (_core_io_lsu_exe_0_req_bits_uop_is_unique), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_flush_on_commit (_core_io_lsu_exe_0_req_bits_uop_flush_on_commit), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_ldst_is_rs1 (_core_io_lsu_exe_0_req_bits_uop_ldst_is_rs1), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_ldst (_core_io_lsu_exe_0_req_bits_uop_ldst), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_lrs1 (_core_io_lsu_exe_0_req_bits_uop_lrs1), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_lrs2 (_core_io_lsu_exe_0_req_bits_uop_lrs2), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_lrs3 (_core_io_lsu_exe_0_req_bits_uop_lrs3), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_ldst_val (_core_io_lsu_exe_0_req_bits_uop_ldst_val), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_dst_rtype (_core_io_lsu_exe_0_req_bits_uop_dst_rtype), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_lrs1_rtype (_core_io_lsu_exe_0_req_bits_uop_lrs1_rtype), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_lrs2_rtype (_core_io_lsu_exe_0_req_bits_uop_lrs2_rtype), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_frs3_en (_core_io_lsu_exe_0_req_bits_uop_frs3_en), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_fp_val (_core_io_lsu_exe_0_req_bits_uop_fp_val), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_fp_single (_core_io_lsu_exe_0_req_bits_uop_fp_single), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_xcpt_pf_if (_core_io_lsu_exe_0_req_bits_uop_xcpt_pf_if), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_xcpt_ae_if (_core_io_lsu_exe_0_req_bits_uop_xcpt_ae_if), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_xcpt_ma_if (_core_io_lsu_exe_0_req_bits_uop_xcpt_ma_if), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_bp_debug_if (_core_io_lsu_exe_0_req_bits_uop_bp_debug_if), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_bp_xcpt_if (_core_io_lsu_exe_0_req_bits_uop_bp_xcpt_if), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_debug_fsrc (_core_io_lsu_exe_0_req_bits_uop_debug_fsrc), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_debug_tsrc (_core_io_lsu_exe_0_req_bits_uop_debug_tsrc), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_data (_core_io_lsu_exe_0_req_bits_data), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_addr (_core_io_lsu_exe_0_req_bits_addr), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_mxcpt_valid (_core_io_lsu_exe_0_req_bits_mxcpt_valid), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_mxcpt_bits (_core_io_lsu_exe_0_req_bits_mxcpt_bits), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_sfence_valid (_core_io_lsu_exe_0_req_bits_sfence_valid), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_sfence_bits_rs1 (_core_io_lsu_exe_0_req_bits_sfence_bits_rs1), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_sfence_bits_rs2 (_core_io_lsu_exe_0_req_bits_sfence_bits_rs2), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_sfence_bits_addr (_core_io_lsu_exe_0_req_bits_sfence_bits_addr), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_sfence_bits_asid (_core_io_lsu_exe_0_req_bits_sfence_bits_asid), // @[tile.scala:159:20]
.io_core_exe_0_iresp_valid (_lsu_io_core_exe_0_iresp_valid),
.io_core_exe_0_iresp_bits_uop_uopc (_lsu_io_core_exe_0_iresp_bits_uop_uopc),
.io_core_exe_0_iresp_bits_uop_inst (_lsu_io_core_exe_0_iresp_bits_uop_inst),
.io_core_exe_0_iresp_bits_uop_debug_inst (_lsu_io_core_exe_0_iresp_bits_uop_debug_inst),
.io_core_exe_0_iresp_bits_uop_is_rvc (_lsu_io_core_exe_0_iresp_bits_uop_is_rvc),
.io_core_exe_0_iresp_bits_uop_debug_pc (_lsu_io_core_exe_0_iresp_bits_uop_debug_pc),
.io_core_exe_0_iresp_bits_uop_iq_type (_lsu_io_core_exe_0_iresp_bits_uop_iq_type),
.io_core_exe_0_iresp_bits_uop_fu_code (_lsu_io_core_exe_0_iresp_bits_uop_fu_code),
.io_core_exe_0_iresp_bits_uop_ctrl_br_type (_lsu_io_core_exe_0_iresp_bits_uop_ctrl_br_type),
.io_core_exe_0_iresp_bits_uop_ctrl_op1_sel (_lsu_io_core_exe_0_iresp_bits_uop_ctrl_op1_sel),
.io_core_exe_0_iresp_bits_uop_ctrl_op2_sel (_lsu_io_core_exe_0_iresp_bits_uop_ctrl_op2_sel),
.io_core_exe_0_iresp_bits_uop_ctrl_imm_sel (_lsu_io_core_exe_0_iresp_bits_uop_ctrl_imm_sel),
.io_core_exe_0_iresp_bits_uop_ctrl_op_fcn (_lsu_io_core_exe_0_iresp_bits_uop_ctrl_op_fcn),
.io_core_exe_0_iresp_bits_uop_ctrl_fcn_dw (_lsu_io_core_exe_0_iresp_bits_uop_ctrl_fcn_dw),
.io_core_exe_0_iresp_bits_uop_ctrl_csr_cmd (_lsu_io_core_exe_0_iresp_bits_uop_ctrl_csr_cmd),
.io_core_exe_0_iresp_bits_uop_ctrl_is_load (_lsu_io_core_exe_0_iresp_bits_uop_ctrl_is_load),
.io_core_exe_0_iresp_bits_uop_ctrl_is_sta (_lsu_io_core_exe_0_iresp_bits_uop_ctrl_is_sta),
.io_core_exe_0_iresp_bits_uop_ctrl_is_std (_lsu_io_core_exe_0_iresp_bits_uop_ctrl_is_std),
.io_core_exe_0_iresp_bits_uop_iw_state (_lsu_io_core_exe_0_iresp_bits_uop_iw_state),
.io_core_exe_0_iresp_bits_uop_iw_p1_poisoned (_lsu_io_core_exe_0_iresp_bits_uop_iw_p1_poisoned),
.io_core_exe_0_iresp_bits_uop_iw_p2_poisoned (_lsu_io_core_exe_0_iresp_bits_uop_iw_p2_poisoned),
.io_core_exe_0_iresp_bits_uop_is_br (_lsu_io_core_exe_0_iresp_bits_uop_is_br),
.io_core_exe_0_iresp_bits_uop_is_jalr (_lsu_io_core_exe_0_iresp_bits_uop_is_jalr),
.io_core_exe_0_iresp_bits_uop_is_jal (_lsu_io_core_exe_0_iresp_bits_uop_is_jal),
.io_core_exe_0_iresp_bits_uop_is_sfb (_lsu_io_core_exe_0_iresp_bits_uop_is_sfb),
.io_core_exe_0_iresp_bits_uop_br_mask (_lsu_io_core_exe_0_iresp_bits_uop_br_mask),
.io_core_exe_0_iresp_bits_uop_br_tag (_lsu_io_core_exe_0_iresp_bits_uop_br_tag),
.io_core_exe_0_iresp_bits_uop_ftq_idx (_lsu_io_core_exe_0_iresp_bits_uop_ftq_idx),
.io_core_exe_0_iresp_bits_uop_edge_inst (_lsu_io_core_exe_0_iresp_bits_uop_edge_inst),
.io_core_exe_0_iresp_bits_uop_pc_lob (_lsu_io_core_exe_0_iresp_bits_uop_pc_lob),
.io_core_exe_0_iresp_bits_uop_taken (_lsu_io_core_exe_0_iresp_bits_uop_taken),
.io_core_exe_0_iresp_bits_uop_imm_packed (_lsu_io_core_exe_0_iresp_bits_uop_imm_packed),
.io_core_exe_0_iresp_bits_uop_csr_addr (_lsu_io_core_exe_0_iresp_bits_uop_csr_addr),
.io_core_exe_0_iresp_bits_uop_rob_idx (_lsu_io_core_exe_0_iresp_bits_uop_rob_idx),
.io_core_exe_0_iresp_bits_uop_ldq_idx (_lsu_io_core_exe_0_iresp_bits_uop_ldq_idx),
.io_core_exe_0_iresp_bits_uop_stq_idx (_lsu_io_core_exe_0_iresp_bits_uop_stq_idx),
.io_core_exe_0_iresp_bits_uop_rxq_idx (_lsu_io_core_exe_0_iresp_bits_uop_rxq_idx),
.io_core_exe_0_iresp_bits_uop_pdst (_lsu_io_core_exe_0_iresp_bits_uop_pdst),
.io_core_exe_0_iresp_bits_uop_prs1 (_lsu_io_core_exe_0_iresp_bits_uop_prs1),
.io_core_exe_0_iresp_bits_uop_prs2 (_lsu_io_core_exe_0_iresp_bits_uop_prs2),
.io_core_exe_0_iresp_bits_uop_prs3 (_lsu_io_core_exe_0_iresp_bits_uop_prs3),
.io_core_exe_0_iresp_bits_uop_ppred (_lsu_io_core_exe_0_iresp_bits_uop_ppred),
.io_core_exe_0_iresp_bits_uop_prs1_busy (_lsu_io_core_exe_0_iresp_bits_uop_prs1_busy),
.io_core_exe_0_iresp_bits_uop_prs2_busy (_lsu_io_core_exe_0_iresp_bits_uop_prs2_busy),
.io_core_exe_0_iresp_bits_uop_prs3_busy (_lsu_io_core_exe_0_iresp_bits_uop_prs3_busy),
.io_core_exe_0_iresp_bits_uop_ppred_busy (_lsu_io_core_exe_0_iresp_bits_uop_ppred_busy),
.io_core_exe_0_iresp_bits_uop_stale_pdst (_lsu_io_core_exe_0_iresp_bits_uop_stale_pdst),
.io_core_exe_0_iresp_bits_uop_exception (_lsu_io_core_exe_0_iresp_bits_uop_exception),
.io_core_exe_0_iresp_bits_uop_exc_cause (_lsu_io_core_exe_0_iresp_bits_uop_exc_cause),
.io_core_exe_0_iresp_bits_uop_bypassable (_lsu_io_core_exe_0_iresp_bits_uop_bypassable),
.io_core_exe_0_iresp_bits_uop_mem_cmd (_lsu_io_core_exe_0_iresp_bits_uop_mem_cmd),
.io_core_exe_0_iresp_bits_uop_mem_size (_lsu_io_core_exe_0_iresp_bits_uop_mem_size),
.io_core_exe_0_iresp_bits_uop_mem_signed (_lsu_io_core_exe_0_iresp_bits_uop_mem_signed),
.io_core_exe_0_iresp_bits_uop_is_fence (_lsu_io_core_exe_0_iresp_bits_uop_is_fence),
.io_core_exe_0_iresp_bits_uop_is_fencei (_lsu_io_core_exe_0_iresp_bits_uop_is_fencei),
.io_core_exe_0_iresp_bits_uop_is_amo (_lsu_io_core_exe_0_iresp_bits_uop_is_amo),
.io_core_exe_0_iresp_bits_uop_uses_ldq (_lsu_io_core_exe_0_iresp_bits_uop_uses_ldq),
.io_core_exe_0_iresp_bits_uop_uses_stq (_lsu_io_core_exe_0_iresp_bits_uop_uses_stq),
.io_core_exe_0_iresp_bits_uop_is_sys_pc2epc (_lsu_io_core_exe_0_iresp_bits_uop_is_sys_pc2epc),
.io_core_exe_0_iresp_bits_uop_is_unique (_lsu_io_core_exe_0_iresp_bits_uop_is_unique),
.io_core_exe_0_iresp_bits_uop_flush_on_commit (_lsu_io_core_exe_0_iresp_bits_uop_flush_on_commit),
.io_core_exe_0_iresp_bits_uop_ldst_is_rs1 (_lsu_io_core_exe_0_iresp_bits_uop_ldst_is_rs1),
.io_core_exe_0_iresp_bits_uop_ldst (_lsu_io_core_exe_0_iresp_bits_uop_ldst),
.io_core_exe_0_iresp_bits_uop_lrs1 (_lsu_io_core_exe_0_iresp_bits_uop_lrs1),
.io_core_exe_0_iresp_bits_uop_lrs2 (_lsu_io_core_exe_0_iresp_bits_uop_lrs2),
.io_core_exe_0_iresp_bits_uop_lrs3 (_lsu_io_core_exe_0_iresp_bits_uop_lrs3),
.io_core_exe_0_iresp_bits_uop_ldst_val (_lsu_io_core_exe_0_iresp_bits_uop_ldst_val),
.io_core_exe_0_iresp_bits_uop_dst_rtype (_lsu_io_core_exe_0_iresp_bits_uop_dst_rtype),
.io_core_exe_0_iresp_bits_uop_lrs1_rtype (_lsu_io_core_exe_0_iresp_bits_uop_lrs1_rtype),
.io_core_exe_0_iresp_bits_uop_lrs2_rtype (_lsu_io_core_exe_0_iresp_bits_uop_lrs2_rtype),
.io_core_exe_0_iresp_bits_uop_frs3_en (_lsu_io_core_exe_0_iresp_bits_uop_frs3_en),
.io_core_exe_0_iresp_bits_uop_fp_val (_lsu_io_core_exe_0_iresp_bits_uop_fp_val),
.io_core_exe_0_iresp_bits_uop_fp_single (_lsu_io_core_exe_0_iresp_bits_uop_fp_single),
.io_core_exe_0_iresp_bits_uop_xcpt_pf_if (_lsu_io_core_exe_0_iresp_bits_uop_xcpt_pf_if),
.io_core_exe_0_iresp_bits_uop_xcpt_ae_if (_lsu_io_core_exe_0_iresp_bits_uop_xcpt_ae_if),
.io_core_exe_0_iresp_bits_uop_xcpt_ma_if (_lsu_io_core_exe_0_iresp_bits_uop_xcpt_ma_if),
.io_core_exe_0_iresp_bits_uop_bp_debug_if (_lsu_io_core_exe_0_iresp_bits_uop_bp_debug_if),
.io_core_exe_0_iresp_bits_uop_bp_xcpt_if (_lsu_io_core_exe_0_iresp_bits_uop_bp_xcpt_if),
.io_core_exe_0_iresp_bits_uop_debug_fsrc (_lsu_io_core_exe_0_iresp_bits_uop_debug_fsrc),
.io_core_exe_0_iresp_bits_uop_debug_tsrc (_lsu_io_core_exe_0_iresp_bits_uop_debug_tsrc),
.io_core_exe_0_iresp_bits_data (_lsu_io_core_exe_0_iresp_bits_data),
.io_core_exe_0_fresp_valid (_lsu_io_core_exe_0_fresp_valid),
.io_core_exe_0_fresp_bits_uop_uopc (_lsu_io_core_exe_0_fresp_bits_uop_uopc),
.io_core_exe_0_fresp_bits_uop_inst (_lsu_io_core_exe_0_fresp_bits_uop_inst),
.io_core_exe_0_fresp_bits_uop_debug_inst (_lsu_io_core_exe_0_fresp_bits_uop_debug_inst),
.io_core_exe_0_fresp_bits_uop_is_rvc (_lsu_io_core_exe_0_fresp_bits_uop_is_rvc),
.io_core_exe_0_fresp_bits_uop_debug_pc (_lsu_io_core_exe_0_fresp_bits_uop_debug_pc),
.io_core_exe_0_fresp_bits_uop_iq_type (_lsu_io_core_exe_0_fresp_bits_uop_iq_type),
.io_core_exe_0_fresp_bits_uop_fu_code (_lsu_io_core_exe_0_fresp_bits_uop_fu_code),
.io_core_exe_0_fresp_bits_uop_ctrl_br_type (_lsu_io_core_exe_0_fresp_bits_uop_ctrl_br_type),
.io_core_exe_0_fresp_bits_uop_ctrl_op1_sel (_lsu_io_core_exe_0_fresp_bits_uop_ctrl_op1_sel),
.io_core_exe_0_fresp_bits_uop_ctrl_op2_sel (_lsu_io_core_exe_0_fresp_bits_uop_ctrl_op2_sel),
.io_core_exe_0_fresp_bits_uop_ctrl_imm_sel (_lsu_io_core_exe_0_fresp_bits_uop_ctrl_imm_sel),
.io_core_exe_0_fresp_bits_uop_ctrl_op_fcn (_lsu_io_core_exe_0_fresp_bits_uop_ctrl_op_fcn),
.io_core_exe_0_fresp_bits_uop_ctrl_fcn_dw (_lsu_io_core_exe_0_fresp_bits_uop_ctrl_fcn_dw),
.io_core_exe_0_fresp_bits_uop_ctrl_csr_cmd (_lsu_io_core_exe_0_fresp_bits_uop_ctrl_csr_cmd),
.io_core_exe_0_fresp_bits_uop_ctrl_is_load (_lsu_io_core_exe_0_fresp_bits_uop_ctrl_is_load),
.io_core_exe_0_fresp_bits_uop_ctrl_is_sta (_lsu_io_core_exe_0_fresp_bits_uop_ctrl_is_sta),
.io_core_exe_0_fresp_bits_uop_ctrl_is_std (_lsu_io_core_exe_0_fresp_bits_uop_ctrl_is_std),
.io_core_exe_0_fresp_bits_uop_iw_state (_lsu_io_core_exe_0_fresp_bits_uop_iw_state),
.io_core_exe_0_fresp_bits_uop_iw_p1_poisoned (_lsu_io_core_exe_0_fresp_bits_uop_iw_p1_poisoned),
.io_core_exe_0_fresp_bits_uop_iw_p2_poisoned (_lsu_io_core_exe_0_fresp_bits_uop_iw_p2_poisoned),
.io_core_exe_0_fresp_bits_uop_is_br (_lsu_io_core_exe_0_fresp_bits_uop_is_br),
.io_core_exe_0_fresp_bits_uop_is_jalr (_lsu_io_core_exe_0_fresp_bits_uop_is_jalr),
.io_core_exe_0_fresp_bits_uop_is_jal (_lsu_io_core_exe_0_fresp_bits_uop_is_jal),
.io_core_exe_0_fresp_bits_uop_is_sfb (_lsu_io_core_exe_0_fresp_bits_uop_is_sfb),
.io_core_exe_0_fresp_bits_uop_br_mask (_lsu_io_core_exe_0_fresp_bits_uop_br_mask),
.io_core_exe_0_fresp_bits_uop_br_tag (_lsu_io_core_exe_0_fresp_bits_uop_br_tag),
.io_core_exe_0_fresp_bits_uop_ftq_idx (_lsu_io_core_exe_0_fresp_bits_uop_ftq_idx),
.io_core_exe_0_fresp_bits_uop_edge_inst (_lsu_io_core_exe_0_fresp_bits_uop_edge_inst),
.io_core_exe_0_fresp_bits_uop_pc_lob (_lsu_io_core_exe_0_fresp_bits_uop_pc_lob),
.io_core_exe_0_fresp_bits_uop_taken (_lsu_io_core_exe_0_fresp_bits_uop_taken),
.io_core_exe_0_fresp_bits_uop_imm_packed (_lsu_io_core_exe_0_fresp_bits_uop_imm_packed),
.io_core_exe_0_fresp_bits_uop_csr_addr (_lsu_io_core_exe_0_fresp_bits_uop_csr_addr),
.io_core_exe_0_fresp_bits_uop_rob_idx (_lsu_io_core_exe_0_fresp_bits_uop_rob_idx),
.io_core_exe_0_fresp_bits_uop_ldq_idx (_lsu_io_core_exe_0_fresp_bits_uop_ldq_idx),
.io_core_exe_0_fresp_bits_uop_stq_idx (_lsu_io_core_exe_0_fresp_bits_uop_stq_idx),
.io_core_exe_0_fresp_bits_uop_rxq_idx (_lsu_io_core_exe_0_fresp_bits_uop_rxq_idx),
.io_core_exe_0_fresp_bits_uop_pdst (_lsu_io_core_exe_0_fresp_bits_uop_pdst),
.io_core_exe_0_fresp_bits_uop_prs1 (_lsu_io_core_exe_0_fresp_bits_uop_prs1),
.io_core_exe_0_fresp_bits_uop_prs2 (_lsu_io_core_exe_0_fresp_bits_uop_prs2),
.io_core_exe_0_fresp_bits_uop_prs3 (_lsu_io_core_exe_0_fresp_bits_uop_prs3),
.io_core_exe_0_fresp_bits_uop_ppred (_lsu_io_core_exe_0_fresp_bits_uop_ppred),
.io_core_exe_0_fresp_bits_uop_prs1_busy (_lsu_io_core_exe_0_fresp_bits_uop_prs1_busy),
.io_core_exe_0_fresp_bits_uop_prs2_busy (_lsu_io_core_exe_0_fresp_bits_uop_prs2_busy),
.io_core_exe_0_fresp_bits_uop_prs3_busy (_lsu_io_core_exe_0_fresp_bits_uop_prs3_busy),
.io_core_exe_0_fresp_bits_uop_ppred_busy (_lsu_io_core_exe_0_fresp_bits_uop_ppred_busy),
.io_core_exe_0_fresp_bits_uop_stale_pdst (_lsu_io_core_exe_0_fresp_bits_uop_stale_pdst),
.io_core_exe_0_fresp_bits_uop_exception (_lsu_io_core_exe_0_fresp_bits_uop_exception),
.io_core_exe_0_fresp_bits_uop_exc_cause (_lsu_io_core_exe_0_fresp_bits_uop_exc_cause),
.io_core_exe_0_fresp_bits_uop_bypassable (_lsu_io_core_exe_0_fresp_bits_uop_bypassable),
.io_core_exe_0_fresp_bits_uop_mem_cmd (_lsu_io_core_exe_0_fresp_bits_uop_mem_cmd),
.io_core_exe_0_fresp_bits_uop_mem_size (_lsu_io_core_exe_0_fresp_bits_uop_mem_size),
.io_core_exe_0_fresp_bits_uop_mem_signed (_lsu_io_core_exe_0_fresp_bits_uop_mem_signed),
.io_core_exe_0_fresp_bits_uop_is_fence (_lsu_io_core_exe_0_fresp_bits_uop_is_fence),
.io_core_exe_0_fresp_bits_uop_is_fencei (_lsu_io_core_exe_0_fresp_bits_uop_is_fencei),
.io_core_exe_0_fresp_bits_uop_is_amo (_lsu_io_core_exe_0_fresp_bits_uop_is_amo),
.io_core_exe_0_fresp_bits_uop_uses_ldq (_lsu_io_core_exe_0_fresp_bits_uop_uses_ldq),
.io_core_exe_0_fresp_bits_uop_uses_stq (_lsu_io_core_exe_0_fresp_bits_uop_uses_stq),
.io_core_exe_0_fresp_bits_uop_is_sys_pc2epc (_lsu_io_core_exe_0_fresp_bits_uop_is_sys_pc2epc),
.io_core_exe_0_fresp_bits_uop_is_unique (_lsu_io_core_exe_0_fresp_bits_uop_is_unique),
.io_core_exe_0_fresp_bits_uop_flush_on_commit (_lsu_io_core_exe_0_fresp_bits_uop_flush_on_commit),
.io_core_exe_0_fresp_bits_uop_ldst_is_rs1 (_lsu_io_core_exe_0_fresp_bits_uop_ldst_is_rs1),
.io_core_exe_0_fresp_bits_uop_ldst (_lsu_io_core_exe_0_fresp_bits_uop_ldst),
.io_core_exe_0_fresp_bits_uop_lrs1 (_lsu_io_core_exe_0_fresp_bits_uop_lrs1),
.io_core_exe_0_fresp_bits_uop_lrs2 (_lsu_io_core_exe_0_fresp_bits_uop_lrs2),
.io_core_exe_0_fresp_bits_uop_lrs3 (_lsu_io_core_exe_0_fresp_bits_uop_lrs3),
.io_core_exe_0_fresp_bits_uop_ldst_val (_lsu_io_core_exe_0_fresp_bits_uop_ldst_val),
.io_core_exe_0_fresp_bits_uop_dst_rtype (_lsu_io_core_exe_0_fresp_bits_uop_dst_rtype),
.io_core_exe_0_fresp_bits_uop_lrs1_rtype (_lsu_io_core_exe_0_fresp_bits_uop_lrs1_rtype),
.io_core_exe_0_fresp_bits_uop_lrs2_rtype (_lsu_io_core_exe_0_fresp_bits_uop_lrs2_rtype),
.io_core_exe_0_fresp_bits_uop_frs3_en (_lsu_io_core_exe_0_fresp_bits_uop_frs3_en),
.io_core_exe_0_fresp_bits_uop_fp_val (_lsu_io_core_exe_0_fresp_bits_uop_fp_val),
.io_core_exe_0_fresp_bits_uop_fp_single (_lsu_io_core_exe_0_fresp_bits_uop_fp_single),
.io_core_exe_0_fresp_bits_uop_xcpt_pf_if (_lsu_io_core_exe_0_fresp_bits_uop_xcpt_pf_if),
.io_core_exe_0_fresp_bits_uop_xcpt_ae_if (_lsu_io_core_exe_0_fresp_bits_uop_xcpt_ae_if),
.io_core_exe_0_fresp_bits_uop_xcpt_ma_if (_lsu_io_core_exe_0_fresp_bits_uop_xcpt_ma_if),
.io_core_exe_0_fresp_bits_uop_bp_debug_if (_lsu_io_core_exe_0_fresp_bits_uop_bp_debug_if),
.io_core_exe_0_fresp_bits_uop_bp_xcpt_if (_lsu_io_core_exe_0_fresp_bits_uop_bp_xcpt_if),
.io_core_exe_0_fresp_bits_uop_debug_fsrc (_lsu_io_core_exe_0_fresp_bits_uop_debug_fsrc),
.io_core_exe_0_fresp_bits_uop_debug_tsrc (_lsu_io_core_exe_0_fresp_bits_uop_debug_tsrc),
.io_core_exe_0_fresp_bits_data (_lsu_io_core_exe_0_fresp_bits_data),
.io_core_dis_uops_0_valid (_core_io_lsu_dis_uops_0_valid), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_uopc (_core_io_lsu_dis_uops_0_bits_uopc), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_inst (_core_io_lsu_dis_uops_0_bits_inst), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_debug_inst (_core_io_lsu_dis_uops_0_bits_debug_inst), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_is_rvc (_core_io_lsu_dis_uops_0_bits_is_rvc), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_debug_pc (_core_io_lsu_dis_uops_0_bits_debug_pc), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_iq_type (_core_io_lsu_dis_uops_0_bits_iq_type), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_fu_code (_core_io_lsu_dis_uops_0_bits_fu_code), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_ctrl_br_type (_core_io_lsu_dis_uops_0_bits_ctrl_br_type), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_ctrl_op1_sel (_core_io_lsu_dis_uops_0_bits_ctrl_op1_sel), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_ctrl_op2_sel (_core_io_lsu_dis_uops_0_bits_ctrl_op2_sel), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_ctrl_imm_sel (_core_io_lsu_dis_uops_0_bits_ctrl_imm_sel), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_ctrl_op_fcn (_core_io_lsu_dis_uops_0_bits_ctrl_op_fcn), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_ctrl_fcn_dw (_core_io_lsu_dis_uops_0_bits_ctrl_fcn_dw), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_ctrl_csr_cmd (_core_io_lsu_dis_uops_0_bits_ctrl_csr_cmd), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_ctrl_is_load (_core_io_lsu_dis_uops_0_bits_ctrl_is_load), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_ctrl_is_sta (_core_io_lsu_dis_uops_0_bits_ctrl_is_sta), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_ctrl_is_std (_core_io_lsu_dis_uops_0_bits_ctrl_is_std), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_iw_state (_core_io_lsu_dis_uops_0_bits_iw_state), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_iw_p1_poisoned (_core_io_lsu_dis_uops_0_bits_iw_p1_poisoned), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_iw_p2_poisoned (_core_io_lsu_dis_uops_0_bits_iw_p2_poisoned), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_is_br (_core_io_lsu_dis_uops_0_bits_is_br), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_is_jalr (_core_io_lsu_dis_uops_0_bits_is_jalr), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_is_jal (_core_io_lsu_dis_uops_0_bits_is_jal), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_is_sfb (_core_io_lsu_dis_uops_0_bits_is_sfb), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_br_mask (_core_io_lsu_dis_uops_0_bits_br_mask), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_br_tag (_core_io_lsu_dis_uops_0_bits_br_tag), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_ftq_idx (_core_io_lsu_dis_uops_0_bits_ftq_idx), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_edge_inst (_core_io_lsu_dis_uops_0_bits_edge_inst), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_pc_lob (_core_io_lsu_dis_uops_0_bits_pc_lob), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_taken (_core_io_lsu_dis_uops_0_bits_taken), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_imm_packed (_core_io_lsu_dis_uops_0_bits_imm_packed), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_csr_addr (_core_io_lsu_dis_uops_0_bits_csr_addr), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_rob_idx (_core_io_lsu_dis_uops_0_bits_rob_idx), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_ldq_idx (_core_io_lsu_dis_uops_0_bits_ldq_idx), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_stq_idx (_core_io_lsu_dis_uops_0_bits_stq_idx), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_rxq_idx (_core_io_lsu_dis_uops_0_bits_rxq_idx), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_pdst (_core_io_lsu_dis_uops_0_bits_pdst), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_prs1 (_core_io_lsu_dis_uops_0_bits_prs1), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_prs2 (_core_io_lsu_dis_uops_0_bits_prs2), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_prs3 (_core_io_lsu_dis_uops_0_bits_prs3), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_prs1_busy (_core_io_lsu_dis_uops_0_bits_prs1_busy), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_prs2_busy (_core_io_lsu_dis_uops_0_bits_prs2_busy), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_prs3_busy (_core_io_lsu_dis_uops_0_bits_prs3_busy), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_stale_pdst (_core_io_lsu_dis_uops_0_bits_stale_pdst), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_exception (_core_io_lsu_dis_uops_0_bits_exception), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_exc_cause (_core_io_lsu_dis_uops_0_bits_exc_cause), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_bypassable (_core_io_lsu_dis_uops_0_bits_bypassable), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_mem_cmd (_core_io_lsu_dis_uops_0_bits_mem_cmd), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_mem_size (_core_io_lsu_dis_uops_0_bits_mem_size), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_mem_signed (_core_io_lsu_dis_uops_0_bits_mem_signed), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_is_fence (_core_io_lsu_dis_uops_0_bits_is_fence), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_is_fencei (_core_io_lsu_dis_uops_0_bits_is_fencei), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_is_amo (_core_io_lsu_dis_uops_0_bits_is_amo), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_uses_ldq (_core_io_lsu_dis_uops_0_bits_uses_ldq), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_uses_stq (_core_io_lsu_dis_uops_0_bits_uses_stq), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_is_sys_pc2epc (_core_io_lsu_dis_uops_0_bits_is_sys_pc2epc), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_is_unique (_core_io_lsu_dis_uops_0_bits_is_unique), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_flush_on_commit (_core_io_lsu_dis_uops_0_bits_flush_on_commit), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_ldst_is_rs1 (_core_io_lsu_dis_uops_0_bits_ldst_is_rs1), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_ldst (_core_io_lsu_dis_uops_0_bits_ldst), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_lrs1 (_core_io_lsu_dis_uops_0_bits_lrs1), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_lrs2 (_core_io_lsu_dis_uops_0_bits_lrs2), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_lrs3 (_core_io_lsu_dis_uops_0_bits_lrs3), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_ldst_val (_core_io_lsu_dis_uops_0_bits_ldst_val), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_dst_rtype (_core_io_lsu_dis_uops_0_bits_dst_rtype), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_lrs1_rtype (_core_io_lsu_dis_uops_0_bits_lrs1_rtype), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_lrs2_rtype (_core_io_lsu_dis_uops_0_bits_lrs2_rtype), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_frs3_en (_core_io_lsu_dis_uops_0_bits_frs3_en), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_fp_val (_core_io_lsu_dis_uops_0_bits_fp_val), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_fp_single (_core_io_lsu_dis_uops_0_bits_fp_single), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_xcpt_pf_if (_core_io_lsu_dis_uops_0_bits_xcpt_pf_if), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_xcpt_ae_if (_core_io_lsu_dis_uops_0_bits_xcpt_ae_if), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_xcpt_ma_if (_core_io_lsu_dis_uops_0_bits_xcpt_ma_if), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_bp_debug_if (_core_io_lsu_dis_uops_0_bits_bp_debug_if), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_bp_xcpt_if (_core_io_lsu_dis_uops_0_bits_bp_xcpt_if), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_debug_fsrc (_core_io_lsu_dis_uops_0_bits_debug_fsrc), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_debug_tsrc (_core_io_lsu_dis_uops_0_bits_debug_tsrc), // @[tile.scala:159:20]
.io_core_dis_uops_1_valid (_core_io_lsu_dis_uops_1_valid), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_uopc (_core_io_lsu_dis_uops_1_bits_uopc), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_inst (_core_io_lsu_dis_uops_1_bits_inst), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_debug_inst (_core_io_lsu_dis_uops_1_bits_debug_inst), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_is_rvc (_core_io_lsu_dis_uops_1_bits_is_rvc), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_debug_pc (_core_io_lsu_dis_uops_1_bits_debug_pc), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_iq_type (_core_io_lsu_dis_uops_1_bits_iq_type), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_fu_code (_core_io_lsu_dis_uops_1_bits_fu_code), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_ctrl_br_type (_core_io_lsu_dis_uops_1_bits_ctrl_br_type), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_ctrl_op1_sel (_core_io_lsu_dis_uops_1_bits_ctrl_op1_sel), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_ctrl_op2_sel (_core_io_lsu_dis_uops_1_bits_ctrl_op2_sel), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_ctrl_imm_sel (_core_io_lsu_dis_uops_1_bits_ctrl_imm_sel), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_ctrl_op_fcn (_core_io_lsu_dis_uops_1_bits_ctrl_op_fcn), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_ctrl_fcn_dw (_core_io_lsu_dis_uops_1_bits_ctrl_fcn_dw), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_ctrl_csr_cmd (_core_io_lsu_dis_uops_1_bits_ctrl_csr_cmd), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_ctrl_is_load (_core_io_lsu_dis_uops_1_bits_ctrl_is_load), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_ctrl_is_sta (_core_io_lsu_dis_uops_1_bits_ctrl_is_sta), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_ctrl_is_std (_core_io_lsu_dis_uops_1_bits_ctrl_is_std), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_iw_state (_core_io_lsu_dis_uops_1_bits_iw_state), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_iw_p1_poisoned (_core_io_lsu_dis_uops_1_bits_iw_p1_poisoned), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_iw_p2_poisoned (_core_io_lsu_dis_uops_1_bits_iw_p2_poisoned), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_is_br (_core_io_lsu_dis_uops_1_bits_is_br), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_is_jalr (_core_io_lsu_dis_uops_1_bits_is_jalr), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_is_jal (_core_io_lsu_dis_uops_1_bits_is_jal), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_is_sfb (_core_io_lsu_dis_uops_1_bits_is_sfb), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_br_mask (_core_io_lsu_dis_uops_1_bits_br_mask), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_br_tag (_core_io_lsu_dis_uops_1_bits_br_tag), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_ftq_idx (_core_io_lsu_dis_uops_1_bits_ftq_idx), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_edge_inst (_core_io_lsu_dis_uops_1_bits_edge_inst), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_pc_lob (_core_io_lsu_dis_uops_1_bits_pc_lob), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_taken (_core_io_lsu_dis_uops_1_bits_taken), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_imm_packed (_core_io_lsu_dis_uops_1_bits_imm_packed), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_csr_addr (_core_io_lsu_dis_uops_1_bits_csr_addr), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_rob_idx (_core_io_lsu_dis_uops_1_bits_rob_idx), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_ldq_idx (_core_io_lsu_dis_uops_1_bits_ldq_idx), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_stq_idx (_core_io_lsu_dis_uops_1_bits_stq_idx), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_rxq_idx (_core_io_lsu_dis_uops_1_bits_rxq_idx), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_pdst (_core_io_lsu_dis_uops_1_bits_pdst), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_prs1 (_core_io_lsu_dis_uops_1_bits_prs1), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_prs2 (_core_io_lsu_dis_uops_1_bits_prs2), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_prs3 (_core_io_lsu_dis_uops_1_bits_prs3), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_prs1_busy (_core_io_lsu_dis_uops_1_bits_prs1_busy), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_prs2_busy (_core_io_lsu_dis_uops_1_bits_prs2_busy), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_prs3_busy (_core_io_lsu_dis_uops_1_bits_prs3_busy), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_stale_pdst (_core_io_lsu_dis_uops_1_bits_stale_pdst), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_exception (_core_io_lsu_dis_uops_1_bits_exception), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_exc_cause (_core_io_lsu_dis_uops_1_bits_exc_cause), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_bypassable (_core_io_lsu_dis_uops_1_bits_bypassable), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_mem_cmd (_core_io_lsu_dis_uops_1_bits_mem_cmd), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_mem_size (_core_io_lsu_dis_uops_1_bits_mem_size), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_mem_signed (_core_io_lsu_dis_uops_1_bits_mem_signed), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_is_fence (_core_io_lsu_dis_uops_1_bits_is_fence), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_is_fencei (_core_io_lsu_dis_uops_1_bits_is_fencei), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_is_amo (_core_io_lsu_dis_uops_1_bits_is_amo), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_uses_ldq (_core_io_lsu_dis_uops_1_bits_uses_ldq), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_uses_stq (_core_io_lsu_dis_uops_1_bits_uses_stq), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_is_sys_pc2epc (_core_io_lsu_dis_uops_1_bits_is_sys_pc2epc), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_is_unique (_core_io_lsu_dis_uops_1_bits_is_unique), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_flush_on_commit (_core_io_lsu_dis_uops_1_bits_flush_on_commit), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_ldst_is_rs1 (_core_io_lsu_dis_uops_1_bits_ldst_is_rs1), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_ldst (_core_io_lsu_dis_uops_1_bits_ldst), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_lrs1 (_core_io_lsu_dis_uops_1_bits_lrs1), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_lrs2 (_core_io_lsu_dis_uops_1_bits_lrs2), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_lrs3 (_core_io_lsu_dis_uops_1_bits_lrs3), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_ldst_val (_core_io_lsu_dis_uops_1_bits_ldst_val), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_dst_rtype (_core_io_lsu_dis_uops_1_bits_dst_rtype), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_lrs1_rtype (_core_io_lsu_dis_uops_1_bits_lrs1_rtype), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_lrs2_rtype (_core_io_lsu_dis_uops_1_bits_lrs2_rtype), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_frs3_en (_core_io_lsu_dis_uops_1_bits_frs3_en), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_fp_val (_core_io_lsu_dis_uops_1_bits_fp_val), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_fp_single (_core_io_lsu_dis_uops_1_bits_fp_single), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_xcpt_pf_if (_core_io_lsu_dis_uops_1_bits_xcpt_pf_if), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_xcpt_ae_if (_core_io_lsu_dis_uops_1_bits_xcpt_ae_if), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_xcpt_ma_if (_core_io_lsu_dis_uops_1_bits_xcpt_ma_if), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_bp_debug_if (_core_io_lsu_dis_uops_1_bits_bp_debug_if), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_bp_xcpt_if (_core_io_lsu_dis_uops_1_bits_bp_xcpt_if), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_debug_fsrc (_core_io_lsu_dis_uops_1_bits_debug_fsrc), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_debug_tsrc (_core_io_lsu_dis_uops_1_bits_debug_tsrc), // @[tile.scala:159:20]
.io_core_dis_uops_2_valid (_core_io_lsu_dis_uops_2_valid), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_uopc (_core_io_lsu_dis_uops_2_bits_uopc), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_inst (_core_io_lsu_dis_uops_2_bits_inst), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_debug_inst (_core_io_lsu_dis_uops_2_bits_debug_inst), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_is_rvc (_core_io_lsu_dis_uops_2_bits_is_rvc), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_debug_pc (_core_io_lsu_dis_uops_2_bits_debug_pc), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_iq_type (_core_io_lsu_dis_uops_2_bits_iq_type), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_fu_code (_core_io_lsu_dis_uops_2_bits_fu_code), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_ctrl_br_type (_core_io_lsu_dis_uops_2_bits_ctrl_br_type), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_ctrl_op1_sel (_core_io_lsu_dis_uops_2_bits_ctrl_op1_sel), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_ctrl_op2_sel (_core_io_lsu_dis_uops_2_bits_ctrl_op2_sel), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_ctrl_imm_sel (_core_io_lsu_dis_uops_2_bits_ctrl_imm_sel), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_ctrl_op_fcn (_core_io_lsu_dis_uops_2_bits_ctrl_op_fcn), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_ctrl_fcn_dw (_core_io_lsu_dis_uops_2_bits_ctrl_fcn_dw), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_ctrl_csr_cmd (_core_io_lsu_dis_uops_2_bits_ctrl_csr_cmd), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_ctrl_is_load (_core_io_lsu_dis_uops_2_bits_ctrl_is_load), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_ctrl_is_sta (_core_io_lsu_dis_uops_2_bits_ctrl_is_sta), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_ctrl_is_std (_core_io_lsu_dis_uops_2_bits_ctrl_is_std), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_iw_state (_core_io_lsu_dis_uops_2_bits_iw_state), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_iw_p1_poisoned (_core_io_lsu_dis_uops_2_bits_iw_p1_poisoned), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_iw_p2_poisoned (_core_io_lsu_dis_uops_2_bits_iw_p2_poisoned), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_is_br (_core_io_lsu_dis_uops_2_bits_is_br), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_is_jalr (_core_io_lsu_dis_uops_2_bits_is_jalr), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_is_jal (_core_io_lsu_dis_uops_2_bits_is_jal), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_is_sfb (_core_io_lsu_dis_uops_2_bits_is_sfb), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_br_mask (_core_io_lsu_dis_uops_2_bits_br_mask), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_br_tag (_core_io_lsu_dis_uops_2_bits_br_tag), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_ftq_idx (_core_io_lsu_dis_uops_2_bits_ftq_idx), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_edge_inst (_core_io_lsu_dis_uops_2_bits_edge_inst), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_pc_lob (_core_io_lsu_dis_uops_2_bits_pc_lob), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_taken (_core_io_lsu_dis_uops_2_bits_taken), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_imm_packed (_core_io_lsu_dis_uops_2_bits_imm_packed), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_csr_addr (_core_io_lsu_dis_uops_2_bits_csr_addr), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_rob_idx (_core_io_lsu_dis_uops_2_bits_rob_idx), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_ldq_idx (_core_io_lsu_dis_uops_2_bits_ldq_idx), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_stq_idx (_core_io_lsu_dis_uops_2_bits_stq_idx), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_rxq_idx (_core_io_lsu_dis_uops_2_bits_rxq_idx), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_pdst (_core_io_lsu_dis_uops_2_bits_pdst), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_prs1 (_core_io_lsu_dis_uops_2_bits_prs1), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_prs2 (_core_io_lsu_dis_uops_2_bits_prs2), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_prs3 (_core_io_lsu_dis_uops_2_bits_prs3), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_prs1_busy (_core_io_lsu_dis_uops_2_bits_prs1_busy), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_prs2_busy (_core_io_lsu_dis_uops_2_bits_prs2_busy), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_prs3_busy (_core_io_lsu_dis_uops_2_bits_prs3_busy), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_stale_pdst (_core_io_lsu_dis_uops_2_bits_stale_pdst), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_exception (_core_io_lsu_dis_uops_2_bits_exception), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_exc_cause (_core_io_lsu_dis_uops_2_bits_exc_cause), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_bypassable (_core_io_lsu_dis_uops_2_bits_bypassable), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_mem_cmd (_core_io_lsu_dis_uops_2_bits_mem_cmd), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_mem_size (_core_io_lsu_dis_uops_2_bits_mem_size), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_mem_signed (_core_io_lsu_dis_uops_2_bits_mem_signed), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_is_fence (_core_io_lsu_dis_uops_2_bits_is_fence), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_is_fencei (_core_io_lsu_dis_uops_2_bits_is_fencei), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_is_amo (_core_io_lsu_dis_uops_2_bits_is_amo), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_uses_ldq (_core_io_lsu_dis_uops_2_bits_uses_ldq), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_uses_stq (_core_io_lsu_dis_uops_2_bits_uses_stq), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_is_sys_pc2epc (_core_io_lsu_dis_uops_2_bits_is_sys_pc2epc), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_is_unique (_core_io_lsu_dis_uops_2_bits_is_unique), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_flush_on_commit (_core_io_lsu_dis_uops_2_bits_flush_on_commit), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_ldst_is_rs1 (_core_io_lsu_dis_uops_2_bits_ldst_is_rs1), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_ldst (_core_io_lsu_dis_uops_2_bits_ldst), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_lrs1 (_core_io_lsu_dis_uops_2_bits_lrs1), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_lrs2 (_core_io_lsu_dis_uops_2_bits_lrs2), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_lrs3 (_core_io_lsu_dis_uops_2_bits_lrs3), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_ldst_val (_core_io_lsu_dis_uops_2_bits_ldst_val), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_dst_rtype (_core_io_lsu_dis_uops_2_bits_dst_rtype), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_lrs1_rtype (_core_io_lsu_dis_uops_2_bits_lrs1_rtype), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_lrs2_rtype (_core_io_lsu_dis_uops_2_bits_lrs2_rtype), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_frs3_en (_core_io_lsu_dis_uops_2_bits_frs3_en), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_fp_val (_core_io_lsu_dis_uops_2_bits_fp_val), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_fp_single (_core_io_lsu_dis_uops_2_bits_fp_single), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_xcpt_pf_if (_core_io_lsu_dis_uops_2_bits_xcpt_pf_if), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_xcpt_ae_if (_core_io_lsu_dis_uops_2_bits_xcpt_ae_if), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_xcpt_ma_if (_core_io_lsu_dis_uops_2_bits_xcpt_ma_if), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_bp_debug_if (_core_io_lsu_dis_uops_2_bits_bp_debug_if), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_bp_xcpt_if (_core_io_lsu_dis_uops_2_bits_bp_xcpt_if), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_debug_fsrc (_core_io_lsu_dis_uops_2_bits_debug_fsrc), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_debug_tsrc (_core_io_lsu_dis_uops_2_bits_debug_tsrc), // @[tile.scala:159:20]
.io_core_dis_ldq_idx_0 (_lsu_io_core_dis_ldq_idx_0),
.io_core_dis_ldq_idx_1 (_lsu_io_core_dis_ldq_idx_1),
.io_core_dis_ldq_idx_2 (_lsu_io_core_dis_ldq_idx_2),
.io_core_dis_stq_idx_0 (_lsu_io_core_dis_stq_idx_0),
.io_core_dis_stq_idx_1 (_lsu_io_core_dis_stq_idx_1),
.io_core_dis_stq_idx_2 (_lsu_io_core_dis_stq_idx_2),
.io_core_ldq_full_0 (_lsu_io_core_ldq_full_0),
.io_core_ldq_full_1 (_lsu_io_core_ldq_full_1),
.io_core_ldq_full_2 (_lsu_io_core_ldq_full_2),
.io_core_stq_full_0 (_lsu_io_core_stq_full_0),
.io_core_stq_full_1 (_lsu_io_core_stq_full_1),
.io_core_stq_full_2 (_lsu_io_core_stq_full_2),
.io_core_fp_stdata_ready (_lsu_io_core_fp_stdata_ready),
.io_core_fp_stdata_valid (_core_io_lsu_fp_stdata_valid), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_uopc (_core_io_lsu_fp_stdata_bits_uop_uopc), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_inst (_core_io_lsu_fp_stdata_bits_uop_inst), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_debug_inst (_core_io_lsu_fp_stdata_bits_uop_debug_inst), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_is_rvc (_core_io_lsu_fp_stdata_bits_uop_is_rvc), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_debug_pc (_core_io_lsu_fp_stdata_bits_uop_debug_pc), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_iq_type (_core_io_lsu_fp_stdata_bits_uop_iq_type), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_fu_code (_core_io_lsu_fp_stdata_bits_uop_fu_code), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_ctrl_br_type (_core_io_lsu_fp_stdata_bits_uop_ctrl_br_type), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_ctrl_op1_sel (_core_io_lsu_fp_stdata_bits_uop_ctrl_op1_sel), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_ctrl_op2_sel (_core_io_lsu_fp_stdata_bits_uop_ctrl_op2_sel), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_ctrl_imm_sel (_core_io_lsu_fp_stdata_bits_uop_ctrl_imm_sel), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_ctrl_op_fcn (_core_io_lsu_fp_stdata_bits_uop_ctrl_op_fcn), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_ctrl_fcn_dw (_core_io_lsu_fp_stdata_bits_uop_ctrl_fcn_dw), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_ctrl_csr_cmd (_core_io_lsu_fp_stdata_bits_uop_ctrl_csr_cmd), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_ctrl_is_load (_core_io_lsu_fp_stdata_bits_uop_ctrl_is_load), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_ctrl_is_sta (_core_io_lsu_fp_stdata_bits_uop_ctrl_is_sta), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_ctrl_is_std (_core_io_lsu_fp_stdata_bits_uop_ctrl_is_std), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_iw_state (_core_io_lsu_fp_stdata_bits_uop_iw_state), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_iw_p1_poisoned (_core_io_lsu_fp_stdata_bits_uop_iw_p1_poisoned), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_iw_p2_poisoned (_core_io_lsu_fp_stdata_bits_uop_iw_p2_poisoned), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_is_br (_core_io_lsu_fp_stdata_bits_uop_is_br), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_is_jalr (_core_io_lsu_fp_stdata_bits_uop_is_jalr), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_is_jal (_core_io_lsu_fp_stdata_bits_uop_is_jal), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_is_sfb (_core_io_lsu_fp_stdata_bits_uop_is_sfb), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_br_mask (_core_io_lsu_fp_stdata_bits_uop_br_mask), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_br_tag (_core_io_lsu_fp_stdata_bits_uop_br_tag), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_ftq_idx (_core_io_lsu_fp_stdata_bits_uop_ftq_idx), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_edge_inst (_core_io_lsu_fp_stdata_bits_uop_edge_inst), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_pc_lob (_core_io_lsu_fp_stdata_bits_uop_pc_lob), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_taken (_core_io_lsu_fp_stdata_bits_uop_taken), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_imm_packed (_core_io_lsu_fp_stdata_bits_uop_imm_packed), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_csr_addr (_core_io_lsu_fp_stdata_bits_uop_csr_addr), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_rob_idx (_core_io_lsu_fp_stdata_bits_uop_rob_idx), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_ldq_idx (_core_io_lsu_fp_stdata_bits_uop_ldq_idx), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_stq_idx (_core_io_lsu_fp_stdata_bits_uop_stq_idx), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_rxq_idx (_core_io_lsu_fp_stdata_bits_uop_rxq_idx), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_pdst (_core_io_lsu_fp_stdata_bits_uop_pdst), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_prs1 (_core_io_lsu_fp_stdata_bits_uop_prs1), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_prs2 (_core_io_lsu_fp_stdata_bits_uop_prs2), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_prs3 (_core_io_lsu_fp_stdata_bits_uop_prs3), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_ppred (_core_io_lsu_fp_stdata_bits_uop_ppred), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_prs1_busy (_core_io_lsu_fp_stdata_bits_uop_prs1_busy), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_prs2_busy (_core_io_lsu_fp_stdata_bits_uop_prs2_busy), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_prs3_busy (_core_io_lsu_fp_stdata_bits_uop_prs3_busy), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_ppred_busy (_core_io_lsu_fp_stdata_bits_uop_ppred_busy), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_stale_pdst (_core_io_lsu_fp_stdata_bits_uop_stale_pdst), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_exception (_core_io_lsu_fp_stdata_bits_uop_exception), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_exc_cause (_core_io_lsu_fp_stdata_bits_uop_exc_cause), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_bypassable (_core_io_lsu_fp_stdata_bits_uop_bypassable), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_mem_cmd (_core_io_lsu_fp_stdata_bits_uop_mem_cmd), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_mem_size (_core_io_lsu_fp_stdata_bits_uop_mem_size), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_mem_signed (_core_io_lsu_fp_stdata_bits_uop_mem_signed), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_is_fence (_core_io_lsu_fp_stdata_bits_uop_is_fence), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_is_fencei (_core_io_lsu_fp_stdata_bits_uop_is_fencei), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_is_amo (_core_io_lsu_fp_stdata_bits_uop_is_amo), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_uses_ldq (_core_io_lsu_fp_stdata_bits_uop_uses_ldq), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_uses_stq (_core_io_lsu_fp_stdata_bits_uop_uses_stq), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_is_sys_pc2epc (_core_io_lsu_fp_stdata_bits_uop_is_sys_pc2epc), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_is_unique (_core_io_lsu_fp_stdata_bits_uop_is_unique), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_flush_on_commit (_core_io_lsu_fp_stdata_bits_uop_flush_on_commit), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_ldst_is_rs1 (_core_io_lsu_fp_stdata_bits_uop_ldst_is_rs1), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_ldst (_core_io_lsu_fp_stdata_bits_uop_ldst), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_lrs1 (_core_io_lsu_fp_stdata_bits_uop_lrs1), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_lrs2 (_core_io_lsu_fp_stdata_bits_uop_lrs2), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_lrs3 (_core_io_lsu_fp_stdata_bits_uop_lrs3), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_ldst_val (_core_io_lsu_fp_stdata_bits_uop_ldst_val), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_dst_rtype (_core_io_lsu_fp_stdata_bits_uop_dst_rtype), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_lrs1_rtype (_core_io_lsu_fp_stdata_bits_uop_lrs1_rtype), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_lrs2_rtype (_core_io_lsu_fp_stdata_bits_uop_lrs2_rtype), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_frs3_en (_core_io_lsu_fp_stdata_bits_uop_frs3_en), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_fp_val (_core_io_lsu_fp_stdata_bits_uop_fp_val), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_fp_single (_core_io_lsu_fp_stdata_bits_uop_fp_single), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_xcpt_pf_if (_core_io_lsu_fp_stdata_bits_uop_xcpt_pf_if), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_xcpt_ae_if (_core_io_lsu_fp_stdata_bits_uop_xcpt_ae_if), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_xcpt_ma_if (_core_io_lsu_fp_stdata_bits_uop_xcpt_ma_if), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_bp_debug_if (_core_io_lsu_fp_stdata_bits_uop_bp_debug_if), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_bp_xcpt_if (_core_io_lsu_fp_stdata_bits_uop_bp_xcpt_if), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_debug_fsrc (_core_io_lsu_fp_stdata_bits_uop_debug_fsrc), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_debug_tsrc (_core_io_lsu_fp_stdata_bits_uop_debug_tsrc), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_data (_core_io_lsu_fp_stdata_bits_data), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_predicated (_core_io_lsu_fp_stdata_bits_predicated), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_valid (_core_io_lsu_fp_stdata_bits_fflags_valid), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_uopc (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_uopc), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_inst (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_inst), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_debug_inst (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_debug_inst), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_is_rvc (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_rvc), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_debug_pc (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_debug_pc), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_iq_type (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_iq_type), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_fu_code (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_fu_code), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_ctrl_br_type (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_br_type), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_ctrl_op1_sel (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op1_sel), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_ctrl_op2_sel (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op2_sel), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_ctrl_imm_sel (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_imm_sel), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_ctrl_op_fcn (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op_fcn), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_ctrl_fcn_dw (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_fcn_dw), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_ctrl_csr_cmd (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_csr_cmd), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_ctrl_is_load (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_load), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_ctrl_is_sta (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_sta), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_ctrl_is_std (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_std), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_iw_state (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_iw_state), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_iw_p1_poisoned (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_iw_p1_poisoned), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_iw_p2_poisoned (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_iw_p2_poisoned), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_is_br (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_br), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_is_jalr (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_jalr), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_is_jal (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_jal), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_is_sfb (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_sfb), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_br_mask (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_br_mask), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_br_tag (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_br_tag), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_ftq_idx (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ftq_idx), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_edge_inst (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_edge_inst), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_pc_lob (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_pc_lob), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_taken (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_taken), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_imm_packed (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_imm_packed), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_csr_addr (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_csr_addr), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_rob_idx (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_rob_idx), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_ldq_idx (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ldq_idx), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_stq_idx (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_stq_idx), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_rxq_idx (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_rxq_idx), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_pdst (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_pdst), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_prs1 (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_prs1), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_prs2 (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_prs2), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_prs3 (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_prs3), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_ppred (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ppred), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_prs1_busy (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_prs1_busy), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_prs2_busy (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_prs2_busy), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_prs3_busy (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_prs3_busy), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_ppred_busy (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ppred_busy), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_stale_pdst (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_stale_pdst), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_exception (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_exception), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_exc_cause (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_exc_cause), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_bypassable (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_bypassable), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_mem_cmd (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_mem_cmd), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_mem_size (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_mem_size), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_mem_signed (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_mem_signed), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_is_fence (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_fence), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_is_fencei (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_fencei), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_is_amo (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_amo), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_uses_ldq (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_uses_ldq), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_uses_stq (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_uses_stq), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_is_sys_pc2epc (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_sys_pc2epc), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_is_unique (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_unique), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_flush_on_commit (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_flush_on_commit), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_ldst_is_rs1 (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ldst_is_rs1), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_ldst (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ldst), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_lrs1 (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_lrs1), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_lrs2 (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_lrs2), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_lrs3 (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_lrs3), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_ldst_val (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ldst_val), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_dst_rtype (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_dst_rtype), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_lrs1_rtype (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_lrs1_rtype), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_lrs2_rtype (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_lrs2_rtype), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_frs3_en (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_frs3_en), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_fp_val (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_fp_val), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_fp_single (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_fp_single), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_xcpt_pf_if (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_pf_if), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_xcpt_ae_if (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_ae_if), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_xcpt_ma_if (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_ma_if), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_bp_debug_if (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_bp_debug_if), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_bp_xcpt_if (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_bp_xcpt_if), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_debug_fsrc (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_debug_fsrc), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_debug_tsrc (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_debug_tsrc), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_flags (_core_io_lsu_fp_stdata_bits_fflags_bits_flags), // @[tile.scala:159:20]
.io_core_commit_valids_0 (_core_io_lsu_commit_valids_0), // @[tile.scala:159:20]
.io_core_commit_valids_1 (_core_io_lsu_commit_valids_1), // @[tile.scala:159:20]
.io_core_commit_valids_2 (_core_io_lsu_commit_valids_2), // @[tile.scala:159:20]
.io_core_commit_arch_valids_0 (_core_io_lsu_commit_arch_valids_0), // @[tile.scala:159:20]
.io_core_commit_arch_valids_1 (_core_io_lsu_commit_arch_valids_1), // @[tile.scala:159:20]
.io_core_commit_arch_valids_2 (_core_io_lsu_commit_arch_valids_2), // @[tile.scala:159:20]
.io_core_commit_uops_0_uopc (_core_io_lsu_commit_uops_0_uopc), // @[tile.scala:159:20]
.io_core_commit_uops_0_inst (_core_io_lsu_commit_uops_0_inst), // @[tile.scala:159:20]
.io_core_commit_uops_0_debug_inst (_core_io_lsu_commit_uops_0_debug_inst), // @[tile.scala:159:20]
.io_core_commit_uops_0_is_rvc (_core_io_lsu_commit_uops_0_is_rvc), // @[tile.scala:159:20]
.io_core_commit_uops_0_debug_pc (_core_io_lsu_commit_uops_0_debug_pc), // @[tile.scala:159:20]
.io_core_commit_uops_0_iq_type (_core_io_lsu_commit_uops_0_iq_type), // @[tile.scala:159:20]
.io_core_commit_uops_0_fu_code (_core_io_lsu_commit_uops_0_fu_code), // @[tile.scala:159:20]
.io_core_commit_uops_0_ctrl_br_type (_core_io_lsu_commit_uops_0_ctrl_br_type), // @[tile.scala:159:20]
.io_core_commit_uops_0_ctrl_op1_sel (_core_io_lsu_commit_uops_0_ctrl_op1_sel), // @[tile.scala:159:20]
.io_core_commit_uops_0_ctrl_op2_sel (_core_io_lsu_commit_uops_0_ctrl_op2_sel), // @[tile.scala:159:20]
.io_core_commit_uops_0_ctrl_imm_sel (_core_io_lsu_commit_uops_0_ctrl_imm_sel), // @[tile.scala:159:20]
.io_core_commit_uops_0_ctrl_op_fcn (_core_io_lsu_commit_uops_0_ctrl_op_fcn), // @[tile.scala:159:20]
.io_core_commit_uops_0_ctrl_fcn_dw (_core_io_lsu_commit_uops_0_ctrl_fcn_dw), // @[tile.scala:159:20]
.io_core_commit_uops_0_ctrl_csr_cmd (_core_io_lsu_commit_uops_0_ctrl_csr_cmd), // @[tile.scala:159:20]
.io_core_commit_uops_0_ctrl_is_load (_core_io_lsu_commit_uops_0_ctrl_is_load), // @[tile.scala:159:20]
.io_core_commit_uops_0_ctrl_is_sta (_core_io_lsu_commit_uops_0_ctrl_is_sta), // @[tile.scala:159:20]
.io_core_commit_uops_0_ctrl_is_std (_core_io_lsu_commit_uops_0_ctrl_is_std), // @[tile.scala:159:20]
.io_core_commit_uops_0_iw_state (_core_io_lsu_commit_uops_0_iw_state), // @[tile.scala:159:20]
.io_core_commit_uops_0_iw_p1_poisoned (_core_io_lsu_commit_uops_0_iw_p1_poisoned), // @[tile.scala:159:20]
.io_core_commit_uops_0_iw_p2_poisoned (_core_io_lsu_commit_uops_0_iw_p2_poisoned), // @[tile.scala:159:20]
.io_core_commit_uops_0_is_br (_core_io_lsu_commit_uops_0_is_br), // @[tile.scala:159:20]
.io_core_commit_uops_0_is_jalr (_core_io_lsu_commit_uops_0_is_jalr), // @[tile.scala:159:20]
.io_core_commit_uops_0_is_jal (_core_io_lsu_commit_uops_0_is_jal), // @[tile.scala:159:20]
.io_core_commit_uops_0_is_sfb (_core_io_lsu_commit_uops_0_is_sfb), // @[tile.scala:159:20]
.io_core_commit_uops_0_br_mask (_core_io_lsu_commit_uops_0_br_mask), // @[tile.scala:159:20]
.io_core_commit_uops_0_br_tag (_core_io_lsu_commit_uops_0_br_tag), // @[tile.scala:159:20]
.io_core_commit_uops_0_ftq_idx (_core_io_lsu_commit_uops_0_ftq_idx), // @[tile.scala:159:20]
.io_core_commit_uops_0_edge_inst (_core_io_lsu_commit_uops_0_edge_inst), // @[tile.scala:159:20]
.io_core_commit_uops_0_pc_lob (_core_io_lsu_commit_uops_0_pc_lob), // @[tile.scala:159:20]
.io_core_commit_uops_0_taken (_core_io_lsu_commit_uops_0_taken), // @[tile.scala:159:20]
.io_core_commit_uops_0_imm_packed (_core_io_lsu_commit_uops_0_imm_packed), // @[tile.scala:159:20]
.io_core_commit_uops_0_csr_addr (_core_io_lsu_commit_uops_0_csr_addr), // @[tile.scala:159:20]
.io_core_commit_uops_0_rob_idx (_core_io_lsu_commit_uops_0_rob_idx), // @[tile.scala:159:20]
.io_core_commit_uops_0_ldq_idx (_core_io_lsu_commit_uops_0_ldq_idx), // @[tile.scala:159:20]
.io_core_commit_uops_0_stq_idx (_core_io_lsu_commit_uops_0_stq_idx), // @[tile.scala:159:20]
.io_core_commit_uops_0_rxq_idx (_core_io_lsu_commit_uops_0_rxq_idx), // @[tile.scala:159:20]
.io_core_commit_uops_0_pdst (_core_io_lsu_commit_uops_0_pdst), // @[tile.scala:159:20]
.io_core_commit_uops_0_prs1 (_core_io_lsu_commit_uops_0_prs1), // @[tile.scala:159:20]
.io_core_commit_uops_0_prs2 (_core_io_lsu_commit_uops_0_prs2), // @[tile.scala:159:20]
.io_core_commit_uops_0_prs3 (_core_io_lsu_commit_uops_0_prs3), // @[tile.scala:159:20]
.io_core_commit_uops_0_ppred (_core_io_lsu_commit_uops_0_ppred), // @[tile.scala:159:20]
.io_core_commit_uops_0_prs1_busy (_core_io_lsu_commit_uops_0_prs1_busy), // @[tile.scala:159:20]
.io_core_commit_uops_0_prs2_busy (_core_io_lsu_commit_uops_0_prs2_busy), // @[tile.scala:159:20]
.io_core_commit_uops_0_prs3_busy (_core_io_lsu_commit_uops_0_prs3_busy), // @[tile.scala:159:20]
.io_core_commit_uops_0_ppred_busy (_core_io_lsu_commit_uops_0_ppred_busy), // @[tile.scala:159:20]
.io_core_commit_uops_0_stale_pdst (_core_io_lsu_commit_uops_0_stale_pdst), // @[tile.scala:159:20]
.io_core_commit_uops_0_exception (_core_io_lsu_commit_uops_0_exception), // @[tile.scala:159:20]
.io_core_commit_uops_0_exc_cause (_core_io_lsu_commit_uops_0_exc_cause), // @[tile.scala:159:20]
.io_core_commit_uops_0_bypassable (_core_io_lsu_commit_uops_0_bypassable), // @[tile.scala:159:20]
.io_core_commit_uops_0_mem_cmd (_core_io_lsu_commit_uops_0_mem_cmd), // @[tile.scala:159:20]
.io_core_commit_uops_0_mem_size (_core_io_lsu_commit_uops_0_mem_size), // @[tile.scala:159:20]
.io_core_commit_uops_0_mem_signed (_core_io_lsu_commit_uops_0_mem_signed), // @[tile.scala:159:20]
.io_core_commit_uops_0_is_fence (_core_io_lsu_commit_uops_0_is_fence), // @[tile.scala:159:20]
.io_core_commit_uops_0_is_fencei (_core_io_lsu_commit_uops_0_is_fencei), // @[tile.scala:159:20]
.io_core_commit_uops_0_is_amo (_core_io_lsu_commit_uops_0_is_amo), // @[tile.scala:159:20]
.io_core_commit_uops_0_uses_ldq (_core_io_lsu_commit_uops_0_uses_ldq), // @[tile.scala:159:20]
.io_core_commit_uops_0_uses_stq (_core_io_lsu_commit_uops_0_uses_stq), // @[tile.scala:159:20]
.io_core_commit_uops_0_is_sys_pc2epc (_core_io_lsu_commit_uops_0_is_sys_pc2epc), // @[tile.scala:159:20]
.io_core_commit_uops_0_is_unique (_core_io_lsu_commit_uops_0_is_unique), // @[tile.scala:159:20]
.io_core_commit_uops_0_flush_on_commit (_core_io_lsu_commit_uops_0_flush_on_commit), // @[tile.scala:159:20]
.io_core_commit_uops_0_ldst_is_rs1 (_core_io_lsu_commit_uops_0_ldst_is_rs1), // @[tile.scala:159:20]
.io_core_commit_uops_0_ldst (_core_io_lsu_commit_uops_0_ldst), // @[tile.scala:159:20]
.io_core_commit_uops_0_lrs1 (_core_io_lsu_commit_uops_0_lrs1), // @[tile.scala:159:20]
.io_core_commit_uops_0_lrs2 (_core_io_lsu_commit_uops_0_lrs2), // @[tile.scala:159:20]
.io_core_commit_uops_0_lrs3 (_core_io_lsu_commit_uops_0_lrs3), // @[tile.scala:159:20]
.io_core_commit_uops_0_ldst_val (_core_io_lsu_commit_uops_0_ldst_val), // @[tile.scala:159:20]
.io_core_commit_uops_0_dst_rtype (_core_io_lsu_commit_uops_0_dst_rtype), // @[tile.scala:159:20]
.io_core_commit_uops_0_lrs1_rtype (_core_io_lsu_commit_uops_0_lrs1_rtype), // @[tile.scala:159:20]
.io_core_commit_uops_0_lrs2_rtype (_core_io_lsu_commit_uops_0_lrs2_rtype), // @[tile.scala:159:20]
.io_core_commit_uops_0_frs3_en (_core_io_lsu_commit_uops_0_frs3_en), // @[tile.scala:159:20]
.io_core_commit_uops_0_fp_val (_core_io_lsu_commit_uops_0_fp_val), // @[tile.scala:159:20]
.io_core_commit_uops_0_fp_single (_core_io_lsu_commit_uops_0_fp_single), // @[tile.scala:159:20]
.io_core_commit_uops_0_xcpt_pf_if (_core_io_lsu_commit_uops_0_xcpt_pf_if), // @[tile.scala:159:20]
.io_core_commit_uops_0_xcpt_ae_if (_core_io_lsu_commit_uops_0_xcpt_ae_if), // @[tile.scala:159:20]
.io_core_commit_uops_0_xcpt_ma_if (_core_io_lsu_commit_uops_0_xcpt_ma_if), // @[tile.scala:159:20]
.io_core_commit_uops_0_bp_debug_if (_core_io_lsu_commit_uops_0_bp_debug_if), // @[tile.scala:159:20]
.io_core_commit_uops_0_bp_xcpt_if (_core_io_lsu_commit_uops_0_bp_xcpt_if), // @[tile.scala:159:20]
.io_core_commit_uops_0_debug_fsrc (_core_io_lsu_commit_uops_0_debug_fsrc), // @[tile.scala:159:20]
.io_core_commit_uops_0_debug_tsrc (_core_io_lsu_commit_uops_0_debug_tsrc), // @[tile.scala:159:20]
.io_core_commit_uops_1_uopc (_core_io_lsu_commit_uops_1_uopc), // @[tile.scala:159:20]
.io_core_commit_uops_1_inst (_core_io_lsu_commit_uops_1_inst), // @[tile.scala:159:20]
.io_core_commit_uops_1_debug_inst (_core_io_lsu_commit_uops_1_debug_inst), // @[tile.scala:159:20]
.io_core_commit_uops_1_is_rvc (_core_io_lsu_commit_uops_1_is_rvc), // @[tile.scala:159:20]
.io_core_commit_uops_1_debug_pc (_core_io_lsu_commit_uops_1_debug_pc), // @[tile.scala:159:20]
.io_core_commit_uops_1_iq_type (_core_io_lsu_commit_uops_1_iq_type), // @[tile.scala:159:20]
.io_core_commit_uops_1_fu_code (_core_io_lsu_commit_uops_1_fu_code), // @[tile.scala:159:20]
.io_core_commit_uops_1_ctrl_br_type (_core_io_lsu_commit_uops_1_ctrl_br_type), // @[tile.scala:159:20]
.io_core_commit_uops_1_ctrl_op1_sel (_core_io_lsu_commit_uops_1_ctrl_op1_sel), // @[tile.scala:159:20]
.io_core_commit_uops_1_ctrl_op2_sel (_core_io_lsu_commit_uops_1_ctrl_op2_sel), // @[tile.scala:159:20]
.io_core_commit_uops_1_ctrl_imm_sel (_core_io_lsu_commit_uops_1_ctrl_imm_sel), // @[tile.scala:159:20]
.io_core_commit_uops_1_ctrl_op_fcn (_core_io_lsu_commit_uops_1_ctrl_op_fcn), // @[tile.scala:159:20]
.io_core_commit_uops_1_ctrl_fcn_dw (_core_io_lsu_commit_uops_1_ctrl_fcn_dw), // @[tile.scala:159:20]
.io_core_commit_uops_1_ctrl_csr_cmd (_core_io_lsu_commit_uops_1_ctrl_csr_cmd), // @[tile.scala:159:20]
.io_core_commit_uops_1_ctrl_is_load (_core_io_lsu_commit_uops_1_ctrl_is_load), // @[tile.scala:159:20]
.io_core_commit_uops_1_ctrl_is_sta (_core_io_lsu_commit_uops_1_ctrl_is_sta), // @[tile.scala:159:20]
.io_core_commit_uops_1_ctrl_is_std (_core_io_lsu_commit_uops_1_ctrl_is_std), // @[tile.scala:159:20]
.io_core_commit_uops_1_iw_state (_core_io_lsu_commit_uops_1_iw_state), // @[tile.scala:159:20]
.io_core_commit_uops_1_iw_p1_poisoned (_core_io_lsu_commit_uops_1_iw_p1_poisoned), // @[tile.scala:159:20]
.io_core_commit_uops_1_iw_p2_poisoned (_core_io_lsu_commit_uops_1_iw_p2_poisoned), // @[tile.scala:159:20]
.io_core_commit_uops_1_is_br (_core_io_lsu_commit_uops_1_is_br), // @[tile.scala:159:20]
.io_core_commit_uops_1_is_jalr (_core_io_lsu_commit_uops_1_is_jalr), // @[tile.scala:159:20]
.io_core_commit_uops_1_is_jal (_core_io_lsu_commit_uops_1_is_jal), // @[tile.scala:159:20]
.io_core_commit_uops_1_is_sfb (_core_io_lsu_commit_uops_1_is_sfb), // @[tile.scala:159:20]
.io_core_commit_uops_1_br_mask (_core_io_lsu_commit_uops_1_br_mask), // @[tile.scala:159:20]
.io_core_commit_uops_1_br_tag (_core_io_lsu_commit_uops_1_br_tag), // @[tile.scala:159:20]
.io_core_commit_uops_1_ftq_idx (_core_io_lsu_commit_uops_1_ftq_idx), // @[tile.scala:159:20]
.io_core_commit_uops_1_edge_inst (_core_io_lsu_commit_uops_1_edge_inst), // @[tile.scala:159:20]
.io_core_commit_uops_1_pc_lob (_core_io_lsu_commit_uops_1_pc_lob), // @[tile.scala:159:20]
.io_core_commit_uops_1_taken (_core_io_lsu_commit_uops_1_taken), // @[tile.scala:159:20]
.io_core_commit_uops_1_imm_packed (_core_io_lsu_commit_uops_1_imm_packed), // @[tile.scala:159:20]
.io_core_commit_uops_1_csr_addr (_core_io_lsu_commit_uops_1_csr_addr), // @[tile.scala:159:20]
.io_core_commit_uops_1_rob_idx (_core_io_lsu_commit_uops_1_rob_idx), // @[tile.scala:159:20]
.io_core_commit_uops_1_ldq_idx (_core_io_lsu_commit_uops_1_ldq_idx), // @[tile.scala:159:20]
.io_core_commit_uops_1_stq_idx (_core_io_lsu_commit_uops_1_stq_idx), // @[tile.scala:159:20]
.io_core_commit_uops_1_rxq_idx (_core_io_lsu_commit_uops_1_rxq_idx), // @[tile.scala:159:20]
.io_core_commit_uops_1_pdst (_core_io_lsu_commit_uops_1_pdst), // @[tile.scala:159:20]
.io_core_commit_uops_1_prs1 (_core_io_lsu_commit_uops_1_prs1), // @[tile.scala:159:20]
.io_core_commit_uops_1_prs2 (_core_io_lsu_commit_uops_1_prs2), // @[tile.scala:159:20]
.io_core_commit_uops_1_prs3 (_core_io_lsu_commit_uops_1_prs3), // @[tile.scala:159:20]
.io_core_commit_uops_1_ppred (_core_io_lsu_commit_uops_1_ppred), // @[tile.scala:159:20]
.io_core_commit_uops_1_prs1_busy (_core_io_lsu_commit_uops_1_prs1_busy), // @[tile.scala:159:20]
.io_core_commit_uops_1_prs2_busy (_core_io_lsu_commit_uops_1_prs2_busy), // @[tile.scala:159:20]
.io_core_commit_uops_1_prs3_busy (_core_io_lsu_commit_uops_1_prs3_busy), // @[tile.scala:159:20]
.io_core_commit_uops_1_ppred_busy (_core_io_lsu_commit_uops_1_ppred_busy), // @[tile.scala:159:20]
.io_core_commit_uops_1_stale_pdst (_core_io_lsu_commit_uops_1_stale_pdst), // @[tile.scala:159:20]
.io_core_commit_uops_1_exception (_core_io_lsu_commit_uops_1_exception), // @[tile.scala:159:20]
.io_core_commit_uops_1_exc_cause (_core_io_lsu_commit_uops_1_exc_cause), // @[tile.scala:159:20]
.io_core_commit_uops_1_bypassable (_core_io_lsu_commit_uops_1_bypassable), // @[tile.scala:159:20]
.io_core_commit_uops_1_mem_cmd (_core_io_lsu_commit_uops_1_mem_cmd), // @[tile.scala:159:20]
.io_core_commit_uops_1_mem_size (_core_io_lsu_commit_uops_1_mem_size), // @[tile.scala:159:20]
.io_core_commit_uops_1_mem_signed (_core_io_lsu_commit_uops_1_mem_signed), // @[tile.scala:159:20]
.io_core_commit_uops_1_is_fence (_core_io_lsu_commit_uops_1_is_fence), // @[tile.scala:159:20]
.io_core_commit_uops_1_is_fencei (_core_io_lsu_commit_uops_1_is_fencei), // @[tile.scala:159:20]
.io_core_commit_uops_1_is_amo (_core_io_lsu_commit_uops_1_is_amo), // @[tile.scala:159:20]
.io_core_commit_uops_1_uses_ldq (_core_io_lsu_commit_uops_1_uses_ldq), // @[tile.scala:159:20]
.io_core_commit_uops_1_uses_stq (_core_io_lsu_commit_uops_1_uses_stq), // @[tile.scala:159:20]
.io_core_commit_uops_1_is_sys_pc2epc (_core_io_lsu_commit_uops_1_is_sys_pc2epc), // @[tile.scala:159:20]
.io_core_commit_uops_1_is_unique (_core_io_lsu_commit_uops_1_is_unique), // @[tile.scala:159:20]
.io_core_commit_uops_1_flush_on_commit (_core_io_lsu_commit_uops_1_flush_on_commit), // @[tile.scala:159:20]
.io_core_commit_uops_1_ldst_is_rs1 (_core_io_lsu_commit_uops_1_ldst_is_rs1), // @[tile.scala:159:20]
.io_core_commit_uops_1_ldst (_core_io_lsu_commit_uops_1_ldst), // @[tile.scala:159:20]
.io_core_commit_uops_1_lrs1 (_core_io_lsu_commit_uops_1_lrs1), // @[tile.scala:159:20]
.io_core_commit_uops_1_lrs2 (_core_io_lsu_commit_uops_1_lrs2), // @[tile.scala:159:20]
.io_core_commit_uops_1_lrs3 (_core_io_lsu_commit_uops_1_lrs3), // @[tile.scala:159:20]
.io_core_commit_uops_1_ldst_val (_core_io_lsu_commit_uops_1_ldst_val), // @[tile.scala:159:20]
.io_core_commit_uops_1_dst_rtype (_core_io_lsu_commit_uops_1_dst_rtype), // @[tile.scala:159:20]
.io_core_commit_uops_1_lrs1_rtype (_core_io_lsu_commit_uops_1_lrs1_rtype), // @[tile.scala:159:20]
.io_core_commit_uops_1_lrs2_rtype (_core_io_lsu_commit_uops_1_lrs2_rtype), // @[tile.scala:159:20]
.io_core_commit_uops_1_frs3_en (_core_io_lsu_commit_uops_1_frs3_en), // @[tile.scala:159:20]
.io_core_commit_uops_1_fp_val (_core_io_lsu_commit_uops_1_fp_val), // @[tile.scala:159:20]
.io_core_commit_uops_1_fp_single (_core_io_lsu_commit_uops_1_fp_single), // @[tile.scala:159:20]
.io_core_commit_uops_1_xcpt_pf_if (_core_io_lsu_commit_uops_1_xcpt_pf_if), // @[tile.scala:159:20]
.io_core_commit_uops_1_xcpt_ae_if (_core_io_lsu_commit_uops_1_xcpt_ae_if), // @[tile.scala:159:20]
.io_core_commit_uops_1_xcpt_ma_if (_core_io_lsu_commit_uops_1_xcpt_ma_if), // @[tile.scala:159:20]
.io_core_commit_uops_1_bp_debug_if (_core_io_lsu_commit_uops_1_bp_debug_if), // @[tile.scala:159:20]
.io_core_commit_uops_1_bp_xcpt_if (_core_io_lsu_commit_uops_1_bp_xcpt_if), // @[tile.scala:159:20]
.io_core_commit_uops_1_debug_fsrc (_core_io_lsu_commit_uops_1_debug_fsrc), // @[tile.scala:159:20]
.io_core_commit_uops_1_debug_tsrc (_core_io_lsu_commit_uops_1_debug_tsrc), // @[tile.scala:159:20]
.io_core_commit_uops_2_uopc (_core_io_lsu_commit_uops_2_uopc), // @[tile.scala:159:20]
.io_core_commit_uops_2_inst (_core_io_lsu_commit_uops_2_inst), // @[tile.scala:159:20]
.io_core_commit_uops_2_debug_inst (_core_io_lsu_commit_uops_2_debug_inst), // @[tile.scala:159:20]
.io_core_commit_uops_2_is_rvc (_core_io_lsu_commit_uops_2_is_rvc), // @[tile.scala:159:20]
.io_core_commit_uops_2_debug_pc (_core_io_lsu_commit_uops_2_debug_pc), // @[tile.scala:159:20]
.io_core_commit_uops_2_iq_type (_core_io_lsu_commit_uops_2_iq_type), // @[tile.scala:159:20]
.io_core_commit_uops_2_fu_code (_core_io_lsu_commit_uops_2_fu_code), // @[tile.scala:159:20]
.io_core_commit_uops_2_ctrl_br_type (_core_io_lsu_commit_uops_2_ctrl_br_type), // @[tile.scala:159:20]
.io_core_commit_uops_2_ctrl_op1_sel (_core_io_lsu_commit_uops_2_ctrl_op1_sel), // @[tile.scala:159:20]
.io_core_commit_uops_2_ctrl_op2_sel (_core_io_lsu_commit_uops_2_ctrl_op2_sel), // @[tile.scala:159:20]
.io_core_commit_uops_2_ctrl_imm_sel (_core_io_lsu_commit_uops_2_ctrl_imm_sel), // @[tile.scala:159:20]
.io_core_commit_uops_2_ctrl_op_fcn (_core_io_lsu_commit_uops_2_ctrl_op_fcn), // @[tile.scala:159:20]
.io_core_commit_uops_2_ctrl_fcn_dw (_core_io_lsu_commit_uops_2_ctrl_fcn_dw), // @[tile.scala:159:20]
.io_core_commit_uops_2_ctrl_csr_cmd (_core_io_lsu_commit_uops_2_ctrl_csr_cmd), // @[tile.scala:159:20]
.io_core_commit_uops_2_ctrl_is_load (_core_io_lsu_commit_uops_2_ctrl_is_load), // @[tile.scala:159:20]
.io_core_commit_uops_2_ctrl_is_sta (_core_io_lsu_commit_uops_2_ctrl_is_sta), // @[tile.scala:159:20]
.io_core_commit_uops_2_ctrl_is_std (_core_io_lsu_commit_uops_2_ctrl_is_std), // @[tile.scala:159:20]
.io_core_commit_uops_2_iw_state (_core_io_lsu_commit_uops_2_iw_state), // @[tile.scala:159:20]
.io_core_commit_uops_2_iw_p1_poisoned (_core_io_lsu_commit_uops_2_iw_p1_poisoned), // @[tile.scala:159:20]
.io_core_commit_uops_2_iw_p2_poisoned (_core_io_lsu_commit_uops_2_iw_p2_poisoned), // @[tile.scala:159:20]
.io_core_commit_uops_2_is_br (_core_io_lsu_commit_uops_2_is_br), // @[tile.scala:159:20]
.io_core_commit_uops_2_is_jalr (_core_io_lsu_commit_uops_2_is_jalr), // @[tile.scala:159:20]
.io_core_commit_uops_2_is_jal (_core_io_lsu_commit_uops_2_is_jal), // @[tile.scala:159:20]
.io_core_commit_uops_2_is_sfb (_core_io_lsu_commit_uops_2_is_sfb), // @[tile.scala:159:20]
.io_core_commit_uops_2_br_mask (_core_io_lsu_commit_uops_2_br_mask), // @[tile.scala:159:20]
.io_core_commit_uops_2_br_tag (_core_io_lsu_commit_uops_2_br_tag), // @[tile.scala:159:20]
.io_core_commit_uops_2_ftq_idx (_core_io_lsu_commit_uops_2_ftq_idx), // @[tile.scala:159:20]
.io_core_commit_uops_2_edge_inst (_core_io_lsu_commit_uops_2_edge_inst), // @[tile.scala:159:20]
.io_core_commit_uops_2_pc_lob (_core_io_lsu_commit_uops_2_pc_lob), // @[tile.scala:159:20]
.io_core_commit_uops_2_taken (_core_io_lsu_commit_uops_2_taken), // @[tile.scala:159:20]
.io_core_commit_uops_2_imm_packed (_core_io_lsu_commit_uops_2_imm_packed), // @[tile.scala:159:20]
.io_core_commit_uops_2_csr_addr (_core_io_lsu_commit_uops_2_csr_addr), // @[tile.scala:159:20]
.io_core_commit_uops_2_rob_idx (_core_io_lsu_commit_uops_2_rob_idx), // @[tile.scala:159:20]
.io_core_commit_uops_2_ldq_idx (_core_io_lsu_commit_uops_2_ldq_idx), // @[tile.scala:159:20]
.io_core_commit_uops_2_stq_idx (_core_io_lsu_commit_uops_2_stq_idx), // @[tile.scala:159:20]
.io_core_commit_uops_2_rxq_idx (_core_io_lsu_commit_uops_2_rxq_idx), // @[tile.scala:159:20]
.io_core_commit_uops_2_pdst (_core_io_lsu_commit_uops_2_pdst), // @[tile.scala:159:20]
.io_core_commit_uops_2_prs1 (_core_io_lsu_commit_uops_2_prs1), // @[tile.scala:159:20]
.io_core_commit_uops_2_prs2 (_core_io_lsu_commit_uops_2_prs2), // @[tile.scala:159:20]
.io_core_commit_uops_2_prs3 (_core_io_lsu_commit_uops_2_prs3), // @[tile.scala:159:20]
.io_core_commit_uops_2_ppred (_core_io_lsu_commit_uops_2_ppred), // @[tile.scala:159:20]
.io_core_commit_uops_2_prs1_busy (_core_io_lsu_commit_uops_2_prs1_busy), // @[tile.scala:159:20]
.io_core_commit_uops_2_prs2_busy (_core_io_lsu_commit_uops_2_prs2_busy), // @[tile.scala:159:20]
.io_core_commit_uops_2_prs3_busy (_core_io_lsu_commit_uops_2_prs3_busy), // @[tile.scala:159:20]
.io_core_commit_uops_2_ppred_busy (_core_io_lsu_commit_uops_2_ppred_busy), // @[tile.scala:159:20]
.io_core_commit_uops_2_stale_pdst (_core_io_lsu_commit_uops_2_stale_pdst), // @[tile.scala:159:20]
.io_core_commit_uops_2_exception (_core_io_lsu_commit_uops_2_exception), // @[tile.scala:159:20]
.io_core_commit_uops_2_exc_cause (_core_io_lsu_commit_uops_2_exc_cause), // @[tile.scala:159:20]
.io_core_commit_uops_2_bypassable (_core_io_lsu_commit_uops_2_bypassable), // @[tile.scala:159:20]
.io_core_commit_uops_2_mem_cmd (_core_io_lsu_commit_uops_2_mem_cmd), // @[tile.scala:159:20]
.io_core_commit_uops_2_mem_size (_core_io_lsu_commit_uops_2_mem_size), // @[tile.scala:159:20]
.io_core_commit_uops_2_mem_signed (_core_io_lsu_commit_uops_2_mem_signed), // @[tile.scala:159:20]
.io_core_commit_uops_2_is_fence (_core_io_lsu_commit_uops_2_is_fence), // @[tile.scala:159:20]
.io_core_commit_uops_2_is_fencei (_core_io_lsu_commit_uops_2_is_fencei), // @[tile.scala:159:20]
.io_core_commit_uops_2_is_amo (_core_io_lsu_commit_uops_2_is_amo), // @[tile.scala:159:20]
.io_core_commit_uops_2_uses_ldq (_core_io_lsu_commit_uops_2_uses_ldq), // @[tile.scala:159:20]
.io_core_commit_uops_2_uses_stq (_core_io_lsu_commit_uops_2_uses_stq), // @[tile.scala:159:20]
.io_core_commit_uops_2_is_sys_pc2epc (_core_io_lsu_commit_uops_2_is_sys_pc2epc), // @[tile.scala:159:20]
.io_core_commit_uops_2_is_unique (_core_io_lsu_commit_uops_2_is_unique), // @[tile.scala:159:20]
.io_core_commit_uops_2_flush_on_commit (_core_io_lsu_commit_uops_2_flush_on_commit), // @[tile.scala:159:20]
.io_core_commit_uops_2_ldst_is_rs1 (_core_io_lsu_commit_uops_2_ldst_is_rs1), // @[tile.scala:159:20]
.io_core_commit_uops_2_ldst (_core_io_lsu_commit_uops_2_ldst), // @[tile.scala:159:20]
.io_core_commit_uops_2_lrs1 (_core_io_lsu_commit_uops_2_lrs1), // @[tile.scala:159:20]
.io_core_commit_uops_2_lrs2 (_core_io_lsu_commit_uops_2_lrs2), // @[tile.scala:159:20]
.io_core_commit_uops_2_lrs3 (_core_io_lsu_commit_uops_2_lrs3), // @[tile.scala:159:20]
.io_core_commit_uops_2_ldst_val (_core_io_lsu_commit_uops_2_ldst_val), // @[tile.scala:159:20]
.io_core_commit_uops_2_dst_rtype (_core_io_lsu_commit_uops_2_dst_rtype), // @[tile.scala:159:20]
.io_core_commit_uops_2_lrs1_rtype (_core_io_lsu_commit_uops_2_lrs1_rtype), // @[tile.scala:159:20]
.io_core_commit_uops_2_lrs2_rtype (_core_io_lsu_commit_uops_2_lrs2_rtype), // @[tile.scala:159:20]
.io_core_commit_uops_2_frs3_en (_core_io_lsu_commit_uops_2_frs3_en), // @[tile.scala:159:20]
.io_core_commit_uops_2_fp_val (_core_io_lsu_commit_uops_2_fp_val), // @[tile.scala:159:20]
.io_core_commit_uops_2_fp_single (_core_io_lsu_commit_uops_2_fp_single), // @[tile.scala:159:20]
.io_core_commit_uops_2_xcpt_pf_if (_core_io_lsu_commit_uops_2_xcpt_pf_if), // @[tile.scala:159:20]
.io_core_commit_uops_2_xcpt_ae_if (_core_io_lsu_commit_uops_2_xcpt_ae_if), // @[tile.scala:159:20]
.io_core_commit_uops_2_xcpt_ma_if (_core_io_lsu_commit_uops_2_xcpt_ma_if), // @[tile.scala:159:20]
.io_core_commit_uops_2_bp_debug_if (_core_io_lsu_commit_uops_2_bp_debug_if), // @[tile.scala:159:20]
.io_core_commit_uops_2_bp_xcpt_if (_core_io_lsu_commit_uops_2_bp_xcpt_if), // @[tile.scala:159:20]
.io_core_commit_uops_2_debug_fsrc (_core_io_lsu_commit_uops_2_debug_fsrc), // @[tile.scala:159:20]
.io_core_commit_uops_2_debug_tsrc (_core_io_lsu_commit_uops_2_debug_tsrc), // @[tile.scala:159:20]
.io_core_commit_fflags_valid (_core_io_lsu_commit_fflags_valid), // @[tile.scala:159:20]
.io_core_commit_fflags_bits (_core_io_lsu_commit_fflags_bits), // @[tile.scala:159:20]
.io_core_commit_debug_insts_0 (_core_io_lsu_commit_debug_insts_0), // @[tile.scala:159:20]
.io_core_commit_debug_insts_1 (_core_io_lsu_commit_debug_insts_1), // @[tile.scala:159:20]
.io_core_commit_debug_insts_2 (_core_io_lsu_commit_debug_insts_2), // @[tile.scala:159:20]
.io_core_commit_rbk_valids_0 (_core_io_lsu_commit_rbk_valids_0), // @[tile.scala:159:20]
.io_core_commit_rbk_valids_1 (_core_io_lsu_commit_rbk_valids_1), // @[tile.scala:159:20]
.io_core_commit_rbk_valids_2 (_core_io_lsu_commit_rbk_valids_2), // @[tile.scala:159:20]
.io_core_commit_rollback (_core_io_lsu_commit_rollback), // @[tile.scala:159:20]
.io_core_commit_debug_wdata_0 (_core_io_lsu_commit_debug_wdata_0), // @[tile.scala:159:20]
.io_core_commit_debug_wdata_1 (_core_io_lsu_commit_debug_wdata_1), // @[tile.scala:159:20]
.io_core_commit_debug_wdata_2 (_core_io_lsu_commit_debug_wdata_2), // @[tile.scala:159:20]
.io_core_commit_load_at_rob_head (_core_io_lsu_commit_load_at_rob_head), // @[tile.scala:159:20]
.io_core_clr_bsy_0_valid (_lsu_io_core_clr_bsy_0_valid),
.io_core_clr_bsy_0_bits (_lsu_io_core_clr_bsy_0_bits),
.io_core_clr_bsy_1_valid (_lsu_io_core_clr_bsy_1_valid),
.io_core_clr_bsy_1_bits (_lsu_io_core_clr_bsy_1_bits),
.io_core_clr_unsafe_0_bits (_lsu_io_core_clr_unsafe_0_bits),
.io_core_fence_dmem (_core_io_lsu_fence_dmem), // @[tile.scala:159:20]
.io_core_spec_ld_wakeup_0_valid (_lsu_io_core_spec_ld_wakeup_0_valid),
.io_core_spec_ld_wakeup_0_bits (_lsu_io_core_spec_ld_wakeup_0_bits),
.io_core_ld_miss (_lsu_io_core_ld_miss),
.io_core_brupdate_b1_resolve_mask (_core_io_lsu_brupdate_b1_resolve_mask), // @[tile.scala:159:20]
.io_core_brupdate_b1_mispredict_mask (_core_io_lsu_brupdate_b1_mispredict_mask), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_uopc (_core_io_lsu_brupdate_b2_uop_uopc), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_inst (_core_io_lsu_brupdate_b2_uop_inst), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_debug_inst (_core_io_lsu_brupdate_b2_uop_debug_inst), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_is_rvc (_core_io_lsu_brupdate_b2_uop_is_rvc), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_debug_pc (_core_io_lsu_brupdate_b2_uop_debug_pc), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_iq_type (_core_io_lsu_brupdate_b2_uop_iq_type), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_fu_code (_core_io_lsu_brupdate_b2_uop_fu_code), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_ctrl_br_type (_core_io_lsu_brupdate_b2_uop_ctrl_br_type), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_ctrl_op1_sel (_core_io_lsu_brupdate_b2_uop_ctrl_op1_sel), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_ctrl_op2_sel (_core_io_lsu_brupdate_b2_uop_ctrl_op2_sel), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_ctrl_imm_sel (_core_io_lsu_brupdate_b2_uop_ctrl_imm_sel), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_ctrl_op_fcn (_core_io_lsu_brupdate_b2_uop_ctrl_op_fcn), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_ctrl_fcn_dw (_core_io_lsu_brupdate_b2_uop_ctrl_fcn_dw), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_ctrl_csr_cmd (_core_io_lsu_brupdate_b2_uop_ctrl_csr_cmd), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_ctrl_is_load (_core_io_lsu_brupdate_b2_uop_ctrl_is_load), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_ctrl_is_sta (_core_io_lsu_brupdate_b2_uop_ctrl_is_sta), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_ctrl_is_std (_core_io_lsu_brupdate_b2_uop_ctrl_is_std), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_iw_state (_core_io_lsu_brupdate_b2_uop_iw_state), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_iw_p1_poisoned (_core_io_lsu_brupdate_b2_uop_iw_p1_poisoned), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_iw_p2_poisoned (_core_io_lsu_brupdate_b2_uop_iw_p2_poisoned), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_is_br (_core_io_lsu_brupdate_b2_uop_is_br), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_is_jalr (_core_io_lsu_brupdate_b2_uop_is_jalr), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_is_jal (_core_io_lsu_brupdate_b2_uop_is_jal), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_is_sfb (_core_io_lsu_brupdate_b2_uop_is_sfb), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_br_mask (_core_io_lsu_brupdate_b2_uop_br_mask), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_br_tag (_core_io_lsu_brupdate_b2_uop_br_tag), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_ftq_idx (_core_io_lsu_brupdate_b2_uop_ftq_idx), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_edge_inst (_core_io_lsu_brupdate_b2_uop_edge_inst), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_pc_lob (_core_io_lsu_brupdate_b2_uop_pc_lob), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_taken (_core_io_lsu_brupdate_b2_uop_taken), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_imm_packed (_core_io_lsu_brupdate_b2_uop_imm_packed), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_csr_addr (_core_io_lsu_brupdate_b2_uop_csr_addr), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_rob_idx (_core_io_lsu_brupdate_b2_uop_rob_idx), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_ldq_idx (_core_io_lsu_brupdate_b2_uop_ldq_idx), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_stq_idx (_core_io_lsu_brupdate_b2_uop_stq_idx), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_rxq_idx (_core_io_lsu_brupdate_b2_uop_rxq_idx), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_pdst (_core_io_lsu_brupdate_b2_uop_pdst), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_prs1 (_core_io_lsu_brupdate_b2_uop_prs1), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_prs2 (_core_io_lsu_brupdate_b2_uop_prs2), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_prs3 (_core_io_lsu_brupdate_b2_uop_prs3), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_ppred (_core_io_lsu_brupdate_b2_uop_ppred), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_prs1_busy (_core_io_lsu_brupdate_b2_uop_prs1_busy), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_prs2_busy (_core_io_lsu_brupdate_b2_uop_prs2_busy), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_prs3_busy (_core_io_lsu_brupdate_b2_uop_prs3_busy), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_ppred_busy (_core_io_lsu_brupdate_b2_uop_ppred_busy), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_stale_pdst (_core_io_lsu_brupdate_b2_uop_stale_pdst), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_exception (_core_io_lsu_brupdate_b2_uop_exception), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_exc_cause (_core_io_lsu_brupdate_b2_uop_exc_cause), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_bypassable (_core_io_lsu_brupdate_b2_uop_bypassable), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_mem_cmd (_core_io_lsu_brupdate_b2_uop_mem_cmd), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_mem_size (_core_io_lsu_brupdate_b2_uop_mem_size), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_mem_signed (_core_io_lsu_brupdate_b2_uop_mem_signed), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_is_fence (_core_io_lsu_brupdate_b2_uop_is_fence), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_is_fencei (_core_io_lsu_brupdate_b2_uop_is_fencei), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_is_amo (_core_io_lsu_brupdate_b2_uop_is_amo), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_uses_ldq (_core_io_lsu_brupdate_b2_uop_uses_ldq), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_uses_stq (_core_io_lsu_brupdate_b2_uop_uses_stq), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_is_sys_pc2epc (_core_io_lsu_brupdate_b2_uop_is_sys_pc2epc), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_is_unique (_core_io_lsu_brupdate_b2_uop_is_unique), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_flush_on_commit (_core_io_lsu_brupdate_b2_uop_flush_on_commit), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_ldst_is_rs1 (_core_io_lsu_brupdate_b2_uop_ldst_is_rs1), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_ldst (_core_io_lsu_brupdate_b2_uop_ldst), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_lrs1 (_core_io_lsu_brupdate_b2_uop_lrs1), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_lrs2 (_core_io_lsu_brupdate_b2_uop_lrs2), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_lrs3 (_core_io_lsu_brupdate_b2_uop_lrs3), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_ldst_val (_core_io_lsu_brupdate_b2_uop_ldst_val), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_dst_rtype (_core_io_lsu_brupdate_b2_uop_dst_rtype), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_lrs1_rtype (_core_io_lsu_brupdate_b2_uop_lrs1_rtype), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_lrs2_rtype (_core_io_lsu_brupdate_b2_uop_lrs2_rtype), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_frs3_en (_core_io_lsu_brupdate_b2_uop_frs3_en), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_fp_val (_core_io_lsu_brupdate_b2_uop_fp_val), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_fp_single (_core_io_lsu_brupdate_b2_uop_fp_single), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_xcpt_pf_if (_core_io_lsu_brupdate_b2_uop_xcpt_pf_if), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_xcpt_ae_if (_core_io_lsu_brupdate_b2_uop_xcpt_ae_if), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_xcpt_ma_if (_core_io_lsu_brupdate_b2_uop_xcpt_ma_if), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_bp_debug_if (_core_io_lsu_brupdate_b2_uop_bp_debug_if), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_bp_xcpt_if (_core_io_lsu_brupdate_b2_uop_bp_xcpt_if), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_debug_fsrc (_core_io_lsu_brupdate_b2_uop_debug_fsrc), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_debug_tsrc (_core_io_lsu_brupdate_b2_uop_debug_tsrc), // @[tile.scala:159:20]
.io_core_brupdate_b2_valid (_core_io_lsu_brupdate_b2_valid), // @[tile.scala:159:20]
.io_core_brupdate_b2_mispredict (_core_io_lsu_brupdate_b2_mispredict), // @[tile.scala:159:20]
.io_core_brupdate_b2_taken (_core_io_lsu_brupdate_b2_taken), // @[tile.scala:159:20]
.io_core_brupdate_b2_cfi_type (_core_io_lsu_brupdate_b2_cfi_type), // @[tile.scala:159:20]
.io_core_brupdate_b2_pc_sel (_core_io_lsu_brupdate_b2_pc_sel), // @[tile.scala:159:20]
.io_core_brupdate_b2_jalr_target (_core_io_lsu_brupdate_b2_jalr_target), // @[tile.scala:159:20]
.io_core_brupdate_b2_target_offset (_core_io_lsu_brupdate_b2_target_offset), // @[tile.scala:159:20]
.io_core_rob_pnr_idx (_core_io_lsu_rob_pnr_idx), // @[tile.scala:159:20]
.io_core_rob_head_idx (_core_io_lsu_rob_head_idx), // @[tile.scala:159:20]
.io_core_exception (_core_io_lsu_exception), // @[tile.scala:159:20]
.io_core_fencei_rdy (_lsu_io_core_fencei_rdy),
.io_core_lxcpt_valid (_lsu_io_core_lxcpt_valid),
.io_core_lxcpt_bits_uop_uopc (_lsu_io_core_lxcpt_bits_uop_uopc),
.io_core_lxcpt_bits_uop_inst (_lsu_io_core_lxcpt_bits_uop_inst),
.io_core_lxcpt_bits_uop_debug_inst (_lsu_io_core_lxcpt_bits_uop_debug_inst),
.io_core_lxcpt_bits_uop_is_rvc (_lsu_io_core_lxcpt_bits_uop_is_rvc),
.io_core_lxcpt_bits_uop_debug_pc (_lsu_io_core_lxcpt_bits_uop_debug_pc),
.io_core_lxcpt_bits_uop_iq_type (_lsu_io_core_lxcpt_bits_uop_iq_type),
.io_core_lxcpt_bits_uop_fu_code (_lsu_io_core_lxcpt_bits_uop_fu_code),
.io_core_lxcpt_bits_uop_ctrl_br_type (_lsu_io_core_lxcpt_bits_uop_ctrl_br_type),
.io_core_lxcpt_bits_uop_ctrl_op1_sel (_lsu_io_core_lxcpt_bits_uop_ctrl_op1_sel),
.io_core_lxcpt_bits_uop_ctrl_op2_sel (_lsu_io_core_lxcpt_bits_uop_ctrl_op2_sel),
.io_core_lxcpt_bits_uop_ctrl_imm_sel (_lsu_io_core_lxcpt_bits_uop_ctrl_imm_sel),
.io_core_lxcpt_bits_uop_ctrl_op_fcn (_lsu_io_core_lxcpt_bits_uop_ctrl_op_fcn),
.io_core_lxcpt_bits_uop_ctrl_fcn_dw (_lsu_io_core_lxcpt_bits_uop_ctrl_fcn_dw),
.io_core_lxcpt_bits_uop_ctrl_csr_cmd (_lsu_io_core_lxcpt_bits_uop_ctrl_csr_cmd),
.io_core_lxcpt_bits_uop_ctrl_is_load (_lsu_io_core_lxcpt_bits_uop_ctrl_is_load),
.io_core_lxcpt_bits_uop_ctrl_is_sta (_lsu_io_core_lxcpt_bits_uop_ctrl_is_sta),
.io_core_lxcpt_bits_uop_ctrl_is_std (_lsu_io_core_lxcpt_bits_uop_ctrl_is_std),
.io_core_lxcpt_bits_uop_iw_state (_lsu_io_core_lxcpt_bits_uop_iw_state),
.io_core_lxcpt_bits_uop_iw_p1_poisoned (_lsu_io_core_lxcpt_bits_uop_iw_p1_poisoned),
.io_core_lxcpt_bits_uop_iw_p2_poisoned (_lsu_io_core_lxcpt_bits_uop_iw_p2_poisoned),
.io_core_lxcpt_bits_uop_is_br (_lsu_io_core_lxcpt_bits_uop_is_br),
.io_core_lxcpt_bits_uop_is_jalr (_lsu_io_core_lxcpt_bits_uop_is_jalr),
.io_core_lxcpt_bits_uop_is_jal (_lsu_io_core_lxcpt_bits_uop_is_jal),
.io_core_lxcpt_bits_uop_is_sfb (_lsu_io_core_lxcpt_bits_uop_is_sfb),
.io_core_lxcpt_bits_uop_br_mask (_lsu_io_core_lxcpt_bits_uop_br_mask),
.io_core_lxcpt_bits_uop_br_tag (_lsu_io_core_lxcpt_bits_uop_br_tag),
.io_core_lxcpt_bits_uop_ftq_idx (_lsu_io_core_lxcpt_bits_uop_ftq_idx),
.io_core_lxcpt_bits_uop_edge_inst (_lsu_io_core_lxcpt_bits_uop_edge_inst),
.io_core_lxcpt_bits_uop_pc_lob (_lsu_io_core_lxcpt_bits_uop_pc_lob),
.io_core_lxcpt_bits_uop_taken (_lsu_io_core_lxcpt_bits_uop_taken),
.io_core_lxcpt_bits_uop_imm_packed (_lsu_io_core_lxcpt_bits_uop_imm_packed),
.io_core_lxcpt_bits_uop_csr_addr (_lsu_io_core_lxcpt_bits_uop_csr_addr),
.io_core_lxcpt_bits_uop_rob_idx (_lsu_io_core_lxcpt_bits_uop_rob_idx),
.io_core_lxcpt_bits_uop_ldq_idx (_lsu_io_core_lxcpt_bits_uop_ldq_idx),
.io_core_lxcpt_bits_uop_stq_idx (_lsu_io_core_lxcpt_bits_uop_stq_idx),
.io_core_lxcpt_bits_uop_rxq_idx (_lsu_io_core_lxcpt_bits_uop_rxq_idx),
.io_core_lxcpt_bits_uop_pdst (_lsu_io_core_lxcpt_bits_uop_pdst),
.io_core_lxcpt_bits_uop_prs1 (_lsu_io_core_lxcpt_bits_uop_prs1),
.io_core_lxcpt_bits_uop_prs2 (_lsu_io_core_lxcpt_bits_uop_prs2),
.io_core_lxcpt_bits_uop_prs3 (_lsu_io_core_lxcpt_bits_uop_prs3),
.io_core_lxcpt_bits_uop_ppred (_lsu_io_core_lxcpt_bits_uop_ppred),
.io_core_lxcpt_bits_uop_prs1_busy (_lsu_io_core_lxcpt_bits_uop_prs1_busy),
.io_core_lxcpt_bits_uop_prs2_busy (_lsu_io_core_lxcpt_bits_uop_prs2_busy),
.io_core_lxcpt_bits_uop_prs3_busy (_lsu_io_core_lxcpt_bits_uop_prs3_busy),
.io_core_lxcpt_bits_uop_ppred_busy (_lsu_io_core_lxcpt_bits_uop_ppred_busy),
.io_core_lxcpt_bits_uop_stale_pdst (_lsu_io_core_lxcpt_bits_uop_stale_pdst),
.io_core_lxcpt_bits_uop_exception (_lsu_io_core_lxcpt_bits_uop_exception),
.io_core_lxcpt_bits_uop_exc_cause (_lsu_io_core_lxcpt_bits_uop_exc_cause),
.io_core_lxcpt_bits_uop_bypassable (_lsu_io_core_lxcpt_bits_uop_bypassable),
.io_core_lxcpt_bits_uop_mem_cmd (_lsu_io_core_lxcpt_bits_uop_mem_cmd),
.io_core_lxcpt_bits_uop_mem_size (_lsu_io_core_lxcpt_bits_uop_mem_size),
.io_core_lxcpt_bits_uop_mem_signed (_lsu_io_core_lxcpt_bits_uop_mem_signed),
.io_core_lxcpt_bits_uop_is_fence (_lsu_io_core_lxcpt_bits_uop_is_fence),
.io_core_lxcpt_bits_uop_is_fencei (_lsu_io_core_lxcpt_bits_uop_is_fencei),
.io_core_lxcpt_bits_uop_is_amo (_lsu_io_core_lxcpt_bits_uop_is_amo),
.io_core_lxcpt_bits_uop_uses_ldq (_lsu_io_core_lxcpt_bits_uop_uses_ldq),
.io_core_lxcpt_bits_uop_uses_stq (_lsu_io_core_lxcpt_bits_uop_uses_stq),
.io_core_lxcpt_bits_uop_is_sys_pc2epc (_lsu_io_core_lxcpt_bits_uop_is_sys_pc2epc),
.io_core_lxcpt_bits_uop_is_unique (_lsu_io_core_lxcpt_bits_uop_is_unique),
.io_core_lxcpt_bits_uop_flush_on_commit (_lsu_io_core_lxcpt_bits_uop_flush_on_commit),
.io_core_lxcpt_bits_uop_ldst_is_rs1 (_lsu_io_core_lxcpt_bits_uop_ldst_is_rs1),
.io_core_lxcpt_bits_uop_ldst (_lsu_io_core_lxcpt_bits_uop_ldst),
.io_core_lxcpt_bits_uop_lrs1 (_lsu_io_core_lxcpt_bits_uop_lrs1),
.io_core_lxcpt_bits_uop_lrs2 (_lsu_io_core_lxcpt_bits_uop_lrs2),
.io_core_lxcpt_bits_uop_lrs3 (_lsu_io_core_lxcpt_bits_uop_lrs3),
.io_core_lxcpt_bits_uop_ldst_val (_lsu_io_core_lxcpt_bits_uop_ldst_val),
.io_core_lxcpt_bits_uop_dst_rtype (_lsu_io_core_lxcpt_bits_uop_dst_rtype),
.io_core_lxcpt_bits_uop_lrs1_rtype (_lsu_io_core_lxcpt_bits_uop_lrs1_rtype),
.io_core_lxcpt_bits_uop_lrs2_rtype (_lsu_io_core_lxcpt_bits_uop_lrs2_rtype),
.io_core_lxcpt_bits_uop_frs3_en (_lsu_io_core_lxcpt_bits_uop_frs3_en),
.io_core_lxcpt_bits_uop_fp_val (_lsu_io_core_lxcpt_bits_uop_fp_val),
.io_core_lxcpt_bits_uop_fp_single (_lsu_io_core_lxcpt_bits_uop_fp_single),
.io_core_lxcpt_bits_uop_xcpt_pf_if (_lsu_io_core_lxcpt_bits_uop_xcpt_pf_if),
.io_core_lxcpt_bits_uop_xcpt_ae_if (_lsu_io_core_lxcpt_bits_uop_xcpt_ae_if),
.io_core_lxcpt_bits_uop_xcpt_ma_if (_lsu_io_core_lxcpt_bits_uop_xcpt_ma_if),
.io_core_lxcpt_bits_uop_bp_debug_if (_lsu_io_core_lxcpt_bits_uop_bp_debug_if),
.io_core_lxcpt_bits_uop_bp_xcpt_if (_lsu_io_core_lxcpt_bits_uop_bp_xcpt_if),
.io_core_lxcpt_bits_uop_debug_fsrc (_lsu_io_core_lxcpt_bits_uop_debug_fsrc),
.io_core_lxcpt_bits_uop_debug_tsrc (_lsu_io_core_lxcpt_bits_uop_debug_tsrc),
.io_core_lxcpt_bits_cause (_lsu_io_core_lxcpt_bits_cause),
.io_core_lxcpt_bits_badvaddr (_lsu_io_core_lxcpt_bits_badvaddr),
.io_core_tsc_reg (_core_io_lsu_tsc_reg), // @[tile.scala:159:20]
.io_core_perf_acquire (_lsu_io_core_perf_acquire),
.io_core_perf_release (_lsu_io_core_perf_release),
.io_core_perf_tlbMiss (_lsu_io_core_perf_tlbMiss),
.io_dmem_req_ready (_dcache_io_lsu_req_ready), // @[tile.scala:132:54]
.io_dmem_req_valid (_lsu_io_dmem_req_valid),
.io_dmem_req_bits_0_valid (_lsu_io_dmem_req_bits_0_valid),
.io_dmem_req_bits_0_bits_uop_uopc (_lsu_io_dmem_req_bits_0_bits_uop_uopc),
.io_dmem_req_bits_0_bits_uop_inst (_lsu_io_dmem_req_bits_0_bits_uop_inst),
.io_dmem_req_bits_0_bits_uop_debug_inst (_lsu_io_dmem_req_bits_0_bits_uop_debug_inst),
.io_dmem_req_bits_0_bits_uop_is_rvc (_lsu_io_dmem_req_bits_0_bits_uop_is_rvc),
.io_dmem_req_bits_0_bits_uop_debug_pc (_lsu_io_dmem_req_bits_0_bits_uop_debug_pc),
.io_dmem_req_bits_0_bits_uop_iq_type (_lsu_io_dmem_req_bits_0_bits_uop_iq_type),
.io_dmem_req_bits_0_bits_uop_fu_code (_lsu_io_dmem_req_bits_0_bits_uop_fu_code),
.io_dmem_req_bits_0_bits_uop_ctrl_br_type (_lsu_io_dmem_req_bits_0_bits_uop_ctrl_br_type),
.io_dmem_req_bits_0_bits_uop_ctrl_op1_sel (_lsu_io_dmem_req_bits_0_bits_uop_ctrl_op1_sel),
.io_dmem_req_bits_0_bits_uop_ctrl_op2_sel (_lsu_io_dmem_req_bits_0_bits_uop_ctrl_op2_sel),
.io_dmem_req_bits_0_bits_uop_ctrl_imm_sel (_lsu_io_dmem_req_bits_0_bits_uop_ctrl_imm_sel),
.io_dmem_req_bits_0_bits_uop_ctrl_op_fcn (_lsu_io_dmem_req_bits_0_bits_uop_ctrl_op_fcn),
.io_dmem_req_bits_0_bits_uop_ctrl_fcn_dw (_lsu_io_dmem_req_bits_0_bits_uop_ctrl_fcn_dw),
.io_dmem_req_bits_0_bits_uop_ctrl_csr_cmd (_lsu_io_dmem_req_bits_0_bits_uop_ctrl_csr_cmd),
.io_dmem_req_bits_0_bits_uop_ctrl_is_load (_lsu_io_dmem_req_bits_0_bits_uop_ctrl_is_load),
.io_dmem_req_bits_0_bits_uop_ctrl_is_sta (_lsu_io_dmem_req_bits_0_bits_uop_ctrl_is_sta),
.io_dmem_req_bits_0_bits_uop_ctrl_is_std (_lsu_io_dmem_req_bits_0_bits_uop_ctrl_is_std),
.io_dmem_req_bits_0_bits_uop_iw_state (_lsu_io_dmem_req_bits_0_bits_uop_iw_state),
.io_dmem_req_bits_0_bits_uop_iw_p1_poisoned (_lsu_io_dmem_req_bits_0_bits_uop_iw_p1_poisoned),
.io_dmem_req_bits_0_bits_uop_iw_p2_poisoned (_lsu_io_dmem_req_bits_0_bits_uop_iw_p2_poisoned),
.io_dmem_req_bits_0_bits_uop_is_br (_lsu_io_dmem_req_bits_0_bits_uop_is_br),
.io_dmem_req_bits_0_bits_uop_is_jalr (_lsu_io_dmem_req_bits_0_bits_uop_is_jalr),
.io_dmem_req_bits_0_bits_uop_is_jal (_lsu_io_dmem_req_bits_0_bits_uop_is_jal),
.io_dmem_req_bits_0_bits_uop_is_sfb (_lsu_io_dmem_req_bits_0_bits_uop_is_sfb),
.io_dmem_req_bits_0_bits_uop_br_mask (_lsu_io_dmem_req_bits_0_bits_uop_br_mask),
.io_dmem_req_bits_0_bits_uop_br_tag (_lsu_io_dmem_req_bits_0_bits_uop_br_tag),
.io_dmem_req_bits_0_bits_uop_ftq_idx (_lsu_io_dmem_req_bits_0_bits_uop_ftq_idx),
.io_dmem_req_bits_0_bits_uop_edge_inst (_lsu_io_dmem_req_bits_0_bits_uop_edge_inst),
.io_dmem_req_bits_0_bits_uop_pc_lob (_lsu_io_dmem_req_bits_0_bits_uop_pc_lob),
.io_dmem_req_bits_0_bits_uop_taken (_lsu_io_dmem_req_bits_0_bits_uop_taken),
.io_dmem_req_bits_0_bits_uop_imm_packed (_lsu_io_dmem_req_bits_0_bits_uop_imm_packed),
.io_dmem_req_bits_0_bits_uop_csr_addr (_lsu_io_dmem_req_bits_0_bits_uop_csr_addr),
.io_dmem_req_bits_0_bits_uop_rob_idx (_lsu_io_dmem_req_bits_0_bits_uop_rob_idx),
.io_dmem_req_bits_0_bits_uop_ldq_idx (_lsu_io_dmem_req_bits_0_bits_uop_ldq_idx),
.io_dmem_req_bits_0_bits_uop_stq_idx (_lsu_io_dmem_req_bits_0_bits_uop_stq_idx),
.io_dmem_req_bits_0_bits_uop_rxq_idx (_lsu_io_dmem_req_bits_0_bits_uop_rxq_idx),
.io_dmem_req_bits_0_bits_uop_pdst (_lsu_io_dmem_req_bits_0_bits_uop_pdst),
.io_dmem_req_bits_0_bits_uop_prs1 (_lsu_io_dmem_req_bits_0_bits_uop_prs1),
.io_dmem_req_bits_0_bits_uop_prs2 (_lsu_io_dmem_req_bits_0_bits_uop_prs2),
.io_dmem_req_bits_0_bits_uop_prs3 (_lsu_io_dmem_req_bits_0_bits_uop_prs3),
.io_dmem_req_bits_0_bits_uop_ppred (_lsu_io_dmem_req_bits_0_bits_uop_ppred),
.io_dmem_req_bits_0_bits_uop_prs1_busy (_lsu_io_dmem_req_bits_0_bits_uop_prs1_busy),
.io_dmem_req_bits_0_bits_uop_prs2_busy (_lsu_io_dmem_req_bits_0_bits_uop_prs2_busy),
.io_dmem_req_bits_0_bits_uop_prs3_busy (_lsu_io_dmem_req_bits_0_bits_uop_prs3_busy),
.io_dmem_req_bits_0_bits_uop_ppred_busy (_lsu_io_dmem_req_bits_0_bits_uop_ppred_busy),
.io_dmem_req_bits_0_bits_uop_stale_pdst (_lsu_io_dmem_req_bits_0_bits_uop_stale_pdst),
.io_dmem_req_bits_0_bits_uop_exception (_lsu_io_dmem_req_bits_0_bits_uop_exception),
.io_dmem_req_bits_0_bits_uop_exc_cause (_lsu_io_dmem_req_bits_0_bits_uop_exc_cause),
.io_dmem_req_bits_0_bits_uop_bypassable (_lsu_io_dmem_req_bits_0_bits_uop_bypassable),
.io_dmem_req_bits_0_bits_uop_mem_cmd (_lsu_io_dmem_req_bits_0_bits_uop_mem_cmd),
.io_dmem_req_bits_0_bits_uop_mem_size (_lsu_io_dmem_req_bits_0_bits_uop_mem_size),
.io_dmem_req_bits_0_bits_uop_mem_signed (_lsu_io_dmem_req_bits_0_bits_uop_mem_signed),
.io_dmem_req_bits_0_bits_uop_is_fence (_lsu_io_dmem_req_bits_0_bits_uop_is_fence),
.io_dmem_req_bits_0_bits_uop_is_fencei (_lsu_io_dmem_req_bits_0_bits_uop_is_fencei),
.io_dmem_req_bits_0_bits_uop_is_amo (_lsu_io_dmem_req_bits_0_bits_uop_is_amo),
.io_dmem_req_bits_0_bits_uop_uses_ldq (_lsu_io_dmem_req_bits_0_bits_uop_uses_ldq),
.io_dmem_req_bits_0_bits_uop_uses_stq (_lsu_io_dmem_req_bits_0_bits_uop_uses_stq),
.io_dmem_req_bits_0_bits_uop_is_sys_pc2epc (_lsu_io_dmem_req_bits_0_bits_uop_is_sys_pc2epc),
.io_dmem_req_bits_0_bits_uop_is_unique (_lsu_io_dmem_req_bits_0_bits_uop_is_unique),
.io_dmem_req_bits_0_bits_uop_flush_on_commit (_lsu_io_dmem_req_bits_0_bits_uop_flush_on_commit),
.io_dmem_req_bits_0_bits_uop_ldst_is_rs1 (_lsu_io_dmem_req_bits_0_bits_uop_ldst_is_rs1),
.io_dmem_req_bits_0_bits_uop_ldst (_lsu_io_dmem_req_bits_0_bits_uop_ldst),
.io_dmem_req_bits_0_bits_uop_lrs1 (_lsu_io_dmem_req_bits_0_bits_uop_lrs1),
.io_dmem_req_bits_0_bits_uop_lrs2 (_lsu_io_dmem_req_bits_0_bits_uop_lrs2),
.io_dmem_req_bits_0_bits_uop_lrs3 (_lsu_io_dmem_req_bits_0_bits_uop_lrs3),
.io_dmem_req_bits_0_bits_uop_ldst_val (_lsu_io_dmem_req_bits_0_bits_uop_ldst_val),
.io_dmem_req_bits_0_bits_uop_dst_rtype (_lsu_io_dmem_req_bits_0_bits_uop_dst_rtype),
.io_dmem_req_bits_0_bits_uop_lrs1_rtype (_lsu_io_dmem_req_bits_0_bits_uop_lrs1_rtype),
.io_dmem_req_bits_0_bits_uop_lrs2_rtype (_lsu_io_dmem_req_bits_0_bits_uop_lrs2_rtype),
.io_dmem_req_bits_0_bits_uop_frs3_en (_lsu_io_dmem_req_bits_0_bits_uop_frs3_en),
.io_dmem_req_bits_0_bits_uop_fp_val (_lsu_io_dmem_req_bits_0_bits_uop_fp_val),
.io_dmem_req_bits_0_bits_uop_fp_single (_lsu_io_dmem_req_bits_0_bits_uop_fp_single),
.io_dmem_req_bits_0_bits_uop_xcpt_pf_if (_lsu_io_dmem_req_bits_0_bits_uop_xcpt_pf_if),
.io_dmem_req_bits_0_bits_uop_xcpt_ae_if (_lsu_io_dmem_req_bits_0_bits_uop_xcpt_ae_if),
.io_dmem_req_bits_0_bits_uop_xcpt_ma_if (_lsu_io_dmem_req_bits_0_bits_uop_xcpt_ma_if),
.io_dmem_req_bits_0_bits_uop_bp_debug_if (_lsu_io_dmem_req_bits_0_bits_uop_bp_debug_if),
.io_dmem_req_bits_0_bits_uop_bp_xcpt_if (_lsu_io_dmem_req_bits_0_bits_uop_bp_xcpt_if),
.io_dmem_req_bits_0_bits_uop_debug_fsrc (_lsu_io_dmem_req_bits_0_bits_uop_debug_fsrc),
.io_dmem_req_bits_0_bits_uop_debug_tsrc (_lsu_io_dmem_req_bits_0_bits_uop_debug_tsrc),
.io_dmem_req_bits_0_bits_addr (_lsu_io_dmem_req_bits_0_bits_addr),
.io_dmem_req_bits_0_bits_data (_lsu_io_dmem_req_bits_0_bits_data),
.io_dmem_req_bits_0_bits_is_hella (_lsu_io_dmem_req_bits_0_bits_is_hella),
.io_dmem_s1_kill_0 (_lsu_io_dmem_s1_kill_0),
.io_dmem_resp_0_valid (_dcache_io_lsu_resp_0_valid), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_uopc (_dcache_io_lsu_resp_0_bits_uop_uopc), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_inst (_dcache_io_lsu_resp_0_bits_uop_inst), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_debug_inst (_dcache_io_lsu_resp_0_bits_uop_debug_inst), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_is_rvc (_dcache_io_lsu_resp_0_bits_uop_is_rvc), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_debug_pc (_dcache_io_lsu_resp_0_bits_uop_debug_pc), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_iq_type (_dcache_io_lsu_resp_0_bits_uop_iq_type), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_fu_code (_dcache_io_lsu_resp_0_bits_uop_fu_code), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_ctrl_br_type (_dcache_io_lsu_resp_0_bits_uop_ctrl_br_type), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_ctrl_op1_sel (_dcache_io_lsu_resp_0_bits_uop_ctrl_op1_sel), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_ctrl_op2_sel (_dcache_io_lsu_resp_0_bits_uop_ctrl_op2_sel), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_ctrl_imm_sel (_dcache_io_lsu_resp_0_bits_uop_ctrl_imm_sel), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_ctrl_op_fcn (_dcache_io_lsu_resp_0_bits_uop_ctrl_op_fcn), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_ctrl_fcn_dw (_dcache_io_lsu_resp_0_bits_uop_ctrl_fcn_dw), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_ctrl_csr_cmd (_dcache_io_lsu_resp_0_bits_uop_ctrl_csr_cmd), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_ctrl_is_load (_dcache_io_lsu_resp_0_bits_uop_ctrl_is_load), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_ctrl_is_sta (_dcache_io_lsu_resp_0_bits_uop_ctrl_is_sta), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_ctrl_is_std (_dcache_io_lsu_resp_0_bits_uop_ctrl_is_std), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_iw_state (_dcache_io_lsu_resp_0_bits_uop_iw_state), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_iw_p1_poisoned (_dcache_io_lsu_resp_0_bits_uop_iw_p1_poisoned), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_iw_p2_poisoned (_dcache_io_lsu_resp_0_bits_uop_iw_p2_poisoned), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_is_br (_dcache_io_lsu_resp_0_bits_uop_is_br), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_is_jalr (_dcache_io_lsu_resp_0_bits_uop_is_jalr), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_is_jal (_dcache_io_lsu_resp_0_bits_uop_is_jal), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_is_sfb (_dcache_io_lsu_resp_0_bits_uop_is_sfb), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_br_mask (_dcache_io_lsu_resp_0_bits_uop_br_mask), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_br_tag (_dcache_io_lsu_resp_0_bits_uop_br_tag), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_ftq_idx (_dcache_io_lsu_resp_0_bits_uop_ftq_idx), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_edge_inst (_dcache_io_lsu_resp_0_bits_uop_edge_inst), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_pc_lob (_dcache_io_lsu_resp_0_bits_uop_pc_lob), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_taken (_dcache_io_lsu_resp_0_bits_uop_taken), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_imm_packed (_dcache_io_lsu_resp_0_bits_uop_imm_packed), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_csr_addr (_dcache_io_lsu_resp_0_bits_uop_csr_addr), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_rob_idx (_dcache_io_lsu_resp_0_bits_uop_rob_idx), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_ldq_idx (_dcache_io_lsu_resp_0_bits_uop_ldq_idx), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_stq_idx (_dcache_io_lsu_resp_0_bits_uop_stq_idx), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_rxq_idx (_dcache_io_lsu_resp_0_bits_uop_rxq_idx), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_pdst (_dcache_io_lsu_resp_0_bits_uop_pdst), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_prs1 (_dcache_io_lsu_resp_0_bits_uop_prs1), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_prs2 (_dcache_io_lsu_resp_0_bits_uop_prs2), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_prs3 (_dcache_io_lsu_resp_0_bits_uop_prs3), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_ppred (_dcache_io_lsu_resp_0_bits_uop_ppred), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_prs1_busy (_dcache_io_lsu_resp_0_bits_uop_prs1_busy), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_prs2_busy (_dcache_io_lsu_resp_0_bits_uop_prs2_busy), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_prs3_busy (_dcache_io_lsu_resp_0_bits_uop_prs3_busy), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_ppred_busy (_dcache_io_lsu_resp_0_bits_uop_ppred_busy), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_stale_pdst (_dcache_io_lsu_resp_0_bits_uop_stale_pdst), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_exception (_dcache_io_lsu_resp_0_bits_uop_exception), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_exc_cause (_dcache_io_lsu_resp_0_bits_uop_exc_cause), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_bypassable (_dcache_io_lsu_resp_0_bits_uop_bypassable), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_mem_cmd (_dcache_io_lsu_resp_0_bits_uop_mem_cmd), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_mem_size (_dcache_io_lsu_resp_0_bits_uop_mem_size), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_mem_signed (_dcache_io_lsu_resp_0_bits_uop_mem_signed), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_is_fence (_dcache_io_lsu_resp_0_bits_uop_is_fence), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_is_fencei (_dcache_io_lsu_resp_0_bits_uop_is_fencei), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_is_amo (_dcache_io_lsu_resp_0_bits_uop_is_amo), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_uses_ldq (_dcache_io_lsu_resp_0_bits_uop_uses_ldq), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_uses_stq (_dcache_io_lsu_resp_0_bits_uop_uses_stq), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_is_sys_pc2epc (_dcache_io_lsu_resp_0_bits_uop_is_sys_pc2epc), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_is_unique (_dcache_io_lsu_resp_0_bits_uop_is_unique), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_flush_on_commit (_dcache_io_lsu_resp_0_bits_uop_flush_on_commit), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_ldst_is_rs1 (_dcache_io_lsu_resp_0_bits_uop_ldst_is_rs1), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_ldst (_dcache_io_lsu_resp_0_bits_uop_ldst), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_lrs1 (_dcache_io_lsu_resp_0_bits_uop_lrs1), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_lrs2 (_dcache_io_lsu_resp_0_bits_uop_lrs2), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_lrs3 (_dcache_io_lsu_resp_0_bits_uop_lrs3), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_ldst_val (_dcache_io_lsu_resp_0_bits_uop_ldst_val), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_dst_rtype (_dcache_io_lsu_resp_0_bits_uop_dst_rtype), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_lrs1_rtype (_dcache_io_lsu_resp_0_bits_uop_lrs1_rtype), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_lrs2_rtype (_dcache_io_lsu_resp_0_bits_uop_lrs2_rtype), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_frs3_en (_dcache_io_lsu_resp_0_bits_uop_frs3_en), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_fp_val (_dcache_io_lsu_resp_0_bits_uop_fp_val), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_fp_single (_dcache_io_lsu_resp_0_bits_uop_fp_single), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_xcpt_pf_if (_dcache_io_lsu_resp_0_bits_uop_xcpt_pf_if), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_xcpt_ae_if (_dcache_io_lsu_resp_0_bits_uop_xcpt_ae_if), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_xcpt_ma_if (_dcache_io_lsu_resp_0_bits_uop_xcpt_ma_if), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_bp_debug_if (_dcache_io_lsu_resp_0_bits_uop_bp_debug_if), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_bp_xcpt_if (_dcache_io_lsu_resp_0_bits_uop_bp_xcpt_if), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_debug_fsrc (_dcache_io_lsu_resp_0_bits_uop_debug_fsrc), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_debug_tsrc (_dcache_io_lsu_resp_0_bits_uop_debug_tsrc), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_data (_dcache_io_lsu_resp_0_bits_data), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_is_hella (_dcache_io_lsu_resp_0_bits_is_hella), // @[tile.scala:132:54]
.io_dmem_nack_0_valid (_dcache_io_lsu_nack_0_valid), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_uopc (_dcache_io_lsu_nack_0_bits_uop_uopc), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_inst (_dcache_io_lsu_nack_0_bits_uop_inst), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_debug_inst (_dcache_io_lsu_nack_0_bits_uop_debug_inst), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_is_rvc (_dcache_io_lsu_nack_0_bits_uop_is_rvc), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_debug_pc (_dcache_io_lsu_nack_0_bits_uop_debug_pc), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_iq_type (_dcache_io_lsu_nack_0_bits_uop_iq_type), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_fu_code (_dcache_io_lsu_nack_0_bits_uop_fu_code), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_ctrl_br_type (_dcache_io_lsu_nack_0_bits_uop_ctrl_br_type), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_ctrl_op1_sel (_dcache_io_lsu_nack_0_bits_uop_ctrl_op1_sel), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_ctrl_op2_sel (_dcache_io_lsu_nack_0_bits_uop_ctrl_op2_sel), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_ctrl_imm_sel (_dcache_io_lsu_nack_0_bits_uop_ctrl_imm_sel), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_ctrl_op_fcn (_dcache_io_lsu_nack_0_bits_uop_ctrl_op_fcn), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_ctrl_fcn_dw (_dcache_io_lsu_nack_0_bits_uop_ctrl_fcn_dw), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_ctrl_csr_cmd (_dcache_io_lsu_nack_0_bits_uop_ctrl_csr_cmd), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_ctrl_is_load (_dcache_io_lsu_nack_0_bits_uop_ctrl_is_load), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_ctrl_is_sta (_dcache_io_lsu_nack_0_bits_uop_ctrl_is_sta), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_ctrl_is_std (_dcache_io_lsu_nack_0_bits_uop_ctrl_is_std), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_iw_state (_dcache_io_lsu_nack_0_bits_uop_iw_state), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_iw_p1_poisoned (_dcache_io_lsu_nack_0_bits_uop_iw_p1_poisoned), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_iw_p2_poisoned (_dcache_io_lsu_nack_0_bits_uop_iw_p2_poisoned), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_is_br (_dcache_io_lsu_nack_0_bits_uop_is_br), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_is_jalr (_dcache_io_lsu_nack_0_bits_uop_is_jalr), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_is_jal (_dcache_io_lsu_nack_0_bits_uop_is_jal), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_is_sfb (_dcache_io_lsu_nack_0_bits_uop_is_sfb), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_br_mask (_dcache_io_lsu_nack_0_bits_uop_br_mask), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_br_tag (_dcache_io_lsu_nack_0_bits_uop_br_tag), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_ftq_idx (_dcache_io_lsu_nack_0_bits_uop_ftq_idx), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_edge_inst (_dcache_io_lsu_nack_0_bits_uop_edge_inst), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_pc_lob (_dcache_io_lsu_nack_0_bits_uop_pc_lob), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_taken (_dcache_io_lsu_nack_0_bits_uop_taken), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_imm_packed (_dcache_io_lsu_nack_0_bits_uop_imm_packed), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_csr_addr (_dcache_io_lsu_nack_0_bits_uop_csr_addr), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_rob_idx (_dcache_io_lsu_nack_0_bits_uop_rob_idx), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_ldq_idx (_dcache_io_lsu_nack_0_bits_uop_ldq_idx), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_stq_idx (_dcache_io_lsu_nack_0_bits_uop_stq_idx), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_rxq_idx (_dcache_io_lsu_nack_0_bits_uop_rxq_idx), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_pdst (_dcache_io_lsu_nack_0_bits_uop_pdst), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_prs1 (_dcache_io_lsu_nack_0_bits_uop_prs1), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_prs2 (_dcache_io_lsu_nack_0_bits_uop_prs2), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_prs3 (_dcache_io_lsu_nack_0_bits_uop_prs3), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_ppred (_dcache_io_lsu_nack_0_bits_uop_ppred), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_prs1_busy (_dcache_io_lsu_nack_0_bits_uop_prs1_busy), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_prs2_busy (_dcache_io_lsu_nack_0_bits_uop_prs2_busy), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_prs3_busy (_dcache_io_lsu_nack_0_bits_uop_prs3_busy), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_ppred_busy (_dcache_io_lsu_nack_0_bits_uop_ppred_busy), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_stale_pdst (_dcache_io_lsu_nack_0_bits_uop_stale_pdst), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_exception (_dcache_io_lsu_nack_0_bits_uop_exception), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_exc_cause (_dcache_io_lsu_nack_0_bits_uop_exc_cause), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_bypassable (_dcache_io_lsu_nack_0_bits_uop_bypassable), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_mem_cmd (_dcache_io_lsu_nack_0_bits_uop_mem_cmd), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_mem_size (_dcache_io_lsu_nack_0_bits_uop_mem_size), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_mem_signed (_dcache_io_lsu_nack_0_bits_uop_mem_signed), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_is_fence (_dcache_io_lsu_nack_0_bits_uop_is_fence), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_is_fencei (_dcache_io_lsu_nack_0_bits_uop_is_fencei), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_is_amo (_dcache_io_lsu_nack_0_bits_uop_is_amo), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_uses_ldq (_dcache_io_lsu_nack_0_bits_uop_uses_ldq), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_uses_stq (_dcache_io_lsu_nack_0_bits_uop_uses_stq), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_is_sys_pc2epc (_dcache_io_lsu_nack_0_bits_uop_is_sys_pc2epc), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_is_unique (_dcache_io_lsu_nack_0_bits_uop_is_unique), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_flush_on_commit (_dcache_io_lsu_nack_0_bits_uop_flush_on_commit), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_ldst_is_rs1 (_dcache_io_lsu_nack_0_bits_uop_ldst_is_rs1), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_ldst (_dcache_io_lsu_nack_0_bits_uop_ldst), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_lrs1 (_dcache_io_lsu_nack_0_bits_uop_lrs1), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_lrs2 (_dcache_io_lsu_nack_0_bits_uop_lrs2), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_lrs3 (_dcache_io_lsu_nack_0_bits_uop_lrs3), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_ldst_val (_dcache_io_lsu_nack_0_bits_uop_ldst_val), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_dst_rtype (_dcache_io_lsu_nack_0_bits_uop_dst_rtype), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_lrs1_rtype (_dcache_io_lsu_nack_0_bits_uop_lrs1_rtype), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_lrs2_rtype (_dcache_io_lsu_nack_0_bits_uop_lrs2_rtype), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_frs3_en (_dcache_io_lsu_nack_0_bits_uop_frs3_en), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_fp_val (_dcache_io_lsu_nack_0_bits_uop_fp_val), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_fp_single (_dcache_io_lsu_nack_0_bits_uop_fp_single), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_xcpt_pf_if (_dcache_io_lsu_nack_0_bits_uop_xcpt_pf_if), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_xcpt_ae_if (_dcache_io_lsu_nack_0_bits_uop_xcpt_ae_if), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_xcpt_ma_if (_dcache_io_lsu_nack_0_bits_uop_xcpt_ma_if), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_bp_debug_if (_dcache_io_lsu_nack_0_bits_uop_bp_debug_if), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_bp_xcpt_if (_dcache_io_lsu_nack_0_bits_uop_bp_xcpt_if), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_debug_fsrc (_dcache_io_lsu_nack_0_bits_uop_debug_fsrc), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_debug_tsrc (_dcache_io_lsu_nack_0_bits_uop_debug_tsrc), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_addr (_dcache_io_lsu_nack_0_bits_addr), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_data (_dcache_io_lsu_nack_0_bits_data), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_is_hella (_dcache_io_lsu_nack_0_bits_is_hella), // @[tile.scala:132:54]
.io_dmem_brupdate_b1_resolve_mask (_lsu_io_dmem_brupdate_b1_resolve_mask),
.io_dmem_brupdate_b1_mispredict_mask (_lsu_io_dmem_brupdate_b1_mispredict_mask),
.io_dmem_brupdate_b2_uop_uopc (_lsu_io_dmem_brupdate_b2_uop_uopc),
.io_dmem_brupdate_b2_uop_inst (_lsu_io_dmem_brupdate_b2_uop_inst),
.io_dmem_brupdate_b2_uop_debug_inst (_lsu_io_dmem_brupdate_b2_uop_debug_inst),
.io_dmem_brupdate_b2_uop_is_rvc (_lsu_io_dmem_brupdate_b2_uop_is_rvc),
.io_dmem_brupdate_b2_uop_debug_pc (_lsu_io_dmem_brupdate_b2_uop_debug_pc),
.io_dmem_brupdate_b2_uop_iq_type (_lsu_io_dmem_brupdate_b2_uop_iq_type),
.io_dmem_brupdate_b2_uop_fu_code (_lsu_io_dmem_brupdate_b2_uop_fu_code),
.io_dmem_brupdate_b2_uop_ctrl_br_type (_lsu_io_dmem_brupdate_b2_uop_ctrl_br_type),
.io_dmem_brupdate_b2_uop_ctrl_op1_sel (_lsu_io_dmem_brupdate_b2_uop_ctrl_op1_sel),
.io_dmem_brupdate_b2_uop_ctrl_op2_sel (_lsu_io_dmem_brupdate_b2_uop_ctrl_op2_sel),
.io_dmem_brupdate_b2_uop_ctrl_imm_sel (_lsu_io_dmem_brupdate_b2_uop_ctrl_imm_sel),
.io_dmem_brupdate_b2_uop_ctrl_op_fcn (_lsu_io_dmem_brupdate_b2_uop_ctrl_op_fcn),
.io_dmem_brupdate_b2_uop_ctrl_fcn_dw (_lsu_io_dmem_brupdate_b2_uop_ctrl_fcn_dw),
.io_dmem_brupdate_b2_uop_ctrl_csr_cmd (_lsu_io_dmem_brupdate_b2_uop_ctrl_csr_cmd),
.io_dmem_brupdate_b2_uop_ctrl_is_load (_lsu_io_dmem_brupdate_b2_uop_ctrl_is_load),
.io_dmem_brupdate_b2_uop_ctrl_is_sta (_lsu_io_dmem_brupdate_b2_uop_ctrl_is_sta),
.io_dmem_brupdate_b2_uop_ctrl_is_std (_lsu_io_dmem_brupdate_b2_uop_ctrl_is_std),
.io_dmem_brupdate_b2_uop_iw_state (_lsu_io_dmem_brupdate_b2_uop_iw_state),
.io_dmem_brupdate_b2_uop_iw_p1_poisoned (_lsu_io_dmem_brupdate_b2_uop_iw_p1_poisoned),
.io_dmem_brupdate_b2_uop_iw_p2_poisoned (_lsu_io_dmem_brupdate_b2_uop_iw_p2_poisoned),
.io_dmem_brupdate_b2_uop_is_br (_lsu_io_dmem_brupdate_b2_uop_is_br),
.io_dmem_brupdate_b2_uop_is_jalr (_lsu_io_dmem_brupdate_b2_uop_is_jalr),
.io_dmem_brupdate_b2_uop_is_jal (_lsu_io_dmem_brupdate_b2_uop_is_jal),
.io_dmem_brupdate_b2_uop_is_sfb (_lsu_io_dmem_brupdate_b2_uop_is_sfb),
.io_dmem_brupdate_b2_uop_br_mask (_lsu_io_dmem_brupdate_b2_uop_br_mask),
.io_dmem_brupdate_b2_uop_br_tag (_lsu_io_dmem_brupdate_b2_uop_br_tag),
.io_dmem_brupdate_b2_uop_ftq_idx (_lsu_io_dmem_brupdate_b2_uop_ftq_idx),
.io_dmem_brupdate_b2_uop_edge_inst (_lsu_io_dmem_brupdate_b2_uop_edge_inst),
.io_dmem_brupdate_b2_uop_pc_lob (_lsu_io_dmem_brupdate_b2_uop_pc_lob),
.io_dmem_brupdate_b2_uop_taken (_lsu_io_dmem_brupdate_b2_uop_taken),
.io_dmem_brupdate_b2_uop_imm_packed (_lsu_io_dmem_brupdate_b2_uop_imm_packed),
.io_dmem_brupdate_b2_uop_csr_addr (_lsu_io_dmem_brupdate_b2_uop_csr_addr),
.io_dmem_brupdate_b2_uop_rob_idx (_lsu_io_dmem_brupdate_b2_uop_rob_idx),
.io_dmem_brupdate_b2_uop_ldq_idx (_lsu_io_dmem_brupdate_b2_uop_ldq_idx),
.io_dmem_brupdate_b2_uop_stq_idx (_lsu_io_dmem_brupdate_b2_uop_stq_idx),
.io_dmem_brupdate_b2_uop_rxq_idx (_lsu_io_dmem_brupdate_b2_uop_rxq_idx),
.io_dmem_brupdate_b2_uop_pdst (_lsu_io_dmem_brupdate_b2_uop_pdst),
.io_dmem_brupdate_b2_uop_prs1 (_lsu_io_dmem_brupdate_b2_uop_prs1),
.io_dmem_brupdate_b2_uop_prs2 (_lsu_io_dmem_brupdate_b2_uop_prs2),
.io_dmem_brupdate_b2_uop_prs3 (_lsu_io_dmem_brupdate_b2_uop_prs3),
.io_dmem_brupdate_b2_uop_ppred (_lsu_io_dmem_brupdate_b2_uop_ppred),
.io_dmem_brupdate_b2_uop_prs1_busy (_lsu_io_dmem_brupdate_b2_uop_prs1_busy),
.io_dmem_brupdate_b2_uop_prs2_busy (_lsu_io_dmem_brupdate_b2_uop_prs2_busy),
.io_dmem_brupdate_b2_uop_prs3_busy (_lsu_io_dmem_brupdate_b2_uop_prs3_busy),
.io_dmem_brupdate_b2_uop_ppred_busy (_lsu_io_dmem_brupdate_b2_uop_ppred_busy),
.io_dmem_brupdate_b2_uop_stale_pdst (_lsu_io_dmem_brupdate_b2_uop_stale_pdst),
.io_dmem_brupdate_b2_uop_exception (_lsu_io_dmem_brupdate_b2_uop_exception),
.io_dmem_brupdate_b2_uop_exc_cause (_lsu_io_dmem_brupdate_b2_uop_exc_cause),
.io_dmem_brupdate_b2_uop_bypassable (_lsu_io_dmem_brupdate_b2_uop_bypassable),
.io_dmem_brupdate_b2_uop_mem_cmd (_lsu_io_dmem_brupdate_b2_uop_mem_cmd),
.io_dmem_brupdate_b2_uop_mem_size (_lsu_io_dmem_brupdate_b2_uop_mem_size),
.io_dmem_brupdate_b2_uop_mem_signed (_lsu_io_dmem_brupdate_b2_uop_mem_signed),
.io_dmem_brupdate_b2_uop_is_fence (_lsu_io_dmem_brupdate_b2_uop_is_fence),
.io_dmem_brupdate_b2_uop_is_fencei (_lsu_io_dmem_brupdate_b2_uop_is_fencei),
.io_dmem_brupdate_b2_uop_is_amo (_lsu_io_dmem_brupdate_b2_uop_is_amo),
.io_dmem_brupdate_b2_uop_uses_ldq (_lsu_io_dmem_brupdate_b2_uop_uses_ldq),
.io_dmem_brupdate_b2_uop_uses_stq (_lsu_io_dmem_brupdate_b2_uop_uses_stq),
.io_dmem_brupdate_b2_uop_is_sys_pc2epc (_lsu_io_dmem_brupdate_b2_uop_is_sys_pc2epc),
.io_dmem_brupdate_b2_uop_is_unique (_lsu_io_dmem_brupdate_b2_uop_is_unique),
.io_dmem_brupdate_b2_uop_flush_on_commit (_lsu_io_dmem_brupdate_b2_uop_flush_on_commit),
.io_dmem_brupdate_b2_uop_ldst_is_rs1 (_lsu_io_dmem_brupdate_b2_uop_ldst_is_rs1),
.io_dmem_brupdate_b2_uop_ldst (_lsu_io_dmem_brupdate_b2_uop_ldst),
.io_dmem_brupdate_b2_uop_lrs1 (_lsu_io_dmem_brupdate_b2_uop_lrs1),
.io_dmem_brupdate_b2_uop_lrs2 (_lsu_io_dmem_brupdate_b2_uop_lrs2),
.io_dmem_brupdate_b2_uop_lrs3 (_lsu_io_dmem_brupdate_b2_uop_lrs3),
.io_dmem_brupdate_b2_uop_ldst_val (_lsu_io_dmem_brupdate_b2_uop_ldst_val),
.io_dmem_brupdate_b2_uop_dst_rtype (_lsu_io_dmem_brupdate_b2_uop_dst_rtype),
.io_dmem_brupdate_b2_uop_lrs1_rtype (_lsu_io_dmem_brupdate_b2_uop_lrs1_rtype),
.io_dmem_brupdate_b2_uop_lrs2_rtype (_lsu_io_dmem_brupdate_b2_uop_lrs2_rtype),
.io_dmem_brupdate_b2_uop_frs3_en (_lsu_io_dmem_brupdate_b2_uop_frs3_en),
.io_dmem_brupdate_b2_uop_fp_val (_lsu_io_dmem_brupdate_b2_uop_fp_val),
.io_dmem_brupdate_b2_uop_fp_single (_lsu_io_dmem_brupdate_b2_uop_fp_single),
.io_dmem_brupdate_b2_uop_xcpt_pf_if (_lsu_io_dmem_brupdate_b2_uop_xcpt_pf_if),
.io_dmem_brupdate_b2_uop_xcpt_ae_if (_lsu_io_dmem_brupdate_b2_uop_xcpt_ae_if),
.io_dmem_brupdate_b2_uop_xcpt_ma_if (_lsu_io_dmem_brupdate_b2_uop_xcpt_ma_if),
.io_dmem_brupdate_b2_uop_bp_debug_if (_lsu_io_dmem_brupdate_b2_uop_bp_debug_if),
.io_dmem_brupdate_b2_uop_bp_xcpt_if (_lsu_io_dmem_brupdate_b2_uop_bp_xcpt_if),
.io_dmem_brupdate_b2_uop_debug_fsrc (_lsu_io_dmem_brupdate_b2_uop_debug_fsrc),
.io_dmem_brupdate_b2_uop_debug_tsrc (_lsu_io_dmem_brupdate_b2_uop_debug_tsrc),
.io_dmem_brupdate_b2_valid (_lsu_io_dmem_brupdate_b2_valid),
.io_dmem_brupdate_b2_mispredict (_lsu_io_dmem_brupdate_b2_mispredict),
.io_dmem_brupdate_b2_taken (_lsu_io_dmem_brupdate_b2_taken),
.io_dmem_brupdate_b2_cfi_type (_lsu_io_dmem_brupdate_b2_cfi_type),
.io_dmem_brupdate_b2_pc_sel (_lsu_io_dmem_brupdate_b2_pc_sel),
.io_dmem_brupdate_b2_jalr_target (_lsu_io_dmem_brupdate_b2_jalr_target),
.io_dmem_brupdate_b2_target_offset (_lsu_io_dmem_brupdate_b2_target_offset),
.io_dmem_exception (_lsu_io_dmem_exception),
.io_dmem_rob_pnr_idx (_lsu_io_dmem_rob_pnr_idx),
.io_dmem_rob_head_idx (_lsu_io_dmem_rob_head_idx),
.io_dmem_release_ready (_lsu_io_dmem_release_ready),
.io_dmem_release_valid (_dcache_io_lsu_release_valid), // @[tile.scala:132:54]
.io_dmem_release_bits_opcode (_dcache_io_lsu_release_bits_opcode), // @[tile.scala:132:54]
.io_dmem_release_bits_param (_dcache_io_lsu_release_bits_param), // @[tile.scala:132:54]
.io_dmem_release_bits_size (_dcache_io_lsu_release_bits_size), // @[tile.scala:132:54]
.io_dmem_release_bits_source (_dcache_io_lsu_release_bits_source), // @[tile.scala:132:54]
.io_dmem_release_bits_address (_dcache_io_lsu_release_bits_address), // @[tile.scala:132:54]
.io_dmem_release_bits_data (_dcache_io_lsu_release_bits_data), // @[tile.scala:132:54]
.io_dmem_force_order (_lsu_io_dmem_force_order),
.io_dmem_ordered (_dcache_io_lsu_ordered), // @[tile.scala:132:54]
.io_dmem_perf_acquire (_dcache_io_lsu_perf_acquire), // @[tile.scala:132:54]
.io_dmem_perf_release (_dcache_io_lsu_perf_release), // @[tile.scala:132:54]
.io_hellacache_req_ready (_lsu_io_hellacache_req_ready),
.io_hellacache_req_valid (_hellaCacheArb_io_mem_req_valid), // @[tile.scala:243:29]
.io_hellacache_req_bits_addr (_hellaCacheArb_io_mem_req_bits_addr), // @[tile.scala:243:29]
.io_hellacache_req_bits_dv (_hellaCacheArb_io_mem_req_bits_dv), // @[tile.scala:243:29]
.io_hellacache_s1_kill (_hellaCacheArb_io_mem_s1_kill), // @[tile.scala:243:29]
.io_hellacache_s2_nack (_lsu_io_hellacache_s2_nack),
.io_hellacache_resp_valid (_lsu_io_hellacache_resp_valid),
.io_hellacache_resp_bits_addr (_lsu_io_hellacache_resp_bits_addr),
.io_hellacache_resp_bits_data (_lsu_io_hellacache_resp_bits_data),
.io_hellacache_s2_xcpt_ma_ld (_lsu_io_hellacache_s2_xcpt_ma_ld),
.io_hellacache_s2_xcpt_ma_st (_lsu_io_hellacache_s2_xcpt_ma_st),
.io_hellacache_s2_xcpt_pf_ld (_lsu_io_hellacache_s2_xcpt_pf_ld),
.io_hellacache_s2_xcpt_pf_st (_lsu_io_hellacache_s2_xcpt_pf_st),
.io_hellacache_s2_xcpt_gf_ld (_lsu_io_hellacache_s2_xcpt_gf_ld),
.io_hellacache_s2_xcpt_gf_st (_lsu_io_hellacache_s2_xcpt_gf_st),
.io_hellacache_s2_xcpt_ae_ld (_lsu_io_hellacache_s2_xcpt_ae_ld),
.io_hellacache_s2_xcpt_ae_st (_lsu_io_hellacache_s2_xcpt_ae_st),
.io_hellacache_store_pending (_lsu_io_hellacache_store_pending)
); // @[tile.scala:160:20]
PTW ptw ( // @[tile.scala:237:20]
.clock (clock),
.reset (reset),
.io_requestor_0_req_ready (_ptw_io_requestor_0_req_ready),
.io_requestor_0_req_valid (_lsu_io_ptw_req_valid), // @[tile.scala:160:20]
.io_requestor_0_req_bits_valid (_lsu_io_ptw_req_bits_valid), // @[tile.scala:160:20]
.io_requestor_0_req_bits_bits_addr (_lsu_io_ptw_req_bits_bits_addr), // @[tile.scala:160:20]
.io_requestor_0_resp_valid (_ptw_io_requestor_0_resp_valid),
.io_requestor_0_resp_bits_ae_ptw (_ptw_io_requestor_0_resp_bits_ae_ptw),
.io_requestor_0_resp_bits_ae_final (_ptw_io_requestor_0_resp_bits_ae_final),
.io_requestor_0_resp_bits_pf (_ptw_io_requestor_0_resp_bits_pf),
.io_requestor_0_resp_bits_gf (_ptw_io_requestor_0_resp_bits_gf),
.io_requestor_0_resp_bits_hr (_ptw_io_requestor_0_resp_bits_hr),
.io_requestor_0_resp_bits_hw (_ptw_io_requestor_0_resp_bits_hw),
.io_requestor_0_resp_bits_hx (_ptw_io_requestor_0_resp_bits_hx),
.io_requestor_0_resp_bits_pte_reserved_for_future (_ptw_io_requestor_0_resp_bits_pte_reserved_for_future),
.io_requestor_0_resp_bits_pte_ppn (_ptw_io_requestor_0_resp_bits_pte_ppn),
.io_requestor_0_resp_bits_pte_reserved_for_software (_ptw_io_requestor_0_resp_bits_pte_reserved_for_software),
.io_requestor_0_resp_bits_pte_d (_ptw_io_requestor_0_resp_bits_pte_d),
.io_requestor_0_resp_bits_pte_a (_ptw_io_requestor_0_resp_bits_pte_a),
.io_requestor_0_resp_bits_pte_g (_ptw_io_requestor_0_resp_bits_pte_g),
.io_requestor_0_resp_bits_pte_u (_ptw_io_requestor_0_resp_bits_pte_u),
.io_requestor_0_resp_bits_pte_x (_ptw_io_requestor_0_resp_bits_pte_x),
.io_requestor_0_resp_bits_pte_w (_ptw_io_requestor_0_resp_bits_pte_w),
.io_requestor_0_resp_bits_pte_r (_ptw_io_requestor_0_resp_bits_pte_r),
.io_requestor_0_resp_bits_pte_v (_ptw_io_requestor_0_resp_bits_pte_v),
.io_requestor_0_resp_bits_level (_ptw_io_requestor_0_resp_bits_level),
.io_requestor_0_resp_bits_homogeneous (_ptw_io_requestor_0_resp_bits_homogeneous),
.io_requestor_0_resp_bits_gpa_valid (_ptw_io_requestor_0_resp_bits_gpa_valid),
.io_requestor_0_resp_bits_gpa_bits (_ptw_io_requestor_0_resp_bits_gpa_bits),
.io_requestor_0_resp_bits_gpa_is_pte (_ptw_io_requestor_0_resp_bits_gpa_is_pte),
.io_requestor_0_ptbr_mode (_ptw_io_requestor_0_ptbr_mode),
.io_requestor_0_ptbr_ppn (_ptw_io_requestor_0_ptbr_ppn),
.io_requestor_0_status_debug (_ptw_io_requestor_0_status_debug),
.io_requestor_0_status_cease (_ptw_io_requestor_0_status_cease),
.io_requestor_0_status_wfi (_ptw_io_requestor_0_status_wfi),
.io_requestor_0_status_dprv (_ptw_io_requestor_0_status_dprv),
.io_requestor_0_status_dv (_ptw_io_requestor_0_status_dv),
.io_requestor_0_status_prv (_ptw_io_requestor_0_status_prv),
.io_requestor_0_status_v (_ptw_io_requestor_0_status_v),
.io_requestor_0_status_sd (_ptw_io_requestor_0_status_sd),
.io_requestor_0_status_mpv (_ptw_io_requestor_0_status_mpv),
.io_requestor_0_status_gva (_ptw_io_requestor_0_status_gva),
.io_requestor_0_status_tsr (_ptw_io_requestor_0_status_tsr),
.io_requestor_0_status_tw (_ptw_io_requestor_0_status_tw),
.io_requestor_0_status_tvm (_ptw_io_requestor_0_status_tvm),
.io_requestor_0_status_mxr (_ptw_io_requestor_0_status_mxr),
.io_requestor_0_status_sum (_ptw_io_requestor_0_status_sum),
.io_requestor_0_status_mprv (_ptw_io_requestor_0_status_mprv),
.io_requestor_0_status_fs (_ptw_io_requestor_0_status_fs),
.io_requestor_0_status_mpp (_ptw_io_requestor_0_status_mpp),
.io_requestor_0_status_spp (_ptw_io_requestor_0_status_spp),
.io_requestor_0_status_mpie (_ptw_io_requestor_0_status_mpie),
.io_requestor_0_status_spie (_ptw_io_requestor_0_status_spie),
.io_requestor_0_status_mie (_ptw_io_requestor_0_status_mie),
.io_requestor_0_status_sie (_ptw_io_requestor_0_status_sie),
.io_requestor_0_pmp_0_cfg_l (_ptw_io_requestor_0_pmp_0_cfg_l),
.io_requestor_0_pmp_0_cfg_a (_ptw_io_requestor_0_pmp_0_cfg_a),
.io_requestor_0_pmp_0_cfg_x (_ptw_io_requestor_0_pmp_0_cfg_x),
.io_requestor_0_pmp_0_cfg_w (_ptw_io_requestor_0_pmp_0_cfg_w),
.io_requestor_0_pmp_0_cfg_r (_ptw_io_requestor_0_pmp_0_cfg_r),
.io_requestor_0_pmp_0_addr (_ptw_io_requestor_0_pmp_0_addr),
.io_requestor_0_pmp_0_mask (_ptw_io_requestor_0_pmp_0_mask),
.io_requestor_0_pmp_1_cfg_l (_ptw_io_requestor_0_pmp_1_cfg_l),
.io_requestor_0_pmp_1_cfg_a (_ptw_io_requestor_0_pmp_1_cfg_a),
.io_requestor_0_pmp_1_cfg_x (_ptw_io_requestor_0_pmp_1_cfg_x),
.io_requestor_0_pmp_1_cfg_w (_ptw_io_requestor_0_pmp_1_cfg_w),
.io_requestor_0_pmp_1_cfg_r (_ptw_io_requestor_0_pmp_1_cfg_r),
.io_requestor_0_pmp_1_addr (_ptw_io_requestor_0_pmp_1_addr),
.io_requestor_0_pmp_1_mask (_ptw_io_requestor_0_pmp_1_mask),
.io_requestor_0_pmp_2_cfg_l (_ptw_io_requestor_0_pmp_2_cfg_l),
.io_requestor_0_pmp_2_cfg_a (_ptw_io_requestor_0_pmp_2_cfg_a),
.io_requestor_0_pmp_2_cfg_x (_ptw_io_requestor_0_pmp_2_cfg_x),
.io_requestor_0_pmp_2_cfg_w (_ptw_io_requestor_0_pmp_2_cfg_w),
.io_requestor_0_pmp_2_cfg_r (_ptw_io_requestor_0_pmp_2_cfg_r),
.io_requestor_0_pmp_2_addr (_ptw_io_requestor_0_pmp_2_addr),
.io_requestor_0_pmp_2_mask (_ptw_io_requestor_0_pmp_2_mask),
.io_requestor_0_pmp_3_cfg_l (_ptw_io_requestor_0_pmp_3_cfg_l),
.io_requestor_0_pmp_3_cfg_a (_ptw_io_requestor_0_pmp_3_cfg_a),
.io_requestor_0_pmp_3_cfg_x (_ptw_io_requestor_0_pmp_3_cfg_x),
.io_requestor_0_pmp_3_cfg_w (_ptw_io_requestor_0_pmp_3_cfg_w),
.io_requestor_0_pmp_3_cfg_r (_ptw_io_requestor_0_pmp_3_cfg_r),
.io_requestor_0_pmp_3_addr (_ptw_io_requestor_0_pmp_3_addr),
.io_requestor_0_pmp_3_mask (_ptw_io_requestor_0_pmp_3_mask),
.io_requestor_0_pmp_4_cfg_l (_ptw_io_requestor_0_pmp_4_cfg_l),
.io_requestor_0_pmp_4_cfg_a (_ptw_io_requestor_0_pmp_4_cfg_a),
.io_requestor_0_pmp_4_cfg_x (_ptw_io_requestor_0_pmp_4_cfg_x),
.io_requestor_0_pmp_4_cfg_w (_ptw_io_requestor_0_pmp_4_cfg_w),
.io_requestor_0_pmp_4_cfg_r (_ptw_io_requestor_0_pmp_4_cfg_r),
.io_requestor_0_pmp_4_addr (_ptw_io_requestor_0_pmp_4_addr),
.io_requestor_0_pmp_4_mask (_ptw_io_requestor_0_pmp_4_mask),
.io_requestor_0_pmp_5_cfg_l (_ptw_io_requestor_0_pmp_5_cfg_l),
.io_requestor_0_pmp_5_cfg_a (_ptw_io_requestor_0_pmp_5_cfg_a),
.io_requestor_0_pmp_5_cfg_x (_ptw_io_requestor_0_pmp_5_cfg_x),
.io_requestor_0_pmp_5_cfg_w (_ptw_io_requestor_0_pmp_5_cfg_w),
.io_requestor_0_pmp_5_cfg_r (_ptw_io_requestor_0_pmp_5_cfg_r),
.io_requestor_0_pmp_5_addr (_ptw_io_requestor_0_pmp_5_addr),
.io_requestor_0_pmp_5_mask (_ptw_io_requestor_0_pmp_5_mask),
.io_requestor_0_pmp_6_cfg_l (_ptw_io_requestor_0_pmp_6_cfg_l),
.io_requestor_0_pmp_6_cfg_a (_ptw_io_requestor_0_pmp_6_cfg_a),
.io_requestor_0_pmp_6_cfg_x (_ptw_io_requestor_0_pmp_6_cfg_x),
.io_requestor_0_pmp_6_cfg_w (_ptw_io_requestor_0_pmp_6_cfg_w),
.io_requestor_0_pmp_6_cfg_r (_ptw_io_requestor_0_pmp_6_cfg_r),
.io_requestor_0_pmp_6_addr (_ptw_io_requestor_0_pmp_6_addr),
.io_requestor_0_pmp_6_mask (_ptw_io_requestor_0_pmp_6_mask),
.io_requestor_0_pmp_7_cfg_l (_ptw_io_requestor_0_pmp_7_cfg_l),
.io_requestor_0_pmp_7_cfg_a (_ptw_io_requestor_0_pmp_7_cfg_a),
.io_requestor_0_pmp_7_cfg_x (_ptw_io_requestor_0_pmp_7_cfg_x),
.io_requestor_0_pmp_7_cfg_w (_ptw_io_requestor_0_pmp_7_cfg_w),
.io_requestor_0_pmp_7_cfg_r (_ptw_io_requestor_0_pmp_7_cfg_r),
.io_requestor_0_pmp_7_addr (_ptw_io_requestor_0_pmp_7_addr),
.io_requestor_0_pmp_7_mask (_ptw_io_requestor_0_pmp_7_mask),
.io_requestor_1_req_ready (_ptw_io_requestor_1_req_ready),
.io_requestor_1_req_valid (_frontend_io_ptw_req_valid), // @[tile.scala:138:28]
.io_requestor_1_req_bits_bits_addr (_frontend_io_ptw_req_bits_bits_addr), // @[tile.scala:138:28]
.io_requestor_1_req_bits_bits_need_gpa (_frontend_io_ptw_req_bits_bits_need_gpa), // @[tile.scala:138:28]
.io_requestor_1_resp_valid (_ptw_io_requestor_1_resp_valid),
.io_requestor_1_resp_bits_ae_ptw (_ptw_io_requestor_1_resp_bits_ae_ptw),
.io_requestor_1_resp_bits_ae_final (_ptw_io_requestor_1_resp_bits_ae_final),
.io_requestor_1_resp_bits_pf (_ptw_io_requestor_1_resp_bits_pf),
.io_requestor_1_resp_bits_gf (_ptw_io_requestor_1_resp_bits_gf),
.io_requestor_1_resp_bits_hr (_ptw_io_requestor_1_resp_bits_hr),
.io_requestor_1_resp_bits_hw (_ptw_io_requestor_1_resp_bits_hw),
.io_requestor_1_resp_bits_hx (_ptw_io_requestor_1_resp_bits_hx),
.io_requestor_1_resp_bits_pte_reserved_for_future (_ptw_io_requestor_1_resp_bits_pte_reserved_for_future),
.io_requestor_1_resp_bits_pte_ppn (_ptw_io_requestor_1_resp_bits_pte_ppn),
.io_requestor_1_resp_bits_pte_reserved_for_software (_ptw_io_requestor_1_resp_bits_pte_reserved_for_software),
.io_requestor_1_resp_bits_pte_d (_ptw_io_requestor_1_resp_bits_pte_d),
.io_requestor_1_resp_bits_pte_a (_ptw_io_requestor_1_resp_bits_pte_a),
.io_requestor_1_resp_bits_pte_g (_ptw_io_requestor_1_resp_bits_pte_g),
.io_requestor_1_resp_bits_pte_u (_ptw_io_requestor_1_resp_bits_pte_u),
.io_requestor_1_resp_bits_pte_x (_ptw_io_requestor_1_resp_bits_pte_x),
.io_requestor_1_resp_bits_pte_w (_ptw_io_requestor_1_resp_bits_pte_w),
.io_requestor_1_resp_bits_pte_r (_ptw_io_requestor_1_resp_bits_pte_r),
.io_requestor_1_resp_bits_pte_v (_ptw_io_requestor_1_resp_bits_pte_v),
.io_requestor_1_resp_bits_level (_ptw_io_requestor_1_resp_bits_level),
.io_requestor_1_resp_bits_homogeneous (_ptw_io_requestor_1_resp_bits_homogeneous),
.io_requestor_1_resp_bits_gpa_valid (_ptw_io_requestor_1_resp_bits_gpa_valid),
.io_requestor_1_resp_bits_gpa_bits (_ptw_io_requestor_1_resp_bits_gpa_bits),
.io_requestor_1_resp_bits_gpa_is_pte (_ptw_io_requestor_1_resp_bits_gpa_is_pte),
.io_requestor_1_ptbr_mode (_ptw_io_requestor_1_ptbr_mode),
.io_requestor_1_ptbr_ppn (_ptw_io_requestor_1_ptbr_ppn),
.io_requestor_1_status_debug (_ptw_io_requestor_1_status_debug),
.io_requestor_1_status_cease (_ptw_io_requestor_1_status_cease),
.io_requestor_1_status_wfi (_ptw_io_requestor_1_status_wfi),
.io_requestor_1_status_dprv (_ptw_io_requestor_1_status_dprv),
.io_requestor_1_status_dv (_ptw_io_requestor_1_status_dv),
.io_requestor_1_status_prv (_ptw_io_requestor_1_status_prv),
.io_requestor_1_status_v (_ptw_io_requestor_1_status_v),
.io_requestor_1_status_sd (_ptw_io_requestor_1_status_sd),
.io_requestor_1_status_mpv (_ptw_io_requestor_1_status_mpv),
.io_requestor_1_status_gva (_ptw_io_requestor_1_status_gva),
.io_requestor_1_status_tsr (_ptw_io_requestor_1_status_tsr),
.io_requestor_1_status_tw (_ptw_io_requestor_1_status_tw),
.io_requestor_1_status_tvm (_ptw_io_requestor_1_status_tvm),
.io_requestor_1_status_mxr (_ptw_io_requestor_1_status_mxr),
.io_requestor_1_status_sum (_ptw_io_requestor_1_status_sum),
.io_requestor_1_status_mprv (_ptw_io_requestor_1_status_mprv),
.io_requestor_1_status_fs (_ptw_io_requestor_1_status_fs),
.io_requestor_1_status_mpp (_ptw_io_requestor_1_status_mpp),
.io_requestor_1_status_spp (_ptw_io_requestor_1_status_spp),
.io_requestor_1_status_mpie (_ptw_io_requestor_1_status_mpie),
.io_requestor_1_status_spie (_ptw_io_requestor_1_status_spie),
.io_requestor_1_status_mie (_ptw_io_requestor_1_status_mie),
.io_requestor_1_status_sie (_ptw_io_requestor_1_status_sie),
.io_requestor_1_pmp_0_cfg_l (_ptw_io_requestor_1_pmp_0_cfg_l),
.io_requestor_1_pmp_0_cfg_a (_ptw_io_requestor_1_pmp_0_cfg_a),
.io_requestor_1_pmp_0_cfg_x (_ptw_io_requestor_1_pmp_0_cfg_x),
.io_requestor_1_pmp_0_cfg_w (_ptw_io_requestor_1_pmp_0_cfg_w),
.io_requestor_1_pmp_0_cfg_r (_ptw_io_requestor_1_pmp_0_cfg_r),
.io_requestor_1_pmp_0_addr (_ptw_io_requestor_1_pmp_0_addr),
.io_requestor_1_pmp_0_mask (_ptw_io_requestor_1_pmp_0_mask),
.io_requestor_1_pmp_1_cfg_l (_ptw_io_requestor_1_pmp_1_cfg_l),
.io_requestor_1_pmp_1_cfg_a (_ptw_io_requestor_1_pmp_1_cfg_a),
.io_requestor_1_pmp_1_cfg_x (_ptw_io_requestor_1_pmp_1_cfg_x),
.io_requestor_1_pmp_1_cfg_w (_ptw_io_requestor_1_pmp_1_cfg_w),
.io_requestor_1_pmp_1_cfg_r (_ptw_io_requestor_1_pmp_1_cfg_r),
.io_requestor_1_pmp_1_addr (_ptw_io_requestor_1_pmp_1_addr),
.io_requestor_1_pmp_1_mask (_ptw_io_requestor_1_pmp_1_mask),
.io_requestor_1_pmp_2_cfg_l (_ptw_io_requestor_1_pmp_2_cfg_l),
.io_requestor_1_pmp_2_cfg_a (_ptw_io_requestor_1_pmp_2_cfg_a),
.io_requestor_1_pmp_2_cfg_x (_ptw_io_requestor_1_pmp_2_cfg_x),
.io_requestor_1_pmp_2_cfg_w (_ptw_io_requestor_1_pmp_2_cfg_w),
.io_requestor_1_pmp_2_cfg_r (_ptw_io_requestor_1_pmp_2_cfg_r),
.io_requestor_1_pmp_2_addr (_ptw_io_requestor_1_pmp_2_addr),
.io_requestor_1_pmp_2_mask (_ptw_io_requestor_1_pmp_2_mask),
.io_requestor_1_pmp_3_cfg_l (_ptw_io_requestor_1_pmp_3_cfg_l),
.io_requestor_1_pmp_3_cfg_a (_ptw_io_requestor_1_pmp_3_cfg_a),
.io_requestor_1_pmp_3_cfg_x (_ptw_io_requestor_1_pmp_3_cfg_x),
.io_requestor_1_pmp_3_cfg_w (_ptw_io_requestor_1_pmp_3_cfg_w),
.io_requestor_1_pmp_3_cfg_r (_ptw_io_requestor_1_pmp_3_cfg_r),
.io_requestor_1_pmp_3_addr (_ptw_io_requestor_1_pmp_3_addr),
.io_requestor_1_pmp_3_mask (_ptw_io_requestor_1_pmp_3_mask),
.io_requestor_1_pmp_4_cfg_l (_ptw_io_requestor_1_pmp_4_cfg_l),
.io_requestor_1_pmp_4_cfg_a (_ptw_io_requestor_1_pmp_4_cfg_a),
.io_requestor_1_pmp_4_cfg_x (_ptw_io_requestor_1_pmp_4_cfg_x),
.io_requestor_1_pmp_4_cfg_w (_ptw_io_requestor_1_pmp_4_cfg_w),
.io_requestor_1_pmp_4_cfg_r (_ptw_io_requestor_1_pmp_4_cfg_r),
.io_requestor_1_pmp_4_addr (_ptw_io_requestor_1_pmp_4_addr),
.io_requestor_1_pmp_4_mask (_ptw_io_requestor_1_pmp_4_mask),
.io_requestor_1_pmp_5_cfg_l (_ptw_io_requestor_1_pmp_5_cfg_l),
.io_requestor_1_pmp_5_cfg_a (_ptw_io_requestor_1_pmp_5_cfg_a),
.io_requestor_1_pmp_5_cfg_x (_ptw_io_requestor_1_pmp_5_cfg_x),
.io_requestor_1_pmp_5_cfg_w (_ptw_io_requestor_1_pmp_5_cfg_w),
.io_requestor_1_pmp_5_cfg_r (_ptw_io_requestor_1_pmp_5_cfg_r),
.io_requestor_1_pmp_5_addr (_ptw_io_requestor_1_pmp_5_addr),
.io_requestor_1_pmp_5_mask (_ptw_io_requestor_1_pmp_5_mask),
.io_requestor_1_pmp_6_cfg_l (_ptw_io_requestor_1_pmp_6_cfg_l),
.io_requestor_1_pmp_6_cfg_a (_ptw_io_requestor_1_pmp_6_cfg_a),
.io_requestor_1_pmp_6_cfg_x (_ptw_io_requestor_1_pmp_6_cfg_x),
.io_requestor_1_pmp_6_cfg_w (_ptw_io_requestor_1_pmp_6_cfg_w),
.io_requestor_1_pmp_6_cfg_r (_ptw_io_requestor_1_pmp_6_cfg_r),
.io_requestor_1_pmp_6_addr (_ptw_io_requestor_1_pmp_6_addr),
.io_requestor_1_pmp_6_mask (_ptw_io_requestor_1_pmp_6_mask),
.io_requestor_1_pmp_7_cfg_l (_ptw_io_requestor_1_pmp_7_cfg_l),
.io_requestor_1_pmp_7_cfg_a (_ptw_io_requestor_1_pmp_7_cfg_a),
.io_requestor_1_pmp_7_cfg_x (_ptw_io_requestor_1_pmp_7_cfg_x),
.io_requestor_1_pmp_7_cfg_w (_ptw_io_requestor_1_pmp_7_cfg_w),
.io_requestor_1_pmp_7_cfg_r (_ptw_io_requestor_1_pmp_7_cfg_r),
.io_requestor_1_pmp_7_addr (_ptw_io_requestor_1_pmp_7_addr),
.io_requestor_1_pmp_7_mask (_ptw_io_requestor_1_pmp_7_mask),
.io_requestor_2_req_ready (_ptw_io_requestor_2_req_ready),
.io_requestor_2_resp_valid (_ptw_io_requestor_2_resp_valid),
.io_requestor_2_resp_bits_ae_ptw (_ptw_io_requestor_2_resp_bits_ae_ptw),
.io_requestor_2_resp_bits_ae_final (_ptw_io_requestor_2_resp_bits_ae_final),
.io_requestor_2_resp_bits_pf (_ptw_io_requestor_2_resp_bits_pf),
.io_requestor_2_resp_bits_gf (_ptw_io_requestor_2_resp_bits_gf),
.io_requestor_2_resp_bits_hr (_ptw_io_requestor_2_resp_bits_hr),
.io_requestor_2_resp_bits_hw (_ptw_io_requestor_2_resp_bits_hw),
.io_requestor_2_resp_bits_hx (_ptw_io_requestor_2_resp_bits_hx),
.io_requestor_2_resp_bits_pte_reserved_for_future (_ptw_io_requestor_2_resp_bits_pte_reserved_for_future),
.io_requestor_2_resp_bits_pte_ppn (_ptw_io_requestor_2_resp_bits_pte_ppn),
.io_requestor_2_resp_bits_pte_reserved_for_software (_ptw_io_requestor_2_resp_bits_pte_reserved_for_software),
.io_requestor_2_resp_bits_pte_d (_ptw_io_requestor_2_resp_bits_pte_d),
.io_requestor_2_resp_bits_pte_a (_ptw_io_requestor_2_resp_bits_pte_a),
.io_requestor_2_resp_bits_pte_g (_ptw_io_requestor_2_resp_bits_pte_g),
.io_requestor_2_resp_bits_pte_u (_ptw_io_requestor_2_resp_bits_pte_u),
.io_requestor_2_resp_bits_pte_x (_ptw_io_requestor_2_resp_bits_pte_x),
.io_requestor_2_resp_bits_pte_w (_ptw_io_requestor_2_resp_bits_pte_w),
.io_requestor_2_resp_bits_pte_r (_ptw_io_requestor_2_resp_bits_pte_r),
.io_requestor_2_resp_bits_pte_v (_ptw_io_requestor_2_resp_bits_pte_v),
.io_requestor_2_resp_bits_level (_ptw_io_requestor_2_resp_bits_level),
.io_requestor_2_resp_bits_homogeneous (_ptw_io_requestor_2_resp_bits_homogeneous),
.io_requestor_2_resp_bits_gpa_valid (_ptw_io_requestor_2_resp_bits_gpa_valid),
.io_requestor_2_resp_bits_gpa_bits (_ptw_io_requestor_2_resp_bits_gpa_bits),
.io_requestor_2_resp_bits_gpa_is_pte (_ptw_io_requestor_2_resp_bits_gpa_is_pte),
.io_requestor_2_ptbr_mode (_ptw_io_requestor_2_ptbr_mode),
.io_requestor_2_ptbr_ppn (_ptw_io_requestor_2_ptbr_ppn),
.io_requestor_2_status_debug (_ptw_io_requestor_2_status_debug),
.io_requestor_2_status_cease (_ptw_io_requestor_2_status_cease),
.io_requestor_2_status_wfi (_ptw_io_requestor_2_status_wfi),
.io_requestor_2_status_dprv (_ptw_io_requestor_2_status_dprv),
.io_requestor_2_status_dv (_ptw_io_requestor_2_status_dv),
.io_requestor_2_status_prv (_ptw_io_requestor_2_status_prv),
.io_requestor_2_status_v (_ptw_io_requestor_2_status_v),
.io_requestor_2_status_sd (_ptw_io_requestor_2_status_sd),
.io_requestor_2_status_mpv (_ptw_io_requestor_2_status_mpv),
.io_requestor_2_status_gva (_ptw_io_requestor_2_status_gva),
.io_requestor_2_status_tsr (_ptw_io_requestor_2_status_tsr),
.io_requestor_2_status_tw (_ptw_io_requestor_2_status_tw),
.io_requestor_2_status_tvm (_ptw_io_requestor_2_status_tvm),
.io_requestor_2_status_mxr (_ptw_io_requestor_2_status_mxr),
.io_requestor_2_status_sum (_ptw_io_requestor_2_status_sum),
.io_requestor_2_status_mprv (_ptw_io_requestor_2_status_mprv),
.io_requestor_2_status_fs (_ptw_io_requestor_2_status_fs),
.io_requestor_2_status_mpp (_ptw_io_requestor_2_status_mpp),
.io_requestor_2_status_spp (_ptw_io_requestor_2_status_spp),
.io_requestor_2_status_mpie (_ptw_io_requestor_2_status_mpie),
.io_requestor_2_status_spie (_ptw_io_requestor_2_status_spie),
.io_requestor_2_status_mie (_ptw_io_requestor_2_status_mie),
.io_requestor_2_status_sie (_ptw_io_requestor_2_status_sie),
.io_requestor_2_pmp_0_cfg_l (_ptw_io_requestor_2_pmp_0_cfg_l),
.io_requestor_2_pmp_0_cfg_a (_ptw_io_requestor_2_pmp_0_cfg_a),
.io_requestor_2_pmp_0_cfg_x (_ptw_io_requestor_2_pmp_0_cfg_x),
.io_requestor_2_pmp_0_cfg_w (_ptw_io_requestor_2_pmp_0_cfg_w),
.io_requestor_2_pmp_0_cfg_r (_ptw_io_requestor_2_pmp_0_cfg_r),
.io_requestor_2_pmp_0_addr (_ptw_io_requestor_2_pmp_0_addr),
.io_requestor_2_pmp_0_mask (_ptw_io_requestor_2_pmp_0_mask),
.io_requestor_2_pmp_1_cfg_l (_ptw_io_requestor_2_pmp_1_cfg_l),
.io_requestor_2_pmp_1_cfg_a (_ptw_io_requestor_2_pmp_1_cfg_a),
.io_requestor_2_pmp_1_cfg_x (_ptw_io_requestor_2_pmp_1_cfg_x),
.io_requestor_2_pmp_1_cfg_w (_ptw_io_requestor_2_pmp_1_cfg_w),
.io_requestor_2_pmp_1_cfg_r (_ptw_io_requestor_2_pmp_1_cfg_r),
.io_requestor_2_pmp_1_addr (_ptw_io_requestor_2_pmp_1_addr),
.io_requestor_2_pmp_1_mask (_ptw_io_requestor_2_pmp_1_mask),
.io_requestor_2_pmp_2_cfg_l (_ptw_io_requestor_2_pmp_2_cfg_l),
.io_requestor_2_pmp_2_cfg_a (_ptw_io_requestor_2_pmp_2_cfg_a),
.io_requestor_2_pmp_2_cfg_x (_ptw_io_requestor_2_pmp_2_cfg_x),
.io_requestor_2_pmp_2_cfg_w (_ptw_io_requestor_2_pmp_2_cfg_w),
.io_requestor_2_pmp_2_cfg_r (_ptw_io_requestor_2_pmp_2_cfg_r),
.io_requestor_2_pmp_2_addr (_ptw_io_requestor_2_pmp_2_addr),
.io_requestor_2_pmp_2_mask (_ptw_io_requestor_2_pmp_2_mask),
.io_requestor_2_pmp_3_cfg_l (_ptw_io_requestor_2_pmp_3_cfg_l),
.io_requestor_2_pmp_3_cfg_a (_ptw_io_requestor_2_pmp_3_cfg_a),
.io_requestor_2_pmp_3_cfg_x (_ptw_io_requestor_2_pmp_3_cfg_x),
.io_requestor_2_pmp_3_cfg_w (_ptw_io_requestor_2_pmp_3_cfg_w),
.io_requestor_2_pmp_3_cfg_r (_ptw_io_requestor_2_pmp_3_cfg_r),
.io_requestor_2_pmp_3_addr (_ptw_io_requestor_2_pmp_3_addr),
.io_requestor_2_pmp_3_mask (_ptw_io_requestor_2_pmp_3_mask),
.io_requestor_2_pmp_4_cfg_l (_ptw_io_requestor_2_pmp_4_cfg_l),
.io_requestor_2_pmp_4_cfg_a (_ptw_io_requestor_2_pmp_4_cfg_a),
.io_requestor_2_pmp_4_cfg_x (_ptw_io_requestor_2_pmp_4_cfg_x),
.io_requestor_2_pmp_4_cfg_w (_ptw_io_requestor_2_pmp_4_cfg_w),
.io_requestor_2_pmp_4_cfg_r (_ptw_io_requestor_2_pmp_4_cfg_r),
.io_requestor_2_pmp_4_addr (_ptw_io_requestor_2_pmp_4_addr),
.io_requestor_2_pmp_4_mask (_ptw_io_requestor_2_pmp_4_mask),
.io_requestor_2_pmp_5_cfg_l (_ptw_io_requestor_2_pmp_5_cfg_l),
.io_requestor_2_pmp_5_cfg_a (_ptw_io_requestor_2_pmp_5_cfg_a),
.io_requestor_2_pmp_5_cfg_x (_ptw_io_requestor_2_pmp_5_cfg_x),
.io_requestor_2_pmp_5_cfg_w (_ptw_io_requestor_2_pmp_5_cfg_w),
.io_requestor_2_pmp_5_cfg_r (_ptw_io_requestor_2_pmp_5_cfg_r),
.io_requestor_2_pmp_5_addr (_ptw_io_requestor_2_pmp_5_addr),
.io_requestor_2_pmp_5_mask (_ptw_io_requestor_2_pmp_5_mask),
.io_requestor_2_pmp_6_cfg_l (_ptw_io_requestor_2_pmp_6_cfg_l),
.io_requestor_2_pmp_6_cfg_a (_ptw_io_requestor_2_pmp_6_cfg_a),
.io_requestor_2_pmp_6_cfg_x (_ptw_io_requestor_2_pmp_6_cfg_x),
.io_requestor_2_pmp_6_cfg_w (_ptw_io_requestor_2_pmp_6_cfg_w),
.io_requestor_2_pmp_6_cfg_r (_ptw_io_requestor_2_pmp_6_cfg_r),
.io_requestor_2_pmp_6_addr (_ptw_io_requestor_2_pmp_6_addr),
.io_requestor_2_pmp_6_mask (_ptw_io_requestor_2_pmp_6_mask),
.io_requestor_2_pmp_7_cfg_l (_ptw_io_requestor_2_pmp_7_cfg_l),
.io_requestor_2_pmp_7_cfg_a (_ptw_io_requestor_2_pmp_7_cfg_a),
.io_requestor_2_pmp_7_cfg_x (_ptw_io_requestor_2_pmp_7_cfg_x),
.io_requestor_2_pmp_7_cfg_w (_ptw_io_requestor_2_pmp_7_cfg_w),
.io_requestor_2_pmp_7_cfg_r (_ptw_io_requestor_2_pmp_7_cfg_r),
.io_requestor_2_pmp_7_addr (_ptw_io_requestor_2_pmp_7_addr),
.io_requestor_2_pmp_7_mask (_ptw_io_requestor_2_pmp_7_mask),
.io_mem_req_ready (_hellaCacheArb_io_requestor_0_req_ready), // @[tile.scala:243:29]
.io_mem_req_valid (_ptw_io_mem_req_valid),
.io_mem_req_bits_addr (_ptw_io_mem_req_bits_addr),
.io_mem_req_bits_dv (_ptw_io_mem_req_bits_dv),
.io_mem_s1_kill (_ptw_io_mem_s1_kill),
.io_mem_s2_nack (_hellaCacheArb_io_requestor_0_s2_nack), // @[tile.scala:243:29]
.io_mem_resp_valid (_hellaCacheArb_io_requestor_0_resp_valid), // @[tile.scala:243:29]
.io_mem_resp_bits_addr (_hellaCacheArb_io_requestor_0_resp_bits_addr), // @[tile.scala:243:29]
.io_mem_resp_bits_data (_hellaCacheArb_io_requestor_0_resp_bits_data), // @[tile.scala:243:29]
.io_mem_s2_xcpt_ma_ld (_hellaCacheArb_io_requestor_0_s2_xcpt_ma_ld), // @[tile.scala:243:29]
.io_mem_s2_xcpt_ma_st (_hellaCacheArb_io_requestor_0_s2_xcpt_ma_st), // @[tile.scala:243:29]
.io_mem_s2_xcpt_pf_ld (_hellaCacheArb_io_requestor_0_s2_xcpt_pf_ld), // @[tile.scala:243:29]
.io_mem_s2_xcpt_pf_st (_hellaCacheArb_io_requestor_0_s2_xcpt_pf_st), // @[tile.scala:243:29]
.io_mem_s2_xcpt_gf_ld (_hellaCacheArb_io_requestor_0_s2_xcpt_gf_ld), // @[tile.scala:243:29]
.io_mem_s2_xcpt_gf_st (_hellaCacheArb_io_requestor_0_s2_xcpt_gf_st), // @[tile.scala:243:29]
.io_mem_s2_xcpt_ae_ld (_hellaCacheArb_io_requestor_0_s2_xcpt_ae_ld), // @[tile.scala:243:29]
.io_mem_s2_xcpt_ae_st (_hellaCacheArb_io_requestor_0_s2_xcpt_ae_st), // @[tile.scala:243:29]
.io_mem_store_pending (_hellaCacheArb_io_requestor_0_store_pending), // @[tile.scala:243:29]
.io_dpath_ptbr_mode (_core_io_ptw_ptbr_mode), // @[tile.scala:159:20]
.io_dpath_ptbr_ppn (_core_io_ptw_ptbr_ppn), // @[tile.scala:159:20]
.io_dpath_sfence_valid (_core_io_ptw_sfence_valid), // @[tile.scala:159:20]
.io_dpath_sfence_bits_rs1 (_core_io_ptw_sfence_bits_rs1), // @[tile.scala:159:20]
.io_dpath_sfence_bits_rs2 (_core_io_ptw_sfence_bits_rs2), // @[tile.scala:159:20]
.io_dpath_sfence_bits_addr (_core_io_ptw_sfence_bits_addr), // @[tile.scala:159:20]
.io_dpath_sfence_bits_asid (_core_io_ptw_sfence_bits_asid), // @[tile.scala:159:20]
.io_dpath_status_debug (_core_io_ptw_status_debug), // @[tile.scala:159:20]
.io_dpath_status_cease (_core_io_ptw_status_cease), // @[tile.scala:159:20]
.io_dpath_status_wfi (_core_io_ptw_status_wfi), // @[tile.scala:159:20]
.io_dpath_status_dprv (_core_io_ptw_status_dprv), // @[tile.scala:159:20]
.io_dpath_status_dv (_core_io_ptw_status_dv), // @[tile.scala:159:20]
.io_dpath_status_prv (_core_io_ptw_status_prv), // @[tile.scala:159:20]
.io_dpath_status_v (_core_io_ptw_status_v), // @[tile.scala:159:20]
.io_dpath_status_sd (_core_io_ptw_status_sd), // @[tile.scala:159:20]
.io_dpath_status_mpv (_core_io_ptw_status_mpv), // @[tile.scala:159:20]
.io_dpath_status_gva (_core_io_ptw_status_gva), // @[tile.scala:159:20]
.io_dpath_status_tsr (_core_io_ptw_status_tsr), // @[tile.scala:159:20]
.io_dpath_status_tw (_core_io_ptw_status_tw), // @[tile.scala:159:20]
.io_dpath_status_tvm (_core_io_ptw_status_tvm), // @[tile.scala:159:20]
.io_dpath_status_mxr (_core_io_ptw_status_mxr), // @[tile.scala:159:20]
.io_dpath_status_sum (_core_io_ptw_status_sum), // @[tile.scala:159:20]
.io_dpath_status_mprv (_core_io_ptw_status_mprv), // @[tile.scala:159:20]
.io_dpath_status_fs (_core_io_ptw_status_fs), // @[tile.scala:159:20]
.io_dpath_status_mpp (_core_io_ptw_status_mpp), // @[tile.scala:159:20]
.io_dpath_status_spp (_core_io_ptw_status_spp), // @[tile.scala:159:20]
.io_dpath_status_mpie (_core_io_ptw_status_mpie), // @[tile.scala:159:20]
.io_dpath_status_spie (_core_io_ptw_status_spie), // @[tile.scala:159:20]
.io_dpath_status_mie (_core_io_ptw_status_mie), // @[tile.scala:159:20]
.io_dpath_status_sie (_core_io_ptw_status_sie), // @[tile.scala:159:20]
.io_dpath_pmp_0_cfg_l (_core_io_ptw_pmp_0_cfg_l), // @[tile.scala:159:20]
.io_dpath_pmp_0_cfg_a (_core_io_ptw_pmp_0_cfg_a), // @[tile.scala:159:20]
.io_dpath_pmp_0_cfg_x (_core_io_ptw_pmp_0_cfg_x), // @[tile.scala:159:20]
.io_dpath_pmp_0_cfg_w (_core_io_ptw_pmp_0_cfg_w), // @[tile.scala:159:20]
.io_dpath_pmp_0_cfg_r (_core_io_ptw_pmp_0_cfg_r), // @[tile.scala:159:20]
.io_dpath_pmp_0_addr (_core_io_ptw_pmp_0_addr), // @[tile.scala:159:20]
.io_dpath_pmp_0_mask (_core_io_ptw_pmp_0_mask), // @[tile.scala:159:20]
.io_dpath_pmp_1_cfg_l (_core_io_ptw_pmp_1_cfg_l), // @[tile.scala:159:20]
.io_dpath_pmp_1_cfg_a (_core_io_ptw_pmp_1_cfg_a), // @[tile.scala:159:20]
.io_dpath_pmp_1_cfg_x (_core_io_ptw_pmp_1_cfg_x), // @[tile.scala:159:20]
.io_dpath_pmp_1_cfg_w (_core_io_ptw_pmp_1_cfg_w), // @[tile.scala:159:20]
.io_dpath_pmp_1_cfg_r (_core_io_ptw_pmp_1_cfg_r), // @[tile.scala:159:20]
.io_dpath_pmp_1_addr (_core_io_ptw_pmp_1_addr), // @[tile.scala:159:20]
.io_dpath_pmp_1_mask (_core_io_ptw_pmp_1_mask), // @[tile.scala:159:20]
.io_dpath_pmp_2_cfg_l (_core_io_ptw_pmp_2_cfg_l), // @[tile.scala:159:20]
.io_dpath_pmp_2_cfg_a (_core_io_ptw_pmp_2_cfg_a), // @[tile.scala:159:20]
.io_dpath_pmp_2_cfg_x (_core_io_ptw_pmp_2_cfg_x), // @[tile.scala:159:20]
.io_dpath_pmp_2_cfg_w (_core_io_ptw_pmp_2_cfg_w), // @[tile.scala:159:20]
.io_dpath_pmp_2_cfg_r (_core_io_ptw_pmp_2_cfg_r), // @[tile.scala:159:20]
.io_dpath_pmp_2_addr (_core_io_ptw_pmp_2_addr), // @[tile.scala:159:20]
.io_dpath_pmp_2_mask (_core_io_ptw_pmp_2_mask), // @[tile.scala:159:20]
.io_dpath_pmp_3_cfg_l (_core_io_ptw_pmp_3_cfg_l), // @[tile.scala:159:20]
.io_dpath_pmp_3_cfg_a (_core_io_ptw_pmp_3_cfg_a), // @[tile.scala:159:20]
.io_dpath_pmp_3_cfg_x (_core_io_ptw_pmp_3_cfg_x), // @[tile.scala:159:20]
.io_dpath_pmp_3_cfg_w (_core_io_ptw_pmp_3_cfg_w), // @[tile.scala:159:20]
.io_dpath_pmp_3_cfg_r (_core_io_ptw_pmp_3_cfg_r), // @[tile.scala:159:20]
.io_dpath_pmp_3_addr (_core_io_ptw_pmp_3_addr), // @[tile.scala:159:20]
.io_dpath_pmp_3_mask (_core_io_ptw_pmp_3_mask), // @[tile.scala:159:20]
.io_dpath_pmp_4_cfg_l (_core_io_ptw_pmp_4_cfg_l), // @[tile.scala:159:20]
.io_dpath_pmp_4_cfg_a (_core_io_ptw_pmp_4_cfg_a), // @[tile.scala:159:20]
.io_dpath_pmp_4_cfg_x (_core_io_ptw_pmp_4_cfg_x), // @[tile.scala:159:20]
.io_dpath_pmp_4_cfg_w (_core_io_ptw_pmp_4_cfg_w), // @[tile.scala:159:20]
.io_dpath_pmp_4_cfg_r (_core_io_ptw_pmp_4_cfg_r), // @[tile.scala:159:20]
.io_dpath_pmp_4_addr (_core_io_ptw_pmp_4_addr), // @[tile.scala:159:20]
.io_dpath_pmp_4_mask (_core_io_ptw_pmp_4_mask), // @[tile.scala:159:20]
.io_dpath_pmp_5_cfg_l (_core_io_ptw_pmp_5_cfg_l), // @[tile.scala:159:20]
.io_dpath_pmp_5_cfg_a (_core_io_ptw_pmp_5_cfg_a), // @[tile.scala:159:20]
.io_dpath_pmp_5_cfg_x (_core_io_ptw_pmp_5_cfg_x), // @[tile.scala:159:20]
.io_dpath_pmp_5_cfg_w (_core_io_ptw_pmp_5_cfg_w), // @[tile.scala:159:20]
.io_dpath_pmp_5_cfg_r (_core_io_ptw_pmp_5_cfg_r), // @[tile.scala:159:20]
.io_dpath_pmp_5_addr (_core_io_ptw_pmp_5_addr), // @[tile.scala:159:20]
.io_dpath_pmp_5_mask (_core_io_ptw_pmp_5_mask), // @[tile.scala:159:20]
.io_dpath_pmp_6_cfg_l (_core_io_ptw_pmp_6_cfg_l), // @[tile.scala:159:20]
.io_dpath_pmp_6_cfg_a (_core_io_ptw_pmp_6_cfg_a), // @[tile.scala:159:20]
.io_dpath_pmp_6_cfg_x (_core_io_ptw_pmp_6_cfg_x), // @[tile.scala:159:20]
.io_dpath_pmp_6_cfg_w (_core_io_ptw_pmp_6_cfg_w), // @[tile.scala:159:20]
.io_dpath_pmp_6_cfg_r (_core_io_ptw_pmp_6_cfg_r), // @[tile.scala:159:20]
.io_dpath_pmp_6_addr (_core_io_ptw_pmp_6_addr), // @[tile.scala:159:20]
.io_dpath_pmp_6_mask (_core_io_ptw_pmp_6_mask), // @[tile.scala:159:20]
.io_dpath_pmp_7_cfg_l (_core_io_ptw_pmp_7_cfg_l), // @[tile.scala:159:20]
.io_dpath_pmp_7_cfg_a (_core_io_ptw_pmp_7_cfg_a), // @[tile.scala:159:20]
.io_dpath_pmp_7_cfg_x (_core_io_ptw_pmp_7_cfg_x), // @[tile.scala:159:20]
.io_dpath_pmp_7_cfg_w (_core_io_ptw_pmp_7_cfg_w), // @[tile.scala:159:20]
.io_dpath_pmp_7_cfg_r (_core_io_ptw_pmp_7_cfg_r), // @[tile.scala:159:20]
.io_dpath_pmp_7_addr (_core_io_ptw_pmp_7_addr), // @[tile.scala:159:20]
.io_dpath_pmp_7_mask (_core_io_ptw_pmp_7_mask), // @[tile.scala:159:20]
.io_dpath_perf_l2miss (_ptw_io_dpath_perf_l2miss),
.io_dpath_perf_l2hit (_ptw_io_dpath_perf_l2hit),
.io_dpath_perf_pte_miss (_ptw_io_dpath_perf_pte_miss),
.io_dpath_perf_pte_hit (_ptw_io_dpath_perf_pte_hit),
.io_dpath_clock_enabled (_ptw_io_dpath_clock_enabled)
); // @[tile.scala:237:20]
HellaCacheArbiter hellaCacheArb ( // @[tile.scala:243:29]
.clock (clock),
.reset (reset),
.io_requestor_0_req_ready (_hellaCacheArb_io_requestor_0_req_ready),
.io_requestor_0_req_valid (_ptw_io_mem_req_valid), // @[tile.scala:237:20]
.io_requestor_0_req_bits_addr (_ptw_io_mem_req_bits_addr), // @[tile.scala:237:20]
.io_requestor_0_req_bits_dv (_ptw_io_mem_req_bits_dv), // @[tile.scala:237:20]
.io_requestor_0_s1_kill (_ptw_io_mem_s1_kill), // @[tile.scala:237:20]
.io_requestor_0_s2_nack (_hellaCacheArb_io_requestor_0_s2_nack),
.io_requestor_0_resp_valid (_hellaCacheArb_io_requestor_0_resp_valid),
.io_requestor_0_resp_bits_addr (_hellaCacheArb_io_requestor_0_resp_bits_addr),
.io_requestor_0_resp_bits_data (_hellaCacheArb_io_requestor_0_resp_bits_data),
.io_requestor_0_s2_xcpt_ma_ld (_hellaCacheArb_io_requestor_0_s2_xcpt_ma_ld),
.io_requestor_0_s2_xcpt_ma_st (_hellaCacheArb_io_requestor_0_s2_xcpt_ma_st),
.io_requestor_0_s2_xcpt_pf_ld (_hellaCacheArb_io_requestor_0_s2_xcpt_pf_ld),
.io_requestor_0_s2_xcpt_pf_st (_hellaCacheArb_io_requestor_0_s2_xcpt_pf_st),
.io_requestor_0_s2_xcpt_gf_ld (_hellaCacheArb_io_requestor_0_s2_xcpt_gf_ld),
.io_requestor_0_s2_xcpt_gf_st (_hellaCacheArb_io_requestor_0_s2_xcpt_gf_st),
.io_requestor_0_s2_xcpt_ae_ld (_hellaCacheArb_io_requestor_0_s2_xcpt_ae_ld),
.io_requestor_0_s2_xcpt_ae_st (_hellaCacheArb_io_requestor_0_s2_xcpt_ae_st),
.io_requestor_0_store_pending (_hellaCacheArb_io_requestor_0_store_pending),
.io_mem_req_ready (_lsu_io_hellacache_req_ready), // @[tile.scala:160:20]
.io_mem_req_valid (_hellaCacheArb_io_mem_req_valid),
.io_mem_req_bits_addr (_hellaCacheArb_io_mem_req_bits_addr),
.io_mem_req_bits_dv (_hellaCacheArb_io_mem_req_bits_dv),
.io_mem_s1_kill (_hellaCacheArb_io_mem_s1_kill),
.io_mem_s2_nack (_lsu_io_hellacache_s2_nack), // @[tile.scala:160:20]
.io_mem_resp_valid (_lsu_io_hellacache_resp_valid), // @[tile.scala:160:20]
.io_mem_resp_bits_addr (_lsu_io_hellacache_resp_bits_addr), // @[tile.scala:160:20]
.io_mem_resp_bits_data (_lsu_io_hellacache_resp_bits_data), // @[tile.scala:160:20]
.io_mem_s2_xcpt_ma_ld (_lsu_io_hellacache_s2_xcpt_ma_ld), // @[tile.scala:160:20]
.io_mem_s2_xcpt_ma_st (_lsu_io_hellacache_s2_xcpt_ma_st), // @[tile.scala:160:20]
.io_mem_s2_xcpt_pf_ld (_lsu_io_hellacache_s2_xcpt_pf_ld), // @[tile.scala:160:20]
.io_mem_s2_xcpt_pf_st (_lsu_io_hellacache_s2_xcpt_pf_st), // @[tile.scala:160:20]
.io_mem_s2_xcpt_gf_ld (_lsu_io_hellacache_s2_xcpt_gf_ld), // @[tile.scala:160:20]
.io_mem_s2_xcpt_gf_st (_lsu_io_hellacache_s2_xcpt_gf_st), // @[tile.scala:160:20]
.io_mem_s2_xcpt_ae_ld (_lsu_io_hellacache_s2_xcpt_ae_ld), // @[tile.scala:160:20]
.io_mem_s2_xcpt_ae_st (_lsu_io_hellacache_s2_xcpt_ae_st), // @[tile.scala:160:20]
.io_mem_store_pending (_lsu_io_hellacache_store_pending) // @[tile.scala:160:20]
); // @[tile.scala:243:29]
assign auto_buffer_out_a_valid = auto_buffer_out_a_valid_0; // @[tile.scala:155:7]
assign auto_buffer_out_a_bits_opcode = auto_buffer_out_a_bits_opcode_0; // @[tile.scala:155:7]
assign auto_buffer_out_a_bits_param = auto_buffer_out_a_bits_param_0; // @[tile.scala:155:7]
assign auto_buffer_out_a_bits_size = auto_buffer_out_a_bits_size_0; // @[tile.scala:155:7]
assign auto_buffer_out_a_bits_source = auto_buffer_out_a_bits_source_0; // @[tile.scala:155:7]
assign auto_buffer_out_a_bits_address = auto_buffer_out_a_bits_address_0; // @[tile.scala:155:7]
assign auto_buffer_out_a_bits_mask = auto_buffer_out_a_bits_mask_0; // @[tile.scala:155:7]
assign auto_buffer_out_a_bits_data = auto_buffer_out_a_bits_data_0; // @[tile.scala:155:7]
assign auto_buffer_out_b_ready = auto_buffer_out_b_ready_0; // @[tile.scala:155:7]
assign auto_buffer_out_c_valid = auto_buffer_out_c_valid_0; // @[tile.scala:155:7]
assign auto_buffer_out_c_bits_opcode = auto_buffer_out_c_bits_opcode_0; // @[tile.scala:155:7]
assign auto_buffer_out_c_bits_param = auto_buffer_out_c_bits_param_0; // @[tile.scala:155:7]
assign auto_buffer_out_c_bits_size = auto_buffer_out_c_bits_size_0; // @[tile.scala:155:7]
assign auto_buffer_out_c_bits_source = auto_buffer_out_c_bits_source_0; // @[tile.scala:155:7]
assign auto_buffer_out_c_bits_address = auto_buffer_out_c_bits_address_0; // @[tile.scala:155:7]
assign auto_buffer_out_c_bits_data = auto_buffer_out_c_bits_data_0; // @[tile.scala:155:7]
assign auto_buffer_out_d_ready = auto_buffer_out_d_ready_0; // @[tile.scala:155:7]
assign auto_buffer_out_e_valid = auto_buffer_out_e_valid_0; // @[tile.scala:155:7]
assign auto_buffer_out_e_bits_sink = auto_buffer_out_e_bits_sink_0; // @[tile.scala:155:7]
assign auto_trace_source_out_time = auto_trace_source_out_time_0; // @[tile.scala:155:7]
assign auto_trace_source_out_custom_rob_empty = auto_trace_source_out_custom_rob_empty_0; // @[tile.scala:155:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module SerialRAM :
input clock : Clock
input reset : Reset
output auto : { }
output io : { ser : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { phit : UInt<32>}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { phit : UInt<32>}}}, tsi : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<32>}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<32>}}, tsi2tl_state : UInt}
inst serdesser of TLSerdesser_SerialRAM
connect serdesser.clock, clock
connect serdesser.reset, reset
inst tsi2tl of TSIToTileLink
connect tsi2tl.clock, clock
connect tsi2tl.reset, reset
inst buffer of TLBuffer_a32d64s1k3z4u
connect buffer.clock, clock
connect buffer.reset, reset
connect buffer.auto.in, tsi2tl.auto.out
connect serdesser.auto.manager_in, buffer.auto.out
inst phy of DecoupledSerialPhy_1
connect phy.io.outer_clock, clock
connect phy.io.outer_reset, reset
connect phy.io.inner_clock, clock
connect phy.io.inner_reset, reset
connect io.ser.out.bits, phy.io.outer_ser.out.bits
connect io.ser.out.valid, phy.io.outer_ser.out.valid
connect phy.io.outer_ser.out.ready, io.ser.out.ready
connect phy.io.outer_ser.in, io.ser.in
connect phy.io.inner_ser[0], serdesser.io.ser[0]
connect phy.io.inner_ser[1], serdesser.io.ser[1]
connect phy.io.inner_ser[2], serdesser.io.ser[2]
connect phy.io.inner_ser[3], serdesser.io.ser[3]
connect phy.io.inner_ser[4], serdesser.io.ser[4]
connect io.tsi.out.bits, tsi2tl.io.tsi.out.bits
connect io.tsi.out.valid, tsi2tl.io.tsi.out.valid
connect tsi2tl.io.tsi.out.ready, io.tsi.out.ready
connect tsi2tl.io.tsi.in, io.tsi.in
connect io.tsi2tl_state, tsi2tl.io.state
extmodule SimTSI :
input clock : Clock
input reset : UInt<1>
input tsi : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<32>}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<32>}}
output exit : UInt<32>
defname = SimTSI
parameter CHIPID = 0 | module SerialRAM( // @[TSIHarness.scala:122:9]
input clock, // @[TSIHarness.scala:122:9]
input reset, // @[TSIHarness.scala:122:9]
output io_ser_in_ready, // @[TSIHarness.scala:123:16]
input io_ser_in_valid, // @[TSIHarness.scala:123:16]
input [31:0] io_ser_in_bits_phit, // @[TSIHarness.scala:123:16]
input io_ser_out_ready, // @[TSIHarness.scala:123:16]
output io_ser_out_valid, // @[TSIHarness.scala:123:16]
output [31:0] io_ser_out_bits_phit, // @[TSIHarness.scala:123:16]
output io_tsi_in_ready, // @[TSIHarness.scala:123:16]
input io_tsi_in_valid, // @[TSIHarness.scala:123:16]
input [31:0] io_tsi_in_bits, // @[TSIHarness.scala:123:16]
input io_tsi_out_ready, // @[TSIHarness.scala:123:16]
output io_tsi_out_valid, // @[TSIHarness.scala:123:16]
output [31:0] io_tsi_out_bits // @[TSIHarness.scala:123:16]
);
wire _phy_io_inner_ser_0_in_valid; // @[TSIHarness.scala:129:21]
wire [31:0] _phy_io_inner_ser_0_in_bits_flit; // @[TSIHarness.scala:129:21]
wire _phy_io_inner_ser_1_in_valid; // @[TSIHarness.scala:129:21]
wire [31:0] _phy_io_inner_ser_1_in_bits_flit; // @[TSIHarness.scala:129:21]
wire _phy_io_inner_ser_2_in_valid; // @[TSIHarness.scala:129:21]
wire [31:0] _phy_io_inner_ser_2_in_bits_flit; // @[TSIHarness.scala:129:21]
wire _phy_io_inner_ser_2_out_ready; // @[TSIHarness.scala:129:21]
wire _phy_io_inner_ser_3_in_valid; // @[TSIHarness.scala:129:21]
wire [31:0] _phy_io_inner_ser_3_in_bits_flit; // @[TSIHarness.scala:129:21]
wire _phy_io_inner_ser_4_in_valid; // @[TSIHarness.scala:129:21]
wire [31:0] _phy_io_inner_ser_4_in_bits_flit; // @[TSIHarness.scala:129:21]
wire _phy_io_inner_ser_4_out_ready; // @[TSIHarness.scala:129:21]
wire _buffer_auto_in_a_ready; // @[Buffer.scala:75:28]
wire _buffer_auto_in_d_valid; // @[Buffer.scala:75:28]
wire [63:0] _buffer_auto_in_d_bits_data; // @[Buffer.scala:75:28]
wire _buffer_auto_out_a_valid; // @[Buffer.scala:75:28]
wire [2:0] _buffer_auto_out_a_bits_opcode; // @[Buffer.scala:75:28]
wire [2:0] _buffer_auto_out_a_bits_param; // @[Buffer.scala:75:28]
wire [3:0] _buffer_auto_out_a_bits_size; // @[Buffer.scala:75:28]
wire _buffer_auto_out_a_bits_source; // @[Buffer.scala:75:28]
wire [31:0] _buffer_auto_out_a_bits_address; // @[Buffer.scala:75:28]
wire [7:0] _buffer_auto_out_a_bits_mask; // @[Buffer.scala:75:28]
wire [63:0] _buffer_auto_out_a_bits_data; // @[Buffer.scala:75:28]
wire _buffer_auto_out_a_bits_corrupt; // @[Buffer.scala:75:28]
wire _buffer_auto_out_d_ready; // @[Buffer.scala:75:28]
wire _tsi2tl_auto_out_a_valid; // @[TSIHarness.scala:76:28]
wire [2:0] _tsi2tl_auto_out_a_bits_opcode; // @[TSIHarness.scala:76:28]
wire [3:0] _tsi2tl_auto_out_a_bits_size; // @[TSIHarness.scala:76:28]
wire [31:0] _tsi2tl_auto_out_a_bits_address; // @[TSIHarness.scala:76:28]
wire [7:0] _tsi2tl_auto_out_a_bits_mask; // @[TSIHarness.scala:76:28]
wire [63:0] _tsi2tl_auto_out_a_bits_data; // @[TSIHarness.scala:76:28]
wire _tsi2tl_auto_out_d_ready; // @[TSIHarness.scala:76:28]
wire _serdesser_auto_manager_in_a_ready; // @[TSIHarness.scala:66:29]
wire _serdesser_auto_manager_in_d_valid; // @[TSIHarness.scala:66:29]
wire [2:0] _serdesser_auto_manager_in_d_bits_opcode; // @[TSIHarness.scala:66:29]
wire [1:0] _serdesser_auto_manager_in_d_bits_param; // @[TSIHarness.scala:66:29]
wire [3:0] _serdesser_auto_manager_in_d_bits_size; // @[TSIHarness.scala:66:29]
wire _serdesser_auto_manager_in_d_bits_source; // @[TSIHarness.scala:66:29]
wire [2:0] _serdesser_auto_manager_in_d_bits_sink; // @[TSIHarness.scala:66:29]
wire _serdesser_auto_manager_in_d_bits_denied; // @[TSIHarness.scala:66:29]
wire [63:0] _serdesser_auto_manager_in_d_bits_data; // @[TSIHarness.scala:66:29]
wire _serdesser_auto_manager_in_d_bits_corrupt; // @[TSIHarness.scala:66:29]
wire _serdesser_io_ser_0_in_ready; // @[TSIHarness.scala:66:29]
wire [31:0] _serdesser_io_ser_0_out_bits_flit; // @[TSIHarness.scala:66:29]
wire _serdesser_io_ser_1_in_ready; // @[TSIHarness.scala:66:29]
wire _serdesser_io_ser_2_in_ready; // @[TSIHarness.scala:66:29]
wire _serdesser_io_ser_2_out_valid; // @[TSIHarness.scala:66:29]
wire [31:0] _serdesser_io_ser_2_out_bits_flit; // @[TSIHarness.scala:66:29]
wire _serdesser_io_ser_3_in_ready; // @[TSIHarness.scala:66:29]
wire _serdesser_io_ser_4_in_ready; // @[TSIHarness.scala:66:29]
wire _serdesser_io_ser_4_out_valid; // @[TSIHarness.scala:66:29]
wire [31:0] _serdesser_io_ser_4_out_bits_flit; // @[TSIHarness.scala:66:29]
TLSerdesser_SerialRAM serdesser ( // @[TSIHarness.scala:66:29]
.clock (clock),
.reset (reset),
.auto_manager_in_a_ready (_serdesser_auto_manager_in_a_ready),
.auto_manager_in_a_valid (_buffer_auto_out_a_valid), // @[Buffer.scala:75:28]
.auto_manager_in_a_bits_opcode (_buffer_auto_out_a_bits_opcode), // @[Buffer.scala:75:28]
.auto_manager_in_a_bits_param (_buffer_auto_out_a_bits_param), // @[Buffer.scala:75:28]
.auto_manager_in_a_bits_size (_buffer_auto_out_a_bits_size), // @[Buffer.scala:75:28]
.auto_manager_in_a_bits_source (_buffer_auto_out_a_bits_source), // @[Buffer.scala:75:28]
.auto_manager_in_a_bits_address (_buffer_auto_out_a_bits_address), // @[Buffer.scala:75:28]
.auto_manager_in_a_bits_mask (_buffer_auto_out_a_bits_mask), // @[Buffer.scala:75:28]
.auto_manager_in_a_bits_data (_buffer_auto_out_a_bits_data), // @[Buffer.scala:75:28]
.auto_manager_in_a_bits_corrupt (_buffer_auto_out_a_bits_corrupt), // @[Buffer.scala:75:28]
.auto_manager_in_d_ready (_buffer_auto_out_d_ready), // @[Buffer.scala:75:28]
.auto_manager_in_d_valid (_serdesser_auto_manager_in_d_valid),
.auto_manager_in_d_bits_opcode (_serdesser_auto_manager_in_d_bits_opcode),
.auto_manager_in_d_bits_param (_serdesser_auto_manager_in_d_bits_param),
.auto_manager_in_d_bits_size (_serdesser_auto_manager_in_d_bits_size),
.auto_manager_in_d_bits_source (_serdesser_auto_manager_in_d_bits_source),
.auto_manager_in_d_bits_sink (_serdesser_auto_manager_in_d_bits_sink),
.auto_manager_in_d_bits_denied (_serdesser_auto_manager_in_d_bits_denied),
.auto_manager_in_d_bits_data (_serdesser_auto_manager_in_d_bits_data),
.auto_manager_in_d_bits_corrupt (_serdesser_auto_manager_in_d_bits_corrupt),
.io_ser_0_in_ready (_serdesser_io_ser_0_in_ready),
.io_ser_0_in_valid (_phy_io_inner_ser_0_in_valid), // @[TSIHarness.scala:129:21]
.io_ser_0_in_bits_flit (_phy_io_inner_ser_0_in_bits_flit), // @[TSIHarness.scala:129:21]
.io_ser_0_out_bits_flit (_serdesser_io_ser_0_out_bits_flit),
.io_ser_1_in_ready (_serdesser_io_ser_1_in_ready),
.io_ser_1_in_valid (_phy_io_inner_ser_1_in_valid), // @[TSIHarness.scala:129:21]
.io_ser_1_in_bits_flit (_phy_io_inner_ser_1_in_bits_flit), // @[TSIHarness.scala:129:21]
.io_ser_2_in_ready (_serdesser_io_ser_2_in_ready),
.io_ser_2_in_valid (_phy_io_inner_ser_2_in_valid), // @[TSIHarness.scala:129:21]
.io_ser_2_in_bits_flit (_phy_io_inner_ser_2_in_bits_flit), // @[TSIHarness.scala:129:21]
.io_ser_2_out_ready (_phy_io_inner_ser_2_out_ready), // @[TSIHarness.scala:129:21]
.io_ser_2_out_valid (_serdesser_io_ser_2_out_valid),
.io_ser_2_out_bits_flit (_serdesser_io_ser_2_out_bits_flit),
.io_ser_3_in_ready (_serdesser_io_ser_3_in_ready),
.io_ser_3_in_valid (_phy_io_inner_ser_3_in_valid), // @[TSIHarness.scala:129:21]
.io_ser_3_in_bits_flit (_phy_io_inner_ser_3_in_bits_flit), // @[TSIHarness.scala:129:21]
.io_ser_4_in_ready (_serdesser_io_ser_4_in_ready),
.io_ser_4_in_valid (_phy_io_inner_ser_4_in_valid), // @[TSIHarness.scala:129:21]
.io_ser_4_in_bits_flit (_phy_io_inner_ser_4_in_bits_flit), // @[TSIHarness.scala:129:21]
.io_ser_4_out_ready (_phy_io_inner_ser_4_out_ready), // @[TSIHarness.scala:129:21]
.io_ser_4_out_valid (_serdesser_io_ser_4_out_valid),
.io_ser_4_out_bits_flit (_serdesser_io_ser_4_out_bits_flit)
); // @[TSIHarness.scala:66:29]
TSIToTileLink tsi2tl ( // @[TSIHarness.scala:76:28]
.clock (clock),
.reset (reset),
.auto_out_a_ready (_buffer_auto_in_a_ready), // @[Buffer.scala:75:28]
.auto_out_a_valid (_tsi2tl_auto_out_a_valid),
.auto_out_a_bits_opcode (_tsi2tl_auto_out_a_bits_opcode),
.auto_out_a_bits_size (_tsi2tl_auto_out_a_bits_size),
.auto_out_a_bits_address (_tsi2tl_auto_out_a_bits_address),
.auto_out_a_bits_mask (_tsi2tl_auto_out_a_bits_mask),
.auto_out_a_bits_data (_tsi2tl_auto_out_a_bits_data),
.auto_out_d_ready (_tsi2tl_auto_out_d_ready),
.auto_out_d_valid (_buffer_auto_in_d_valid), // @[Buffer.scala:75:28]
.auto_out_d_bits_data (_buffer_auto_in_d_bits_data), // @[Buffer.scala:75:28]
.io_tsi_in_ready (io_tsi_in_ready),
.io_tsi_in_valid (io_tsi_in_valid),
.io_tsi_in_bits (io_tsi_in_bits),
.io_tsi_out_ready (io_tsi_out_ready),
.io_tsi_out_valid (io_tsi_out_valid),
.io_tsi_out_bits (io_tsi_out_bits)
); // @[TSIHarness.scala:76:28]
TLBuffer_a32d64s1k3z4u buffer ( // @[Buffer.scala:75:28]
.clock (clock),
.reset (reset),
.auto_in_a_ready (_buffer_auto_in_a_ready),
.auto_in_a_valid (_tsi2tl_auto_out_a_valid), // @[TSIHarness.scala:76:28]
.auto_in_a_bits_opcode (_tsi2tl_auto_out_a_bits_opcode), // @[TSIHarness.scala:76:28]
.auto_in_a_bits_size (_tsi2tl_auto_out_a_bits_size), // @[TSIHarness.scala:76:28]
.auto_in_a_bits_address (_tsi2tl_auto_out_a_bits_address), // @[TSIHarness.scala:76:28]
.auto_in_a_bits_mask (_tsi2tl_auto_out_a_bits_mask), // @[TSIHarness.scala:76:28]
.auto_in_a_bits_data (_tsi2tl_auto_out_a_bits_data), // @[TSIHarness.scala:76:28]
.auto_in_d_ready (_tsi2tl_auto_out_d_ready), // @[TSIHarness.scala:76:28]
.auto_in_d_valid (_buffer_auto_in_d_valid),
.auto_in_d_bits_data (_buffer_auto_in_d_bits_data),
.auto_out_a_ready (_serdesser_auto_manager_in_a_ready), // @[TSIHarness.scala:66:29]
.auto_out_a_valid (_buffer_auto_out_a_valid),
.auto_out_a_bits_opcode (_buffer_auto_out_a_bits_opcode),
.auto_out_a_bits_param (_buffer_auto_out_a_bits_param),
.auto_out_a_bits_size (_buffer_auto_out_a_bits_size),
.auto_out_a_bits_source (_buffer_auto_out_a_bits_source),
.auto_out_a_bits_address (_buffer_auto_out_a_bits_address),
.auto_out_a_bits_mask (_buffer_auto_out_a_bits_mask),
.auto_out_a_bits_data (_buffer_auto_out_a_bits_data),
.auto_out_a_bits_corrupt (_buffer_auto_out_a_bits_corrupt),
.auto_out_d_ready (_buffer_auto_out_d_ready),
.auto_out_d_valid (_serdesser_auto_manager_in_d_valid), // @[TSIHarness.scala:66:29]
.auto_out_d_bits_opcode (_serdesser_auto_manager_in_d_bits_opcode), // @[TSIHarness.scala:66:29]
.auto_out_d_bits_param (_serdesser_auto_manager_in_d_bits_param), // @[TSIHarness.scala:66:29]
.auto_out_d_bits_size (_serdesser_auto_manager_in_d_bits_size), // @[TSIHarness.scala:66:29]
.auto_out_d_bits_source (_serdesser_auto_manager_in_d_bits_source), // @[TSIHarness.scala:66:29]
.auto_out_d_bits_sink (_serdesser_auto_manager_in_d_bits_sink), // @[TSIHarness.scala:66:29]
.auto_out_d_bits_denied (_serdesser_auto_manager_in_d_bits_denied), // @[TSIHarness.scala:66:29]
.auto_out_d_bits_data (_serdesser_auto_manager_in_d_bits_data), // @[TSIHarness.scala:66:29]
.auto_out_d_bits_corrupt (_serdesser_auto_manager_in_d_bits_corrupt) // @[TSIHarness.scala:66:29]
); // @[Buffer.scala:75:28]
DecoupledSerialPhy phy ( // @[TSIHarness.scala:129:21]
.io_outer_clock (clock),
.io_outer_reset (reset),
.io_inner_clock (clock),
.io_inner_reset (reset),
.io_outer_ser_in_ready (io_ser_in_ready),
.io_outer_ser_in_valid (io_ser_in_valid),
.io_outer_ser_in_bits_phit (io_ser_in_bits_phit),
.io_outer_ser_out_ready (io_ser_out_ready),
.io_outer_ser_out_valid (io_ser_out_valid),
.io_outer_ser_out_bits_phit (io_ser_out_bits_phit),
.io_inner_ser_0_in_ready (_serdesser_io_ser_0_in_ready), // @[TSIHarness.scala:66:29]
.io_inner_ser_0_in_valid (_phy_io_inner_ser_0_in_valid),
.io_inner_ser_0_in_bits_flit (_phy_io_inner_ser_0_in_bits_flit),
.io_inner_ser_0_out_bits_flit (_serdesser_io_ser_0_out_bits_flit), // @[TSIHarness.scala:66:29]
.io_inner_ser_1_in_ready (_serdesser_io_ser_1_in_ready), // @[TSIHarness.scala:66:29]
.io_inner_ser_1_in_valid (_phy_io_inner_ser_1_in_valid),
.io_inner_ser_1_in_bits_flit (_phy_io_inner_ser_1_in_bits_flit),
.io_inner_ser_1_out_ready (/* unused */),
.io_inner_ser_1_out_valid (1'h0), // @[TSIHarness.scala:66:29, :76:28, :129:21]
.io_inner_ser_1_out_bits_flit (32'h0), // @[TSIHarness.scala:66:29, :129:21]
.io_inner_ser_2_in_ready (_serdesser_io_ser_2_in_ready), // @[TSIHarness.scala:66:29]
.io_inner_ser_2_in_valid (_phy_io_inner_ser_2_in_valid),
.io_inner_ser_2_in_bits_flit (_phy_io_inner_ser_2_in_bits_flit),
.io_inner_ser_2_out_ready (_phy_io_inner_ser_2_out_ready),
.io_inner_ser_2_out_valid (_serdesser_io_ser_2_out_valid), // @[TSIHarness.scala:66:29]
.io_inner_ser_2_out_bits_flit (_serdesser_io_ser_2_out_bits_flit), // @[TSIHarness.scala:66:29]
.io_inner_ser_3_in_ready (_serdesser_io_ser_3_in_ready), // @[TSIHarness.scala:66:29]
.io_inner_ser_3_in_valid (_phy_io_inner_ser_3_in_valid),
.io_inner_ser_3_in_bits_flit (_phy_io_inner_ser_3_in_bits_flit),
.io_inner_ser_3_out_ready (/* unused */),
.io_inner_ser_3_out_valid (1'h0), // @[TSIHarness.scala:66:29, :76:28, :129:21]
.io_inner_ser_3_out_bits_flit (32'h0), // @[TSIHarness.scala:66:29, :129:21]
.io_inner_ser_4_in_ready (_serdesser_io_ser_4_in_ready), // @[TSIHarness.scala:66:29]
.io_inner_ser_4_in_valid (_phy_io_inner_ser_4_in_valid),
.io_inner_ser_4_in_bits_flit (_phy_io_inner_ser_4_in_bits_flit),
.io_inner_ser_4_out_ready (_phy_io_inner_ser_4_out_ready),
.io_inner_ser_4_out_valid (_serdesser_io_ser_4_out_valid), // @[TSIHarness.scala:66:29]
.io_inner_ser_4_out_bits_flit (_serdesser_io_ser_4_out_bits_flit) // @[TSIHarness.scala:66:29]
); // @[TSIHarness.scala:129:21]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_140 :
input clock : Clock
input reset : Reset
output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}}
connect io.y, io.x | module OptimizationBarrier_TLBEntryData_140( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae_ptw, // @[package.scala:268:18]
input io_x_ae_final, // @[package.scala:268:18]
input io_x_ae_stage2, // @[package.scala:268:18]
input io_x_pf, // @[package.scala:268:18]
input io_x_gf, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_hw, // @[package.scala:268:18]
input io_x_hx, // @[package.scala:268:18]
input io_x_hr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_ppp, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output [19:0] io_y_ppn // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30]
wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30]
wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30]
wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30]
wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30]
wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30]
wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_ptw = io_x_ae_ptw_0; // @[package.scala:267:30]
wire io_y_ae_final = io_x_ae_final_0; // @[package.scala:267:30]
wire io_y_ae_stage2 = io_x_ae_stage2_0; // @[package.scala:267:30]
wire io_y_pf = io_x_pf_0; // @[package.scala:267:30]
wire io_y_gf = io_x_gf_0; // @[package.scala:267:30]
wire io_y_sw = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr = io_x_sr_0; // @[package.scala:267:30]
wire io_y_hw = io_x_hw_0; // @[package.scala:267:30]
wire io_y_hx = io_x_hx_0; // @[package.scala:267:30]
wire io_y_hr = io_x_hr_0; // @[package.scala:267:30]
wire io_y_pw = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr = io_x_pr_0; // @[package.scala:267:30]
wire io_y_ppp = io_x_ppp_0; // @[package.scala:267:30]
wire io_y_pal = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_321 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_321( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module SwitchArbiter_120 :
input clock : Clock
input reset : Reset
output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[2], `0` : UInt<1>[2]}, tail : UInt<1>}}[2], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[2], `0` : UInt<1>[2]}, tail : UInt<1>}}[1], chosen_oh : UInt<2>[1]}
regreset lock_0 : UInt<2>, clock, reset, UInt<2>(0h0)
node _unassigned_T = cat(io.in[1].valid, io.in[0].valid)
node _unassigned_T_1 = not(lock_0)
node unassigned = and(_unassigned_T, _unassigned_T_1)
regreset mask : UInt<2>, clock, reset, UInt<2>(0h0)
wire choices : UInt<2>[1]
node _sel_T = not(mask)
node _sel_T_1 = and(unassigned, _sel_T)
node _sel_T_2 = cat(unassigned, _sel_T_1)
node _sel_T_3 = bits(_sel_T_2, 0, 0)
node _sel_T_4 = bits(_sel_T_2, 1, 1)
node _sel_T_5 = bits(_sel_T_2, 2, 2)
node _sel_T_6 = bits(_sel_T_2, 3, 3)
node _sel_T_7 = mux(_sel_T_6, UInt<4>(0h8), UInt<4>(0h0))
node _sel_T_8 = mux(_sel_T_5, UInt<4>(0h4), _sel_T_7)
node _sel_T_9 = mux(_sel_T_4, UInt<4>(0h2), _sel_T_8)
node sel = mux(_sel_T_3, UInt<4>(0h1), _sel_T_9)
node _choices_0_T = shr(sel, 2)
node _choices_0_T_1 = or(sel, _choices_0_T)
connect choices[0], _choices_0_T_1
node _T = not(choices[0])
node _T_1 = and(unassigned, _T)
node _T_2 = bits(_T_1, 0, 0)
node _T_3 = bits(_T_1, 1, 1)
node _T_4 = mux(_T_3, UInt<2>(0h2), UInt<2>(0h0))
node _T_5 = mux(_T_2, UInt<2>(0h1), _T_4)
connect io.in[0].ready, UInt<1>(0h0)
connect io.in[1].ready, UInt<1>(0h0)
node in_tails = cat(io.in[1].bits.tail, io.in[0].bits.tail)
node _in_valids_T = eq(UInt<1>(0h0), UInt<1>(0h0))
node _in_valids_T_1 = and(io.in[0].valid, _in_valids_T)
node _in_valids_T_2 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _in_valids_T_3 = and(io.in[1].valid, _in_valids_T_2)
node in_valids = cat(_in_valids_T_3, _in_valids_T_1)
node _chosen_T = and(in_valids, lock_0)
node _chosen_T_1 = not(UInt<2>(0h0))
node _chosen_T_2 = and(_chosen_T, _chosen_T_1)
node _chosen_T_3 = orr(_chosen_T_2)
node chosen = mux(_chosen_T_3, lock_0, choices[0])
connect io.chosen_oh[0], chosen
node _io_out_0_valid_T = and(in_valids, chosen)
node _io_out_0_valid_T_1 = orr(_io_out_0_valid_T)
connect io.out[0].valid, _io_out_0_valid_T_1
node _io_out_0_bits_T = bits(chosen, 0, 0)
node _io_out_0_bits_T_1 = bits(chosen, 1, 1)
wire _io_out_0_bits_WIRE : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[2], `0` : UInt<1>[2]}, tail : UInt<1>}
node _io_out_0_bits_T_2 = mux(_io_out_0_bits_T, io.in[0].bits.tail, UInt<1>(0h0))
node _io_out_0_bits_T_3 = mux(_io_out_0_bits_T_1, io.in[1].bits.tail, UInt<1>(0h0))
node _io_out_0_bits_T_4 = or(_io_out_0_bits_T_2, _io_out_0_bits_T_3)
wire _io_out_0_bits_WIRE_1 : UInt<1>
connect _io_out_0_bits_WIRE_1, _io_out_0_bits_T_4
connect _io_out_0_bits_WIRE.tail, _io_out_0_bits_WIRE_1
wire _io_out_0_bits_WIRE_2 : { `2` : UInt<1>[1], `1` : UInt<1>[2], `0` : UInt<1>[2]}
wire _io_out_0_bits_WIRE_3 : UInt<1>[2]
node _io_out_0_bits_T_5 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[0], UInt<1>(0h0))
node _io_out_0_bits_T_6 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[0], UInt<1>(0h0))
node _io_out_0_bits_T_7 = or(_io_out_0_bits_T_5, _io_out_0_bits_T_6)
wire _io_out_0_bits_WIRE_4 : UInt<1>
connect _io_out_0_bits_WIRE_4, _io_out_0_bits_T_7
connect _io_out_0_bits_WIRE_3[0], _io_out_0_bits_WIRE_4
node _io_out_0_bits_T_8 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[1], UInt<1>(0h0))
node _io_out_0_bits_T_9 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[1], UInt<1>(0h0))
node _io_out_0_bits_T_10 = or(_io_out_0_bits_T_8, _io_out_0_bits_T_9)
wire _io_out_0_bits_WIRE_5 : UInt<1>
connect _io_out_0_bits_WIRE_5, _io_out_0_bits_T_10
connect _io_out_0_bits_WIRE_3[1], _io_out_0_bits_WIRE_5
connect _io_out_0_bits_WIRE_2.`0`, _io_out_0_bits_WIRE_3
wire _io_out_0_bits_WIRE_6 : UInt<1>[2]
node _io_out_0_bits_T_11 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`1`[0], UInt<1>(0h0))
node _io_out_0_bits_T_12 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`1`[0], UInt<1>(0h0))
node _io_out_0_bits_T_13 = or(_io_out_0_bits_T_11, _io_out_0_bits_T_12)
wire _io_out_0_bits_WIRE_7 : UInt<1>
connect _io_out_0_bits_WIRE_7, _io_out_0_bits_T_13
connect _io_out_0_bits_WIRE_6[0], _io_out_0_bits_WIRE_7
node _io_out_0_bits_T_14 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`1`[1], UInt<1>(0h0))
node _io_out_0_bits_T_15 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`1`[1], UInt<1>(0h0))
node _io_out_0_bits_T_16 = or(_io_out_0_bits_T_14, _io_out_0_bits_T_15)
wire _io_out_0_bits_WIRE_8 : UInt<1>
connect _io_out_0_bits_WIRE_8, _io_out_0_bits_T_16
connect _io_out_0_bits_WIRE_6[1], _io_out_0_bits_WIRE_8
connect _io_out_0_bits_WIRE_2.`1`, _io_out_0_bits_WIRE_6
wire _io_out_0_bits_WIRE_9 : UInt<1>[1]
node _io_out_0_bits_T_17 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`2`[0], UInt<1>(0h0))
node _io_out_0_bits_T_18 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`2`[0], UInt<1>(0h0))
node _io_out_0_bits_T_19 = or(_io_out_0_bits_T_17, _io_out_0_bits_T_18)
wire _io_out_0_bits_WIRE_10 : UInt<1>
connect _io_out_0_bits_WIRE_10, _io_out_0_bits_T_19
connect _io_out_0_bits_WIRE_9[0], _io_out_0_bits_WIRE_10
connect _io_out_0_bits_WIRE_2.`2`, _io_out_0_bits_WIRE_9
connect _io_out_0_bits_WIRE.vc_sel, _io_out_0_bits_WIRE_2
connect io.out[0].bits, _io_out_0_bits_WIRE
node _T_6 = bits(chosen, 0, 0)
node _T_7 = and(_T_6, io.out[0].ready)
when _T_7 :
connect io.in[0].ready, UInt<1>(0h1)
node _T_8 = bits(chosen, 1, 1)
node _T_9 = and(_T_8, io.out[0].ready)
when _T_9 :
connect io.in[1].ready, UInt<1>(0h1)
node _T_10 = or(UInt<2>(0h0), chosen)
node _T_11 = and(io.out[0].ready, io.out[0].valid)
when _T_11 :
node _lock_0_T = not(in_tails)
node _lock_0_T_1 = and(chosen, _lock_0_T)
connect lock_0, _lock_0_T_1
node _T_12 = and(io.out[0].ready, io.out[0].valid)
when _T_12 :
node _mask_T = shr(io.chosen_oh[0], 0)
node _mask_T_1 = shr(io.chosen_oh[0], 1)
node _mask_T_2 = or(_mask_T, _mask_T_1)
connect mask, _mask_T_2
else :
node _mask_T_3 = not(mask)
node _mask_T_4 = eq(_mask_T_3, UInt<1>(0h0))
node _mask_T_5 = shl(mask, 1)
node _mask_T_6 = or(_mask_T_5, UInt<1>(0h1))
node _mask_T_7 = mux(_mask_T_4, UInt<1>(0h0), _mask_T_6)
connect mask, _mask_T_7 | module SwitchArbiter_120( // @[SwitchAllocator.scala:17:7]
input clock, // @[SwitchAllocator.scala:17:7]
input reset, // @[SwitchAllocator.scala:17:7]
output io_in_0_ready, // @[SwitchAllocator.scala:18:14]
input io_in_0_valid, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_0_0, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_tail, // @[SwitchAllocator.scala:18:14]
output io_in_1_ready, // @[SwitchAllocator.scala:18:14]
input io_in_1_valid, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_tail, // @[SwitchAllocator.scala:18:14]
input io_out_0_ready, // @[SwitchAllocator.scala:18:14]
output io_out_0_valid, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_0_0, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_tail, // @[SwitchAllocator.scala:18:14]
output [1:0] io_chosen_oh_0 // @[SwitchAllocator.scala:18:14]
);
reg [1:0] lock_0; // @[SwitchAllocator.scala:24:38]
wire [1:0] unassigned = {io_in_1_valid, io_in_0_valid} & ~lock_0; // @[SwitchAllocator.scala:24:38, :25:{23,52,54}]
reg [1:0] mask; // @[SwitchAllocator.scala:27:21]
wire [1:0] _sel_T_1 = unassigned & ~mask; // @[SwitchAllocator.scala:25:52, :27:21, :30:{58,60}]
wire [3:0] sel = _sel_T_1[0] ? 4'h1 : _sel_T_1[1] ? 4'h2 : unassigned[0] ? 4'h4 : {unassigned[1], 3'h0}; // @[OneHot.scala:85:71]
wire [1:0] in_valids = {io_in_1_valid, io_in_0_valid}; // @[SwitchAllocator.scala:41:24]
wire [1:0] chosen = (|(in_valids & lock_0)) ? lock_0 : sel[1:0] | sel[3:2]; // @[Mux.scala:50:70]
wire [1:0] _io_out_0_valid_T = in_valids & chosen; // @[SwitchAllocator.scala:41:24, :42:21, :44:35]
wire _GEN = io_out_0_ready & (|_io_out_0_valid_T); // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[SwitchAllocator.scala:17:7]
if (reset) begin // @[SwitchAllocator.scala:17:7]
lock_0 <= 2'h0; // @[SwitchAllocator.scala:24:38]
mask <= 2'h0; // @[SwitchAllocator.scala:27:21]
end
else begin // @[SwitchAllocator.scala:17:7]
if (_GEN) // @[Decoupled.scala:51:35]
lock_0 <= chosen & ~{io_in_1_bits_tail, io_in_0_bits_tail}; // @[SwitchAllocator.scala:24:38, :39:21, :42:21, :53:{25,27}]
mask <= _GEN ? {chosen[1], |chosen} : (&mask) ? 2'h0 : {mask[0], 1'h1}; // @[Decoupled.scala:51:35]
end
always @(posedge) |
Generate the Verilog code corresponding to this FIRRTL code module MemExeUnit :
input clock : Clock
input reset : Reset
input io_kill : UInt<1>
input io_brupdate : { b1 : { resolve_mask : UInt<12>, mispredict_mask : UInt<12>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}
input io_status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}
output io_ready_fu_types : UInt<1>[10]
input io_fcsr_rm : UInt<3>
input io_iss_uop : { valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}
output io_arb_irf_reqs : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<7>}[1]
input io_arb_rebusys : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<2>, rebusy : UInt<1>}}[1]
input io_rrd_irf_resps : UInt<64>[1]
input io_rrd_irf_bypasses : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, data : UInt<64>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : UInt<5>}}}[3]
output io_arb_immrf_req : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<5>}
input io_rrd_immrf_resp : UInt<64>
output io_rrd_immrf_wakeup : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<2>, rebusy : UInt<1>}}
output io_squash_iss : UInt<1>
output io_dgen : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, data : UInt<64>}}
reg arb_uop : { valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}, clock
node _arb_uop_valid_T = and(io_brupdate.b1.mispredict_mask, io_iss_uop.bits.br_mask)
node _arb_uop_valid_T_1 = neq(_arb_uop_valid_T, UInt<1>(0h0))
node _arb_uop_valid_T_2 = or(_arb_uop_valid_T_1, io_kill)
node _arb_uop_valid_T_3 = eq(_arb_uop_valid_T_2, UInt<1>(0h0))
node _arb_uop_valid_T_4 = and(io_iss_uop.valid, _arb_uop_valid_T_3)
connect arb_uop.valid, _arb_uop_valid_T_4
wire arb_uop_bits_out : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}
connect arb_uop_bits_out, io_iss_uop.bits
node _arb_uop_bits_out_br_mask_T = not(io_brupdate.b1.resolve_mask)
node _arb_uop_bits_out_br_mask_T_1 = and(io_iss_uop.bits.br_mask, _arb_uop_bits_out_br_mask_T)
connect arb_uop_bits_out.br_mask, _arb_uop_bits_out_br_mask_T_1
connect arb_uop.bits, arb_uop_bits_out
reg rrd_uop : { valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}, clock
node _rrd_uop_valid_T = and(io_brupdate.b1.mispredict_mask, arb_uop.bits.br_mask)
node _rrd_uop_valid_T_1 = neq(_rrd_uop_valid_T, UInt<1>(0h0))
node _rrd_uop_valid_T_2 = or(_rrd_uop_valid_T_1, io_kill)
node _rrd_uop_valid_T_3 = eq(_rrd_uop_valid_T_2, UInt<1>(0h0))
node _rrd_uop_valid_T_4 = and(arb_uop.valid, _rrd_uop_valid_T_3)
connect rrd_uop.valid, _rrd_uop_valid_T_4
wire rrd_uop_bits_out : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}
connect rrd_uop_bits_out, arb_uop.bits
node _rrd_uop_bits_out_br_mask_T = not(io_brupdate.b1.resolve_mask)
node _rrd_uop_bits_out_br_mask_T_1 = and(arb_uop.bits.br_mask, _rrd_uop_bits_out_br_mask_T)
connect rrd_uop_bits_out.br_mask, _rrd_uop_bits_out_br_mask_T_1
connect rrd_uop.bits, rrd_uop_bits_out
reg exe_uop : { valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}, clock
node _exe_uop_valid_T = and(io_brupdate.b1.mispredict_mask, rrd_uop.bits.br_mask)
node _exe_uop_valid_T_1 = neq(_exe_uop_valid_T, UInt<1>(0h0))
node _exe_uop_valid_T_2 = or(_exe_uop_valid_T_1, io_kill)
node _exe_uop_valid_T_3 = eq(_exe_uop_valid_T_2, UInt<1>(0h0))
node _exe_uop_valid_T_4 = and(rrd_uop.valid, _exe_uop_valid_T_3)
connect exe_uop.valid, _exe_uop_valid_T_4
wire exe_uop_bits_out : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}
connect exe_uop_bits_out, rrd_uop.bits
node _exe_uop_bits_out_br_mask_T = not(io_brupdate.b1.resolve_mask)
node _exe_uop_bits_out_br_mask_T_1 = and(rrd_uop.bits.br_mask, _exe_uop_bits_out_br_mask_T)
connect exe_uop_bits_out.br_mask, _exe_uop_bits_out_br_mask_T_1
connect exe_uop.bits, exe_uop_bits_out
node _io_arb_irf_reqs_0_valid_T = eq(arb_uop.bits.lrs1_rtype, UInt<2>(0h0))
node _io_arb_irf_reqs_0_valid_T_1 = and(arb_uop.valid, _io_arb_irf_reqs_0_valid_T)
node _io_arb_irf_reqs_0_valid_T_2 = eq(arb_uop.bits.iw_p1_bypass_hint, UInt<1>(0h0))
node _io_arb_irf_reqs_0_valid_T_3 = and(_io_arb_irf_reqs_0_valid_T_1, _io_arb_irf_reqs_0_valid_T_2)
connect io_arb_irf_reqs[0].valid, _io_arb_irf_reqs_0_valid_T_3
connect io_arb_irf_reqs[0].bits, arb_uop.bits.prs1
node _arb_rebusied_prs1_T = eq(arb_uop.bits.lrs1_rtype, UInt<2>(0h0))
node _arb_rebusied_prs1_T_1 = and(io_arb_rebusys[0].valid, io_arb_rebusys[0].bits.rebusy)
node _arb_rebusied_prs1_T_2 = eq(io_arb_rebusys[0].bits.uop.pdst, arb_uop.bits.prs1)
node _arb_rebusied_prs1_T_3 = and(_arb_rebusied_prs1_T_1, _arb_rebusied_prs1_T_2)
node arb_rebusied_prs1 = and(_arb_rebusied_prs1_T, _arb_rebusied_prs1_T_3)
node _arb_rebusied_prs2_T = eq(arb_uop.bits.lrs2_rtype, UInt<2>(0h0))
node _arb_rebusied_prs2_T_1 = and(io_arb_rebusys[0].valid, io_arb_rebusys[0].bits.rebusy)
node _arb_rebusied_prs2_T_2 = eq(io_arb_rebusys[0].bits.uop.pdst, arb_uop.bits.prs2)
node _arb_rebusied_prs2_T_3 = and(_arb_rebusied_prs2_T_1, _arb_rebusied_prs2_T_2)
node _arb_rebusied_prs2_T_4 = and(_arb_rebusied_prs2_T, _arb_rebusied_prs2_T_3)
node arb_rebusied_prs2 = and(_arb_rebusied_prs2_T_4, UInt<1>(0h0))
node arb_rebusied = or(arb_rebusied_prs1, arb_rebusied_prs2)
reg exe_rs1_data : UInt<64>, clock
reg exe_rs2_data : UInt<64>, clock
node _hits_T = eq(rrd_uop.bits.prs1, io_rrd_irf_bypasses[0].bits.uop.pdst)
node hits_0 = and(io_rrd_irf_bypasses[0].valid, _hits_T)
node _hits_T_1 = eq(rrd_uop.bits.prs1, io_rrd_irf_bypasses[1].bits.uop.pdst)
node hits_1 = and(io_rrd_irf_bypasses[1].valid, _hits_T_1)
node _hits_T_2 = eq(rrd_uop.bits.prs1, io_rrd_irf_bypasses[2].bits.uop.pdst)
node hits_2 = and(io_rrd_irf_bypasses[2].valid, _hits_T_2)
node _T = or(hits_0, hits_1)
node rs1_hit = or(_T, hits_2)
node _T_1 = or(hits_0, hits_1)
node _T_2 = or(_T_1, hits_2)
node _T_3 = mux(hits_0, io_rrd_irf_bypasses[0].bits.data, UInt<1>(0h0))
node _T_4 = mux(hits_1, io_rrd_irf_bypasses[1].bits.data, UInt<1>(0h0))
node _T_5 = mux(hits_2, io_rrd_irf_bypasses[2].bits.data, UInt<1>(0h0))
node _T_6 = or(_T_3, _T_4)
node _T_7 = or(_T_6, _T_5)
wire _WIRE : UInt<64>
connect _WIRE, _T_7
node rs1_data = mux(_T_2, _WIRE, io_rrd_irf_resps[0])
node _T_8 = eq(rrd_uop.bits.lrs1_rtype, UInt<2>(0h0))
node _T_9 = and(rrd_uop.valid, _T_8)
node _T_10 = and(_T_9, rrd_uop.bits.iw_p1_bypass_hint)
node _T_11 = eq(rs1_hit, UInt<1>(0h0))
node _T_12 = and(_T_10, _T_11)
node _T_13 = eq(_T_12, UInt<1>(0h0))
node _T_14 = asUInt(reset)
node _T_15 = eq(_T_14, UInt<1>(0h0))
when _T_15 :
node _T_16 = eq(_T_13, UInt<1>(0h0))
when _T_16 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at execution-unit.scala:136 assert(!(rrd_uop.valid && rrd_uop.bits.lrs1_rtype === RT_FIX && rrd_uop.bits.iw_p1_bypass_hint && !rs1_hit))\n") : printf
assert(clock, _T_13, UInt<1>(0h1), "") : assert
node _exe_rs1_data_T = eq(rrd_uop.bits.lrs1_rtype, UInt<2>(0h3))
node _exe_rs1_data_T_1 = mux(_exe_rs1_data_T, UInt<1>(0h0), rs1_data)
connect exe_rs1_data, _exe_rs1_data_T_1
invalidate exe_rs2_data
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(io_arb_immrf_req.ready, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at execution-unit.scala:152 assert(io_arb_immrf_req.ready)\n") : printf_1
assert(clock, io_arb_immrf_req.ready, UInt<1>(0h1), "") : assert_1
node _io_arb_immrf_req_valid_T = eq(arb_uop.bits.imm_sel, UInt<3>(0h6))
node _io_arb_immrf_req_valid_T_1 = eq(arb_uop.bits.imm_sel, UInt<3>(0h5))
node _io_arb_immrf_req_valid_T_2 = or(_io_arb_immrf_req_valid_T, _io_arb_immrf_req_valid_T_1)
node _io_arb_immrf_req_valid_T_3 = eq(_io_arb_immrf_req_valid_T_2, UInt<1>(0h0))
node _io_arb_immrf_req_valid_T_4 = and(arb_uop.valid, _io_arb_immrf_req_valid_T_3)
connect io_arb_immrf_req.valid, _io_arb_immrf_req_valid_T_4
connect io_arb_immrf_req.bits, arb_uop.bits.pimm
node _io_rrd_immrf_wakeup_valid_T = eq(rrd_uop.bits.imm_sel, UInt<3>(0h6))
node _io_rrd_immrf_wakeup_valid_T_1 = eq(rrd_uop.bits.imm_sel, UInt<3>(0h5))
node _io_rrd_immrf_wakeup_valid_T_2 = or(_io_rrd_immrf_wakeup_valid_T, _io_rrd_immrf_wakeup_valid_T_1)
node _io_rrd_immrf_wakeup_valid_T_3 = eq(_io_rrd_immrf_wakeup_valid_T_2, UInt<1>(0h0))
node _io_rrd_immrf_wakeup_valid_T_4 = and(rrd_uop.valid, _io_rrd_immrf_wakeup_valid_T_3)
connect io_rrd_immrf_wakeup.valid, _io_rrd_immrf_wakeup_valid_T_4
connect io_rrd_immrf_wakeup.bits.speculative_mask, UInt<1>(0h0)
connect io_rrd_immrf_wakeup.bits.rebusy, UInt<1>(0h0)
connect io_rrd_immrf_wakeup.bits.bypassable, UInt<1>(0h0)
connect io_rrd_immrf_wakeup.bits.uop, rrd_uop.bits
node _exe_imm_data_T = eq(rrd_uop.bits.imm_sel, UInt<3>(0h5))
node _exe_imm_data_T_1 = bits(rrd_uop.bits.pimm, 4, 4)
node _exe_imm_data_T_2 = mux(_exe_imm_data_T_1, UInt<59>(0h7ffffffffffffff), UInt<59>(0h0))
node _exe_imm_data_T_3 = cat(_exe_imm_data_T_2, rrd_uop.bits.pimm)
node _exe_imm_data_ip_T = eq(rrd_uop.bits.imm_sel, UInt<3>(0h6))
node exe_imm_data_ip = mux(_exe_imm_data_ip_T, UInt<20>(0h0), io_rrd_immrf_resp)
node _exe_imm_data_sign_T = bits(exe_imm_data_ip, 19, 19)
node exe_imm_data_sign = asSInt(_exe_imm_data_sign_T)
node _exe_imm_data_i30_20_T = eq(rrd_uop.bits.imm_sel, UInt<3>(0h3))
node _exe_imm_data_i30_20_T_1 = bits(exe_imm_data_ip, 18, 8)
node _exe_imm_data_i30_20_T_2 = asSInt(_exe_imm_data_i30_20_T_1)
node exe_imm_data_i30_20 = mux(_exe_imm_data_i30_20_T, _exe_imm_data_i30_20_T_2, exe_imm_data_sign)
node _exe_imm_data_i19_12_T = eq(rrd_uop.bits.imm_sel, UInt<3>(0h3))
node _exe_imm_data_i19_12_T_1 = eq(rrd_uop.bits.imm_sel, UInt<3>(0h4))
node _exe_imm_data_i19_12_T_2 = or(_exe_imm_data_i19_12_T, _exe_imm_data_i19_12_T_1)
node _exe_imm_data_i19_12_T_3 = bits(exe_imm_data_ip, 7, 0)
node _exe_imm_data_i19_12_T_4 = asSInt(_exe_imm_data_i19_12_T_3)
node exe_imm_data_i19_12 = mux(_exe_imm_data_i19_12_T_2, _exe_imm_data_i19_12_T_4, exe_imm_data_sign)
node _exe_imm_data_i11_T = eq(rrd_uop.bits.imm_sel, UInt<3>(0h3))
node _exe_imm_data_i11_T_1 = eq(rrd_uop.bits.imm_sel, UInt<3>(0h4))
node _exe_imm_data_i11_T_2 = eq(rrd_uop.bits.imm_sel, UInt<3>(0h2))
node _exe_imm_data_i11_T_3 = or(_exe_imm_data_i11_T_1, _exe_imm_data_i11_T_2)
node _exe_imm_data_i11_T_4 = bits(exe_imm_data_ip, 8, 8)
node _exe_imm_data_i11_T_5 = asSInt(_exe_imm_data_i11_T_4)
node _exe_imm_data_i11_T_6 = mux(_exe_imm_data_i11_T_3, _exe_imm_data_i11_T_5, exe_imm_data_sign)
node exe_imm_data_i11 = mux(_exe_imm_data_i11_T, asSInt(UInt<1>(0h0)), _exe_imm_data_i11_T_6)
node _exe_imm_data_i10_5_T = eq(rrd_uop.bits.imm_sel, UInt<3>(0h3))
node _exe_imm_data_i10_5_T_1 = bits(exe_imm_data_ip, 18, 14)
node _exe_imm_data_i10_5_T_2 = asSInt(_exe_imm_data_i10_5_T_1)
node exe_imm_data_i10_5 = mux(_exe_imm_data_i10_5_T, asSInt(UInt<1>(0h0)), _exe_imm_data_i10_5_T_2)
node _exe_imm_data_i4_1_T = eq(rrd_uop.bits.imm_sel, UInt<3>(0h3))
node _exe_imm_data_i4_1_T_1 = bits(exe_imm_data_ip, 13, 9)
node _exe_imm_data_i4_1_T_2 = asSInt(_exe_imm_data_i4_1_T_1)
node exe_imm_data_i4_1 = mux(_exe_imm_data_i4_1_T, asSInt(UInt<1>(0h0)), _exe_imm_data_i4_1_T_2)
node _exe_imm_data_i0_T = eq(rrd_uop.bits.imm_sel, UInt<3>(0h1))
node _exe_imm_data_i0_T_1 = eq(rrd_uop.bits.imm_sel, UInt<3>(0h0))
node _exe_imm_data_i0_T_2 = or(_exe_imm_data_i0_T, _exe_imm_data_i0_T_1)
node _exe_imm_data_i0_T_3 = bits(exe_imm_data_ip, 8, 8)
node _exe_imm_data_i0_T_4 = asSInt(_exe_imm_data_i0_T_3)
node exe_imm_data_i0 = mux(_exe_imm_data_i0_T_2, _exe_imm_data_i0_T_4, asSInt(UInt<1>(0h0)))
node exe_imm_data_lo_lo = asUInt(exe_imm_data_i0)
node exe_imm_data_lo_hi_lo = asUInt(exe_imm_data_i4_1)
node exe_imm_data_lo_hi_hi = asUInt(exe_imm_data_i10_5)
node exe_imm_data_lo_hi = cat(exe_imm_data_lo_hi_hi, exe_imm_data_lo_hi_lo)
node exe_imm_data_lo = cat(exe_imm_data_lo_hi, exe_imm_data_lo_lo)
node exe_imm_data_hi_lo_lo = asUInt(exe_imm_data_i11)
node exe_imm_data_hi_lo_hi = asUInt(exe_imm_data_i19_12)
node exe_imm_data_hi_lo = cat(exe_imm_data_hi_lo_hi, exe_imm_data_hi_lo_lo)
node exe_imm_data_hi_hi_lo = asUInt(exe_imm_data_i30_20)
node exe_imm_data_hi_hi_hi = asUInt(exe_imm_data_sign)
node exe_imm_data_hi_hi = cat(exe_imm_data_hi_hi_hi, exe_imm_data_hi_hi_lo)
node exe_imm_data_hi = cat(exe_imm_data_hi_hi, exe_imm_data_hi_lo)
node _exe_imm_data_T_4 = cat(exe_imm_data_hi, exe_imm_data_lo)
node _exe_imm_data_T_5 = bits(_exe_imm_data_T_4, 31, 31)
node _exe_imm_data_T_6 = mux(_exe_imm_data_T_5, UInt<32>(0hffffffff), UInt<32>(0h0))
node _exe_imm_data_T_7 = cat(_exe_imm_data_T_6, _exe_imm_data_T_4)
node _exe_imm_data_T_8 = mux(_exe_imm_data_T, _exe_imm_data_T_3, _exe_imm_data_T_7)
reg exe_imm_data : UInt, clock
connect exe_imm_data, _exe_imm_data_T_8
node _io_squash_iss_T = eq(io_arb_irf_reqs[0].ready, UInt<1>(0h0))
node _io_squash_iss_T_1 = and(io_arb_irf_reqs[0].valid, _io_squash_iss_T)
connect io_squash_iss, _io_squash_iss_T_1
node _T_20 = or(io_squash_iss, arb_rebusied)
when _T_20 :
node _will_replay_T = and(io_brupdate.b1.mispredict_mask, arb_uop.bits.br_mask)
node _will_replay_T_1 = neq(_will_replay_T, UInt<1>(0h0))
node _will_replay_T_2 = or(_will_replay_T_1, io_kill)
node _will_replay_T_3 = eq(_will_replay_T_2, UInt<1>(0h0))
node _will_replay_T_4 = and(arb_uop.valid, _will_replay_T_3)
node _will_replay_T_5 = eq(arb_rebusied, UInt<1>(0h0))
node will_replay = and(_will_replay_T_4, _will_replay_T_5)
connect arb_uop.valid, will_replay
wire arb_uop_bits_out_1 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}
connect arb_uop_bits_out_1, arb_uop.bits
node _arb_uop_bits_out_br_mask_T_2 = not(io_brupdate.b1.resolve_mask)
node _arb_uop_bits_out_br_mask_T_3 = and(arb_uop.bits.br_mask, _arb_uop_bits_out_br_mask_T_2)
connect arb_uop_bits_out_1.br_mask, _arb_uop_bits_out_br_mask_T_3
connect arb_uop.bits, arb_uop_bits_out_1
connect arb_uop.bits.iw_p1_bypass_hint, UInt<1>(0h0)
connect arb_uop.bits.iw_p2_bypass_hint, UInt<1>(0h0)
connect rrd_uop.valid, UInt<1>(0h0)
node _io_agen_T = and(exe_uop.valid, exe_uop.bits.fu_code[1])
node _io_agen_T_1 = eq(_io_agen_T, UInt<1>(0h0))
node _io_agen_T_2 = asUInt(reset)
node _io_agen_T_3 = eq(_io_agen_T_2, UInt<1>(0h0))
when _io_agen_T_3 :
node _io_agen_T_4 = eq(_io_agen_T_1, UInt<1>(0h0))
when _io_agen_T_4 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at execution-unit.scala:311 assert(!(exe_uop.valid && exe_uop.bits.fu_code(FC_AGEN)))\n") : io_agen_printf
assert(clock, _io_agen_T_1, UInt<1>(0h1), "") : io_agen_assert
node _io_dgen_dgen_valid_T = and(exe_uop.valid, exe_uop.bits.fu_code[2])
connect io_dgen.valid, _io_dgen_dgen_valid_T
connect io_dgen.bits.data, exe_rs1_data
connect io_dgen.bits.uop, exe_uop.bits
wire _r_WIRE : UInt<1>[10]
connect _r_WIRE[0], UInt<1>(0h0)
connect _r_WIRE[1], UInt<1>(0h0)
connect _r_WIRE[2], UInt<1>(0h0)
connect _r_WIRE[3], UInt<1>(0h0)
connect _r_WIRE[4], UInt<1>(0h0)
connect _r_WIRE[5], UInt<1>(0h0)
connect _r_WIRE[6], UInt<1>(0h0)
connect _r_WIRE[7], UInt<1>(0h0)
connect _r_WIRE[8], UInt<1>(0h0)
connect _r_WIRE[9], UInt<1>(0h0)
wire r : UInt<1>[10]
connect r, _r_WIRE
when UInt<1>(0h1) :
connect r[2], UInt<1>(0h1)
connect io_ready_fu_types, r | module MemExeUnit( // @[execution-unit.scala:255:7]
input clock, // @[execution-unit.scala:255:7]
input reset, // @[execution-unit.scala:255:7]
input io_kill, // @[execution-unit.scala:79:19]
input [11:0] io_brupdate_b1_resolve_mask, // @[execution-unit.scala:80:23]
input [11:0] io_brupdate_b1_mispredict_mask, // @[execution-unit.scala:80:23]
input [31:0] io_brupdate_b2_uop_inst, // @[execution-unit.scala:80:23]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_is_rvc, // @[execution-unit.scala:80:23]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_iq_type_0, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_iq_type_1, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_iq_type_2, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_iq_type_3, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_fu_code_0, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_fu_code_1, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_fu_code_2, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_fu_code_3, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_fu_code_4, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_fu_code_5, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_fu_code_6, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_fu_code_7, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_fu_code_8, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_fu_code_9, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_iw_issued, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_iw_issued_partial_agen, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[execution-unit.scala:80:23]
input [1:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[execution-unit.scala:80:23]
input [1:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[execution-unit.scala:80:23]
input [1:0] io_brupdate_b2_uop_dis_col_sel, // @[execution-unit.scala:80:23]
input [11:0] io_brupdate_b2_uop_br_mask, // @[execution-unit.scala:80:23]
input [3:0] io_brupdate_b2_uop_br_tag, // @[execution-unit.scala:80:23]
input [3:0] io_brupdate_b2_uop_br_type, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_is_sfb, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_is_fence, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_is_fencei, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_is_sfence, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_is_amo, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_is_eret, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_is_rocc, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_is_mov, // @[execution-unit.scala:80:23]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_edge_inst, // @[execution-unit.scala:80:23]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_taken, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_imm_rename, // @[execution-unit.scala:80:23]
input [2:0] io_brupdate_b2_uop_imm_sel, // @[execution-unit.scala:80:23]
input [4:0] io_brupdate_b2_uop_pimm, // @[execution-unit.scala:80:23]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[execution-unit.scala:80:23]
input [1:0] io_brupdate_b2_uop_op1_sel, // @[execution-unit.scala:80:23]
input [2:0] io_brupdate_b2_uop_op2_sel, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_fp_ctrl_ldst, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_fp_ctrl_wen, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_fp_ctrl_ren1, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_fp_ctrl_ren2, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_fp_ctrl_ren3, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_fp_ctrl_swap12, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_fp_ctrl_swap23, // @[execution-unit.scala:80:23]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[execution-unit.scala:80:23]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_fp_ctrl_fromint, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_fp_ctrl_toint, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_fp_ctrl_fma, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_fp_ctrl_div, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_fp_ctrl_wflags, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_fp_ctrl_vec, // @[execution-unit.scala:80:23]
input [5:0] io_brupdate_b2_uop_rob_idx, // @[execution-unit.scala:80:23]
input [3:0] io_brupdate_b2_uop_ldq_idx, // @[execution-unit.scala:80:23]
input [3:0] io_brupdate_b2_uop_stq_idx, // @[execution-unit.scala:80:23]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[execution-unit.scala:80:23]
input [6:0] io_brupdate_b2_uop_pdst, // @[execution-unit.scala:80:23]
input [6:0] io_brupdate_b2_uop_prs1, // @[execution-unit.scala:80:23]
input [6:0] io_brupdate_b2_uop_prs2, // @[execution-unit.scala:80:23]
input [6:0] io_brupdate_b2_uop_prs3, // @[execution-unit.scala:80:23]
input [4:0] io_brupdate_b2_uop_ppred, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_prs1_busy, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_prs2_busy, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_prs3_busy, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_ppred_busy, // @[execution-unit.scala:80:23]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_exception, // @[execution-unit.scala:80:23]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[execution-unit.scala:80:23]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[execution-unit.scala:80:23]
input [1:0] io_brupdate_b2_uop_mem_size, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_mem_signed, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_uses_ldq, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_uses_stq, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_is_unique, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_flush_on_commit, // @[execution-unit.scala:80:23]
input [2:0] io_brupdate_b2_uop_csr_cmd, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_ldst_is_rs1, // @[execution-unit.scala:80:23]
input [5:0] io_brupdate_b2_uop_ldst, // @[execution-unit.scala:80:23]
input [5:0] io_brupdate_b2_uop_lrs1, // @[execution-unit.scala:80:23]
input [5:0] io_brupdate_b2_uop_lrs2, // @[execution-unit.scala:80:23]
input [5:0] io_brupdate_b2_uop_lrs3, // @[execution-unit.scala:80:23]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[execution-unit.scala:80:23]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[execution-unit.scala:80:23]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_frs3_en, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_fcn_dw, // @[execution-unit.scala:80:23]
input [4:0] io_brupdate_b2_uop_fcn_op, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_fp_val, // @[execution-unit.scala:80:23]
input [2:0] io_brupdate_b2_uop_fp_rm, // @[execution-unit.scala:80:23]
input [1:0] io_brupdate_b2_uop_fp_typ, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_xcpt_pf_if, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_xcpt_ae_if, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_xcpt_ma_if, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_bp_debug_if, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_bp_xcpt_if, // @[execution-unit.scala:80:23]
input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[execution-unit.scala:80:23]
input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[execution-unit.scala:80:23]
input io_brupdate_b2_mispredict, // @[execution-unit.scala:80:23]
input io_brupdate_b2_taken, // @[execution-unit.scala:80:23]
input [2:0] io_brupdate_b2_cfi_type, // @[execution-unit.scala:80:23]
input [1:0] io_brupdate_b2_pc_sel, // @[execution-unit.scala:80:23]
input [39:0] io_brupdate_b2_jalr_target, // @[execution-unit.scala:80:23]
input [20:0] io_brupdate_b2_target_offset, // @[execution-unit.scala:80:23]
input io_status_debug, // @[execution-unit.scala:81:21]
input io_status_cease, // @[execution-unit.scala:81:21]
input io_status_wfi, // @[execution-unit.scala:81:21]
input [1:0] io_status_dprv, // @[execution-unit.scala:81:21]
input io_status_dv, // @[execution-unit.scala:81:21]
input [1:0] io_status_prv, // @[execution-unit.scala:81:21]
input io_status_v, // @[execution-unit.scala:81:21]
input io_status_sd, // @[execution-unit.scala:81:21]
input io_status_mpv, // @[execution-unit.scala:81:21]
input io_status_gva, // @[execution-unit.scala:81:21]
input io_status_tsr, // @[execution-unit.scala:81:21]
input io_status_tw, // @[execution-unit.scala:81:21]
input io_status_tvm, // @[execution-unit.scala:81:21]
input io_status_mxr, // @[execution-unit.scala:81:21]
input io_status_sum, // @[execution-unit.scala:81:21]
input io_status_mprv, // @[execution-unit.scala:81:21]
input [1:0] io_status_fs, // @[execution-unit.scala:81:21]
input [1:0] io_status_mpp, // @[execution-unit.scala:81:21]
input io_status_spp, // @[execution-unit.scala:81:21]
input io_status_mpie, // @[execution-unit.scala:81:21]
input io_status_spie, // @[execution-unit.scala:81:21]
input io_status_mie, // @[execution-unit.scala:81:21]
input io_status_sie, // @[execution-unit.scala:81:21]
input [2:0] io_fcsr_rm, // @[execution-unit.scala:84:22]
input io_iss_uop_valid, // @[execution-unit.scala:90:22]
input [31:0] io_iss_uop_bits_inst, // @[execution-unit.scala:90:22]
input [31:0] io_iss_uop_bits_debug_inst, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_is_rvc, // @[execution-unit.scala:90:22]
input [39:0] io_iss_uop_bits_debug_pc, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_iq_type_0, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_iq_type_1, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_iq_type_2, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_iq_type_3, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_fu_code_0, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_fu_code_1, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_fu_code_2, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_fu_code_3, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_fu_code_4, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_fu_code_5, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_fu_code_6, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_fu_code_7, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_fu_code_8, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_fu_code_9, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_iw_issued, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_iw_issued_partial_agen, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_iw_issued_partial_dgen, // @[execution-unit.scala:90:22]
input [1:0] io_iss_uop_bits_iw_p1_speculative_child, // @[execution-unit.scala:90:22]
input [1:0] io_iss_uop_bits_iw_p2_speculative_child, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_iw_p1_bypass_hint, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_iw_p2_bypass_hint, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_iw_p3_bypass_hint, // @[execution-unit.scala:90:22]
input [1:0] io_iss_uop_bits_dis_col_sel, // @[execution-unit.scala:90:22]
input [11:0] io_iss_uop_bits_br_mask, // @[execution-unit.scala:90:22]
input [3:0] io_iss_uop_bits_br_tag, // @[execution-unit.scala:90:22]
input [3:0] io_iss_uop_bits_br_type, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_is_sfb, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_is_fence, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_is_fencei, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_is_sfence, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_is_amo, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_is_eret, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_is_sys_pc2epc, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_is_rocc, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_is_mov, // @[execution-unit.scala:90:22]
input [4:0] io_iss_uop_bits_ftq_idx, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_edge_inst, // @[execution-unit.scala:90:22]
input [5:0] io_iss_uop_bits_pc_lob, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_taken, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_imm_rename, // @[execution-unit.scala:90:22]
input [2:0] io_iss_uop_bits_imm_sel, // @[execution-unit.scala:90:22]
input [4:0] io_iss_uop_bits_pimm, // @[execution-unit.scala:90:22]
input [19:0] io_iss_uop_bits_imm_packed, // @[execution-unit.scala:90:22]
input [1:0] io_iss_uop_bits_op1_sel, // @[execution-unit.scala:90:22]
input [2:0] io_iss_uop_bits_op2_sel, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_fp_ctrl_ldst, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_fp_ctrl_wen, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_fp_ctrl_ren1, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_fp_ctrl_ren2, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_fp_ctrl_ren3, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_fp_ctrl_swap12, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_fp_ctrl_swap23, // @[execution-unit.scala:90:22]
input [1:0] io_iss_uop_bits_fp_ctrl_typeTagIn, // @[execution-unit.scala:90:22]
input [1:0] io_iss_uop_bits_fp_ctrl_typeTagOut, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_fp_ctrl_fromint, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_fp_ctrl_toint, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_fp_ctrl_fastpipe, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_fp_ctrl_fma, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_fp_ctrl_div, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_fp_ctrl_sqrt, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_fp_ctrl_wflags, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_fp_ctrl_vec, // @[execution-unit.scala:90:22]
input [5:0] io_iss_uop_bits_rob_idx, // @[execution-unit.scala:90:22]
input [3:0] io_iss_uop_bits_ldq_idx, // @[execution-unit.scala:90:22]
input [3:0] io_iss_uop_bits_stq_idx, // @[execution-unit.scala:90:22]
input [1:0] io_iss_uop_bits_rxq_idx, // @[execution-unit.scala:90:22]
input [6:0] io_iss_uop_bits_pdst, // @[execution-unit.scala:90:22]
input [6:0] io_iss_uop_bits_prs1, // @[execution-unit.scala:90:22]
input [6:0] io_iss_uop_bits_prs2, // @[execution-unit.scala:90:22]
input [6:0] io_iss_uop_bits_prs3, // @[execution-unit.scala:90:22]
input [4:0] io_iss_uop_bits_ppred, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_prs1_busy, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_prs2_busy, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_prs3_busy, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_ppred_busy, // @[execution-unit.scala:90:22]
input [6:0] io_iss_uop_bits_stale_pdst, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_exception, // @[execution-unit.scala:90:22]
input [63:0] io_iss_uop_bits_exc_cause, // @[execution-unit.scala:90:22]
input [4:0] io_iss_uop_bits_mem_cmd, // @[execution-unit.scala:90:22]
input [1:0] io_iss_uop_bits_mem_size, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_mem_signed, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_uses_ldq, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_uses_stq, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_is_unique, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_flush_on_commit, // @[execution-unit.scala:90:22]
input [2:0] io_iss_uop_bits_csr_cmd, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_ldst_is_rs1, // @[execution-unit.scala:90:22]
input [5:0] io_iss_uop_bits_ldst, // @[execution-unit.scala:90:22]
input [5:0] io_iss_uop_bits_lrs1, // @[execution-unit.scala:90:22]
input [5:0] io_iss_uop_bits_lrs2, // @[execution-unit.scala:90:22]
input [5:0] io_iss_uop_bits_lrs3, // @[execution-unit.scala:90:22]
input [1:0] io_iss_uop_bits_dst_rtype, // @[execution-unit.scala:90:22]
input [1:0] io_iss_uop_bits_lrs1_rtype, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_frs3_en, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_fcn_dw, // @[execution-unit.scala:90:22]
input [4:0] io_iss_uop_bits_fcn_op, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_fp_val, // @[execution-unit.scala:90:22]
input [2:0] io_iss_uop_bits_fp_rm, // @[execution-unit.scala:90:22]
input [1:0] io_iss_uop_bits_fp_typ, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_xcpt_pf_if, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_xcpt_ae_if, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_xcpt_ma_if, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_bp_debug_if, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_bp_xcpt_if, // @[execution-unit.scala:90:22]
input [2:0] io_iss_uop_bits_debug_fsrc, // @[execution-unit.scala:90:22]
input [2:0] io_iss_uop_bits_debug_tsrc, // @[execution-unit.scala:90:22]
input io_arb_irf_reqs_0_ready, // @[execution-unit.scala:106:27]
output io_arb_irf_reqs_0_valid, // @[execution-unit.scala:106:27]
output [6:0] io_arb_irf_reqs_0_bits, // @[execution-unit.scala:106:27]
input io_arb_rebusys_0_valid, // @[execution-unit.scala:107:27]
input [31:0] io_arb_rebusys_0_bits_uop_inst, // @[execution-unit.scala:107:27]
input [31:0] io_arb_rebusys_0_bits_uop_debug_inst, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_is_rvc, // @[execution-unit.scala:107:27]
input [39:0] io_arb_rebusys_0_bits_uop_debug_pc, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_iq_type_0, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_iq_type_1, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_iq_type_2, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_iq_type_3, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_fu_code_0, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_fu_code_1, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_fu_code_2, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_fu_code_3, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_fu_code_4, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_fu_code_5, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_fu_code_6, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_fu_code_7, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_fu_code_8, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_fu_code_9, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_iw_issued, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_iw_issued_partial_agen, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_iw_issued_partial_dgen, // @[execution-unit.scala:107:27]
input [1:0] io_arb_rebusys_0_bits_uop_iw_p1_speculative_child, // @[execution-unit.scala:107:27]
input [1:0] io_arb_rebusys_0_bits_uop_iw_p2_speculative_child, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_iw_p1_bypass_hint, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_iw_p2_bypass_hint, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_iw_p3_bypass_hint, // @[execution-unit.scala:107:27]
input [1:0] io_arb_rebusys_0_bits_uop_dis_col_sel, // @[execution-unit.scala:107:27]
input [11:0] io_arb_rebusys_0_bits_uop_br_mask, // @[execution-unit.scala:107:27]
input [3:0] io_arb_rebusys_0_bits_uop_br_tag, // @[execution-unit.scala:107:27]
input [3:0] io_arb_rebusys_0_bits_uop_br_type, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_is_sfb, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_is_fence, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_is_fencei, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_is_sfence, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_is_amo, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_is_eret, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_is_rocc, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_is_mov, // @[execution-unit.scala:107:27]
input [4:0] io_arb_rebusys_0_bits_uop_ftq_idx, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_edge_inst, // @[execution-unit.scala:107:27]
input [5:0] io_arb_rebusys_0_bits_uop_pc_lob, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_taken, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_imm_rename, // @[execution-unit.scala:107:27]
input [2:0] io_arb_rebusys_0_bits_uop_imm_sel, // @[execution-unit.scala:107:27]
input [4:0] io_arb_rebusys_0_bits_uop_pimm, // @[execution-unit.scala:107:27]
input [19:0] io_arb_rebusys_0_bits_uop_imm_packed, // @[execution-unit.scala:107:27]
input [1:0] io_arb_rebusys_0_bits_uop_op1_sel, // @[execution-unit.scala:107:27]
input [2:0] io_arb_rebusys_0_bits_uop_op2_sel, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_fp_ctrl_ldst, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_fp_ctrl_wen, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_fp_ctrl_ren1, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_fp_ctrl_ren2, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_fp_ctrl_ren3, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_fp_ctrl_swap12, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_fp_ctrl_swap23, // @[execution-unit.scala:107:27]
input [1:0] io_arb_rebusys_0_bits_uop_fp_ctrl_typeTagIn, // @[execution-unit.scala:107:27]
input [1:0] io_arb_rebusys_0_bits_uop_fp_ctrl_typeTagOut, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_fp_ctrl_fromint, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_fp_ctrl_toint, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_fp_ctrl_fastpipe, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_fp_ctrl_fma, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_fp_ctrl_div, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_fp_ctrl_sqrt, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_fp_ctrl_wflags, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_fp_ctrl_vec, // @[execution-unit.scala:107:27]
input [5:0] io_arb_rebusys_0_bits_uop_rob_idx, // @[execution-unit.scala:107:27]
input [3:0] io_arb_rebusys_0_bits_uop_ldq_idx, // @[execution-unit.scala:107:27]
input [3:0] io_arb_rebusys_0_bits_uop_stq_idx, // @[execution-unit.scala:107:27]
input [1:0] io_arb_rebusys_0_bits_uop_rxq_idx, // @[execution-unit.scala:107:27]
input [6:0] io_arb_rebusys_0_bits_uop_pdst, // @[execution-unit.scala:107:27]
input [6:0] io_arb_rebusys_0_bits_uop_prs1, // @[execution-unit.scala:107:27]
input [6:0] io_arb_rebusys_0_bits_uop_prs2, // @[execution-unit.scala:107:27]
input [6:0] io_arb_rebusys_0_bits_uop_prs3, // @[execution-unit.scala:107:27]
input [4:0] io_arb_rebusys_0_bits_uop_ppred, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_prs1_busy, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_prs2_busy, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_prs3_busy, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_ppred_busy, // @[execution-unit.scala:107:27]
input [6:0] io_arb_rebusys_0_bits_uop_stale_pdst, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_exception, // @[execution-unit.scala:107:27]
input [63:0] io_arb_rebusys_0_bits_uop_exc_cause, // @[execution-unit.scala:107:27]
input [4:0] io_arb_rebusys_0_bits_uop_mem_cmd, // @[execution-unit.scala:107:27]
input [1:0] io_arb_rebusys_0_bits_uop_mem_size, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_mem_signed, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_uses_ldq, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_uses_stq, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_is_unique, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_flush_on_commit, // @[execution-unit.scala:107:27]
input [2:0] io_arb_rebusys_0_bits_uop_csr_cmd, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_ldst_is_rs1, // @[execution-unit.scala:107:27]
input [5:0] io_arb_rebusys_0_bits_uop_ldst, // @[execution-unit.scala:107:27]
input [5:0] io_arb_rebusys_0_bits_uop_lrs1, // @[execution-unit.scala:107:27]
input [5:0] io_arb_rebusys_0_bits_uop_lrs2, // @[execution-unit.scala:107:27]
input [5:0] io_arb_rebusys_0_bits_uop_lrs3, // @[execution-unit.scala:107:27]
input [1:0] io_arb_rebusys_0_bits_uop_dst_rtype, // @[execution-unit.scala:107:27]
input [1:0] io_arb_rebusys_0_bits_uop_lrs1_rtype, // @[execution-unit.scala:107:27]
input [1:0] io_arb_rebusys_0_bits_uop_lrs2_rtype, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_frs3_en, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_fcn_dw, // @[execution-unit.scala:107:27]
input [4:0] io_arb_rebusys_0_bits_uop_fcn_op, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_fp_val, // @[execution-unit.scala:107:27]
input [2:0] io_arb_rebusys_0_bits_uop_fp_rm, // @[execution-unit.scala:107:27]
input [1:0] io_arb_rebusys_0_bits_uop_fp_typ, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_xcpt_pf_if, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_xcpt_ae_if, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_xcpt_ma_if, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_bp_debug_if, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_bp_xcpt_if, // @[execution-unit.scala:107:27]
input [2:0] io_arb_rebusys_0_bits_uop_debug_fsrc, // @[execution-unit.scala:107:27]
input [2:0] io_arb_rebusys_0_bits_uop_debug_tsrc, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_bypassable, // @[execution-unit.scala:107:27]
input [1:0] io_arb_rebusys_0_bits_speculative_mask, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_rebusy, // @[execution-unit.scala:107:27]
input [63:0] io_rrd_irf_resps_0, // @[execution-unit.scala:108:31]
input io_rrd_irf_bypasses_0_valid, // @[execution-unit.scala:109:31]
input [31:0] io_rrd_irf_bypasses_0_bits_uop_inst, // @[execution-unit.scala:109:31]
input [31:0] io_rrd_irf_bypasses_0_bits_uop_debug_inst, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_is_rvc, // @[execution-unit.scala:109:31]
input [39:0] io_rrd_irf_bypasses_0_bits_uop_debug_pc, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_iq_type_0, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_iq_type_1, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_iq_type_2, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_iq_type_3, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_fu_code_0, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_fu_code_1, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_fu_code_2, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_fu_code_3, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_fu_code_4, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_fu_code_5, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_fu_code_6, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_fu_code_7, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_fu_code_8, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_fu_code_9, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_iw_issued, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_iw_issued_partial_agen, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_iw_issued_partial_dgen, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_0_bits_uop_iw_p1_speculative_child, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_0_bits_uop_iw_p2_speculative_child, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_iw_p1_bypass_hint, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_iw_p2_bypass_hint, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_iw_p3_bypass_hint, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_0_bits_uop_dis_col_sel, // @[execution-unit.scala:109:31]
input [11:0] io_rrd_irf_bypasses_0_bits_uop_br_mask, // @[execution-unit.scala:109:31]
input [3:0] io_rrd_irf_bypasses_0_bits_uop_br_tag, // @[execution-unit.scala:109:31]
input [3:0] io_rrd_irf_bypasses_0_bits_uop_br_type, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_is_sfb, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_is_fence, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_is_fencei, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_is_sfence, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_is_amo, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_is_eret, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_is_rocc, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_is_mov, // @[execution-unit.scala:109:31]
input [4:0] io_rrd_irf_bypasses_0_bits_uop_ftq_idx, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_edge_inst, // @[execution-unit.scala:109:31]
input [5:0] io_rrd_irf_bypasses_0_bits_uop_pc_lob, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_taken, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_imm_rename, // @[execution-unit.scala:109:31]
input [2:0] io_rrd_irf_bypasses_0_bits_uop_imm_sel, // @[execution-unit.scala:109:31]
input [4:0] io_rrd_irf_bypasses_0_bits_uop_pimm, // @[execution-unit.scala:109:31]
input [19:0] io_rrd_irf_bypasses_0_bits_uop_imm_packed, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_0_bits_uop_op1_sel, // @[execution-unit.scala:109:31]
input [2:0] io_rrd_irf_bypasses_0_bits_uop_op2_sel, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_ldst, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_wen, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_ren1, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_ren2, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_ren3, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_swap12, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_swap23, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_typeTagIn, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_typeTagOut, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_fromint, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_toint, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_fastpipe, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_fma, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_div, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_sqrt, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_wflags, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_vec, // @[execution-unit.scala:109:31]
input [5:0] io_rrd_irf_bypasses_0_bits_uop_rob_idx, // @[execution-unit.scala:109:31]
input [3:0] io_rrd_irf_bypasses_0_bits_uop_ldq_idx, // @[execution-unit.scala:109:31]
input [3:0] io_rrd_irf_bypasses_0_bits_uop_stq_idx, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_0_bits_uop_rxq_idx, // @[execution-unit.scala:109:31]
input [6:0] io_rrd_irf_bypasses_0_bits_uop_pdst, // @[execution-unit.scala:109:31]
input [6:0] io_rrd_irf_bypasses_0_bits_uop_prs1, // @[execution-unit.scala:109:31]
input [6:0] io_rrd_irf_bypasses_0_bits_uop_prs2, // @[execution-unit.scala:109:31]
input [6:0] io_rrd_irf_bypasses_0_bits_uop_prs3, // @[execution-unit.scala:109:31]
input [4:0] io_rrd_irf_bypasses_0_bits_uop_ppred, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_prs1_busy, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_prs2_busy, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_prs3_busy, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_ppred_busy, // @[execution-unit.scala:109:31]
input [6:0] io_rrd_irf_bypasses_0_bits_uop_stale_pdst, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_exception, // @[execution-unit.scala:109:31]
input [63:0] io_rrd_irf_bypasses_0_bits_uop_exc_cause, // @[execution-unit.scala:109:31]
input [4:0] io_rrd_irf_bypasses_0_bits_uop_mem_cmd, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_0_bits_uop_mem_size, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_mem_signed, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_uses_ldq, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_uses_stq, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_is_unique, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_flush_on_commit, // @[execution-unit.scala:109:31]
input [2:0] io_rrd_irf_bypasses_0_bits_uop_csr_cmd, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_ldst_is_rs1, // @[execution-unit.scala:109:31]
input [5:0] io_rrd_irf_bypasses_0_bits_uop_ldst, // @[execution-unit.scala:109:31]
input [5:0] io_rrd_irf_bypasses_0_bits_uop_lrs1, // @[execution-unit.scala:109:31]
input [5:0] io_rrd_irf_bypasses_0_bits_uop_lrs2, // @[execution-unit.scala:109:31]
input [5:0] io_rrd_irf_bypasses_0_bits_uop_lrs3, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_0_bits_uop_dst_rtype, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_0_bits_uop_lrs1_rtype, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_0_bits_uop_lrs2_rtype, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_frs3_en, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_fcn_dw, // @[execution-unit.scala:109:31]
input [4:0] io_rrd_irf_bypasses_0_bits_uop_fcn_op, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_fp_val, // @[execution-unit.scala:109:31]
input [2:0] io_rrd_irf_bypasses_0_bits_uop_fp_rm, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_0_bits_uop_fp_typ, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_xcpt_pf_if, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_xcpt_ae_if, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_xcpt_ma_if, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_bp_debug_if, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_bp_xcpt_if, // @[execution-unit.scala:109:31]
input [2:0] io_rrd_irf_bypasses_0_bits_uop_debug_fsrc, // @[execution-unit.scala:109:31]
input [2:0] io_rrd_irf_bypasses_0_bits_uop_debug_tsrc, // @[execution-unit.scala:109:31]
input [63:0] io_rrd_irf_bypasses_0_bits_data, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_predicated, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_fflags_valid, // @[execution-unit.scala:109:31]
input [4:0] io_rrd_irf_bypasses_0_bits_fflags_bits, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_valid, // @[execution-unit.scala:109:31]
input [31:0] io_rrd_irf_bypasses_1_bits_uop_inst, // @[execution-unit.scala:109:31]
input [31:0] io_rrd_irf_bypasses_1_bits_uop_debug_inst, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_is_rvc, // @[execution-unit.scala:109:31]
input [39:0] io_rrd_irf_bypasses_1_bits_uop_debug_pc, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_iq_type_0, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_iq_type_1, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_iq_type_2, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_iq_type_3, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_fu_code_0, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_fu_code_1, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_fu_code_2, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_fu_code_3, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_fu_code_4, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_fu_code_5, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_fu_code_6, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_fu_code_7, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_fu_code_8, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_fu_code_9, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_iw_issued, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_iw_issued_partial_agen, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_iw_issued_partial_dgen, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_1_bits_uop_iw_p1_speculative_child, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_1_bits_uop_iw_p2_speculative_child, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_iw_p1_bypass_hint, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_iw_p2_bypass_hint, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_iw_p3_bypass_hint, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_1_bits_uop_dis_col_sel, // @[execution-unit.scala:109:31]
input [11:0] io_rrd_irf_bypasses_1_bits_uop_br_mask, // @[execution-unit.scala:109:31]
input [3:0] io_rrd_irf_bypasses_1_bits_uop_br_tag, // @[execution-unit.scala:109:31]
input [3:0] io_rrd_irf_bypasses_1_bits_uop_br_type, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_is_sfb, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_is_fence, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_is_fencei, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_is_sfence, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_is_amo, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_is_eret, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_is_rocc, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_is_mov, // @[execution-unit.scala:109:31]
input [4:0] io_rrd_irf_bypasses_1_bits_uop_ftq_idx, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_edge_inst, // @[execution-unit.scala:109:31]
input [5:0] io_rrd_irf_bypasses_1_bits_uop_pc_lob, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_taken, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_imm_rename, // @[execution-unit.scala:109:31]
input [2:0] io_rrd_irf_bypasses_1_bits_uop_imm_sel, // @[execution-unit.scala:109:31]
input [4:0] io_rrd_irf_bypasses_1_bits_uop_pimm, // @[execution-unit.scala:109:31]
input [19:0] io_rrd_irf_bypasses_1_bits_uop_imm_packed, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_1_bits_uop_op1_sel, // @[execution-unit.scala:109:31]
input [2:0] io_rrd_irf_bypasses_1_bits_uop_op2_sel, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_ldst, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_wen, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_ren1, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_ren2, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_ren3, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_swap12, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_swap23, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_typeTagIn, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_typeTagOut, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_fromint, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_toint, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_fastpipe, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_fma, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_div, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_sqrt, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_wflags, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_vec, // @[execution-unit.scala:109:31]
input [5:0] io_rrd_irf_bypasses_1_bits_uop_rob_idx, // @[execution-unit.scala:109:31]
input [3:0] io_rrd_irf_bypasses_1_bits_uop_ldq_idx, // @[execution-unit.scala:109:31]
input [3:0] io_rrd_irf_bypasses_1_bits_uop_stq_idx, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_1_bits_uop_rxq_idx, // @[execution-unit.scala:109:31]
input [6:0] io_rrd_irf_bypasses_1_bits_uop_pdst, // @[execution-unit.scala:109:31]
input [6:0] io_rrd_irf_bypasses_1_bits_uop_prs1, // @[execution-unit.scala:109:31]
input [6:0] io_rrd_irf_bypasses_1_bits_uop_prs2, // @[execution-unit.scala:109:31]
input [6:0] io_rrd_irf_bypasses_1_bits_uop_prs3, // @[execution-unit.scala:109:31]
input [4:0] io_rrd_irf_bypasses_1_bits_uop_ppred, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_prs1_busy, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_prs2_busy, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_prs3_busy, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_ppred_busy, // @[execution-unit.scala:109:31]
input [6:0] io_rrd_irf_bypasses_1_bits_uop_stale_pdst, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_exception, // @[execution-unit.scala:109:31]
input [63:0] io_rrd_irf_bypasses_1_bits_uop_exc_cause, // @[execution-unit.scala:109:31]
input [4:0] io_rrd_irf_bypasses_1_bits_uop_mem_cmd, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_1_bits_uop_mem_size, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_mem_signed, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_uses_ldq, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_uses_stq, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_is_unique, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_flush_on_commit, // @[execution-unit.scala:109:31]
input [2:0] io_rrd_irf_bypasses_1_bits_uop_csr_cmd, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_ldst_is_rs1, // @[execution-unit.scala:109:31]
input [5:0] io_rrd_irf_bypasses_1_bits_uop_ldst, // @[execution-unit.scala:109:31]
input [5:0] io_rrd_irf_bypasses_1_bits_uop_lrs1, // @[execution-unit.scala:109:31]
input [5:0] io_rrd_irf_bypasses_1_bits_uop_lrs2, // @[execution-unit.scala:109:31]
input [5:0] io_rrd_irf_bypasses_1_bits_uop_lrs3, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_1_bits_uop_dst_rtype, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_1_bits_uop_lrs1_rtype, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_1_bits_uop_lrs2_rtype, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_frs3_en, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_fcn_dw, // @[execution-unit.scala:109:31]
input [4:0] io_rrd_irf_bypasses_1_bits_uop_fcn_op, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_fp_val, // @[execution-unit.scala:109:31]
input [2:0] io_rrd_irf_bypasses_1_bits_uop_fp_rm, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_1_bits_uop_fp_typ, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_xcpt_pf_if, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_xcpt_ae_if, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_xcpt_ma_if, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_bp_debug_if, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_bp_xcpt_if, // @[execution-unit.scala:109:31]
input [2:0] io_rrd_irf_bypasses_1_bits_uop_debug_fsrc, // @[execution-unit.scala:109:31]
input [2:0] io_rrd_irf_bypasses_1_bits_uop_debug_tsrc, // @[execution-unit.scala:109:31]
input [63:0] io_rrd_irf_bypasses_1_bits_data, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_predicated, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_valid, // @[execution-unit.scala:109:31]
input [31:0] io_rrd_irf_bypasses_2_bits_uop_inst, // @[execution-unit.scala:109:31]
input [31:0] io_rrd_irf_bypasses_2_bits_uop_debug_inst, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_is_rvc, // @[execution-unit.scala:109:31]
input [39:0] io_rrd_irf_bypasses_2_bits_uop_debug_pc, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_iq_type_0, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_iq_type_1, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_iq_type_2, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_iq_type_3, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_fu_code_0, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_fu_code_1, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_fu_code_2, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_fu_code_3, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_fu_code_4, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_fu_code_5, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_fu_code_6, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_fu_code_7, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_fu_code_8, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_fu_code_9, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_iw_issued, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_iw_issued_partial_agen, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_iw_issued_partial_dgen, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_2_bits_uop_iw_p1_speculative_child, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_2_bits_uop_iw_p2_speculative_child, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_iw_p1_bypass_hint, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_iw_p2_bypass_hint, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_iw_p3_bypass_hint, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_2_bits_uop_dis_col_sel, // @[execution-unit.scala:109:31]
input [11:0] io_rrd_irf_bypasses_2_bits_uop_br_mask, // @[execution-unit.scala:109:31]
input [3:0] io_rrd_irf_bypasses_2_bits_uop_br_tag, // @[execution-unit.scala:109:31]
input [3:0] io_rrd_irf_bypasses_2_bits_uop_br_type, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_is_sfb, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_is_fence, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_is_fencei, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_is_sfence, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_is_amo, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_is_eret, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_is_rocc, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_is_mov, // @[execution-unit.scala:109:31]
input [4:0] io_rrd_irf_bypasses_2_bits_uop_ftq_idx, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_edge_inst, // @[execution-unit.scala:109:31]
input [5:0] io_rrd_irf_bypasses_2_bits_uop_pc_lob, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_taken, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_imm_rename, // @[execution-unit.scala:109:31]
input [2:0] io_rrd_irf_bypasses_2_bits_uop_imm_sel, // @[execution-unit.scala:109:31]
input [4:0] io_rrd_irf_bypasses_2_bits_uop_pimm, // @[execution-unit.scala:109:31]
input [19:0] io_rrd_irf_bypasses_2_bits_uop_imm_packed, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_2_bits_uop_op1_sel, // @[execution-unit.scala:109:31]
input [2:0] io_rrd_irf_bypasses_2_bits_uop_op2_sel, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_ldst, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_wen, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_ren1, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_ren2, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_ren3, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_swap12, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_swap23, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_typeTagIn, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_typeTagOut, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_fromint, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_toint, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_fastpipe, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_fma, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_div, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_sqrt, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_wflags, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_vec, // @[execution-unit.scala:109:31]
input [5:0] io_rrd_irf_bypasses_2_bits_uop_rob_idx, // @[execution-unit.scala:109:31]
input [3:0] io_rrd_irf_bypasses_2_bits_uop_ldq_idx, // @[execution-unit.scala:109:31]
input [3:0] io_rrd_irf_bypasses_2_bits_uop_stq_idx, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_2_bits_uop_rxq_idx, // @[execution-unit.scala:109:31]
input [6:0] io_rrd_irf_bypasses_2_bits_uop_pdst, // @[execution-unit.scala:109:31]
input [6:0] io_rrd_irf_bypasses_2_bits_uop_prs1, // @[execution-unit.scala:109:31]
input [6:0] io_rrd_irf_bypasses_2_bits_uop_prs2, // @[execution-unit.scala:109:31]
input [6:0] io_rrd_irf_bypasses_2_bits_uop_prs3, // @[execution-unit.scala:109:31]
input [4:0] io_rrd_irf_bypasses_2_bits_uop_ppred, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_prs1_busy, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_prs2_busy, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_prs3_busy, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_ppred_busy, // @[execution-unit.scala:109:31]
input [6:0] io_rrd_irf_bypasses_2_bits_uop_stale_pdst, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_exception, // @[execution-unit.scala:109:31]
input [63:0] io_rrd_irf_bypasses_2_bits_uop_exc_cause, // @[execution-unit.scala:109:31]
input [4:0] io_rrd_irf_bypasses_2_bits_uop_mem_cmd, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_2_bits_uop_mem_size, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_mem_signed, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_uses_ldq, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_uses_stq, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_is_unique, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_flush_on_commit, // @[execution-unit.scala:109:31]
input [2:0] io_rrd_irf_bypasses_2_bits_uop_csr_cmd, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_ldst_is_rs1, // @[execution-unit.scala:109:31]
input [5:0] io_rrd_irf_bypasses_2_bits_uop_ldst, // @[execution-unit.scala:109:31]
input [5:0] io_rrd_irf_bypasses_2_bits_uop_lrs1, // @[execution-unit.scala:109:31]
input [5:0] io_rrd_irf_bypasses_2_bits_uop_lrs2, // @[execution-unit.scala:109:31]
input [5:0] io_rrd_irf_bypasses_2_bits_uop_lrs3, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_2_bits_uop_dst_rtype, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_2_bits_uop_lrs1_rtype, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_2_bits_uop_lrs2_rtype, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_frs3_en, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_fcn_dw, // @[execution-unit.scala:109:31]
input [4:0] io_rrd_irf_bypasses_2_bits_uop_fcn_op, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_fp_val, // @[execution-unit.scala:109:31]
input [2:0] io_rrd_irf_bypasses_2_bits_uop_fp_rm, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_2_bits_uop_fp_typ, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_xcpt_pf_if, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_xcpt_ae_if, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_xcpt_ma_if, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_bp_debug_if, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_bp_xcpt_if, // @[execution-unit.scala:109:31]
input [2:0] io_rrd_irf_bypasses_2_bits_uop_debug_fsrc, // @[execution-unit.scala:109:31]
input [2:0] io_rrd_irf_bypasses_2_bits_uop_debug_tsrc, // @[execution-unit.scala:109:31]
input [63:0] io_rrd_irf_bypasses_2_bits_data, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_predicated, // @[execution-unit.scala:109:31]
output io_arb_immrf_req_valid, // @[execution-unit.scala:151:31]
output [4:0] io_arb_immrf_req_bits, // @[execution-unit.scala:151:31]
input [63:0] io_rrd_immrf_resp, // @[execution-unit.scala:153:31]
output io_rrd_immrf_wakeup_valid, // @[execution-unit.scala:154:31]
output [31:0] io_rrd_immrf_wakeup_bits_uop_inst, // @[execution-unit.scala:154:31]
output [31:0] io_rrd_immrf_wakeup_bits_uop_debug_inst, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_is_rvc, // @[execution-unit.scala:154:31]
output [39:0] io_rrd_immrf_wakeup_bits_uop_debug_pc, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_iq_type_0, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_iq_type_1, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_iq_type_2, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_iq_type_3, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_fu_code_0, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_fu_code_1, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_fu_code_2, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_fu_code_3, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_fu_code_4, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_fu_code_5, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_fu_code_6, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_fu_code_7, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_fu_code_8, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_fu_code_9, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_iw_issued, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_iw_issued_partial_agen, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_iw_issued_partial_dgen, // @[execution-unit.scala:154:31]
output [1:0] io_rrd_immrf_wakeup_bits_uop_iw_p1_speculative_child, // @[execution-unit.scala:154:31]
output [1:0] io_rrd_immrf_wakeup_bits_uop_iw_p2_speculative_child, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_iw_p1_bypass_hint, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_iw_p2_bypass_hint, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_iw_p3_bypass_hint, // @[execution-unit.scala:154:31]
output [1:0] io_rrd_immrf_wakeup_bits_uop_dis_col_sel, // @[execution-unit.scala:154:31]
output [11:0] io_rrd_immrf_wakeup_bits_uop_br_mask, // @[execution-unit.scala:154:31]
output [3:0] io_rrd_immrf_wakeup_bits_uop_br_tag, // @[execution-unit.scala:154:31]
output [3:0] io_rrd_immrf_wakeup_bits_uop_br_type, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_is_sfb, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_is_fence, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_is_fencei, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_is_sfence, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_is_amo, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_is_eret, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_is_rocc, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_is_mov, // @[execution-unit.scala:154:31]
output [4:0] io_rrd_immrf_wakeup_bits_uop_ftq_idx, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_edge_inst, // @[execution-unit.scala:154:31]
output [5:0] io_rrd_immrf_wakeup_bits_uop_pc_lob, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_taken, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_imm_rename, // @[execution-unit.scala:154:31]
output [2:0] io_rrd_immrf_wakeup_bits_uop_imm_sel, // @[execution-unit.scala:154:31]
output [4:0] io_rrd_immrf_wakeup_bits_uop_pimm, // @[execution-unit.scala:154:31]
output [19:0] io_rrd_immrf_wakeup_bits_uop_imm_packed, // @[execution-unit.scala:154:31]
output [1:0] io_rrd_immrf_wakeup_bits_uop_op1_sel, // @[execution-unit.scala:154:31]
output [2:0] io_rrd_immrf_wakeup_bits_uop_op2_sel, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_ldst, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_wen, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_ren1, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_ren2, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_ren3, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_swap12, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_swap23, // @[execution-unit.scala:154:31]
output [1:0] io_rrd_immrf_wakeup_bits_uop_fp_ctrl_typeTagIn, // @[execution-unit.scala:154:31]
output [1:0] io_rrd_immrf_wakeup_bits_uop_fp_ctrl_typeTagOut, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_fromint, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_toint, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_fastpipe, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_fma, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_div, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_sqrt, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_wflags, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_vec, // @[execution-unit.scala:154:31]
output [5:0] io_rrd_immrf_wakeup_bits_uop_rob_idx, // @[execution-unit.scala:154:31]
output [3:0] io_rrd_immrf_wakeup_bits_uop_ldq_idx, // @[execution-unit.scala:154:31]
output [3:0] io_rrd_immrf_wakeup_bits_uop_stq_idx, // @[execution-unit.scala:154:31]
output [1:0] io_rrd_immrf_wakeup_bits_uop_rxq_idx, // @[execution-unit.scala:154:31]
output [6:0] io_rrd_immrf_wakeup_bits_uop_pdst, // @[execution-unit.scala:154:31]
output [6:0] io_rrd_immrf_wakeup_bits_uop_prs1, // @[execution-unit.scala:154:31]
output [6:0] io_rrd_immrf_wakeup_bits_uop_prs2, // @[execution-unit.scala:154:31]
output [6:0] io_rrd_immrf_wakeup_bits_uop_prs3, // @[execution-unit.scala:154:31]
output [4:0] io_rrd_immrf_wakeup_bits_uop_ppred, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_prs1_busy, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_prs2_busy, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_prs3_busy, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_ppred_busy, // @[execution-unit.scala:154:31]
output [6:0] io_rrd_immrf_wakeup_bits_uop_stale_pdst, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_exception, // @[execution-unit.scala:154:31]
output [63:0] io_rrd_immrf_wakeup_bits_uop_exc_cause, // @[execution-unit.scala:154:31]
output [4:0] io_rrd_immrf_wakeup_bits_uop_mem_cmd, // @[execution-unit.scala:154:31]
output [1:0] io_rrd_immrf_wakeup_bits_uop_mem_size, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_mem_signed, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_uses_ldq, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_uses_stq, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_is_unique, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_flush_on_commit, // @[execution-unit.scala:154:31]
output [2:0] io_rrd_immrf_wakeup_bits_uop_csr_cmd, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_ldst_is_rs1, // @[execution-unit.scala:154:31]
output [5:0] io_rrd_immrf_wakeup_bits_uop_ldst, // @[execution-unit.scala:154:31]
output [5:0] io_rrd_immrf_wakeup_bits_uop_lrs1, // @[execution-unit.scala:154:31]
output [5:0] io_rrd_immrf_wakeup_bits_uop_lrs2, // @[execution-unit.scala:154:31]
output [5:0] io_rrd_immrf_wakeup_bits_uop_lrs3, // @[execution-unit.scala:154:31]
output [1:0] io_rrd_immrf_wakeup_bits_uop_dst_rtype, // @[execution-unit.scala:154:31]
output [1:0] io_rrd_immrf_wakeup_bits_uop_lrs1_rtype, // @[execution-unit.scala:154:31]
output [1:0] io_rrd_immrf_wakeup_bits_uop_lrs2_rtype, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_frs3_en, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_fcn_dw, // @[execution-unit.scala:154:31]
output [4:0] io_rrd_immrf_wakeup_bits_uop_fcn_op, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_fp_val, // @[execution-unit.scala:154:31]
output [2:0] io_rrd_immrf_wakeup_bits_uop_fp_rm, // @[execution-unit.scala:154:31]
output [1:0] io_rrd_immrf_wakeup_bits_uop_fp_typ, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_xcpt_pf_if, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_xcpt_ae_if, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_xcpt_ma_if, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_bp_debug_if, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_bp_xcpt_if, // @[execution-unit.scala:154:31]
output [2:0] io_rrd_immrf_wakeup_bits_uop_debug_fsrc, // @[execution-unit.scala:154:31]
output [2:0] io_rrd_immrf_wakeup_bits_uop_debug_tsrc, // @[execution-unit.scala:154:31]
output io_squash_iss, // @[execution-unit.scala:264:25]
output io_dgen_valid, // @[execution-unit.scala:317:18]
output [31:0] io_dgen_bits_uop_inst, // @[execution-unit.scala:317:18]
output [31:0] io_dgen_bits_uop_debug_inst, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_is_rvc, // @[execution-unit.scala:317:18]
output [39:0] io_dgen_bits_uop_debug_pc, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_iq_type_0, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_iq_type_1, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_iq_type_2, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_iq_type_3, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_fu_code_0, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_fu_code_1, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_fu_code_2, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_fu_code_3, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_fu_code_4, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_fu_code_5, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_fu_code_6, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_fu_code_7, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_fu_code_8, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_fu_code_9, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_iw_issued, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_iw_issued_partial_agen, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_iw_issued_partial_dgen, // @[execution-unit.scala:317:18]
output [1:0] io_dgen_bits_uop_iw_p1_speculative_child, // @[execution-unit.scala:317:18]
output [1:0] io_dgen_bits_uop_iw_p2_speculative_child, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_iw_p1_bypass_hint, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_iw_p2_bypass_hint, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_iw_p3_bypass_hint, // @[execution-unit.scala:317:18]
output [1:0] io_dgen_bits_uop_dis_col_sel, // @[execution-unit.scala:317:18]
output [11:0] io_dgen_bits_uop_br_mask, // @[execution-unit.scala:317:18]
output [3:0] io_dgen_bits_uop_br_tag, // @[execution-unit.scala:317:18]
output [3:0] io_dgen_bits_uop_br_type, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_is_sfb, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_is_fence, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_is_fencei, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_is_sfence, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_is_amo, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_is_eret, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_is_rocc, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_is_mov, // @[execution-unit.scala:317:18]
output [4:0] io_dgen_bits_uop_ftq_idx, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_edge_inst, // @[execution-unit.scala:317:18]
output [5:0] io_dgen_bits_uop_pc_lob, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_taken, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_imm_rename, // @[execution-unit.scala:317:18]
output [2:0] io_dgen_bits_uop_imm_sel, // @[execution-unit.scala:317:18]
output [4:0] io_dgen_bits_uop_pimm, // @[execution-unit.scala:317:18]
output [19:0] io_dgen_bits_uop_imm_packed, // @[execution-unit.scala:317:18]
output [1:0] io_dgen_bits_uop_op1_sel, // @[execution-unit.scala:317:18]
output [2:0] io_dgen_bits_uop_op2_sel, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_fp_ctrl_ldst, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_fp_ctrl_wen, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_fp_ctrl_ren1, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_fp_ctrl_ren2, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_fp_ctrl_ren3, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_fp_ctrl_swap12, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_fp_ctrl_swap23, // @[execution-unit.scala:317:18]
output [1:0] io_dgen_bits_uop_fp_ctrl_typeTagIn, // @[execution-unit.scala:317:18]
output [1:0] io_dgen_bits_uop_fp_ctrl_typeTagOut, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_fp_ctrl_fromint, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_fp_ctrl_toint, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_fp_ctrl_fastpipe, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_fp_ctrl_fma, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_fp_ctrl_div, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_fp_ctrl_sqrt, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_fp_ctrl_wflags, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_fp_ctrl_vec, // @[execution-unit.scala:317:18]
output [5:0] io_dgen_bits_uop_rob_idx, // @[execution-unit.scala:317:18]
output [3:0] io_dgen_bits_uop_ldq_idx, // @[execution-unit.scala:317:18]
output [3:0] io_dgen_bits_uop_stq_idx, // @[execution-unit.scala:317:18]
output [1:0] io_dgen_bits_uop_rxq_idx, // @[execution-unit.scala:317:18]
output [6:0] io_dgen_bits_uop_pdst, // @[execution-unit.scala:317:18]
output [6:0] io_dgen_bits_uop_prs1, // @[execution-unit.scala:317:18]
output [6:0] io_dgen_bits_uop_prs2, // @[execution-unit.scala:317:18]
output [6:0] io_dgen_bits_uop_prs3, // @[execution-unit.scala:317:18]
output [4:0] io_dgen_bits_uop_ppred, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_prs1_busy, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_prs2_busy, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_prs3_busy, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_ppred_busy, // @[execution-unit.scala:317:18]
output [6:0] io_dgen_bits_uop_stale_pdst, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_exception, // @[execution-unit.scala:317:18]
output [63:0] io_dgen_bits_uop_exc_cause, // @[execution-unit.scala:317:18]
output [4:0] io_dgen_bits_uop_mem_cmd, // @[execution-unit.scala:317:18]
output [1:0] io_dgen_bits_uop_mem_size, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_mem_signed, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_uses_ldq, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_uses_stq, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_is_unique, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_flush_on_commit, // @[execution-unit.scala:317:18]
output [2:0] io_dgen_bits_uop_csr_cmd, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_ldst_is_rs1, // @[execution-unit.scala:317:18]
output [5:0] io_dgen_bits_uop_ldst, // @[execution-unit.scala:317:18]
output [5:0] io_dgen_bits_uop_lrs1, // @[execution-unit.scala:317:18]
output [5:0] io_dgen_bits_uop_lrs2, // @[execution-unit.scala:317:18]
output [5:0] io_dgen_bits_uop_lrs3, // @[execution-unit.scala:317:18]
output [1:0] io_dgen_bits_uop_dst_rtype, // @[execution-unit.scala:317:18]
output [1:0] io_dgen_bits_uop_lrs1_rtype, // @[execution-unit.scala:317:18]
output [1:0] io_dgen_bits_uop_lrs2_rtype, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_frs3_en, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_fcn_dw, // @[execution-unit.scala:317:18]
output [4:0] io_dgen_bits_uop_fcn_op, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_fp_val, // @[execution-unit.scala:317:18]
output [2:0] io_dgen_bits_uop_fp_rm, // @[execution-unit.scala:317:18]
output [1:0] io_dgen_bits_uop_fp_typ, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_xcpt_pf_if, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_xcpt_ae_if, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_xcpt_ma_if, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_bp_debug_if, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_bp_xcpt_if, // @[execution-unit.scala:317:18]
output [2:0] io_dgen_bits_uop_debug_fsrc, // @[execution-unit.scala:317:18]
output [2:0] io_dgen_bits_uop_debug_tsrc, // @[execution-unit.scala:317:18]
output [63:0] io_dgen_bits_data // @[execution-unit.scala:317:18]
);
reg [63:0] exe_rs1_data; // @[execution-unit.scala:133:25]
reg [2:0] exe_uop_bits_debug_tsrc; // @[execution-unit.scala:98:20]
reg [2:0] exe_uop_bits_debug_fsrc; // @[execution-unit.scala:98:20]
reg exe_uop_bits_bp_xcpt_if; // @[execution-unit.scala:98:20]
reg exe_uop_bits_bp_debug_if; // @[execution-unit.scala:98:20]
reg exe_uop_bits_xcpt_ma_if; // @[execution-unit.scala:98:20]
reg exe_uop_bits_xcpt_ae_if; // @[execution-unit.scala:98:20]
reg exe_uop_bits_xcpt_pf_if; // @[execution-unit.scala:98:20]
reg [1:0] exe_uop_bits_fp_typ; // @[execution-unit.scala:98:20]
reg [2:0] exe_uop_bits_fp_rm; // @[execution-unit.scala:98:20]
reg exe_uop_bits_fp_val; // @[execution-unit.scala:98:20]
reg [4:0] exe_uop_bits_fcn_op; // @[execution-unit.scala:98:20]
reg exe_uop_bits_fcn_dw; // @[execution-unit.scala:98:20]
reg exe_uop_bits_frs3_en; // @[execution-unit.scala:98:20]
reg [1:0] exe_uop_bits_lrs2_rtype; // @[execution-unit.scala:98:20]
reg [1:0] exe_uop_bits_lrs1_rtype; // @[execution-unit.scala:98:20]
reg [1:0] exe_uop_bits_dst_rtype; // @[execution-unit.scala:98:20]
reg [5:0] exe_uop_bits_lrs3; // @[execution-unit.scala:98:20]
reg [5:0] exe_uop_bits_lrs2; // @[execution-unit.scala:98:20]
reg [5:0] exe_uop_bits_lrs1; // @[execution-unit.scala:98:20]
reg [5:0] exe_uop_bits_ldst; // @[execution-unit.scala:98:20]
reg exe_uop_bits_ldst_is_rs1; // @[execution-unit.scala:98:20]
reg [2:0] exe_uop_bits_csr_cmd; // @[execution-unit.scala:98:20]
reg exe_uop_bits_flush_on_commit; // @[execution-unit.scala:98:20]
reg exe_uop_bits_is_unique; // @[execution-unit.scala:98:20]
reg exe_uop_bits_uses_stq; // @[execution-unit.scala:98:20]
reg exe_uop_bits_uses_ldq; // @[execution-unit.scala:98:20]
reg exe_uop_bits_mem_signed; // @[execution-unit.scala:98:20]
reg [1:0] exe_uop_bits_mem_size; // @[execution-unit.scala:98:20]
reg [4:0] exe_uop_bits_mem_cmd; // @[execution-unit.scala:98:20]
reg [63:0] exe_uop_bits_exc_cause; // @[execution-unit.scala:98:20]
reg exe_uop_bits_exception; // @[execution-unit.scala:98:20]
reg [6:0] exe_uop_bits_stale_pdst; // @[execution-unit.scala:98:20]
reg exe_uop_bits_ppred_busy; // @[execution-unit.scala:98:20]
reg exe_uop_bits_prs3_busy; // @[execution-unit.scala:98:20]
reg exe_uop_bits_prs2_busy; // @[execution-unit.scala:98:20]
reg exe_uop_bits_prs1_busy; // @[execution-unit.scala:98:20]
reg [4:0] exe_uop_bits_ppred; // @[execution-unit.scala:98:20]
reg [6:0] exe_uop_bits_prs3; // @[execution-unit.scala:98:20]
reg [6:0] exe_uop_bits_prs2; // @[execution-unit.scala:98:20]
reg [6:0] exe_uop_bits_prs1; // @[execution-unit.scala:98:20]
reg [6:0] exe_uop_bits_pdst; // @[execution-unit.scala:98:20]
reg [1:0] exe_uop_bits_rxq_idx; // @[execution-unit.scala:98:20]
reg [3:0] exe_uop_bits_stq_idx; // @[execution-unit.scala:98:20]
reg [3:0] exe_uop_bits_ldq_idx; // @[execution-unit.scala:98:20]
reg [5:0] exe_uop_bits_rob_idx; // @[execution-unit.scala:98:20]
reg exe_uop_bits_fp_ctrl_vec; // @[execution-unit.scala:98:20]
reg exe_uop_bits_fp_ctrl_wflags; // @[execution-unit.scala:98:20]
reg exe_uop_bits_fp_ctrl_sqrt; // @[execution-unit.scala:98:20]
reg exe_uop_bits_fp_ctrl_div; // @[execution-unit.scala:98:20]
reg exe_uop_bits_fp_ctrl_fma; // @[execution-unit.scala:98:20]
reg exe_uop_bits_fp_ctrl_fastpipe; // @[execution-unit.scala:98:20]
reg exe_uop_bits_fp_ctrl_toint; // @[execution-unit.scala:98:20]
reg exe_uop_bits_fp_ctrl_fromint; // @[execution-unit.scala:98:20]
reg [1:0] exe_uop_bits_fp_ctrl_typeTagOut; // @[execution-unit.scala:98:20]
reg [1:0] exe_uop_bits_fp_ctrl_typeTagIn; // @[execution-unit.scala:98:20]
reg exe_uop_bits_fp_ctrl_swap23; // @[execution-unit.scala:98:20]
reg exe_uop_bits_fp_ctrl_swap12; // @[execution-unit.scala:98:20]
reg exe_uop_bits_fp_ctrl_ren3; // @[execution-unit.scala:98:20]
reg exe_uop_bits_fp_ctrl_ren2; // @[execution-unit.scala:98:20]
reg exe_uop_bits_fp_ctrl_ren1; // @[execution-unit.scala:98:20]
reg exe_uop_bits_fp_ctrl_wen; // @[execution-unit.scala:98:20]
reg exe_uop_bits_fp_ctrl_ldst; // @[execution-unit.scala:98:20]
reg [2:0] exe_uop_bits_op2_sel; // @[execution-unit.scala:98:20]
reg [1:0] exe_uop_bits_op1_sel; // @[execution-unit.scala:98:20]
reg [19:0] exe_uop_bits_imm_packed; // @[execution-unit.scala:98:20]
reg [4:0] exe_uop_bits_pimm; // @[execution-unit.scala:98:20]
reg [2:0] exe_uop_bits_imm_sel; // @[execution-unit.scala:98:20]
reg exe_uop_bits_imm_rename; // @[execution-unit.scala:98:20]
reg exe_uop_bits_taken; // @[execution-unit.scala:98:20]
reg [5:0] exe_uop_bits_pc_lob; // @[execution-unit.scala:98:20]
reg exe_uop_bits_edge_inst; // @[execution-unit.scala:98:20]
reg [4:0] exe_uop_bits_ftq_idx; // @[execution-unit.scala:98:20]
reg exe_uop_bits_is_mov; // @[execution-unit.scala:98:20]
reg exe_uop_bits_is_rocc; // @[execution-unit.scala:98:20]
reg exe_uop_bits_is_sys_pc2epc; // @[execution-unit.scala:98:20]
reg exe_uop_bits_is_eret; // @[execution-unit.scala:98:20]
reg exe_uop_bits_is_amo; // @[execution-unit.scala:98:20]
reg exe_uop_bits_is_sfence; // @[execution-unit.scala:98:20]
reg exe_uop_bits_is_fencei; // @[execution-unit.scala:98:20]
reg exe_uop_bits_is_fence; // @[execution-unit.scala:98:20]
reg exe_uop_bits_is_sfb; // @[execution-unit.scala:98:20]
reg [3:0] exe_uop_bits_br_type; // @[execution-unit.scala:98:20]
reg [3:0] exe_uop_bits_br_tag; // @[execution-unit.scala:98:20]
reg [11:0] exe_uop_bits_br_mask; // @[execution-unit.scala:98:20]
reg [1:0] exe_uop_bits_dis_col_sel; // @[execution-unit.scala:98:20]
reg exe_uop_bits_iw_p3_bypass_hint; // @[execution-unit.scala:98:20]
reg exe_uop_bits_iw_p2_bypass_hint; // @[execution-unit.scala:98:20]
reg exe_uop_bits_iw_p1_bypass_hint; // @[execution-unit.scala:98:20]
reg [1:0] exe_uop_bits_iw_p2_speculative_child; // @[execution-unit.scala:98:20]
reg [1:0] exe_uop_bits_iw_p1_speculative_child; // @[execution-unit.scala:98:20]
reg exe_uop_bits_iw_issued_partial_dgen; // @[execution-unit.scala:98:20]
reg exe_uop_bits_iw_issued_partial_agen; // @[execution-unit.scala:98:20]
reg exe_uop_bits_iw_issued; // @[execution-unit.scala:98:20]
reg exe_uop_bits_fu_code_9; // @[execution-unit.scala:98:20]
reg exe_uop_bits_fu_code_8; // @[execution-unit.scala:98:20]
reg exe_uop_bits_fu_code_7; // @[execution-unit.scala:98:20]
reg exe_uop_bits_fu_code_6; // @[execution-unit.scala:98:20]
reg exe_uop_bits_fu_code_5; // @[execution-unit.scala:98:20]
reg exe_uop_bits_fu_code_4; // @[execution-unit.scala:98:20]
reg exe_uop_bits_fu_code_3; // @[execution-unit.scala:98:20]
reg exe_uop_bits_fu_code_2; // @[execution-unit.scala:98:20]
reg exe_uop_bits_fu_code_1; // @[execution-unit.scala:98:20]
reg exe_uop_bits_fu_code_0; // @[execution-unit.scala:98:20]
reg exe_uop_bits_iq_type_3; // @[execution-unit.scala:98:20]
reg exe_uop_bits_iq_type_2; // @[execution-unit.scala:98:20]
reg exe_uop_bits_iq_type_1; // @[execution-unit.scala:98:20]
reg exe_uop_bits_iq_type_0; // @[execution-unit.scala:98:20]
reg [39:0] exe_uop_bits_debug_pc; // @[execution-unit.scala:98:20]
reg exe_uop_bits_is_rvc; // @[execution-unit.scala:98:20]
reg [31:0] exe_uop_bits_debug_inst; // @[execution-unit.scala:98:20]
reg [31:0] exe_uop_bits_inst; // @[execution-unit.scala:98:20]
reg [2:0] rrd_uop_bits_debug_tsrc; // @[execution-unit.scala:95:20]
reg [2:0] rrd_uop_bits_debug_fsrc; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_bp_xcpt_if; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_bp_debug_if; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_xcpt_ma_if; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_xcpt_ae_if; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_xcpt_pf_if; // @[execution-unit.scala:95:20]
reg [1:0] rrd_uop_bits_fp_typ; // @[execution-unit.scala:95:20]
reg [2:0] rrd_uop_bits_fp_rm; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_fp_val; // @[execution-unit.scala:95:20]
reg [4:0] rrd_uop_bits_fcn_op; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_fcn_dw; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_frs3_en; // @[execution-unit.scala:95:20]
reg [1:0] rrd_uop_bits_lrs2_rtype; // @[execution-unit.scala:95:20]
reg [1:0] rrd_uop_bits_lrs1_rtype; // @[execution-unit.scala:95:20]
reg [1:0] rrd_uop_bits_dst_rtype; // @[execution-unit.scala:95:20]
reg [5:0] rrd_uop_bits_lrs3; // @[execution-unit.scala:95:20]
reg [5:0] rrd_uop_bits_lrs2; // @[execution-unit.scala:95:20]
reg [5:0] rrd_uop_bits_lrs1; // @[execution-unit.scala:95:20]
reg [5:0] rrd_uop_bits_ldst; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_ldst_is_rs1; // @[execution-unit.scala:95:20]
reg [2:0] rrd_uop_bits_csr_cmd; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_flush_on_commit; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_is_unique; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_uses_stq; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_uses_ldq; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_mem_signed; // @[execution-unit.scala:95:20]
reg [1:0] rrd_uop_bits_mem_size; // @[execution-unit.scala:95:20]
reg [4:0] rrd_uop_bits_mem_cmd; // @[execution-unit.scala:95:20]
reg [63:0] rrd_uop_bits_exc_cause; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_exception; // @[execution-unit.scala:95:20]
reg [6:0] rrd_uop_bits_stale_pdst; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_ppred_busy; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_prs3_busy; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_prs2_busy; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_prs1_busy; // @[execution-unit.scala:95:20]
reg [4:0] rrd_uop_bits_ppred; // @[execution-unit.scala:95:20]
reg [6:0] rrd_uop_bits_prs3; // @[execution-unit.scala:95:20]
reg [6:0] rrd_uop_bits_prs2; // @[execution-unit.scala:95:20]
reg [6:0] rrd_uop_bits_prs1; // @[execution-unit.scala:95:20]
reg [6:0] rrd_uop_bits_pdst; // @[execution-unit.scala:95:20]
reg [1:0] rrd_uop_bits_rxq_idx; // @[execution-unit.scala:95:20]
reg [3:0] rrd_uop_bits_stq_idx; // @[execution-unit.scala:95:20]
reg [3:0] rrd_uop_bits_ldq_idx; // @[execution-unit.scala:95:20]
reg [5:0] rrd_uop_bits_rob_idx; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_fp_ctrl_vec; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_fp_ctrl_wflags; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_fp_ctrl_sqrt; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_fp_ctrl_div; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_fp_ctrl_fma; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_fp_ctrl_fastpipe; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_fp_ctrl_toint; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_fp_ctrl_fromint; // @[execution-unit.scala:95:20]
reg [1:0] rrd_uop_bits_fp_ctrl_typeTagOut; // @[execution-unit.scala:95:20]
reg [1:0] rrd_uop_bits_fp_ctrl_typeTagIn; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_fp_ctrl_swap23; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_fp_ctrl_swap12; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_fp_ctrl_ren3; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_fp_ctrl_ren2; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_fp_ctrl_ren1; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_fp_ctrl_wen; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_fp_ctrl_ldst; // @[execution-unit.scala:95:20]
reg [2:0] rrd_uop_bits_op2_sel; // @[execution-unit.scala:95:20]
reg [1:0] rrd_uop_bits_op1_sel; // @[execution-unit.scala:95:20]
reg [19:0] rrd_uop_bits_imm_packed; // @[execution-unit.scala:95:20]
reg [4:0] rrd_uop_bits_pimm; // @[execution-unit.scala:95:20]
reg [2:0] rrd_uop_bits_imm_sel; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_imm_rename; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_taken; // @[execution-unit.scala:95:20]
reg [5:0] rrd_uop_bits_pc_lob; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_edge_inst; // @[execution-unit.scala:95:20]
reg [4:0] rrd_uop_bits_ftq_idx; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_is_mov; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_is_rocc; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_is_sys_pc2epc; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_is_eret; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_is_amo; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_is_sfence; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_is_fencei; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_is_fence; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_is_sfb; // @[execution-unit.scala:95:20]
reg [3:0] rrd_uop_bits_br_type; // @[execution-unit.scala:95:20]
reg [3:0] rrd_uop_bits_br_tag; // @[execution-unit.scala:95:20]
reg [11:0] rrd_uop_bits_br_mask; // @[execution-unit.scala:95:20]
reg [1:0] rrd_uop_bits_dis_col_sel; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_iw_p3_bypass_hint; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_iw_p2_bypass_hint; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_iw_p1_bypass_hint; // @[execution-unit.scala:95:20]
reg [1:0] rrd_uop_bits_iw_p2_speculative_child; // @[execution-unit.scala:95:20]
reg [1:0] rrd_uop_bits_iw_p1_speculative_child; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_iw_issued_partial_dgen; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_iw_issued_partial_agen; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_iw_issued; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_fu_code_9; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_fu_code_8; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_fu_code_7; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_fu_code_6; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_fu_code_5; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_fu_code_4; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_fu_code_3; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_fu_code_2; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_fu_code_1; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_fu_code_0; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_iq_type_3; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_iq_type_2; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_iq_type_1; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_iq_type_0; // @[execution-unit.scala:95:20]
reg [39:0] rrd_uop_bits_debug_pc; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_is_rvc; // @[execution-unit.scala:95:20]
reg [31:0] rrd_uop_bits_debug_inst; // @[execution-unit.scala:95:20]
reg [31:0] rrd_uop_bits_inst; // @[execution-unit.scala:95:20]
wire io_arb_irf_reqs_0_ready_0 = io_arb_irf_reqs_0_ready; // @[execution-unit.scala:255:7]
wire [31:0] arb_uop_bits_out_inst = io_iss_uop_bits_inst; // @[util.scala:104:23]
wire [31:0] arb_uop_bits_out_debug_inst = io_iss_uop_bits_debug_inst; // @[util.scala:104:23]
wire arb_uop_bits_out_is_rvc = io_iss_uop_bits_is_rvc; // @[util.scala:104:23]
wire [39:0] arb_uop_bits_out_debug_pc = io_iss_uop_bits_debug_pc; // @[util.scala:104:23]
wire arb_uop_bits_out_iq_type_0 = io_iss_uop_bits_iq_type_0; // @[util.scala:104:23]
wire arb_uop_bits_out_iq_type_1 = io_iss_uop_bits_iq_type_1; // @[util.scala:104:23]
wire arb_uop_bits_out_iq_type_2 = io_iss_uop_bits_iq_type_2; // @[util.scala:104:23]
wire arb_uop_bits_out_iq_type_3 = io_iss_uop_bits_iq_type_3; // @[util.scala:104:23]
wire arb_uop_bits_out_fu_code_0 = io_iss_uop_bits_fu_code_0; // @[util.scala:104:23]
wire arb_uop_bits_out_fu_code_1 = io_iss_uop_bits_fu_code_1; // @[util.scala:104:23]
wire arb_uop_bits_out_fu_code_2 = io_iss_uop_bits_fu_code_2; // @[util.scala:104:23]
wire arb_uop_bits_out_fu_code_3 = io_iss_uop_bits_fu_code_3; // @[util.scala:104:23]
wire arb_uop_bits_out_fu_code_4 = io_iss_uop_bits_fu_code_4; // @[util.scala:104:23]
wire arb_uop_bits_out_fu_code_5 = io_iss_uop_bits_fu_code_5; // @[util.scala:104:23]
wire arb_uop_bits_out_fu_code_6 = io_iss_uop_bits_fu_code_6; // @[util.scala:104:23]
wire arb_uop_bits_out_fu_code_7 = io_iss_uop_bits_fu_code_7; // @[util.scala:104:23]
wire arb_uop_bits_out_fu_code_8 = io_iss_uop_bits_fu_code_8; // @[util.scala:104:23]
wire arb_uop_bits_out_fu_code_9 = io_iss_uop_bits_fu_code_9; // @[util.scala:104:23]
wire arb_uop_bits_out_iw_issued = io_iss_uop_bits_iw_issued; // @[util.scala:104:23]
wire arb_uop_bits_out_iw_issued_partial_agen = io_iss_uop_bits_iw_issued_partial_agen; // @[util.scala:104:23]
wire arb_uop_bits_out_iw_issued_partial_dgen = io_iss_uop_bits_iw_issued_partial_dgen; // @[util.scala:104:23]
wire [1:0] arb_uop_bits_out_iw_p1_speculative_child = io_iss_uop_bits_iw_p1_speculative_child; // @[util.scala:104:23]
wire [1:0] arb_uop_bits_out_iw_p2_speculative_child = io_iss_uop_bits_iw_p2_speculative_child; // @[util.scala:104:23]
wire arb_uop_bits_out_iw_p1_bypass_hint = io_iss_uop_bits_iw_p1_bypass_hint; // @[util.scala:104:23]
wire arb_uop_bits_out_iw_p2_bypass_hint = io_iss_uop_bits_iw_p2_bypass_hint; // @[util.scala:104:23]
wire arb_uop_bits_out_iw_p3_bypass_hint = io_iss_uop_bits_iw_p3_bypass_hint; // @[util.scala:104:23]
wire [1:0] arb_uop_bits_out_dis_col_sel = io_iss_uop_bits_dis_col_sel; // @[util.scala:104:23]
wire [3:0] arb_uop_bits_out_br_tag = io_iss_uop_bits_br_tag; // @[util.scala:104:23]
wire [3:0] arb_uop_bits_out_br_type = io_iss_uop_bits_br_type; // @[util.scala:104:23]
wire arb_uop_bits_out_is_sfb = io_iss_uop_bits_is_sfb; // @[util.scala:104:23]
wire arb_uop_bits_out_is_fence = io_iss_uop_bits_is_fence; // @[util.scala:104:23]
wire arb_uop_bits_out_is_fencei = io_iss_uop_bits_is_fencei; // @[util.scala:104:23]
wire arb_uop_bits_out_is_sfence = io_iss_uop_bits_is_sfence; // @[util.scala:104:23]
wire arb_uop_bits_out_is_amo = io_iss_uop_bits_is_amo; // @[util.scala:104:23]
wire arb_uop_bits_out_is_eret = io_iss_uop_bits_is_eret; // @[util.scala:104:23]
wire arb_uop_bits_out_is_sys_pc2epc = io_iss_uop_bits_is_sys_pc2epc; // @[util.scala:104:23]
wire arb_uop_bits_out_is_rocc = io_iss_uop_bits_is_rocc; // @[util.scala:104:23]
wire arb_uop_bits_out_is_mov = io_iss_uop_bits_is_mov; // @[util.scala:104:23]
wire [4:0] arb_uop_bits_out_ftq_idx = io_iss_uop_bits_ftq_idx; // @[util.scala:104:23]
wire arb_uop_bits_out_edge_inst = io_iss_uop_bits_edge_inst; // @[util.scala:104:23]
wire [5:0] arb_uop_bits_out_pc_lob = io_iss_uop_bits_pc_lob; // @[util.scala:104:23]
wire arb_uop_bits_out_taken = io_iss_uop_bits_taken; // @[util.scala:104:23]
wire arb_uop_bits_out_imm_rename = io_iss_uop_bits_imm_rename; // @[util.scala:104:23]
wire [2:0] arb_uop_bits_out_imm_sel = io_iss_uop_bits_imm_sel; // @[util.scala:104:23]
wire [4:0] arb_uop_bits_out_pimm = io_iss_uop_bits_pimm; // @[util.scala:104:23]
wire [19:0] arb_uop_bits_out_imm_packed = io_iss_uop_bits_imm_packed; // @[util.scala:104:23]
wire [1:0] arb_uop_bits_out_op1_sel = io_iss_uop_bits_op1_sel; // @[util.scala:104:23]
wire [2:0] arb_uop_bits_out_op2_sel = io_iss_uop_bits_op2_sel; // @[util.scala:104:23]
wire arb_uop_bits_out_fp_ctrl_ldst = io_iss_uop_bits_fp_ctrl_ldst; // @[util.scala:104:23]
wire arb_uop_bits_out_fp_ctrl_wen = io_iss_uop_bits_fp_ctrl_wen; // @[util.scala:104:23]
wire arb_uop_bits_out_fp_ctrl_ren1 = io_iss_uop_bits_fp_ctrl_ren1; // @[util.scala:104:23]
wire arb_uop_bits_out_fp_ctrl_ren2 = io_iss_uop_bits_fp_ctrl_ren2; // @[util.scala:104:23]
wire arb_uop_bits_out_fp_ctrl_ren3 = io_iss_uop_bits_fp_ctrl_ren3; // @[util.scala:104:23]
wire arb_uop_bits_out_fp_ctrl_swap12 = io_iss_uop_bits_fp_ctrl_swap12; // @[util.scala:104:23]
wire arb_uop_bits_out_fp_ctrl_swap23 = io_iss_uop_bits_fp_ctrl_swap23; // @[util.scala:104:23]
wire [1:0] arb_uop_bits_out_fp_ctrl_typeTagIn = io_iss_uop_bits_fp_ctrl_typeTagIn; // @[util.scala:104:23]
wire [1:0] arb_uop_bits_out_fp_ctrl_typeTagOut = io_iss_uop_bits_fp_ctrl_typeTagOut; // @[util.scala:104:23]
wire arb_uop_bits_out_fp_ctrl_fromint = io_iss_uop_bits_fp_ctrl_fromint; // @[util.scala:104:23]
wire arb_uop_bits_out_fp_ctrl_toint = io_iss_uop_bits_fp_ctrl_toint; // @[util.scala:104:23]
wire arb_uop_bits_out_fp_ctrl_fastpipe = io_iss_uop_bits_fp_ctrl_fastpipe; // @[util.scala:104:23]
wire arb_uop_bits_out_fp_ctrl_fma = io_iss_uop_bits_fp_ctrl_fma; // @[util.scala:104:23]
wire arb_uop_bits_out_fp_ctrl_div = io_iss_uop_bits_fp_ctrl_div; // @[util.scala:104:23]
wire arb_uop_bits_out_fp_ctrl_sqrt = io_iss_uop_bits_fp_ctrl_sqrt; // @[util.scala:104:23]
wire arb_uop_bits_out_fp_ctrl_wflags = io_iss_uop_bits_fp_ctrl_wflags; // @[util.scala:104:23]
wire arb_uop_bits_out_fp_ctrl_vec = io_iss_uop_bits_fp_ctrl_vec; // @[util.scala:104:23]
wire [5:0] arb_uop_bits_out_rob_idx = io_iss_uop_bits_rob_idx; // @[util.scala:104:23]
wire [3:0] arb_uop_bits_out_ldq_idx = io_iss_uop_bits_ldq_idx; // @[util.scala:104:23]
wire [3:0] arb_uop_bits_out_stq_idx = io_iss_uop_bits_stq_idx; // @[util.scala:104:23]
wire [1:0] arb_uop_bits_out_rxq_idx = io_iss_uop_bits_rxq_idx; // @[util.scala:104:23]
wire [6:0] arb_uop_bits_out_pdst = io_iss_uop_bits_pdst; // @[util.scala:104:23]
wire [6:0] arb_uop_bits_out_prs1 = io_iss_uop_bits_prs1; // @[util.scala:104:23]
wire [6:0] arb_uop_bits_out_prs2 = io_iss_uop_bits_prs2; // @[util.scala:104:23]
wire [6:0] arb_uop_bits_out_prs3 = io_iss_uop_bits_prs3; // @[util.scala:104:23]
wire [4:0] arb_uop_bits_out_ppred = io_iss_uop_bits_ppred; // @[util.scala:104:23]
wire arb_uop_bits_out_prs1_busy = io_iss_uop_bits_prs1_busy; // @[util.scala:104:23]
wire arb_uop_bits_out_prs2_busy = io_iss_uop_bits_prs2_busy; // @[util.scala:104:23]
wire arb_uop_bits_out_prs3_busy = io_iss_uop_bits_prs3_busy; // @[util.scala:104:23]
wire arb_uop_bits_out_ppred_busy = io_iss_uop_bits_ppred_busy; // @[util.scala:104:23]
wire [6:0] arb_uop_bits_out_stale_pdst = io_iss_uop_bits_stale_pdst; // @[util.scala:104:23]
wire arb_uop_bits_out_exception = io_iss_uop_bits_exception; // @[util.scala:104:23]
wire [63:0] arb_uop_bits_out_exc_cause = io_iss_uop_bits_exc_cause; // @[util.scala:104:23]
wire [4:0] arb_uop_bits_out_mem_cmd = io_iss_uop_bits_mem_cmd; // @[util.scala:104:23]
wire [1:0] arb_uop_bits_out_mem_size = io_iss_uop_bits_mem_size; // @[util.scala:104:23]
wire arb_uop_bits_out_mem_signed = io_iss_uop_bits_mem_signed; // @[util.scala:104:23]
wire arb_uop_bits_out_uses_ldq = io_iss_uop_bits_uses_ldq; // @[util.scala:104:23]
wire arb_uop_bits_out_uses_stq = io_iss_uop_bits_uses_stq; // @[util.scala:104:23]
wire arb_uop_bits_out_is_unique = io_iss_uop_bits_is_unique; // @[util.scala:104:23]
wire arb_uop_bits_out_flush_on_commit = io_iss_uop_bits_flush_on_commit; // @[util.scala:104:23]
wire [2:0] arb_uop_bits_out_csr_cmd = io_iss_uop_bits_csr_cmd; // @[util.scala:104:23]
wire arb_uop_bits_out_ldst_is_rs1 = io_iss_uop_bits_ldst_is_rs1; // @[util.scala:104:23]
wire [5:0] arb_uop_bits_out_ldst = io_iss_uop_bits_ldst; // @[util.scala:104:23]
wire [5:0] arb_uop_bits_out_lrs1 = io_iss_uop_bits_lrs1; // @[util.scala:104:23]
wire [5:0] arb_uop_bits_out_lrs2 = io_iss_uop_bits_lrs2; // @[util.scala:104:23]
wire [5:0] arb_uop_bits_out_lrs3 = io_iss_uop_bits_lrs3; // @[util.scala:104:23]
wire [1:0] arb_uop_bits_out_dst_rtype = io_iss_uop_bits_dst_rtype; // @[util.scala:104:23]
wire [1:0] arb_uop_bits_out_lrs1_rtype = io_iss_uop_bits_lrs1_rtype; // @[util.scala:104:23]
wire arb_uop_bits_out_frs3_en = io_iss_uop_bits_frs3_en; // @[util.scala:104:23]
wire arb_uop_bits_out_fcn_dw = io_iss_uop_bits_fcn_dw; // @[util.scala:104:23]
wire [4:0] arb_uop_bits_out_fcn_op = io_iss_uop_bits_fcn_op; // @[util.scala:104:23]
wire arb_uop_bits_out_fp_val = io_iss_uop_bits_fp_val; // @[util.scala:104:23]
wire [2:0] arb_uop_bits_out_fp_rm = io_iss_uop_bits_fp_rm; // @[util.scala:104:23]
wire [1:0] arb_uop_bits_out_fp_typ = io_iss_uop_bits_fp_typ; // @[util.scala:104:23]
wire arb_uop_bits_out_xcpt_pf_if = io_iss_uop_bits_xcpt_pf_if; // @[util.scala:104:23]
wire arb_uop_bits_out_xcpt_ae_if = io_iss_uop_bits_xcpt_ae_if; // @[util.scala:104:23]
wire arb_uop_bits_out_xcpt_ma_if = io_iss_uop_bits_xcpt_ma_if; // @[util.scala:104:23]
wire arb_uop_bits_out_bp_debug_if = io_iss_uop_bits_bp_debug_if; // @[util.scala:104:23]
wire arb_uop_bits_out_bp_xcpt_if = io_iss_uop_bits_bp_xcpt_if; // @[util.scala:104:23]
wire [2:0] arb_uop_bits_out_debug_fsrc = io_iss_uop_bits_debug_fsrc; // @[util.scala:104:23]
wire [2:0] arb_uop_bits_out_debug_tsrc = io_iss_uop_bits_debug_tsrc; // @[util.scala:104:23]
wire _io_agen_T_2 = reset; // @[execution-unit.scala:311:11]
wire arb_rebusied_prs2 = 1'h0; // @[execution-unit.scala:129:93]
wire _r_WIRE_0 = 1'h0; // @[execution-unit.scala:74:29]
wire _r_WIRE_1 = 1'h0; // @[execution-unit.scala:74:29]
wire _r_WIRE_2 = 1'h0; // @[execution-unit.scala:74:29]
wire _r_WIRE_3 = 1'h0; // @[execution-unit.scala:74:29]
wire _r_WIRE_4 = 1'h0; // @[execution-unit.scala:74:29]
wire _r_WIRE_5 = 1'h0; // @[execution-unit.scala:74:29]
wire _r_WIRE_6 = 1'h0; // @[execution-unit.scala:74:29]
wire _r_WIRE_7 = 1'h0; // @[execution-unit.scala:74:29]
wire _r_WIRE_8 = 1'h0; // @[execution-unit.scala:74:29]
wire _r_WIRE_9 = 1'h0; // @[execution-unit.scala:74:29]
wire r_0 = 1'h0; // @[execution-unit.scala:74:21]
wire r_1 = 1'h0; // @[execution-unit.scala:74:21]
wire r_3 = 1'h0; // @[execution-unit.scala:74:21]
wire r_4 = 1'h0; // @[execution-unit.scala:74:21]
wire r_5 = 1'h0; // @[execution-unit.scala:74:21]
wire r_6 = 1'h0; // @[execution-unit.scala:74:21]
wire r_7 = 1'h0; // @[execution-unit.scala:74:21]
wire r_8 = 1'h0; // @[execution-unit.scala:74:21]
wire r_9 = 1'h0; // @[execution-unit.scala:74:21]
wire [1:0] arb_uop_bits_out_lrs2_rtype = 2'h2; // @[util.scala:104:23]
wire io_arb_immrf_req_ready = 1'h1; // @[execution-unit.scala:255:7]
wire r_2 = 1'h1; // @[execution-unit.scala:74:21]
wire _io_arb_irf_reqs_0_valid_T_3; // @[execution-unit.scala:121:83]
wire _io_arb_immrf_req_valid_T_4; // @[execution-unit.scala:157:44]
wire io_arb_irf_reqs_0_valid_0; // @[execution-unit.scala:255:7]
wire [6:0] io_arb_irf_reqs_0_bits_0; // @[execution-unit.scala:255:7]
wire io_arb_immrf_req_valid_0; // @[execution-unit.scala:255:7]
wire [4:0] io_arb_immrf_req_bits_0; // @[execution-unit.scala:255:7]
wire _io_rrd_immrf_wakeup_valid_T_4; // @[execution-unit.scala:162:47]
wire _io_squash_iss_T_1; // @[execution-unit.scala:265:46]
wire _io_dgen_dgen_valid_T; // @[execution-unit.scala:318:37]
reg arb_uop_valid; // @[execution-unit.scala:92:20]
reg [31:0] arb_uop_bits_inst; // @[execution-unit.scala:92:20]
wire [31:0] rrd_uop_bits_out_inst = arb_uop_bits_inst; // @[util.scala:104:23]
wire [31:0] arb_uop_bits_out_1_inst = arb_uop_bits_inst; // @[util.scala:104:23]
reg [31:0] arb_uop_bits_debug_inst; // @[execution-unit.scala:92:20]
wire [31:0] rrd_uop_bits_out_debug_inst = arb_uop_bits_debug_inst; // @[util.scala:104:23]
wire [31:0] arb_uop_bits_out_1_debug_inst = arb_uop_bits_debug_inst; // @[util.scala:104:23]
reg arb_uop_bits_is_rvc; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_is_rvc = arb_uop_bits_is_rvc; // @[util.scala:104:23]
wire arb_uop_bits_out_1_is_rvc = arb_uop_bits_is_rvc; // @[util.scala:104:23]
reg [39:0] arb_uop_bits_debug_pc; // @[execution-unit.scala:92:20]
wire [39:0] rrd_uop_bits_out_debug_pc = arb_uop_bits_debug_pc; // @[util.scala:104:23]
wire [39:0] arb_uop_bits_out_1_debug_pc = arb_uop_bits_debug_pc; // @[util.scala:104:23]
reg arb_uop_bits_iq_type_0; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_iq_type_0 = arb_uop_bits_iq_type_0; // @[util.scala:104:23]
wire arb_uop_bits_out_1_iq_type_0 = arb_uop_bits_iq_type_0; // @[util.scala:104:23]
reg arb_uop_bits_iq_type_1; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_iq_type_1 = arb_uop_bits_iq_type_1; // @[util.scala:104:23]
wire arb_uop_bits_out_1_iq_type_1 = arb_uop_bits_iq_type_1; // @[util.scala:104:23]
reg arb_uop_bits_iq_type_2; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_iq_type_2 = arb_uop_bits_iq_type_2; // @[util.scala:104:23]
wire arb_uop_bits_out_1_iq_type_2 = arb_uop_bits_iq_type_2; // @[util.scala:104:23]
reg arb_uop_bits_iq_type_3; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_iq_type_3 = arb_uop_bits_iq_type_3; // @[util.scala:104:23]
wire arb_uop_bits_out_1_iq_type_3 = arb_uop_bits_iq_type_3; // @[util.scala:104:23]
reg arb_uop_bits_fu_code_0; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_fu_code_0 = arb_uop_bits_fu_code_0; // @[util.scala:104:23]
wire arb_uop_bits_out_1_fu_code_0 = arb_uop_bits_fu_code_0; // @[util.scala:104:23]
reg arb_uop_bits_fu_code_1; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_fu_code_1 = arb_uop_bits_fu_code_1; // @[util.scala:104:23]
wire arb_uop_bits_out_1_fu_code_1 = arb_uop_bits_fu_code_1; // @[util.scala:104:23]
reg arb_uop_bits_fu_code_2; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_fu_code_2 = arb_uop_bits_fu_code_2; // @[util.scala:104:23]
wire arb_uop_bits_out_1_fu_code_2 = arb_uop_bits_fu_code_2; // @[util.scala:104:23]
reg arb_uop_bits_fu_code_3; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_fu_code_3 = arb_uop_bits_fu_code_3; // @[util.scala:104:23]
wire arb_uop_bits_out_1_fu_code_3 = arb_uop_bits_fu_code_3; // @[util.scala:104:23]
reg arb_uop_bits_fu_code_4; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_fu_code_4 = arb_uop_bits_fu_code_4; // @[util.scala:104:23]
wire arb_uop_bits_out_1_fu_code_4 = arb_uop_bits_fu_code_4; // @[util.scala:104:23]
reg arb_uop_bits_fu_code_5; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_fu_code_5 = arb_uop_bits_fu_code_5; // @[util.scala:104:23]
wire arb_uop_bits_out_1_fu_code_5 = arb_uop_bits_fu_code_5; // @[util.scala:104:23]
reg arb_uop_bits_fu_code_6; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_fu_code_6 = arb_uop_bits_fu_code_6; // @[util.scala:104:23]
wire arb_uop_bits_out_1_fu_code_6 = arb_uop_bits_fu_code_6; // @[util.scala:104:23]
reg arb_uop_bits_fu_code_7; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_fu_code_7 = arb_uop_bits_fu_code_7; // @[util.scala:104:23]
wire arb_uop_bits_out_1_fu_code_7 = arb_uop_bits_fu_code_7; // @[util.scala:104:23]
reg arb_uop_bits_fu_code_8; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_fu_code_8 = arb_uop_bits_fu_code_8; // @[util.scala:104:23]
wire arb_uop_bits_out_1_fu_code_8 = arb_uop_bits_fu_code_8; // @[util.scala:104:23]
reg arb_uop_bits_fu_code_9; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_fu_code_9 = arb_uop_bits_fu_code_9; // @[util.scala:104:23]
wire arb_uop_bits_out_1_fu_code_9 = arb_uop_bits_fu_code_9; // @[util.scala:104:23]
reg arb_uop_bits_iw_issued; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_iw_issued = arb_uop_bits_iw_issued; // @[util.scala:104:23]
wire arb_uop_bits_out_1_iw_issued = arb_uop_bits_iw_issued; // @[util.scala:104:23]
reg arb_uop_bits_iw_issued_partial_agen; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_iw_issued_partial_agen = arb_uop_bits_iw_issued_partial_agen; // @[util.scala:104:23]
wire arb_uop_bits_out_1_iw_issued_partial_agen = arb_uop_bits_iw_issued_partial_agen; // @[util.scala:104:23]
reg arb_uop_bits_iw_issued_partial_dgen; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_iw_issued_partial_dgen = arb_uop_bits_iw_issued_partial_dgen; // @[util.scala:104:23]
wire arb_uop_bits_out_1_iw_issued_partial_dgen = arb_uop_bits_iw_issued_partial_dgen; // @[util.scala:104:23]
reg [1:0] arb_uop_bits_iw_p1_speculative_child; // @[execution-unit.scala:92:20]
wire [1:0] rrd_uop_bits_out_iw_p1_speculative_child = arb_uop_bits_iw_p1_speculative_child; // @[util.scala:104:23]
wire [1:0] arb_uop_bits_out_1_iw_p1_speculative_child = arb_uop_bits_iw_p1_speculative_child; // @[util.scala:104:23]
reg [1:0] arb_uop_bits_iw_p2_speculative_child; // @[execution-unit.scala:92:20]
wire [1:0] rrd_uop_bits_out_iw_p2_speculative_child = arb_uop_bits_iw_p2_speculative_child; // @[util.scala:104:23]
wire [1:0] arb_uop_bits_out_1_iw_p2_speculative_child = arb_uop_bits_iw_p2_speculative_child; // @[util.scala:104:23]
reg arb_uop_bits_iw_p1_bypass_hint; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_iw_p1_bypass_hint = arb_uop_bits_iw_p1_bypass_hint; // @[util.scala:104:23]
wire arb_uop_bits_out_1_iw_p1_bypass_hint = arb_uop_bits_iw_p1_bypass_hint; // @[util.scala:104:23]
reg arb_uop_bits_iw_p2_bypass_hint; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_iw_p2_bypass_hint = arb_uop_bits_iw_p2_bypass_hint; // @[util.scala:104:23]
wire arb_uop_bits_out_1_iw_p2_bypass_hint = arb_uop_bits_iw_p2_bypass_hint; // @[util.scala:104:23]
reg arb_uop_bits_iw_p3_bypass_hint; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_iw_p3_bypass_hint = arb_uop_bits_iw_p3_bypass_hint; // @[util.scala:104:23]
wire arb_uop_bits_out_1_iw_p3_bypass_hint = arb_uop_bits_iw_p3_bypass_hint; // @[util.scala:104:23]
reg [1:0] arb_uop_bits_dis_col_sel; // @[execution-unit.scala:92:20]
wire [1:0] rrd_uop_bits_out_dis_col_sel = arb_uop_bits_dis_col_sel; // @[util.scala:104:23]
wire [1:0] arb_uop_bits_out_1_dis_col_sel = arb_uop_bits_dis_col_sel; // @[util.scala:104:23]
reg [11:0] arb_uop_bits_br_mask; // @[execution-unit.scala:92:20]
reg [3:0] arb_uop_bits_br_tag; // @[execution-unit.scala:92:20]
wire [3:0] rrd_uop_bits_out_br_tag = arb_uop_bits_br_tag; // @[util.scala:104:23]
wire [3:0] arb_uop_bits_out_1_br_tag = arb_uop_bits_br_tag; // @[util.scala:104:23]
reg [3:0] arb_uop_bits_br_type; // @[execution-unit.scala:92:20]
wire [3:0] rrd_uop_bits_out_br_type = arb_uop_bits_br_type; // @[util.scala:104:23]
wire [3:0] arb_uop_bits_out_1_br_type = arb_uop_bits_br_type; // @[util.scala:104:23]
reg arb_uop_bits_is_sfb; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_is_sfb = arb_uop_bits_is_sfb; // @[util.scala:104:23]
wire arb_uop_bits_out_1_is_sfb = arb_uop_bits_is_sfb; // @[util.scala:104:23]
reg arb_uop_bits_is_fence; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_is_fence = arb_uop_bits_is_fence; // @[util.scala:104:23]
wire arb_uop_bits_out_1_is_fence = arb_uop_bits_is_fence; // @[util.scala:104:23]
reg arb_uop_bits_is_fencei; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_is_fencei = arb_uop_bits_is_fencei; // @[util.scala:104:23]
wire arb_uop_bits_out_1_is_fencei = arb_uop_bits_is_fencei; // @[util.scala:104:23]
reg arb_uop_bits_is_sfence; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_is_sfence = arb_uop_bits_is_sfence; // @[util.scala:104:23]
wire arb_uop_bits_out_1_is_sfence = arb_uop_bits_is_sfence; // @[util.scala:104:23]
reg arb_uop_bits_is_amo; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_is_amo = arb_uop_bits_is_amo; // @[util.scala:104:23]
wire arb_uop_bits_out_1_is_amo = arb_uop_bits_is_amo; // @[util.scala:104:23]
reg arb_uop_bits_is_eret; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_is_eret = arb_uop_bits_is_eret; // @[util.scala:104:23]
wire arb_uop_bits_out_1_is_eret = arb_uop_bits_is_eret; // @[util.scala:104:23]
reg arb_uop_bits_is_sys_pc2epc; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_is_sys_pc2epc = arb_uop_bits_is_sys_pc2epc; // @[util.scala:104:23]
wire arb_uop_bits_out_1_is_sys_pc2epc = arb_uop_bits_is_sys_pc2epc; // @[util.scala:104:23]
reg arb_uop_bits_is_rocc; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_is_rocc = arb_uop_bits_is_rocc; // @[util.scala:104:23]
wire arb_uop_bits_out_1_is_rocc = arb_uop_bits_is_rocc; // @[util.scala:104:23]
reg arb_uop_bits_is_mov; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_is_mov = arb_uop_bits_is_mov; // @[util.scala:104:23]
wire arb_uop_bits_out_1_is_mov = arb_uop_bits_is_mov; // @[util.scala:104:23]
reg [4:0] arb_uop_bits_ftq_idx; // @[execution-unit.scala:92:20]
wire [4:0] rrd_uop_bits_out_ftq_idx = arb_uop_bits_ftq_idx; // @[util.scala:104:23]
wire [4:0] arb_uop_bits_out_1_ftq_idx = arb_uop_bits_ftq_idx; // @[util.scala:104:23]
reg arb_uop_bits_edge_inst; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_edge_inst = arb_uop_bits_edge_inst; // @[util.scala:104:23]
wire arb_uop_bits_out_1_edge_inst = arb_uop_bits_edge_inst; // @[util.scala:104:23]
reg [5:0] arb_uop_bits_pc_lob; // @[execution-unit.scala:92:20]
wire [5:0] rrd_uop_bits_out_pc_lob = arb_uop_bits_pc_lob; // @[util.scala:104:23]
wire [5:0] arb_uop_bits_out_1_pc_lob = arb_uop_bits_pc_lob; // @[util.scala:104:23]
reg arb_uop_bits_taken; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_taken = arb_uop_bits_taken; // @[util.scala:104:23]
wire arb_uop_bits_out_1_taken = arb_uop_bits_taken; // @[util.scala:104:23]
reg arb_uop_bits_imm_rename; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_imm_rename = arb_uop_bits_imm_rename; // @[util.scala:104:23]
wire arb_uop_bits_out_1_imm_rename = arb_uop_bits_imm_rename; // @[util.scala:104:23]
reg [2:0] arb_uop_bits_imm_sel; // @[execution-unit.scala:92:20]
wire [2:0] rrd_uop_bits_out_imm_sel = arb_uop_bits_imm_sel; // @[util.scala:104:23]
wire [2:0] arb_uop_bits_out_1_imm_sel = arb_uop_bits_imm_sel; // @[util.scala:104:23]
reg [4:0] arb_uop_bits_pimm; // @[execution-unit.scala:92:20]
assign io_arb_immrf_req_bits_0 = arb_uop_bits_pimm; // @[execution-unit.scala:92:20, :255:7]
wire [4:0] rrd_uop_bits_out_pimm = arb_uop_bits_pimm; // @[util.scala:104:23]
wire [4:0] arb_uop_bits_out_1_pimm = arb_uop_bits_pimm; // @[util.scala:104:23]
reg [19:0] arb_uop_bits_imm_packed; // @[execution-unit.scala:92:20]
wire [19:0] rrd_uop_bits_out_imm_packed = arb_uop_bits_imm_packed; // @[util.scala:104:23]
wire [19:0] arb_uop_bits_out_1_imm_packed = arb_uop_bits_imm_packed; // @[util.scala:104:23]
reg [1:0] arb_uop_bits_op1_sel; // @[execution-unit.scala:92:20]
wire [1:0] rrd_uop_bits_out_op1_sel = arb_uop_bits_op1_sel; // @[util.scala:104:23]
wire [1:0] arb_uop_bits_out_1_op1_sel = arb_uop_bits_op1_sel; // @[util.scala:104:23]
reg [2:0] arb_uop_bits_op2_sel; // @[execution-unit.scala:92:20]
wire [2:0] rrd_uop_bits_out_op2_sel = arb_uop_bits_op2_sel; // @[util.scala:104:23]
wire [2:0] arb_uop_bits_out_1_op2_sel = arb_uop_bits_op2_sel; // @[util.scala:104:23]
reg arb_uop_bits_fp_ctrl_ldst; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_fp_ctrl_ldst = arb_uop_bits_fp_ctrl_ldst; // @[util.scala:104:23]
wire arb_uop_bits_out_1_fp_ctrl_ldst = arb_uop_bits_fp_ctrl_ldst; // @[util.scala:104:23]
reg arb_uop_bits_fp_ctrl_wen; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_fp_ctrl_wen = arb_uop_bits_fp_ctrl_wen; // @[util.scala:104:23]
wire arb_uop_bits_out_1_fp_ctrl_wen = arb_uop_bits_fp_ctrl_wen; // @[util.scala:104:23]
reg arb_uop_bits_fp_ctrl_ren1; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_fp_ctrl_ren1 = arb_uop_bits_fp_ctrl_ren1; // @[util.scala:104:23]
wire arb_uop_bits_out_1_fp_ctrl_ren1 = arb_uop_bits_fp_ctrl_ren1; // @[util.scala:104:23]
reg arb_uop_bits_fp_ctrl_ren2; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_fp_ctrl_ren2 = arb_uop_bits_fp_ctrl_ren2; // @[util.scala:104:23]
wire arb_uop_bits_out_1_fp_ctrl_ren2 = arb_uop_bits_fp_ctrl_ren2; // @[util.scala:104:23]
reg arb_uop_bits_fp_ctrl_ren3; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_fp_ctrl_ren3 = arb_uop_bits_fp_ctrl_ren3; // @[util.scala:104:23]
wire arb_uop_bits_out_1_fp_ctrl_ren3 = arb_uop_bits_fp_ctrl_ren3; // @[util.scala:104:23]
reg arb_uop_bits_fp_ctrl_swap12; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_fp_ctrl_swap12 = arb_uop_bits_fp_ctrl_swap12; // @[util.scala:104:23]
wire arb_uop_bits_out_1_fp_ctrl_swap12 = arb_uop_bits_fp_ctrl_swap12; // @[util.scala:104:23]
reg arb_uop_bits_fp_ctrl_swap23; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_fp_ctrl_swap23 = arb_uop_bits_fp_ctrl_swap23; // @[util.scala:104:23]
wire arb_uop_bits_out_1_fp_ctrl_swap23 = arb_uop_bits_fp_ctrl_swap23; // @[util.scala:104:23]
reg [1:0] arb_uop_bits_fp_ctrl_typeTagIn; // @[execution-unit.scala:92:20]
wire [1:0] rrd_uop_bits_out_fp_ctrl_typeTagIn = arb_uop_bits_fp_ctrl_typeTagIn; // @[util.scala:104:23]
wire [1:0] arb_uop_bits_out_1_fp_ctrl_typeTagIn = arb_uop_bits_fp_ctrl_typeTagIn; // @[util.scala:104:23]
reg [1:0] arb_uop_bits_fp_ctrl_typeTagOut; // @[execution-unit.scala:92:20]
wire [1:0] rrd_uop_bits_out_fp_ctrl_typeTagOut = arb_uop_bits_fp_ctrl_typeTagOut; // @[util.scala:104:23]
wire [1:0] arb_uop_bits_out_1_fp_ctrl_typeTagOut = arb_uop_bits_fp_ctrl_typeTagOut; // @[util.scala:104:23]
reg arb_uop_bits_fp_ctrl_fromint; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_fp_ctrl_fromint = arb_uop_bits_fp_ctrl_fromint; // @[util.scala:104:23]
wire arb_uop_bits_out_1_fp_ctrl_fromint = arb_uop_bits_fp_ctrl_fromint; // @[util.scala:104:23]
reg arb_uop_bits_fp_ctrl_toint; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_fp_ctrl_toint = arb_uop_bits_fp_ctrl_toint; // @[util.scala:104:23]
wire arb_uop_bits_out_1_fp_ctrl_toint = arb_uop_bits_fp_ctrl_toint; // @[util.scala:104:23]
reg arb_uop_bits_fp_ctrl_fastpipe; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_fp_ctrl_fastpipe = arb_uop_bits_fp_ctrl_fastpipe; // @[util.scala:104:23]
wire arb_uop_bits_out_1_fp_ctrl_fastpipe = arb_uop_bits_fp_ctrl_fastpipe; // @[util.scala:104:23]
reg arb_uop_bits_fp_ctrl_fma; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_fp_ctrl_fma = arb_uop_bits_fp_ctrl_fma; // @[util.scala:104:23]
wire arb_uop_bits_out_1_fp_ctrl_fma = arb_uop_bits_fp_ctrl_fma; // @[util.scala:104:23]
reg arb_uop_bits_fp_ctrl_div; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_fp_ctrl_div = arb_uop_bits_fp_ctrl_div; // @[util.scala:104:23]
wire arb_uop_bits_out_1_fp_ctrl_div = arb_uop_bits_fp_ctrl_div; // @[util.scala:104:23]
reg arb_uop_bits_fp_ctrl_sqrt; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_fp_ctrl_sqrt = arb_uop_bits_fp_ctrl_sqrt; // @[util.scala:104:23]
wire arb_uop_bits_out_1_fp_ctrl_sqrt = arb_uop_bits_fp_ctrl_sqrt; // @[util.scala:104:23]
reg arb_uop_bits_fp_ctrl_wflags; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_fp_ctrl_wflags = arb_uop_bits_fp_ctrl_wflags; // @[util.scala:104:23]
wire arb_uop_bits_out_1_fp_ctrl_wflags = arb_uop_bits_fp_ctrl_wflags; // @[util.scala:104:23]
reg arb_uop_bits_fp_ctrl_vec; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_fp_ctrl_vec = arb_uop_bits_fp_ctrl_vec; // @[util.scala:104:23]
wire arb_uop_bits_out_1_fp_ctrl_vec = arb_uop_bits_fp_ctrl_vec; // @[util.scala:104:23]
reg [5:0] arb_uop_bits_rob_idx; // @[execution-unit.scala:92:20]
wire [5:0] rrd_uop_bits_out_rob_idx = arb_uop_bits_rob_idx; // @[util.scala:104:23]
wire [5:0] arb_uop_bits_out_1_rob_idx = arb_uop_bits_rob_idx; // @[util.scala:104:23]
reg [3:0] arb_uop_bits_ldq_idx; // @[execution-unit.scala:92:20]
wire [3:0] rrd_uop_bits_out_ldq_idx = arb_uop_bits_ldq_idx; // @[util.scala:104:23]
wire [3:0] arb_uop_bits_out_1_ldq_idx = arb_uop_bits_ldq_idx; // @[util.scala:104:23]
reg [3:0] arb_uop_bits_stq_idx; // @[execution-unit.scala:92:20]
wire [3:0] rrd_uop_bits_out_stq_idx = arb_uop_bits_stq_idx; // @[util.scala:104:23]
wire [3:0] arb_uop_bits_out_1_stq_idx = arb_uop_bits_stq_idx; // @[util.scala:104:23]
reg [1:0] arb_uop_bits_rxq_idx; // @[execution-unit.scala:92:20]
wire [1:0] rrd_uop_bits_out_rxq_idx = arb_uop_bits_rxq_idx; // @[util.scala:104:23]
wire [1:0] arb_uop_bits_out_1_rxq_idx = arb_uop_bits_rxq_idx; // @[util.scala:104:23]
reg [6:0] arb_uop_bits_pdst; // @[execution-unit.scala:92:20]
wire [6:0] rrd_uop_bits_out_pdst = arb_uop_bits_pdst; // @[util.scala:104:23]
wire [6:0] arb_uop_bits_out_1_pdst = arb_uop_bits_pdst; // @[util.scala:104:23]
reg [6:0] arb_uop_bits_prs1; // @[execution-unit.scala:92:20]
assign io_arb_irf_reqs_0_bits_0 = arb_uop_bits_prs1; // @[execution-unit.scala:92:20, :255:7]
wire [6:0] rrd_uop_bits_out_prs1 = arb_uop_bits_prs1; // @[util.scala:104:23]
wire [6:0] arb_uop_bits_out_1_prs1 = arb_uop_bits_prs1; // @[util.scala:104:23]
reg [6:0] arb_uop_bits_prs2; // @[execution-unit.scala:92:20]
wire [6:0] rrd_uop_bits_out_prs2 = arb_uop_bits_prs2; // @[util.scala:104:23]
wire [6:0] arb_uop_bits_out_1_prs2 = arb_uop_bits_prs2; // @[util.scala:104:23]
reg [6:0] arb_uop_bits_prs3; // @[execution-unit.scala:92:20]
wire [6:0] rrd_uop_bits_out_prs3 = arb_uop_bits_prs3; // @[util.scala:104:23]
wire [6:0] arb_uop_bits_out_1_prs3 = arb_uop_bits_prs3; // @[util.scala:104:23]
reg [4:0] arb_uop_bits_ppred; // @[execution-unit.scala:92:20]
wire [4:0] rrd_uop_bits_out_ppred = arb_uop_bits_ppred; // @[util.scala:104:23]
wire [4:0] arb_uop_bits_out_1_ppred = arb_uop_bits_ppred; // @[util.scala:104:23]
reg arb_uop_bits_prs1_busy; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_prs1_busy = arb_uop_bits_prs1_busy; // @[util.scala:104:23]
wire arb_uop_bits_out_1_prs1_busy = arb_uop_bits_prs1_busy; // @[util.scala:104:23]
reg arb_uop_bits_prs2_busy; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_prs2_busy = arb_uop_bits_prs2_busy; // @[util.scala:104:23]
wire arb_uop_bits_out_1_prs2_busy = arb_uop_bits_prs2_busy; // @[util.scala:104:23]
reg arb_uop_bits_prs3_busy; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_prs3_busy = arb_uop_bits_prs3_busy; // @[util.scala:104:23]
wire arb_uop_bits_out_1_prs3_busy = arb_uop_bits_prs3_busy; // @[util.scala:104:23]
reg arb_uop_bits_ppred_busy; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_ppred_busy = arb_uop_bits_ppred_busy; // @[util.scala:104:23]
wire arb_uop_bits_out_1_ppred_busy = arb_uop_bits_ppred_busy; // @[util.scala:104:23]
reg [6:0] arb_uop_bits_stale_pdst; // @[execution-unit.scala:92:20]
wire [6:0] rrd_uop_bits_out_stale_pdst = arb_uop_bits_stale_pdst; // @[util.scala:104:23]
wire [6:0] arb_uop_bits_out_1_stale_pdst = arb_uop_bits_stale_pdst; // @[util.scala:104:23]
reg arb_uop_bits_exception; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_exception = arb_uop_bits_exception; // @[util.scala:104:23]
wire arb_uop_bits_out_1_exception = arb_uop_bits_exception; // @[util.scala:104:23]
reg [63:0] arb_uop_bits_exc_cause; // @[execution-unit.scala:92:20]
wire [63:0] rrd_uop_bits_out_exc_cause = arb_uop_bits_exc_cause; // @[util.scala:104:23]
wire [63:0] arb_uop_bits_out_1_exc_cause = arb_uop_bits_exc_cause; // @[util.scala:104:23]
reg [4:0] arb_uop_bits_mem_cmd; // @[execution-unit.scala:92:20]
wire [4:0] rrd_uop_bits_out_mem_cmd = arb_uop_bits_mem_cmd; // @[util.scala:104:23]
wire [4:0] arb_uop_bits_out_1_mem_cmd = arb_uop_bits_mem_cmd; // @[util.scala:104:23]
reg [1:0] arb_uop_bits_mem_size; // @[execution-unit.scala:92:20]
wire [1:0] rrd_uop_bits_out_mem_size = arb_uop_bits_mem_size; // @[util.scala:104:23]
wire [1:0] arb_uop_bits_out_1_mem_size = arb_uop_bits_mem_size; // @[util.scala:104:23]
reg arb_uop_bits_mem_signed; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_mem_signed = arb_uop_bits_mem_signed; // @[util.scala:104:23]
wire arb_uop_bits_out_1_mem_signed = arb_uop_bits_mem_signed; // @[util.scala:104:23]
reg arb_uop_bits_uses_ldq; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_uses_ldq = arb_uop_bits_uses_ldq; // @[util.scala:104:23]
wire arb_uop_bits_out_1_uses_ldq = arb_uop_bits_uses_ldq; // @[util.scala:104:23]
reg arb_uop_bits_uses_stq; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_uses_stq = arb_uop_bits_uses_stq; // @[util.scala:104:23]
wire arb_uop_bits_out_1_uses_stq = arb_uop_bits_uses_stq; // @[util.scala:104:23]
reg arb_uop_bits_is_unique; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_is_unique = arb_uop_bits_is_unique; // @[util.scala:104:23]
wire arb_uop_bits_out_1_is_unique = arb_uop_bits_is_unique; // @[util.scala:104:23]
reg arb_uop_bits_flush_on_commit; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_flush_on_commit = arb_uop_bits_flush_on_commit; // @[util.scala:104:23]
wire arb_uop_bits_out_1_flush_on_commit = arb_uop_bits_flush_on_commit; // @[util.scala:104:23]
reg [2:0] arb_uop_bits_csr_cmd; // @[execution-unit.scala:92:20]
wire [2:0] rrd_uop_bits_out_csr_cmd = arb_uop_bits_csr_cmd; // @[util.scala:104:23]
wire [2:0] arb_uop_bits_out_1_csr_cmd = arb_uop_bits_csr_cmd; // @[util.scala:104:23]
reg arb_uop_bits_ldst_is_rs1; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_ldst_is_rs1 = arb_uop_bits_ldst_is_rs1; // @[util.scala:104:23]
wire arb_uop_bits_out_1_ldst_is_rs1 = arb_uop_bits_ldst_is_rs1; // @[util.scala:104:23]
reg [5:0] arb_uop_bits_ldst; // @[execution-unit.scala:92:20]
wire [5:0] rrd_uop_bits_out_ldst = arb_uop_bits_ldst; // @[util.scala:104:23]
wire [5:0] arb_uop_bits_out_1_ldst = arb_uop_bits_ldst; // @[util.scala:104:23]
reg [5:0] arb_uop_bits_lrs1; // @[execution-unit.scala:92:20]
wire [5:0] rrd_uop_bits_out_lrs1 = arb_uop_bits_lrs1; // @[util.scala:104:23]
wire [5:0] arb_uop_bits_out_1_lrs1 = arb_uop_bits_lrs1; // @[util.scala:104:23]
reg [5:0] arb_uop_bits_lrs2; // @[execution-unit.scala:92:20]
wire [5:0] rrd_uop_bits_out_lrs2 = arb_uop_bits_lrs2; // @[util.scala:104:23]
wire [5:0] arb_uop_bits_out_1_lrs2 = arb_uop_bits_lrs2; // @[util.scala:104:23]
reg [5:0] arb_uop_bits_lrs3; // @[execution-unit.scala:92:20]
wire [5:0] rrd_uop_bits_out_lrs3 = arb_uop_bits_lrs3; // @[util.scala:104:23]
wire [5:0] arb_uop_bits_out_1_lrs3 = arb_uop_bits_lrs3; // @[util.scala:104:23]
reg [1:0] arb_uop_bits_dst_rtype; // @[execution-unit.scala:92:20]
wire [1:0] rrd_uop_bits_out_dst_rtype = arb_uop_bits_dst_rtype; // @[util.scala:104:23]
wire [1:0] arb_uop_bits_out_1_dst_rtype = arb_uop_bits_dst_rtype; // @[util.scala:104:23]
reg [1:0] arb_uop_bits_lrs1_rtype; // @[execution-unit.scala:92:20]
wire [1:0] rrd_uop_bits_out_lrs1_rtype = arb_uop_bits_lrs1_rtype; // @[util.scala:104:23]
wire [1:0] arb_uop_bits_out_1_lrs1_rtype = arb_uop_bits_lrs1_rtype; // @[util.scala:104:23]
reg [1:0] arb_uop_bits_lrs2_rtype; // @[execution-unit.scala:92:20]
wire [1:0] rrd_uop_bits_out_lrs2_rtype = arb_uop_bits_lrs2_rtype; // @[util.scala:104:23]
wire [1:0] arb_uop_bits_out_1_lrs2_rtype = arb_uop_bits_lrs2_rtype; // @[util.scala:104:23]
reg arb_uop_bits_frs3_en; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_frs3_en = arb_uop_bits_frs3_en; // @[util.scala:104:23]
wire arb_uop_bits_out_1_frs3_en = arb_uop_bits_frs3_en; // @[util.scala:104:23]
reg arb_uop_bits_fcn_dw; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_fcn_dw = arb_uop_bits_fcn_dw; // @[util.scala:104:23]
wire arb_uop_bits_out_1_fcn_dw = arb_uop_bits_fcn_dw; // @[util.scala:104:23]
reg [4:0] arb_uop_bits_fcn_op; // @[execution-unit.scala:92:20]
wire [4:0] rrd_uop_bits_out_fcn_op = arb_uop_bits_fcn_op; // @[util.scala:104:23]
wire [4:0] arb_uop_bits_out_1_fcn_op = arb_uop_bits_fcn_op; // @[util.scala:104:23]
reg arb_uop_bits_fp_val; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_fp_val = arb_uop_bits_fp_val; // @[util.scala:104:23]
wire arb_uop_bits_out_1_fp_val = arb_uop_bits_fp_val; // @[util.scala:104:23]
reg [2:0] arb_uop_bits_fp_rm; // @[execution-unit.scala:92:20]
wire [2:0] rrd_uop_bits_out_fp_rm = arb_uop_bits_fp_rm; // @[util.scala:104:23]
wire [2:0] arb_uop_bits_out_1_fp_rm = arb_uop_bits_fp_rm; // @[util.scala:104:23]
reg [1:0] arb_uop_bits_fp_typ; // @[execution-unit.scala:92:20]
wire [1:0] rrd_uop_bits_out_fp_typ = arb_uop_bits_fp_typ; // @[util.scala:104:23]
wire [1:0] arb_uop_bits_out_1_fp_typ = arb_uop_bits_fp_typ; // @[util.scala:104:23]
reg arb_uop_bits_xcpt_pf_if; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_xcpt_pf_if = arb_uop_bits_xcpt_pf_if; // @[util.scala:104:23]
wire arb_uop_bits_out_1_xcpt_pf_if = arb_uop_bits_xcpt_pf_if; // @[util.scala:104:23]
reg arb_uop_bits_xcpt_ae_if; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_xcpt_ae_if = arb_uop_bits_xcpt_ae_if; // @[util.scala:104:23]
wire arb_uop_bits_out_1_xcpt_ae_if = arb_uop_bits_xcpt_ae_if; // @[util.scala:104:23]
reg arb_uop_bits_xcpt_ma_if; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_xcpt_ma_if = arb_uop_bits_xcpt_ma_if; // @[util.scala:104:23]
wire arb_uop_bits_out_1_xcpt_ma_if = arb_uop_bits_xcpt_ma_if; // @[util.scala:104:23]
reg arb_uop_bits_bp_debug_if; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_bp_debug_if = arb_uop_bits_bp_debug_if; // @[util.scala:104:23]
wire arb_uop_bits_out_1_bp_debug_if = arb_uop_bits_bp_debug_if; // @[util.scala:104:23]
reg arb_uop_bits_bp_xcpt_if; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_bp_xcpt_if = arb_uop_bits_bp_xcpt_if; // @[util.scala:104:23]
wire arb_uop_bits_out_1_bp_xcpt_if = arb_uop_bits_bp_xcpt_if; // @[util.scala:104:23]
reg [2:0] arb_uop_bits_debug_fsrc; // @[execution-unit.scala:92:20]
wire [2:0] rrd_uop_bits_out_debug_fsrc = arb_uop_bits_debug_fsrc; // @[util.scala:104:23]
wire [2:0] arb_uop_bits_out_1_debug_fsrc = arb_uop_bits_debug_fsrc; // @[util.scala:104:23]
reg [2:0] arb_uop_bits_debug_tsrc; // @[execution-unit.scala:92:20]
wire [2:0] rrd_uop_bits_out_debug_tsrc = arb_uop_bits_debug_tsrc; // @[util.scala:104:23]
wire [2:0] arb_uop_bits_out_1_debug_tsrc = arb_uop_bits_debug_tsrc; // @[util.scala:104:23]
wire [11:0] _arb_uop_valid_T = io_brupdate_b1_mispredict_mask & io_iss_uop_bits_br_mask; // @[util.scala:126:51]
wire _arb_uop_valid_T_1 = |_arb_uop_valid_T; // @[util.scala:126:{51,59}]
wire _arb_uop_valid_T_2 = _arb_uop_valid_T_1 | io_kill; // @[util.scala:61:61, :126:59]
wire _arb_uop_valid_T_3 = ~_arb_uop_valid_T_2; // @[util.scala:61:61]
wire _arb_uop_valid_T_4 = io_iss_uop_valid & _arb_uop_valid_T_3; // @[execution-unit.scala:93:{37,40}]
wire [11:0] _arb_uop_bits_out_br_mask_T_1; // @[util.scala:93:25]
wire [11:0] arb_uop_bits_out_br_mask; // @[util.scala:104:23]
wire [11:0] _arb_uop_bits_out_br_mask_T = ~io_brupdate_b1_resolve_mask; // @[util.scala:93:27]
assign _arb_uop_bits_out_br_mask_T_1 = io_iss_uop_bits_br_mask & _arb_uop_bits_out_br_mask_T; // @[util.scala:93:{25,27}]
assign arb_uop_bits_out_br_mask = _arb_uop_bits_out_br_mask_T_1; // @[util.scala:93:25, :104:23]
reg rrd_uop_valid; // @[execution-unit.scala:95:20]
wire [31:0] exe_uop_bits_out_inst = rrd_uop_bits_inst; // @[util.scala:104:23]
wire [31:0] exe_uop_bits_out_debug_inst = rrd_uop_bits_debug_inst; // @[util.scala:104:23]
wire exe_uop_bits_out_is_rvc = rrd_uop_bits_is_rvc; // @[util.scala:104:23]
wire [39:0] exe_uop_bits_out_debug_pc = rrd_uop_bits_debug_pc; // @[util.scala:104:23]
wire exe_uop_bits_out_iq_type_0 = rrd_uop_bits_iq_type_0; // @[util.scala:104:23]
wire exe_uop_bits_out_iq_type_1 = rrd_uop_bits_iq_type_1; // @[util.scala:104:23]
wire exe_uop_bits_out_iq_type_2 = rrd_uop_bits_iq_type_2; // @[util.scala:104:23]
wire exe_uop_bits_out_iq_type_3 = rrd_uop_bits_iq_type_3; // @[util.scala:104:23]
wire exe_uop_bits_out_fu_code_0 = rrd_uop_bits_fu_code_0; // @[util.scala:104:23]
wire exe_uop_bits_out_fu_code_1 = rrd_uop_bits_fu_code_1; // @[util.scala:104:23]
wire exe_uop_bits_out_fu_code_2 = rrd_uop_bits_fu_code_2; // @[util.scala:104:23]
wire exe_uop_bits_out_fu_code_3 = rrd_uop_bits_fu_code_3; // @[util.scala:104:23]
wire exe_uop_bits_out_fu_code_4 = rrd_uop_bits_fu_code_4; // @[util.scala:104:23]
wire exe_uop_bits_out_fu_code_5 = rrd_uop_bits_fu_code_5; // @[util.scala:104:23]
wire exe_uop_bits_out_fu_code_6 = rrd_uop_bits_fu_code_6; // @[util.scala:104:23]
wire exe_uop_bits_out_fu_code_7 = rrd_uop_bits_fu_code_7; // @[util.scala:104:23]
wire exe_uop_bits_out_fu_code_8 = rrd_uop_bits_fu_code_8; // @[util.scala:104:23]
wire exe_uop_bits_out_fu_code_9 = rrd_uop_bits_fu_code_9; // @[util.scala:104:23]
wire exe_uop_bits_out_iw_issued = rrd_uop_bits_iw_issued; // @[util.scala:104:23]
wire exe_uop_bits_out_iw_issued_partial_agen = rrd_uop_bits_iw_issued_partial_agen; // @[util.scala:104:23]
wire exe_uop_bits_out_iw_issued_partial_dgen = rrd_uop_bits_iw_issued_partial_dgen; // @[util.scala:104:23]
wire [1:0] exe_uop_bits_out_iw_p1_speculative_child = rrd_uop_bits_iw_p1_speculative_child; // @[util.scala:104:23]
wire [1:0] exe_uop_bits_out_iw_p2_speculative_child = rrd_uop_bits_iw_p2_speculative_child; // @[util.scala:104:23]
wire exe_uop_bits_out_iw_p1_bypass_hint = rrd_uop_bits_iw_p1_bypass_hint; // @[util.scala:104:23]
wire exe_uop_bits_out_iw_p2_bypass_hint = rrd_uop_bits_iw_p2_bypass_hint; // @[util.scala:104:23]
wire exe_uop_bits_out_iw_p3_bypass_hint = rrd_uop_bits_iw_p3_bypass_hint; // @[util.scala:104:23]
wire [1:0] exe_uop_bits_out_dis_col_sel = rrd_uop_bits_dis_col_sel; // @[util.scala:104:23]
wire [3:0] exe_uop_bits_out_br_tag = rrd_uop_bits_br_tag; // @[util.scala:104:23]
wire [3:0] exe_uop_bits_out_br_type = rrd_uop_bits_br_type; // @[util.scala:104:23]
wire exe_uop_bits_out_is_sfb = rrd_uop_bits_is_sfb; // @[util.scala:104:23]
wire exe_uop_bits_out_is_fence = rrd_uop_bits_is_fence; // @[util.scala:104:23]
wire exe_uop_bits_out_is_fencei = rrd_uop_bits_is_fencei; // @[util.scala:104:23]
wire exe_uop_bits_out_is_sfence = rrd_uop_bits_is_sfence; // @[util.scala:104:23]
wire exe_uop_bits_out_is_amo = rrd_uop_bits_is_amo; // @[util.scala:104:23]
wire exe_uop_bits_out_is_eret = rrd_uop_bits_is_eret; // @[util.scala:104:23]
wire exe_uop_bits_out_is_sys_pc2epc = rrd_uop_bits_is_sys_pc2epc; // @[util.scala:104:23]
wire exe_uop_bits_out_is_rocc = rrd_uop_bits_is_rocc; // @[util.scala:104:23]
wire exe_uop_bits_out_is_mov = rrd_uop_bits_is_mov; // @[util.scala:104:23]
wire [4:0] exe_uop_bits_out_ftq_idx = rrd_uop_bits_ftq_idx; // @[util.scala:104:23]
wire exe_uop_bits_out_edge_inst = rrd_uop_bits_edge_inst; // @[util.scala:104:23]
wire [5:0] exe_uop_bits_out_pc_lob = rrd_uop_bits_pc_lob; // @[util.scala:104:23]
wire exe_uop_bits_out_taken = rrd_uop_bits_taken; // @[util.scala:104:23]
wire exe_uop_bits_out_imm_rename = rrd_uop_bits_imm_rename; // @[util.scala:104:23]
wire [2:0] exe_uop_bits_out_imm_sel = rrd_uop_bits_imm_sel; // @[util.scala:104:23]
wire [4:0] exe_uop_bits_out_pimm = rrd_uop_bits_pimm; // @[util.scala:104:23]
wire [19:0] exe_uop_bits_out_imm_packed = rrd_uop_bits_imm_packed; // @[util.scala:104:23]
wire [1:0] exe_uop_bits_out_op1_sel = rrd_uop_bits_op1_sel; // @[util.scala:104:23]
wire [2:0] exe_uop_bits_out_op2_sel = rrd_uop_bits_op2_sel; // @[util.scala:104:23]
wire exe_uop_bits_out_fp_ctrl_ldst = rrd_uop_bits_fp_ctrl_ldst; // @[util.scala:104:23]
wire exe_uop_bits_out_fp_ctrl_wen = rrd_uop_bits_fp_ctrl_wen; // @[util.scala:104:23]
wire exe_uop_bits_out_fp_ctrl_ren1 = rrd_uop_bits_fp_ctrl_ren1; // @[util.scala:104:23]
wire exe_uop_bits_out_fp_ctrl_ren2 = rrd_uop_bits_fp_ctrl_ren2; // @[util.scala:104:23]
wire exe_uop_bits_out_fp_ctrl_ren3 = rrd_uop_bits_fp_ctrl_ren3; // @[util.scala:104:23]
wire exe_uop_bits_out_fp_ctrl_swap12 = rrd_uop_bits_fp_ctrl_swap12; // @[util.scala:104:23]
wire exe_uop_bits_out_fp_ctrl_swap23 = rrd_uop_bits_fp_ctrl_swap23; // @[util.scala:104:23]
wire [1:0] exe_uop_bits_out_fp_ctrl_typeTagIn = rrd_uop_bits_fp_ctrl_typeTagIn; // @[util.scala:104:23]
wire [1:0] exe_uop_bits_out_fp_ctrl_typeTagOut = rrd_uop_bits_fp_ctrl_typeTagOut; // @[util.scala:104:23]
wire exe_uop_bits_out_fp_ctrl_fromint = rrd_uop_bits_fp_ctrl_fromint; // @[util.scala:104:23]
wire exe_uop_bits_out_fp_ctrl_toint = rrd_uop_bits_fp_ctrl_toint; // @[util.scala:104:23]
wire exe_uop_bits_out_fp_ctrl_fastpipe = rrd_uop_bits_fp_ctrl_fastpipe; // @[util.scala:104:23]
wire exe_uop_bits_out_fp_ctrl_fma = rrd_uop_bits_fp_ctrl_fma; // @[util.scala:104:23]
wire exe_uop_bits_out_fp_ctrl_div = rrd_uop_bits_fp_ctrl_div; // @[util.scala:104:23]
wire exe_uop_bits_out_fp_ctrl_sqrt = rrd_uop_bits_fp_ctrl_sqrt; // @[util.scala:104:23]
wire exe_uop_bits_out_fp_ctrl_wflags = rrd_uop_bits_fp_ctrl_wflags; // @[util.scala:104:23]
wire exe_uop_bits_out_fp_ctrl_vec = rrd_uop_bits_fp_ctrl_vec; // @[util.scala:104:23]
wire [5:0] exe_uop_bits_out_rob_idx = rrd_uop_bits_rob_idx; // @[util.scala:104:23]
wire [3:0] exe_uop_bits_out_ldq_idx = rrd_uop_bits_ldq_idx; // @[util.scala:104:23]
wire [3:0] exe_uop_bits_out_stq_idx = rrd_uop_bits_stq_idx; // @[util.scala:104:23]
wire [1:0] exe_uop_bits_out_rxq_idx = rrd_uop_bits_rxq_idx; // @[util.scala:104:23]
wire [6:0] exe_uop_bits_out_pdst = rrd_uop_bits_pdst; // @[util.scala:104:23]
wire [6:0] exe_uop_bits_out_prs1 = rrd_uop_bits_prs1; // @[util.scala:104:23]
wire [6:0] exe_uop_bits_out_prs2 = rrd_uop_bits_prs2; // @[util.scala:104:23]
wire [6:0] exe_uop_bits_out_prs3 = rrd_uop_bits_prs3; // @[util.scala:104:23]
wire [4:0] exe_uop_bits_out_ppred = rrd_uop_bits_ppred; // @[util.scala:104:23]
wire exe_uop_bits_out_prs1_busy = rrd_uop_bits_prs1_busy; // @[util.scala:104:23]
wire exe_uop_bits_out_prs2_busy = rrd_uop_bits_prs2_busy; // @[util.scala:104:23]
wire exe_uop_bits_out_prs3_busy = rrd_uop_bits_prs3_busy; // @[util.scala:104:23]
wire exe_uop_bits_out_ppred_busy = rrd_uop_bits_ppred_busy; // @[util.scala:104:23]
wire [6:0] exe_uop_bits_out_stale_pdst = rrd_uop_bits_stale_pdst; // @[util.scala:104:23]
wire exe_uop_bits_out_exception = rrd_uop_bits_exception; // @[util.scala:104:23]
wire [63:0] exe_uop_bits_out_exc_cause = rrd_uop_bits_exc_cause; // @[util.scala:104:23]
wire [4:0] exe_uop_bits_out_mem_cmd = rrd_uop_bits_mem_cmd; // @[util.scala:104:23]
wire [1:0] exe_uop_bits_out_mem_size = rrd_uop_bits_mem_size; // @[util.scala:104:23]
wire exe_uop_bits_out_mem_signed = rrd_uop_bits_mem_signed; // @[util.scala:104:23]
wire exe_uop_bits_out_uses_ldq = rrd_uop_bits_uses_ldq; // @[util.scala:104:23]
wire exe_uop_bits_out_uses_stq = rrd_uop_bits_uses_stq; // @[util.scala:104:23]
wire exe_uop_bits_out_is_unique = rrd_uop_bits_is_unique; // @[util.scala:104:23]
wire exe_uop_bits_out_flush_on_commit = rrd_uop_bits_flush_on_commit; // @[util.scala:104:23]
wire [2:0] exe_uop_bits_out_csr_cmd = rrd_uop_bits_csr_cmd; // @[util.scala:104:23]
wire exe_uop_bits_out_ldst_is_rs1 = rrd_uop_bits_ldst_is_rs1; // @[util.scala:104:23]
wire [5:0] exe_uop_bits_out_ldst = rrd_uop_bits_ldst; // @[util.scala:104:23]
wire [5:0] exe_uop_bits_out_lrs1 = rrd_uop_bits_lrs1; // @[util.scala:104:23]
wire [5:0] exe_uop_bits_out_lrs2 = rrd_uop_bits_lrs2; // @[util.scala:104:23]
wire [5:0] exe_uop_bits_out_lrs3 = rrd_uop_bits_lrs3; // @[util.scala:104:23]
wire [1:0] exe_uop_bits_out_dst_rtype = rrd_uop_bits_dst_rtype; // @[util.scala:104:23]
wire [1:0] exe_uop_bits_out_lrs1_rtype = rrd_uop_bits_lrs1_rtype; // @[util.scala:104:23]
wire [1:0] exe_uop_bits_out_lrs2_rtype = rrd_uop_bits_lrs2_rtype; // @[util.scala:104:23]
wire exe_uop_bits_out_frs3_en = rrd_uop_bits_frs3_en; // @[util.scala:104:23]
wire exe_uop_bits_out_fcn_dw = rrd_uop_bits_fcn_dw; // @[util.scala:104:23]
wire [4:0] exe_uop_bits_out_fcn_op = rrd_uop_bits_fcn_op; // @[util.scala:104:23]
wire exe_uop_bits_out_fp_val = rrd_uop_bits_fp_val; // @[util.scala:104:23]
wire [2:0] exe_uop_bits_out_fp_rm = rrd_uop_bits_fp_rm; // @[util.scala:104:23]
wire [1:0] exe_uop_bits_out_fp_typ = rrd_uop_bits_fp_typ; // @[util.scala:104:23]
wire exe_uop_bits_out_xcpt_pf_if = rrd_uop_bits_xcpt_pf_if; // @[util.scala:104:23]
wire exe_uop_bits_out_xcpt_ae_if = rrd_uop_bits_xcpt_ae_if; // @[util.scala:104:23]
wire exe_uop_bits_out_xcpt_ma_if = rrd_uop_bits_xcpt_ma_if; // @[util.scala:104:23]
wire exe_uop_bits_out_bp_debug_if = rrd_uop_bits_bp_debug_if; // @[util.scala:104:23]
wire exe_uop_bits_out_bp_xcpt_if = rrd_uop_bits_bp_xcpt_if; // @[util.scala:104:23]
wire [2:0] exe_uop_bits_out_debug_fsrc = rrd_uop_bits_debug_fsrc; // @[util.scala:104:23]
wire [2:0] exe_uop_bits_out_debug_tsrc = rrd_uop_bits_debug_tsrc; // @[util.scala:104:23]
wire [11:0] _GEN = io_brupdate_b1_mispredict_mask & arb_uop_bits_br_mask; // @[util.scala:126:51]
wire [11:0] _rrd_uop_valid_T; // @[util.scala:126:51]
assign _rrd_uop_valid_T = _GEN; // @[util.scala:126:51]
wire [11:0] _will_replay_T; // @[util.scala:126:51]
assign _will_replay_T = _GEN; // @[util.scala:126:51]
wire _rrd_uop_valid_T_1 = |_rrd_uop_valid_T; // @[util.scala:126:{51,59}]
wire _rrd_uop_valid_T_2 = _rrd_uop_valid_T_1 | io_kill; // @[util.scala:61:61, :126:59]
wire _rrd_uop_valid_T_3 = ~_rrd_uop_valid_T_2; // @[util.scala:61:61]
wire _rrd_uop_valid_T_4 = arb_uop_valid & _rrd_uop_valid_T_3; // @[execution-unit.scala:92:20, :96:{34,37}]
wire [11:0] _rrd_uop_bits_out_br_mask_T_1; // @[util.scala:93:25]
wire [11:0] rrd_uop_bits_out_br_mask; // @[util.scala:104:23]
wire [11:0] _rrd_uop_bits_out_br_mask_T = ~io_brupdate_b1_resolve_mask; // @[util.scala:93:27]
assign _rrd_uop_bits_out_br_mask_T_1 = arb_uop_bits_br_mask & _rrd_uop_bits_out_br_mask_T; // @[util.scala:93:{25,27}]
assign rrd_uop_bits_out_br_mask = _rrd_uop_bits_out_br_mask_T_1; // @[util.scala:93:25, :104:23]
reg exe_uop_valid; // @[execution-unit.scala:98:20]
wire [11:0] _exe_uop_valid_T = io_brupdate_b1_mispredict_mask & rrd_uop_bits_br_mask; // @[util.scala:126:51]
wire _exe_uop_valid_T_1 = |_exe_uop_valid_T; // @[util.scala:126:{51,59}]
wire _exe_uop_valid_T_2 = _exe_uop_valid_T_1 | io_kill; // @[util.scala:61:61, :126:59]
wire _exe_uop_valid_T_3 = ~_exe_uop_valid_T_2; // @[util.scala:61:61]
wire _exe_uop_valid_T_4 = rrd_uop_valid & _exe_uop_valid_T_3; // @[execution-unit.scala:95:20, :99:{34,37}]
wire [11:0] _exe_uop_bits_out_br_mask_T_1; // @[util.scala:93:25]
wire [11:0] exe_uop_bits_out_br_mask; // @[util.scala:104:23]
wire [11:0] _exe_uop_bits_out_br_mask_T = ~io_brupdate_b1_resolve_mask; // @[util.scala:93:27]
assign _exe_uop_bits_out_br_mask_T_1 = rrd_uop_bits_br_mask & _exe_uop_bits_out_br_mask_T; // @[util.scala:93:{25,27}]
assign exe_uop_bits_out_br_mask = _exe_uop_bits_out_br_mask_T_1; // @[util.scala:93:25, :104:23]
wire _GEN_0 = arb_uop_bits_lrs1_rtype == 2'h0; // @[execution-unit.scala:92:20, :121:72]
wire _io_arb_irf_reqs_0_valid_T; // @[execution-unit.scala:121:72]
assign _io_arb_irf_reqs_0_valid_T = _GEN_0; // @[execution-unit.scala:121:72]
wire _arb_rebusied_prs1_T; // @[execution-unit.scala:128:51]
assign _arb_rebusied_prs1_T = _GEN_0; // @[execution-unit.scala:121:72, :128:51]
wire _io_arb_irf_reqs_0_valid_T_1 = arb_uop_valid & _io_arb_irf_reqs_0_valid_T; // @[execution-unit.scala:92:20, :121:{45,72}]
wire _io_arb_irf_reqs_0_valid_T_2 = ~arb_uop_bits_iw_p1_bypass_hint; // @[execution-unit.scala:92:20, :121:86]
assign _io_arb_irf_reqs_0_valid_T_3 = _io_arb_irf_reqs_0_valid_T_1 & _io_arb_irf_reqs_0_valid_T_2; // @[execution-unit.scala:121:{45,83,86}]
assign io_arb_irf_reqs_0_valid_0 = _io_arb_irf_reqs_0_valid_T_3; // @[execution-unit.scala:121:83, :255:7]
wire _GEN_1 = io_arb_rebusys_0_valid & io_arb_rebusys_0_bits_rebusy; // @[execution-unit.scala:118:39]
wire _arb_rebusied_prs1_T_1; // @[execution-unit.scala:118:39]
assign _arb_rebusied_prs1_T_1 = _GEN_1; // @[execution-unit.scala:118:39]
wire _arb_rebusied_prs2_T_1; // @[execution-unit.scala:118:39]
assign _arb_rebusied_prs2_T_1 = _GEN_1; // @[execution-unit.scala:118:39]
wire _arb_rebusied_prs1_T_2 = io_arb_rebusys_0_bits_uop_pdst == arb_uop_bits_prs1; // @[execution-unit.scala:92:20, :118:75]
wire _arb_rebusied_prs1_T_3 = _arb_rebusied_prs1_T_1 & _arb_rebusied_prs1_T_2; // @[execution-unit.scala:118:{39,56,75}]
wire arb_rebusied_prs1 = _arb_rebusied_prs1_T & _arb_rebusied_prs1_T_3; // @[execution-unit.scala:118:56, :128:{51,62}]
wire arb_rebusied = arb_rebusied_prs1; // @[execution-unit.scala:128:62, :130:45]
wire _arb_rebusied_prs2_T = arb_uop_bits_lrs2_rtype == 2'h0; // @[execution-unit.scala:92:20, :129:51]
wire _arb_rebusied_prs2_T_2 = io_arb_rebusys_0_bits_uop_pdst == arb_uop_bits_prs2; // @[execution-unit.scala:92:20, :118:75]
wire _arb_rebusied_prs2_T_3 = _arb_rebusied_prs2_T_1 & _arb_rebusied_prs2_T_2; // @[execution-unit.scala:118:{39,56,75}]
wire _arb_rebusied_prs2_T_4 = _arb_rebusied_prs2_T & _arb_rebusied_prs2_T_3; // @[execution-unit.scala:118:56, :129:{51,62}]
wire _hits_T = rrd_uop_bits_prs1 == io_rrd_irf_bypasses_0_bits_uop_pdst; // @[execution-unit.scala:95:20, :113:62]
wire hits_0 = io_rrd_irf_bypasses_0_valid & _hits_T; // @[execution-unit.scala:113:{55,62}]
wire _hits_T_1 = rrd_uop_bits_prs1 == io_rrd_irf_bypasses_1_bits_uop_pdst; // @[execution-unit.scala:95:20, :113:62]
wire hits_1 = io_rrd_irf_bypasses_1_valid & _hits_T_1; // @[execution-unit.scala:113:{55,62}]
wire _hits_T_2 = rrd_uop_bits_prs1 == io_rrd_irf_bypasses_2_bits_uop_pdst; // @[execution-unit.scala:95:20, :113:62]
wire hits_2 = io_rrd_irf_bypasses_2_valid & _hits_T_2; // @[execution-unit.scala:113:{55,62}]
wire _T_1 = hits_0 | hits_1; // @[execution-unit.scala:113:55, :114:19]
wire rs1_hit = _T_1 | hits_2; // @[execution-unit.scala:113:55, :114:19]
wire [63:0] rs1_data = _T_1 | hits_2 ? (hits_0 ? io_rrd_irf_bypasses_0_bits_data : 64'h0) | (hits_1 ? io_rrd_irf_bypasses_1_bits_data : 64'h0) | (hits_2 ? io_rrd_irf_bypasses_2_bits_data : 64'h0) : io_rrd_irf_resps_0; // @[Mux.scala:30:73]
wire _exe_rs1_data_T = &rrd_uop_bits_lrs1_rtype; // @[execution-unit.scala:95:20, :137:47]
wire [63:0] _exe_rs1_data_T_1 = _exe_rs1_data_T ? 64'h0 : rs1_data; // @[execution-unit.scala:114:28, :137:{22,47}]
wire _io_arb_immrf_req_valid_T = arb_uop_bits_imm_sel == 3'h6; // @[package.scala:16:47]
wire _io_arb_immrf_req_valid_T_1 = arb_uop_bits_imm_sel == 3'h5; // @[package.scala:16:47]
wire _io_arb_immrf_req_valid_T_2 = _io_arb_immrf_req_valid_T | _io_arb_immrf_req_valid_T_1; // @[package.scala:16:47, :81:59]
wire _io_arb_immrf_req_valid_T_3 = ~_io_arb_immrf_req_valid_T_2; // @[package.scala:81:59]
assign _io_arb_immrf_req_valid_T_4 = arb_uop_valid & _io_arb_immrf_req_valid_T_3; // @[execution-unit.scala:92:20, :157:44, :158:5]
assign io_arb_immrf_req_valid_0 = _io_arb_immrf_req_valid_T_4; // @[execution-unit.scala:157:44, :255:7]
wire _GEN_2 = rrd_uop_bits_imm_sel == 3'h6; // @[package.scala:16:47]
wire _io_rrd_immrf_wakeup_valid_T; // @[package.scala:16:47]
assign _io_rrd_immrf_wakeup_valid_T = _GEN_2; // @[package.scala:16:47]
wire _exe_imm_data_ip_T; // @[util.scala:282:23]
assign _exe_imm_data_ip_T = _GEN_2; // @[package.scala:16:47]
wire _GEN_3 = rrd_uop_bits_imm_sel == 3'h5; // @[package.scala:16:47]
wire _io_rrd_immrf_wakeup_valid_T_1; // @[package.scala:16:47]
assign _io_rrd_immrf_wakeup_valid_T_1 = _GEN_3; // @[package.scala:16:47]
wire _exe_imm_data_T; // @[execution-unit.scala:170:55]
assign _exe_imm_data_T = _GEN_3; // @[package.scala:16:47]
wire _io_rrd_immrf_wakeup_valid_T_2 = _io_rrd_immrf_wakeup_valid_T | _io_rrd_immrf_wakeup_valid_T_1; // @[package.scala:16:47, :81:59]
wire _io_rrd_immrf_wakeup_valid_T_3 = ~_io_rrd_immrf_wakeup_valid_T_2; // @[package.scala:81:59]
assign _io_rrd_immrf_wakeup_valid_T_4 = rrd_uop_valid & _io_rrd_immrf_wakeup_valid_T_3; // @[execution-unit.scala:95:20, :162:47, :163:5]
wire _exe_imm_data_T_1 = rrd_uop_bits_pimm[4]; // @[util.scala:269:46]
wire [58:0] _exe_imm_data_T_2 = {59{_exe_imm_data_T_1}}; // @[util.scala:269:{25,46}]
wire [63:0] _exe_imm_data_T_3 = {_exe_imm_data_T_2, rrd_uop_bits_pimm}; // @[util.scala:269:{20,25}]
wire [63:0] exe_imm_data_ip = _exe_imm_data_ip_T ? 64'h0 : io_rrd_immrf_resp; // @[util.scala:282:{17,23}]
wire _exe_imm_data_sign_T = exe_imm_data_ip[19]; // @[util.scala:282:17, :284:18]
wire exe_imm_data_sign = _exe_imm_data_sign_T; // @[util.scala:284:{18,37}]
wire exe_imm_data_hi_hi_hi = exe_imm_data_sign; // @[util.scala:284:37, :294:15]
wire _GEN_4 = rrd_uop_bits_imm_sel == 3'h3; // @[util.scala:285:27]
wire _exe_imm_data_i30_20_T; // @[util.scala:285:27]
assign _exe_imm_data_i30_20_T = _GEN_4; // @[util.scala:285:27]
wire _exe_imm_data_i19_12_T; // @[util.scala:286:27]
assign _exe_imm_data_i19_12_T = _GEN_4; // @[util.scala:285:27, :286:27]
wire _exe_imm_data_i11_T; // @[util.scala:287:27]
assign _exe_imm_data_i11_T = _GEN_4; // @[util.scala:285:27, :287:27]
wire _exe_imm_data_i10_5_T; // @[util.scala:289:27]
assign _exe_imm_data_i10_5_T = _GEN_4; // @[util.scala:285:27, :289:27]
wire _exe_imm_data_i4_1_T; // @[util.scala:290:27]
assign _exe_imm_data_i4_1_T = _GEN_4; // @[util.scala:285:27, :290:27]
wire [10:0] _exe_imm_data_i30_20_T_1 = exe_imm_data_ip[18:8]; // @[util.scala:282:17, :285:39]
wire [10:0] _exe_imm_data_i30_20_T_2 = _exe_imm_data_i30_20_T_1; // @[util.scala:285:{39,46}]
wire [10:0] exe_imm_data_i30_20 = _exe_imm_data_i30_20_T ? _exe_imm_data_i30_20_T_2 : {11{exe_imm_data_sign}}; // @[util.scala:284:37, :285:{21,27,46}]
wire [10:0] exe_imm_data_hi_hi_lo = exe_imm_data_i30_20; // @[util.scala:285:21, :294:15]
wire _GEN_5 = rrd_uop_bits_imm_sel == 3'h4; // @[util.scala:286:44]
wire _exe_imm_data_i19_12_T_1; // @[util.scala:286:44]
assign _exe_imm_data_i19_12_T_1 = _GEN_5; // @[util.scala:286:44]
wire _exe_imm_data_i11_T_1; // @[util.scala:288:27]
assign _exe_imm_data_i11_T_1 = _GEN_5; // @[util.scala:286:44, :288:27]
wire _exe_imm_data_i19_12_T_2 = _exe_imm_data_i19_12_T | _exe_imm_data_i19_12_T_1; // @[util.scala:286:{27,36,44}]
wire [7:0] _exe_imm_data_i19_12_T_3 = exe_imm_data_ip[7:0]; // @[util.scala:282:17, :286:56]
wire [7:0] _exe_imm_data_i19_12_T_4 = _exe_imm_data_i19_12_T_3; // @[util.scala:286:{56,62}]
wire [7:0] exe_imm_data_i19_12 = _exe_imm_data_i19_12_T_2 ? _exe_imm_data_i19_12_T_4 : {8{exe_imm_data_sign}}; // @[util.scala:284:37, :286:{21,36,62}]
wire [7:0] exe_imm_data_hi_lo_hi = exe_imm_data_i19_12; // @[util.scala:286:21, :294:15]
wire _exe_imm_data_i11_T_2 = rrd_uop_bits_imm_sel == 3'h2; // @[util.scala:288:44]
wire _exe_imm_data_i11_T_3 = _exe_imm_data_i11_T_1 | _exe_imm_data_i11_T_2; // @[util.scala:288:{27,36,44}]
wire _exe_imm_data_i11_T_4 = exe_imm_data_ip[8]; // @[util.scala:282:17, :288:56]
wire _exe_imm_data_i0_T_3 = exe_imm_data_ip[8]; // @[util.scala:282:17, :288:56, :291:56]
wire _exe_imm_data_i11_T_5 = _exe_imm_data_i11_T_4; // @[util.scala:288:{56,60}]
wire _exe_imm_data_i11_T_6 = _exe_imm_data_i11_T_3 ? _exe_imm_data_i11_T_5 : exe_imm_data_sign; // @[util.scala:284:37, :288:{21,36,60}]
wire exe_imm_data_i11 = ~_exe_imm_data_i11_T & _exe_imm_data_i11_T_6; // @[util.scala:287:{21,27}, :288:21]
wire exe_imm_data_hi_lo_lo = exe_imm_data_i11; // @[util.scala:287:21, :294:15]
wire [4:0] _exe_imm_data_i10_5_T_1 = exe_imm_data_ip[18:14]; // @[util.scala:282:17, :289:44]
wire [4:0] _exe_imm_data_i10_5_T_2 = _exe_imm_data_i10_5_T_1; // @[util.scala:289:{44,52}]
wire [4:0] exe_imm_data_i10_5 = _exe_imm_data_i10_5_T ? 5'h0 : _exe_imm_data_i10_5_T_2; // @[util.scala:289:{21,27,52}]
wire [4:0] exe_imm_data_lo_hi_hi = exe_imm_data_i10_5; // @[util.scala:289:21, :294:15]
wire [4:0] _exe_imm_data_i4_1_T_1 = exe_imm_data_ip[13:9]; // @[util.scala:282:17, :290:44]
wire [4:0] _exe_imm_data_i4_1_T_2 = _exe_imm_data_i4_1_T_1; // @[util.scala:290:{44,51}]
wire [4:0] exe_imm_data_i4_1 = _exe_imm_data_i4_1_T ? 5'h0 : _exe_imm_data_i4_1_T_2; // @[util.scala:290:{21,27,51}]
wire [4:0] exe_imm_data_lo_hi_lo = exe_imm_data_i4_1; // @[util.scala:290:21, :294:15]
wire _exe_imm_data_i0_T = rrd_uop_bits_imm_sel == 3'h1; // @[util.scala:291:27]
wire _exe_imm_data_i0_T_1 = rrd_uop_bits_imm_sel == 3'h0; // @[util.scala:291:44]
wire _exe_imm_data_i0_T_2 = _exe_imm_data_i0_T | _exe_imm_data_i0_T_1; // @[util.scala:291:{27,36,44}]
wire _exe_imm_data_i0_T_4 = _exe_imm_data_i0_T_3; // @[util.scala:291:{56,60}]
wire exe_imm_data_i0 = _exe_imm_data_i0_T_2 & _exe_imm_data_i0_T_4; // @[util.scala:291:{21,36,60}]
wire exe_imm_data_lo_lo = exe_imm_data_i0; // @[util.scala:291:21, :294:15]
wire [9:0] exe_imm_data_lo_hi = {exe_imm_data_lo_hi_hi, exe_imm_data_lo_hi_lo}; // @[util.scala:294:15]
wire [10:0] exe_imm_data_lo = {exe_imm_data_lo_hi, exe_imm_data_lo_lo}; // @[util.scala:294:15]
wire [8:0] exe_imm_data_hi_lo = {exe_imm_data_hi_lo_hi, exe_imm_data_hi_lo_lo}; // @[util.scala:294:15]
wire [11:0] exe_imm_data_hi_hi = {exe_imm_data_hi_hi_hi, exe_imm_data_hi_hi_lo}; // @[util.scala:294:15]
wire [20:0] exe_imm_data_hi = {exe_imm_data_hi_hi, exe_imm_data_hi_lo}; // @[util.scala:294:15]
wire [31:0] _exe_imm_data_T_4 = {exe_imm_data_hi, exe_imm_data_lo}; // @[util.scala:294:15]
wire _exe_imm_data_T_5 = _exe_imm_data_T_4[31]; // @[util.scala:269:46, :294:15]
wire [31:0] _exe_imm_data_T_6 = {32{_exe_imm_data_T_5}}; // @[util.scala:269:{25,46}]
wire [63:0] _exe_imm_data_T_7 = {_exe_imm_data_T_6, _exe_imm_data_T_4}; // @[util.scala:269:{20,25}, :294:15]
wire [63:0] _exe_imm_data_T_8 = _exe_imm_data_T ? _exe_imm_data_T_3 : _exe_imm_data_T_7; // @[util.scala:269:20]
reg [63:0] exe_imm_data; // @[execution-unit.scala:170:29]
wire _io_squash_iss_T = ~io_arb_irf_reqs_0_ready_0; // @[execution-unit.scala:255:7, :265:49]
assign _io_squash_iss_T_1 = io_arb_irf_reqs_0_valid_0 & _io_squash_iss_T; // @[execution-unit.scala:255:7, :265:{46,49}]
wire _will_replay_T_1 = |_will_replay_T; // @[util.scala:126:{51,59}]
wire _will_replay_T_2 = _will_replay_T_1 | io_kill; // @[util.scala:61:61, :126:59]
wire _will_replay_T_3 = ~_will_replay_T_2; // @[util.scala:61:61]
wire _will_replay_T_4 = arb_uop_valid & _will_replay_T_3; // @[execution-unit.scala:92:20, :268:{37,40}]
wire _will_replay_T_5 = ~arb_rebusied; // @[execution-unit.scala:130:45, :268:97]
wire will_replay = _will_replay_T_4 & _will_replay_T_5; // @[execution-unit.scala:268:{37,94,97}]
wire [11:0] _arb_uop_bits_out_br_mask_T_3; // @[util.scala:93:25]
wire [11:0] arb_uop_bits_out_1_br_mask; // @[util.scala:104:23]
wire [11:0] _arb_uop_bits_out_br_mask_T_2 = ~io_brupdate_b1_resolve_mask; // @[util.scala:93:27]
assign _arb_uop_bits_out_br_mask_T_3 = arb_uop_bits_br_mask & _arb_uop_bits_out_br_mask_T_2; // @[util.scala:93:{25,27}]
assign arb_uop_bits_out_1_br_mask = _arb_uop_bits_out_br_mask_T_3; // @[util.scala:93:25, :104:23]
wire _io_agen_T = exe_uop_valid & exe_uop_bits_fu_code_1; // @[execution-unit.scala:98:20, :311:28]
wire _io_agen_T_1 = ~_io_agen_T; // @[execution-unit.scala:311:{12,28}]
wire _io_agen_T_3 = ~_io_agen_T_2; // @[execution-unit.scala:311:11]
wire _io_agen_T_4 = ~_io_agen_T_1; // @[execution-unit.scala:311:{11,12}] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_150 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_source_extend of AsyncResetSynchronizerShiftReg_w1_d3_i0_165
connect io_out_source_extend.clock, clock
connect io_out_source_extend.reset, reset
connect io_out_source_extend.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_source_extend.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_150( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_165 io_out_source_extend ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_37 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<8>(0h90))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<6>(0h20))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<6>(0h21))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<6>(0h22))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<6>(0h23))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<6>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 5, 0)
node _source_ok_T_25 = shr(io.in.a.bits.source, 6)
node _source_ok_T_26 = eq(_source_ok_T_25, UInt<1>(0h1))
node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27)
node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<6>(0h3f))
node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29)
node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<6>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 5, 0)
node _source_ok_T_31 = shr(io.in.a.bits.source, 6)
node _source_ok_T_32 = eq(_source_ok_T_31, UInt<1>(0h0))
node _source_ok_T_33 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_34 = and(_source_ok_T_32, _source_ok_T_33)
node _source_ok_T_35 = leq(source_ok_uncommonBits_5, UInt<6>(0h3f))
node _source_ok_T_36 = and(_source_ok_T_34, _source_ok_T_35)
node _source_ok_T_37 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _source_ok_T_38 = eq(io.in.a.bits.source, UInt<8>(0ha2))
wire _source_ok_WIRE : UInt<1>[9]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_30
connect _source_ok_WIRE[6], _source_ok_T_36
connect _source_ok_WIRE[7], _source_ok_T_37
connect _source_ok_WIRE[8], _source_ok_T_38
node _source_ok_T_39 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_40 = or(_source_ok_T_39, _source_ok_WIRE[2])
node _source_ok_T_41 = or(_source_ok_T_40, _source_ok_WIRE[3])
node _source_ok_T_42 = or(_source_ok_T_41, _source_ok_WIRE[4])
node _source_ok_T_43 = or(_source_ok_T_42, _source_ok_WIRE[5])
node _source_ok_T_44 = or(_source_ok_T_43, _source_ok_WIRE[6])
node _source_ok_T_45 = or(_source_ok_T_44, _source_ok_WIRE[7])
node source_ok = or(_source_ok_T_45, _source_ok_WIRE[8])
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<4>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 3, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<3>(0h4))
node mask_sub_sub_sub_size = bits(mask_sizeOH, 3, 3)
node mask_sub_sub_sub_bit = bits(io.in.a.bits.address, 3, 3)
node mask_sub_sub_sub_nbit = eq(mask_sub_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_sub_nbit)
node _mask_sub_sub_sub_acc_T = and(mask_sub_sub_sub_size, mask_sub_sub_sub_0_2)
node mask_sub_sub_sub_0_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T)
node mask_sub_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_sub_bit)
node _mask_sub_sub_sub_acc_T_1 = and(mask_sub_sub_sub_size, mask_sub_sub_sub_1_2)
node mask_sub_sub_sub_1_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T_1)
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_sub_2_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_nbit)
node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size, mask_sub_sub_2_2)
node mask_sub_sub_2_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_2)
node mask_sub_sub_3_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_bit)
node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size, mask_sub_sub_3_2)
node mask_sub_sub_3_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_3)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_sub_4_2 = and(mask_sub_sub_2_2, mask_sub_nbit)
node _mask_sub_acc_T_4 = and(mask_sub_size, mask_sub_4_2)
node mask_sub_4_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_4)
node mask_sub_5_2 = and(mask_sub_sub_2_2, mask_sub_bit)
node _mask_sub_acc_T_5 = and(mask_sub_size, mask_sub_5_2)
node mask_sub_5_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_5)
node mask_sub_6_2 = and(mask_sub_sub_3_2, mask_sub_nbit)
node _mask_sub_acc_T_6 = and(mask_sub_size, mask_sub_6_2)
node mask_sub_6_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_6)
node mask_sub_7_2 = and(mask_sub_sub_3_2, mask_sub_bit)
node _mask_sub_acc_T_7 = and(mask_sub_size, mask_sub_7_2)
node mask_sub_7_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_7)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_eq_8 = and(mask_sub_4_2, mask_nbit)
node _mask_acc_T_8 = and(mask_size, mask_eq_8)
node mask_acc_8 = or(mask_sub_4_1, _mask_acc_T_8)
node mask_eq_9 = and(mask_sub_4_2, mask_bit)
node _mask_acc_T_9 = and(mask_size, mask_eq_9)
node mask_acc_9 = or(mask_sub_4_1, _mask_acc_T_9)
node mask_eq_10 = and(mask_sub_5_2, mask_nbit)
node _mask_acc_T_10 = and(mask_size, mask_eq_10)
node mask_acc_10 = or(mask_sub_5_1, _mask_acc_T_10)
node mask_eq_11 = and(mask_sub_5_2, mask_bit)
node _mask_acc_T_11 = and(mask_size, mask_eq_11)
node mask_acc_11 = or(mask_sub_5_1, _mask_acc_T_11)
node mask_eq_12 = and(mask_sub_6_2, mask_nbit)
node _mask_acc_T_12 = and(mask_size, mask_eq_12)
node mask_acc_12 = or(mask_sub_6_1, _mask_acc_T_12)
node mask_eq_13 = and(mask_sub_6_2, mask_bit)
node _mask_acc_T_13 = and(mask_size, mask_eq_13)
node mask_acc_13 = or(mask_sub_6_1, _mask_acc_T_13)
node mask_eq_14 = and(mask_sub_7_2, mask_nbit)
node _mask_acc_T_14 = and(mask_size, mask_eq_14)
node mask_acc_14 = or(mask_sub_7_1, _mask_acc_T_14)
node mask_eq_15 = and(mask_sub_7_2, mask_bit)
node _mask_acc_T_15 = and(mask_size, mask_eq_15)
node mask_acc_15 = or(mask_sub_7_1, _mask_acc_T_15)
node mask_lo_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo_lo = cat(mask_lo_lo_hi, mask_lo_lo_lo)
node mask_lo_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_lo_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_lo_hi = cat(mask_lo_hi_hi, mask_lo_hi_lo)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo_lo = cat(mask_acc_9, mask_acc_8)
node mask_hi_lo_hi = cat(mask_acc_11, mask_acc_10)
node mask_hi_lo = cat(mask_hi_lo_hi, mask_hi_lo_lo)
node mask_hi_hi_lo = cat(mask_acc_13, mask_acc_12)
node mask_hi_hi_hi = cat(mask_acc_15, mask_acc_14)
node mask_hi_hi = cat(mask_hi_hi_hi, mask_hi_hi_lo)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<6>(0h20))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<6>(0h21))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<6>(0h22))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<6>(0h23))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 5, 0)
node _T_64 = shr(io.in.a.bits.source, 6)
node _T_65 = eq(_T_64, UInt<1>(0h1))
node _T_66 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_67 = and(_T_65, _T_66)
node _T_68 = leq(uncommonBits_4, UInt<6>(0h3f))
node _T_69 = and(_T_67, _T_68)
node _T_70 = eq(_T_69, UInt<1>(0h0))
node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_72 = cvt(_T_71)
node _T_73 = and(_T_72, asSInt(UInt<1>(0h0)))
node _T_74 = asSInt(_T_73)
node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0)))
node _T_76 = or(_T_70, _T_75)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 5, 0)
node _T_77 = shr(io.in.a.bits.source, 6)
node _T_78 = eq(_T_77, UInt<1>(0h0))
node _T_79 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_80 = and(_T_78, _T_79)
node _T_81 = leq(uncommonBits_5, UInt<6>(0h3f))
node _T_82 = and(_T_80, _T_81)
node _T_83 = eq(_T_82, UInt<1>(0h0))
node _T_84 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_85 = cvt(_T_84)
node _T_86 = and(_T_85, asSInt(UInt<1>(0h0)))
node _T_87 = asSInt(_T_86)
node _T_88 = eq(_T_87, asSInt(UInt<1>(0h0)))
node _T_89 = or(_T_83, _T_88)
node _T_90 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_91 = eq(_T_90, UInt<1>(0h0))
node _T_92 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_93 = cvt(_T_92)
node _T_94 = and(_T_93, asSInt(UInt<1>(0h0)))
node _T_95 = asSInt(_T_94)
node _T_96 = eq(_T_95, asSInt(UInt<1>(0h0)))
node _T_97 = or(_T_91, _T_96)
node _T_98 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_99 = eq(_T_98, UInt<1>(0h0))
node _T_100 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_101 = cvt(_T_100)
node _T_102 = and(_T_101, asSInt(UInt<1>(0h0)))
node _T_103 = asSInt(_T_102)
node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0)))
node _T_105 = or(_T_99, _T_104)
node _T_106 = and(_T_11, _T_24)
node _T_107 = and(_T_106, _T_37)
node _T_108 = and(_T_107, _T_50)
node _T_109 = and(_T_108, _T_63)
node _T_110 = and(_T_109, _T_76)
node _T_111 = and(_T_110, _T_89)
node _T_112 = and(_T_111, _T_97)
node _T_113 = and(_T_112, _T_105)
node _T_114 = asUInt(reset)
node _T_115 = eq(_T_114, UInt<1>(0h0))
when _T_115 :
node _T_116 = eq(_T_113, UInt<1>(0h0))
when _T_116 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_113, UInt<1>(0h1), "") : assert_1
node _T_117 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_117 :
node _T_118 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_119 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_120 = and(_T_118, _T_119)
node _T_121 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_122 = shr(io.in.a.bits.source, 2)
node _T_123 = eq(_T_122, UInt<6>(0h20))
node _T_124 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_125 = and(_T_123, _T_124)
node _T_126 = leq(uncommonBits_6, UInt<2>(0h3))
node _T_127 = and(_T_125, _T_126)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_128 = shr(io.in.a.bits.source, 2)
node _T_129 = eq(_T_128, UInt<6>(0h21))
node _T_130 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_131 = and(_T_129, _T_130)
node _T_132 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_133 = and(_T_131, _T_132)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_134 = shr(io.in.a.bits.source, 2)
node _T_135 = eq(_T_134, UInt<6>(0h22))
node _T_136 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_137 = and(_T_135, _T_136)
node _T_138 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_139 = and(_T_137, _T_138)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_140 = shr(io.in.a.bits.source, 2)
node _T_141 = eq(_T_140, UInt<6>(0h23))
node _T_142 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_143 = and(_T_141, _T_142)
node _T_144 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_145 = and(_T_143, _T_144)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 5, 0)
node _T_146 = shr(io.in.a.bits.source, 6)
node _T_147 = eq(_T_146, UInt<1>(0h1))
node _T_148 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_149 = and(_T_147, _T_148)
node _T_150 = leq(uncommonBits_10, UInt<6>(0h3f))
node _T_151 = and(_T_149, _T_150)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 5, 0)
node _T_152 = shr(io.in.a.bits.source, 6)
node _T_153 = eq(_T_152, UInt<1>(0h0))
node _T_154 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_155 = and(_T_153, _T_154)
node _T_156 = leq(uncommonBits_11, UInt<6>(0h3f))
node _T_157 = and(_T_155, _T_156)
node _T_158 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_159 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_160 = or(_T_121, _T_127)
node _T_161 = or(_T_160, _T_133)
node _T_162 = or(_T_161, _T_139)
node _T_163 = or(_T_162, _T_145)
node _T_164 = or(_T_163, _T_151)
node _T_165 = or(_T_164, _T_157)
node _T_166 = or(_T_165, _T_158)
node _T_167 = or(_T_166, _T_159)
node _T_168 = and(_T_120, _T_167)
node _T_169 = or(UInt<1>(0h0), _T_168)
node _T_170 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_171 = or(UInt<1>(0h0), _T_170)
node _T_172 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_173 = cvt(_T_172)
node _T_174 = and(_T_173, asSInt(UInt<17>(0h10000)))
node _T_175 = asSInt(_T_174)
node _T_176 = eq(_T_175, asSInt(UInt<1>(0h0)))
node _T_177 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_178 = cvt(_T_177)
node _T_179 = and(_T_178, asSInt(UInt<29>(0h10000000)))
node _T_180 = asSInt(_T_179)
node _T_181 = eq(_T_180, asSInt(UInt<1>(0h0)))
node _T_182 = or(_T_176, _T_181)
node _T_183 = and(_T_171, _T_182)
node _T_184 = or(UInt<1>(0h0), _T_183)
node _T_185 = and(_T_169, _T_184)
node _T_186 = asUInt(reset)
node _T_187 = eq(_T_186, UInt<1>(0h0))
when _T_187 :
node _T_188 = eq(_T_185, UInt<1>(0h0))
when _T_188 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_185, UInt<1>(0h1), "") : assert_2
node _T_189 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_190 = shr(io.in.a.bits.source, 2)
node _T_191 = eq(_T_190, UInt<6>(0h20))
node _T_192 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_193 = and(_T_191, _T_192)
node _T_194 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_195 = and(_T_193, _T_194)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_196 = shr(io.in.a.bits.source, 2)
node _T_197 = eq(_T_196, UInt<6>(0h21))
node _T_198 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_199 = and(_T_197, _T_198)
node _T_200 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_201 = and(_T_199, _T_200)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_202 = shr(io.in.a.bits.source, 2)
node _T_203 = eq(_T_202, UInt<6>(0h22))
node _T_204 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_205 = and(_T_203, _T_204)
node _T_206 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_207 = and(_T_205, _T_206)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_208 = shr(io.in.a.bits.source, 2)
node _T_209 = eq(_T_208, UInt<6>(0h23))
node _T_210 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_211 = and(_T_209, _T_210)
node _T_212 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_213 = and(_T_211, _T_212)
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 5, 0)
node _T_214 = shr(io.in.a.bits.source, 6)
node _T_215 = eq(_T_214, UInt<1>(0h1))
node _T_216 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_217 = and(_T_215, _T_216)
node _T_218 = leq(uncommonBits_16, UInt<6>(0h3f))
node _T_219 = and(_T_217, _T_218)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 5, 0)
node _T_220 = shr(io.in.a.bits.source, 6)
node _T_221 = eq(_T_220, UInt<1>(0h0))
node _T_222 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_223 = and(_T_221, _T_222)
node _T_224 = leq(uncommonBits_17, UInt<6>(0h3f))
node _T_225 = and(_T_223, _T_224)
node _T_226 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_227 = eq(io.in.a.bits.source, UInt<8>(0ha2))
wire _WIRE : UInt<1>[9]
connect _WIRE[0], _T_189
connect _WIRE[1], _T_195
connect _WIRE[2], _T_201
connect _WIRE[3], _T_207
connect _WIRE[4], _T_213
connect _WIRE[5], _T_219
connect _WIRE[6], _T_225
connect _WIRE[7], _T_226
connect _WIRE[8], _T_227
node _T_228 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_229 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_230 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_231 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_232 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_233 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_234 = mux(_WIRE[5], UInt<1>(0h0), UInt<1>(0h0))
node _T_235 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_236 = mux(_WIRE[7], _T_228, UInt<1>(0h0))
node _T_237 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_238 = or(_T_229, _T_230)
node _T_239 = or(_T_238, _T_231)
node _T_240 = or(_T_239, _T_232)
node _T_241 = or(_T_240, _T_233)
node _T_242 = or(_T_241, _T_234)
node _T_243 = or(_T_242, _T_235)
node _T_244 = or(_T_243, _T_236)
node _T_245 = or(_T_244, _T_237)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_245
node _T_246 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_247 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_248 = and(_T_246, _T_247)
node _T_249 = or(UInt<1>(0h0), _T_248)
node _T_250 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_251 = cvt(_T_250)
node _T_252 = and(_T_251, asSInt(UInt<17>(0h10000)))
node _T_253 = asSInt(_T_252)
node _T_254 = eq(_T_253, asSInt(UInt<1>(0h0)))
node _T_255 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_256 = cvt(_T_255)
node _T_257 = and(_T_256, asSInt(UInt<29>(0h10000000)))
node _T_258 = asSInt(_T_257)
node _T_259 = eq(_T_258, asSInt(UInt<1>(0h0)))
node _T_260 = or(_T_254, _T_259)
node _T_261 = and(_T_249, _T_260)
node _T_262 = or(UInt<1>(0h0), _T_261)
node _T_263 = and(_WIRE_1, _T_262)
node _T_264 = asUInt(reset)
node _T_265 = eq(_T_264, UInt<1>(0h0))
when _T_265 :
node _T_266 = eq(_T_263, UInt<1>(0h0))
when _T_266 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_263, UInt<1>(0h1), "") : assert_3
node _T_267 = asUInt(reset)
node _T_268 = eq(_T_267, UInt<1>(0h0))
when _T_268 :
node _T_269 = eq(source_ok, UInt<1>(0h0))
when _T_269 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_270 = geq(io.in.a.bits.size, UInt<3>(0h4))
node _T_271 = asUInt(reset)
node _T_272 = eq(_T_271, UInt<1>(0h0))
when _T_272 :
node _T_273 = eq(_T_270, UInt<1>(0h0))
when _T_273 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_270, UInt<1>(0h1), "") : assert_5
node _T_274 = asUInt(reset)
node _T_275 = eq(_T_274, UInt<1>(0h0))
when _T_275 :
node _T_276 = eq(is_aligned, UInt<1>(0h0))
when _T_276 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_277 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_278 = asUInt(reset)
node _T_279 = eq(_T_278, UInt<1>(0h0))
when _T_279 :
node _T_280 = eq(_T_277, UInt<1>(0h0))
when _T_280 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_277, UInt<1>(0h1), "") : assert_7
node _T_281 = not(io.in.a.bits.mask)
node _T_282 = eq(_T_281, UInt<1>(0h0))
node _T_283 = asUInt(reset)
node _T_284 = eq(_T_283, UInt<1>(0h0))
when _T_284 :
node _T_285 = eq(_T_282, UInt<1>(0h0))
when _T_285 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_282, UInt<1>(0h1), "") : assert_8
node _T_286 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_287 = asUInt(reset)
node _T_288 = eq(_T_287, UInt<1>(0h0))
when _T_288 :
node _T_289 = eq(_T_286, UInt<1>(0h0))
when _T_289 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_286, UInt<1>(0h1), "") : assert_9
node _T_290 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_290 :
node _T_291 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_292 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_293 = and(_T_291, _T_292)
node _T_294 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0)
node _T_295 = shr(io.in.a.bits.source, 2)
node _T_296 = eq(_T_295, UInt<6>(0h20))
node _T_297 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_298 = and(_T_296, _T_297)
node _T_299 = leq(uncommonBits_18, UInt<2>(0h3))
node _T_300 = and(_T_298, _T_299)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0)
node _T_301 = shr(io.in.a.bits.source, 2)
node _T_302 = eq(_T_301, UInt<6>(0h21))
node _T_303 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_304 = and(_T_302, _T_303)
node _T_305 = leq(uncommonBits_19, UInt<2>(0h3))
node _T_306 = and(_T_304, _T_305)
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_307 = shr(io.in.a.bits.source, 2)
node _T_308 = eq(_T_307, UInt<6>(0h22))
node _T_309 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_310 = and(_T_308, _T_309)
node _T_311 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_312 = and(_T_310, _T_311)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_313 = shr(io.in.a.bits.source, 2)
node _T_314 = eq(_T_313, UInt<6>(0h23))
node _T_315 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_316 = and(_T_314, _T_315)
node _T_317 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_318 = and(_T_316, _T_317)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 5, 0)
node _T_319 = shr(io.in.a.bits.source, 6)
node _T_320 = eq(_T_319, UInt<1>(0h1))
node _T_321 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_322 = and(_T_320, _T_321)
node _T_323 = leq(uncommonBits_22, UInt<6>(0h3f))
node _T_324 = and(_T_322, _T_323)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 5, 0)
node _T_325 = shr(io.in.a.bits.source, 6)
node _T_326 = eq(_T_325, UInt<1>(0h0))
node _T_327 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_328 = and(_T_326, _T_327)
node _T_329 = leq(uncommonBits_23, UInt<6>(0h3f))
node _T_330 = and(_T_328, _T_329)
node _T_331 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_332 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_333 = or(_T_294, _T_300)
node _T_334 = or(_T_333, _T_306)
node _T_335 = or(_T_334, _T_312)
node _T_336 = or(_T_335, _T_318)
node _T_337 = or(_T_336, _T_324)
node _T_338 = or(_T_337, _T_330)
node _T_339 = or(_T_338, _T_331)
node _T_340 = or(_T_339, _T_332)
node _T_341 = and(_T_293, _T_340)
node _T_342 = or(UInt<1>(0h0), _T_341)
node _T_343 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_344 = or(UInt<1>(0h0), _T_343)
node _T_345 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_346 = cvt(_T_345)
node _T_347 = and(_T_346, asSInt(UInt<17>(0h10000)))
node _T_348 = asSInt(_T_347)
node _T_349 = eq(_T_348, asSInt(UInt<1>(0h0)))
node _T_350 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_351 = cvt(_T_350)
node _T_352 = and(_T_351, asSInt(UInt<29>(0h10000000)))
node _T_353 = asSInt(_T_352)
node _T_354 = eq(_T_353, asSInt(UInt<1>(0h0)))
node _T_355 = or(_T_349, _T_354)
node _T_356 = and(_T_344, _T_355)
node _T_357 = or(UInt<1>(0h0), _T_356)
node _T_358 = and(_T_342, _T_357)
node _T_359 = asUInt(reset)
node _T_360 = eq(_T_359, UInt<1>(0h0))
when _T_360 :
node _T_361 = eq(_T_358, UInt<1>(0h0))
when _T_361 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_358, UInt<1>(0h1), "") : assert_10
node _T_362 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_363 = shr(io.in.a.bits.source, 2)
node _T_364 = eq(_T_363, UInt<6>(0h20))
node _T_365 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_366 = and(_T_364, _T_365)
node _T_367 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_368 = and(_T_366, _T_367)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_369 = shr(io.in.a.bits.source, 2)
node _T_370 = eq(_T_369, UInt<6>(0h21))
node _T_371 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_372 = and(_T_370, _T_371)
node _T_373 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_374 = and(_T_372, _T_373)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_375 = shr(io.in.a.bits.source, 2)
node _T_376 = eq(_T_375, UInt<6>(0h22))
node _T_377 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_378 = and(_T_376, _T_377)
node _T_379 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_380 = and(_T_378, _T_379)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_381 = shr(io.in.a.bits.source, 2)
node _T_382 = eq(_T_381, UInt<6>(0h23))
node _T_383 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_384 = and(_T_382, _T_383)
node _T_385 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_386 = and(_T_384, _T_385)
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 5, 0)
node _T_387 = shr(io.in.a.bits.source, 6)
node _T_388 = eq(_T_387, UInt<1>(0h1))
node _T_389 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_390 = and(_T_388, _T_389)
node _T_391 = leq(uncommonBits_28, UInt<6>(0h3f))
node _T_392 = and(_T_390, _T_391)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 5, 0)
node _T_393 = shr(io.in.a.bits.source, 6)
node _T_394 = eq(_T_393, UInt<1>(0h0))
node _T_395 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_396 = and(_T_394, _T_395)
node _T_397 = leq(uncommonBits_29, UInt<6>(0h3f))
node _T_398 = and(_T_396, _T_397)
node _T_399 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_400 = eq(io.in.a.bits.source, UInt<8>(0ha2))
wire _WIRE_2 : UInt<1>[9]
connect _WIRE_2[0], _T_362
connect _WIRE_2[1], _T_368
connect _WIRE_2[2], _T_374
connect _WIRE_2[3], _T_380
connect _WIRE_2[4], _T_386
connect _WIRE_2[5], _T_392
connect _WIRE_2[6], _T_398
connect _WIRE_2[7], _T_399
connect _WIRE_2[8], _T_400
node _T_401 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_402 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_403 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_404 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_405 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_406 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_407 = mux(_WIRE_2[5], UInt<1>(0h0), UInt<1>(0h0))
node _T_408 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_409 = mux(_WIRE_2[7], _T_401, UInt<1>(0h0))
node _T_410 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_411 = or(_T_402, _T_403)
node _T_412 = or(_T_411, _T_404)
node _T_413 = or(_T_412, _T_405)
node _T_414 = or(_T_413, _T_406)
node _T_415 = or(_T_414, _T_407)
node _T_416 = or(_T_415, _T_408)
node _T_417 = or(_T_416, _T_409)
node _T_418 = or(_T_417, _T_410)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_418
node _T_419 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_420 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_421 = and(_T_419, _T_420)
node _T_422 = or(UInt<1>(0h0), _T_421)
node _T_423 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_424 = cvt(_T_423)
node _T_425 = and(_T_424, asSInt(UInt<17>(0h10000)))
node _T_426 = asSInt(_T_425)
node _T_427 = eq(_T_426, asSInt(UInt<1>(0h0)))
node _T_428 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_429 = cvt(_T_428)
node _T_430 = and(_T_429, asSInt(UInt<29>(0h10000000)))
node _T_431 = asSInt(_T_430)
node _T_432 = eq(_T_431, asSInt(UInt<1>(0h0)))
node _T_433 = or(_T_427, _T_432)
node _T_434 = and(_T_422, _T_433)
node _T_435 = or(UInt<1>(0h0), _T_434)
node _T_436 = and(_WIRE_3, _T_435)
node _T_437 = asUInt(reset)
node _T_438 = eq(_T_437, UInt<1>(0h0))
when _T_438 :
node _T_439 = eq(_T_436, UInt<1>(0h0))
when _T_439 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_436, UInt<1>(0h1), "") : assert_11
node _T_440 = asUInt(reset)
node _T_441 = eq(_T_440, UInt<1>(0h0))
when _T_441 :
node _T_442 = eq(source_ok, UInt<1>(0h0))
when _T_442 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_443 = geq(io.in.a.bits.size, UInt<3>(0h4))
node _T_444 = asUInt(reset)
node _T_445 = eq(_T_444, UInt<1>(0h0))
when _T_445 :
node _T_446 = eq(_T_443, UInt<1>(0h0))
when _T_446 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_443, UInt<1>(0h1), "") : assert_13
node _T_447 = asUInt(reset)
node _T_448 = eq(_T_447, UInt<1>(0h0))
when _T_448 :
node _T_449 = eq(is_aligned, UInt<1>(0h0))
when _T_449 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_450 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_451 = asUInt(reset)
node _T_452 = eq(_T_451, UInt<1>(0h0))
when _T_452 :
node _T_453 = eq(_T_450, UInt<1>(0h0))
when _T_453 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_450, UInt<1>(0h1), "") : assert_15
node _T_454 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_455 = asUInt(reset)
node _T_456 = eq(_T_455, UInt<1>(0h0))
when _T_456 :
node _T_457 = eq(_T_454, UInt<1>(0h0))
when _T_457 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_454, UInt<1>(0h1), "") : assert_16
node _T_458 = not(io.in.a.bits.mask)
node _T_459 = eq(_T_458, UInt<1>(0h0))
node _T_460 = asUInt(reset)
node _T_461 = eq(_T_460, UInt<1>(0h0))
when _T_461 :
node _T_462 = eq(_T_459, UInt<1>(0h0))
when _T_462 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_459, UInt<1>(0h1), "") : assert_17
node _T_463 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_464 = asUInt(reset)
node _T_465 = eq(_T_464, UInt<1>(0h0))
when _T_465 :
node _T_466 = eq(_T_463, UInt<1>(0h0))
when _T_466 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_463, UInt<1>(0h1), "") : assert_18
node _T_467 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_467 :
node _T_468 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_469 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_470 = and(_T_468, _T_469)
node _T_471 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_472 = shr(io.in.a.bits.source, 2)
node _T_473 = eq(_T_472, UInt<6>(0h20))
node _T_474 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_475 = and(_T_473, _T_474)
node _T_476 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_477 = and(_T_475, _T_476)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_478 = shr(io.in.a.bits.source, 2)
node _T_479 = eq(_T_478, UInt<6>(0h21))
node _T_480 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_481 = and(_T_479, _T_480)
node _T_482 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_483 = and(_T_481, _T_482)
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_484 = shr(io.in.a.bits.source, 2)
node _T_485 = eq(_T_484, UInt<6>(0h22))
node _T_486 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_487 = and(_T_485, _T_486)
node _T_488 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_489 = and(_T_487, _T_488)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_490 = shr(io.in.a.bits.source, 2)
node _T_491 = eq(_T_490, UInt<6>(0h23))
node _T_492 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_493 = and(_T_491, _T_492)
node _T_494 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_495 = and(_T_493, _T_494)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 5, 0)
node _T_496 = shr(io.in.a.bits.source, 6)
node _T_497 = eq(_T_496, UInt<1>(0h1))
node _T_498 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_499 = and(_T_497, _T_498)
node _T_500 = leq(uncommonBits_34, UInt<6>(0h3f))
node _T_501 = and(_T_499, _T_500)
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 5, 0)
node _T_502 = shr(io.in.a.bits.source, 6)
node _T_503 = eq(_T_502, UInt<1>(0h0))
node _T_504 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_505 = and(_T_503, _T_504)
node _T_506 = leq(uncommonBits_35, UInt<6>(0h3f))
node _T_507 = and(_T_505, _T_506)
node _T_508 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_509 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_510 = or(_T_471, _T_477)
node _T_511 = or(_T_510, _T_483)
node _T_512 = or(_T_511, _T_489)
node _T_513 = or(_T_512, _T_495)
node _T_514 = or(_T_513, _T_501)
node _T_515 = or(_T_514, _T_507)
node _T_516 = or(_T_515, _T_508)
node _T_517 = or(_T_516, _T_509)
node _T_518 = and(_T_470, _T_517)
node _T_519 = or(UInt<1>(0h0), _T_518)
node _T_520 = asUInt(reset)
node _T_521 = eq(_T_520, UInt<1>(0h0))
when _T_521 :
node _T_522 = eq(_T_519, UInt<1>(0h0))
when _T_522 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_519, UInt<1>(0h1), "") : assert_19
node _T_523 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_524 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_525 = and(_T_523, _T_524)
node _T_526 = or(UInt<1>(0h0), _T_525)
node _T_527 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_528 = cvt(_T_527)
node _T_529 = and(_T_528, asSInt(UInt<17>(0h10000)))
node _T_530 = asSInt(_T_529)
node _T_531 = eq(_T_530, asSInt(UInt<1>(0h0)))
node _T_532 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_533 = cvt(_T_532)
node _T_534 = and(_T_533, asSInt(UInt<29>(0h10000000)))
node _T_535 = asSInt(_T_534)
node _T_536 = eq(_T_535, asSInt(UInt<1>(0h0)))
node _T_537 = or(_T_531, _T_536)
node _T_538 = and(_T_526, _T_537)
node _T_539 = or(UInt<1>(0h0), _T_538)
node _T_540 = asUInt(reset)
node _T_541 = eq(_T_540, UInt<1>(0h0))
when _T_541 :
node _T_542 = eq(_T_539, UInt<1>(0h0))
when _T_542 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_539, UInt<1>(0h1), "") : assert_20
node _T_543 = asUInt(reset)
node _T_544 = eq(_T_543, UInt<1>(0h0))
when _T_544 :
node _T_545 = eq(source_ok, UInt<1>(0h0))
when _T_545 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_546 = asUInt(reset)
node _T_547 = eq(_T_546, UInt<1>(0h0))
when _T_547 :
node _T_548 = eq(is_aligned, UInt<1>(0h0))
when _T_548 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_549 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_550 = asUInt(reset)
node _T_551 = eq(_T_550, UInt<1>(0h0))
when _T_551 :
node _T_552 = eq(_T_549, UInt<1>(0h0))
when _T_552 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_549, UInt<1>(0h1), "") : assert_23
node _T_553 = eq(io.in.a.bits.mask, mask)
node _T_554 = asUInt(reset)
node _T_555 = eq(_T_554, UInt<1>(0h0))
when _T_555 :
node _T_556 = eq(_T_553, UInt<1>(0h0))
when _T_556 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_553, UInt<1>(0h1), "") : assert_24
node _T_557 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_558 = asUInt(reset)
node _T_559 = eq(_T_558, UInt<1>(0h0))
when _T_559 :
node _T_560 = eq(_T_557, UInt<1>(0h0))
when _T_560 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_557, UInt<1>(0h1), "") : assert_25
node _T_561 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_561 :
node _T_562 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_563 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_564 = and(_T_562, _T_563)
node _T_565 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0)
node _T_566 = shr(io.in.a.bits.source, 2)
node _T_567 = eq(_T_566, UInt<6>(0h20))
node _T_568 = leq(UInt<1>(0h0), uncommonBits_36)
node _T_569 = and(_T_567, _T_568)
node _T_570 = leq(uncommonBits_36, UInt<2>(0h3))
node _T_571 = and(_T_569, _T_570)
node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0)
node _T_572 = shr(io.in.a.bits.source, 2)
node _T_573 = eq(_T_572, UInt<6>(0h21))
node _T_574 = leq(UInt<1>(0h0), uncommonBits_37)
node _T_575 = and(_T_573, _T_574)
node _T_576 = leq(uncommonBits_37, UInt<2>(0h3))
node _T_577 = and(_T_575, _T_576)
node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0)
node _T_578 = shr(io.in.a.bits.source, 2)
node _T_579 = eq(_T_578, UInt<6>(0h22))
node _T_580 = leq(UInt<1>(0h0), uncommonBits_38)
node _T_581 = and(_T_579, _T_580)
node _T_582 = leq(uncommonBits_38, UInt<2>(0h3))
node _T_583 = and(_T_581, _T_582)
node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0)
node _T_584 = shr(io.in.a.bits.source, 2)
node _T_585 = eq(_T_584, UInt<6>(0h23))
node _T_586 = leq(UInt<1>(0h0), uncommonBits_39)
node _T_587 = and(_T_585, _T_586)
node _T_588 = leq(uncommonBits_39, UInt<2>(0h3))
node _T_589 = and(_T_587, _T_588)
node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_40 = bits(_uncommonBits_T_40, 5, 0)
node _T_590 = shr(io.in.a.bits.source, 6)
node _T_591 = eq(_T_590, UInt<1>(0h1))
node _T_592 = leq(UInt<1>(0h0), uncommonBits_40)
node _T_593 = and(_T_591, _T_592)
node _T_594 = leq(uncommonBits_40, UInt<6>(0h3f))
node _T_595 = and(_T_593, _T_594)
node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_41 = bits(_uncommonBits_T_41, 5, 0)
node _T_596 = shr(io.in.a.bits.source, 6)
node _T_597 = eq(_T_596, UInt<1>(0h0))
node _T_598 = leq(UInt<1>(0h0), uncommonBits_41)
node _T_599 = and(_T_597, _T_598)
node _T_600 = leq(uncommonBits_41, UInt<6>(0h3f))
node _T_601 = and(_T_599, _T_600)
node _T_602 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_603 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_604 = or(_T_565, _T_571)
node _T_605 = or(_T_604, _T_577)
node _T_606 = or(_T_605, _T_583)
node _T_607 = or(_T_606, _T_589)
node _T_608 = or(_T_607, _T_595)
node _T_609 = or(_T_608, _T_601)
node _T_610 = or(_T_609, _T_602)
node _T_611 = or(_T_610, _T_603)
node _T_612 = and(_T_564, _T_611)
node _T_613 = or(UInt<1>(0h0), _T_612)
node _T_614 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_615 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_616 = and(_T_614, _T_615)
node _T_617 = or(UInt<1>(0h0), _T_616)
node _T_618 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_619 = cvt(_T_618)
node _T_620 = and(_T_619, asSInt(UInt<17>(0h10000)))
node _T_621 = asSInt(_T_620)
node _T_622 = eq(_T_621, asSInt(UInt<1>(0h0)))
node _T_623 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_624 = cvt(_T_623)
node _T_625 = and(_T_624, asSInt(UInt<29>(0h10000000)))
node _T_626 = asSInt(_T_625)
node _T_627 = eq(_T_626, asSInt(UInt<1>(0h0)))
node _T_628 = or(_T_622, _T_627)
node _T_629 = and(_T_617, _T_628)
node _T_630 = or(UInt<1>(0h0), _T_629)
node _T_631 = and(_T_613, _T_630)
node _T_632 = asUInt(reset)
node _T_633 = eq(_T_632, UInt<1>(0h0))
when _T_633 :
node _T_634 = eq(_T_631, UInt<1>(0h0))
when _T_634 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_631, UInt<1>(0h1), "") : assert_26
node _T_635 = asUInt(reset)
node _T_636 = eq(_T_635, UInt<1>(0h0))
when _T_636 :
node _T_637 = eq(source_ok, UInt<1>(0h0))
when _T_637 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_638 = asUInt(reset)
node _T_639 = eq(_T_638, UInt<1>(0h0))
when _T_639 :
node _T_640 = eq(is_aligned, UInt<1>(0h0))
when _T_640 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_641 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_642 = asUInt(reset)
node _T_643 = eq(_T_642, UInt<1>(0h0))
when _T_643 :
node _T_644 = eq(_T_641, UInt<1>(0h0))
when _T_644 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_641, UInt<1>(0h1), "") : assert_29
node _T_645 = eq(io.in.a.bits.mask, mask)
node _T_646 = asUInt(reset)
node _T_647 = eq(_T_646, UInt<1>(0h0))
when _T_647 :
node _T_648 = eq(_T_645, UInt<1>(0h0))
when _T_648 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_645, UInt<1>(0h1), "") : assert_30
node _T_649 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_649 :
node _T_650 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_651 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_652 = and(_T_650, _T_651)
node _T_653 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0)
node _T_654 = shr(io.in.a.bits.source, 2)
node _T_655 = eq(_T_654, UInt<6>(0h20))
node _T_656 = leq(UInt<1>(0h0), uncommonBits_42)
node _T_657 = and(_T_655, _T_656)
node _T_658 = leq(uncommonBits_42, UInt<2>(0h3))
node _T_659 = and(_T_657, _T_658)
node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0)
node _T_660 = shr(io.in.a.bits.source, 2)
node _T_661 = eq(_T_660, UInt<6>(0h21))
node _T_662 = leq(UInt<1>(0h0), uncommonBits_43)
node _T_663 = and(_T_661, _T_662)
node _T_664 = leq(uncommonBits_43, UInt<2>(0h3))
node _T_665 = and(_T_663, _T_664)
node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0)
node _T_666 = shr(io.in.a.bits.source, 2)
node _T_667 = eq(_T_666, UInt<6>(0h22))
node _T_668 = leq(UInt<1>(0h0), uncommonBits_44)
node _T_669 = and(_T_667, _T_668)
node _T_670 = leq(uncommonBits_44, UInt<2>(0h3))
node _T_671 = and(_T_669, _T_670)
node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0)
node _T_672 = shr(io.in.a.bits.source, 2)
node _T_673 = eq(_T_672, UInt<6>(0h23))
node _T_674 = leq(UInt<1>(0h0), uncommonBits_45)
node _T_675 = and(_T_673, _T_674)
node _T_676 = leq(uncommonBits_45, UInt<2>(0h3))
node _T_677 = and(_T_675, _T_676)
node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_46 = bits(_uncommonBits_T_46, 5, 0)
node _T_678 = shr(io.in.a.bits.source, 6)
node _T_679 = eq(_T_678, UInt<1>(0h1))
node _T_680 = leq(UInt<1>(0h0), uncommonBits_46)
node _T_681 = and(_T_679, _T_680)
node _T_682 = leq(uncommonBits_46, UInt<6>(0h3f))
node _T_683 = and(_T_681, _T_682)
node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_47 = bits(_uncommonBits_T_47, 5, 0)
node _T_684 = shr(io.in.a.bits.source, 6)
node _T_685 = eq(_T_684, UInt<1>(0h0))
node _T_686 = leq(UInt<1>(0h0), uncommonBits_47)
node _T_687 = and(_T_685, _T_686)
node _T_688 = leq(uncommonBits_47, UInt<6>(0h3f))
node _T_689 = and(_T_687, _T_688)
node _T_690 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_691 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_692 = or(_T_653, _T_659)
node _T_693 = or(_T_692, _T_665)
node _T_694 = or(_T_693, _T_671)
node _T_695 = or(_T_694, _T_677)
node _T_696 = or(_T_695, _T_683)
node _T_697 = or(_T_696, _T_689)
node _T_698 = or(_T_697, _T_690)
node _T_699 = or(_T_698, _T_691)
node _T_700 = and(_T_652, _T_699)
node _T_701 = or(UInt<1>(0h0), _T_700)
node _T_702 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_703 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_704 = and(_T_702, _T_703)
node _T_705 = or(UInt<1>(0h0), _T_704)
node _T_706 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_707 = cvt(_T_706)
node _T_708 = and(_T_707, asSInt(UInt<17>(0h10000)))
node _T_709 = asSInt(_T_708)
node _T_710 = eq(_T_709, asSInt(UInt<1>(0h0)))
node _T_711 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_712 = cvt(_T_711)
node _T_713 = and(_T_712, asSInt(UInt<29>(0h10000000)))
node _T_714 = asSInt(_T_713)
node _T_715 = eq(_T_714, asSInt(UInt<1>(0h0)))
node _T_716 = or(_T_710, _T_715)
node _T_717 = and(_T_705, _T_716)
node _T_718 = or(UInt<1>(0h0), _T_717)
node _T_719 = and(_T_701, _T_718)
node _T_720 = asUInt(reset)
node _T_721 = eq(_T_720, UInt<1>(0h0))
when _T_721 :
node _T_722 = eq(_T_719, UInt<1>(0h0))
when _T_722 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_719, UInt<1>(0h1), "") : assert_31
node _T_723 = asUInt(reset)
node _T_724 = eq(_T_723, UInt<1>(0h0))
when _T_724 :
node _T_725 = eq(source_ok, UInt<1>(0h0))
when _T_725 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_726 = asUInt(reset)
node _T_727 = eq(_T_726, UInt<1>(0h0))
when _T_727 :
node _T_728 = eq(is_aligned, UInt<1>(0h0))
when _T_728 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_729 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_730 = asUInt(reset)
node _T_731 = eq(_T_730, UInt<1>(0h0))
when _T_731 :
node _T_732 = eq(_T_729, UInt<1>(0h0))
when _T_732 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_729, UInt<1>(0h1), "") : assert_34
node _T_733 = not(mask)
node _T_734 = and(io.in.a.bits.mask, _T_733)
node _T_735 = eq(_T_734, UInt<1>(0h0))
node _T_736 = asUInt(reset)
node _T_737 = eq(_T_736, UInt<1>(0h0))
when _T_737 :
node _T_738 = eq(_T_735, UInt<1>(0h0))
when _T_738 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_735, UInt<1>(0h1), "") : assert_35
node _T_739 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_739 :
node _T_740 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_741 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_742 = and(_T_740, _T_741)
node _T_743 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0)
node _T_744 = shr(io.in.a.bits.source, 2)
node _T_745 = eq(_T_744, UInt<6>(0h20))
node _T_746 = leq(UInt<1>(0h0), uncommonBits_48)
node _T_747 = and(_T_745, _T_746)
node _T_748 = leq(uncommonBits_48, UInt<2>(0h3))
node _T_749 = and(_T_747, _T_748)
node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0)
node _T_750 = shr(io.in.a.bits.source, 2)
node _T_751 = eq(_T_750, UInt<6>(0h21))
node _T_752 = leq(UInt<1>(0h0), uncommonBits_49)
node _T_753 = and(_T_751, _T_752)
node _T_754 = leq(uncommonBits_49, UInt<2>(0h3))
node _T_755 = and(_T_753, _T_754)
node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0)
node _T_756 = shr(io.in.a.bits.source, 2)
node _T_757 = eq(_T_756, UInt<6>(0h22))
node _T_758 = leq(UInt<1>(0h0), uncommonBits_50)
node _T_759 = and(_T_757, _T_758)
node _T_760 = leq(uncommonBits_50, UInt<2>(0h3))
node _T_761 = and(_T_759, _T_760)
node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0)
node _T_762 = shr(io.in.a.bits.source, 2)
node _T_763 = eq(_T_762, UInt<6>(0h23))
node _T_764 = leq(UInt<1>(0h0), uncommonBits_51)
node _T_765 = and(_T_763, _T_764)
node _T_766 = leq(uncommonBits_51, UInt<2>(0h3))
node _T_767 = and(_T_765, _T_766)
node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_52 = bits(_uncommonBits_T_52, 5, 0)
node _T_768 = shr(io.in.a.bits.source, 6)
node _T_769 = eq(_T_768, UInt<1>(0h1))
node _T_770 = leq(UInt<1>(0h0), uncommonBits_52)
node _T_771 = and(_T_769, _T_770)
node _T_772 = leq(uncommonBits_52, UInt<6>(0h3f))
node _T_773 = and(_T_771, _T_772)
node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_53 = bits(_uncommonBits_T_53, 5, 0)
node _T_774 = shr(io.in.a.bits.source, 6)
node _T_775 = eq(_T_774, UInt<1>(0h0))
node _T_776 = leq(UInt<1>(0h0), uncommonBits_53)
node _T_777 = and(_T_775, _T_776)
node _T_778 = leq(uncommonBits_53, UInt<6>(0h3f))
node _T_779 = and(_T_777, _T_778)
node _T_780 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_781 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_782 = or(_T_743, _T_749)
node _T_783 = or(_T_782, _T_755)
node _T_784 = or(_T_783, _T_761)
node _T_785 = or(_T_784, _T_767)
node _T_786 = or(_T_785, _T_773)
node _T_787 = or(_T_786, _T_779)
node _T_788 = or(_T_787, _T_780)
node _T_789 = or(_T_788, _T_781)
node _T_790 = and(_T_742, _T_789)
node _T_791 = or(UInt<1>(0h0), _T_790)
node _T_792 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_793 = leq(io.in.a.bits.size, UInt<3>(0h4))
node _T_794 = and(_T_792, _T_793)
node _T_795 = or(UInt<1>(0h0), _T_794)
node _T_796 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_797 = cvt(_T_796)
node _T_798 = and(_T_797, asSInt(UInt<17>(0h10000)))
node _T_799 = asSInt(_T_798)
node _T_800 = eq(_T_799, asSInt(UInt<1>(0h0)))
node _T_801 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_802 = cvt(_T_801)
node _T_803 = and(_T_802, asSInt(UInt<29>(0h10000000)))
node _T_804 = asSInt(_T_803)
node _T_805 = eq(_T_804, asSInt(UInt<1>(0h0)))
node _T_806 = or(_T_800, _T_805)
node _T_807 = and(_T_795, _T_806)
node _T_808 = or(UInt<1>(0h0), _T_807)
node _T_809 = and(_T_791, _T_808)
node _T_810 = asUInt(reset)
node _T_811 = eq(_T_810, UInt<1>(0h0))
when _T_811 :
node _T_812 = eq(_T_809, UInt<1>(0h0))
when _T_812 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_809, UInt<1>(0h1), "") : assert_36
node _T_813 = asUInt(reset)
node _T_814 = eq(_T_813, UInt<1>(0h0))
when _T_814 :
node _T_815 = eq(source_ok, UInt<1>(0h0))
when _T_815 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_816 = asUInt(reset)
node _T_817 = eq(_T_816, UInt<1>(0h0))
when _T_817 :
node _T_818 = eq(is_aligned, UInt<1>(0h0))
when _T_818 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_819 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_820 = asUInt(reset)
node _T_821 = eq(_T_820, UInt<1>(0h0))
when _T_821 :
node _T_822 = eq(_T_819, UInt<1>(0h0))
when _T_822 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_819, UInt<1>(0h1), "") : assert_39
node _T_823 = eq(io.in.a.bits.mask, mask)
node _T_824 = asUInt(reset)
node _T_825 = eq(_T_824, UInt<1>(0h0))
when _T_825 :
node _T_826 = eq(_T_823, UInt<1>(0h0))
when _T_826 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_823, UInt<1>(0h1), "") : assert_40
node _T_827 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_827 :
node _T_828 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_829 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_830 = and(_T_828, _T_829)
node _T_831 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_54 = bits(_uncommonBits_T_54, 1, 0)
node _T_832 = shr(io.in.a.bits.source, 2)
node _T_833 = eq(_T_832, UInt<6>(0h20))
node _T_834 = leq(UInt<1>(0h0), uncommonBits_54)
node _T_835 = and(_T_833, _T_834)
node _T_836 = leq(uncommonBits_54, UInt<2>(0h3))
node _T_837 = and(_T_835, _T_836)
node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_55 = bits(_uncommonBits_T_55, 1, 0)
node _T_838 = shr(io.in.a.bits.source, 2)
node _T_839 = eq(_T_838, UInt<6>(0h21))
node _T_840 = leq(UInt<1>(0h0), uncommonBits_55)
node _T_841 = and(_T_839, _T_840)
node _T_842 = leq(uncommonBits_55, UInt<2>(0h3))
node _T_843 = and(_T_841, _T_842)
node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0)
node _T_844 = shr(io.in.a.bits.source, 2)
node _T_845 = eq(_T_844, UInt<6>(0h22))
node _T_846 = leq(UInt<1>(0h0), uncommonBits_56)
node _T_847 = and(_T_845, _T_846)
node _T_848 = leq(uncommonBits_56, UInt<2>(0h3))
node _T_849 = and(_T_847, _T_848)
node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0)
node _T_850 = shr(io.in.a.bits.source, 2)
node _T_851 = eq(_T_850, UInt<6>(0h23))
node _T_852 = leq(UInt<1>(0h0), uncommonBits_57)
node _T_853 = and(_T_851, _T_852)
node _T_854 = leq(uncommonBits_57, UInt<2>(0h3))
node _T_855 = and(_T_853, _T_854)
node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_58 = bits(_uncommonBits_T_58, 5, 0)
node _T_856 = shr(io.in.a.bits.source, 6)
node _T_857 = eq(_T_856, UInt<1>(0h1))
node _T_858 = leq(UInt<1>(0h0), uncommonBits_58)
node _T_859 = and(_T_857, _T_858)
node _T_860 = leq(uncommonBits_58, UInt<6>(0h3f))
node _T_861 = and(_T_859, _T_860)
node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_59 = bits(_uncommonBits_T_59, 5, 0)
node _T_862 = shr(io.in.a.bits.source, 6)
node _T_863 = eq(_T_862, UInt<1>(0h0))
node _T_864 = leq(UInt<1>(0h0), uncommonBits_59)
node _T_865 = and(_T_863, _T_864)
node _T_866 = leq(uncommonBits_59, UInt<6>(0h3f))
node _T_867 = and(_T_865, _T_866)
node _T_868 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_869 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_870 = or(_T_831, _T_837)
node _T_871 = or(_T_870, _T_843)
node _T_872 = or(_T_871, _T_849)
node _T_873 = or(_T_872, _T_855)
node _T_874 = or(_T_873, _T_861)
node _T_875 = or(_T_874, _T_867)
node _T_876 = or(_T_875, _T_868)
node _T_877 = or(_T_876, _T_869)
node _T_878 = and(_T_830, _T_877)
node _T_879 = or(UInt<1>(0h0), _T_878)
node _T_880 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_881 = leq(io.in.a.bits.size, UInt<3>(0h4))
node _T_882 = and(_T_880, _T_881)
node _T_883 = or(UInt<1>(0h0), _T_882)
node _T_884 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_885 = cvt(_T_884)
node _T_886 = and(_T_885, asSInt(UInt<17>(0h10000)))
node _T_887 = asSInt(_T_886)
node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0)))
node _T_889 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_890 = cvt(_T_889)
node _T_891 = and(_T_890, asSInt(UInt<29>(0h10000000)))
node _T_892 = asSInt(_T_891)
node _T_893 = eq(_T_892, asSInt(UInt<1>(0h0)))
node _T_894 = or(_T_888, _T_893)
node _T_895 = and(_T_883, _T_894)
node _T_896 = or(UInt<1>(0h0), _T_895)
node _T_897 = and(_T_879, _T_896)
node _T_898 = asUInt(reset)
node _T_899 = eq(_T_898, UInt<1>(0h0))
when _T_899 :
node _T_900 = eq(_T_897, UInt<1>(0h0))
when _T_900 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_897, UInt<1>(0h1), "") : assert_41
node _T_901 = asUInt(reset)
node _T_902 = eq(_T_901, UInt<1>(0h0))
when _T_902 :
node _T_903 = eq(source_ok, UInt<1>(0h0))
when _T_903 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_904 = asUInt(reset)
node _T_905 = eq(_T_904, UInt<1>(0h0))
when _T_905 :
node _T_906 = eq(is_aligned, UInt<1>(0h0))
when _T_906 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_907 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_908 = asUInt(reset)
node _T_909 = eq(_T_908, UInt<1>(0h0))
when _T_909 :
node _T_910 = eq(_T_907, UInt<1>(0h0))
when _T_910 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_907, UInt<1>(0h1), "") : assert_44
node _T_911 = eq(io.in.a.bits.mask, mask)
node _T_912 = asUInt(reset)
node _T_913 = eq(_T_912, UInt<1>(0h0))
when _T_913 :
node _T_914 = eq(_T_911, UInt<1>(0h0))
when _T_914 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_911, UInt<1>(0h1), "") : assert_45
node _T_915 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_915 :
node _T_916 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_917 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_918 = and(_T_916, _T_917)
node _T_919 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_60 = bits(_uncommonBits_T_60, 1, 0)
node _T_920 = shr(io.in.a.bits.source, 2)
node _T_921 = eq(_T_920, UInt<6>(0h20))
node _T_922 = leq(UInt<1>(0h0), uncommonBits_60)
node _T_923 = and(_T_921, _T_922)
node _T_924 = leq(uncommonBits_60, UInt<2>(0h3))
node _T_925 = and(_T_923, _T_924)
node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_61 = bits(_uncommonBits_T_61, 1, 0)
node _T_926 = shr(io.in.a.bits.source, 2)
node _T_927 = eq(_T_926, UInt<6>(0h21))
node _T_928 = leq(UInt<1>(0h0), uncommonBits_61)
node _T_929 = and(_T_927, _T_928)
node _T_930 = leq(uncommonBits_61, UInt<2>(0h3))
node _T_931 = and(_T_929, _T_930)
node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_62 = bits(_uncommonBits_T_62, 1, 0)
node _T_932 = shr(io.in.a.bits.source, 2)
node _T_933 = eq(_T_932, UInt<6>(0h22))
node _T_934 = leq(UInt<1>(0h0), uncommonBits_62)
node _T_935 = and(_T_933, _T_934)
node _T_936 = leq(uncommonBits_62, UInt<2>(0h3))
node _T_937 = and(_T_935, _T_936)
node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0)
node _T_938 = shr(io.in.a.bits.source, 2)
node _T_939 = eq(_T_938, UInt<6>(0h23))
node _T_940 = leq(UInt<1>(0h0), uncommonBits_63)
node _T_941 = and(_T_939, _T_940)
node _T_942 = leq(uncommonBits_63, UInt<2>(0h3))
node _T_943 = and(_T_941, _T_942)
node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_64 = bits(_uncommonBits_T_64, 5, 0)
node _T_944 = shr(io.in.a.bits.source, 6)
node _T_945 = eq(_T_944, UInt<1>(0h1))
node _T_946 = leq(UInt<1>(0h0), uncommonBits_64)
node _T_947 = and(_T_945, _T_946)
node _T_948 = leq(uncommonBits_64, UInt<6>(0h3f))
node _T_949 = and(_T_947, _T_948)
node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_65 = bits(_uncommonBits_T_65, 5, 0)
node _T_950 = shr(io.in.a.bits.source, 6)
node _T_951 = eq(_T_950, UInt<1>(0h0))
node _T_952 = leq(UInt<1>(0h0), uncommonBits_65)
node _T_953 = and(_T_951, _T_952)
node _T_954 = leq(uncommonBits_65, UInt<6>(0h3f))
node _T_955 = and(_T_953, _T_954)
node _T_956 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_957 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_958 = or(_T_919, _T_925)
node _T_959 = or(_T_958, _T_931)
node _T_960 = or(_T_959, _T_937)
node _T_961 = or(_T_960, _T_943)
node _T_962 = or(_T_961, _T_949)
node _T_963 = or(_T_962, _T_955)
node _T_964 = or(_T_963, _T_956)
node _T_965 = or(_T_964, _T_957)
node _T_966 = and(_T_918, _T_965)
node _T_967 = or(UInt<1>(0h0), _T_966)
node _T_968 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_969 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_970 = and(_T_968, _T_969)
node _T_971 = or(UInt<1>(0h0), _T_970)
node _T_972 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_973 = cvt(_T_972)
node _T_974 = and(_T_973, asSInt(UInt<17>(0h10000)))
node _T_975 = asSInt(_T_974)
node _T_976 = eq(_T_975, asSInt(UInt<1>(0h0)))
node _T_977 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_978 = cvt(_T_977)
node _T_979 = and(_T_978, asSInt(UInt<29>(0h10000000)))
node _T_980 = asSInt(_T_979)
node _T_981 = eq(_T_980, asSInt(UInt<1>(0h0)))
node _T_982 = or(_T_976, _T_981)
node _T_983 = and(_T_971, _T_982)
node _T_984 = or(UInt<1>(0h0), _T_983)
node _T_985 = and(_T_967, _T_984)
node _T_986 = asUInt(reset)
node _T_987 = eq(_T_986, UInt<1>(0h0))
when _T_987 :
node _T_988 = eq(_T_985, UInt<1>(0h0))
when _T_988 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_985, UInt<1>(0h1), "") : assert_46
node _T_989 = asUInt(reset)
node _T_990 = eq(_T_989, UInt<1>(0h0))
when _T_990 :
node _T_991 = eq(source_ok, UInt<1>(0h0))
when _T_991 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_992 = asUInt(reset)
node _T_993 = eq(_T_992, UInt<1>(0h0))
when _T_993 :
node _T_994 = eq(is_aligned, UInt<1>(0h0))
when _T_994 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_995 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_996 = asUInt(reset)
node _T_997 = eq(_T_996, UInt<1>(0h0))
when _T_997 :
node _T_998 = eq(_T_995, UInt<1>(0h0))
when _T_998 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_995, UInt<1>(0h1), "") : assert_49
node _T_999 = eq(io.in.a.bits.mask, mask)
node _T_1000 = asUInt(reset)
node _T_1001 = eq(_T_1000, UInt<1>(0h0))
when _T_1001 :
node _T_1002 = eq(_T_999, UInt<1>(0h0))
when _T_1002 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_999, UInt<1>(0h1), "") : assert_50
node _T_1003 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1004 = asUInt(reset)
node _T_1005 = eq(_T_1004, UInt<1>(0h0))
when _T_1005 :
node _T_1006 = eq(_T_1003, UInt<1>(0h0))
when _T_1006 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_1003, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_1007 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1008 = asUInt(reset)
node _T_1009 = eq(_T_1008, UInt<1>(0h0))
when _T_1009 :
node _T_1010 = eq(_T_1007, UInt<1>(0h0))
when _T_1010 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_1007, UInt<1>(0h1), "") : assert_52
node _source_ok_T_46 = eq(io.in.d.bits.source, UInt<8>(0h90))
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0)
node _source_ok_T_47 = shr(io.in.d.bits.source, 2)
node _source_ok_T_48 = eq(_source_ok_T_47, UInt<6>(0h20))
node _source_ok_T_49 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_50 = and(_source_ok_T_48, _source_ok_T_49)
node _source_ok_T_51 = leq(source_ok_uncommonBits_6, UInt<2>(0h3))
node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_53 = shr(io.in.d.bits.source, 2)
node _source_ok_T_54 = eq(_source_ok_T_53, UInt<6>(0h21))
node _source_ok_T_55 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_56 = and(_source_ok_T_54, _source_ok_T_55)
node _source_ok_T_57 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57)
node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0)
node _source_ok_T_59 = shr(io.in.d.bits.source, 2)
node _source_ok_T_60 = eq(_source_ok_T_59, UInt<6>(0h22))
node _source_ok_T_61 = leq(UInt<1>(0h0), source_ok_uncommonBits_8)
node _source_ok_T_62 = and(_source_ok_T_60, _source_ok_T_61)
node _source_ok_T_63 = leq(source_ok_uncommonBits_8, UInt<2>(0h3))
node _source_ok_T_64 = and(_source_ok_T_62, _source_ok_T_63)
node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0)
node _source_ok_T_65 = shr(io.in.d.bits.source, 2)
node _source_ok_T_66 = eq(_source_ok_T_65, UInt<6>(0h23))
node _source_ok_T_67 = leq(UInt<1>(0h0), source_ok_uncommonBits_9)
node _source_ok_T_68 = and(_source_ok_T_66, _source_ok_T_67)
node _source_ok_T_69 = leq(source_ok_uncommonBits_9, UInt<2>(0h3))
node _source_ok_T_70 = and(_source_ok_T_68, _source_ok_T_69)
node _source_ok_uncommonBits_T_10 = or(io.in.d.bits.source, UInt<6>(0h0))
node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 5, 0)
node _source_ok_T_71 = shr(io.in.d.bits.source, 6)
node _source_ok_T_72 = eq(_source_ok_T_71, UInt<1>(0h1))
node _source_ok_T_73 = leq(UInt<1>(0h0), source_ok_uncommonBits_10)
node _source_ok_T_74 = and(_source_ok_T_72, _source_ok_T_73)
node _source_ok_T_75 = leq(source_ok_uncommonBits_10, UInt<6>(0h3f))
node _source_ok_T_76 = and(_source_ok_T_74, _source_ok_T_75)
node _source_ok_uncommonBits_T_11 = or(io.in.d.bits.source, UInt<6>(0h0))
node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 5, 0)
node _source_ok_T_77 = shr(io.in.d.bits.source, 6)
node _source_ok_T_78 = eq(_source_ok_T_77, UInt<1>(0h0))
node _source_ok_T_79 = leq(UInt<1>(0h0), source_ok_uncommonBits_11)
node _source_ok_T_80 = and(_source_ok_T_78, _source_ok_T_79)
node _source_ok_T_81 = leq(source_ok_uncommonBits_11, UInt<6>(0h3f))
node _source_ok_T_82 = and(_source_ok_T_80, _source_ok_T_81)
node _source_ok_T_83 = eq(io.in.d.bits.source, UInt<8>(0ha0))
node _source_ok_T_84 = eq(io.in.d.bits.source, UInt<8>(0ha2))
wire _source_ok_WIRE_1 : UInt<1>[9]
connect _source_ok_WIRE_1[0], _source_ok_T_46
connect _source_ok_WIRE_1[1], _source_ok_T_52
connect _source_ok_WIRE_1[2], _source_ok_T_58
connect _source_ok_WIRE_1[3], _source_ok_T_64
connect _source_ok_WIRE_1[4], _source_ok_T_70
connect _source_ok_WIRE_1[5], _source_ok_T_76
connect _source_ok_WIRE_1[6], _source_ok_T_82
connect _source_ok_WIRE_1[7], _source_ok_T_83
connect _source_ok_WIRE_1[8], _source_ok_T_84
node _source_ok_T_85 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_86 = or(_source_ok_T_85, _source_ok_WIRE_1[2])
node _source_ok_T_87 = or(_source_ok_T_86, _source_ok_WIRE_1[3])
node _source_ok_T_88 = or(_source_ok_T_87, _source_ok_WIRE_1[4])
node _source_ok_T_89 = or(_source_ok_T_88, _source_ok_WIRE_1[5])
node _source_ok_T_90 = or(_source_ok_T_89, _source_ok_WIRE_1[6])
node _source_ok_T_91 = or(_source_ok_T_90, _source_ok_WIRE_1[7])
node source_ok_1 = or(_source_ok_T_91, _source_ok_WIRE_1[8])
node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0hc))
node _T_1011 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1011 :
node _T_1012 = asUInt(reset)
node _T_1013 = eq(_T_1012, UInt<1>(0h0))
when _T_1013 :
node _T_1014 = eq(source_ok_1, UInt<1>(0h0))
when _T_1014 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_1015 = geq(io.in.d.bits.size, UInt<3>(0h4))
node _T_1016 = asUInt(reset)
node _T_1017 = eq(_T_1016, UInt<1>(0h0))
when _T_1017 :
node _T_1018 = eq(_T_1015, UInt<1>(0h0))
when _T_1018 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1015, UInt<1>(0h1), "") : assert_54
node _T_1019 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1020 = asUInt(reset)
node _T_1021 = eq(_T_1020, UInt<1>(0h0))
when _T_1021 :
node _T_1022 = eq(_T_1019, UInt<1>(0h0))
when _T_1022 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1019, UInt<1>(0h1), "") : assert_55
node _T_1023 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1024 = asUInt(reset)
node _T_1025 = eq(_T_1024, UInt<1>(0h0))
when _T_1025 :
node _T_1026 = eq(_T_1023, UInt<1>(0h0))
when _T_1026 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1023, UInt<1>(0h1), "") : assert_56
node _T_1027 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1028 = asUInt(reset)
node _T_1029 = eq(_T_1028, UInt<1>(0h0))
when _T_1029 :
node _T_1030 = eq(_T_1027, UInt<1>(0h0))
when _T_1030 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1027, UInt<1>(0h1), "") : assert_57
node _T_1031 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1031 :
node _T_1032 = asUInt(reset)
node _T_1033 = eq(_T_1032, UInt<1>(0h0))
when _T_1033 :
node _T_1034 = eq(source_ok_1, UInt<1>(0h0))
when _T_1034 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1035 = asUInt(reset)
node _T_1036 = eq(_T_1035, UInt<1>(0h0))
when _T_1036 :
node _T_1037 = eq(sink_ok, UInt<1>(0h0))
when _T_1037 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1038 = geq(io.in.d.bits.size, UInt<3>(0h4))
node _T_1039 = asUInt(reset)
node _T_1040 = eq(_T_1039, UInt<1>(0h0))
when _T_1040 :
node _T_1041 = eq(_T_1038, UInt<1>(0h0))
when _T_1041 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1038, UInt<1>(0h1), "") : assert_60
node _T_1042 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1043 = asUInt(reset)
node _T_1044 = eq(_T_1043, UInt<1>(0h0))
when _T_1044 :
node _T_1045 = eq(_T_1042, UInt<1>(0h0))
when _T_1045 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1042, UInt<1>(0h1), "") : assert_61
node _T_1046 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1047 = asUInt(reset)
node _T_1048 = eq(_T_1047, UInt<1>(0h0))
when _T_1048 :
node _T_1049 = eq(_T_1046, UInt<1>(0h0))
when _T_1049 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1046, UInt<1>(0h1), "") : assert_62
node _T_1050 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1051 = asUInt(reset)
node _T_1052 = eq(_T_1051, UInt<1>(0h0))
when _T_1052 :
node _T_1053 = eq(_T_1050, UInt<1>(0h0))
when _T_1053 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1050, UInt<1>(0h1), "") : assert_63
node _T_1054 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1055 = or(UInt<1>(0h1), _T_1054)
node _T_1056 = asUInt(reset)
node _T_1057 = eq(_T_1056, UInt<1>(0h0))
when _T_1057 :
node _T_1058 = eq(_T_1055, UInt<1>(0h0))
when _T_1058 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1055, UInt<1>(0h1), "") : assert_64
node _T_1059 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1059 :
node _T_1060 = asUInt(reset)
node _T_1061 = eq(_T_1060, UInt<1>(0h0))
when _T_1061 :
node _T_1062 = eq(source_ok_1, UInt<1>(0h0))
when _T_1062 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1063 = asUInt(reset)
node _T_1064 = eq(_T_1063, UInt<1>(0h0))
when _T_1064 :
node _T_1065 = eq(sink_ok, UInt<1>(0h0))
when _T_1065 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1066 = geq(io.in.d.bits.size, UInt<3>(0h4))
node _T_1067 = asUInt(reset)
node _T_1068 = eq(_T_1067, UInt<1>(0h0))
when _T_1068 :
node _T_1069 = eq(_T_1066, UInt<1>(0h0))
when _T_1069 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1066, UInt<1>(0h1), "") : assert_67
node _T_1070 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1071 = asUInt(reset)
node _T_1072 = eq(_T_1071, UInt<1>(0h0))
when _T_1072 :
node _T_1073 = eq(_T_1070, UInt<1>(0h0))
when _T_1073 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1070, UInt<1>(0h1), "") : assert_68
node _T_1074 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1075 = asUInt(reset)
node _T_1076 = eq(_T_1075, UInt<1>(0h0))
when _T_1076 :
node _T_1077 = eq(_T_1074, UInt<1>(0h0))
when _T_1077 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1074, UInt<1>(0h1), "") : assert_69
node _T_1078 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1079 = or(_T_1078, io.in.d.bits.corrupt)
node _T_1080 = asUInt(reset)
node _T_1081 = eq(_T_1080, UInt<1>(0h0))
when _T_1081 :
node _T_1082 = eq(_T_1079, UInt<1>(0h0))
when _T_1082 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1079, UInt<1>(0h1), "") : assert_70
node _T_1083 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1084 = or(UInt<1>(0h1), _T_1083)
node _T_1085 = asUInt(reset)
node _T_1086 = eq(_T_1085, UInt<1>(0h0))
when _T_1086 :
node _T_1087 = eq(_T_1084, UInt<1>(0h0))
when _T_1087 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1084, UInt<1>(0h1), "") : assert_71
node _T_1088 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1088 :
node _T_1089 = asUInt(reset)
node _T_1090 = eq(_T_1089, UInt<1>(0h0))
when _T_1090 :
node _T_1091 = eq(source_ok_1, UInt<1>(0h0))
when _T_1091 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1092 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1093 = asUInt(reset)
node _T_1094 = eq(_T_1093, UInt<1>(0h0))
when _T_1094 :
node _T_1095 = eq(_T_1092, UInt<1>(0h0))
when _T_1095 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1092, UInt<1>(0h1), "") : assert_73
node _T_1096 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1097 = asUInt(reset)
node _T_1098 = eq(_T_1097, UInt<1>(0h0))
when _T_1098 :
node _T_1099 = eq(_T_1096, UInt<1>(0h0))
when _T_1099 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1096, UInt<1>(0h1), "") : assert_74
node _T_1100 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1101 = or(UInt<1>(0h1), _T_1100)
node _T_1102 = asUInt(reset)
node _T_1103 = eq(_T_1102, UInt<1>(0h0))
when _T_1103 :
node _T_1104 = eq(_T_1101, UInt<1>(0h0))
when _T_1104 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1101, UInt<1>(0h1), "") : assert_75
node _T_1105 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1105 :
node _T_1106 = asUInt(reset)
node _T_1107 = eq(_T_1106, UInt<1>(0h0))
when _T_1107 :
node _T_1108 = eq(source_ok_1, UInt<1>(0h0))
when _T_1108 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1109 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1110 = asUInt(reset)
node _T_1111 = eq(_T_1110, UInt<1>(0h0))
when _T_1111 :
node _T_1112 = eq(_T_1109, UInt<1>(0h0))
when _T_1112 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1109, UInt<1>(0h1), "") : assert_77
node _T_1113 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1114 = or(_T_1113, io.in.d.bits.corrupt)
node _T_1115 = asUInt(reset)
node _T_1116 = eq(_T_1115, UInt<1>(0h0))
when _T_1116 :
node _T_1117 = eq(_T_1114, UInt<1>(0h0))
when _T_1117 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1114, UInt<1>(0h1), "") : assert_78
node _T_1118 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1119 = or(UInt<1>(0h1), _T_1118)
node _T_1120 = asUInt(reset)
node _T_1121 = eq(_T_1120, UInt<1>(0h0))
when _T_1121 :
node _T_1122 = eq(_T_1119, UInt<1>(0h0))
when _T_1122 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1119, UInt<1>(0h1), "") : assert_79
node _T_1123 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1123 :
node _T_1124 = asUInt(reset)
node _T_1125 = eq(_T_1124, UInt<1>(0h0))
when _T_1125 :
node _T_1126 = eq(source_ok_1, UInt<1>(0h0))
when _T_1126 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1127 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1128 = asUInt(reset)
node _T_1129 = eq(_T_1128, UInt<1>(0h0))
when _T_1129 :
node _T_1130 = eq(_T_1127, UInt<1>(0h0))
when _T_1130 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1127, UInt<1>(0h1), "") : assert_81
node _T_1131 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1132 = asUInt(reset)
node _T_1133 = eq(_T_1132, UInt<1>(0h0))
when _T_1133 :
node _T_1134 = eq(_T_1131, UInt<1>(0h0))
when _T_1134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1131, UInt<1>(0h1), "") : assert_82
node _T_1135 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1136 = or(UInt<1>(0h1), _T_1135)
node _T_1137 = asUInt(reset)
node _T_1138 = eq(_T_1137, UInt<1>(0h0))
when _T_1138 :
node _T_1139 = eq(_T_1136, UInt<1>(0h0))
when _T_1139 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1136, UInt<1>(0h1), "") : assert_83
when io.in.b.valid :
node _T_1140 = leq(io.in.b.bits.opcode, UInt<3>(0h6))
node _T_1141 = asUInt(reset)
node _T_1142 = eq(_T_1141, UInt<1>(0h0))
when _T_1142 :
node _T_1143 = eq(_T_1140, UInt<1>(0h0))
when _T_1143 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1140, UInt<1>(0h1), "") : assert_84
node _T_1144 = eq(io.in.b.bits.source, UInt<8>(0h90))
node _T_1145 = eq(_T_1144, UInt<1>(0h0))
node _T_1146 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1147 = cvt(_T_1146)
node _T_1148 = and(_T_1147, asSInt(UInt<1>(0h0)))
node _T_1149 = asSInt(_T_1148)
node _T_1150 = eq(_T_1149, asSInt(UInt<1>(0h0)))
node _T_1151 = or(_T_1145, _T_1150)
node _uncommonBits_T_66 = or(io.in.b.bits.source, UInt<2>(0h0))
node uncommonBits_66 = bits(_uncommonBits_T_66, 1, 0)
node _T_1152 = shr(io.in.b.bits.source, 2)
node _T_1153 = eq(_T_1152, UInt<6>(0h20))
node _T_1154 = leq(UInt<1>(0h0), uncommonBits_66)
node _T_1155 = and(_T_1153, _T_1154)
node _T_1156 = leq(uncommonBits_66, UInt<2>(0h3))
node _T_1157 = and(_T_1155, _T_1156)
node _T_1158 = eq(_T_1157, UInt<1>(0h0))
node _T_1159 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1160 = cvt(_T_1159)
node _T_1161 = and(_T_1160, asSInt(UInt<1>(0h0)))
node _T_1162 = asSInt(_T_1161)
node _T_1163 = eq(_T_1162, asSInt(UInt<1>(0h0)))
node _T_1164 = or(_T_1158, _T_1163)
node _uncommonBits_T_67 = or(io.in.b.bits.source, UInt<2>(0h0))
node uncommonBits_67 = bits(_uncommonBits_T_67, 1, 0)
node _T_1165 = shr(io.in.b.bits.source, 2)
node _T_1166 = eq(_T_1165, UInt<6>(0h21))
node _T_1167 = leq(UInt<1>(0h0), uncommonBits_67)
node _T_1168 = and(_T_1166, _T_1167)
node _T_1169 = leq(uncommonBits_67, UInt<2>(0h3))
node _T_1170 = and(_T_1168, _T_1169)
node _T_1171 = eq(_T_1170, UInt<1>(0h0))
node _T_1172 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1173 = cvt(_T_1172)
node _T_1174 = and(_T_1173, asSInt(UInt<1>(0h0)))
node _T_1175 = asSInt(_T_1174)
node _T_1176 = eq(_T_1175, asSInt(UInt<1>(0h0)))
node _T_1177 = or(_T_1171, _T_1176)
node _uncommonBits_T_68 = or(io.in.b.bits.source, UInt<2>(0h0))
node uncommonBits_68 = bits(_uncommonBits_T_68, 1, 0)
node _T_1178 = shr(io.in.b.bits.source, 2)
node _T_1179 = eq(_T_1178, UInt<6>(0h22))
node _T_1180 = leq(UInt<1>(0h0), uncommonBits_68)
node _T_1181 = and(_T_1179, _T_1180)
node _T_1182 = leq(uncommonBits_68, UInt<2>(0h3))
node _T_1183 = and(_T_1181, _T_1182)
node _T_1184 = eq(_T_1183, UInt<1>(0h0))
node _T_1185 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1186 = cvt(_T_1185)
node _T_1187 = and(_T_1186, asSInt(UInt<1>(0h0)))
node _T_1188 = asSInt(_T_1187)
node _T_1189 = eq(_T_1188, asSInt(UInt<1>(0h0)))
node _T_1190 = or(_T_1184, _T_1189)
node _uncommonBits_T_69 = or(io.in.b.bits.source, UInt<2>(0h0))
node uncommonBits_69 = bits(_uncommonBits_T_69, 1, 0)
node _T_1191 = shr(io.in.b.bits.source, 2)
node _T_1192 = eq(_T_1191, UInt<6>(0h23))
node _T_1193 = leq(UInt<1>(0h0), uncommonBits_69)
node _T_1194 = and(_T_1192, _T_1193)
node _T_1195 = leq(uncommonBits_69, UInt<2>(0h3))
node _T_1196 = and(_T_1194, _T_1195)
node _T_1197 = eq(_T_1196, UInt<1>(0h0))
node _T_1198 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1199 = cvt(_T_1198)
node _T_1200 = and(_T_1199, asSInt(UInt<1>(0h0)))
node _T_1201 = asSInt(_T_1200)
node _T_1202 = eq(_T_1201, asSInt(UInt<1>(0h0)))
node _T_1203 = or(_T_1197, _T_1202)
node _uncommonBits_T_70 = or(io.in.b.bits.source, UInt<6>(0h0))
node uncommonBits_70 = bits(_uncommonBits_T_70, 5, 0)
node _T_1204 = shr(io.in.b.bits.source, 6)
node _T_1205 = eq(_T_1204, UInt<1>(0h1))
node _T_1206 = leq(UInt<1>(0h0), uncommonBits_70)
node _T_1207 = and(_T_1205, _T_1206)
node _T_1208 = leq(uncommonBits_70, UInt<6>(0h3f))
node _T_1209 = and(_T_1207, _T_1208)
node _T_1210 = eq(_T_1209, UInt<1>(0h0))
node _T_1211 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1212 = cvt(_T_1211)
node _T_1213 = and(_T_1212, asSInt(UInt<1>(0h0)))
node _T_1214 = asSInt(_T_1213)
node _T_1215 = eq(_T_1214, asSInt(UInt<1>(0h0)))
node _T_1216 = or(_T_1210, _T_1215)
node _uncommonBits_T_71 = or(io.in.b.bits.source, UInt<6>(0h0))
node uncommonBits_71 = bits(_uncommonBits_T_71, 5, 0)
node _T_1217 = shr(io.in.b.bits.source, 6)
node _T_1218 = eq(_T_1217, UInt<1>(0h0))
node _T_1219 = leq(UInt<1>(0h0), uncommonBits_71)
node _T_1220 = and(_T_1218, _T_1219)
node _T_1221 = leq(uncommonBits_71, UInt<6>(0h3f))
node _T_1222 = and(_T_1220, _T_1221)
node _T_1223 = eq(_T_1222, UInt<1>(0h0))
node _T_1224 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1225 = cvt(_T_1224)
node _T_1226 = and(_T_1225, asSInt(UInt<1>(0h0)))
node _T_1227 = asSInt(_T_1226)
node _T_1228 = eq(_T_1227, asSInt(UInt<1>(0h0)))
node _T_1229 = or(_T_1223, _T_1228)
node _T_1230 = eq(io.in.b.bits.source, UInt<8>(0ha0))
node _T_1231 = eq(_T_1230, UInt<1>(0h0))
node _T_1232 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1233 = cvt(_T_1232)
node _T_1234 = and(_T_1233, asSInt(UInt<1>(0h0)))
node _T_1235 = asSInt(_T_1234)
node _T_1236 = eq(_T_1235, asSInt(UInt<1>(0h0)))
node _T_1237 = or(_T_1231, _T_1236)
node _T_1238 = eq(io.in.b.bits.source, UInt<8>(0ha2))
node _T_1239 = eq(_T_1238, UInt<1>(0h0))
node _T_1240 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1241 = cvt(_T_1240)
node _T_1242 = and(_T_1241, asSInt(UInt<1>(0h0)))
node _T_1243 = asSInt(_T_1242)
node _T_1244 = eq(_T_1243, asSInt(UInt<1>(0h0)))
node _T_1245 = or(_T_1239, _T_1244)
node _T_1246 = and(_T_1151, _T_1164)
node _T_1247 = and(_T_1246, _T_1177)
node _T_1248 = and(_T_1247, _T_1190)
node _T_1249 = and(_T_1248, _T_1203)
node _T_1250 = and(_T_1249, _T_1216)
node _T_1251 = and(_T_1250, _T_1229)
node _T_1252 = and(_T_1251, _T_1237)
node _T_1253 = and(_T_1252, _T_1245)
node _T_1254 = asUInt(reset)
node _T_1255 = eq(_T_1254, UInt<1>(0h0))
when _T_1255 :
node _T_1256 = eq(_T_1253, UInt<1>(0h0))
when _T_1256 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1253, UInt<1>(0h1), "") : assert_85
node _address_ok_T = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _address_ok_T_1 = cvt(_address_ok_T)
node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<17>(0h10000)))
node _address_ok_T_3 = asSInt(_address_ok_T_2)
node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0)))
node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _address_ok_T_6 = cvt(_address_ok_T_5)
node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<29>(0h10000000)))
node _address_ok_T_8 = asSInt(_address_ok_T_7)
node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0)))
wire _address_ok_WIRE : UInt<1>[2]
connect _address_ok_WIRE[0], _address_ok_T_4
connect _address_ok_WIRE[1], _address_ok_T_9
node address_ok = or(_address_ok_WIRE[0], _address_ok_WIRE[1])
node _is_aligned_mask_T_2 = dshl(UInt<6>(0h3f), io.in.b.bits.size)
node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 5, 0)
node is_aligned_mask_1 = not(_is_aligned_mask_T_3)
node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1)
node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0))
node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<4>(0h0))
node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0)
node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1)
node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 3, 0)
node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1))
node mask_sub_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<3>(0h4))
node mask_sub_sub_sub_size_1 = bits(mask_sizeOH_1, 3, 3)
node mask_sub_sub_sub_bit_1 = bits(io.in.b.bits.address, 3, 3)
node mask_sub_sub_sub_nbit_1 = eq(mask_sub_sub_sub_bit_1, UInt<1>(0h0))
node mask_sub_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_sub_nbit_1)
node _mask_sub_sub_sub_acc_T_2 = and(mask_sub_sub_sub_size_1, mask_sub_sub_sub_0_2_1)
node mask_sub_sub_sub_0_1_1 = or(mask_sub_sub_sub_sub_0_1_1, _mask_sub_sub_sub_acc_T_2)
node mask_sub_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_sub_bit_1)
node _mask_sub_sub_sub_acc_T_3 = and(mask_sub_sub_sub_size_1, mask_sub_sub_sub_1_2_1)
node mask_sub_sub_sub_1_1_1 = or(mask_sub_sub_sub_sub_0_1_1, _mask_sub_sub_sub_acc_T_3)
node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2)
node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2)
node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0))
node mask_sub_sub_0_2_1 = and(mask_sub_sub_sub_0_2_1, mask_sub_sub_nbit_1)
node _mask_sub_sub_acc_T_4 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1)
node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_4)
node mask_sub_sub_1_2_1 = and(mask_sub_sub_sub_0_2_1, mask_sub_sub_bit_1)
node _mask_sub_sub_acc_T_5 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1)
node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_5)
node mask_sub_sub_2_2_1 = and(mask_sub_sub_sub_1_2_1, mask_sub_sub_nbit_1)
node _mask_sub_sub_acc_T_6 = and(mask_sub_sub_size_1, mask_sub_sub_2_2_1)
node mask_sub_sub_2_1_1 = or(mask_sub_sub_sub_1_1_1, _mask_sub_sub_acc_T_6)
node mask_sub_sub_3_2_1 = and(mask_sub_sub_sub_1_2_1, mask_sub_sub_bit_1)
node _mask_sub_sub_acc_T_7 = and(mask_sub_sub_size_1, mask_sub_sub_3_2_1)
node mask_sub_sub_3_1_1 = or(mask_sub_sub_sub_1_1_1, _mask_sub_sub_acc_T_7)
node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1)
node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1)
node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0))
node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1)
node _mask_sub_acc_T_8 = and(mask_sub_size_1, mask_sub_0_2_1)
node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_8)
node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1)
node _mask_sub_acc_T_9 = and(mask_sub_size_1, mask_sub_1_2_1)
node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_9)
node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1)
node _mask_sub_acc_T_10 = and(mask_sub_size_1, mask_sub_2_2_1)
node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_10)
node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1)
node _mask_sub_acc_T_11 = and(mask_sub_size_1, mask_sub_3_2_1)
node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_11)
node mask_sub_4_2_1 = and(mask_sub_sub_2_2_1, mask_sub_nbit_1)
node _mask_sub_acc_T_12 = and(mask_sub_size_1, mask_sub_4_2_1)
node mask_sub_4_1_1 = or(mask_sub_sub_2_1_1, _mask_sub_acc_T_12)
node mask_sub_5_2_1 = and(mask_sub_sub_2_2_1, mask_sub_bit_1)
node _mask_sub_acc_T_13 = and(mask_sub_size_1, mask_sub_5_2_1)
node mask_sub_5_1_1 = or(mask_sub_sub_2_1_1, _mask_sub_acc_T_13)
node mask_sub_6_2_1 = and(mask_sub_sub_3_2_1, mask_sub_nbit_1)
node _mask_sub_acc_T_14 = and(mask_sub_size_1, mask_sub_6_2_1)
node mask_sub_6_1_1 = or(mask_sub_sub_3_1_1, _mask_sub_acc_T_14)
node mask_sub_7_2_1 = and(mask_sub_sub_3_2_1, mask_sub_bit_1)
node _mask_sub_acc_T_15 = and(mask_sub_size_1, mask_sub_7_2_1)
node mask_sub_7_1_1 = or(mask_sub_sub_3_1_1, _mask_sub_acc_T_15)
node mask_size_1 = bits(mask_sizeOH_1, 0, 0)
node mask_bit_1 = bits(io.in.b.bits.address, 0, 0)
node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0))
node mask_eq_16 = and(mask_sub_0_2_1, mask_nbit_1)
node _mask_acc_T_16 = and(mask_size_1, mask_eq_16)
node mask_acc_16 = or(mask_sub_0_1_1, _mask_acc_T_16)
node mask_eq_17 = and(mask_sub_0_2_1, mask_bit_1)
node _mask_acc_T_17 = and(mask_size_1, mask_eq_17)
node mask_acc_17 = or(mask_sub_0_1_1, _mask_acc_T_17)
node mask_eq_18 = and(mask_sub_1_2_1, mask_nbit_1)
node _mask_acc_T_18 = and(mask_size_1, mask_eq_18)
node mask_acc_18 = or(mask_sub_1_1_1, _mask_acc_T_18)
node mask_eq_19 = and(mask_sub_1_2_1, mask_bit_1)
node _mask_acc_T_19 = and(mask_size_1, mask_eq_19)
node mask_acc_19 = or(mask_sub_1_1_1, _mask_acc_T_19)
node mask_eq_20 = and(mask_sub_2_2_1, mask_nbit_1)
node _mask_acc_T_20 = and(mask_size_1, mask_eq_20)
node mask_acc_20 = or(mask_sub_2_1_1, _mask_acc_T_20)
node mask_eq_21 = and(mask_sub_2_2_1, mask_bit_1)
node _mask_acc_T_21 = and(mask_size_1, mask_eq_21)
node mask_acc_21 = or(mask_sub_2_1_1, _mask_acc_T_21)
node mask_eq_22 = and(mask_sub_3_2_1, mask_nbit_1)
node _mask_acc_T_22 = and(mask_size_1, mask_eq_22)
node mask_acc_22 = or(mask_sub_3_1_1, _mask_acc_T_22)
node mask_eq_23 = and(mask_sub_3_2_1, mask_bit_1)
node _mask_acc_T_23 = and(mask_size_1, mask_eq_23)
node mask_acc_23 = or(mask_sub_3_1_1, _mask_acc_T_23)
node mask_eq_24 = and(mask_sub_4_2_1, mask_nbit_1)
node _mask_acc_T_24 = and(mask_size_1, mask_eq_24)
node mask_acc_24 = or(mask_sub_4_1_1, _mask_acc_T_24)
node mask_eq_25 = and(mask_sub_4_2_1, mask_bit_1)
node _mask_acc_T_25 = and(mask_size_1, mask_eq_25)
node mask_acc_25 = or(mask_sub_4_1_1, _mask_acc_T_25)
node mask_eq_26 = and(mask_sub_5_2_1, mask_nbit_1)
node _mask_acc_T_26 = and(mask_size_1, mask_eq_26)
node mask_acc_26 = or(mask_sub_5_1_1, _mask_acc_T_26)
node mask_eq_27 = and(mask_sub_5_2_1, mask_bit_1)
node _mask_acc_T_27 = and(mask_size_1, mask_eq_27)
node mask_acc_27 = or(mask_sub_5_1_1, _mask_acc_T_27)
node mask_eq_28 = and(mask_sub_6_2_1, mask_nbit_1)
node _mask_acc_T_28 = and(mask_size_1, mask_eq_28)
node mask_acc_28 = or(mask_sub_6_1_1, _mask_acc_T_28)
node mask_eq_29 = and(mask_sub_6_2_1, mask_bit_1)
node _mask_acc_T_29 = and(mask_size_1, mask_eq_29)
node mask_acc_29 = or(mask_sub_6_1_1, _mask_acc_T_29)
node mask_eq_30 = and(mask_sub_7_2_1, mask_nbit_1)
node _mask_acc_T_30 = and(mask_size_1, mask_eq_30)
node mask_acc_30 = or(mask_sub_7_1_1, _mask_acc_T_30)
node mask_eq_31 = and(mask_sub_7_2_1, mask_bit_1)
node _mask_acc_T_31 = and(mask_size_1, mask_eq_31)
node mask_acc_31 = or(mask_sub_7_1_1, _mask_acc_T_31)
node mask_lo_lo_lo_1 = cat(mask_acc_17, mask_acc_16)
node mask_lo_lo_hi_1 = cat(mask_acc_19, mask_acc_18)
node mask_lo_lo_1 = cat(mask_lo_lo_hi_1, mask_lo_lo_lo_1)
node mask_lo_hi_lo_1 = cat(mask_acc_21, mask_acc_20)
node mask_lo_hi_hi_1 = cat(mask_acc_23, mask_acc_22)
node mask_lo_hi_1 = cat(mask_lo_hi_hi_1, mask_lo_hi_lo_1)
node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1)
node mask_hi_lo_lo_1 = cat(mask_acc_25, mask_acc_24)
node mask_hi_lo_hi_1 = cat(mask_acc_27, mask_acc_26)
node mask_hi_lo_1 = cat(mask_hi_lo_hi_1, mask_hi_lo_lo_1)
node mask_hi_hi_lo_1 = cat(mask_acc_29, mask_acc_28)
node mask_hi_hi_hi_1 = cat(mask_acc_31, mask_acc_30)
node mask_hi_hi_1 = cat(mask_hi_hi_hi_1, mask_hi_hi_lo_1)
node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1)
node mask_1 = cat(mask_hi_1, mask_lo_1)
node _legal_source_T = eq(io.in.b.bits.source, UInt<8>(0h90))
node _legal_source_uncommonBits_T = or(io.in.b.bits.source, UInt<2>(0h0))
node legal_source_uncommonBits = bits(_legal_source_uncommonBits_T, 1, 0)
node _legal_source_T_1 = shr(io.in.b.bits.source, 2)
node _legal_source_T_2 = eq(_legal_source_T_1, UInt<6>(0h20))
node _legal_source_T_3 = leq(UInt<1>(0h0), legal_source_uncommonBits)
node _legal_source_T_4 = and(_legal_source_T_2, _legal_source_T_3)
node _legal_source_T_5 = leq(legal_source_uncommonBits, UInt<2>(0h3))
node _legal_source_T_6 = and(_legal_source_T_4, _legal_source_T_5)
node _legal_source_uncommonBits_T_1 = or(io.in.b.bits.source, UInt<2>(0h0))
node legal_source_uncommonBits_1 = bits(_legal_source_uncommonBits_T_1, 1, 0)
node _legal_source_T_7 = shr(io.in.b.bits.source, 2)
node _legal_source_T_8 = eq(_legal_source_T_7, UInt<6>(0h21))
node _legal_source_T_9 = leq(UInt<1>(0h0), legal_source_uncommonBits_1)
node _legal_source_T_10 = and(_legal_source_T_8, _legal_source_T_9)
node _legal_source_T_11 = leq(legal_source_uncommonBits_1, UInt<2>(0h3))
node _legal_source_T_12 = and(_legal_source_T_10, _legal_source_T_11)
node _legal_source_uncommonBits_T_2 = or(io.in.b.bits.source, UInt<2>(0h0))
node legal_source_uncommonBits_2 = bits(_legal_source_uncommonBits_T_2, 1, 0)
node _legal_source_T_13 = shr(io.in.b.bits.source, 2)
node _legal_source_T_14 = eq(_legal_source_T_13, UInt<6>(0h22))
node _legal_source_T_15 = leq(UInt<1>(0h0), legal_source_uncommonBits_2)
node _legal_source_T_16 = and(_legal_source_T_14, _legal_source_T_15)
node _legal_source_T_17 = leq(legal_source_uncommonBits_2, UInt<2>(0h3))
node _legal_source_T_18 = and(_legal_source_T_16, _legal_source_T_17)
node _legal_source_uncommonBits_T_3 = or(io.in.b.bits.source, UInt<2>(0h0))
node legal_source_uncommonBits_3 = bits(_legal_source_uncommonBits_T_3, 1, 0)
node _legal_source_T_19 = shr(io.in.b.bits.source, 2)
node _legal_source_T_20 = eq(_legal_source_T_19, UInt<6>(0h23))
node _legal_source_T_21 = leq(UInt<1>(0h0), legal_source_uncommonBits_3)
node _legal_source_T_22 = and(_legal_source_T_20, _legal_source_T_21)
node _legal_source_T_23 = leq(legal_source_uncommonBits_3, UInt<2>(0h3))
node _legal_source_T_24 = and(_legal_source_T_22, _legal_source_T_23)
node _legal_source_uncommonBits_T_4 = or(io.in.b.bits.source, UInt<6>(0h0))
node legal_source_uncommonBits_4 = bits(_legal_source_uncommonBits_T_4, 5, 0)
node _legal_source_T_25 = shr(io.in.b.bits.source, 6)
node _legal_source_T_26 = eq(_legal_source_T_25, UInt<1>(0h1))
node _legal_source_T_27 = leq(UInt<1>(0h0), legal_source_uncommonBits_4)
node _legal_source_T_28 = and(_legal_source_T_26, _legal_source_T_27)
node _legal_source_T_29 = leq(legal_source_uncommonBits_4, UInt<6>(0h3f))
node _legal_source_T_30 = and(_legal_source_T_28, _legal_source_T_29)
node _legal_source_uncommonBits_T_5 = or(io.in.b.bits.source, UInt<6>(0h0))
node legal_source_uncommonBits_5 = bits(_legal_source_uncommonBits_T_5, 5, 0)
node _legal_source_T_31 = shr(io.in.b.bits.source, 6)
node _legal_source_T_32 = eq(_legal_source_T_31, UInt<1>(0h0))
node _legal_source_T_33 = leq(UInt<1>(0h0), legal_source_uncommonBits_5)
node _legal_source_T_34 = and(_legal_source_T_32, _legal_source_T_33)
node _legal_source_T_35 = leq(legal_source_uncommonBits_5, UInt<6>(0h3f))
node _legal_source_T_36 = and(_legal_source_T_34, _legal_source_T_35)
node _legal_source_T_37 = eq(io.in.b.bits.source, UInt<8>(0ha0))
node _legal_source_T_38 = eq(io.in.b.bits.source, UInt<8>(0ha2))
wire _legal_source_WIRE : UInt<1>[9]
connect _legal_source_WIRE[0], _legal_source_T
connect _legal_source_WIRE[1], _legal_source_T_6
connect _legal_source_WIRE[2], _legal_source_T_12
connect _legal_source_WIRE[3], _legal_source_T_18
connect _legal_source_WIRE[4], _legal_source_T_24
connect _legal_source_WIRE[5], _legal_source_T_30
connect _legal_source_WIRE[6], _legal_source_T_36
connect _legal_source_WIRE[7], _legal_source_T_37
connect _legal_source_WIRE[8], _legal_source_T_38
node _legal_source_T_39 = mux(_legal_source_WIRE[0], UInt<8>(0h90), UInt<1>(0h0))
node _legal_source_T_40 = mux(_legal_source_WIRE[1], UInt<8>(0h80), UInt<1>(0h0))
node _legal_source_T_41 = mux(_legal_source_WIRE[2], UInt<8>(0h84), UInt<1>(0h0))
node _legal_source_T_42 = mux(_legal_source_WIRE[3], UInt<8>(0h88), UInt<1>(0h0))
node _legal_source_T_43 = mux(_legal_source_WIRE[4], UInt<8>(0h8c), UInt<1>(0h0))
node _legal_source_T_44 = mux(_legal_source_WIRE[5], UInt<7>(0h40), UInt<1>(0h0))
node _legal_source_T_45 = mux(_legal_source_WIRE[6], UInt<1>(0h0), UInt<1>(0h0))
node _legal_source_T_46 = mux(_legal_source_WIRE[7], UInt<8>(0ha0), UInt<1>(0h0))
node _legal_source_T_47 = mux(_legal_source_WIRE[8], UInt<8>(0ha2), UInt<1>(0h0))
node _legal_source_T_48 = or(_legal_source_T_39, _legal_source_T_40)
node _legal_source_T_49 = or(_legal_source_T_48, _legal_source_T_41)
node _legal_source_T_50 = or(_legal_source_T_49, _legal_source_T_42)
node _legal_source_T_51 = or(_legal_source_T_50, _legal_source_T_43)
node _legal_source_T_52 = or(_legal_source_T_51, _legal_source_T_44)
node _legal_source_T_53 = or(_legal_source_T_52, _legal_source_T_45)
node _legal_source_T_54 = or(_legal_source_T_53, _legal_source_T_46)
node _legal_source_T_55 = or(_legal_source_T_54, _legal_source_T_47)
wire _legal_source_WIRE_1 : UInt<8>
connect _legal_source_WIRE_1, _legal_source_T_55
node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source)
node _T_1257 = eq(io.in.b.bits.opcode, UInt<3>(0h6))
when _T_1257 :
node _T_1258 = eq(io.in.b.bits.source, UInt<8>(0h90))
node _uncommonBits_T_72 = or(io.in.b.bits.source, UInt<2>(0h0))
node uncommonBits_72 = bits(_uncommonBits_T_72, 1, 0)
node _T_1259 = shr(io.in.b.bits.source, 2)
node _T_1260 = eq(_T_1259, UInt<6>(0h20))
node _T_1261 = leq(UInt<1>(0h0), uncommonBits_72)
node _T_1262 = and(_T_1260, _T_1261)
node _T_1263 = leq(uncommonBits_72, UInt<2>(0h3))
node _T_1264 = and(_T_1262, _T_1263)
node _uncommonBits_T_73 = or(io.in.b.bits.source, UInt<2>(0h0))
node uncommonBits_73 = bits(_uncommonBits_T_73, 1, 0)
node _T_1265 = shr(io.in.b.bits.source, 2)
node _T_1266 = eq(_T_1265, UInt<6>(0h21))
node _T_1267 = leq(UInt<1>(0h0), uncommonBits_73)
node _T_1268 = and(_T_1266, _T_1267)
node _T_1269 = leq(uncommonBits_73, UInt<2>(0h3))
node _T_1270 = and(_T_1268, _T_1269)
node _uncommonBits_T_74 = or(io.in.b.bits.source, UInt<2>(0h0))
node uncommonBits_74 = bits(_uncommonBits_T_74, 1, 0)
node _T_1271 = shr(io.in.b.bits.source, 2)
node _T_1272 = eq(_T_1271, UInt<6>(0h22))
node _T_1273 = leq(UInt<1>(0h0), uncommonBits_74)
node _T_1274 = and(_T_1272, _T_1273)
node _T_1275 = leq(uncommonBits_74, UInt<2>(0h3))
node _T_1276 = and(_T_1274, _T_1275)
node _uncommonBits_T_75 = or(io.in.b.bits.source, UInt<2>(0h0))
node uncommonBits_75 = bits(_uncommonBits_T_75, 1, 0)
node _T_1277 = shr(io.in.b.bits.source, 2)
node _T_1278 = eq(_T_1277, UInt<6>(0h23))
node _T_1279 = leq(UInt<1>(0h0), uncommonBits_75)
node _T_1280 = and(_T_1278, _T_1279)
node _T_1281 = leq(uncommonBits_75, UInt<2>(0h3))
node _T_1282 = and(_T_1280, _T_1281)
node _uncommonBits_T_76 = or(io.in.b.bits.source, UInt<6>(0h0))
node uncommonBits_76 = bits(_uncommonBits_T_76, 5, 0)
node _T_1283 = shr(io.in.b.bits.source, 6)
node _T_1284 = eq(_T_1283, UInt<1>(0h1))
node _T_1285 = leq(UInt<1>(0h0), uncommonBits_76)
node _T_1286 = and(_T_1284, _T_1285)
node _T_1287 = leq(uncommonBits_76, UInt<6>(0h3f))
node _T_1288 = and(_T_1286, _T_1287)
node _uncommonBits_T_77 = or(io.in.b.bits.source, UInt<6>(0h0))
node uncommonBits_77 = bits(_uncommonBits_T_77, 5, 0)
node _T_1289 = shr(io.in.b.bits.source, 6)
node _T_1290 = eq(_T_1289, UInt<1>(0h0))
node _T_1291 = leq(UInt<1>(0h0), uncommonBits_77)
node _T_1292 = and(_T_1290, _T_1291)
node _T_1293 = leq(uncommonBits_77, UInt<6>(0h3f))
node _T_1294 = and(_T_1292, _T_1293)
node _T_1295 = eq(io.in.b.bits.source, UInt<8>(0ha0))
node _T_1296 = eq(io.in.b.bits.source, UInt<8>(0ha2))
wire _WIRE_4 : UInt<1>[9]
connect _WIRE_4[0], _T_1258
connect _WIRE_4[1], _T_1264
connect _WIRE_4[2], _T_1270
connect _WIRE_4[3], _T_1276
connect _WIRE_4[4], _T_1282
connect _WIRE_4[5], _T_1288
connect _WIRE_4[6], _T_1294
connect _WIRE_4[7], _T_1295
connect _WIRE_4[8], _T_1296
node _T_1297 = eq(UInt<3>(0h6), io.in.b.bits.size)
node _T_1298 = mux(_WIRE_4[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_1299 = mux(_WIRE_4[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_1300 = mux(_WIRE_4[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_1301 = mux(_WIRE_4[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_1302 = mux(_WIRE_4[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_1303 = mux(_WIRE_4[5], UInt<1>(0h0), UInt<1>(0h0))
node _T_1304 = mux(_WIRE_4[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_1305 = mux(_WIRE_4[7], _T_1297, UInt<1>(0h0))
node _T_1306 = mux(_WIRE_4[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_1307 = or(_T_1298, _T_1299)
node _T_1308 = or(_T_1307, _T_1300)
node _T_1309 = or(_T_1308, _T_1301)
node _T_1310 = or(_T_1309, _T_1302)
node _T_1311 = or(_T_1310, _T_1303)
node _T_1312 = or(_T_1311, _T_1304)
node _T_1313 = or(_T_1312, _T_1305)
node _T_1314 = or(_T_1313, _T_1306)
wire _WIRE_5 : UInt<1>
connect _WIRE_5, _T_1314
node _T_1315 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1316 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1317 = and(_T_1315, _T_1316)
node _T_1318 = or(UInt<1>(0h0), _T_1317)
node _T_1319 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1320 = cvt(_T_1319)
node _T_1321 = and(_T_1320, asSInt(UInt<17>(0h10000)))
node _T_1322 = asSInt(_T_1321)
node _T_1323 = eq(_T_1322, asSInt(UInt<1>(0h0)))
node _T_1324 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1325 = cvt(_T_1324)
node _T_1326 = and(_T_1325, asSInt(UInt<29>(0h10000000)))
node _T_1327 = asSInt(_T_1326)
node _T_1328 = eq(_T_1327, asSInt(UInt<1>(0h0)))
node _T_1329 = or(_T_1323, _T_1328)
node _T_1330 = and(_T_1318, _T_1329)
node _T_1331 = or(UInt<1>(0h0), _T_1330)
node _T_1332 = and(_WIRE_5, _T_1331)
node _T_1333 = asUInt(reset)
node _T_1334 = eq(_T_1333, UInt<1>(0h0))
when _T_1334 :
node _T_1335 = eq(_T_1332, UInt<1>(0h0))
when _T_1335 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86
assert(clock, _T_1332, UInt<1>(0h1), "") : assert_86
node _T_1336 = asUInt(reset)
node _T_1337 = eq(_T_1336, UInt<1>(0h0))
when _T_1337 :
node _T_1338 = eq(address_ok, UInt<1>(0h0))
when _T_1338 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87
assert(clock, address_ok, UInt<1>(0h1), "") : assert_87
node _T_1339 = asUInt(reset)
node _T_1340 = eq(_T_1339, UInt<1>(0h0))
when _T_1340 :
node _T_1341 = eq(legal_source, UInt<1>(0h0))
when _T_1341 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88
assert(clock, legal_source, UInt<1>(0h1), "") : assert_88
node _T_1342 = asUInt(reset)
node _T_1343 = eq(_T_1342, UInt<1>(0h0))
when _T_1343 :
node _T_1344 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1344 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89
node _T_1345 = leq(io.in.b.bits.param, UInt<2>(0h2))
node _T_1346 = asUInt(reset)
node _T_1347 = eq(_T_1346, UInt<1>(0h0))
when _T_1347 :
node _T_1348 = eq(_T_1345, UInt<1>(0h0))
when _T_1348 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90
assert(clock, _T_1345, UInt<1>(0h1), "") : assert_90
node _T_1349 = eq(io.in.b.bits.mask, mask_1)
node _T_1350 = asUInt(reset)
node _T_1351 = eq(_T_1350, UInt<1>(0h0))
when _T_1351 :
node _T_1352 = eq(_T_1349, UInt<1>(0h0))
when _T_1352 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91
assert(clock, _T_1349, UInt<1>(0h1), "") : assert_91
node _T_1353 = eq(io.in.b.bits.corrupt, UInt<1>(0h0))
node _T_1354 = asUInt(reset)
node _T_1355 = eq(_T_1354, UInt<1>(0h0))
when _T_1355 :
node _T_1356 = eq(_T_1353, UInt<1>(0h0))
when _T_1356 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1353, UInt<1>(0h1), "") : assert_92
node _T_1357 = eq(io.in.b.bits.opcode, UInt<3>(0h4))
when _T_1357 :
node _T_1358 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1359 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1360 = and(_T_1358, _T_1359)
node _T_1361 = or(UInt<1>(0h0), _T_1360)
node _T_1362 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1363 = cvt(_T_1362)
node _T_1364 = and(_T_1363, asSInt(UInt<17>(0h10000)))
node _T_1365 = asSInt(_T_1364)
node _T_1366 = eq(_T_1365, asSInt(UInt<1>(0h0)))
node _T_1367 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1368 = cvt(_T_1367)
node _T_1369 = and(_T_1368, asSInt(UInt<29>(0h10000000)))
node _T_1370 = asSInt(_T_1369)
node _T_1371 = eq(_T_1370, asSInt(UInt<1>(0h0)))
node _T_1372 = or(_T_1366, _T_1371)
node _T_1373 = and(_T_1361, _T_1372)
node _T_1374 = or(UInt<1>(0h0), _T_1373)
node _T_1375 = and(UInt<1>(0h0), _T_1374)
node _T_1376 = asUInt(reset)
node _T_1377 = eq(_T_1376, UInt<1>(0h0))
when _T_1377 :
node _T_1378 = eq(_T_1375, UInt<1>(0h0))
when _T_1378 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93
assert(clock, _T_1375, UInt<1>(0h1), "") : assert_93
node _T_1379 = asUInt(reset)
node _T_1380 = eq(_T_1379, UInt<1>(0h0))
when _T_1380 :
node _T_1381 = eq(address_ok, UInt<1>(0h0))
when _T_1381 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94
assert(clock, address_ok, UInt<1>(0h1), "") : assert_94
node _T_1382 = asUInt(reset)
node _T_1383 = eq(_T_1382, UInt<1>(0h0))
when _T_1383 :
node _T_1384 = eq(legal_source, UInt<1>(0h0))
when _T_1384 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95
assert(clock, legal_source, UInt<1>(0h1), "") : assert_95
node _T_1385 = asUInt(reset)
node _T_1386 = eq(_T_1385, UInt<1>(0h0))
when _T_1386 :
node _T_1387 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1387 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96
node _T_1388 = eq(io.in.b.bits.param, UInt<1>(0h0))
node _T_1389 = asUInt(reset)
node _T_1390 = eq(_T_1389, UInt<1>(0h0))
when _T_1390 :
node _T_1391 = eq(_T_1388, UInt<1>(0h0))
when _T_1391 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97
assert(clock, _T_1388, UInt<1>(0h1), "") : assert_97
node _T_1392 = eq(io.in.b.bits.mask, mask_1)
node _T_1393 = asUInt(reset)
node _T_1394 = eq(_T_1393, UInt<1>(0h0))
when _T_1394 :
node _T_1395 = eq(_T_1392, UInt<1>(0h0))
when _T_1395 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1392, UInt<1>(0h1), "") : assert_98
node _T_1396 = eq(io.in.b.bits.corrupt, UInt<1>(0h0))
node _T_1397 = asUInt(reset)
node _T_1398 = eq(_T_1397, UInt<1>(0h0))
when _T_1398 :
node _T_1399 = eq(_T_1396, UInt<1>(0h0))
when _T_1399 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99
assert(clock, _T_1396, UInt<1>(0h1), "") : assert_99
node _T_1400 = eq(io.in.b.bits.opcode, UInt<1>(0h0))
when _T_1400 :
node _T_1401 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1402 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1403 = and(_T_1401, _T_1402)
node _T_1404 = or(UInt<1>(0h0), _T_1403)
node _T_1405 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1406 = cvt(_T_1405)
node _T_1407 = and(_T_1406, asSInt(UInt<17>(0h10000)))
node _T_1408 = asSInt(_T_1407)
node _T_1409 = eq(_T_1408, asSInt(UInt<1>(0h0)))
node _T_1410 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1411 = cvt(_T_1410)
node _T_1412 = and(_T_1411, asSInt(UInt<29>(0h10000000)))
node _T_1413 = asSInt(_T_1412)
node _T_1414 = eq(_T_1413, asSInt(UInt<1>(0h0)))
node _T_1415 = or(_T_1409, _T_1414)
node _T_1416 = and(_T_1404, _T_1415)
node _T_1417 = or(UInt<1>(0h0), _T_1416)
node _T_1418 = and(UInt<1>(0h0), _T_1417)
node _T_1419 = asUInt(reset)
node _T_1420 = eq(_T_1419, UInt<1>(0h0))
when _T_1420 :
node _T_1421 = eq(_T_1418, UInt<1>(0h0))
when _T_1421 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100
assert(clock, _T_1418, UInt<1>(0h1), "") : assert_100
node _T_1422 = asUInt(reset)
node _T_1423 = eq(_T_1422, UInt<1>(0h0))
when _T_1423 :
node _T_1424 = eq(address_ok, UInt<1>(0h0))
when _T_1424 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101
assert(clock, address_ok, UInt<1>(0h1), "") : assert_101
node _T_1425 = asUInt(reset)
node _T_1426 = eq(_T_1425, UInt<1>(0h0))
when _T_1426 :
node _T_1427 = eq(legal_source, UInt<1>(0h0))
when _T_1427 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102
assert(clock, legal_source, UInt<1>(0h1), "") : assert_102
node _T_1428 = asUInt(reset)
node _T_1429 = eq(_T_1428, UInt<1>(0h0))
when _T_1429 :
node _T_1430 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1430 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103
node _T_1431 = eq(io.in.b.bits.param, UInt<1>(0h0))
node _T_1432 = asUInt(reset)
node _T_1433 = eq(_T_1432, UInt<1>(0h0))
when _T_1433 :
node _T_1434 = eq(_T_1431, UInt<1>(0h0))
when _T_1434 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104
assert(clock, _T_1431, UInt<1>(0h1), "") : assert_104
node _T_1435 = eq(io.in.b.bits.mask, mask_1)
node _T_1436 = asUInt(reset)
node _T_1437 = eq(_T_1436, UInt<1>(0h0))
when _T_1437 :
node _T_1438 = eq(_T_1435, UInt<1>(0h0))
when _T_1438 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_1435, UInt<1>(0h1), "") : assert_105
node _T_1439 = eq(io.in.b.bits.opcode, UInt<1>(0h1))
when _T_1439 :
node _T_1440 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1441 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1442 = and(_T_1440, _T_1441)
node _T_1443 = or(UInt<1>(0h0), _T_1442)
node _T_1444 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1445 = cvt(_T_1444)
node _T_1446 = and(_T_1445, asSInt(UInt<17>(0h10000)))
node _T_1447 = asSInt(_T_1446)
node _T_1448 = eq(_T_1447, asSInt(UInt<1>(0h0)))
node _T_1449 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1450 = cvt(_T_1449)
node _T_1451 = and(_T_1450, asSInt(UInt<29>(0h10000000)))
node _T_1452 = asSInt(_T_1451)
node _T_1453 = eq(_T_1452, asSInt(UInt<1>(0h0)))
node _T_1454 = or(_T_1448, _T_1453)
node _T_1455 = and(_T_1443, _T_1454)
node _T_1456 = or(UInt<1>(0h0), _T_1455)
node _T_1457 = and(UInt<1>(0h0), _T_1456)
node _T_1458 = asUInt(reset)
node _T_1459 = eq(_T_1458, UInt<1>(0h0))
when _T_1459 :
node _T_1460 = eq(_T_1457, UInt<1>(0h0))
when _T_1460 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1457, UInt<1>(0h1), "") : assert_106
node _T_1461 = asUInt(reset)
node _T_1462 = eq(_T_1461, UInt<1>(0h0))
when _T_1462 :
node _T_1463 = eq(address_ok, UInt<1>(0h0))
when _T_1463 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, address_ok, UInt<1>(0h1), "") : assert_107
node _T_1464 = asUInt(reset)
node _T_1465 = eq(_T_1464, UInt<1>(0h0))
when _T_1465 :
node _T_1466 = eq(legal_source, UInt<1>(0h0))
when _T_1466 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108
assert(clock, legal_source, UInt<1>(0h1), "") : assert_108
node _T_1467 = asUInt(reset)
node _T_1468 = eq(_T_1467, UInt<1>(0h0))
when _T_1468 :
node _T_1469 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1469 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109
node _T_1470 = eq(io.in.b.bits.param, UInt<1>(0h0))
node _T_1471 = asUInt(reset)
node _T_1472 = eq(_T_1471, UInt<1>(0h0))
when _T_1472 :
node _T_1473 = eq(_T_1470, UInt<1>(0h0))
when _T_1473 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110
assert(clock, _T_1470, UInt<1>(0h1), "") : assert_110
node _T_1474 = not(mask_1)
node _T_1475 = and(io.in.b.bits.mask, _T_1474)
node _T_1476 = eq(_T_1475, UInt<1>(0h0))
node _T_1477 = asUInt(reset)
node _T_1478 = eq(_T_1477, UInt<1>(0h0))
when _T_1478 :
node _T_1479 = eq(_T_1476, UInt<1>(0h0))
when _T_1479 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_1476, UInt<1>(0h1), "") : assert_111
node _T_1480 = eq(io.in.b.bits.opcode, UInt<2>(0h2))
when _T_1480 :
node _T_1481 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1482 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1483 = and(_T_1481, _T_1482)
node _T_1484 = or(UInt<1>(0h0), _T_1483)
node _T_1485 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1486 = cvt(_T_1485)
node _T_1487 = and(_T_1486, asSInt(UInt<17>(0h10000)))
node _T_1488 = asSInt(_T_1487)
node _T_1489 = eq(_T_1488, asSInt(UInt<1>(0h0)))
node _T_1490 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1491 = cvt(_T_1490)
node _T_1492 = and(_T_1491, asSInt(UInt<29>(0h10000000)))
node _T_1493 = asSInt(_T_1492)
node _T_1494 = eq(_T_1493, asSInt(UInt<1>(0h0)))
node _T_1495 = or(_T_1489, _T_1494)
node _T_1496 = and(_T_1484, _T_1495)
node _T_1497 = or(UInt<1>(0h0), _T_1496)
node _T_1498 = and(UInt<1>(0h0), _T_1497)
node _T_1499 = asUInt(reset)
node _T_1500 = eq(_T_1499, UInt<1>(0h0))
when _T_1500 :
node _T_1501 = eq(_T_1498, UInt<1>(0h0))
when _T_1501 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112
assert(clock, _T_1498, UInt<1>(0h1), "") : assert_112
node _T_1502 = asUInt(reset)
node _T_1503 = eq(_T_1502, UInt<1>(0h0))
when _T_1503 :
node _T_1504 = eq(address_ok, UInt<1>(0h0))
when _T_1504 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, address_ok, UInt<1>(0h1), "") : assert_113
node _T_1505 = asUInt(reset)
node _T_1506 = eq(_T_1505, UInt<1>(0h0))
when _T_1506 :
node _T_1507 = eq(legal_source, UInt<1>(0h0))
when _T_1507 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114
assert(clock, legal_source, UInt<1>(0h1), "") : assert_114
node _T_1508 = asUInt(reset)
node _T_1509 = eq(_T_1508, UInt<1>(0h0))
when _T_1509 :
node _T_1510 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1510 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115
node _T_1511 = leq(io.in.b.bits.param, UInt<3>(0h4))
node _T_1512 = asUInt(reset)
node _T_1513 = eq(_T_1512, UInt<1>(0h0))
when _T_1513 :
node _T_1514 = eq(_T_1511, UInt<1>(0h0))
when _T_1514 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116
assert(clock, _T_1511, UInt<1>(0h1), "") : assert_116
node _T_1515 = eq(io.in.b.bits.mask, mask_1)
node _T_1516 = asUInt(reset)
node _T_1517 = eq(_T_1516, UInt<1>(0h0))
when _T_1517 :
node _T_1518 = eq(_T_1515, UInt<1>(0h0))
when _T_1518 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117
assert(clock, _T_1515, UInt<1>(0h1), "") : assert_117
node _T_1519 = eq(io.in.b.bits.opcode, UInt<2>(0h3))
when _T_1519 :
node _T_1520 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1521 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1522 = and(_T_1520, _T_1521)
node _T_1523 = or(UInt<1>(0h0), _T_1522)
node _T_1524 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1525 = cvt(_T_1524)
node _T_1526 = and(_T_1525, asSInt(UInt<17>(0h10000)))
node _T_1527 = asSInt(_T_1526)
node _T_1528 = eq(_T_1527, asSInt(UInt<1>(0h0)))
node _T_1529 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1530 = cvt(_T_1529)
node _T_1531 = and(_T_1530, asSInt(UInt<29>(0h10000000)))
node _T_1532 = asSInt(_T_1531)
node _T_1533 = eq(_T_1532, asSInt(UInt<1>(0h0)))
node _T_1534 = or(_T_1528, _T_1533)
node _T_1535 = and(_T_1523, _T_1534)
node _T_1536 = or(UInt<1>(0h0), _T_1535)
node _T_1537 = and(UInt<1>(0h0), _T_1536)
node _T_1538 = asUInt(reset)
node _T_1539 = eq(_T_1538, UInt<1>(0h0))
when _T_1539 :
node _T_1540 = eq(_T_1537, UInt<1>(0h0))
when _T_1540 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118
assert(clock, _T_1537, UInt<1>(0h1), "") : assert_118
node _T_1541 = asUInt(reset)
node _T_1542 = eq(_T_1541, UInt<1>(0h0))
when _T_1542 :
node _T_1543 = eq(address_ok, UInt<1>(0h0))
when _T_1543 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119
assert(clock, address_ok, UInt<1>(0h1), "") : assert_119
node _T_1544 = asUInt(reset)
node _T_1545 = eq(_T_1544, UInt<1>(0h0))
when _T_1545 :
node _T_1546 = eq(legal_source, UInt<1>(0h0))
when _T_1546 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120
assert(clock, legal_source, UInt<1>(0h1), "") : assert_120
node _T_1547 = asUInt(reset)
node _T_1548 = eq(_T_1547, UInt<1>(0h0))
when _T_1548 :
node _T_1549 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1549 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121
node _T_1550 = leq(io.in.b.bits.param, UInt<3>(0h3))
node _T_1551 = asUInt(reset)
node _T_1552 = eq(_T_1551, UInt<1>(0h0))
when _T_1552 :
node _T_1553 = eq(_T_1550, UInt<1>(0h0))
when _T_1553 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122
assert(clock, _T_1550, UInt<1>(0h1), "") : assert_122
node _T_1554 = eq(io.in.b.bits.mask, mask_1)
node _T_1555 = asUInt(reset)
node _T_1556 = eq(_T_1555, UInt<1>(0h0))
when _T_1556 :
node _T_1557 = eq(_T_1554, UInt<1>(0h0))
when _T_1557 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123
assert(clock, _T_1554, UInt<1>(0h1), "") : assert_123
node _T_1558 = eq(io.in.b.bits.opcode, UInt<3>(0h5))
when _T_1558 :
node _T_1559 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1560 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1561 = and(_T_1559, _T_1560)
node _T_1562 = or(UInt<1>(0h0), _T_1561)
node _T_1563 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1564 = cvt(_T_1563)
node _T_1565 = and(_T_1564, asSInt(UInt<17>(0h10000)))
node _T_1566 = asSInt(_T_1565)
node _T_1567 = eq(_T_1566, asSInt(UInt<1>(0h0)))
node _T_1568 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1569 = cvt(_T_1568)
node _T_1570 = and(_T_1569, asSInt(UInt<29>(0h10000000)))
node _T_1571 = asSInt(_T_1570)
node _T_1572 = eq(_T_1571, asSInt(UInt<1>(0h0)))
node _T_1573 = or(_T_1567, _T_1572)
node _T_1574 = and(_T_1562, _T_1573)
node _T_1575 = or(UInt<1>(0h0), _T_1574)
node _T_1576 = and(UInt<1>(0h0), _T_1575)
node _T_1577 = asUInt(reset)
node _T_1578 = eq(_T_1577, UInt<1>(0h0))
when _T_1578 :
node _T_1579 = eq(_T_1576, UInt<1>(0h0))
when _T_1579 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124
assert(clock, _T_1576, UInt<1>(0h1), "") : assert_124
node _T_1580 = asUInt(reset)
node _T_1581 = eq(_T_1580, UInt<1>(0h0))
when _T_1581 :
node _T_1582 = eq(address_ok, UInt<1>(0h0))
when _T_1582 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125
assert(clock, address_ok, UInt<1>(0h1), "") : assert_125
node _T_1583 = asUInt(reset)
node _T_1584 = eq(_T_1583, UInt<1>(0h0))
when _T_1584 :
node _T_1585 = eq(legal_source, UInt<1>(0h0))
when _T_1585 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126
assert(clock, legal_source, UInt<1>(0h1), "") : assert_126
node _T_1586 = asUInt(reset)
node _T_1587 = eq(_T_1586, UInt<1>(0h0))
when _T_1587 :
node _T_1588 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1588 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127
node _T_1589 = eq(io.in.b.bits.mask, mask_1)
node _T_1590 = asUInt(reset)
node _T_1591 = eq(_T_1590, UInt<1>(0h0))
when _T_1591 :
node _T_1592 = eq(_T_1589, UInt<1>(0h0))
when _T_1592 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128
assert(clock, _T_1589, UInt<1>(0h1), "") : assert_128
node _T_1593 = eq(io.in.b.bits.corrupt, UInt<1>(0h0))
node _T_1594 = asUInt(reset)
node _T_1595 = eq(_T_1594, UInt<1>(0h0))
when _T_1595 :
node _T_1596 = eq(_T_1593, UInt<1>(0h0))
when _T_1596 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129
assert(clock, _T_1593, UInt<1>(0h1), "") : assert_129
when io.in.c.valid :
node _T_1597 = leq(io.in.c.bits.opcode, UInt<3>(0h7))
node _T_1598 = asUInt(reset)
node _T_1599 = eq(_T_1598, UInt<1>(0h0))
when _T_1599 :
node _T_1600 = eq(_T_1597, UInt<1>(0h0))
when _T_1600 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130
assert(clock, _T_1597, UInt<1>(0h1), "") : assert_130
node _source_ok_T_92 = eq(io.in.c.bits.source, UInt<8>(0h90))
node _source_ok_uncommonBits_T_12 = or(io.in.c.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_12 = bits(_source_ok_uncommonBits_T_12, 1, 0)
node _source_ok_T_93 = shr(io.in.c.bits.source, 2)
node _source_ok_T_94 = eq(_source_ok_T_93, UInt<6>(0h20))
node _source_ok_T_95 = leq(UInt<1>(0h0), source_ok_uncommonBits_12)
node _source_ok_T_96 = and(_source_ok_T_94, _source_ok_T_95)
node _source_ok_T_97 = leq(source_ok_uncommonBits_12, UInt<2>(0h3))
node _source_ok_T_98 = and(_source_ok_T_96, _source_ok_T_97)
node _source_ok_uncommonBits_T_13 = or(io.in.c.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_13 = bits(_source_ok_uncommonBits_T_13, 1, 0)
node _source_ok_T_99 = shr(io.in.c.bits.source, 2)
node _source_ok_T_100 = eq(_source_ok_T_99, UInt<6>(0h21))
node _source_ok_T_101 = leq(UInt<1>(0h0), source_ok_uncommonBits_13)
node _source_ok_T_102 = and(_source_ok_T_100, _source_ok_T_101)
node _source_ok_T_103 = leq(source_ok_uncommonBits_13, UInt<2>(0h3))
node _source_ok_T_104 = and(_source_ok_T_102, _source_ok_T_103)
node _source_ok_uncommonBits_T_14 = or(io.in.c.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_14 = bits(_source_ok_uncommonBits_T_14, 1, 0)
node _source_ok_T_105 = shr(io.in.c.bits.source, 2)
node _source_ok_T_106 = eq(_source_ok_T_105, UInt<6>(0h22))
node _source_ok_T_107 = leq(UInt<1>(0h0), source_ok_uncommonBits_14)
node _source_ok_T_108 = and(_source_ok_T_106, _source_ok_T_107)
node _source_ok_T_109 = leq(source_ok_uncommonBits_14, UInt<2>(0h3))
node _source_ok_T_110 = and(_source_ok_T_108, _source_ok_T_109)
node _source_ok_uncommonBits_T_15 = or(io.in.c.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_15 = bits(_source_ok_uncommonBits_T_15, 1, 0)
node _source_ok_T_111 = shr(io.in.c.bits.source, 2)
node _source_ok_T_112 = eq(_source_ok_T_111, UInt<6>(0h23))
node _source_ok_T_113 = leq(UInt<1>(0h0), source_ok_uncommonBits_15)
node _source_ok_T_114 = and(_source_ok_T_112, _source_ok_T_113)
node _source_ok_T_115 = leq(source_ok_uncommonBits_15, UInt<2>(0h3))
node _source_ok_T_116 = and(_source_ok_T_114, _source_ok_T_115)
node _source_ok_uncommonBits_T_16 = or(io.in.c.bits.source, UInt<6>(0h0))
node source_ok_uncommonBits_16 = bits(_source_ok_uncommonBits_T_16, 5, 0)
node _source_ok_T_117 = shr(io.in.c.bits.source, 6)
node _source_ok_T_118 = eq(_source_ok_T_117, UInt<1>(0h1))
node _source_ok_T_119 = leq(UInt<1>(0h0), source_ok_uncommonBits_16)
node _source_ok_T_120 = and(_source_ok_T_118, _source_ok_T_119)
node _source_ok_T_121 = leq(source_ok_uncommonBits_16, UInt<6>(0h3f))
node _source_ok_T_122 = and(_source_ok_T_120, _source_ok_T_121)
node _source_ok_uncommonBits_T_17 = or(io.in.c.bits.source, UInt<6>(0h0))
node source_ok_uncommonBits_17 = bits(_source_ok_uncommonBits_T_17, 5, 0)
node _source_ok_T_123 = shr(io.in.c.bits.source, 6)
node _source_ok_T_124 = eq(_source_ok_T_123, UInt<1>(0h0))
node _source_ok_T_125 = leq(UInt<1>(0h0), source_ok_uncommonBits_17)
node _source_ok_T_126 = and(_source_ok_T_124, _source_ok_T_125)
node _source_ok_T_127 = leq(source_ok_uncommonBits_17, UInt<6>(0h3f))
node _source_ok_T_128 = and(_source_ok_T_126, _source_ok_T_127)
node _source_ok_T_129 = eq(io.in.c.bits.source, UInt<8>(0ha0))
node _source_ok_T_130 = eq(io.in.c.bits.source, UInt<8>(0ha2))
wire _source_ok_WIRE_2 : UInt<1>[9]
connect _source_ok_WIRE_2[0], _source_ok_T_92
connect _source_ok_WIRE_2[1], _source_ok_T_98
connect _source_ok_WIRE_2[2], _source_ok_T_104
connect _source_ok_WIRE_2[3], _source_ok_T_110
connect _source_ok_WIRE_2[4], _source_ok_T_116
connect _source_ok_WIRE_2[5], _source_ok_T_122
connect _source_ok_WIRE_2[6], _source_ok_T_128
connect _source_ok_WIRE_2[7], _source_ok_T_129
connect _source_ok_WIRE_2[8], _source_ok_T_130
node _source_ok_T_131 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1])
node _source_ok_T_132 = or(_source_ok_T_131, _source_ok_WIRE_2[2])
node _source_ok_T_133 = or(_source_ok_T_132, _source_ok_WIRE_2[3])
node _source_ok_T_134 = or(_source_ok_T_133, _source_ok_WIRE_2[4])
node _source_ok_T_135 = or(_source_ok_T_134, _source_ok_WIRE_2[5])
node _source_ok_T_136 = or(_source_ok_T_135, _source_ok_WIRE_2[6])
node _source_ok_T_137 = or(_source_ok_T_136, _source_ok_WIRE_2[7])
node source_ok_2 = or(_source_ok_T_137, _source_ok_WIRE_2[8])
node _is_aligned_mask_T_4 = dshl(UInt<6>(0h3f), io.in.c.bits.size)
node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 5, 0)
node is_aligned_mask_2 = not(_is_aligned_mask_T_5)
node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2)
node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0))
node _address_ok_T_10 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _address_ok_T_11 = cvt(_address_ok_T_10)
node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<17>(0h10000)))
node _address_ok_T_13 = asSInt(_address_ok_T_12)
node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0)))
node _address_ok_T_15 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _address_ok_T_16 = cvt(_address_ok_T_15)
node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<29>(0h10000000)))
node _address_ok_T_18 = asSInt(_address_ok_T_17)
node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0)))
wire _address_ok_WIRE_1 : UInt<1>[2]
connect _address_ok_WIRE_1[0], _address_ok_T_14
connect _address_ok_WIRE_1[1], _address_ok_T_19
node address_ok_1 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1])
node _T_1601 = eq(io.in.c.bits.source, UInt<8>(0h90))
node _T_1602 = eq(_T_1601, UInt<1>(0h0))
node _T_1603 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1604 = cvt(_T_1603)
node _T_1605 = and(_T_1604, asSInt(UInt<1>(0h0)))
node _T_1606 = asSInt(_T_1605)
node _T_1607 = eq(_T_1606, asSInt(UInt<1>(0h0)))
node _T_1608 = or(_T_1602, _T_1607)
node _uncommonBits_T_78 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_78 = bits(_uncommonBits_T_78, 1, 0)
node _T_1609 = shr(io.in.c.bits.source, 2)
node _T_1610 = eq(_T_1609, UInt<6>(0h20))
node _T_1611 = leq(UInt<1>(0h0), uncommonBits_78)
node _T_1612 = and(_T_1610, _T_1611)
node _T_1613 = leq(uncommonBits_78, UInt<2>(0h3))
node _T_1614 = and(_T_1612, _T_1613)
node _T_1615 = eq(_T_1614, UInt<1>(0h0))
node _T_1616 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1617 = cvt(_T_1616)
node _T_1618 = and(_T_1617, asSInt(UInt<1>(0h0)))
node _T_1619 = asSInt(_T_1618)
node _T_1620 = eq(_T_1619, asSInt(UInt<1>(0h0)))
node _T_1621 = or(_T_1615, _T_1620)
node _uncommonBits_T_79 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_79 = bits(_uncommonBits_T_79, 1, 0)
node _T_1622 = shr(io.in.c.bits.source, 2)
node _T_1623 = eq(_T_1622, UInt<6>(0h21))
node _T_1624 = leq(UInt<1>(0h0), uncommonBits_79)
node _T_1625 = and(_T_1623, _T_1624)
node _T_1626 = leq(uncommonBits_79, UInt<2>(0h3))
node _T_1627 = and(_T_1625, _T_1626)
node _T_1628 = eq(_T_1627, UInt<1>(0h0))
node _T_1629 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1630 = cvt(_T_1629)
node _T_1631 = and(_T_1630, asSInt(UInt<1>(0h0)))
node _T_1632 = asSInt(_T_1631)
node _T_1633 = eq(_T_1632, asSInt(UInt<1>(0h0)))
node _T_1634 = or(_T_1628, _T_1633)
node _uncommonBits_T_80 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_80 = bits(_uncommonBits_T_80, 1, 0)
node _T_1635 = shr(io.in.c.bits.source, 2)
node _T_1636 = eq(_T_1635, UInt<6>(0h22))
node _T_1637 = leq(UInt<1>(0h0), uncommonBits_80)
node _T_1638 = and(_T_1636, _T_1637)
node _T_1639 = leq(uncommonBits_80, UInt<2>(0h3))
node _T_1640 = and(_T_1638, _T_1639)
node _T_1641 = eq(_T_1640, UInt<1>(0h0))
node _T_1642 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1643 = cvt(_T_1642)
node _T_1644 = and(_T_1643, asSInt(UInt<1>(0h0)))
node _T_1645 = asSInt(_T_1644)
node _T_1646 = eq(_T_1645, asSInt(UInt<1>(0h0)))
node _T_1647 = or(_T_1641, _T_1646)
node _uncommonBits_T_81 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_81 = bits(_uncommonBits_T_81, 1, 0)
node _T_1648 = shr(io.in.c.bits.source, 2)
node _T_1649 = eq(_T_1648, UInt<6>(0h23))
node _T_1650 = leq(UInt<1>(0h0), uncommonBits_81)
node _T_1651 = and(_T_1649, _T_1650)
node _T_1652 = leq(uncommonBits_81, UInt<2>(0h3))
node _T_1653 = and(_T_1651, _T_1652)
node _T_1654 = eq(_T_1653, UInt<1>(0h0))
node _T_1655 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1656 = cvt(_T_1655)
node _T_1657 = and(_T_1656, asSInt(UInt<1>(0h0)))
node _T_1658 = asSInt(_T_1657)
node _T_1659 = eq(_T_1658, asSInt(UInt<1>(0h0)))
node _T_1660 = or(_T_1654, _T_1659)
node _uncommonBits_T_82 = or(io.in.c.bits.source, UInt<6>(0h0))
node uncommonBits_82 = bits(_uncommonBits_T_82, 5, 0)
node _T_1661 = shr(io.in.c.bits.source, 6)
node _T_1662 = eq(_T_1661, UInt<1>(0h1))
node _T_1663 = leq(UInt<1>(0h0), uncommonBits_82)
node _T_1664 = and(_T_1662, _T_1663)
node _T_1665 = leq(uncommonBits_82, UInt<6>(0h3f))
node _T_1666 = and(_T_1664, _T_1665)
node _T_1667 = eq(_T_1666, UInt<1>(0h0))
node _T_1668 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1669 = cvt(_T_1668)
node _T_1670 = and(_T_1669, asSInt(UInt<1>(0h0)))
node _T_1671 = asSInt(_T_1670)
node _T_1672 = eq(_T_1671, asSInt(UInt<1>(0h0)))
node _T_1673 = or(_T_1667, _T_1672)
node _uncommonBits_T_83 = or(io.in.c.bits.source, UInt<6>(0h0))
node uncommonBits_83 = bits(_uncommonBits_T_83, 5, 0)
node _T_1674 = shr(io.in.c.bits.source, 6)
node _T_1675 = eq(_T_1674, UInt<1>(0h0))
node _T_1676 = leq(UInt<1>(0h0), uncommonBits_83)
node _T_1677 = and(_T_1675, _T_1676)
node _T_1678 = leq(uncommonBits_83, UInt<6>(0h3f))
node _T_1679 = and(_T_1677, _T_1678)
node _T_1680 = eq(_T_1679, UInt<1>(0h0))
node _T_1681 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1682 = cvt(_T_1681)
node _T_1683 = and(_T_1682, asSInt(UInt<1>(0h0)))
node _T_1684 = asSInt(_T_1683)
node _T_1685 = eq(_T_1684, asSInt(UInt<1>(0h0)))
node _T_1686 = or(_T_1680, _T_1685)
node _T_1687 = eq(io.in.c.bits.source, UInt<8>(0ha0))
node _T_1688 = eq(_T_1687, UInt<1>(0h0))
node _T_1689 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1690 = cvt(_T_1689)
node _T_1691 = and(_T_1690, asSInt(UInt<1>(0h0)))
node _T_1692 = asSInt(_T_1691)
node _T_1693 = eq(_T_1692, asSInt(UInt<1>(0h0)))
node _T_1694 = or(_T_1688, _T_1693)
node _T_1695 = eq(io.in.c.bits.source, UInt<8>(0ha2))
node _T_1696 = eq(_T_1695, UInt<1>(0h0))
node _T_1697 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1698 = cvt(_T_1697)
node _T_1699 = and(_T_1698, asSInt(UInt<1>(0h0)))
node _T_1700 = asSInt(_T_1699)
node _T_1701 = eq(_T_1700, asSInt(UInt<1>(0h0)))
node _T_1702 = or(_T_1696, _T_1701)
node _T_1703 = and(_T_1608, _T_1621)
node _T_1704 = and(_T_1703, _T_1634)
node _T_1705 = and(_T_1704, _T_1647)
node _T_1706 = and(_T_1705, _T_1660)
node _T_1707 = and(_T_1706, _T_1673)
node _T_1708 = and(_T_1707, _T_1686)
node _T_1709 = and(_T_1708, _T_1694)
node _T_1710 = and(_T_1709, _T_1702)
node _T_1711 = asUInt(reset)
node _T_1712 = eq(_T_1711, UInt<1>(0h0))
when _T_1712 :
node _T_1713 = eq(_T_1710, UInt<1>(0h0))
when _T_1713 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131
assert(clock, _T_1710, UInt<1>(0h1), "") : assert_131
node _T_1714 = eq(io.in.c.bits.opcode, UInt<3>(0h4))
when _T_1714 :
node _T_1715 = asUInt(reset)
node _T_1716 = eq(_T_1715, UInt<1>(0h0))
when _T_1716 :
node _T_1717 = eq(address_ok_1, UInt<1>(0h0))
when _T_1717 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132
node _T_1718 = asUInt(reset)
node _T_1719 = eq(_T_1718, UInt<1>(0h0))
when _T_1719 :
node _T_1720 = eq(source_ok_2, UInt<1>(0h0))
when _T_1720 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133
node _T_1721 = geq(io.in.c.bits.size, UInt<3>(0h4))
node _T_1722 = asUInt(reset)
node _T_1723 = eq(_T_1722, UInt<1>(0h0))
when _T_1723 :
node _T_1724 = eq(_T_1721, UInt<1>(0h0))
when _T_1724 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134
assert(clock, _T_1721, UInt<1>(0h1), "") : assert_134
node _T_1725 = asUInt(reset)
node _T_1726 = eq(_T_1725, UInt<1>(0h0))
when _T_1726 :
node _T_1727 = eq(is_aligned_2, UInt<1>(0h0))
when _T_1727 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135
node _T_1728 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_1729 = asUInt(reset)
node _T_1730 = eq(_T_1729, UInt<1>(0h0))
when _T_1730 :
node _T_1731 = eq(_T_1728, UInt<1>(0h0))
when _T_1731 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136
assert(clock, _T_1728, UInt<1>(0h1), "") : assert_136
node _T_1732 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_1733 = asUInt(reset)
node _T_1734 = eq(_T_1733, UInt<1>(0h0))
when _T_1734 :
node _T_1735 = eq(_T_1732, UInt<1>(0h0))
when _T_1735 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137
assert(clock, _T_1732, UInt<1>(0h1), "") : assert_137
node _T_1736 = eq(io.in.c.bits.opcode, UInt<3>(0h5))
when _T_1736 :
node _T_1737 = asUInt(reset)
node _T_1738 = eq(_T_1737, UInt<1>(0h0))
when _T_1738 :
node _T_1739 = eq(address_ok_1, UInt<1>(0h0))
when _T_1739 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138
node _T_1740 = asUInt(reset)
node _T_1741 = eq(_T_1740, UInt<1>(0h0))
when _T_1741 :
node _T_1742 = eq(source_ok_2, UInt<1>(0h0))
when _T_1742 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139
node _T_1743 = geq(io.in.c.bits.size, UInt<3>(0h4))
node _T_1744 = asUInt(reset)
node _T_1745 = eq(_T_1744, UInt<1>(0h0))
when _T_1745 :
node _T_1746 = eq(_T_1743, UInt<1>(0h0))
when _T_1746 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140
assert(clock, _T_1743, UInt<1>(0h1), "") : assert_140
node _T_1747 = asUInt(reset)
node _T_1748 = eq(_T_1747, UInt<1>(0h0))
when _T_1748 :
node _T_1749 = eq(is_aligned_2, UInt<1>(0h0))
when _T_1749 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141
node _T_1750 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_1751 = asUInt(reset)
node _T_1752 = eq(_T_1751, UInt<1>(0h0))
when _T_1752 :
node _T_1753 = eq(_T_1750, UInt<1>(0h0))
when _T_1753 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142
assert(clock, _T_1750, UInt<1>(0h1), "") : assert_142
node _T_1754 = eq(io.in.c.bits.opcode, UInt<3>(0h6))
when _T_1754 :
node _T_1755 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_1756 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_1757 = and(_T_1755, _T_1756)
node _T_1758 = eq(io.in.c.bits.source, UInt<8>(0h90))
node _uncommonBits_T_84 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_84 = bits(_uncommonBits_T_84, 1, 0)
node _T_1759 = shr(io.in.c.bits.source, 2)
node _T_1760 = eq(_T_1759, UInt<6>(0h20))
node _T_1761 = leq(UInt<1>(0h0), uncommonBits_84)
node _T_1762 = and(_T_1760, _T_1761)
node _T_1763 = leq(uncommonBits_84, UInt<2>(0h3))
node _T_1764 = and(_T_1762, _T_1763)
node _uncommonBits_T_85 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_85 = bits(_uncommonBits_T_85, 1, 0)
node _T_1765 = shr(io.in.c.bits.source, 2)
node _T_1766 = eq(_T_1765, UInt<6>(0h21))
node _T_1767 = leq(UInt<1>(0h0), uncommonBits_85)
node _T_1768 = and(_T_1766, _T_1767)
node _T_1769 = leq(uncommonBits_85, UInt<2>(0h3))
node _T_1770 = and(_T_1768, _T_1769)
node _uncommonBits_T_86 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_86 = bits(_uncommonBits_T_86, 1, 0)
node _T_1771 = shr(io.in.c.bits.source, 2)
node _T_1772 = eq(_T_1771, UInt<6>(0h22))
node _T_1773 = leq(UInt<1>(0h0), uncommonBits_86)
node _T_1774 = and(_T_1772, _T_1773)
node _T_1775 = leq(uncommonBits_86, UInt<2>(0h3))
node _T_1776 = and(_T_1774, _T_1775)
node _uncommonBits_T_87 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_87 = bits(_uncommonBits_T_87, 1, 0)
node _T_1777 = shr(io.in.c.bits.source, 2)
node _T_1778 = eq(_T_1777, UInt<6>(0h23))
node _T_1779 = leq(UInt<1>(0h0), uncommonBits_87)
node _T_1780 = and(_T_1778, _T_1779)
node _T_1781 = leq(uncommonBits_87, UInt<2>(0h3))
node _T_1782 = and(_T_1780, _T_1781)
node _uncommonBits_T_88 = or(io.in.c.bits.source, UInt<6>(0h0))
node uncommonBits_88 = bits(_uncommonBits_T_88, 5, 0)
node _T_1783 = shr(io.in.c.bits.source, 6)
node _T_1784 = eq(_T_1783, UInt<1>(0h1))
node _T_1785 = leq(UInt<1>(0h0), uncommonBits_88)
node _T_1786 = and(_T_1784, _T_1785)
node _T_1787 = leq(uncommonBits_88, UInt<6>(0h3f))
node _T_1788 = and(_T_1786, _T_1787)
node _uncommonBits_T_89 = or(io.in.c.bits.source, UInt<6>(0h0))
node uncommonBits_89 = bits(_uncommonBits_T_89, 5, 0)
node _T_1789 = shr(io.in.c.bits.source, 6)
node _T_1790 = eq(_T_1789, UInt<1>(0h0))
node _T_1791 = leq(UInt<1>(0h0), uncommonBits_89)
node _T_1792 = and(_T_1790, _T_1791)
node _T_1793 = leq(uncommonBits_89, UInt<6>(0h3f))
node _T_1794 = and(_T_1792, _T_1793)
node _T_1795 = eq(io.in.c.bits.source, UInt<8>(0ha0))
node _T_1796 = eq(io.in.c.bits.source, UInt<8>(0ha2))
node _T_1797 = or(_T_1758, _T_1764)
node _T_1798 = or(_T_1797, _T_1770)
node _T_1799 = or(_T_1798, _T_1776)
node _T_1800 = or(_T_1799, _T_1782)
node _T_1801 = or(_T_1800, _T_1788)
node _T_1802 = or(_T_1801, _T_1794)
node _T_1803 = or(_T_1802, _T_1795)
node _T_1804 = or(_T_1803, _T_1796)
node _T_1805 = and(_T_1757, _T_1804)
node _T_1806 = or(UInt<1>(0h0), _T_1805)
node _T_1807 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_1808 = or(UInt<1>(0h0), _T_1807)
node _T_1809 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _T_1810 = cvt(_T_1809)
node _T_1811 = and(_T_1810, asSInt(UInt<17>(0h10000)))
node _T_1812 = asSInt(_T_1811)
node _T_1813 = eq(_T_1812, asSInt(UInt<1>(0h0)))
node _T_1814 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _T_1815 = cvt(_T_1814)
node _T_1816 = and(_T_1815, asSInt(UInt<29>(0h10000000)))
node _T_1817 = asSInt(_T_1816)
node _T_1818 = eq(_T_1817, asSInt(UInt<1>(0h0)))
node _T_1819 = or(_T_1813, _T_1818)
node _T_1820 = and(_T_1808, _T_1819)
node _T_1821 = or(UInt<1>(0h0), _T_1820)
node _T_1822 = and(_T_1806, _T_1821)
node _T_1823 = asUInt(reset)
node _T_1824 = eq(_T_1823, UInt<1>(0h0))
when _T_1824 :
node _T_1825 = eq(_T_1822, UInt<1>(0h0))
when _T_1825 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143
assert(clock, _T_1822, UInt<1>(0h1), "") : assert_143
node _T_1826 = eq(io.in.c.bits.source, UInt<8>(0h90))
node _uncommonBits_T_90 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_90 = bits(_uncommonBits_T_90, 1, 0)
node _T_1827 = shr(io.in.c.bits.source, 2)
node _T_1828 = eq(_T_1827, UInt<6>(0h20))
node _T_1829 = leq(UInt<1>(0h0), uncommonBits_90)
node _T_1830 = and(_T_1828, _T_1829)
node _T_1831 = leq(uncommonBits_90, UInt<2>(0h3))
node _T_1832 = and(_T_1830, _T_1831)
node _uncommonBits_T_91 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_91 = bits(_uncommonBits_T_91, 1, 0)
node _T_1833 = shr(io.in.c.bits.source, 2)
node _T_1834 = eq(_T_1833, UInt<6>(0h21))
node _T_1835 = leq(UInt<1>(0h0), uncommonBits_91)
node _T_1836 = and(_T_1834, _T_1835)
node _T_1837 = leq(uncommonBits_91, UInt<2>(0h3))
node _T_1838 = and(_T_1836, _T_1837)
node _uncommonBits_T_92 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_92 = bits(_uncommonBits_T_92, 1, 0)
node _T_1839 = shr(io.in.c.bits.source, 2)
node _T_1840 = eq(_T_1839, UInt<6>(0h22))
node _T_1841 = leq(UInt<1>(0h0), uncommonBits_92)
node _T_1842 = and(_T_1840, _T_1841)
node _T_1843 = leq(uncommonBits_92, UInt<2>(0h3))
node _T_1844 = and(_T_1842, _T_1843)
node _uncommonBits_T_93 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_93 = bits(_uncommonBits_T_93, 1, 0)
node _T_1845 = shr(io.in.c.bits.source, 2)
node _T_1846 = eq(_T_1845, UInt<6>(0h23))
node _T_1847 = leq(UInt<1>(0h0), uncommonBits_93)
node _T_1848 = and(_T_1846, _T_1847)
node _T_1849 = leq(uncommonBits_93, UInt<2>(0h3))
node _T_1850 = and(_T_1848, _T_1849)
node _uncommonBits_T_94 = or(io.in.c.bits.source, UInt<6>(0h0))
node uncommonBits_94 = bits(_uncommonBits_T_94, 5, 0)
node _T_1851 = shr(io.in.c.bits.source, 6)
node _T_1852 = eq(_T_1851, UInt<1>(0h1))
node _T_1853 = leq(UInt<1>(0h0), uncommonBits_94)
node _T_1854 = and(_T_1852, _T_1853)
node _T_1855 = leq(uncommonBits_94, UInt<6>(0h3f))
node _T_1856 = and(_T_1854, _T_1855)
node _uncommonBits_T_95 = or(io.in.c.bits.source, UInt<6>(0h0))
node uncommonBits_95 = bits(_uncommonBits_T_95, 5, 0)
node _T_1857 = shr(io.in.c.bits.source, 6)
node _T_1858 = eq(_T_1857, UInt<1>(0h0))
node _T_1859 = leq(UInt<1>(0h0), uncommonBits_95)
node _T_1860 = and(_T_1858, _T_1859)
node _T_1861 = leq(uncommonBits_95, UInt<6>(0h3f))
node _T_1862 = and(_T_1860, _T_1861)
node _T_1863 = eq(io.in.c.bits.source, UInt<8>(0ha0))
node _T_1864 = eq(io.in.c.bits.source, UInt<8>(0ha2))
wire _WIRE_6 : UInt<1>[9]
connect _WIRE_6[0], _T_1826
connect _WIRE_6[1], _T_1832
connect _WIRE_6[2], _T_1838
connect _WIRE_6[3], _T_1844
connect _WIRE_6[4], _T_1850
connect _WIRE_6[5], _T_1856
connect _WIRE_6[6], _T_1862
connect _WIRE_6[7], _T_1863
connect _WIRE_6[8], _T_1864
node _T_1865 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_1866 = mux(_WIRE_6[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_1867 = mux(_WIRE_6[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_1868 = mux(_WIRE_6[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_1869 = mux(_WIRE_6[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_1870 = mux(_WIRE_6[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_1871 = mux(_WIRE_6[5], UInt<1>(0h0), UInt<1>(0h0))
node _T_1872 = mux(_WIRE_6[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_1873 = mux(_WIRE_6[7], _T_1865, UInt<1>(0h0))
node _T_1874 = mux(_WIRE_6[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_1875 = or(_T_1866, _T_1867)
node _T_1876 = or(_T_1875, _T_1868)
node _T_1877 = or(_T_1876, _T_1869)
node _T_1878 = or(_T_1877, _T_1870)
node _T_1879 = or(_T_1878, _T_1871)
node _T_1880 = or(_T_1879, _T_1872)
node _T_1881 = or(_T_1880, _T_1873)
node _T_1882 = or(_T_1881, _T_1874)
wire _WIRE_7 : UInt<1>
connect _WIRE_7, _T_1882
node _T_1883 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_1884 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_1885 = and(_T_1883, _T_1884)
node _T_1886 = or(UInt<1>(0h0), _T_1885)
node _T_1887 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _T_1888 = cvt(_T_1887)
node _T_1889 = and(_T_1888, asSInt(UInt<17>(0h10000)))
node _T_1890 = asSInt(_T_1889)
node _T_1891 = eq(_T_1890, asSInt(UInt<1>(0h0)))
node _T_1892 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _T_1893 = cvt(_T_1892)
node _T_1894 = and(_T_1893, asSInt(UInt<29>(0h10000000)))
node _T_1895 = asSInt(_T_1894)
node _T_1896 = eq(_T_1895, asSInt(UInt<1>(0h0)))
node _T_1897 = or(_T_1891, _T_1896)
node _T_1898 = and(_T_1886, _T_1897)
node _T_1899 = or(UInt<1>(0h0), _T_1898)
node _T_1900 = and(_WIRE_7, _T_1899)
node _T_1901 = asUInt(reset)
node _T_1902 = eq(_T_1901, UInt<1>(0h0))
when _T_1902 :
node _T_1903 = eq(_T_1900, UInt<1>(0h0))
when _T_1903 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144
assert(clock, _T_1900, UInt<1>(0h1), "") : assert_144
node _T_1904 = asUInt(reset)
node _T_1905 = eq(_T_1904, UInt<1>(0h0))
when _T_1905 :
node _T_1906 = eq(source_ok_2, UInt<1>(0h0))
when _T_1906 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145
node _T_1907 = geq(io.in.c.bits.size, UInt<3>(0h4))
node _T_1908 = asUInt(reset)
node _T_1909 = eq(_T_1908, UInt<1>(0h0))
when _T_1909 :
node _T_1910 = eq(_T_1907, UInt<1>(0h0))
when _T_1910 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146
assert(clock, _T_1907, UInt<1>(0h1), "") : assert_146
node _T_1911 = asUInt(reset)
node _T_1912 = eq(_T_1911, UInt<1>(0h0))
when _T_1912 :
node _T_1913 = eq(is_aligned_2, UInt<1>(0h0))
when _T_1913 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147
node _T_1914 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_1915 = asUInt(reset)
node _T_1916 = eq(_T_1915, UInt<1>(0h0))
when _T_1916 :
node _T_1917 = eq(_T_1914, UInt<1>(0h0))
when _T_1917 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148
assert(clock, _T_1914, UInt<1>(0h1), "") : assert_148
node _T_1918 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_1919 = asUInt(reset)
node _T_1920 = eq(_T_1919, UInt<1>(0h0))
when _T_1920 :
node _T_1921 = eq(_T_1918, UInt<1>(0h0))
when _T_1921 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149
assert(clock, _T_1918, UInt<1>(0h1), "") : assert_149
node _T_1922 = eq(io.in.c.bits.opcode, UInt<3>(0h7))
when _T_1922 :
node _T_1923 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_1924 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_1925 = and(_T_1923, _T_1924)
node _T_1926 = eq(io.in.c.bits.source, UInt<8>(0h90))
node _uncommonBits_T_96 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_96 = bits(_uncommonBits_T_96, 1, 0)
node _T_1927 = shr(io.in.c.bits.source, 2)
node _T_1928 = eq(_T_1927, UInt<6>(0h20))
node _T_1929 = leq(UInt<1>(0h0), uncommonBits_96)
node _T_1930 = and(_T_1928, _T_1929)
node _T_1931 = leq(uncommonBits_96, UInt<2>(0h3))
node _T_1932 = and(_T_1930, _T_1931)
node _uncommonBits_T_97 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_97 = bits(_uncommonBits_T_97, 1, 0)
node _T_1933 = shr(io.in.c.bits.source, 2)
node _T_1934 = eq(_T_1933, UInt<6>(0h21))
node _T_1935 = leq(UInt<1>(0h0), uncommonBits_97)
node _T_1936 = and(_T_1934, _T_1935)
node _T_1937 = leq(uncommonBits_97, UInt<2>(0h3))
node _T_1938 = and(_T_1936, _T_1937)
node _uncommonBits_T_98 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_98 = bits(_uncommonBits_T_98, 1, 0)
node _T_1939 = shr(io.in.c.bits.source, 2)
node _T_1940 = eq(_T_1939, UInt<6>(0h22))
node _T_1941 = leq(UInt<1>(0h0), uncommonBits_98)
node _T_1942 = and(_T_1940, _T_1941)
node _T_1943 = leq(uncommonBits_98, UInt<2>(0h3))
node _T_1944 = and(_T_1942, _T_1943)
node _uncommonBits_T_99 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_99 = bits(_uncommonBits_T_99, 1, 0)
node _T_1945 = shr(io.in.c.bits.source, 2)
node _T_1946 = eq(_T_1945, UInt<6>(0h23))
node _T_1947 = leq(UInt<1>(0h0), uncommonBits_99)
node _T_1948 = and(_T_1946, _T_1947)
node _T_1949 = leq(uncommonBits_99, UInt<2>(0h3))
node _T_1950 = and(_T_1948, _T_1949)
node _uncommonBits_T_100 = or(io.in.c.bits.source, UInt<6>(0h0))
node uncommonBits_100 = bits(_uncommonBits_T_100, 5, 0)
node _T_1951 = shr(io.in.c.bits.source, 6)
node _T_1952 = eq(_T_1951, UInt<1>(0h1))
node _T_1953 = leq(UInt<1>(0h0), uncommonBits_100)
node _T_1954 = and(_T_1952, _T_1953)
node _T_1955 = leq(uncommonBits_100, UInt<6>(0h3f))
node _T_1956 = and(_T_1954, _T_1955)
node _uncommonBits_T_101 = or(io.in.c.bits.source, UInt<6>(0h0))
node uncommonBits_101 = bits(_uncommonBits_T_101, 5, 0)
node _T_1957 = shr(io.in.c.bits.source, 6)
node _T_1958 = eq(_T_1957, UInt<1>(0h0))
node _T_1959 = leq(UInt<1>(0h0), uncommonBits_101)
node _T_1960 = and(_T_1958, _T_1959)
node _T_1961 = leq(uncommonBits_101, UInt<6>(0h3f))
node _T_1962 = and(_T_1960, _T_1961)
node _T_1963 = eq(io.in.c.bits.source, UInt<8>(0ha0))
node _T_1964 = eq(io.in.c.bits.source, UInt<8>(0ha2))
node _T_1965 = or(_T_1926, _T_1932)
node _T_1966 = or(_T_1965, _T_1938)
node _T_1967 = or(_T_1966, _T_1944)
node _T_1968 = or(_T_1967, _T_1950)
node _T_1969 = or(_T_1968, _T_1956)
node _T_1970 = or(_T_1969, _T_1962)
node _T_1971 = or(_T_1970, _T_1963)
node _T_1972 = or(_T_1971, _T_1964)
node _T_1973 = and(_T_1925, _T_1972)
node _T_1974 = or(UInt<1>(0h0), _T_1973)
node _T_1975 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_1976 = or(UInt<1>(0h0), _T_1975)
node _T_1977 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _T_1978 = cvt(_T_1977)
node _T_1979 = and(_T_1978, asSInt(UInt<17>(0h10000)))
node _T_1980 = asSInt(_T_1979)
node _T_1981 = eq(_T_1980, asSInt(UInt<1>(0h0)))
node _T_1982 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _T_1983 = cvt(_T_1982)
node _T_1984 = and(_T_1983, asSInt(UInt<29>(0h10000000)))
node _T_1985 = asSInt(_T_1984)
node _T_1986 = eq(_T_1985, asSInt(UInt<1>(0h0)))
node _T_1987 = or(_T_1981, _T_1986)
node _T_1988 = and(_T_1976, _T_1987)
node _T_1989 = or(UInt<1>(0h0), _T_1988)
node _T_1990 = and(_T_1974, _T_1989)
node _T_1991 = asUInt(reset)
node _T_1992 = eq(_T_1991, UInt<1>(0h0))
when _T_1992 :
node _T_1993 = eq(_T_1990, UInt<1>(0h0))
when _T_1993 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150
assert(clock, _T_1990, UInt<1>(0h1), "") : assert_150
node _T_1994 = eq(io.in.c.bits.source, UInt<8>(0h90))
node _uncommonBits_T_102 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_102 = bits(_uncommonBits_T_102, 1, 0)
node _T_1995 = shr(io.in.c.bits.source, 2)
node _T_1996 = eq(_T_1995, UInt<6>(0h20))
node _T_1997 = leq(UInt<1>(0h0), uncommonBits_102)
node _T_1998 = and(_T_1996, _T_1997)
node _T_1999 = leq(uncommonBits_102, UInt<2>(0h3))
node _T_2000 = and(_T_1998, _T_1999)
node _uncommonBits_T_103 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_103 = bits(_uncommonBits_T_103, 1, 0)
node _T_2001 = shr(io.in.c.bits.source, 2)
node _T_2002 = eq(_T_2001, UInt<6>(0h21))
node _T_2003 = leq(UInt<1>(0h0), uncommonBits_103)
node _T_2004 = and(_T_2002, _T_2003)
node _T_2005 = leq(uncommonBits_103, UInt<2>(0h3))
node _T_2006 = and(_T_2004, _T_2005)
node _uncommonBits_T_104 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_104 = bits(_uncommonBits_T_104, 1, 0)
node _T_2007 = shr(io.in.c.bits.source, 2)
node _T_2008 = eq(_T_2007, UInt<6>(0h22))
node _T_2009 = leq(UInt<1>(0h0), uncommonBits_104)
node _T_2010 = and(_T_2008, _T_2009)
node _T_2011 = leq(uncommonBits_104, UInt<2>(0h3))
node _T_2012 = and(_T_2010, _T_2011)
node _uncommonBits_T_105 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_105 = bits(_uncommonBits_T_105, 1, 0)
node _T_2013 = shr(io.in.c.bits.source, 2)
node _T_2014 = eq(_T_2013, UInt<6>(0h23))
node _T_2015 = leq(UInt<1>(0h0), uncommonBits_105)
node _T_2016 = and(_T_2014, _T_2015)
node _T_2017 = leq(uncommonBits_105, UInt<2>(0h3))
node _T_2018 = and(_T_2016, _T_2017)
node _uncommonBits_T_106 = or(io.in.c.bits.source, UInt<6>(0h0))
node uncommonBits_106 = bits(_uncommonBits_T_106, 5, 0)
node _T_2019 = shr(io.in.c.bits.source, 6)
node _T_2020 = eq(_T_2019, UInt<1>(0h1))
node _T_2021 = leq(UInt<1>(0h0), uncommonBits_106)
node _T_2022 = and(_T_2020, _T_2021)
node _T_2023 = leq(uncommonBits_106, UInt<6>(0h3f))
node _T_2024 = and(_T_2022, _T_2023)
node _uncommonBits_T_107 = or(io.in.c.bits.source, UInt<6>(0h0))
node uncommonBits_107 = bits(_uncommonBits_T_107, 5, 0)
node _T_2025 = shr(io.in.c.bits.source, 6)
node _T_2026 = eq(_T_2025, UInt<1>(0h0))
node _T_2027 = leq(UInt<1>(0h0), uncommonBits_107)
node _T_2028 = and(_T_2026, _T_2027)
node _T_2029 = leq(uncommonBits_107, UInt<6>(0h3f))
node _T_2030 = and(_T_2028, _T_2029)
node _T_2031 = eq(io.in.c.bits.source, UInt<8>(0ha0))
node _T_2032 = eq(io.in.c.bits.source, UInt<8>(0ha2))
wire _WIRE_8 : UInt<1>[9]
connect _WIRE_8[0], _T_1994
connect _WIRE_8[1], _T_2000
connect _WIRE_8[2], _T_2006
connect _WIRE_8[3], _T_2012
connect _WIRE_8[4], _T_2018
connect _WIRE_8[5], _T_2024
connect _WIRE_8[6], _T_2030
connect _WIRE_8[7], _T_2031
connect _WIRE_8[8], _T_2032
node _T_2033 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_2034 = mux(_WIRE_8[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_2035 = mux(_WIRE_8[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_2036 = mux(_WIRE_8[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_2037 = mux(_WIRE_8[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_2038 = mux(_WIRE_8[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_2039 = mux(_WIRE_8[5], UInt<1>(0h0), UInt<1>(0h0))
node _T_2040 = mux(_WIRE_8[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_2041 = mux(_WIRE_8[7], _T_2033, UInt<1>(0h0))
node _T_2042 = mux(_WIRE_8[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_2043 = or(_T_2034, _T_2035)
node _T_2044 = or(_T_2043, _T_2036)
node _T_2045 = or(_T_2044, _T_2037)
node _T_2046 = or(_T_2045, _T_2038)
node _T_2047 = or(_T_2046, _T_2039)
node _T_2048 = or(_T_2047, _T_2040)
node _T_2049 = or(_T_2048, _T_2041)
node _T_2050 = or(_T_2049, _T_2042)
wire _WIRE_9 : UInt<1>
connect _WIRE_9, _T_2050
node _T_2051 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_2052 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_2053 = and(_T_2051, _T_2052)
node _T_2054 = or(UInt<1>(0h0), _T_2053)
node _T_2055 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _T_2056 = cvt(_T_2055)
node _T_2057 = and(_T_2056, asSInt(UInt<17>(0h10000)))
node _T_2058 = asSInt(_T_2057)
node _T_2059 = eq(_T_2058, asSInt(UInt<1>(0h0)))
node _T_2060 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _T_2061 = cvt(_T_2060)
node _T_2062 = and(_T_2061, asSInt(UInt<29>(0h10000000)))
node _T_2063 = asSInt(_T_2062)
node _T_2064 = eq(_T_2063, asSInt(UInt<1>(0h0)))
node _T_2065 = or(_T_2059, _T_2064)
node _T_2066 = and(_T_2054, _T_2065)
node _T_2067 = or(UInt<1>(0h0), _T_2066)
node _T_2068 = and(_WIRE_9, _T_2067)
node _T_2069 = asUInt(reset)
node _T_2070 = eq(_T_2069, UInt<1>(0h0))
when _T_2070 :
node _T_2071 = eq(_T_2068, UInt<1>(0h0))
when _T_2071 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151
assert(clock, _T_2068, UInt<1>(0h1), "") : assert_151
node _T_2072 = asUInt(reset)
node _T_2073 = eq(_T_2072, UInt<1>(0h0))
when _T_2073 :
node _T_2074 = eq(source_ok_2, UInt<1>(0h0))
when _T_2074 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152
node _T_2075 = geq(io.in.c.bits.size, UInt<3>(0h4))
node _T_2076 = asUInt(reset)
node _T_2077 = eq(_T_2076, UInt<1>(0h0))
when _T_2077 :
node _T_2078 = eq(_T_2075, UInt<1>(0h0))
when _T_2078 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153
assert(clock, _T_2075, UInt<1>(0h1), "") : assert_153
node _T_2079 = asUInt(reset)
node _T_2080 = eq(_T_2079, UInt<1>(0h0))
when _T_2080 :
node _T_2081 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2081 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154
node _T_2082 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_2083 = asUInt(reset)
node _T_2084 = eq(_T_2083, UInt<1>(0h0))
when _T_2084 :
node _T_2085 = eq(_T_2082, UInt<1>(0h0))
when _T_2085 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155
assert(clock, _T_2082, UInt<1>(0h1), "") : assert_155
node _T_2086 = eq(io.in.c.bits.opcode, UInt<1>(0h0))
when _T_2086 :
node _T_2087 = asUInt(reset)
node _T_2088 = eq(_T_2087, UInt<1>(0h0))
when _T_2088 :
node _T_2089 = eq(address_ok_1, UInt<1>(0h0))
when _T_2089 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156
node _T_2090 = asUInt(reset)
node _T_2091 = eq(_T_2090, UInt<1>(0h0))
when _T_2091 :
node _T_2092 = eq(source_ok_2, UInt<1>(0h0))
when _T_2092 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157
node _T_2093 = asUInt(reset)
node _T_2094 = eq(_T_2093, UInt<1>(0h0))
when _T_2094 :
node _T_2095 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2095 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158
node _T_2096 = eq(io.in.c.bits.param, UInt<1>(0h0))
node _T_2097 = asUInt(reset)
node _T_2098 = eq(_T_2097, UInt<1>(0h0))
when _T_2098 :
node _T_2099 = eq(_T_2096, UInt<1>(0h0))
when _T_2099 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159
assert(clock, _T_2096, UInt<1>(0h1), "") : assert_159
node _T_2100 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_2101 = asUInt(reset)
node _T_2102 = eq(_T_2101, UInt<1>(0h0))
when _T_2102 :
node _T_2103 = eq(_T_2100, UInt<1>(0h0))
when _T_2103 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160
assert(clock, _T_2100, UInt<1>(0h1), "") : assert_160
node _T_2104 = eq(io.in.c.bits.opcode, UInt<1>(0h1))
when _T_2104 :
node _T_2105 = asUInt(reset)
node _T_2106 = eq(_T_2105, UInt<1>(0h0))
when _T_2106 :
node _T_2107 = eq(address_ok_1, UInt<1>(0h0))
when _T_2107 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161
node _T_2108 = asUInt(reset)
node _T_2109 = eq(_T_2108, UInt<1>(0h0))
when _T_2109 :
node _T_2110 = eq(source_ok_2, UInt<1>(0h0))
when _T_2110 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162
node _T_2111 = asUInt(reset)
node _T_2112 = eq(_T_2111, UInt<1>(0h0))
when _T_2112 :
node _T_2113 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2113 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163
node _T_2114 = eq(io.in.c.bits.param, UInt<1>(0h0))
node _T_2115 = asUInt(reset)
node _T_2116 = eq(_T_2115, UInt<1>(0h0))
when _T_2116 :
node _T_2117 = eq(_T_2114, UInt<1>(0h0))
when _T_2117 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164
assert(clock, _T_2114, UInt<1>(0h1), "") : assert_164
node _T_2118 = eq(io.in.c.bits.opcode, UInt<2>(0h2))
when _T_2118 :
node _T_2119 = asUInt(reset)
node _T_2120 = eq(_T_2119, UInt<1>(0h0))
when _T_2120 :
node _T_2121 = eq(address_ok_1, UInt<1>(0h0))
when _T_2121 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165
node _T_2122 = asUInt(reset)
node _T_2123 = eq(_T_2122, UInt<1>(0h0))
when _T_2123 :
node _T_2124 = eq(source_ok_2, UInt<1>(0h0))
when _T_2124 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166
node _T_2125 = asUInt(reset)
node _T_2126 = eq(_T_2125, UInt<1>(0h0))
when _T_2126 :
node _T_2127 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167
node _T_2128 = eq(io.in.c.bits.param, UInt<1>(0h0))
node _T_2129 = asUInt(reset)
node _T_2130 = eq(_T_2129, UInt<1>(0h0))
when _T_2130 :
node _T_2131 = eq(_T_2128, UInt<1>(0h0))
when _T_2131 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168
assert(clock, _T_2128, UInt<1>(0h1), "") : assert_168
node _T_2132 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_2133 = asUInt(reset)
node _T_2134 = eq(_T_2133, UInt<1>(0h0))
when _T_2134 :
node _T_2135 = eq(_T_2132, UInt<1>(0h0))
when _T_2135 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169
assert(clock, _T_2132, UInt<1>(0h1), "") : assert_169
when io.in.e.valid :
node sink_ok_1 = lt(io.in.e.bits.sink, UInt<4>(0hc))
node _T_2136 = asUInt(reset)
node _T_2137 = eq(_T_2136, UInt<1>(0h0))
when _T_2137 :
node _T_2138 = eq(sink_ok_1, UInt<1>(0h0))
when _T_2138 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170
assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 4)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<2>, clock, reset, UInt<2>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_2139 = eq(a_first, UInt<1>(0h0))
node _T_2140 = and(io.in.a.valid, _T_2139)
when _T_2140 :
node _T_2141 = eq(io.in.a.bits.opcode, opcode)
node _T_2142 = asUInt(reset)
node _T_2143 = eq(_T_2142, UInt<1>(0h0))
when _T_2143 :
node _T_2144 = eq(_T_2141, UInt<1>(0h0))
when _T_2144 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171
assert(clock, _T_2141, UInt<1>(0h1), "") : assert_171
node _T_2145 = eq(io.in.a.bits.param, param)
node _T_2146 = asUInt(reset)
node _T_2147 = eq(_T_2146, UInt<1>(0h0))
when _T_2147 :
node _T_2148 = eq(_T_2145, UInt<1>(0h0))
when _T_2148 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172
assert(clock, _T_2145, UInt<1>(0h1), "") : assert_172
node _T_2149 = eq(io.in.a.bits.size, size)
node _T_2150 = asUInt(reset)
node _T_2151 = eq(_T_2150, UInt<1>(0h0))
when _T_2151 :
node _T_2152 = eq(_T_2149, UInt<1>(0h0))
when _T_2152 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173
assert(clock, _T_2149, UInt<1>(0h1), "") : assert_173
node _T_2153 = eq(io.in.a.bits.source, source)
node _T_2154 = asUInt(reset)
node _T_2155 = eq(_T_2154, UInt<1>(0h0))
when _T_2155 :
node _T_2156 = eq(_T_2153, UInt<1>(0h0))
when _T_2156 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174
assert(clock, _T_2153, UInt<1>(0h1), "") : assert_174
node _T_2157 = eq(io.in.a.bits.address, address)
node _T_2158 = asUInt(reset)
node _T_2159 = eq(_T_2158, UInt<1>(0h0))
when _T_2159 :
node _T_2160 = eq(_T_2157, UInt<1>(0h0))
when _T_2160 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175
assert(clock, _T_2157, UInt<1>(0h1), "") : assert_175
node _T_2161 = and(io.in.a.ready, io.in.a.valid)
node _T_2162 = and(_T_2161, a_first)
when _T_2162 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 4)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<2>, clock, reset, UInt<2>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_2163 = eq(d_first, UInt<1>(0h0))
node _T_2164 = and(io.in.d.valid, _T_2163)
when _T_2164 :
node _T_2165 = eq(io.in.d.bits.opcode, opcode_1)
node _T_2166 = asUInt(reset)
node _T_2167 = eq(_T_2166, UInt<1>(0h0))
when _T_2167 :
node _T_2168 = eq(_T_2165, UInt<1>(0h0))
when _T_2168 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176
assert(clock, _T_2165, UInt<1>(0h1), "") : assert_176
node _T_2169 = eq(io.in.d.bits.param, param_1)
node _T_2170 = asUInt(reset)
node _T_2171 = eq(_T_2170, UInt<1>(0h0))
when _T_2171 :
node _T_2172 = eq(_T_2169, UInt<1>(0h0))
when _T_2172 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177
assert(clock, _T_2169, UInt<1>(0h1), "") : assert_177
node _T_2173 = eq(io.in.d.bits.size, size_1)
node _T_2174 = asUInt(reset)
node _T_2175 = eq(_T_2174, UInt<1>(0h0))
when _T_2175 :
node _T_2176 = eq(_T_2173, UInt<1>(0h0))
when _T_2176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178
assert(clock, _T_2173, UInt<1>(0h1), "") : assert_178
node _T_2177 = eq(io.in.d.bits.source, source_1)
node _T_2178 = asUInt(reset)
node _T_2179 = eq(_T_2178, UInt<1>(0h0))
when _T_2179 :
node _T_2180 = eq(_T_2177, UInt<1>(0h0))
when _T_2180 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179
assert(clock, _T_2177, UInt<1>(0h1), "") : assert_179
node _T_2181 = eq(io.in.d.bits.sink, sink)
node _T_2182 = asUInt(reset)
node _T_2183 = eq(_T_2182, UInt<1>(0h0))
when _T_2183 :
node _T_2184 = eq(_T_2181, UInt<1>(0h0))
when _T_2184 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180
assert(clock, _T_2181, UInt<1>(0h1), "") : assert_180
node _T_2185 = eq(io.in.d.bits.denied, denied)
node _T_2186 = asUInt(reset)
node _T_2187 = eq(_T_2186, UInt<1>(0h0))
when _T_2187 :
node _T_2188 = eq(_T_2185, UInt<1>(0h0))
when _T_2188 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181
assert(clock, _T_2185, UInt<1>(0h1), "") : assert_181
node _T_2189 = and(io.in.d.ready, io.in.d.valid)
node _T_2190 = and(_T_2189, d_first)
when _T_2190 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
node _b_first_T = and(io.in.b.ready, io.in.b.valid)
node _b_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.b.bits.size)
node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 5, 0)
node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1)
node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 4)
node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2)
node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0))
node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0))
regreset b_first_counter : UInt<2>, clock, reset, UInt<2>(0h0)
node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1))
node b_first_counter1 = tail(_b_first_counter1_T, 1)
node b_first = eq(b_first_counter, UInt<1>(0h0))
node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1))
node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0))
node b_first_last = or(_b_first_last_T, _b_first_last_T_1)
node b_first_done = and(b_first_last, _b_first_T)
node _b_first_count_T = not(b_first_counter1)
node b_first_count = and(b_first_beats1, _b_first_count_T)
when _b_first_T :
node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1)
connect b_first_counter, _b_first_counter_T
reg opcode_2 : UInt, clock
reg param_2 : UInt, clock
reg size_2 : UInt, clock
reg source_2 : UInt, clock
reg address_1 : UInt, clock
node _T_2191 = eq(b_first, UInt<1>(0h0))
node _T_2192 = and(io.in.b.valid, _T_2191)
when _T_2192 :
node _T_2193 = eq(io.in.b.bits.opcode, opcode_2)
node _T_2194 = asUInt(reset)
node _T_2195 = eq(_T_2194, UInt<1>(0h0))
when _T_2195 :
node _T_2196 = eq(_T_2193, UInt<1>(0h0))
when _T_2196 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182
assert(clock, _T_2193, UInt<1>(0h1), "") : assert_182
node _T_2197 = eq(io.in.b.bits.param, param_2)
node _T_2198 = asUInt(reset)
node _T_2199 = eq(_T_2198, UInt<1>(0h0))
when _T_2199 :
node _T_2200 = eq(_T_2197, UInt<1>(0h0))
when _T_2200 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183
assert(clock, _T_2197, UInt<1>(0h1), "") : assert_183
node _T_2201 = eq(io.in.b.bits.size, size_2)
node _T_2202 = asUInt(reset)
node _T_2203 = eq(_T_2202, UInt<1>(0h0))
when _T_2203 :
node _T_2204 = eq(_T_2201, UInt<1>(0h0))
when _T_2204 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184
assert(clock, _T_2201, UInt<1>(0h1), "") : assert_184
node _T_2205 = eq(io.in.b.bits.source, source_2)
node _T_2206 = asUInt(reset)
node _T_2207 = eq(_T_2206, UInt<1>(0h0))
when _T_2207 :
node _T_2208 = eq(_T_2205, UInt<1>(0h0))
when _T_2208 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185
assert(clock, _T_2205, UInt<1>(0h1), "") : assert_185
node _T_2209 = eq(io.in.b.bits.address, address_1)
node _T_2210 = asUInt(reset)
node _T_2211 = eq(_T_2210, UInt<1>(0h0))
when _T_2211 :
node _T_2212 = eq(_T_2209, UInt<1>(0h0))
when _T_2212 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186
assert(clock, _T_2209, UInt<1>(0h1), "") : assert_186
node _T_2213 = and(io.in.b.ready, io.in.b.valid)
node _T_2214 = and(_T_2213, b_first)
when _T_2214 :
connect opcode_2, io.in.b.bits.opcode
connect param_2, io.in.b.bits.param
connect size_2, io.in.b.bits.size
connect source_2, io.in.b.bits.source
connect address_1, io.in.b.bits.address
node _c_first_T = and(io.in.c.ready, io.in.c.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.c.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 4)
node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<2>, clock, reset, UInt<2>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
reg opcode_3 : UInt, clock
reg param_3 : UInt, clock
reg size_3 : UInt, clock
reg source_3 : UInt, clock
reg address_2 : UInt, clock
node _T_2215 = eq(c_first, UInt<1>(0h0))
node _T_2216 = and(io.in.c.valid, _T_2215)
when _T_2216 :
node _T_2217 = eq(io.in.c.bits.opcode, opcode_3)
node _T_2218 = asUInt(reset)
node _T_2219 = eq(_T_2218, UInt<1>(0h0))
when _T_2219 :
node _T_2220 = eq(_T_2217, UInt<1>(0h0))
when _T_2220 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187
assert(clock, _T_2217, UInt<1>(0h1), "") : assert_187
node _T_2221 = eq(io.in.c.bits.param, param_3)
node _T_2222 = asUInt(reset)
node _T_2223 = eq(_T_2222, UInt<1>(0h0))
when _T_2223 :
node _T_2224 = eq(_T_2221, UInt<1>(0h0))
when _T_2224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188
assert(clock, _T_2221, UInt<1>(0h1), "") : assert_188
node _T_2225 = eq(io.in.c.bits.size, size_3)
node _T_2226 = asUInt(reset)
node _T_2227 = eq(_T_2226, UInt<1>(0h0))
when _T_2227 :
node _T_2228 = eq(_T_2225, UInt<1>(0h0))
when _T_2228 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189
assert(clock, _T_2225, UInt<1>(0h1), "") : assert_189
node _T_2229 = eq(io.in.c.bits.source, source_3)
node _T_2230 = asUInt(reset)
node _T_2231 = eq(_T_2230, UInt<1>(0h0))
when _T_2231 :
node _T_2232 = eq(_T_2229, UInt<1>(0h0))
when _T_2232 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190
assert(clock, _T_2229, UInt<1>(0h1), "") : assert_190
node _T_2233 = eq(io.in.c.bits.address, address_2)
node _T_2234 = asUInt(reset)
node _T_2235 = eq(_T_2234, UInt<1>(0h0))
when _T_2235 :
node _T_2236 = eq(_T_2233, UInt<1>(0h0))
when _T_2236 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191
assert(clock, _T_2233, UInt<1>(0h1), "") : assert_191
node _T_2237 = and(io.in.c.ready, io.in.c.valid)
node _T_2238 = and(_T_2237, c_first)
when _T_2238 :
connect opcode_3, io.in.c.bits.opcode
connect param_3, io.in.c.bits.param
connect size_3, io.in.c.bits.size
connect source_3, io.in.c.bits.source
connect address_2, io.in.c.bits.address
regreset inflight : UInt<163>, clock, reset, UInt<163>(0h0)
regreset inflight_opcodes : UInt<652>, clock, reset, UInt<652>(0h0)
regreset inflight_sizes : UInt<652>, clock, reset, UInt<652>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 4)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<2>, clock, reset, UInt<2>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 4)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<2>, clock, reset, UInt<2>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<163>
connect a_set, UInt<163>(0h0)
wire a_set_wo_ready : UInt<163>
connect a_set_wo_ready, UInt<163>(0h0)
wire a_opcodes_set : UInt<652>
connect a_opcodes_set, UInt<652>(0h0)
wire a_sizes_set : UInt<652>
connect a_sizes_set, UInt<652>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_2239 = and(io.in.a.valid, a_first_1)
node _T_2240 = and(_T_2239, UInt<1>(0h1))
when _T_2240 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_2241 = and(io.in.a.ready, io.in.a.valid)
node _T_2242 = and(_T_2241, a_first_1)
node _T_2243 = and(_T_2242, UInt<1>(0h1))
when _T_2243 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_2244 = dshr(inflight, io.in.a.bits.source)
node _T_2245 = bits(_T_2244, 0, 0)
node _T_2246 = eq(_T_2245, UInt<1>(0h0))
node _T_2247 = asUInt(reset)
node _T_2248 = eq(_T_2247, UInt<1>(0h0))
when _T_2248 :
node _T_2249 = eq(_T_2246, UInt<1>(0h0))
when _T_2249 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192
assert(clock, _T_2246, UInt<1>(0h1), "") : assert_192
wire d_clr : UInt<163>
connect d_clr, UInt<163>(0h0)
wire d_clr_wo_ready : UInt<163>
connect d_clr_wo_ready, UInt<163>(0h0)
wire d_opcodes_clr : UInt<652>
connect d_opcodes_clr, UInt<652>(0h0)
wire d_sizes_clr : UInt<652>
connect d_sizes_clr, UInt<652>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_2250 = and(io.in.d.valid, d_first_1)
node _T_2251 = and(_T_2250, UInt<1>(0h1))
node _T_2252 = eq(d_release_ack, UInt<1>(0h0))
node _T_2253 = and(_T_2251, _T_2252)
when _T_2253 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_2254 = and(io.in.d.ready, io.in.d.valid)
node _T_2255 = and(_T_2254, d_first_1)
node _T_2256 = and(_T_2255, UInt<1>(0h1))
node _T_2257 = eq(d_release_ack, UInt<1>(0h0))
node _T_2258 = and(_T_2256, _T_2257)
when _T_2258 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_2259 = and(io.in.d.valid, d_first_1)
node _T_2260 = and(_T_2259, UInt<1>(0h1))
node _T_2261 = eq(d_release_ack, UInt<1>(0h0))
node _T_2262 = and(_T_2260, _T_2261)
when _T_2262 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_2263 = dshr(inflight, io.in.d.bits.source)
node _T_2264 = bits(_T_2263, 0, 0)
node _T_2265 = or(_T_2264, same_cycle_resp)
node _T_2266 = asUInt(reset)
node _T_2267 = eq(_T_2266, UInt<1>(0h0))
when _T_2267 :
node _T_2268 = eq(_T_2265, UInt<1>(0h0))
when _T_2268 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193
assert(clock, _T_2265, UInt<1>(0h1), "") : assert_193
when same_cycle_resp :
node _T_2269 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_2270 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_2271 = or(_T_2269, _T_2270)
node _T_2272 = asUInt(reset)
node _T_2273 = eq(_T_2272, UInt<1>(0h0))
when _T_2273 :
node _T_2274 = eq(_T_2271, UInt<1>(0h0))
when _T_2274 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194
assert(clock, _T_2271, UInt<1>(0h1), "") : assert_194
node _T_2275 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_2276 = asUInt(reset)
node _T_2277 = eq(_T_2276, UInt<1>(0h0))
when _T_2277 :
node _T_2278 = eq(_T_2275, UInt<1>(0h0))
when _T_2278 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195
assert(clock, _T_2275, UInt<1>(0h1), "") : assert_195
else :
node _T_2279 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_2280 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_2281 = or(_T_2279, _T_2280)
node _T_2282 = asUInt(reset)
node _T_2283 = eq(_T_2282, UInt<1>(0h0))
when _T_2283 :
node _T_2284 = eq(_T_2281, UInt<1>(0h0))
when _T_2284 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196
assert(clock, _T_2281, UInt<1>(0h1), "") : assert_196
node _T_2285 = eq(io.in.d.bits.size, a_size_lookup)
node _T_2286 = asUInt(reset)
node _T_2287 = eq(_T_2286, UInt<1>(0h0))
when _T_2287 :
node _T_2288 = eq(_T_2285, UInt<1>(0h0))
when _T_2288 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197
assert(clock, _T_2285, UInt<1>(0h1), "") : assert_197
node _T_2289 = and(io.in.d.valid, d_first_1)
node _T_2290 = and(_T_2289, a_first_1)
node _T_2291 = and(_T_2290, io.in.a.valid)
node _T_2292 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_2293 = and(_T_2291, _T_2292)
node _T_2294 = eq(d_release_ack, UInt<1>(0h0))
node _T_2295 = and(_T_2293, _T_2294)
when _T_2295 :
node _T_2296 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_2297 = or(_T_2296, io.in.a.ready)
node _T_2298 = asUInt(reset)
node _T_2299 = eq(_T_2298, UInt<1>(0h0))
when _T_2299 :
node _T_2300 = eq(_T_2297, UInt<1>(0h0))
when _T_2300 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198
assert(clock, _T_2297, UInt<1>(0h1), "") : assert_198
node _T_2301 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_2302 = orr(a_set_wo_ready)
node _T_2303 = eq(_T_2302, UInt<1>(0h0))
node _T_2304 = or(_T_2301, _T_2303)
node _T_2305 = asUInt(reset)
node _T_2306 = eq(_T_2305, UInt<1>(0h0))
when _T_2306 :
node _T_2307 = eq(_T_2304, UInt<1>(0h0))
when _T_2307 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199
assert(clock, _T_2304, UInt<1>(0h1), "") : assert_199
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_74
node _T_2308 = orr(inflight)
node _T_2309 = eq(_T_2308, UInt<1>(0h0))
node _T_2310 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_2311 = or(_T_2309, _T_2310)
node _T_2312 = lt(watchdog, plusarg_reader.out)
node _T_2313 = or(_T_2311, _T_2312)
node _T_2314 = asUInt(reset)
node _T_2315 = eq(_T_2314, UInt<1>(0h0))
when _T_2315 :
node _T_2316 = eq(_T_2313, UInt<1>(0h0))
when _T_2316 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200
assert(clock, _T_2313, UInt<1>(0h1), "") : assert_200
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_2317 = and(io.in.a.ready, io.in.a.valid)
node _T_2318 = and(io.in.d.ready, io.in.d.valid)
node _T_2319 = or(_T_2317, _T_2318)
when _T_2319 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<163>, clock, reset, UInt<163>(0h0)
regreset inflight_opcodes_1 : UInt<652>, clock, reset, UInt<652>(0h0)
regreset inflight_sizes_1 : UInt<652>, clock, reset, UInt<652>(0h0)
node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid)
node _c_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.c.bits.size)
node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 5, 0)
node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4)
node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 4)
node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0)
node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0))
regreset c_first_counter_1 : UInt<2>, clock, reset, UInt<2>(0h0)
node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1))
node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1)
node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0))
node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1))
node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0))
node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3)
node c_first_done_1 = and(c_first_last_1, _c_first_T_1)
node _c_first_count_T_1 = not(c_first_counter1_1)
node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1)
when _c_first_T_1 :
node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1)
connect c_first_counter_1, _c_first_counter_T_1
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 4)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<2>, clock, reset, UInt<2>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<163>
connect c_set, UInt<163>(0h0)
wire c_set_wo_ready : UInt<163>
connect c_set_wo_ready, UInt<163>(0h0)
wire c_opcodes_set : UInt<652>
connect c_opcodes_set, UInt<652>(0h0)
wire c_sizes_set : UInt<652>
connect c_sizes_set, UInt<652>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
node _T_2320 = and(io.in.c.valid, c_first_1)
node _T_2321 = bits(io.in.c.bits.opcode, 2, 2)
node _T_2322 = bits(io.in.c.bits.opcode, 1, 1)
node _T_2323 = and(_T_2321, _T_2322)
node _T_2324 = and(_T_2320, _T_2323)
when _T_2324 :
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
node _T_2325 = and(io.in.c.ready, io.in.c.valid)
node _T_2326 = and(_T_2325, c_first_1)
node _T_2327 = bits(io.in.c.bits.opcode, 2, 2)
node _T_2328 = bits(io.in.c.bits.opcode, 1, 1)
node _T_2329 = and(_T_2327, _T_2328)
node _T_2330 = and(_T_2326, _T_2329)
when _T_2330 :
node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source)
connect c_set, _c_set_T
node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
node _T_2331 = dshr(inflight_1, io.in.c.bits.source)
node _T_2332 = bits(_T_2331, 0, 0)
node _T_2333 = eq(_T_2332, UInt<1>(0h0))
node _T_2334 = asUInt(reset)
node _T_2335 = eq(_T_2334, UInt<1>(0h0))
when _T_2335 :
node _T_2336 = eq(_T_2333, UInt<1>(0h0))
when _T_2336 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201
assert(clock, _T_2333, UInt<1>(0h1), "") : assert_201
node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4))
node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<163>
connect d_clr_1, UInt<163>(0h0)
wire d_clr_wo_ready_1 : UInt<163>
connect d_clr_wo_ready_1, UInt<163>(0h0)
wire d_opcodes_clr_1 : UInt<652>
connect d_opcodes_clr_1, UInt<652>(0h0)
wire d_sizes_clr_1 : UInt<652>
connect d_sizes_clr_1, UInt<652>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_2337 = and(io.in.d.valid, d_first_2)
node _T_2338 = and(_T_2337, UInt<1>(0h1))
node _T_2339 = and(_T_2338, d_release_ack_1)
when _T_2339 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_2340 = and(io.in.d.ready, io.in.d.valid)
node _T_2341 = and(_T_2340, d_first_2)
node _T_2342 = and(_T_2341, UInt<1>(0h1))
node _T_2343 = and(_T_2342, d_release_ack_1)
when _T_2343 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_2344 = and(io.in.d.valid, d_first_2)
node _T_2345 = and(_T_2344, UInt<1>(0h1))
node _T_2346 = and(_T_2345, d_release_ack_1)
when _T_2346 :
node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1)
node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_2347 = dshr(inflight_1, io.in.d.bits.source)
node _T_2348 = bits(_T_2347, 0, 0)
node _T_2349 = or(_T_2348, same_cycle_resp_1)
node _T_2350 = asUInt(reset)
node _T_2351 = eq(_T_2350, UInt<1>(0h0))
when _T_2351 :
node _T_2352 = eq(_T_2349, UInt<1>(0h0))
when _T_2352 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202
assert(clock, _T_2349, UInt<1>(0h1), "") : assert_202
when same_cycle_resp_1 :
node _T_2353 = eq(io.in.d.bits.size, io.in.c.bits.size)
node _T_2354 = asUInt(reset)
node _T_2355 = eq(_T_2354, UInt<1>(0h0))
when _T_2355 :
node _T_2356 = eq(_T_2353, UInt<1>(0h0))
when _T_2356 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203
assert(clock, _T_2353, UInt<1>(0h1), "") : assert_203
else :
node _T_2357 = eq(io.in.d.bits.size, c_size_lookup)
node _T_2358 = asUInt(reset)
node _T_2359 = eq(_T_2358, UInt<1>(0h0))
when _T_2359 :
node _T_2360 = eq(_T_2357, UInt<1>(0h0))
when _T_2360 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204
assert(clock, _T_2357, UInt<1>(0h1), "") : assert_204
node _T_2361 = and(io.in.d.valid, d_first_2)
node _T_2362 = and(_T_2361, c_first_1)
node _T_2363 = and(_T_2362, io.in.c.valid)
node _T_2364 = eq(io.in.c.bits.source, io.in.d.bits.source)
node _T_2365 = and(_T_2363, _T_2364)
node _T_2366 = and(_T_2365, d_release_ack_1)
node _T_2367 = eq(c_probe_ack, UInt<1>(0h0))
node _T_2368 = and(_T_2366, _T_2367)
when _T_2368 :
node _T_2369 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_2370 = or(_T_2369, io.in.c.ready)
node _T_2371 = asUInt(reset)
node _T_2372 = eq(_T_2371, UInt<1>(0h0))
when _T_2372 :
node _T_2373 = eq(_T_2370, UInt<1>(0h0))
when _T_2373 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205
assert(clock, _T_2370, UInt<1>(0h1), "") : assert_205
node _T_2374 = orr(c_set_wo_ready)
when _T_2374 :
node _T_2375 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_2376 = asUInt(reset)
node _T_2377 = eq(_T_2376, UInt<1>(0h0))
when _T_2377 :
node _T_2378 = eq(_T_2375, UInt<1>(0h0))
when _T_2378 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206
assert(clock, _T_2375, UInt<1>(0h1), "") : assert_206
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_75
node _T_2379 = orr(inflight_1)
node _T_2380 = eq(_T_2379, UInt<1>(0h0))
node _T_2381 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_2382 = or(_T_2380, _T_2381)
node _T_2383 = lt(watchdog_1, plusarg_reader_1.out)
node _T_2384 = or(_T_2382, _T_2383)
node _T_2385 = asUInt(reset)
node _T_2386 = eq(_T_2385, UInt<1>(0h0))
when _T_2386 :
node _T_2387 = eq(_T_2384, UInt<1>(0h0))
when _T_2387 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207
assert(clock, _T_2384, UInt<1>(0h1), "") : assert_207
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
node _T_2388 = and(io.in.c.ready, io.in.c.valid)
node _T_2389 = and(io.in.d.ready, io.in.d.valid)
node _T_2390 = or(_T_2388, _T_2389)
when _T_2390 :
connect watchdog_1, UInt<1>(0h0)
regreset inflight_2 : UInt<12>, clock, reset, UInt<12>(0h0)
node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_9 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 5, 0)
node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10)
node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 4)
node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0))
regreset d_first_counter_3 : UInt<2>, clock, reset, UInt<2>(0h0)
node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1))
node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1)
node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0))
node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1))
node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0))
node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7)
node d_first_done_3 = and(d_first_last_3, _d_first_T_3)
node _d_first_count_T_3 = not(d_first_counter1_3)
node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3)
when _d_first_T_3 :
node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3)
connect d_first_counter_3, _d_first_counter_T_3
wire d_set : UInt<12>
connect d_set, UInt<12>(0h0)
node _T_2391 = and(io.in.d.ready, io.in.d.valid)
node _T_2392 = and(_T_2391, d_first_3)
node _T_2393 = bits(io.in.d.bits.opcode, 2, 2)
node _T_2394 = bits(io.in.d.bits.opcode, 1, 1)
node _T_2395 = eq(_T_2394, UInt<1>(0h0))
node _T_2396 = and(_T_2393, _T_2395)
node _T_2397 = and(_T_2392, _T_2396)
when _T_2397 :
node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink)
connect d_set, _d_set_T
node _T_2398 = dshr(inflight_2, io.in.d.bits.sink)
node _T_2399 = bits(_T_2398, 0, 0)
node _T_2400 = eq(_T_2399, UInt<1>(0h0))
node _T_2401 = asUInt(reset)
node _T_2402 = eq(_T_2401, UInt<1>(0h0))
when _T_2402 :
node _T_2403 = eq(_T_2400, UInt<1>(0h0))
when _T_2403 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208
assert(clock, _T_2400, UInt<1>(0h1), "") : assert_208
wire e_clr : UInt<12>
connect e_clr, UInt<12>(0h0)
node _T_2404 = and(io.in.e.ready, io.in.e.valid)
node _T_2405 = and(_T_2404, UInt<1>(0h1))
node _T_2406 = and(_T_2405, UInt<1>(0h1))
when _T_2406 :
node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink)
connect e_clr, _e_clr_T
node _T_2407 = or(d_set, inflight_2)
node _T_2408 = dshr(_T_2407, io.in.e.bits.sink)
node _T_2409 = bits(_T_2408, 0, 0)
node _T_2410 = asUInt(reset)
node _T_2411 = eq(_T_2410, UInt<1>(0h0))
when _T_2411 :
node _T_2412 = eq(_T_2409, UInt<1>(0h0))
when _T_2412 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209
assert(clock, _T_2409, UInt<1>(0h1), "") : assert_209
node _inflight_T_6 = or(inflight_2, d_set)
node _inflight_T_7 = not(e_clr)
node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7)
connect inflight_2, _inflight_T_8 | module TLMonitor_37( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [15:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [127:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_b_ready, // @[Monitor.scala:20:14]
input io_in_b_valid, // @[Monitor.scala:20:14]
input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14]
input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14]
input io_in_c_ready, // @[Monitor.scala:20:14]
input io_in_c_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_size, // @[Monitor.scala:20:14]
input [7:0] io_in_c_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14]
input [127:0] io_in_c_bits_data, // @[Monitor.scala:20:14]
input io_in_c_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [7:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [127:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_e_valid, // @[Monitor.scala:20:14]
input [3:0] io_in_e_bits_sink // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [15:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [127:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7]
wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7]
wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7]
wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7]
wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7]
wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7]
wire [7:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7]
wire [127:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7]
wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [7:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [127:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7]
wire [3:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7]
wire io_in_e_ready = 1'h1; // @[Monitor.scala:36:7]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_49 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_61 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_63 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_67 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_69 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_73 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_75 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_79 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:57:20]
wire mask_sub_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:206:21]
wire mask_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_sub_size_1 = 1'h1; // @[Misc.scala:209:26]
wire mask_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_4_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_5_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_6_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_7_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_size_1 = 1'h1; // @[Misc.scala:209:26]
wire mask_acc_16 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_17 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_18 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_19 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_20 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_21 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_22 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_23 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_24 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_25 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_26 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_27 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_28 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_29 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_30 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_31 = 1'h1; // @[Misc.scala:215:29]
wire _legal_source_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _legal_source_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _legal_source_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _legal_source_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _legal_source_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _legal_source_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _legal_source_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _legal_source_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _legal_source_T_27 = 1'h1; // @[Parameters.scala:56:32]
wire _legal_source_T_29 = 1'h1; // @[Parameters.scala:57:20]
wire _legal_source_T_33 = 1'h1; // @[Parameters.scala:56:32]
wire _legal_source_T_35 = 1'h1; // @[Parameters.scala:57:20]
wire _legal_source_T_37 = 1'h1; // @[Parameters.scala:46:9]
wire _legal_source_WIRE_7 = 1'h1; // @[Parameters.scala:1138:31]
wire legal_source = 1'h1; // @[Monitor.scala:168:113]
wire _source_ok_T_95 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_97 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_101 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_103 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_107 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_109 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_113 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_115 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_119 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_121 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_125 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_127 = 1'h1; // @[Parameters.scala:57:20]
wire _b_first_beats1_opdata_T = 1'h1; // @[Edges.scala:97:37]
wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire b_first_last = 1'h1; // @[Edges.scala:232:33]
wire [7:0] io_in_b_bits_source = 8'hA0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_66 = 8'hA0; // @[Parameters.scala:52:29]
wire [7:0] _uncommonBits_T_67 = 8'hA0; // @[Parameters.scala:52:29]
wire [7:0] _uncommonBits_T_68 = 8'hA0; // @[Parameters.scala:52:29]
wire [7:0] _uncommonBits_T_69 = 8'hA0; // @[Parameters.scala:52:29]
wire [7:0] _uncommonBits_T_70 = 8'hA0; // @[Parameters.scala:52:29]
wire [7:0] _uncommonBits_T_71 = 8'hA0; // @[Parameters.scala:52:29]
wire [7:0] _legal_source_uncommonBits_T = 8'hA0; // @[Parameters.scala:52:29]
wire [7:0] _legal_source_uncommonBits_T_1 = 8'hA0; // @[Parameters.scala:52:29]
wire [7:0] _legal_source_uncommonBits_T_2 = 8'hA0; // @[Parameters.scala:52:29]
wire [7:0] _legal_source_uncommonBits_T_3 = 8'hA0; // @[Parameters.scala:52:29]
wire [7:0] _legal_source_uncommonBits_T_4 = 8'hA0; // @[Parameters.scala:52:29]
wire [7:0] _legal_source_uncommonBits_T_5 = 8'hA0; // @[Parameters.scala:52:29]
wire [7:0] _legal_source_T_46 = 8'hA0; // @[Mux.scala:30:73]
wire [7:0] _legal_source_T_54 = 8'hA0; // @[Mux.scala:30:73]
wire [7:0] _legal_source_T_55 = 8'hA0; // @[Mux.scala:30:73]
wire [7:0] _legal_source_WIRE_1 = 8'hA0; // @[Mux.scala:30:73]
wire [7:0] _uncommonBits_T_72 = 8'hA0; // @[Parameters.scala:52:29]
wire [7:0] _uncommonBits_T_73 = 8'hA0; // @[Parameters.scala:52:29]
wire [7:0] _uncommonBits_T_74 = 8'hA0; // @[Parameters.scala:52:29]
wire [7:0] _uncommonBits_T_75 = 8'hA0; // @[Parameters.scala:52:29]
wire [7:0] _uncommonBits_T_76 = 8'hA0; // @[Parameters.scala:52:29]
wire [7:0] _uncommonBits_T_77 = 8'hA0; // @[Parameters.scala:52:29]
wire [2:0] io_in_b_bits_opcode = 3'h6; // @[Monitor.scala:36:7]
wire [2:0] io_in_b_bits_size = 3'h6; // @[Monitor.scala:36:7]
wire [15:0] io_in_b_bits_mask = 16'hFFFF; // @[Monitor.scala:36:7]
wire [15:0] mask_1 = 16'hFFFF; // @[Misc.scala:222:10]
wire [127:0] io_in_b_bits_data = 128'h0; // @[Monitor.scala:36:7]
wire io_in_b_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire mask_sub_sub_sub_size_1 = 1'h0; // @[Misc.scala:209:26]
wire _mask_sub_sub_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_sub_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38]
wire mask_sub_size_1 = 1'h0; // @[Misc.scala:209:26]
wire _mask_sub_acc_T_8 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_9 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_10 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_11 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_12 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_13 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_14 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_15 = 1'h0; // @[Misc.scala:215:38]
wire _legal_source_T = 1'h0; // @[Parameters.scala:46:9]
wire _legal_source_T_2 = 1'h0; // @[Parameters.scala:54:32]
wire _legal_source_T_4 = 1'h0; // @[Parameters.scala:54:67]
wire _legal_source_T_6 = 1'h0; // @[Parameters.scala:56:48]
wire _legal_source_T_8 = 1'h0; // @[Parameters.scala:54:32]
wire _legal_source_T_10 = 1'h0; // @[Parameters.scala:54:67]
wire _legal_source_T_12 = 1'h0; // @[Parameters.scala:56:48]
wire _legal_source_T_14 = 1'h0; // @[Parameters.scala:54:32]
wire _legal_source_T_16 = 1'h0; // @[Parameters.scala:54:67]
wire _legal_source_T_18 = 1'h0; // @[Parameters.scala:56:48]
wire _legal_source_T_20 = 1'h0; // @[Parameters.scala:54:32]
wire _legal_source_T_22 = 1'h0; // @[Parameters.scala:54:67]
wire _legal_source_T_24 = 1'h0; // @[Parameters.scala:56:48]
wire _legal_source_T_26 = 1'h0; // @[Parameters.scala:54:32]
wire _legal_source_T_28 = 1'h0; // @[Parameters.scala:54:67]
wire _legal_source_T_30 = 1'h0; // @[Parameters.scala:56:48]
wire _legal_source_T_32 = 1'h0; // @[Parameters.scala:54:32]
wire _legal_source_T_34 = 1'h0; // @[Parameters.scala:54:67]
wire _legal_source_T_36 = 1'h0; // @[Parameters.scala:56:48]
wire _legal_source_T_38 = 1'h0; // @[Parameters.scala:46:9]
wire _legal_source_WIRE_0 = 1'h0; // @[Parameters.scala:1138:31]
wire _legal_source_WIRE_1_0 = 1'h0; // @[Parameters.scala:1138:31]
wire _legal_source_WIRE_2 = 1'h0; // @[Parameters.scala:1138:31]
wire _legal_source_WIRE_3 = 1'h0; // @[Parameters.scala:1138:31]
wire _legal_source_WIRE_4 = 1'h0; // @[Parameters.scala:1138:31]
wire _legal_source_WIRE_5 = 1'h0; // @[Parameters.scala:1138:31]
wire _legal_source_WIRE_6 = 1'h0; // @[Parameters.scala:1138:31]
wire _legal_source_WIRE_8 = 1'h0; // @[Parameters.scala:1138:31]
wire _legal_source_T_45 = 1'h0; // @[Mux.scala:30:73]
wire b_first_beats1_opdata = 1'h0; // @[Edges.scala:97:28]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [3:0] _mask_sizeOH_T_4 = 4'h4; // @[OneHot.scala:65:12]
wire [3:0] _mask_sizeOH_T_5 = 4'h4; // @[OneHot.scala:65:27]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [1:0] uncommonBits_66 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] uncommonBits_67 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] uncommonBits_68 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] uncommonBits_69 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] legal_source_uncommonBits = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] legal_source_uncommonBits_1 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] legal_source_uncommonBits_2 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] legal_source_uncommonBits_3 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] uncommonBits_72 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] uncommonBits_73 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] uncommonBits_74 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] uncommonBits_75 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] b_first_beats1 = 2'h0; // @[Edges.scala:221:14]
wire [1:0] b_first_count = 2'h0; // @[Edges.scala:234:25]
wire [1:0] mask_lo_lo_lo_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_lo_lo_hi_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_lo_hi_lo_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_lo_hi_hi_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo_lo_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo_hi_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_hi_hi_lo_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_hi_hi_hi_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] b_first_beats1_decode = 2'h3; // @[Edges.scala:220:59]
wire [5:0] is_aligned_mask_1 = 6'h3F; // @[package.scala:243:46]
wire [5:0] _b_first_beats1_decode_T_2 = 6'h3F; // @[package.scala:243:46]
wire [5:0] _is_aligned_mask_T_3 = 6'h0; // @[package.scala:243:76]
wire [5:0] _b_first_beats1_decode_T_1 = 6'h0; // @[package.scala:243:76]
wire [12:0] _is_aligned_mask_T_2 = 13'hFC0; // @[package.scala:243:71]
wire [12:0] _b_first_beats1_decode_T = 13'hFC0; // @[package.scala:243:71]
wire [5:0] uncommonBits_70 = 6'h20; // @[Parameters.scala:52:56]
wire [5:0] uncommonBits_71 = 6'h20; // @[Parameters.scala:52:56]
wire [5:0] legal_source_uncommonBits_4 = 6'h20; // @[Parameters.scala:52:56]
wire [5:0] legal_source_uncommonBits_5 = 6'h20; // @[Parameters.scala:52:56]
wire [5:0] uncommonBits_76 = 6'h20; // @[Parameters.scala:52:56]
wire [5:0] uncommonBits_77 = 6'h20; // @[Parameters.scala:52:56]
wire [7:0] _legal_source_T_39 = 8'h0; // @[Mux.scala:30:73]
wire [7:0] _legal_source_T_40 = 8'h0; // @[Mux.scala:30:73]
wire [7:0] _legal_source_T_41 = 8'h0; // @[Mux.scala:30:73]
wire [7:0] _legal_source_T_42 = 8'h0; // @[Mux.scala:30:73]
wire [7:0] _legal_source_T_43 = 8'h0; // @[Mux.scala:30:73]
wire [7:0] _legal_source_T_47 = 8'h0; // @[Mux.scala:30:73]
wire [7:0] _legal_source_T_48 = 8'h0; // @[Mux.scala:30:73]
wire [7:0] _legal_source_T_49 = 8'h0; // @[Mux.scala:30:73]
wire [7:0] _legal_source_T_50 = 8'h0; // @[Mux.scala:30:73]
wire [7:0] _legal_source_T_51 = 8'h0; // @[Mux.scala:30:73]
wire [7:0] _legal_source_T_52 = 8'h0; // @[Mux.scala:30:73]
wire [7:0] _legal_source_T_53 = 8'h0; // @[Mux.scala:30:73]
wire [6:0] _legal_source_T_44 = 7'h0; // @[Mux.scala:30:73]
wire [1:0] mask_sizeOH_shiftAmount_1 = 2'h2; // @[OneHot.scala:64:49]
wire [1:0] _legal_source_T_25 = 2'h2; // @[Parameters.scala:54:10]
wire [1:0] _legal_source_T_31 = 2'h2; // @[Parameters.scala:54:10]
wire [5:0] _legal_source_T_1 = 6'h28; // @[Parameters.scala:54:10]
wire [5:0] _legal_source_T_7 = 6'h28; // @[Parameters.scala:54:10]
wire [5:0] _legal_source_T_13 = 6'h28; // @[Parameters.scala:54:10]
wire [5:0] _legal_source_T_19 = 6'h28; // @[Parameters.scala:54:10]
wire [7:0] mask_lo_1 = 8'hFF; // @[Misc.scala:222:10]
wire [7:0] mask_hi_1 = 8'hFF; // @[Misc.scala:222:10]
wire [3:0] mask_lo_lo_1 = 4'hF; // @[Misc.scala:222:10]
wire [3:0] mask_lo_hi_1 = 4'hF; // @[Misc.scala:222:10]
wire [3:0] mask_hi_lo_1 = 4'hF; // @[Misc.scala:222:10]
wire [3:0] mask_hi_hi_1 = 4'hF; // @[Misc.scala:222:10]
wire [3:0] mask_sizeOH_1 = 4'h5; // @[Misc.scala:202:81]
wire [3:0] _mask_sizeOH_T_3 = 4'h6; // @[Misc.scala:202:34]
wire [7:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_12 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_13 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_14 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_15 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_16 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_17 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_78 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_79 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_80 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_81 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_82 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_83 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_84 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_85 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_86 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_87 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_88 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_89 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_90 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_91 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_92 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_93 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_94 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_95 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_96 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_97 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_98 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_99 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_100 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_101 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_102 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_103 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_104 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_105 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_106 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_107 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 8'h90; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] _source_ok_T_1 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_7 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_13 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_19 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 6'h20; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 6'h21; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 6'h22; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 6'h23; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire [5:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] _source_ok_T_25 = io_in_a_bits_source_0[7:6]; // @[Monitor.scala:36:7]
wire [1:0] _source_ok_T_31 = io_in_a_bits_source_0[7:6]; // @[Monitor.scala:36:7]
wire _source_ok_T_26 = _source_ok_T_25 == 2'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31]
wire [5:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[5:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_32 = _source_ok_T_31 == 2'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_6 = _source_ok_T_36; // @[Parameters.scala:1138:31]
wire _source_ok_T_37 = io_in_a_bits_source_0 == 8'hA0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_7 = _source_ok_T_37; // @[Parameters.scala:1138:31]
wire _source_ok_T_38 = io_in_a_bits_source_0 == 8'hA2; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_8 = _source_ok_T_38; // @[Parameters.scala:1138:31]
wire _source_ok_T_39 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_40 = _source_ok_T_39 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_41 = _source_ok_T_40 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_42 = _source_ok_T_41 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_43 = _source_ok_T_42 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_44 = _source_ok_T_43 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_45 = _source_ok_T_44 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_45 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [3:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [3:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}]
wire [3:0] mask_sizeOH = {_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_sub_0_1 = io_in_a_bits_size_0[2]; // @[Misc.scala:206:21]
wire mask_sub_sub_sub_size = mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26]
wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_sub_acc_T = mask_sub_sub_sub_size & mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_size & mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size & mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_2_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size & mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_3_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_4 = mask_sub_size & mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_4_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_5 = mask_sub_size & mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_5_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_6 = mask_sub_size & mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_6_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_7 = mask_sub_size & mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_7_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_8 = mask_size & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_8 = mask_sub_4_1 | _mask_acc_T_8; // @[Misc.scala:215:{29,38}]
wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_9 = mask_size & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_9 = mask_sub_4_1 | _mask_acc_T_9; // @[Misc.scala:215:{29,38}]
wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_10 = mask_size & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_10 = mask_sub_5_1 | _mask_acc_T_10; // @[Misc.scala:215:{29,38}]
wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_11 = mask_size & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_11 = mask_sub_5_1 | _mask_acc_T_11; // @[Misc.scala:215:{29,38}]
wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_12 = mask_size & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_12 = mask_sub_6_1 | _mask_acc_T_12; // @[Misc.scala:215:{29,38}]
wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_13 = mask_size & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_13 = mask_sub_6_1 | _mask_acc_T_13; // @[Misc.scala:215:{29,38}]
wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_14 = mask_size & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_14 = mask_sub_7_1 | _mask_acc_T_14; // @[Misc.scala:215:{29,38}]
wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_15 = mask_size & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_15 = mask_sub_7_1 | _mask_acc_T_15; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo_lo = {mask_lo_lo_hi, mask_lo_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_lo_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo_hi = {mask_lo_hi_hi, mask_lo_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo_lo = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_lo_hi = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi_lo = {mask_hi_lo_hi, mask_hi_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_hi_lo = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi_hi = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi_hi = {mask_hi_hi_hi, mask_hi_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [15:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_4 = _uncommonBits_T_4[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_5 = _uncommonBits_T_5[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_10 = _uncommonBits_T_10[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_11 = _uncommonBits_T_11[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_16 = _uncommonBits_T_16[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_17 = _uncommonBits_T_17[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_22 = _uncommonBits_T_22[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_23 = _uncommonBits_T_23[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_28 = _uncommonBits_T_28[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_29 = _uncommonBits_T_29[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_34 = _uncommonBits_T_34[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_35 = _uncommonBits_T_35[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_40 = _uncommonBits_T_40[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_41 = _uncommonBits_T_41[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_46 = _uncommonBits_T_46[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_47 = _uncommonBits_T_47[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_52 = _uncommonBits_T_52[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_53 = _uncommonBits_T_53[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_55 = _uncommonBits_T_55[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_58 = _uncommonBits_T_58[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_59 = _uncommonBits_T_59[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_60 = _uncommonBits_T_60[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_61 = _uncommonBits_T_61[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_62 = _uncommonBits_T_62[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_64 = _uncommonBits_T_64[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_65 = _uncommonBits_T_65[5:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_46 = io_in_d_bits_source_0 == 8'h90; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_46; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] _source_ok_T_47 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_53 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_59 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_65 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_48 = _source_ok_T_47 == 6'h20; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_50 = _source_ok_T_48; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_52; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_54 = _source_ok_T_53 == 6'h21; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_58; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_60 = _source_ok_T_59 == 6'h22; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_62 = _source_ok_T_60; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_64 = _source_ok_T_62; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_64; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_66 = _source_ok_T_65 == 6'h23; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_68 = _source_ok_T_66; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_70 = _source_ok_T_68; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_70; // @[Parameters.scala:1138:31]
wire [5:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] _source_ok_T_71 = io_in_d_bits_source_0[7:6]; // @[Monitor.scala:36:7]
wire [1:0] _source_ok_T_77 = io_in_d_bits_source_0[7:6]; // @[Monitor.scala:36:7]
wire _source_ok_T_72 = _source_ok_T_71 == 2'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_74 = _source_ok_T_72; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_76 = _source_ok_T_74; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_5 = _source_ok_T_76; // @[Parameters.scala:1138:31]
wire [5:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[5:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_78 = _source_ok_T_77 == 2'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_80 = _source_ok_T_78; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_6 = _source_ok_T_82; // @[Parameters.scala:1138:31]
wire _source_ok_T_83 = io_in_d_bits_source_0 == 8'hA0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_7 = _source_ok_T_83; // @[Parameters.scala:1138:31]
wire _source_ok_T_84 = io_in_d_bits_source_0 == 8'hA2; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_8 = _source_ok_T_84; // @[Parameters.scala:1138:31]
wire _source_ok_T_85 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_86 = _source_ok_T_85 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_87 = _source_ok_T_86 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_88 = _source_ok_T_87 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_89 = _source_ok_T_88 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_90 = _source_ok_T_89 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_91 = _source_ok_T_90 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_91 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire sink_ok = io_in_d_bits_sink_0[3:2] != 2'h3; // @[Monitor.scala:36:7, :309:31]
wire [27:0] _GEN_0 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T = {io_in_b_bits_address_0[31:28], _GEN_0}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46]
wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_5 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46]
wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40]
wire address_ok = _address_ok_WIRE_0 | _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64]
wire [31:0] _is_aligned_T_1 = {26'h0, io_in_b_bits_address_0[5:0]}; // @[Monitor.scala:36:7]
wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}]
wire mask_sub_sub_sub_bit_1 = io_in_b_bits_address_0[3]; // @[Misc.scala:210:26]
wire mask_sub_sub_sub_1_2_1 = mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_sub_nbit_1 = ~mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_sub_0_2_1 = mask_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2_1 = mask_sub_sub_sub_0_2_1 & mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T_4 = mask_sub_sub_0_2_1; // @[Misc.scala:214:27, :215:38]
wire mask_sub_sub_1_2_1 = mask_sub_sub_sub_0_2_1 & mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_sub_acc_T_5 = mask_sub_sub_1_2_1; // @[Misc.scala:214:27, :215:38]
wire mask_sub_sub_2_2_1 = mask_sub_sub_sub_1_2_1 & mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T_6 = mask_sub_sub_2_2_1; // @[Misc.scala:214:27, :215:38]
wire mask_sub_sub_3_2_1 = mask_sub_sub_sub_1_2_1 & mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_sub_acc_T_7 = mask_sub_sub_3_2_1; // @[Misc.scala:214:27, :215:38]
wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire mask_sub_4_2_1 = mask_sub_sub_2_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire mask_sub_5_2_1 = mask_sub_sub_2_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire mask_sub_6_2_1 = mask_sub_sub_3_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire mask_sub_7_2_1 = mask_sub_sub_3_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20]
wire mask_eq_16 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_16 = mask_eq_16; // @[Misc.scala:214:27, :215:38]
wire mask_eq_17 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_17 = mask_eq_17; // @[Misc.scala:214:27, :215:38]
wire mask_eq_18 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_18 = mask_eq_18; // @[Misc.scala:214:27, :215:38]
wire mask_eq_19 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_19 = mask_eq_19; // @[Misc.scala:214:27, :215:38]
wire mask_eq_20 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_20 = mask_eq_20; // @[Misc.scala:214:27, :215:38]
wire mask_eq_21 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_21 = mask_eq_21; // @[Misc.scala:214:27, :215:38]
wire mask_eq_22 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_22 = mask_eq_22; // @[Misc.scala:214:27, :215:38]
wire mask_eq_23 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_23 = mask_eq_23; // @[Misc.scala:214:27, :215:38]
wire mask_eq_24 = mask_sub_4_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_24 = mask_eq_24; // @[Misc.scala:214:27, :215:38]
wire mask_eq_25 = mask_sub_4_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_25 = mask_eq_25; // @[Misc.scala:214:27, :215:38]
wire mask_eq_26 = mask_sub_5_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_26 = mask_eq_26; // @[Misc.scala:214:27, :215:38]
wire mask_eq_27 = mask_sub_5_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_27 = mask_eq_27; // @[Misc.scala:214:27, :215:38]
wire mask_eq_28 = mask_sub_6_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_28 = mask_eq_28; // @[Misc.scala:214:27, :215:38]
wire mask_eq_29 = mask_sub_6_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_29 = mask_eq_29; // @[Misc.scala:214:27, :215:38]
wire mask_eq_30 = mask_sub_7_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_30 = mask_eq_30; // @[Misc.scala:214:27, :215:38]
wire mask_eq_31 = mask_sub_7_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_31 = mask_eq_31; // @[Misc.scala:214:27, :215:38]
wire _source_ok_T_92 = io_in_c_bits_source_0 == 8'h90; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_2_0 = _source_ok_T_92; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_12 = _source_ok_uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] _source_ok_T_93 = io_in_c_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_99 = io_in_c_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_105 = io_in_c_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_111 = io_in_c_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_94 = _source_ok_T_93 == 6'h20; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_96 = _source_ok_T_94; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_98 = _source_ok_T_96; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2_1 = _source_ok_T_98; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_13 = _source_ok_uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_100 = _source_ok_T_99 == 6'h21; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_102 = _source_ok_T_100; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_104 = _source_ok_T_102; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2_2 = _source_ok_T_104; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_14 = _source_ok_uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_106 = _source_ok_T_105 == 6'h22; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_108 = _source_ok_T_106; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_110 = _source_ok_T_108; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2_3 = _source_ok_T_110; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_15 = _source_ok_uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_112 = _source_ok_T_111 == 6'h23; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_114 = _source_ok_T_112; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_116 = _source_ok_T_114; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2_4 = _source_ok_T_116; // @[Parameters.scala:1138:31]
wire [5:0] source_ok_uncommonBits_16 = _source_ok_uncommonBits_T_16[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] _source_ok_T_117 = io_in_c_bits_source_0[7:6]; // @[Monitor.scala:36:7]
wire [1:0] _source_ok_T_123 = io_in_c_bits_source_0[7:6]; // @[Monitor.scala:36:7]
wire _source_ok_T_118 = _source_ok_T_117 == 2'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_120 = _source_ok_T_118; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_122 = _source_ok_T_120; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2_5 = _source_ok_T_122; // @[Parameters.scala:1138:31]
wire [5:0] source_ok_uncommonBits_17 = _source_ok_uncommonBits_T_17[5:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_124 = _source_ok_T_123 == 2'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_126 = _source_ok_T_124; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_128 = _source_ok_T_126; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2_6 = _source_ok_T_128; // @[Parameters.scala:1138:31]
wire _source_ok_T_129 = io_in_c_bits_source_0 == 8'hA0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_2_7 = _source_ok_T_129; // @[Parameters.scala:1138:31]
wire _source_ok_T_130 = io_in_c_bits_source_0 == 8'hA2; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_2_8 = _source_ok_T_130; // @[Parameters.scala:1138:31]
wire _source_ok_T_131 = _source_ok_WIRE_2_0 | _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_132 = _source_ok_T_131 | _source_ok_WIRE_2_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_133 = _source_ok_T_132 | _source_ok_WIRE_2_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_134 = _source_ok_T_133 | _source_ok_WIRE_2_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_135 = _source_ok_T_134 | _source_ok_WIRE_2_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_136 = _source_ok_T_135 | _source_ok_WIRE_2_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_137 = _source_ok_T_136 | _source_ok_WIRE_2_7; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_2 = _source_ok_T_137 | _source_ok_WIRE_2_8; // @[Parameters.scala:1138:31, :1139:46]
wire [12:0] _GEN_1 = 13'h3F << io_in_c_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T_4; // @[package.scala:243:71]
assign _is_aligned_mask_T_4 = _GEN_1; // @[package.scala:243:71]
wire [12:0] _c_first_beats1_decode_T; // @[package.scala:243:71]
assign _c_first_beats1_decode_T = _GEN_1; // @[package.scala:243:71]
wire [12:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _c_first_beats1_decode_T_3 = _GEN_1; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T_2 = {26'h0, io_in_c_bits_address_0[5:0] & is_aligned_mask_2}; // @[package.scala:243:46]
wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}]
wire [27:0] _GEN_2 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_10 = {io_in_c_bits_address_0[31:28], _GEN_2}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46]
wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_0 = _address_ok_T_14; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_15 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46]
wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_1 = _address_ok_T_19; // @[Parameters.scala:612:40]
wire address_ok_1 = _address_ok_WIRE_1_0 | _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64]
wire [1:0] uncommonBits_78 = _uncommonBits_T_78[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_79 = _uncommonBits_T_79[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_80 = _uncommonBits_T_80[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_81 = _uncommonBits_T_81[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_82 = _uncommonBits_T_82[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_83 = _uncommonBits_T_83[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_84 = _uncommonBits_T_84[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_85 = _uncommonBits_T_85[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_86 = _uncommonBits_T_86[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_87 = _uncommonBits_T_87[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_88 = _uncommonBits_T_88[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_89 = _uncommonBits_T_89[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_90 = _uncommonBits_T_90[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_91 = _uncommonBits_T_91[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_92 = _uncommonBits_T_92[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_93 = _uncommonBits_T_93[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_94 = _uncommonBits_T_94[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_95 = _uncommonBits_T_95[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_96 = _uncommonBits_T_96[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_97 = _uncommonBits_T_97[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_98 = _uncommonBits_T_98[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_99 = _uncommonBits_T_99[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_100 = _uncommonBits_T_100[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_101 = _uncommonBits_T_101[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_102 = _uncommonBits_T_102[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_103 = _uncommonBits_T_103[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_104 = _uncommonBits_T_104[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_105 = _uncommonBits_T_105[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_106 = _uncommonBits_T_106[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_107 = _uncommonBits_T_107[5:0]; // @[Parameters.scala:52:{29,56}]
wire sink_ok_1 = io_in_e_bits_sink_0[3:2] != 2'h3; // @[Monitor.scala:36:7, :367:31]
wire _T_2317 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_2317; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_2317; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [1:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:4]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [1:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 2'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [1:0] a_first_counter; // @[Edges.scala:229:27]
wire [2:0] _a_first_counter1_T = {1'h0, a_first_counter} - 3'h1; // @[Edges.scala:229:27, :230:28]
wire [1:0] a_first_counter1 = _a_first_counter1_T[1:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 2'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 2'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 2'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [1:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [1:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [1:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [7:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_2391 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_2391; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_2391; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_2391; // @[Decoupled.scala:51:35]
wire _d_first_T_3; // @[Decoupled.scala:51:35]
assign _d_first_T_3 = _T_2391; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_3 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_3; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_3; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_3; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_9 = _GEN_3; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [1:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:4]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [1:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 2'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [1:0] d_first_counter; // @[Edges.scala:229:27]
wire [2:0] _d_first_counter1_T = {1'h0, d_first_counter} - 3'h1; // @[Edges.scala:229:27, :230:28]
wire [1:0] d_first_counter1 = _d_first_counter1_T[1:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 2'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 2'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 2'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [1:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [1:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [1:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [7:0] source_1; // @[Monitor.scala:541:22]
reg [3:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35]
wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35]
reg [1:0] b_first_counter; // @[Edges.scala:229:27]
wire [2:0] _b_first_counter1_T = {1'h0, b_first_counter} - 3'h1; // @[Edges.scala:229:27, :230:28]
wire [1:0] b_first_counter1 = _b_first_counter1_T[1:0]; // @[Edges.scala:230:28]
wire b_first = b_first_counter == 2'h0; // @[Edges.scala:229:27, :231:25]
wire _b_first_last_T = b_first_counter == 2'h1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [1:0] _b_first_counter_T = b_first ? 2'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [1:0] param_2; // @[Monitor.scala:411:22]
reg [31:0] address_1; // @[Monitor.scala:414:22]
wire _T_2388 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35]
wire _c_first_T; // @[Decoupled.scala:51:35]
assign _c_first_T = _T_2388; // @[Decoupled.scala:51:35]
wire _c_first_T_1; // @[Decoupled.scala:51:35]
assign _c_first_T_1 = _T_2388; // @[Decoupled.scala:51:35]
wire [5:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [1:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[5:4]; // @[package.scala:243:46]
wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [1:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 2'h0; // @[Edges.scala:102:36, :220:59, :221:14]
reg [1:0] c_first_counter; // @[Edges.scala:229:27]
wire [2:0] _c_first_counter1_T = {1'h0, c_first_counter} - 3'h1; // @[Edges.scala:229:27, :230:28]
wire [1:0] c_first_counter1 = _c_first_counter1_T[1:0]; // @[Edges.scala:230:28]
wire c_first = c_first_counter == 2'h0; // @[Edges.scala:229:27, :231:25]
wire _c_first_last_T = c_first_counter == 2'h1; // @[Edges.scala:229:27, :232:25]
wire _c_first_last_T_1 = c_first_beats1 == 2'h0; // @[Edges.scala:221:14, :232:43]
wire c_first_last = _c_first_last_T | _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35]
wire [1:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [1:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [1:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_3; // @[Monitor.scala:515:22]
reg [2:0] param_3; // @[Monitor.scala:516:22]
reg [2:0] size_3; // @[Monitor.scala:517:22]
reg [7:0] source_3; // @[Monitor.scala:518:22]
reg [31:0] address_2; // @[Monitor.scala:519:22]
reg [162:0] inflight; // @[Monitor.scala:614:27]
reg [651:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [651:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [1:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:4]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [1:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 2'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [1:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [2:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 3'h1; // @[Edges.scala:229:27, :230:28]
wire [1:0] a_first_counter1_1 = _a_first_counter1_T_1[1:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 2'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 2'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 2'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [1:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [1:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [1:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [1:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:4]; // @[package.scala:243:46]
wire [1:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 2'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [1:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [2:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 3'h1; // @[Edges.scala:229:27, :230:28]
wire [1:0] d_first_counter1_1 = _d_first_counter1_T_1[1:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 2'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 2'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 2'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [1:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [1:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [1:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [162:0] a_set; // @[Monitor.scala:626:34]
wire [162:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [651:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [651:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [10:0] _GEN_4 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [10:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_4; // @[Monitor.scala:637:69]
wire [10:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_4; // @[Monitor.scala:637:69, :641:65]
wire [10:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_4; // @[Monitor.scala:637:69, :680:101]
wire [10:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_4; // @[Monitor.scala:637:69, :681:99]
wire [10:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_4; // @[Monitor.scala:637:69, :749:69]
wire [10:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_4; // @[Monitor.scala:637:69, :750:67]
wire [10:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_4; // @[Monitor.scala:637:69, :790:101]
wire [10:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_4; // @[Monitor.scala:637:69, :791:99]
wire [651:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [651:0] _a_opcode_lookup_T_6 = {648'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [651:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[651:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [651:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [651:0] _a_size_lookup_T_6 = {648'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [651:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[651:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [255:0] _GEN_5 = 256'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [255:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [255:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_5; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[162:0] : 163'h0; // @[OneHot.scala:58:35]
wire _T_2243 = _T_2317 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_2243 ? _a_set_T[162:0] : 163'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_2243 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_2243 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [10:0] _GEN_6 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [10:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_6; // @[Monitor.scala:659:79]
wire [10:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_6; // @[Monitor.scala:659:79, :660:77]
wire [2050:0] _a_opcodes_set_T_1 = {2047'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_2243 ? _a_opcodes_set_T_1[651:0] : 652'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [2050:0] _a_sizes_set_T_1 = {2047'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_2243 ? _a_sizes_set_T_1[651:0] : 652'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [162:0] d_clr; // @[Monitor.scala:664:34]
wire [162:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [651:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [651:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_7 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_7; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_7; // @[Monitor.scala:673:46, :783:46]
wire _T_2289 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [255:0] _GEN_8 = 256'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_8; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_8; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_8; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_8; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_2289 & ~d_release_ack ? _d_clr_wo_ready_T[162:0] : 163'h0; // @[OneHot.scala:58:35]
wire _T_2258 = _T_2391 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_2258 ? _d_clr_T[162:0] : 163'h0; // @[OneHot.scala:58:35]
wire [2062:0] _d_opcodes_clr_T_5 = 2063'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_2258 ? _d_opcodes_clr_T_5[651:0] : 652'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [2062:0] _d_sizes_clr_T_5 = 2063'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_2258 ? _d_sizes_clr_T_5[651:0] : 652'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [162:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [162:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [162:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [651:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [651:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [651:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [651:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [651:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [651:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [162:0] inflight_1; // @[Monitor.scala:726:35]
reg [651:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
reg [651:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [5:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [1:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[5:4]; // @[package.scala:243:46]
wire [1:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 2'h0; // @[Edges.scala:102:36, :220:59, :221:14]
reg [1:0] c_first_counter_1; // @[Edges.scala:229:27]
wire [2:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 3'h1; // @[Edges.scala:229:27, :230:28]
wire [1:0] c_first_counter1_1 = _c_first_counter1_T_1[1:0]; // @[Edges.scala:230:28]
wire c_first_1 = c_first_counter_1 == 2'h0; // @[Edges.scala:229:27, :231:25]
wire _c_first_last_T_2 = c_first_counter_1 == 2'h1; // @[Edges.scala:229:27, :232:25]
wire _c_first_last_T_3 = c_first_beats1_1 == 2'h0; // @[Edges.scala:221:14, :232:43]
wire c_first_last_1 = _c_first_last_T_2 | _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35]
wire [1:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [1:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [1:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [1:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:4]; // @[package.scala:243:46]
wire [1:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 2'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [1:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [2:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 3'h1; // @[Edges.scala:229:27, :230:28]
wire [1:0] d_first_counter1_2 = _d_first_counter1_T_2[1:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 2'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 2'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 2'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [1:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [1:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [1:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [162:0] c_set; // @[Monitor.scala:738:34]
wire [162:0] c_set_wo_ready; // @[Monitor.scala:739:34]
wire [651:0] c_opcodes_set; // @[Monitor.scala:740:34]
wire [651:0] c_sizes_set; // @[Monitor.scala:741:34]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [651:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [651:0] _c_opcode_lookup_T_6 = {648'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [651:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[651:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [651:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [651:0] _c_size_lookup_T_6 = {648'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [651:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[651:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm; // @[Monitor.scala:755:40]
wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44]
wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7]
wire [255:0] _GEN_9 = 256'h1 << io_in_c_bits_source_0; // @[OneHot.scala:58:35]
wire [255:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _c_set_wo_ready_T = _GEN_9; // @[OneHot.scala:58:35]
wire [255:0] _c_set_T; // @[OneHot.scala:58:35]
assign _c_set_T = _GEN_9; // @[OneHot.scala:58:35]
assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T[162:0] : 163'h0; // @[OneHot.scala:58:35]
wire _T_2330 = _T_2388 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35]
assign c_set = _T_2330 ? _c_set_T[162:0] : 163'h0; // @[OneHot.scala:58:35]
wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53]
wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}]
assign c_opcodes_set_interm = _T_2330 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}]
wire [3:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51]
wire [3:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:766:{51,59}]
assign c_sizes_set_interm = _T_2330 ? _c_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}]
wire [10:0] _GEN_10 = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79]
wire [10:0] _c_opcodes_set_T; // @[Monitor.scala:767:79]
assign _c_opcodes_set_T = _GEN_10; // @[Monitor.scala:767:79]
wire [10:0] _c_sizes_set_T; // @[Monitor.scala:768:77]
assign _c_sizes_set_T = _GEN_10; // @[Monitor.scala:767:79, :768:77]
wire [2050:0] _c_opcodes_set_T_1 = {2047'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}]
assign c_opcodes_set = _T_2330 ? _c_opcodes_set_T_1[651:0] : 652'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}]
wire [2050:0] _c_sizes_set_T_1 = {2047'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}]
assign c_sizes_set = _T_2330 ? _c_sizes_set_T_1[651:0] : 652'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}]
wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47]
wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95]
wire c_probe_ack = _c_probe_ack_T | _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}]
wire [162:0] d_clr_1; // @[Monitor.scala:774:34]
wire [162:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [651:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [651:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_2361 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_2361 & d_release_ack_1 ? _d_clr_wo_ready_T_1[162:0] : 163'h0; // @[OneHot.scala:58:35]
wire _T_2343 = _T_2391 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_2343 ? _d_clr_T_1[162:0] : 163'h0; // @[OneHot.scala:58:35]
wire [2062:0] _d_opcodes_clr_T_11 = 2063'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_2343 ? _d_opcodes_clr_T_11[651:0] : 652'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [2062:0] _d_sizes_clr_T_11 = 2063'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_2343 ? _d_sizes_clr_T_11[651:0] : 652'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}]
wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}]
wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113]
wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}]
wire [162:0] _inflight_T_3 = inflight_1 | c_set; // @[Monitor.scala:726:35, :738:34, :814:35]
wire [162:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [162:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [651:0] _inflight_opcodes_T_3 = inflight_opcodes_1 | c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43]
wire [651:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [651:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [651:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41]
wire [651:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [651:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26]
wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26]
reg [11:0] inflight_2; // @[Monitor.scala:828:27]
wire [5:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}]
wire [1:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[5:4]; // @[package.scala:243:46]
wire [1:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 2'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [1:0] d_first_counter_3; // @[Edges.scala:229:27]
wire [2:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 3'h1; // @[Edges.scala:229:27, :230:28]
wire [1:0] d_first_counter1_3 = _d_first_counter1_T_3[1:0]; // @[Edges.scala:230:28]
wire d_first_3 = d_first_counter_3 == 2'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_6 = d_first_counter_3 == 2'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_7 = d_first_beats1_3 == 2'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_3 = _d_first_last_T_6 | _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35]
wire [1:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27]
wire [1:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}]
wire [1:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] d_set; // @[Monitor.scala:833:25]
wire _T_2397 = _T_2391 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35]
wire [15:0] _d_set_T = 16'h1 << io_in_d_bits_sink_0; // @[OneHot.scala:58:35]
assign d_set = _T_2397 ? _d_set_T[11:0] : 12'h0; // @[OneHot.scala:58:35]
wire [11:0] e_clr; // @[Monitor.scala:839:25]
wire [15:0] _e_clr_T = 16'h1 << io_in_e_bits_sink_0; // @[OneHot.scala:58:35]
assign e_clr = io_in_e_valid_0 ? _e_clr_T[11:0] : 12'h0; // @[OneHot.scala:58:35] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_477 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_477( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module ZstdCompressor :
input clock : Clock
input reset : Reset
output auto : { tl_out_17 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, tl_out_16 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, tl_out_15 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, tl_out_14 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, tl_out_13 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, tl_out_12 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, tl_out_11 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, tl_out_10 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, tl_out_9 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, tl_out_8 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, tl_out_7 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, tl_out_6 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, tl_out_5 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, tl_out_4 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, tl_out_3 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, tl_out_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, tl_out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, tl_out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
output io : { flip cmd : { flip ready : UInt<1>, valid : UInt<1>, bits : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}}, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { rd : UInt<5>, data : UInt<64>}}, mem : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}}, s1_kill : UInt<1>, s1_data : { data : UInt<64>, mask : UInt<8>}, flip s2_nack : UInt<1>, flip s2_nack_cause_raw : UInt<1>, s2_kill : UInt<1>, flip s2_uncached : UInt<1>, flip s2_paddr : UInt<32>, flip resp : { valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, data : UInt<64>, mask : UInt<8>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, data_raw : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip s2_xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>}}, flip s2_gpa : UInt<40>, flip s2_gpa_is_pte : UInt<1>, flip ordered : UInt<1>, flip store_pending : UInt<1>, flip perf : { acquire : UInt<1>, release : UInt<1>, grant : UInt<1>, tlbMiss : UInt<1>, blocked : UInt<1>, canAcceptStoreThenLoad : UInt<1>, canAcceptStoreThenRMW : UInt<1>, canAcceptLoadThenLoad : UInt<1>, storeBufferEmptyAfterLoad : UInt<1>, storeBufferEmptyAfterStore : UInt<1>}, keep_clock_enabled : UInt<1>, flip clock_enabled : UInt<1>}, busy : UInt<1>, interrupt : UInt<1>, flip exception : UInt<1>, flip csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[0], ptw : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { addr : UInt<27>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}}}, flip resp : { valid : UInt<1>, bits : { ae_ptw : UInt<1>, ae_final : UInt<1>, pf : UInt<1>, gf : UInt<1>, hr : UInt<1>, hw : UInt<1>, hx : UInt<1>, pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>, fragmented_superpage : UInt<1>, homogeneous : UInt<1>, gpa : { valid : UInt<1>, bits : UInt<39>}, gpa_is_pte : UInt<1>}}, flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[4]}}[18], fpu_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, flip fpu_resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<65>, exc : UInt<5>}}}
inst l2_fhdr_writer of L2MemHelperLatencyInjection
connect l2_fhdr_writer.clock, clock
connect l2_fhdr_writer.reset, reset
inst widget of TLWidthWidget32
connect widget.clock, clock
connect widget.reset, reset
inst l2_bhdr_writer of L2MemHelperLatencyInjection_1
connect l2_bhdr_writer.clock, clock
connect l2_bhdr_writer.reset, reset
inst widget_1 of TLWidthWidget32_1
connect widget_1.clock, clock
connect widget_1.reset, reset
inst l2_mf_reader of L2MemHelperLatencyInjection_2
connect l2_mf_reader.clock, clock
connect l2_mf_reader.reset, reset
inst widget_2 of TLWidthWidget32_2
connect widget_2.clock, clock
connect widget_2.reset, reset
inst l2_mf_seqwriter of L2MemHelperLatencyInjection_3
connect l2_mf_seqwriter.clock, clock
connect l2_mf_seqwriter.reset, reset
inst widget_3 of TLWidthWidget32_3
connect widget_3.clock, clock
connect widget_3.reset, reset
inst l2_mf_litwriter of L2MemHelperLatencyInjection_4
connect l2_mf_litwriter.clock, clock
connect l2_mf_litwriter.reset, reset
inst widget_4 of TLWidthWidget32_4
connect widget_4.clock, clock
connect widget_4.reset, reset
inst l2_huf_lit_reader of L2MemHelperLatencyInjection_5
connect l2_huf_lit_reader.clock, clock
connect l2_huf_lit_reader.reset, reset
inst widget_5 of TLWidthWidget32_5
connect widget_5.clock, clock
connect widget_5.reset, reset
inst l2_huf_dic_reader of L2MemHelperLatencyInjection_6
connect l2_huf_dic_reader.clock, clock
connect l2_huf_dic_reader.reset, reset
inst widget_6 of TLWidthWidget32_6
connect widget_6.clock, clock
connect widget_6.reset, reset
inst l2_huf_dic_writer of L2MemHelperLatencyInjection_7
connect l2_huf_dic_writer.clock, clock
connect l2_huf_dic_writer.reset, reset
inst widget_7 of TLWidthWidget32_7
connect widget_7.clock, clock
connect widget_7.reset, reset
inst l2_huf_hdr_writer of L2MemHelperLatencyInjection_8
connect l2_huf_hdr_writer.clock, clock
connect l2_huf_hdr_writer.reset, reset
inst widget_8 of TLWidthWidget32_8
connect widget_8.clock, clock
connect widget_8.reset, reset
inst l2_huf_jt_writer of L2MemHelperLatencyInjection_9
connect l2_huf_jt_writer.clock, clock
connect l2_huf_jt_writer.reset, reset
inst widget_9 of TLWidthWidget32_9
connect widget_9.clock, clock
connect widget_9.reset, reset
inst l2_huf_lit_writer of L2MemHelperLatencyInjection_10
connect l2_huf_lit_writer.clock, clock
connect l2_huf_lit_writer.reset, reset
inst widget_10 of TLWidthWidget32_10
connect widget_10.clock, clock
connect widget_10.reset, reset
inst l2_seq_reader of L2MemHelperLatencyInjection_11
connect l2_seq_reader.clock, clock
connect l2_seq_reader.reset, reset
inst widget_11 of TLWidthWidget32_11
connect widget_11.clock, clock
connect widget_11.reset, reset
inst l2_seq_reader2 of L2MemHelperLatencyInjection_12
connect l2_seq_reader2.clock, clock
connect l2_seq_reader2.reset, reset
inst widget_12 of TLWidthWidget32_12
connect widget_12.clock, clock
connect widget_12.reset, reset
inst l2_seq_writer of L2MemHelperLatencyInjection_13
connect l2_seq_writer.clock, clock
connect l2_seq_writer.reset, reset
inst widget_13 of TLWidthWidget32_13
connect widget_13.clock, clock
connect widget_13.reset, reset
inst l2_raw_block_reader of L2MemHelperLatencyInjection_14
connect l2_raw_block_reader.clock, clock
connect l2_raw_block_reader.reset, reset
inst widget_14 of TLWidthWidget32_14
connect widget_14.clock, clock
connect widget_14.reset, reset
inst l2_raw_block_writer of L2MemHelperLatencyInjection_15
connect l2_raw_block_writer.clock, clock
connect l2_raw_block_writer.reset, reset
inst widget_15 of TLWidthWidget32_15
connect widget_15.clock, clock
connect widget_15.reset, reset
inst l2_raw_lit_reader of L2MemHelperLatencyInjection_16
connect l2_raw_lit_reader.clock, clock
connect l2_raw_lit_reader.reset, reset
inst widget_16 of TLWidthWidget32_16
connect widget_16.clock, clock
connect widget_16.reset, reset
inst l2_raw_lit_writer of L2MemHelperLatencyInjection_17
connect l2_raw_lit_writer.clock, clock
connect l2_raw_lit_writer.reset, reset
inst widget_17 of TLWidthWidget32_17
connect widget_17.clock, clock
connect widget_17.reset, reset
wire tlNodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate tlNodeOut.d.bits.corrupt
invalidate tlNodeOut.d.bits.data
invalidate tlNodeOut.d.bits.denied
invalidate tlNodeOut.d.bits.sink
invalidate tlNodeOut.d.bits.source
invalidate tlNodeOut.d.bits.size
invalidate tlNodeOut.d.bits.param
invalidate tlNodeOut.d.bits.opcode
invalidate tlNodeOut.d.valid
invalidate tlNodeOut.d.ready
invalidate tlNodeOut.a.bits.corrupt
invalidate tlNodeOut.a.bits.data
invalidate tlNodeOut.a.bits.mask
invalidate tlNodeOut.a.bits.address
invalidate tlNodeOut.a.bits.source
invalidate tlNodeOut.a.bits.size
invalidate tlNodeOut.a.bits.param
invalidate tlNodeOut.a.bits.opcode
invalidate tlNodeOut.a.valid
invalidate tlNodeOut.a.ready
wire x1_tlNodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate x1_tlNodeOut.d.bits.corrupt
invalidate x1_tlNodeOut.d.bits.data
invalidate x1_tlNodeOut.d.bits.denied
invalidate x1_tlNodeOut.d.bits.sink
invalidate x1_tlNodeOut.d.bits.source
invalidate x1_tlNodeOut.d.bits.size
invalidate x1_tlNodeOut.d.bits.param
invalidate x1_tlNodeOut.d.bits.opcode
invalidate x1_tlNodeOut.d.valid
invalidate x1_tlNodeOut.d.ready
invalidate x1_tlNodeOut.a.bits.corrupt
invalidate x1_tlNodeOut.a.bits.data
invalidate x1_tlNodeOut.a.bits.mask
invalidate x1_tlNodeOut.a.bits.address
invalidate x1_tlNodeOut.a.bits.source
invalidate x1_tlNodeOut.a.bits.size
invalidate x1_tlNodeOut.a.bits.param
invalidate x1_tlNodeOut.a.bits.opcode
invalidate x1_tlNodeOut.a.valid
invalidate x1_tlNodeOut.a.ready
wire x1_tlNodeOut_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate x1_tlNodeOut_1.d.bits.corrupt
invalidate x1_tlNodeOut_1.d.bits.data
invalidate x1_tlNodeOut_1.d.bits.denied
invalidate x1_tlNodeOut_1.d.bits.sink
invalidate x1_tlNodeOut_1.d.bits.source
invalidate x1_tlNodeOut_1.d.bits.size
invalidate x1_tlNodeOut_1.d.bits.param
invalidate x1_tlNodeOut_1.d.bits.opcode
invalidate x1_tlNodeOut_1.d.valid
invalidate x1_tlNodeOut_1.d.ready
invalidate x1_tlNodeOut_1.a.bits.corrupt
invalidate x1_tlNodeOut_1.a.bits.data
invalidate x1_tlNodeOut_1.a.bits.mask
invalidate x1_tlNodeOut_1.a.bits.address
invalidate x1_tlNodeOut_1.a.bits.source
invalidate x1_tlNodeOut_1.a.bits.size
invalidate x1_tlNodeOut_1.a.bits.param
invalidate x1_tlNodeOut_1.a.bits.opcode
invalidate x1_tlNodeOut_1.a.valid
invalidate x1_tlNodeOut_1.a.ready
wire x1_tlNodeOut_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate x1_tlNodeOut_2.d.bits.corrupt
invalidate x1_tlNodeOut_2.d.bits.data
invalidate x1_tlNodeOut_2.d.bits.denied
invalidate x1_tlNodeOut_2.d.bits.sink
invalidate x1_tlNodeOut_2.d.bits.source
invalidate x1_tlNodeOut_2.d.bits.size
invalidate x1_tlNodeOut_2.d.bits.param
invalidate x1_tlNodeOut_2.d.bits.opcode
invalidate x1_tlNodeOut_2.d.valid
invalidate x1_tlNodeOut_2.d.ready
invalidate x1_tlNodeOut_2.a.bits.corrupt
invalidate x1_tlNodeOut_2.a.bits.data
invalidate x1_tlNodeOut_2.a.bits.mask
invalidate x1_tlNodeOut_2.a.bits.address
invalidate x1_tlNodeOut_2.a.bits.source
invalidate x1_tlNodeOut_2.a.bits.size
invalidate x1_tlNodeOut_2.a.bits.param
invalidate x1_tlNodeOut_2.a.bits.opcode
invalidate x1_tlNodeOut_2.a.valid
invalidate x1_tlNodeOut_2.a.ready
wire x1_tlNodeOut_3 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate x1_tlNodeOut_3.d.bits.corrupt
invalidate x1_tlNodeOut_3.d.bits.data
invalidate x1_tlNodeOut_3.d.bits.denied
invalidate x1_tlNodeOut_3.d.bits.sink
invalidate x1_tlNodeOut_3.d.bits.source
invalidate x1_tlNodeOut_3.d.bits.size
invalidate x1_tlNodeOut_3.d.bits.param
invalidate x1_tlNodeOut_3.d.bits.opcode
invalidate x1_tlNodeOut_3.d.valid
invalidate x1_tlNodeOut_3.d.ready
invalidate x1_tlNodeOut_3.a.bits.corrupt
invalidate x1_tlNodeOut_3.a.bits.data
invalidate x1_tlNodeOut_3.a.bits.mask
invalidate x1_tlNodeOut_3.a.bits.address
invalidate x1_tlNodeOut_3.a.bits.source
invalidate x1_tlNodeOut_3.a.bits.size
invalidate x1_tlNodeOut_3.a.bits.param
invalidate x1_tlNodeOut_3.a.bits.opcode
invalidate x1_tlNodeOut_3.a.valid
invalidate x1_tlNodeOut_3.a.ready
wire x1_tlNodeOut_4 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate x1_tlNodeOut_4.d.bits.corrupt
invalidate x1_tlNodeOut_4.d.bits.data
invalidate x1_tlNodeOut_4.d.bits.denied
invalidate x1_tlNodeOut_4.d.bits.sink
invalidate x1_tlNodeOut_4.d.bits.source
invalidate x1_tlNodeOut_4.d.bits.size
invalidate x1_tlNodeOut_4.d.bits.param
invalidate x1_tlNodeOut_4.d.bits.opcode
invalidate x1_tlNodeOut_4.d.valid
invalidate x1_tlNodeOut_4.d.ready
invalidate x1_tlNodeOut_4.a.bits.corrupt
invalidate x1_tlNodeOut_4.a.bits.data
invalidate x1_tlNodeOut_4.a.bits.mask
invalidate x1_tlNodeOut_4.a.bits.address
invalidate x1_tlNodeOut_4.a.bits.source
invalidate x1_tlNodeOut_4.a.bits.size
invalidate x1_tlNodeOut_4.a.bits.param
invalidate x1_tlNodeOut_4.a.bits.opcode
invalidate x1_tlNodeOut_4.a.valid
invalidate x1_tlNodeOut_4.a.ready
wire x1_tlNodeOut_5 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate x1_tlNodeOut_5.d.bits.corrupt
invalidate x1_tlNodeOut_5.d.bits.data
invalidate x1_tlNodeOut_5.d.bits.denied
invalidate x1_tlNodeOut_5.d.bits.sink
invalidate x1_tlNodeOut_5.d.bits.source
invalidate x1_tlNodeOut_5.d.bits.size
invalidate x1_tlNodeOut_5.d.bits.param
invalidate x1_tlNodeOut_5.d.bits.opcode
invalidate x1_tlNodeOut_5.d.valid
invalidate x1_tlNodeOut_5.d.ready
invalidate x1_tlNodeOut_5.a.bits.corrupt
invalidate x1_tlNodeOut_5.a.bits.data
invalidate x1_tlNodeOut_5.a.bits.mask
invalidate x1_tlNodeOut_5.a.bits.address
invalidate x1_tlNodeOut_5.a.bits.source
invalidate x1_tlNodeOut_5.a.bits.size
invalidate x1_tlNodeOut_5.a.bits.param
invalidate x1_tlNodeOut_5.a.bits.opcode
invalidate x1_tlNodeOut_5.a.valid
invalidate x1_tlNodeOut_5.a.ready
wire x1_tlNodeOut_6 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate x1_tlNodeOut_6.d.bits.corrupt
invalidate x1_tlNodeOut_6.d.bits.data
invalidate x1_tlNodeOut_6.d.bits.denied
invalidate x1_tlNodeOut_6.d.bits.sink
invalidate x1_tlNodeOut_6.d.bits.source
invalidate x1_tlNodeOut_6.d.bits.size
invalidate x1_tlNodeOut_6.d.bits.param
invalidate x1_tlNodeOut_6.d.bits.opcode
invalidate x1_tlNodeOut_6.d.valid
invalidate x1_tlNodeOut_6.d.ready
invalidate x1_tlNodeOut_6.a.bits.corrupt
invalidate x1_tlNodeOut_6.a.bits.data
invalidate x1_tlNodeOut_6.a.bits.mask
invalidate x1_tlNodeOut_6.a.bits.address
invalidate x1_tlNodeOut_6.a.bits.source
invalidate x1_tlNodeOut_6.a.bits.size
invalidate x1_tlNodeOut_6.a.bits.param
invalidate x1_tlNodeOut_6.a.bits.opcode
invalidate x1_tlNodeOut_6.a.valid
invalidate x1_tlNodeOut_6.a.ready
wire x1_tlNodeOut_7 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate x1_tlNodeOut_7.d.bits.corrupt
invalidate x1_tlNodeOut_7.d.bits.data
invalidate x1_tlNodeOut_7.d.bits.denied
invalidate x1_tlNodeOut_7.d.bits.sink
invalidate x1_tlNodeOut_7.d.bits.source
invalidate x1_tlNodeOut_7.d.bits.size
invalidate x1_tlNodeOut_7.d.bits.param
invalidate x1_tlNodeOut_7.d.bits.opcode
invalidate x1_tlNodeOut_7.d.valid
invalidate x1_tlNodeOut_7.d.ready
invalidate x1_tlNodeOut_7.a.bits.corrupt
invalidate x1_tlNodeOut_7.a.bits.data
invalidate x1_tlNodeOut_7.a.bits.mask
invalidate x1_tlNodeOut_7.a.bits.address
invalidate x1_tlNodeOut_7.a.bits.source
invalidate x1_tlNodeOut_7.a.bits.size
invalidate x1_tlNodeOut_7.a.bits.param
invalidate x1_tlNodeOut_7.a.bits.opcode
invalidate x1_tlNodeOut_7.a.valid
invalidate x1_tlNodeOut_7.a.ready
wire x1_tlNodeOut_8 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate x1_tlNodeOut_8.d.bits.corrupt
invalidate x1_tlNodeOut_8.d.bits.data
invalidate x1_tlNodeOut_8.d.bits.denied
invalidate x1_tlNodeOut_8.d.bits.sink
invalidate x1_tlNodeOut_8.d.bits.source
invalidate x1_tlNodeOut_8.d.bits.size
invalidate x1_tlNodeOut_8.d.bits.param
invalidate x1_tlNodeOut_8.d.bits.opcode
invalidate x1_tlNodeOut_8.d.valid
invalidate x1_tlNodeOut_8.d.ready
invalidate x1_tlNodeOut_8.a.bits.corrupt
invalidate x1_tlNodeOut_8.a.bits.data
invalidate x1_tlNodeOut_8.a.bits.mask
invalidate x1_tlNodeOut_8.a.bits.address
invalidate x1_tlNodeOut_8.a.bits.source
invalidate x1_tlNodeOut_8.a.bits.size
invalidate x1_tlNodeOut_8.a.bits.param
invalidate x1_tlNodeOut_8.a.bits.opcode
invalidate x1_tlNodeOut_8.a.valid
invalidate x1_tlNodeOut_8.a.ready
wire x1_tlNodeOut_9 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate x1_tlNodeOut_9.d.bits.corrupt
invalidate x1_tlNodeOut_9.d.bits.data
invalidate x1_tlNodeOut_9.d.bits.denied
invalidate x1_tlNodeOut_9.d.bits.sink
invalidate x1_tlNodeOut_9.d.bits.source
invalidate x1_tlNodeOut_9.d.bits.size
invalidate x1_tlNodeOut_9.d.bits.param
invalidate x1_tlNodeOut_9.d.bits.opcode
invalidate x1_tlNodeOut_9.d.valid
invalidate x1_tlNodeOut_9.d.ready
invalidate x1_tlNodeOut_9.a.bits.corrupt
invalidate x1_tlNodeOut_9.a.bits.data
invalidate x1_tlNodeOut_9.a.bits.mask
invalidate x1_tlNodeOut_9.a.bits.address
invalidate x1_tlNodeOut_9.a.bits.source
invalidate x1_tlNodeOut_9.a.bits.size
invalidate x1_tlNodeOut_9.a.bits.param
invalidate x1_tlNodeOut_9.a.bits.opcode
invalidate x1_tlNodeOut_9.a.valid
invalidate x1_tlNodeOut_9.a.ready
wire x1_tlNodeOut_10 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate x1_tlNodeOut_10.d.bits.corrupt
invalidate x1_tlNodeOut_10.d.bits.data
invalidate x1_tlNodeOut_10.d.bits.denied
invalidate x1_tlNodeOut_10.d.bits.sink
invalidate x1_tlNodeOut_10.d.bits.source
invalidate x1_tlNodeOut_10.d.bits.size
invalidate x1_tlNodeOut_10.d.bits.param
invalidate x1_tlNodeOut_10.d.bits.opcode
invalidate x1_tlNodeOut_10.d.valid
invalidate x1_tlNodeOut_10.d.ready
invalidate x1_tlNodeOut_10.a.bits.corrupt
invalidate x1_tlNodeOut_10.a.bits.data
invalidate x1_tlNodeOut_10.a.bits.mask
invalidate x1_tlNodeOut_10.a.bits.address
invalidate x1_tlNodeOut_10.a.bits.source
invalidate x1_tlNodeOut_10.a.bits.size
invalidate x1_tlNodeOut_10.a.bits.param
invalidate x1_tlNodeOut_10.a.bits.opcode
invalidate x1_tlNodeOut_10.a.valid
invalidate x1_tlNodeOut_10.a.ready
wire x1_tlNodeOut_11 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate x1_tlNodeOut_11.d.bits.corrupt
invalidate x1_tlNodeOut_11.d.bits.data
invalidate x1_tlNodeOut_11.d.bits.denied
invalidate x1_tlNodeOut_11.d.bits.sink
invalidate x1_tlNodeOut_11.d.bits.source
invalidate x1_tlNodeOut_11.d.bits.size
invalidate x1_tlNodeOut_11.d.bits.param
invalidate x1_tlNodeOut_11.d.bits.opcode
invalidate x1_tlNodeOut_11.d.valid
invalidate x1_tlNodeOut_11.d.ready
invalidate x1_tlNodeOut_11.a.bits.corrupt
invalidate x1_tlNodeOut_11.a.bits.data
invalidate x1_tlNodeOut_11.a.bits.mask
invalidate x1_tlNodeOut_11.a.bits.address
invalidate x1_tlNodeOut_11.a.bits.source
invalidate x1_tlNodeOut_11.a.bits.size
invalidate x1_tlNodeOut_11.a.bits.param
invalidate x1_tlNodeOut_11.a.bits.opcode
invalidate x1_tlNodeOut_11.a.valid
invalidate x1_tlNodeOut_11.a.ready
wire x1_tlNodeOut_12 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate x1_tlNodeOut_12.d.bits.corrupt
invalidate x1_tlNodeOut_12.d.bits.data
invalidate x1_tlNodeOut_12.d.bits.denied
invalidate x1_tlNodeOut_12.d.bits.sink
invalidate x1_tlNodeOut_12.d.bits.source
invalidate x1_tlNodeOut_12.d.bits.size
invalidate x1_tlNodeOut_12.d.bits.param
invalidate x1_tlNodeOut_12.d.bits.opcode
invalidate x1_tlNodeOut_12.d.valid
invalidate x1_tlNodeOut_12.d.ready
invalidate x1_tlNodeOut_12.a.bits.corrupt
invalidate x1_tlNodeOut_12.a.bits.data
invalidate x1_tlNodeOut_12.a.bits.mask
invalidate x1_tlNodeOut_12.a.bits.address
invalidate x1_tlNodeOut_12.a.bits.source
invalidate x1_tlNodeOut_12.a.bits.size
invalidate x1_tlNodeOut_12.a.bits.param
invalidate x1_tlNodeOut_12.a.bits.opcode
invalidate x1_tlNodeOut_12.a.valid
invalidate x1_tlNodeOut_12.a.ready
wire x1_tlNodeOut_13 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate x1_tlNodeOut_13.d.bits.corrupt
invalidate x1_tlNodeOut_13.d.bits.data
invalidate x1_tlNodeOut_13.d.bits.denied
invalidate x1_tlNodeOut_13.d.bits.sink
invalidate x1_tlNodeOut_13.d.bits.source
invalidate x1_tlNodeOut_13.d.bits.size
invalidate x1_tlNodeOut_13.d.bits.param
invalidate x1_tlNodeOut_13.d.bits.opcode
invalidate x1_tlNodeOut_13.d.valid
invalidate x1_tlNodeOut_13.d.ready
invalidate x1_tlNodeOut_13.a.bits.corrupt
invalidate x1_tlNodeOut_13.a.bits.data
invalidate x1_tlNodeOut_13.a.bits.mask
invalidate x1_tlNodeOut_13.a.bits.address
invalidate x1_tlNodeOut_13.a.bits.source
invalidate x1_tlNodeOut_13.a.bits.size
invalidate x1_tlNodeOut_13.a.bits.param
invalidate x1_tlNodeOut_13.a.bits.opcode
invalidate x1_tlNodeOut_13.a.valid
invalidate x1_tlNodeOut_13.a.ready
wire x1_tlNodeOut_14 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate x1_tlNodeOut_14.d.bits.corrupt
invalidate x1_tlNodeOut_14.d.bits.data
invalidate x1_tlNodeOut_14.d.bits.denied
invalidate x1_tlNodeOut_14.d.bits.sink
invalidate x1_tlNodeOut_14.d.bits.source
invalidate x1_tlNodeOut_14.d.bits.size
invalidate x1_tlNodeOut_14.d.bits.param
invalidate x1_tlNodeOut_14.d.bits.opcode
invalidate x1_tlNodeOut_14.d.valid
invalidate x1_tlNodeOut_14.d.ready
invalidate x1_tlNodeOut_14.a.bits.corrupt
invalidate x1_tlNodeOut_14.a.bits.data
invalidate x1_tlNodeOut_14.a.bits.mask
invalidate x1_tlNodeOut_14.a.bits.address
invalidate x1_tlNodeOut_14.a.bits.source
invalidate x1_tlNodeOut_14.a.bits.size
invalidate x1_tlNodeOut_14.a.bits.param
invalidate x1_tlNodeOut_14.a.bits.opcode
invalidate x1_tlNodeOut_14.a.valid
invalidate x1_tlNodeOut_14.a.ready
wire x1_tlNodeOut_15 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate x1_tlNodeOut_15.d.bits.corrupt
invalidate x1_tlNodeOut_15.d.bits.data
invalidate x1_tlNodeOut_15.d.bits.denied
invalidate x1_tlNodeOut_15.d.bits.sink
invalidate x1_tlNodeOut_15.d.bits.source
invalidate x1_tlNodeOut_15.d.bits.size
invalidate x1_tlNodeOut_15.d.bits.param
invalidate x1_tlNodeOut_15.d.bits.opcode
invalidate x1_tlNodeOut_15.d.valid
invalidate x1_tlNodeOut_15.d.ready
invalidate x1_tlNodeOut_15.a.bits.corrupt
invalidate x1_tlNodeOut_15.a.bits.data
invalidate x1_tlNodeOut_15.a.bits.mask
invalidate x1_tlNodeOut_15.a.bits.address
invalidate x1_tlNodeOut_15.a.bits.source
invalidate x1_tlNodeOut_15.a.bits.size
invalidate x1_tlNodeOut_15.a.bits.param
invalidate x1_tlNodeOut_15.a.bits.opcode
invalidate x1_tlNodeOut_15.a.valid
invalidate x1_tlNodeOut_15.a.ready
wire x1_tlNodeOut_16 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate x1_tlNodeOut_16.d.bits.corrupt
invalidate x1_tlNodeOut_16.d.bits.data
invalidate x1_tlNodeOut_16.d.bits.denied
invalidate x1_tlNodeOut_16.d.bits.sink
invalidate x1_tlNodeOut_16.d.bits.source
invalidate x1_tlNodeOut_16.d.bits.size
invalidate x1_tlNodeOut_16.d.bits.param
invalidate x1_tlNodeOut_16.d.bits.opcode
invalidate x1_tlNodeOut_16.d.valid
invalidate x1_tlNodeOut_16.d.ready
invalidate x1_tlNodeOut_16.a.bits.corrupt
invalidate x1_tlNodeOut_16.a.bits.data
invalidate x1_tlNodeOut_16.a.bits.mask
invalidate x1_tlNodeOut_16.a.bits.address
invalidate x1_tlNodeOut_16.a.bits.source
invalidate x1_tlNodeOut_16.a.bits.size
invalidate x1_tlNodeOut_16.a.bits.param
invalidate x1_tlNodeOut_16.a.bits.opcode
invalidate x1_tlNodeOut_16.a.valid
invalidate x1_tlNodeOut_16.a.ready
wire tlNodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate tlNodeIn.d.bits.corrupt
invalidate tlNodeIn.d.bits.data
invalidate tlNodeIn.d.bits.denied
invalidate tlNodeIn.d.bits.sink
invalidate tlNodeIn.d.bits.source
invalidate tlNodeIn.d.bits.size
invalidate tlNodeIn.d.bits.param
invalidate tlNodeIn.d.bits.opcode
invalidate tlNodeIn.d.valid
invalidate tlNodeIn.d.ready
invalidate tlNodeIn.a.bits.corrupt
invalidate tlNodeIn.a.bits.data
invalidate tlNodeIn.a.bits.mask
invalidate tlNodeIn.a.bits.address
invalidate tlNodeIn.a.bits.source
invalidate tlNodeIn.a.bits.size
invalidate tlNodeIn.a.bits.param
invalidate tlNodeIn.a.bits.opcode
invalidate tlNodeIn.a.valid
invalidate tlNodeIn.a.ready
wire x1_tlNodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate x1_tlNodeIn.d.bits.corrupt
invalidate x1_tlNodeIn.d.bits.data
invalidate x1_tlNodeIn.d.bits.denied
invalidate x1_tlNodeIn.d.bits.sink
invalidate x1_tlNodeIn.d.bits.source
invalidate x1_tlNodeIn.d.bits.size
invalidate x1_tlNodeIn.d.bits.param
invalidate x1_tlNodeIn.d.bits.opcode
invalidate x1_tlNodeIn.d.valid
invalidate x1_tlNodeIn.d.ready
invalidate x1_tlNodeIn.a.bits.corrupt
invalidate x1_tlNodeIn.a.bits.data
invalidate x1_tlNodeIn.a.bits.mask
invalidate x1_tlNodeIn.a.bits.address
invalidate x1_tlNodeIn.a.bits.source
invalidate x1_tlNodeIn.a.bits.size
invalidate x1_tlNodeIn.a.bits.param
invalidate x1_tlNodeIn.a.bits.opcode
invalidate x1_tlNodeIn.a.valid
invalidate x1_tlNodeIn.a.ready
wire x1_tlNodeIn_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate x1_tlNodeIn_1.d.bits.corrupt
invalidate x1_tlNodeIn_1.d.bits.data
invalidate x1_tlNodeIn_1.d.bits.denied
invalidate x1_tlNodeIn_1.d.bits.sink
invalidate x1_tlNodeIn_1.d.bits.source
invalidate x1_tlNodeIn_1.d.bits.size
invalidate x1_tlNodeIn_1.d.bits.param
invalidate x1_tlNodeIn_1.d.bits.opcode
invalidate x1_tlNodeIn_1.d.valid
invalidate x1_tlNodeIn_1.d.ready
invalidate x1_tlNodeIn_1.a.bits.corrupt
invalidate x1_tlNodeIn_1.a.bits.data
invalidate x1_tlNodeIn_1.a.bits.mask
invalidate x1_tlNodeIn_1.a.bits.address
invalidate x1_tlNodeIn_1.a.bits.source
invalidate x1_tlNodeIn_1.a.bits.size
invalidate x1_tlNodeIn_1.a.bits.param
invalidate x1_tlNodeIn_1.a.bits.opcode
invalidate x1_tlNodeIn_1.a.valid
invalidate x1_tlNodeIn_1.a.ready
wire x1_tlNodeIn_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate x1_tlNodeIn_2.d.bits.corrupt
invalidate x1_tlNodeIn_2.d.bits.data
invalidate x1_tlNodeIn_2.d.bits.denied
invalidate x1_tlNodeIn_2.d.bits.sink
invalidate x1_tlNodeIn_2.d.bits.source
invalidate x1_tlNodeIn_2.d.bits.size
invalidate x1_tlNodeIn_2.d.bits.param
invalidate x1_tlNodeIn_2.d.bits.opcode
invalidate x1_tlNodeIn_2.d.valid
invalidate x1_tlNodeIn_2.d.ready
invalidate x1_tlNodeIn_2.a.bits.corrupt
invalidate x1_tlNodeIn_2.a.bits.data
invalidate x1_tlNodeIn_2.a.bits.mask
invalidate x1_tlNodeIn_2.a.bits.address
invalidate x1_tlNodeIn_2.a.bits.source
invalidate x1_tlNodeIn_2.a.bits.size
invalidate x1_tlNodeIn_2.a.bits.param
invalidate x1_tlNodeIn_2.a.bits.opcode
invalidate x1_tlNodeIn_2.a.valid
invalidate x1_tlNodeIn_2.a.ready
wire x1_tlNodeIn_3 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate x1_tlNodeIn_3.d.bits.corrupt
invalidate x1_tlNodeIn_3.d.bits.data
invalidate x1_tlNodeIn_3.d.bits.denied
invalidate x1_tlNodeIn_3.d.bits.sink
invalidate x1_tlNodeIn_3.d.bits.source
invalidate x1_tlNodeIn_3.d.bits.size
invalidate x1_tlNodeIn_3.d.bits.param
invalidate x1_tlNodeIn_3.d.bits.opcode
invalidate x1_tlNodeIn_3.d.valid
invalidate x1_tlNodeIn_3.d.ready
invalidate x1_tlNodeIn_3.a.bits.corrupt
invalidate x1_tlNodeIn_3.a.bits.data
invalidate x1_tlNodeIn_3.a.bits.mask
invalidate x1_tlNodeIn_3.a.bits.address
invalidate x1_tlNodeIn_3.a.bits.source
invalidate x1_tlNodeIn_3.a.bits.size
invalidate x1_tlNodeIn_3.a.bits.param
invalidate x1_tlNodeIn_3.a.bits.opcode
invalidate x1_tlNodeIn_3.a.valid
invalidate x1_tlNodeIn_3.a.ready
wire x1_tlNodeIn_4 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate x1_tlNodeIn_4.d.bits.corrupt
invalidate x1_tlNodeIn_4.d.bits.data
invalidate x1_tlNodeIn_4.d.bits.denied
invalidate x1_tlNodeIn_4.d.bits.sink
invalidate x1_tlNodeIn_4.d.bits.source
invalidate x1_tlNodeIn_4.d.bits.size
invalidate x1_tlNodeIn_4.d.bits.param
invalidate x1_tlNodeIn_4.d.bits.opcode
invalidate x1_tlNodeIn_4.d.valid
invalidate x1_tlNodeIn_4.d.ready
invalidate x1_tlNodeIn_4.a.bits.corrupt
invalidate x1_tlNodeIn_4.a.bits.data
invalidate x1_tlNodeIn_4.a.bits.mask
invalidate x1_tlNodeIn_4.a.bits.address
invalidate x1_tlNodeIn_4.a.bits.source
invalidate x1_tlNodeIn_4.a.bits.size
invalidate x1_tlNodeIn_4.a.bits.param
invalidate x1_tlNodeIn_4.a.bits.opcode
invalidate x1_tlNodeIn_4.a.valid
invalidate x1_tlNodeIn_4.a.ready
wire x1_tlNodeIn_5 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate x1_tlNodeIn_5.d.bits.corrupt
invalidate x1_tlNodeIn_5.d.bits.data
invalidate x1_tlNodeIn_5.d.bits.denied
invalidate x1_tlNodeIn_5.d.bits.sink
invalidate x1_tlNodeIn_5.d.bits.source
invalidate x1_tlNodeIn_5.d.bits.size
invalidate x1_tlNodeIn_5.d.bits.param
invalidate x1_tlNodeIn_5.d.bits.opcode
invalidate x1_tlNodeIn_5.d.valid
invalidate x1_tlNodeIn_5.d.ready
invalidate x1_tlNodeIn_5.a.bits.corrupt
invalidate x1_tlNodeIn_5.a.bits.data
invalidate x1_tlNodeIn_5.a.bits.mask
invalidate x1_tlNodeIn_5.a.bits.address
invalidate x1_tlNodeIn_5.a.bits.source
invalidate x1_tlNodeIn_5.a.bits.size
invalidate x1_tlNodeIn_5.a.bits.param
invalidate x1_tlNodeIn_5.a.bits.opcode
invalidate x1_tlNodeIn_5.a.valid
invalidate x1_tlNodeIn_5.a.ready
wire x1_tlNodeIn_6 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate x1_tlNodeIn_6.d.bits.corrupt
invalidate x1_tlNodeIn_6.d.bits.data
invalidate x1_tlNodeIn_6.d.bits.denied
invalidate x1_tlNodeIn_6.d.bits.sink
invalidate x1_tlNodeIn_6.d.bits.source
invalidate x1_tlNodeIn_6.d.bits.size
invalidate x1_tlNodeIn_6.d.bits.param
invalidate x1_tlNodeIn_6.d.bits.opcode
invalidate x1_tlNodeIn_6.d.valid
invalidate x1_tlNodeIn_6.d.ready
invalidate x1_tlNodeIn_6.a.bits.corrupt
invalidate x1_tlNodeIn_6.a.bits.data
invalidate x1_tlNodeIn_6.a.bits.mask
invalidate x1_tlNodeIn_6.a.bits.address
invalidate x1_tlNodeIn_6.a.bits.source
invalidate x1_tlNodeIn_6.a.bits.size
invalidate x1_tlNodeIn_6.a.bits.param
invalidate x1_tlNodeIn_6.a.bits.opcode
invalidate x1_tlNodeIn_6.a.valid
invalidate x1_tlNodeIn_6.a.ready
wire x1_tlNodeIn_7 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate x1_tlNodeIn_7.d.bits.corrupt
invalidate x1_tlNodeIn_7.d.bits.data
invalidate x1_tlNodeIn_7.d.bits.denied
invalidate x1_tlNodeIn_7.d.bits.sink
invalidate x1_tlNodeIn_7.d.bits.source
invalidate x1_tlNodeIn_7.d.bits.size
invalidate x1_tlNodeIn_7.d.bits.param
invalidate x1_tlNodeIn_7.d.bits.opcode
invalidate x1_tlNodeIn_7.d.valid
invalidate x1_tlNodeIn_7.d.ready
invalidate x1_tlNodeIn_7.a.bits.corrupt
invalidate x1_tlNodeIn_7.a.bits.data
invalidate x1_tlNodeIn_7.a.bits.mask
invalidate x1_tlNodeIn_7.a.bits.address
invalidate x1_tlNodeIn_7.a.bits.source
invalidate x1_tlNodeIn_7.a.bits.size
invalidate x1_tlNodeIn_7.a.bits.param
invalidate x1_tlNodeIn_7.a.bits.opcode
invalidate x1_tlNodeIn_7.a.valid
invalidate x1_tlNodeIn_7.a.ready
wire x1_tlNodeIn_8 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate x1_tlNodeIn_8.d.bits.corrupt
invalidate x1_tlNodeIn_8.d.bits.data
invalidate x1_tlNodeIn_8.d.bits.denied
invalidate x1_tlNodeIn_8.d.bits.sink
invalidate x1_tlNodeIn_8.d.bits.source
invalidate x1_tlNodeIn_8.d.bits.size
invalidate x1_tlNodeIn_8.d.bits.param
invalidate x1_tlNodeIn_8.d.bits.opcode
invalidate x1_tlNodeIn_8.d.valid
invalidate x1_tlNodeIn_8.d.ready
invalidate x1_tlNodeIn_8.a.bits.corrupt
invalidate x1_tlNodeIn_8.a.bits.data
invalidate x1_tlNodeIn_8.a.bits.mask
invalidate x1_tlNodeIn_8.a.bits.address
invalidate x1_tlNodeIn_8.a.bits.source
invalidate x1_tlNodeIn_8.a.bits.size
invalidate x1_tlNodeIn_8.a.bits.param
invalidate x1_tlNodeIn_8.a.bits.opcode
invalidate x1_tlNodeIn_8.a.valid
invalidate x1_tlNodeIn_8.a.ready
wire x1_tlNodeIn_9 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate x1_tlNodeIn_9.d.bits.corrupt
invalidate x1_tlNodeIn_9.d.bits.data
invalidate x1_tlNodeIn_9.d.bits.denied
invalidate x1_tlNodeIn_9.d.bits.sink
invalidate x1_tlNodeIn_9.d.bits.source
invalidate x1_tlNodeIn_9.d.bits.size
invalidate x1_tlNodeIn_9.d.bits.param
invalidate x1_tlNodeIn_9.d.bits.opcode
invalidate x1_tlNodeIn_9.d.valid
invalidate x1_tlNodeIn_9.d.ready
invalidate x1_tlNodeIn_9.a.bits.corrupt
invalidate x1_tlNodeIn_9.a.bits.data
invalidate x1_tlNodeIn_9.a.bits.mask
invalidate x1_tlNodeIn_9.a.bits.address
invalidate x1_tlNodeIn_9.a.bits.source
invalidate x1_tlNodeIn_9.a.bits.size
invalidate x1_tlNodeIn_9.a.bits.param
invalidate x1_tlNodeIn_9.a.bits.opcode
invalidate x1_tlNodeIn_9.a.valid
invalidate x1_tlNodeIn_9.a.ready
wire x1_tlNodeIn_10 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate x1_tlNodeIn_10.d.bits.corrupt
invalidate x1_tlNodeIn_10.d.bits.data
invalidate x1_tlNodeIn_10.d.bits.denied
invalidate x1_tlNodeIn_10.d.bits.sink
invalidate x1_tlNodeIn_10.d.bits.source
invalidate x1_tlNodeIn_10.d.bits.size
invalidate x1_tlNodeIn_10.d.bits.param
invalidate x1_tlNodeIn_10.d.bits.opcode
invalidate x1_tlNodeIn_10.d.valid
invalidate x1_tlNodeIn_10.d.ready
invalidate x1_tlNodeIn_10.a.bits.corrupt
invalidate x1_tlNodeIn_10.a.bits.data
invalidate x1_tlNodeIn_10.a.bits.mask
invalidate x1_tlNodeIn_10.a.bits.address
invalidate x1_tlNodeIn_10.a.bits.source
invalidate x1_tlNodeIn_10.a.bits.size
invalidate x1_tlNodeIn_10.a.bits.param
invalidate x1_tlNodeIn_10.a.bits.opcode
invalidate x1_tlNodeIn_10.a.valid
invalidate x1_tlNodeIn_10.a.ready
wire x1_tlNodeIn_11 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate x1_tlNodeIn_11.d.bits.corrupt
invalidate x1_tlNodeIn_11.d.bits.data
invalidate x1_tlNodeIn_11.d.bits.denied
invalidate x1_tlNodeIn_11.d.bits.sink
invalidate x1_tlNodeIn_11.d.bits.source
invalidate x1_tlNodeIn_11.d.bits.size
invalidate x1_tlNodeIn_11.d.bits.param
invalidate x1_tlNodeIn_11.d.bits.opcode
invalidate x1_tlNodeIn_11.d.valid
invalidate x1_tlNodeIn_11.d.ready
invalidate x1_tlNodeIn_11.a.bits.corrupt
invalidate x1_tlNodeIn_11.a.bits.data
invalidate x1_tlNodeIn_11.a.bits.mask
invalidate x1_tlNodeIn_11.a.bits.address
invalidate x1_tlNodeIn_11.a.bits.source
invalidate x1_tlNodeIn_11.a.bits.size
invalidate x1_tlNodeIn_11.a.bits.param
invalidate x1_tlNodeIn_11.a.bits.opcode
invalidate x1_tlNodeIn_11.a.valid
invalidate x1_tlNodeIn_11.a.ready
wire x1_tlNodeIn_12 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate x1_tlNodeIn_12.d.bits.corrupt
invalidate x1_tlNodeIn_12.d.bits.data
invalidate x1_tlNodeIn_12.d.bits.denied
invalidate x1_tlNodeIn_12.d.bits.sink
invalidate x1_tlNodeIn_12.d.bits.source
invalidate x1_tlNodeIn_12.d.bits.size
invalidate x1_tlNodeIn_12.d.bits.param
invalidate x1_tlNodeIn_12.d.bits.opcode
invalidate x1_tlNodeIn_12.d.valid
invalidate x1_tlNodeIn_12.d.ready
invalidate x1_tlNodeIn_12.a.bits.corrupt
invalidate x1_tlNodeIn_12.a.bits.data
invalidate x1_tlNodeIn_12.a.bits.mask
invalidate x1_tlNodeIn_12.a.bits.address
invalidate x1_tlNodeIn_12.a.bits.source
invalidate x1_tlNodeIn_12.a.bits.size
invalidate x1_tlNodeIn_12.a.bits.param
invalidate x1_tlNodeIn_12.a.bits.opcode
invalidate x1_tlNodeIn_12.a.valid
invalidate x1_tlNodeIn_12.a.ready
wire x1_tlNodeIn_13 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate x1_tlNodeIn_13.d.bits.corrupt
invalidate x1_tlNodeIn_13.d.bits.data
invalidate x1_tlNodeIn_13.d.bits.denied
invalidate x1_tlNodeIn_13.d.bits.sink
invalidate x1_tlNodeIn_13.d.bits.source
invalidate x1_tlNodeIn_13.d.bits.size
invalidate x1_tlNodeIn_13.d.bits.param
invalidate x1_tlNodeIn_13.d.bits.opcode
invalidate x1_tlNodeIn_13.d.valid
invalidate x1_tlNodeIn_13.d.ready
invalidate x1_tlNodeIn_13.a.bits.corrupt
invalidate x1_tlNodeIn_13.a.bits.data
invalidate x1_tlNodeIn_13.a.bits.mask
invalidate x1_tlNodeIn_13.a.bits.address
invalidate x1_tlNodeIn_13.a.bits.source
invalidate x1_tlNodeIn_13.a.bits.size
invalidate x1_tlNodeIn_13.a.bits.param
invalidate x1_tlNodeIn_13.a.bits.opcode
invalidate x1_tlNodeIn_13.a.valid
invalidate x1_tlNodeIn_13.a.ready
wire x1_tlNodeIn_14 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate x1_tlNodeIn_14.d.bits.corrupt
invalidate x1_tlNodeIn_14.d.bits.data
invalidate x1_tlNodeIn_14.d.bits.denied
invalidate x1_tlNodeIn_14.d.bits.sink
invalidate x1_tlNodeIn_14.d.bits.source
invalidate x1_tlNodeIn_14.d.bits.size
invalidate x1_tlNodeIn_14.d.bits.param
invalidate x1_tlNodeIn_14.d.bits.opcode
invalidate x1_tlNodeIn_14.d.valid
invalidate x1_tlNodeIn_14.d.ready
invalidate x1_tlNodeIn_14.a.bits.corrupt
invalidate x1_tlNodeIn_14.a.bits.data
invalidate x1_tlNodeIn_14.a.bits.mask
invalidate x1_tlNodeIn_14.a.bits.address
invalidate x1_tlNodeIn_14.a.bits.source
invalidate x1_tlNodeIn_14.a.bits.size
invalidate x1_tlNodeIn_14.a.bits.param
invalidate x1_tlNodeIn_14.a.bits.opcode
invalidate x1_tlNodeIn_14.a.valid
invalidate x1_tlNodeIn_14.a.ready
wire x1_tlNodeIn_15 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate x1_tlNodeIn_15.d.bits.corrupt
invalidate x1_tlNodeIn_15.d.bits.data
invalidate x1_tlNodeIn_15.d.bits.denied
invalidate x1_tlNodeIn_15.d.bits.sink
invalidate x1_tlNodeIn_15.d.bits.source
invalidate x1_tlNodeIn_15.d.bits.size
invalidate x1_tlNodeIn_15.d.bits.param
invalidate x1_tlNodeIn_15.d.bits.opcode
invalidate x1_tlNodeIn_15.d.valid
invalidate x1_tlNodeIn_15.d.ready
invalidate x1_tlNodeIn_15.a.bits.corrupt
invalidate x1_tlNodeIn_15.a.bits.data
invalidate x1_tlNodeIn_15.a.bits.mask
invalidate x1_tlNodeIn_15.a.bits.address
invalidate x1_tlNodeIn_15.a.bits.source
invalidate x1_tlNodeIn_15.a.bits.size
invalidate x1_tlNodeIn_15.a.bits.param
invalidate x1_tlNodeIn_15.a.bits.opcode
invalidate x1_tlNodeIn_15.a.valid
invalidate x1_tlNodeIn_15.a.ready
wire x1_tlNodeIn_16 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate x1_tlNodeIn_16.d.bits.corrupt
invalidate x1_tlNodeIn_16.d.bits.data
invalidate x1_tlNodeIn_16.d.bits.denied
invalidate x1_tlNodeIn_16.d.bits.sink
invalidate x1_tlNodeIn_16.d.bits.source
invalidate x1_tlNodeIn_16.d.bits.size
invalidate x1_tlNodeIn_16.d.bits.param
invalidate x1_tlNodeIn_16.d.bits.opcode
invalidate x1_tlNodeIn_16.d.valid
invalidate x1_tlNodeIn_16.d.ready
invalidate x1_tlNodeIn_16.a.bits.corrupt
invalidate x1_tlNodeIn_16.a.bits.data
invalidate x1_tlNodeIn_16.a.bits.mask
invalidate x1_tlNodeIn_16.a.bits.address
invalidate x1_tlNodeIn_16.a.bits.source
invalidate x1_tlNodeIn_16.a.bits.size
invalidate x1_tlNodeIn_16.a.bits.param
invalidate x1_tlNodeIn_16.a.bits.opcode
invalidate x1_tlNodeIn_16.a.valid
invalidate x1_tlNodeIn_16.a.ready
connect tlNodeOut, tlNodeIn
connect x1_tlNodeOut, x1_tlNodeIn
connect x1_tlNodeOut_1, x1_tlNodeIn_1
connect x1_tlNodeOut_2, x1_tlNodeIn_2
connect x1_tlNodeOut_3, x1_tlNodeIn_3
connect x1_tlNodeOut_4, x1_tlNodeIn_4
connect x1_tlNodeOut_5, x1_tlNodeIn_5
connect x1_tlNodeOut_6, x1_tlNodeIn_6
connect x1_tlNodeOut_7, x1_tlNodeIn_7
connect x1_tlNodeOut_8, x1_tlNodeIn_8
connect x1_tlNodeOut_9, x1_tlNodeIn_9
connect x1_tlNodeOut_10, x1_tlNodeIn_10
connect x1_tlNodeOut_11, x1_tlNodeIn_11
connect x1_tlNodeOut_12, x1_tlNodeIn_12
connect x1_tlNodeOut_13, x1_tlNodeIn_13
connect x1_tlNodeOut_14, x1_tlNodeIn_14
connect x1_tlNodeOut_15, x1_tlNodeIn_15
connect x1_tlNodeOut_16, x1_tlNodeIn_16
connect widget.auto.anon_in, l2_fhdr_writer.auto.master_out
connect widget.auto.anon_out.d, tlNodeIn.d
connect tlNodeIn.a.bits, widget.auto.anon_out.a.bits
connect tlNodeIn.a.valid, widget.auto.anon_out.a.valid
connect widget.auto.anon_out.a.ready, tlNodeIn.a.ready
connect widget_1.auto.anon_in, l2_bhdr_writer.auto.master_out
connect widget_1.auto.anon_out.d, x1_tlNodeIn.d
connect x1_tlNodeIn.a.bits, widget_1.auto.anon_out.a.bits
connect x1_tlNodeIn.a.valid, widget_1.auto.anon_out.a.valid
connect widget_1.auto.anon_out.a.ready, x1_tlNodeIn.a.ready
connect widget_2.auto.anon_in, l2_mf_reader.auto.master_out
connect widget_2.auto.anon_out.d, x1_tlNodeIn_1.d
connect x1_tlNodeIn_1.a.bits, widget_2.auto.anon_out.a.bits
connect x1_tlNodeIn_1.a.valid, widget_2.auto.anon_out.a.valid
connect widget_2.auto.anon_out.a.ready, x1_tlNodeIn_1.a.ready
connect widget_3.auto.anon_in, l2_mf_seqwriter.auto.master_out
connect widget_3.auto.anon_out.d, x1_tlNodeIn_2.d
connect x1_tlNodeIn_2.a.bits, widget_3.auto.anon_out.a.bits
connect x1_tlNodeIn_2.a.valid, widget_3.auto.anon_out.a.valid
connect widget_3.auto.anon_out.a.ready, x1_tlNodeIn_2.a.ready
connect widget_4.auto.anon_in, l2_mf_litwriter.auto.master_out
connect widget_4.auto.anon_out.d, x1_tlNodeIn_3.d
connect x1_tlNodeIn_3.a.bits, widget_4.auto.anon_out.a.bits
connect x1_tlNodeIn_3.a.valid, widget_4.auto.anon_out.a.valid
connect widget_4.auto.anon_out.a.ready, x1_tlNodeIn_3.a.ready
connect widget_5.auto.anon_in, l2_huf_lit_reader.auto.master_out
connect widget_5.auto.anon_out.d, x1_tlNodeIn_4.d
connect x1_tlNodeIn_4.a.bits, widget_5.auto.anon_out.a.bits
connect x1_tlNodeIn_4.a.valid, widget_5.auto.anon_out.a.valid
connect widget_5.auto.anon_out.a.ready, x1_tlNodeIn_4.a.ready
connect widget_6.auto.anon_in, l2_huf_dic_reader.auto.master_out
connect widget_6.auto.anon_out.d, x1_tlNodeIn_5.d
connect x1_tlNodeIn_5.a.bits, widget_6.auto.anon_out.a.bits
connect x1_tlNodeIn_5.a.valid, widget_6.auto.anon_out.a.valid
connect widget_6.auto.anon_out.a.ready, x1_tlNodeIn_5.a.ready
connect widget_7.auto.anon_in, l2_huf_dic_writer.auto.master_out
connect widget_7.auto.anon_out.d, x1_tlNodeIn_6.d
connect x1_tlNodeIn_6.a.bits, widget_7.auto.anon_out.a.bits
connect x1_tlNodeIn_6.a.valid, widget_7.auto.anon_out.a.valid
connect widget_7.auto.anon_out.a.ready, x1_tlNodeIn_6.a.ready
connect widget_8.auto.anon_in, l2_huf_hdr_writer.auto.master_out
connect widget_8.auto.anon_out.d, x1_tlNodeIn_7.d
connect x1_tlNodeIn_7.a.bits, widget_8.auto.anon_out.a.bits
connect x1_tlNodeIn_7.a.valid, widget_8.auto.anon_out.a.valid
connect widget_8.auto.anon_out.a.ready, x1_tlNodeIn_7.a.ready
connect widget_9.auto.anon_in, l2_huf_jt_writer.auto.master_out
connect widget_9.auto.anon_out.d, x1_tlNodeIn_8.d
connect x1_tlNodeIn_8.a.bits, widget_9.auto.anon_out.a.bits
connect x1_tlNodeIn_8.a.valid, widget_9.auto.anon_out.a.valid
connect widget_9.auto.anon_out.a.ready, x1_tlNodeIn_8.a.ready
connect widget_10.auto.anon_in, l2_huf_lit_writer.auto.master_out
connect widget_10.auto.anon_out.d, x1_tlNodeIn_9.d
connect x1_tlNodeIn_9.a.bits, widget_10.auto.anon_out.a.bits
connect x1_tlNodeIn_9.a.valid, widget_10.auto.anon_out.a.valid
connect widget_10.auto.anon_out.a.ready, x1_tlNodeIn_9.a.ready
connect widget_11.auto.anon_in, l2_seq_reader.auto.master_out
connect widget_11.auto.anon_out.d, x1_tlNodeIn_10.d
connect x1_tlNodeIn_10.a.bits, widget_11.auto.anon_out.a.bits
connect x1_tlNodeIn_10.a.valid, widget_11.auto.anon_out.a.valid
connect widget_11.auto.anon_out.a.ready, x1_tlNodeIn_10.a.ready
connect widget_12.auto.anon_in, l2_seq_reader2.auto.master_out
connect widget_12.auto.anon_out.d, x1_tlNodeIn_11.d
connect x1_tlNodeIn_11.a.bits, widget_12.auto.anon_out.a.bits
connect x1_tlNodeIn_11.a.valid, widget_12.auto.anon_out.a.valid
connect widget_12.auto.anon_out.a.ready, x1_tlNodeIn_11.a.ready
connect widget_13.auto.anon_in, l2_seq_writer.auto.master_out
connect widget_13.auto.anon_out.d, x1_tlNodeIn_12.d
connect x1_tlNodeIn_12.a.bits, widget_13.auto.anon_out.a.bits
connect x1_tlNodeIn_12.a.valid, widget_13.auto.anon_out.a.valid
connect widget_13.auto.anon_out.a.ready, x1_tlNodeIn_12.a.ready
connect widget_14.auto.anon_in, l2_raw_block_reader.auto.master_out
connect widget_14.auto.anon_out.d, x1_tlNodeIn_13.d
connect x1_tlNodeIn_13.a.bits, widget_14.auto.anon_out.a.bits
connect x1_tlNodeIn_13.a.valid, widget_14.auto.anon_out.a.valid
connect widget_14.auto.anon_out.a.ready, x1_tlNodeIn_13.a.ready
connect widget_15.auto.anon_in, l2_raw_block_writer.auto.master_out
connect widget_15.auto.anon_out.d, x1_tlNodeIn_14.d
connect x1_tlNodeIn_14.a.bits, widget_15.auto.anon_out.a.bits
connect x1_tlNodeIn_14.a.valid, widget_15.auto.anon_out.a.valid
connect widget_15.auto.anon_out.a.ready, x1_tlNodeIn_14.a.ready
connect widget_16.auto.anon_in, l2_raw_lit_reader.auto.master_out
connect widget_16.auto.anon_out.d, x1_tlNodeIn_15.d
connect x1_tlNodeIn_15.a.bits, widget_16.auto.anon_out.a.bits
connect x1_tlNodeIn_15.a.valid, widget_16.auto.anon_out.a.valid
connect widget_16.auto.anon_out.a.ready, x1_tlNodeIn_15.a.ready
connect widget_17.auto.anon_in, l2_raw_lit_writer.auto.master_out
connect widget_17.auto.anon_out.d, x1_tlNodeIn_16.d
connect x1_tlNodeIn_16.a.bits, widget_17.auto.anon_out.a.bits
connect x1_tlNodeIn_16.a.valid, widget_17.auto.anon_out.a.valid
connect widget_17.auto.anon_out.a.ready, x1_tlNodeIn_16.a.ready
connect auto.tl_out_0, tlNodeOut
connect auto.tl_out_1, x1_tlNodeOut
connect auto.tl_out_2, x1_tlNodeOut_1
connect auto.tl_out_3, x1_tlNodeOut_2
connect auto.tl_out_4, x1_tlNodeOut_3
connect auto.tl_out_5, x1_tlNodeOut_4
connect auto.tl_out_6, x1_tlNodeOut_5
connect auto.tl_out_7, x1_tlNodeOut_6
connect auto.tl_out_8, x1_tlNodeOut_7
connect auto.tl_out_9, x1_tlNodeOut_8
connect auto.tl_out_10, x1_tlNodeOut_9
connect auto.tl_out_11, x1_tlNodeOut_10
connect auto.tl_out_12, x1_tlNodeOut_11
connect auto.tl_out_13, x1_tlNodeOut_12
connect auto.tl_out_14, x1_tlNodeOut_13
connect auto.tl_out_15, x1_tlNodeOut_14
connect auto.tl_out_16, x1_tlNodeOut_15
connect auto.tl_out_17, x1_tlNodeOut_16
invalidate io.fpu_resp.bits.exc
invalidate io.fpu_resp.bits.data
invalidate io.fpu_resp.valid
invalidate io.fpu_resp.ready
invalidate io.fpu_req.bits.in3
invalidate io.fpu_req.bits.in2
invalidate io.fpu_req.bits.in1
invalidate io.fpu_req.bits.fmt
invalidate io.fpu_req.bits.typ
invalidate io.fpu_req.bits.fmaCmd
invalidate io.fpu_req.bits.rm
invalidate io.fpu_req.bits.vec
invalidate io.fpu_req.bits.wflags
invalidate io.fpu_req.bits.sqrt
invalidate io.fpu_req.bits.div
invalidate io.fpu_req.bits.fma
invalidate io.fpu_req.bits.fastpipe
invalidate io.fpu_req.bits.toint
invalidate io.fpu_req.bits.fromint
invalidate io.fpu_req.bits.typeTagOut
invalidate io.fpu_req.bits.typeTagIn
invalidate io.fpu_req.bits.swap23
invalidate io.fpu_req.bits.swap12
invalidate io.fpu_req.bits.ren3
invalidate io.fpu_req.bits.ren2
invalidate io.fpu_req.bits.ren1
invalidate io.fpu_req.bits.wen
invalidate io.fpu_req.bits.ldst
invalidate io.fpu_req.valid
invalidate io.fpu_req.ready
invalidate io.ptw[0].customCSRs.csrs[0].sdata
invalidate io.ptw[0].customCSRs.csrs[0].set
invalidate io.ptw[0].customCSRs.csrs[0].stall
invalidate io.ptw[0].customCSRs.csrs[0].value
invalidate io.ptw[0].customCSRs.csrs[0].wdata
invalidate io.ptw[0].customCSRs.csrs[0].wen
invalidate io.ptw[0].customCSRs.csrs[0].ren
invalidate io.ptw[0].customCSRs.csrs[1].sdata
invalidate io.ptw[0].customCSRs.csrs[1].set
invalidate io.ptw[0].customCSRs.csrs[1].stall
invalidate io.ptw[0].customCSRs.csrs[1].value
invalidate io.ptw[0].customCSRs.csrs[1].wdata
invalidate io.ptw[0].customCSRs.csrs[1].wen
invalidate io.ptw[0].customCSRs.csrs[1].ren
invalidate io.ptw[0].customCSRs.csrs[2].sdata
invalidate io.ptw[0].customCSRs.csrs[2].set
invalidate io.ptw[0].customCSRs.csrs[2].stall
invalidate io.ptw[0].customCSRs.csrs[2].value
invalidate io.ptw[0].customCSRs.csrs[2].wdata
invalidate io.ptw[0].customCSRs.csrs[2].wen
invalidate io.ptw[0].customCSRs.csrs[2].ren
invalidate io.ptw[0].customCSRs.csrs[3].sdata
invalidate io.ptw[0].customCSRs.csrs[3].set
invalidate io.ptw[0].customCSRs.csrs[3].stall
invalidate io.ptw[0].customCSRs.csrs[3].value
invalidate io.ptw[0].customCSRs.csrs[3].wdata
invalidate io.ptw[0].customCSRs.csrs[3].wen
invalidate io.ptw[0].customCSRs.csrs[3].ren
invalidate io.ptw[0].pmp[0].mask
invalidate io.ptw[0].pmp[0].addr
invalidate io.ptw[0].pmp[0].cfg.r
invalidate io.ptw[0].pmp[0].cfg.w
invalidate io.ptw[0].pmp[0].cfg.x
invalidate io.ptw[0].pmp[0].cfg.a
invalidate io.ptw[0].pmp[0].cfg.res
invalidate io.ptw[0].pmp[0].cfg.l
invalidate io.ptw[0].pmp[1].mask
invalidate io.ptw[0].pmp[1].addr
invalidate io.ptw[0].pmp[1].cfg.r
invalidate io.ptw[0].pmp[1].cfg.w
invalidate io.ptw[0].pmp[1].cfg.x
invalidate io.ptw[0].pmp[1].cfg.a
invalidate io.ptw[0].pmp[1].cfg.res
invalidate io.ptw[0].pmp[1].cfg.l
invalidate io.ptw[0].pmp[2].mask
invalidate io.ptw[0].pmp[2].addr
invalidate io.ptw[0].pmp[2].cfg.r
invalidate io.ptw[0].pmp[2].cfg.w
invalidate io.ptw[0].pmp[2].cfg.x
invalidate io.ptw[0].pmp[2].cfg.a
invalidate io.ptw[0].pmp[2].cfg.res
invalidate io.ptw[0].pmp[2].cfg.l
invalidate io.ptw[0].pmp[3].mask
invalidate io.ptw[0].pmp[3].addr
invalidate io.ptw[0].pmp[3].cfg.r
invalidate io.ptw[0].pmp[3].cfg.w
invalidate io.ptw[0].pmp[3].cfg.x
invalidate io.ptw[0].pmp[3].cfg.a
invalidate io.ptw[0].pmp[3].cfg.res
invalidate io.ptw[0].pmp[3].cfg.l
invalidate io.ptw[0].pmp[4].mask
invalidate io.ptw[0].pmp[4].addr
invalidate io.ptw[0].pmp[4].cfg.r
invalidate io.ptw[0].pmp[4].cfg.w
invalidate io.ptw[0].pmp[4].cfg.x
invalidate io.ptw[0].pmp[4].cfg.a
invalidate io.ptw[0].pmp[4].cfg.res
invalidate io.ptw[0].pmp[4].cfg.l
invalidate io.ptw[0].pmp[5].mask
invalidate io.ptw[0].pmp[5].addr
invalidate io.ptw[0].pmp[5].cfg.r
invalidate io.ptw[0].pmp[5].cfg.w
invalidate io.ptw[0].pmp[5].cfg.x
invalidate io.ptw[0].pmp[5].cfg.a
invalidate io.ptw[0].pmp[5].cfg.res
invalidate io.ptw[0].pmp[5].cfg.l
invalidate io.ptw[0].pmp[6].mask
invalidate io.ptw[0].pmp[6].addr
invalidate io.ptw[0].pmp[6].cfg.r
invalidate io.ptw[0].pmp[6].cfg.w
invalidate io.ptw[0].pmp[6].cfg.x
invalidate io.ptw[0].pmp[6].cfg.a
invalidate io.ptw[0].pmp[6].cfg.res
invalidate io.ptw[0].pmp[6].cfg.l
invalidate io.ptw[0].pmp[7].mask
invalidate io.ptw[0].pmp[7].addr
invalidate io.ptw[0].pmp[7].cfg.r
invalidate io.ptw[0].pmp[7].cfg.w
invalidate io.ptw[0].pmp[7].cfg.x
invalidate io.ptw[0].pmp[7].cfg.a
invalidate io.ptw[0].pmp[7].cfg.res
invalidate io.ptw[0].pmp[7].cfg.l
invalidate io.ptw[0].gstatus.uie
invalidate io.ptw[0].gstatus.sie
invalidate io.ptw[0].gstatus.hie
invalidate io.ptw[0].gstatus.mie
invalidate io.ptw[0].gstatus.upie
invalidate io.ptw[0].gstatus.spie
invalidate io.ptw[0].gstatus.ube
invalidate io.ptw[0].gstatus.mpie
invalidate io.ptw[0].gstatus.spp
invalidate io.ptw[0].gstatus.vs
invalidate io.ptw[0].gstatus.mpp
invalidate io.ptw[0].gstatus.fs
invalidate io.ptw[0].gstatus.xs
invalidate io.ptw[0].gstatus.mprv
invalidate io.ptw[0].gstatus.sum
invalidate io.ptw[0].gstatus.mxr
invalidate io.ptw[0].gstatus.tvm
invalidate io.ptw[0].gstatus.tw
invalidate io.ptw[0].gstatus.tsr
invalidate io.ptw[0].gstatus.zero1
invalidate io.ptw[0].gstatus.sd_rv32
invalidate io.ptw[0].gstatus.uxl
invalidate io.ptw[0].gstatus.sxl
invalidate io.ptw[0].gstatus.sbe
invalidate io.ptw[0].gstatus.mbe
invalidate io.ptw[0].gstatus.gva
invalidate io.ptw[0].gstatus.mpv
invalidate io.ptw[0].gstatus.zero2
invalidate io.ptw[0].gstatus.sd
invalidate io.ptw[0].gstatus.v
invalidate io.ptw[0].gstatus.prv
invalidate io.ptw[0].gstatus.dv
invalidate io.ptw[0].gstatus.dprv
invalidate io.ptw[0].gstatus.isa
invalidate io.ptw[0].gstatus.wfi
invalidate io.ptw[0].gstatus.cease
invalidate io.ptw[0].gstatus.debug
invalidate io.ptw[0].hstatus.zero1
invalidate io.ptw[0].hstatus.vsbe
invalidate io.ptw[0].hstatus.gva
invalidate io.ptw[0].hstatus.spv
invalidate io.ptw[0].hstatus.spvp
invalidate io.ptw[0].hstatus.hu
invalidate io.ptw[0].hstatus.zero2
invalidate io.ptw[0].hstatus.vgein
invalidate io.ptw[0].hstatus.zero3
invalidate io.ptw[0].hstatus.vtvm
invalidate io.ptw[0].hstatus.vtw
invalidate io.ptw[0].hstatus.vtsr
invalidate io.ptw[0].hstatus.zero5
invalidate io.ptw[0].hstatus.vsxl
invalidate io.ptw[0].hstatus.zero6
invalidate io.ptw[0].status.uie
invalidate io.ptw[0].status.sie
invalidate io.ptw[0].status.hie
invalidate io.ptw[0].status.mie
invalidate io.ptw[0].status.upie
invalidate io.ptw[0].status.spie
invalidate io.ptw[0].status.ube
invalidate io.ptw[0].status.mpie
invalidate io.ptw[0].status.spp
invalidate io.ptw[0].status.vs
invalidate io.ptw[0].status.mpp
invalidate io.ptw[0].status.fs
invalidate io.ptw[0].status.xs
invalidate io.ptw[0].status.mprv
invalidate io.ptw[0].status.sum
invalidate io.ptw[0].status.mxr
invalidate io.ptw[0].status.tvm
invalidate io.ptw[0].status.tw
invalidate io.ptw[0].status.tsr
invalidate io.ptw[0].status.zero1
invalidate io.ptw[0].status.sd_rv32
invalidate io.ptw[0].status.uxl
invalidate io.ptw[0].status.sxl
invalidate io.ptw[0].status.sbe
invalidate io.ptw[0].status.mbe
invalidate io.ptw[0].status.gva
invalidate io.ptw[0].status.mpv
invalidate io.ptw[0].status.zero2
invalidate io.ptw[0].status.sd
invalidate io.ptw[0].status.v
invalidate io.ptw[0].status.prv
invalidate io.ptw[0].status.dv
invalidate io.ptw[0].status.dprv
invalidate io.ptw[0].status.isa
invalidate io.ptw[0].status.wfi
invalidate io.ptw[0].status.cease
invalidate io.ptw[0].status.debug
invalidate io.ptw[0].vsatp.ppn
invalidate io.ptw[0].vsatp.asid
invalidate io.ptw[0].vsatp.mode
invalidate io.ptw[0].hgatp.ppn
invalidate io.ptw[0].hgatp.asid
invalidate io.ptw[0].hgatp.mode
invalidate io.ptw[0].ptbr.ppn
invalidate io.ptw[0].ptbr.asid
invalidate io.ptw[0].ptbr.mode
invalidate io.ptw[0].resp.bits.gpa_is_pte
invalidate io.ptw[0].resp.bits.gpa.bits
invalidate io.ptw[0].resp.bits.gpa.valid
invalidate io.ptw[0].resp.bits.homogeneous
invalidate io.ptw[0].resp.bits.fragmented_superpage
invalidate io.ptw[0].resp.bits.level
invalidate io.ptw[0].resp.bits.pte.v
invalidate io.ptw[0].resp.bits.pte.r
invalidate io.ptw[0].resp.bits.pte.w
invalidate io.ptw[0].resp.bits.pte.x
invalidate io.ptw[0].resp.bits.pte.u
invalidate io.ptw[0].resp.bits.pte.g
invalidate io.ptw[0].resp.bits.pte.a
invalidate io.ptw[0].resp.bits.pte.d
invalidate io.ptw[0].resp.bits.pte.reserved_for_software
invalidate io.ptw[0].resp.bits.pte.ppn
invalidate io.ptw[0].resp.bits.pte.reserved_for_future
invalidate io.ptw[0].resp.bits.hx
invalidate io.ptw[0].resp.bits.hw
invalidate io.ptw[0].resp.bits.hr
invalidate io.ptw[0].resp.bits.gf
invalidate io.ptw[0].resp.bits.pf
invalidate io.ptw[0].resp.bits.ae_final
invalidate io.ptw[0].resp.bits.ae_ptw
invalidate io.ptw[0].resp.valid
invalidate io.ptw[0].req.bits.bits.stage2
invalidate io.ptw[0].req.bits.bits.vstage1
invalidate io.ptw[0].req.bits.bits.need_gpa
invalidate io.ptw[0].req.bits.bits.addr
invalidate io.ptw[0].req.bits.valid
invalidate io.ptw[0].req.valid
invalidate io.ptw[0].req.ready
invalidate io.ptw[1].customCSRs.csrs[0].sdata
invalidate io.ptw[1].customCSRs.csrs[0].set
invalidate io.ptw[1].customCSRs.csrs[0].stall
invalidate io.ptw[1].customCSRs.csrs[0].value
invalidate io.ptw[1].customCSRs.csrs[0].wdata
invalidate io.ptw[1].customCSRs.csrs[0].wen
invalidate io.ptw[1].customCSRs.csrs[0].ren
invalidate io.ptw[1].customCSRs.csrs[1].sdata
invalidate io.ptw[1].customCSRs.csrs[1].set
invalidate io.ptw[1].customCSRs.csrs[1].stall
invalidate io.ptw[1].customCSRs.csrs[1].value
invalidate io.ptw[1].customCSRs.csrs[1].wdata
invalidate io.ptw[1].customCSRs.csrs[1].wen
invalidate io.ptw[1].customCSRs.csrs[1].ren
invalidate io.ptw[1].customCSRs.csrs[2].sdata
invalidate io.ptw[1].customCSRs.csrs[2].set
invalidate io.ptw[1].customCSRs.csrs[2].stall
invalidate io.ptw[1].customCSRs.csrs[2].value
invalidate io.ptw[1].customCSRs.csrs[2].wdata
invalidate io.ptw[1].customCSRs.csrs[2].wen
invalidate io.ptw[1].customCSRs.csrs[2].ren
invalidate io.ptw[1].customCSRs.csrs[3].sdata
invalidate io.ptw[1].customCSRs.csrs[3].set
invalidate io.ptw[1].customCSRs.csrs[3].stall
invalidate io.ptw[1].customCSRs.csrs[3].value
invalidate io.ptw[1].customCSRs.csrs[3].wdata
invalidate io.ptw[1].customCSRs.csrs[3].wen
invalidate io.ptw[1].customCSRs.csrs[3].ren
invalidate io.ptw[1].pmp[0].mask
invalidate io.ptw[1].pmp[0].addr
invalidate io.ptw[1].pmp[0].cfg.r
invalidate io.ptw[1].pmp[0].cfg.w
invalidate io.ptw[1].pmp[0].cfg.x
invalidate io.ptw[1].pmp[0].cfg.a
invalidate io.ptw[1].pmp[0].cfg.res
invalidate io.ptw[1].pmp[0].cfg.l
invalidate io.ptw[1].pmp[1].mask
invalidate io.ptw[1].pmp[1].addr
invalidate io.ptw[1].pmp[1].cfg.r
invalidate io.ptw[1].pmp[1].cfg.w
invalidate io.ptw[1].pmp[1].cfg.x
invalidate io.ptw[1].pmp[1].cfg.a
invalidate io.ptw[1].pmp[1].cfg.res
invalidate io.ptw[1].pmp[1].cfg.l
invalidate io.ptw[1].pmp[2].mask
invalidate io.ptw[1].pmp[2].addr
invalidate io.ptw[1].pmp[2].cfg.r
invalidate io.ptw[1].pmp[2].cfg.w
invalidate io.ptw[1].pmp[2].cfg.x
invalidate io.ptw[1].pmp[2].cfg.a
invalidate io.ptw[1].pmp[2].cfg.res
invalidate io.ptw[1].pmp[2].cfg.l
invalidate io.ptw[1].pmp[3].mask
invalidate io.ptw[1].pmp[3].addr
invalidate io.ptw[1].pmp[3].cfg.r
invalidate io.ptw[1].pmp[3].cfg.w
invalidate io.ptw[1].pmp[3].cfg.x
invalidate io.ptw[1].pmp[3].cfg.a
invalidate io.ptw[1].pmp[3].cfg.res
invalidate io.ptw[1].pmp[3].cfg.l
invalidate io.ptw[1].pmp[4].mask
invalidate io.ptw[1].pmp[4].addr
invalidate io.ptw[1].pmp[4].cfg.r
invalidate io.ptw[1].pmp[4].cfg.w
invalidate io.ptw[1].pmp[4].cfg.x
invalidate io.ptw[1].pmp[4].cfg.a
invalidate io.ptw[1].pmp[4].cfg.res
invalidate io.ptw[1].pmp[4].cfg.l
invalidate io.ptw[1].pmp[5].mask
invalidate io.ptw[1].pmp[5].addr
invalidate io.ptw[1].pmp[5].cfg.r
invalidate io.ptw[1].pmp[5].cfg.w
invalidate io.ptw[1].pmp[5].cfg.x
invalidate io.ptw[1].pmp[5].cfg.a
invalidate io.ptw[1].pmp[5].cfg.res
invalidate io.ptw[1].pmp[5].cfg.l
invalidate io.ptw[1].pmp[6].mask
invalidate io.ptw[1].pmp[6].addr
invalidate io.ptw[1].pmp[6].cfg.r
invalidate io.ptw[1].pmp[6].cfg.w
invalidate io.ptw[1].pmp[6].cfg.x
invalidate io.ptw[1].pmp[6].cfg.a
invalidate io.ptw[1].pmp[6].cfg.res
invalidate io.ptw[1].pmp[6].cfg.l
invalidate io.ptw[1].pmp[7].mask
invalidate io.ptw[1].pmp[7].addr
invalidate io.ptw[1].pmp[7].cfg.r
invalidate io.ptw[1].pmp[7].cfg.w
invalidate io.ptw[1].pmp[7].cfg.x
invalidate io.ptw[1].pmp[7].cfg.a
invalidate io.ptw[1].pmp[7].cfg.res
invalidate io.ptw[1].pmp[7].cfg.l
invalidate io.ptw[1].gstatus.uie
invalidate io.ptw[1].gstatus.sie
invalidate io.ptw[1].gstatus.hie
invalidate io.ptw[1].gstatus.mie
invalidate io.ptw[1].gstatus.upie
invalidate io.ptw[1].gstatus.spie
invalidate io.ptw[1].gstatus.ube
invalidate io.ptw[1].gstatus.mpie
invalidate io.ptw[1].gstatus.spp
invalidate io.ptw[1].gstatus.vs
invalidate io.ptw[1].gstatus.mpp
invalidate io.ptw[1].gstatus.fs
invalidate io.ptw[1].gstatus.xs
invalidate io.ptw[1].gstatus.mprv
invalidate io.ptw[1].gstatus.sum
invalidate io.ptw[1].gstatus.mxr
invalidate io.ptw[1].gstatus.tvm
invalidate io.ptw[1].gstatus.tw
invalidate io.ptw[1].gstatus.tsr
invalidate io.ptw[1].gstatus.zero1
invalidate io.ptw[1].gstatus.sd_rv32
invalidate io.ptw[1].gstatus.uxl
invalidate io.ptw[1].gstatus.sxl
invalidate io.ptw[1].gstatus.sbe
invalidate io.ptw[1].gstatus.mbe
invalidate io.ptw[1].gstatus.gva
invalidate io.ptw[1].gstatus.mpv
invalidate io.ptw[1].gstatus.zero2
invalidate io.ptw[1].gstatus.sd
invalidate io.ptw[1].gstatus.v
invalidate io.ptw[1].gstatus.prv
invalidate io.ptw[1].gstatus.dv
invalidate io.ptw[1].gstatus.dprv
invalidate io.ptw[1].gstatus.isa
invalidate io.ptw[1].gstatus.wfi
invalidate io.ptw[1].gstatus.cease
invalidate io.ptw[1].gstatus.debug
invalidate io.ptw[1].hstatus.zero1
invalidate io.ptw[1].hstatus.vsbe
invalidate io.ptw[1].hstatus.gva
invalidate io.ptw[1].hstatus.spv
invalidate io.ptw[1].hstatus.spvp
invalidate io.ptw[1].hstatus.hu
invalidate io.ptw[1].hstatus.zero2
invalidate io.ptw[1].hstatus.vgein
invalidate io.ptw[1].hstatus.zero3
invalidate io.ptw[1].hstatus.vtvm
invalidate io.ptw[1].hstatus.vtw
invalidate io.ptw[1].hstatus.vtsr
invalidate io.ptw[1].hstatus.zero5
invalidate io.ptw[1].hstatus.vsxl
invalidate io.ptw[1].hstatus.zero6
invalidate io.ptw[1].status.uie
invalidate io.ptw[1].status.sie
invalidate io.ptw[1].status.hie
invalidate io.ptw[1].status.mie
invalidate io.ptw[1].status.upie
invalidate io.ptw[1].status.spie
invalidate io.ptw[1].status.ube
invalidate io.ptw[1].status.mpie
invalidate io.ptw[1].status.spp
invalidate io.ptw[1].status.vs
invalidate io.ptw[1].status.mpp
invalidate io.ptw[1].status.fs
invalidate io.ptw[1].status.xs
invalidate io.ptw[1].status.mprv
invalidate io.ptw[1].status.sum
invalidate io.ptw[1].status.mxr
invalidate io.ptw[1].status.tvm
invalidate io.ptw[1].status.tw
invalidate io.ptw[1].status.tsr
invalidate io.ptw[1].status.zero1
invalidate io.ptw[1].status.sd_rv32
invalidate io.ptw[1].status.uxl
invalidate io.ptw[1].status.sxl
invalidate io.ptw[1].status.sbe
invalidate io.ptw[1].status.mbe
invalidate io.ptw[1].status.gva
invalidate io.ptw[1].status.mpv
invalidate io.ptw[1].status.zero2
invalidate io.ptw[1].status.sd
invalidate io.ptw[1].status.v
invalidate io.ptw[1].status.prv
invalidate io.ptw[1].status.dv
invalidate io.ptw[1].status.dprv
invalidate io.ptw[1].status.isa
invalidate io.ptw[1].status.wfi
invalidate io.ptw[1].status.cease
invalidate io.ptw[1].status.debug
invalidate io.ptw[1].vsatp.ppn
invalidate io.ptw[1].vsatp.asid
invalidate io.ptw[1].vsatp.mode
invalidate io.ptw[1].hgatp.ppn
invalidate io.ptw[1].hgatp.asid
invalidate io.ptw[1].hgatp.mode
invalidate io.ptw[1].ptbr.ppn
invalidate io.ptw[1].ptbr.asid
invalidate io.ptw[1].ptbr.mode
invalidate io.ptw[1].resp.bits.gpa_is_pte
invalidate io.ptw[1].resp.bits.gpa.bits
invalidate io.ptw[1].resp.bits.gpa.valid
invalidate io.ptw[1].resp.bits.homogeneous
invalidate io.ptw[1].resp.bits.fragmented_superpage
invalidate io.ptw[1].resp.bits.level
invalidate io.ptw[1].resp.bits.pte.v
invalidate io.ptw[1].resp.bits.pte.r
invalidate io.ptw[1].resp.bits.pte.w
invalidate io.ptw[1].resp.bits.pte.x
invalidate io.ptw[1].resp.bits.pte.u
invalidate io.ptw[1].resp.bits.pte.g
invalidate io.ptw[1].resp.bits.pte.a
invalidate io.ptw[1].resp.bits.pte.d
invalidate io.ptw[1].resp.bits.pte.reserved_for_software
invalidate io.ptw[1].resp.bits.pte.ppn
invalidate io.ptw[1].resp.bits.pte.reserved_for_future
invalidate io.ptw[1].resp.bits.hx
invalidate io.ptw[1].resp.bits.hw
invalidate io.ptw[1].resp.bits.hr
invalidate io.ptw[1].resp.bits.gf
invalidate io.ptw[1].resp.bits.pf
invalidate io.ptw[1].resp.bits.ae_final
invalidate io.ptw[1].resp.bits.ae_ptw
invalidate io.ptw[1].resp.valid
invalidate io.ptw[1].req.bits.bits.stage2
invalidate io.ptw[1].req.bits.bits.vstage1
invalidate io.ptw[1].req.bits.bits.need_gpa
invalidate io.ptw[1].req.bits.bits.addr
invalidate io.ptw[1].req.bits.valid
invalidate io.ptw[1].req.valid
invalidate io.ptw[1].req.ready
invalidate io.ptw[2].customCSRs.csrs[0].sdata
invalidate io.ptw[2].customCSRs.csrs[0].set
invalidate io.ptw[2].customCSRs.csrs[0].stall
invalidate io.ptw[2].customCSRs.csrs[0].value
invalidate io.ptw[2].customCSRs.csrs[0].wdata
invalidate io.ptw[2].customCSRs.csrs[0].wen
invalidate io.ptw[2].customCSRs.csrs[0].ren
invalidate io.ptw[2].customCSRs.csrs[1].sdata
invalidate io.ptw[2].customCSRs.csrs[1].set
invalidate io.ptw[2].customCSRs.csrs[1].stall
invalidate io.ptw[2].customCSRs.csrs[1].value
invalidate io.ptw[2].customCSRs.csrs[1].wdata
invalidate io.ptw[2].customCSRs.csrs[1].wen
invalidate io.ptw[2].customCSRs.csrs[1].ren
invalidate io.ptw[2].customCSRs.csrs[2].sdata
invalidate io.ptw[2].customCSRs.csrs[2].set
invalidate io.ptw[2].customCSRs.csrs[2].stall
invalidate io.ptw[2].customCSRs.csrs[2].value
invalidate io.ptw[2].customCSRs.csrs[2].wdata
invalidate io.ptw[2].customCSRs.csrs[2].wen
invalidate io.ptw[2].customCSRs.csrs[2].ren
invalidate io.ptw[2].customCSRs.csrs[3].sdata
invalidate io.ptw[2].customCSRs.csrs[3].set
invalidate io.ptw[2].customCSRs.csrs[3].stall
invalidate io.ptw[2].customCSRs.csrs[3].value
invalidate io.ptw[2].customCSRs.csrs[3].wdata
invalidate io.ptw[2].customCSRs.csrs[3].wen
invalidate io.ptw[2].customCSRs.csrs[3].ren
invalidate io.ptw[2].pmp[0].mask
invalidate io.ptw[2].pmp[0].addr
invalidate io.ptw[2].pmp[0].cfg.r
invalidate io.ptw[2].pmp[0].cfg.w
invalidate io.ptw[2].pmp[0].cfg.x
invalidate io.ptw[2].pmp[0].cfg.a
invalidate io.ptw[2].pmp[0].cfg.res
invalidate io.ptw[2].pmp[0].cfg.l
invalidate io.ptw[2].pmp[1].mask
invalidate io.ptw[2].pmp[1].addr
invalidate io.ptw[2].pmp[1].cfg.r
invalidate io.ptw[2].pmp[1].cfg.w
invalidate io.ptw[2].pmp[1].cfg.x
invalidate io.ptw[2].pmp[1].cfg.a
invalidate io.ptw[2].pmp[1].cfg.res
invalidate io.ptw[2].pmp[1].cfg.l
invalidate io.ptw[2].pmp[2].mask
invalidate io.ptw[2].pmp[2].addr
invalidate io.ptw[2].pmp[2].cfg.r
invalidate io.ptw[2].pmp[2].cfg.w
invalidate io.ptw[2].pmp[2].cfg.x
invalidate io.ptw[2].pmp[2].cfg.a
invalidate io.ptw[2].pmp[2].cfg.res
invalidate io.ptw[2].pmp[2].cfg.l
invalidate io.ptw[2].pmp[3].mask
invalidate io.ptw[2].pmp[3].addr
invalidate io.ptw[2].pmp[3].cfg.r
invalidate io.ptw[2].pmp[3].cfg.w
invalidate io.ptw[2].pmp[3].cfg.x
invalidate io.ptw[2].pmp[3].cfg.a
invalidate io.ptw[2].pmp[3].cfg.res
invalidate io.ptw[2].pmp[3].cfg.l
invalidate io.ptw[2].pmp[4].mask
invalidate io.ptw[2].pmp[4].addr
invalidate io.ptw[2].pmp[4].cfg.r
invalidate io.ptw[2].pmp[4].cfg.w
invalidate io.ptw[2].pmp[4].cfg.x
invalidate io.ptw[2].pmp[4].cfg.a
invalidate io.ptw[2].pmp[4].cfg.res
invalidate io.ptw[2].pmp[4].cfg.l
invalidate io.ptw[2].pmp[5].mask
invalidate io.ptw[2].pmp[5].addr
invalidate io.ptw[2].pmp[5].cfg.r
invalidate io.ptw[2].pmp[5].cfg.w
invalidate io.ptw[2].pmp[5].cfg.x
invalidate io.ptw[2].pmp[5].cfg.a
invalidate io.ptw[2].pmp[5].cfg.res
invalidate io.ptw[2].pmp[5].cfg.l
invalidate io.ptw[2].pmp[6].mask
invalidate io.ptw[2].pmp[6].addr
invalidate io.ptw[2].pmp[6].cfg.r
invalidate io.ptw[2].pmp[6].cfg.w
invalidate io.ptw[2].pmp[6].cfg.x
invalidate io.ptw[2].pmp[6].cfg.a
invalidate io.ptw[2].pmp[6].cfg.res
invalidate io.ptw[2].pmp[6].cfg.l
invalidate io.ptw[2].pmp[7].mask
invalidate io.ptw[2].pmp[7].addr
invalidate io.ptw[2].pmp[7].cfg.r
invalidate io.ptw[2].pmp[7].cfg.w
invalidate io.ptw[2].pmp[7].cfg.x
invalidate io.ptw[2].pmp[7].cfg.a
invalidate io.ptw[2].pmp[7].cfg.res
invalidate io.ptw[2].pmp[7].cfg.l
invalidate io.ptw[2].gstatus.uie
invalidate io.ptw[2].gstatus.sie
invalidate io.ptw[2].gstatus.hie
invalidate io.ptw[2].gstatus.mie
invalidate io.ptw[2].gstatus.upie
invalidate io.ptw[2].gstatus.spie
invalidate io.ptw[2].gstatus.ube
invalidate io.ptw[2].gstatus.mpie
invalidate io.ptw[2].gstatus.spp
invalidate io.ptw[2].gstatus.vs
invalidate io.ptw[2].gstatus.mpp
invalidate io.ptw[2].gstatus.fs
invalidate io.ptw[2].gstatus.xs
invalidate io.ptw[2].gstatus.mprv
invalidate io.ptw[2].gstatus.sum
invalidate io.ptw[2].gstatus.mxr
invalidate io.ptw[2].gstatus.tvm
invalidate io.ptw[2].gstatus.tw
invalidate io.ptw[2].gstatus.tsr
invalidate io.ptw[2].gstatus.zero1
invalidate io.ptw[2].gstatus.sd_rv32
invalidate io.ptw[2].gstatus.uxl
invalidate io.ptw[2].gstatus.sxl
invalidate io.ptw[2].gstatus.sbe
invalidate io.ptw[2].gstatus.mbe
invalidate io.ptw[2].gstatus.gva
invalidate io.ptw[2].gstatus.mpv
invalidate io.ptw[2].gstatus.zero2
invalidate io.ptw[2].gstatus.sd
invalidate io.ptw[2].gstatus.v
invalidate io.ptw[2].gstatus.prv
invalidate io.ptw[2].gstatus.dv
invalidate io.ptw[2].gstatus.dprv
invalidate io.ptw[2].gstatus.isa
invalidate io.ptw[2].gstatus.wfi
invalidate io.ptw[2].gstatus.cease
invalidate io.ptw[2].gstatus.debug
invalidate io.ptw[2].hstatus.zero1
invalidate io.ptw[2].hstatus.vsbe
invalidate io.ptw[2].hstatus.gva
invalidate io.ptw[2].hstatus.spv
invalidate io.ptw[2].hstatus.spvp
invalidate io.ptw[2].hstatus.hu
invalidate io.ptw[2].hstatus.zero2
invalidate io.ptw[2].hstatus.vgein
invalidate io.ptw[2].hstatus.zero3
invalidate io.ptw[2].hstatus.vtvm
invalidate io.ptw[2].hstatus.vtw
invalidate io.ptw[2].hstatus.vtsr
invalidate io.ptw[2].hstatus.zero5
invalidate io.ptw[2].hstatus.vsxl
invalidate io.ptw[2].hstatus.zero6
invalidate io.ptw[2].status.uie
invalidate io.ptw[2].status.sie
invalidate io.ptw[2].status.hie
invalidate io.ptw[2].status.mie
invalidate io.ptw[2].status.upie
invalidate io.ptw[2].status.spie
invalidate io.ptw[2].status.ube
invalidate io.ptw[2].status.mpie
invalidate io.ptw[2].status.spp
invalidate io.ptw[2].status.vs
invalidate io.ptw[2].status.mpp
invalidate io.ptw[2].status.fs
invalidate io.ptw[2].status.xs
invalidate io.ptw[2].status.mprv
invalidate io.ptw[2].status.sum
invalidate io.ptw[2].status.mxr
invalidate io.ptw[2].status.tvm
invalidate io.ptw[2].status.tw
invalidate io.ptw[2].status.tsr
invalidate io.ptw[2].status.zero1
invalidate io.ptw[2].status.sd_rv32
invalidate io.ptw[2].status.uxl
invalidate io.ptw[2].status.sxl
invalidate io.ptw[2].status.sbe
invalidate io.ptw[2].status.mbe
invalidate io.ptw[2].status.gva
invalidate io.ptw[2].status.mpv
invalidate io.ptw[2].status.zero2
invalidate io.ptw[2].status.sd
invalidate io.ptw[2].status.v
invalidate io.ptw[2].status.prv
invalidate io.ptw[2].status.dv
invalidate io.ptw[2].status.dprv
invalidate io.ptw[2].status.isa
invalidate io.ptw[2].status.wfi
invalidate io.ptw[2].status.cease
invalidate io.ptw[2].status.debug
invalidate io.ptw[2].vsatp.ppn
invalidate io.ptw[2].vsatp.asid
invalidate io.ptw[2].vsatp.mode
invalidate io.ptw[2].hgatp.ppn
invalidate io.ptw[2].hgatp.asid
invalidate io.ptw[2].hgatp.mode
invalidate io.ptw[2].ptbr.ppn
invalidate io.ptw[2].ptbr.asid
invalidate io.ptw[2].ptbr.mode
invalidate io.ptw[2].resp.bits.gpa_is_pte
invalidate io.ptw[2].resp.bits.gpa.bits
invalidate io.ptw[2].resp.bits.gpa.valid
invalidate io.ptw[2].resp.bits.homogeneous
invalidate io.ptw[2].resp.bits.fragmented_superpage
invalidate io.ptw[2].resp.bits.level
invalidate io.ptw[2].resp.bits.pte.v
invalidate io.ptw[2].resp.bits.pte.r
invalidate io.ptw[2].resp.bits.pte.w
invalidate io.ptw[2].resp.bits.pte.x
invalidate io.ptw[2].resp.bits.pte.u
invalidate io.ptw[2].resp.bits.pte.g
invalidate io.ptw[2].resp.bits.pte.a
invalidate io.ptw[2].resp.bits.pte.d
invalidate io.ptw[2].resp.bits.pte.reserved_for_software
invalidate io.ptw[2].resp.bits.pte.ppn
invalidate io.ptw[2].resp.bits.pte.reserved_for_future
invalidate io.ptw[2].resp.bits.hx
invalidate io.ptw[2].resp.bits.hw
invalidate io.ptw[2].resp.bits.hr
invalidate io.ptw[2].resp.bits.gf
invalidate io.ptw[2].resp.bits.pf
invalidate io.ptw[2].resp.bits.ae_final
invalidate io.ptw[2].resp.bits.ae_ptw
invalidate io.ptw[2].resp.valid
invalidate io.ptw[2].req.bits.bits.stage2
invalidate io.ptw[2].req.bits.bits.vstage1
invalidate io.ptw[2].req.bits.bits.need_gpa
invalidate io.ptw[2].req.bits.bits.addr
invalidate io.ptw[2].req.bits.valid
invalidate io.ptw[2].req.valid
invalidate io.ptw[2].req.ready
invalidate io.ptw[3].customCSRs.csrs[0].sdata
invalidate io.ptw[3].customCSRs.csrs[0].set
invalidate io.ptw[3].customCSRs.csrs[0].stall
invalidate io.ptw[3].customCSRs.csrs[0].value
invalidate io.ptw[3].customCSRs.csrs[0].wdata
invalidate io.ptw[3].customCSRs.csrs[0].wen
invalidate io.ptw[3].customCSRs.csrs[0].ren
invalidate io.ptw[3].customCSRs.csrs[1].sdata
invalidate io.ptw[3].customCSRs.csrs[1].set
invalidate io.ptw[3].customCSRs.csrs[1].stall
invalidate io.ptw[3].customCSRs.csrs[1].value
invalidate io.ptw[3].customCSRs.csrs[1].wdata
invalidate io.ptw[3].customCSRs.csrs[1].wen
invalidate io.ptw[3].customCSRs.csrs[1].ren
invalidate io.ptw[3].customCSRs.csrs[2].sdata
invalidate io.ptw[3].customCSRs.csrs[2].set
invalidate io.ptw[3].customCSRs.csrs[2].stall
invalidate io.ptw[3].customCSRs.csrs[2].value
invalidate io.ptw[3].customCSRs.csrs[2].wdata
invalidate io.ptw[3].customCSRs.csrs[2].wen
invalidate io.ptw[3].customCSRs.csrs[2].ren
invalidate io.ptw[3].customCSRs.csrs[3].sdata
invalidate io.ptw[3].customCSRs.csrs[3].set
invalidate io.ptw[3].customCSRs.csrs[3].stall
invalidate io.ptw[3].customCSRs.csrs[3].value
invalidate io.ptw[3].customCSRs.csrs[3].wdata
invalidate io.ptw[3].customCSRs.csrs[3].wen
invalidate io.ptw[3].customCSRs.csrs[3].ren
invalidate io.ptw[3].pmp[0].mask
invalidate io.ptw[3].pmp[0].addr
invalidate io.ptw[3].pmp[0].cfg.r
invalidate io.ptw[3].pmp[0].cfg.w
invalidate io.ptw[3].pmp[0].cfg.x
invalidate io.ptw[3].pmp[0].cfg.a
invalidate io.ptw[3].pmp[0].cfg.res
invalidate io.ptw[3].pmp[0].cfg.l
invalidate io.ptw[3].pmp[1].mask
invalidate io.ptw[3].pmp[1].addr
invalidate io.ptw[3].pmp[1].cfg.r
invalidate io.ptw[3].pmp[1].cfg.w
invalidate io.ptw[3].pmp[1].cfg.x
invalidate io.ptw[3].pmp[1].cfg.a
invalidate io.ptw[3].pmp[1].cfg.res
invalidate io.ptw[3].pmp[1].cfg.l
invalidate io.ptw[3].pmp[2].mask
invalidate io.ptw[3].pmp[2].addr
invalidate io.ptw[3].pmp[2].cfg.r
invalidate io.ptw[3].pmp[2].cfg.w
invalidate io.ptw[3].pmp[2].cfg.x
invalidate io.ptw[3].pmp[2].cfg.a
invalidate io.ptw[3].pmp[2].cfg.res
invalidate io.ptw[3].pmp[2].cfg.l
invalidate io.ptw[3].pmp[3].mask
invalidate io.ptw[3].pmp[3].addr
invalidate io.ptw[3].pmp[3].cfg.r
invalidate io.ptw[3].pmp[3].cfg.w
invalidate io.ptw[3].pmp[3].cfg.x
invalidate io.ptw[3].pmp[3].cfg.a
invalidate io.ptw[3].pmp[3].cfg.res
invalidate io.ptw[3].pmp[3].cfg.l
invalidate io.ptw[3].pmp[4].mask
invalidate io.ptw[3].pmp[4].addr
invalidate io.ptw[3].pmp[4].cfg.r
invalidate io.ptw[3].pmp[4].cfg.w
invalidate io.ptw[3].pmp[4].cfg.x
invalidate io.ptw[3].pmp[4].cfg.a
invalidate io.ptw[3].pmp[4].cfg.res
invalidate io.ptw[3].pmp[4].cfg.l
invalidate io.ptw[3].pmp[5].mask
invalidate io.ptw[3].pmp[5].addr
invalidate io.ptw[3].pmp[5].cfg.r
invalidate io.ptw[3].pmp[5].cfg.w
invalidate io.ptw[3].pmp[5].cfg.x
invalidate io.ptw[3].pmp[5].cfg.a
invalidate io.ptw[3].pmp[5].cfg.res
invalidate io.ptw[3].pmp[5].cfg.l
invalidate io.ptw[3].pmp[6].mask
invalidate io.ptw[3].pmp[6].addr
invalidate io.ptw[3].pmp[6].cfg.r
invalidate io.ptw[3].pmp[6].cfg.w
invalidate io.ptw[3].pmp[6].cfg.x
invalidate io.ptw[3].pmp[6].cfg.a
invalidate io.ptw[3].pmp[6].cfg.res
invalidate io.ptw[3].pmp[6].cfg.l
invalidate io.ptw[3].pmp[7].mask
invalidate io.ptw[3].pmp[7].addr
invalidate io.ptw[3].pmp[7].cfg.r
invalidate io.ptw[3].pmp[7].cfg.w
invalidate io.ptw[3].pmp[7].cfg.x
invalidate io.ptw[3].pmp[7].cfg.a
invalidate io.ptw[3].pmp[7].cfg.res
invalidate io.ptw[3].pmp[7].cfg.l
invalidate io.ptw[3].gstatus.uie
invalidate io.ptw[3].gstatus.sie
invalidate io.ptw[3].gstatus.hie
invalidate io.ptw[3].gstatus.mie
invalidate io.ptw[3].gstatus.upie
invalidate io.ptw[3].gstatus.spie
invalidate io.ptw[3].gstatus.ube
invalidate io.ptw[3].gstatus.mpie
invalidate io.ptw[3].gstatus.spp
invalidate io.ptw[3].gstatus.vs
invalidate io.ptw[3].gstatus.mpp
invalidate io.ptw[3].gstatus.fs
invalidate io.ptw[3].gstatus.xs
invalidate io.ptw[3].gstatus.mprv
invalidate io.ptw[3].gstatus.sum
invalidate io.ptw[3].gstatus.mxr
invalidate io.ptw[3].gstatus.tvm
invalidate io.ptw[3].gstatus.tw
invalidate io.ptw[3].gstatus.tsr
invalidate io.ptw[3].gstatus.zero1
invalidate io.ptw[3].gstatus.sd_rv32
invalidate io.ptw[3].gstatus.uxl
invalidate io.ptw[3].gstatus.sxl
invalidate io.ptw[3].gstatus.sbe
invalidate io.ptw[3].gstatus.mbe
invalidate io.ptw[3].gstatus.gva
invalidate io.ptw[3].gstatus.mpv
invalidate io.ptw[3].gstatus.zero2
invalidate io.ptw[3].gstatus.sd
invalidate io.ptw[3].gstatus.v
invalidate io.ptw[3].gstatus.prv
invalidate io.ptw[3].gstatus.dv
invalidate io.ptw[3].gstatus.dprv
invalidate io.ptw[3].gstatus.isa
invalidate io.ptw[3].gstatus.wfi
invalidate io.ptw[3].gstatus.cease
invalidate io.ptw[3].gstatus.debug
invalidate io.ptw[3].hstatus.zero1
invalidate io.ptw[3].hstatus.vsbe
invalidate io.ptw[3].hstatus.gva
invalidate io.ptw[3].hstatus.spv
invalidate io.ptw[3].hstatus.spvp
invalidate io.ptw[3].hstatus.hu
invalidate io.ptw[3].hstatus.zero2
invalidate io.ptw[3].hstatus.vgein
invalidate io.ptw[3].hstatus.zero3
invalidate io.ptw[3].hstatus.vtvm
invalidate io.ptw[3].hstatus.vtw
invalidate io.ptw[3].hstatus.vtsr
invalidate io.ptw[3].hstatus.zero5
invalidate io.ptw[3].hstatus.vsxl
invalidate io.ptw[3].hstatus.zero6
invalidate io.ptw[3].status.uie
invalidate io.ptw[3].status.sie
invalidate io.ptw[3].status.hie
invalidate io.ptw[3].status.mie
invalidate io.ptw[3].status.upie
invalidate io.ptw[3].status.spie
invalidate io.ptw[3].status.ube
invalidate io.ptw[3].status.mpie
invalidate io.ptw[3].status.spp
invalidate io.ptw[3].status.vs
invalidate io.ptw[3].status.mpp
invalidate io.ptw[3].status.fs
invalidate io.ptw[3].status.xs
invalidate io.ptw[3].status.mprv
invalidate io.ptw[3].status.sum
invalidate io.ptw[3].status.mxr
invalidate io.ptw[3].status.tvm
invalidate io.ptw[3].status.tw
invalidate io.ptw[3].status.tsr
invalidate io.ptw[3].status.zero1
invalidate io.ptw[3].status.sd_rv32
invalidate io.ptw[3].status.uxl
invalidate io.ptw[3].status.sxl
invalidate io.ptw[3].status.sbe
invalidate io.ptw[3].status.mbe
invalidate io.ptw[3].status.gva
invalidate io.ptw[3].status.mpv
invalidate io.ptw[3].status.zero2
invalidate io.ptw[3].status.sd
invalidate io.ptw[3].status.v
invalidate io.ptw[3].status.prv
invalidate io.ptw[3].status.dv
invalidate io.ptw[3].status.dprv
invalidate io.ptw[3].status.isa
invalidate io.ptw[3].status.wfi
invalidate io.ptw[3].status.cease
invalidate io.ptw[3].status.debug
invalidate io.ptw[3].vsatp.ppn
invalidate io.ptw[3].vsatp.asid
invalidate io.ptw[3].vsatp.mode
invalidate io.ptw[3].hgatp.ppn
invalidate io.ptw[3].hgatp.asid
invalidate io.ptw[3].hgatp.mode
invalidate io.ptw[3].ptbr.ppn
invalidate io.ptw[3].ptbr.asid
invalidate io.ptw[3].ptbr.mode
invalidate io.ptw[3].resp.bits.gpa_is_pte
invalidate io.ptw[3].resp.bits.gpa.bits
invalidate io.ptw[3].resp.bits.gpa.valid
invalidate io.ptw[3].resp.bits.homogeneous
invalidate io.ptw[3].resp.bits.fragmented_superpage
invalidate io.ptw[3].resp.bits.level
invalidate io.ptw[3].resp.bits.pte.v
invalidate io.ptw[3].resp.bits.pte.r
invalidate io.ptw[3].resp.bits.pte.w
invalidate io.ptw[3].resp.bits.pte.x
invalidate io.ptw[3].resp.bits.pte.u
invalidate io.ptw[3].resp.bits.pte.g
invalidate io.ptw[3].resp.bits.pte.a
invalidate io.ptw[3].resp.bits.pte.d
invalidate io.ptw[3].resp.bits.pte.reserved_for_software
invalidate io.ptw[3].resp.bits.pte.ppn
invalidate io.ptw[3].resp.bits.pte.reserved_for_future
invalidate io.ptw[3].resp.bits.hx
invalidate io.ptw[3].resp.bits.hw
invalidate io.ptw[3].resp.bits.hr
invalidate io.ptw[3].resp.bits.gf
invalidate io.ptw[3].resp.bits.pf
invalidate io.ptw[3].resp.bits.ae_final
invalidate io.ptw[3].resp.bits.ae_ptw
invalidate io.ptw[3].resp.valid
invalidate io.ptw[3].req.bits.bits.stage2
invalidate io.ptw[3].req.bits.bits.vstage1
invalidate io.ptw[3].req.bits.bits.need_gpa
invalidate io.ptw[3].req.bits.bits.addr
invalidate io.ptw[3].req.bits.valid
invalidate io.ptw[3].req.valid
invalidate io.ptw[3].req.ready
invalidate io.ptw[4].customCSRs.csrs[0].sdata
invalidate io.ptw[4].customCSRs.csrs[0].set
invalidate io.ptw[4].customCSRs.csrs[0].stall
invalidate io.ptw[4].customCSRs.csrs[0].value
invalidate io.ptw[4].customCSRs.csrs[0].wdata
invalidate io.ptw[4].customCSRs.csrs[0].wen
invalidate io.ptw[4].customCSRs.csrs[0].ren
invalidate io.ptw[4].customCSRs.csrs[1].sdata
invalidate io.ptw[4].customCSRs.csrs[1].set
invalidate io.ptw[4].customCSRs.csrs[1].stall
invalidate io.ptw[4].customCSRs.csrs[1].value
invalidate io.ptw[4].customCSRs.csrs[1].wdata
invalidate io.ptw[4].customCSRs.csrs[1].wen
invalidate io.ptw[4].customCSRs.csrs[1].ren
invalidate io.ptw[4].customCSRs.csrs[2].sdata
invalidate io.ptw[4].customCSRs.csrs[2].set
invalidate io.ptw[4].customCSRs.csrs[2].stall
invalidate io.ptw[4].customCSRs.csrs[2].value
invalidate io.ptw[4].customCSRs.csrs[2].wdata
invalidate io.ptw[4].customCSRs.csrs[2].wen
invalidate io.ptw[4].customCSRs.csrs[2].ren
invalidate io.ptw[4].customCSRs.csrs[3].sdata
invalidate io.ptw[4].customCSRs.csrs[3].set
invalidate io.ptw[4].customCSRs.csrs[3].stall
invalidate io.ptw[4].customCSRs.csrs[3].value
invalidate io.ptw[4].customCSRs.csrs[3].wdata
invalidate io.ptw[4].customCSRs.csrs[3].wen
invalidate io.ptw[4].customCSRs.csrs[3].ren
invalidate io.ptw[4].pmp[0].mask
invalidate io.ptw[4].pmp[0].addr
invalidate io.ptw[4].pmp[0].cfg.r
invalidate io.ptw[4].pmp[0].cfg.w
invalidate io.ptw[4].pmp[0].cfg.x
invalidate io.ptw[4].pmp[0].cfg.a
invalidate io.ptw[4].pmp[0].cfg.res
invalidate io.ptw[4].pmp[0].cfg.l
invalidate io.ptw[4].pmp[1].mask
invalidate io.ptw[4].pmp[1].addr
invalidate io.ptw[4].pmp[1].cfg.r
invalidate io.ptw[4].pmp[1].cfg.w
invalidate io.ptw[4].pmp[1].cfg.x
invalidate io.ptw[4].pmp[1].cfg.a
invalidate io.ptw[4].pmp[1].cfg.res
invalidate io.ptw[4].pmp[1].cfg.l
invalidate io.ptw[4].pmp[2].mask
invalidate io.ptw[4].pmp[2].addr
invalidate io.ptw[4].pmp[2].cfg.r
invalidate io.ptw[4].pmp[2].cfg.w
invalidate io.ptw[4].pmp[2].cfg.x
invalidate io.ptw[4].pmp[2].cfg.a
invalidate io.ptw[4].pmp[2].cfg.res
invalidate io.ptw[4].pmp[2].cfg.l
invalidate io.ptw[4].pmp[3].mask
invalidate io.ptw[4].pmp[3].addr
invalidate io.ptw[4].pmp[3].cfg.r
invalidate io.ptw[4].pmp[3].cfg.w
invalidate io.ptw[4].pmp[3].cfg.x
invalidate io.ptw[4].pmp[3].cfg.a
invalidate io.ptw[4].pmp[3].cfg.res
invalidate io.ptw[4].pmp[3].cfg.l
invalidate io.ptw[4].pmp[4].mask
invalidate io.ptw[4].pmp[4].addr
invalidate io.ptw[4].pmp[4].cfg.r
invalidate io.ptw[4].pmp[4].cfg.w
invalidate io.ptw[4].pmp[4].cfg.x
invalidate io.ptw[4].pmp[4].cfg.a
invalidate io.ptw[4].pmp[4].cfg.res
invalidate io.ptw[4].pmp[4].cfg.l
invalidate io.ptw[4].pmp[5].mask
invalidate io.ptw[4].pmp[5].addr
invalidate io.ptw[4].pmp[5].cfg.r
invalidate io.ptw[4].pmp[5].cfg.w
invalidate io.ptw[4].pmp[5].cfg.x
invalidate io.ptw[4].pmp[5].cfg.a
invalidate io.ptw[4].pmp[5].cfg.res
invalidate io.ptw[4].pmp[5].cfg.l
invalidate io.ptw[4].pmp[6].mask
invalidate io.ptw[4].pmp[6].addr
invalidate io.ptw[4].pmp[6].cfg.r
invalidate io.ptw[4].pmp[6].cfg.w
invalidate io.ptw[4].pmp[6].cfg.x
invalidate io.ptw[4].pmp[6].cfg.a
invalidate io.ptw[4].pmp[6].cfg.res
invalidate io.ptw[4].pmp[6].cfg.l
invalidate io.ptw[4].pmp[7].mask
invalidate io.ptw[4].pmp[7].addr
invalidate io.ptw[4].pmp[7].cfg.r
invalidate io.ptw[4].pmp[7].cfg.w
invalidate io.ptw[4].pmp[7].cfg.x
invalidate io.ptw[4].pmp[7].cfg.a
invalidate io.ptw[4].pmp[7].cfg.res
invalidate io.ptw[4].pmp[7].cfg.l
invalidate io.ptw[4].gstatus.uie
invalidate io.ptw[4].gstatus.sie
invalidate io.ptw[4].gstatus.hie
invalidate io.ptw[4].gstatus.mie
invalidate io.ptw[4].gstatus.upie
invalidate io.ptw[4].gstatus.spie
invalidate io.ptw[4].gstatus.ube
invalidate io.ptw[4].gstatus.mpie
invalidate io.ptw[4].gstatus.spp
invalidate io.ptw[4].gstatus.vs
invalidate io.ptw[4].gstatus.mpp
invalidate io.ptw[4].gstatus.fs
invalidate io.ptw[4].gstatus.xs
invalidate io.ptw[4].gstatus.mprv
invalidate io.ptw[4].gstatus.sum
invalidate io.ptw[4].gstatus.mxr
invalidate io.ptw[4].gstatus.tvm
invalidate io.ptw[4].gstatus.tw
invalidate io.ptw[4].gstatus.tsr
invalidate io.ptw[4].gstatus.zero1
invalidate io.ptw[4].gstatus.sd_rv32
invalidate io.ptw[4].gstatus.uxl
invalidate io.ptw[4].gstatus.sxl
invalidate io.ptw[4].gstatus.sbe
invalidate io.ptw[4].gstatus.mbe
invalidate io.ptw[4].gstatus.gva
invalidate io.ptw[4].gstatus.mpv
invalidate io.ptw[4].gstatus.zero2
invalidate io.ptw[4].gstatus.sd
invalidate io.ptw[4].gstatus.v
invalidate io.ptw[4].gstatus.prv
invalidate io.ptw[4].gstatus.dv
invalidate io.ptw[4].gstatus.dprv
invalidate io.ptw[4].gstatus.isa
invalidate io.ptw[4].gstatus.wfi
invalidate io.ptw[4].gstatus.cease
invalidate io.ptw[4].gstatus.debug
invalidate io.ptw[4].hstatus.zero1
invalidate io.ptw[4].hstatus.vsbe
invalidate io.ptw[4].hstatus.gva
invalidate io.ptw[4].hstatus.spv
invalidate io.ptw[4].hstatus.spvp
invalidate io.ptw[4].hstatus.hu
invalidate io.ptw[4].hstatus.zero2
invalidate io.ptw[4].hstatus.vgein
invalidate io.ptw[4].hstatus.zero3
invalidate io.ptw[4].hstatus.vtvm
invalidate io.ptw[4].hstatus.vtw
invalidate io.ptw[4].hstatus.vtsr
invalidate io.ptw[4].hstatus.zero5
invalidate io.ptw[4].hstatus.vsxl
invalidate io.ptw[4].hstatus.zero6
invalidate io.ptw[4].status.uie
invalidate io.ptw[4].status.sie
invalidate io.ptw[4].status.hie
invalidate io.ptw[4].status.mie
invalidate io.ptw[4].status.upie
invalidate io.ptw[4].status.spie
invalidate io.ptw[4].status.ube
invalidate io.ptw[4].status.mpie
invalidate io.ptw[4].status.spp
invalidate io.ptw[4].status.vs
invalidate io.ptw[4].status.mpp
invalidate io.ptw[4].status.fs
invalidate io.ptw[4].status.xs
invalidate io.ptw[4].status.mprv
invalidate io.ptw[4].status.sum
invalidate io.ptw[4].status.mxr
invalidate io.ptw[4].status.tvm
invalidate io.ptw[4].status.tw
invalidate io.ptw[4].status.tsr
invalidate io.ptw[4].status.zero1
invalidate io.ptw[4].status.sd_rv32
invalidate io.ptw[4].status.uxl
invalidate io.ptw[4].status.sxl
invalidate io.ptw[4].status.sbe
invalidate io.ptw[4].status.mbe
invalidate io.ptw[4].status.gva
invalidate io.ptw[4].status.mpv
invalidate io.ptw[4].status.zero2
invalidate io.ptw[4].status.sd
invalidate io.ptw[4].status.v
invalidate io.ptw[4].status.prv
invalidate io.ptw[4].status.dv
invalidate io.ptw[4].status.dprv
invalidate io.ptw[4].status.isa
invalidate io.ptw[4].status.wfi
invalidate io.ptw[4].status.cease
invalidate io.ptw[4].status.debug
invalidate io.ptw[4].vsatp.ppn
invalidate io.ptw[4].vsatp.asid
invalidate io.ptw[4].vsatp.mode
invalidate io.ptw[4].hgatp.ppn
invalidate io.ptw[4].hgatp.asid
invalidate io.ptw[4].hgatp.mode
invalidate io.ptw[4].ptbr.ppn
invalidate io.ptw[4].ptbr.asid
invalidate io.ptw[4].ptbr.mode
invalidate io.ptw[4].resp.bits.gpa_is_pte
invalidate io.ptw[4].resp.bits.gpa.bits
invalidate io.ptw[4].resp.bits.gpa.valid
invalidate io.ptw[4].resp.bits.homogeneous
invalidate io.ptw[4].resp.bits.fragmented_superpage
invalidate io.ptw[4].resp.bits.level
invalidate io.ptw[4].resp.bits.pte.v
invalidate io.ptw[4].resp.bits.pte.r
invalidate io.ptw[4].resp.bits.pte.w
invalidate io.ptw[4].resp.bits.pte.x
invalidate io.ptw[4].resp.bits.pte.u
invalidate io.ptw[4].resp.bits.pte.g
invalidate io.ptw[4].resp.bits.pte.a
invalidate io.ptw[4].resp.bits.pte.d
invalidate io.ptw[4].resp.bits.pte.reserved_for_software
invalidate io.ptw[4].resp.bits.pte.ppn
invalidate io.ptw[4].resp.bits.pte.reserved_for_future
invalidate io.ptw[4].resp.bits.hx
invalidate io.ptw[4].resp.bits.hw
invalidate io.ptw[4].resp.bits.hr
invalidate io.ptw[4].resp.bits.gf
invalidate io.ptw[4].resp.bits.pf
invalidate io.ptw[4].resp.bits.ae_final
invalidate io.ptw[4].resp.bits.ae_ptw
invalidate io.ptw[4].resp.valid
invalidate io.ptw[4].req.bits.bits.stage2
invalidate io.ptw[4].req.bits.bits.vstage1
invalidate io.ptw[4].req.bits.bits.need_gpa
invalidate io.ptw[4].req.bits.bits.addr
invalidate io.ptw[4].req.bits.valid
invalidate io.ptw[4].req.valid
invalidate io.ptw[4].req.ready
invalidate io.ptw[5].customCSRs.csrs[0].sdata
invalidate io.ptw[5].customCSRs.csrs[0].set
invalidate io.ptw[5].customCSRs.csrs[0].stall
invalidate io.ptw[5].customCSRs.csrs[0].value
invalidate io.ptw[5].customCSRs.csrs[0].wdata
invalidate io.ptw[5].customCSRs.csrs[0].wen
invalidate io.ptw[5].customCSRs.csrs[0].ren
invalidate io.ptw[5].customCSRs.csrs[1].sdata
invalidate io.ptw[5].customCSRs.csrs[1].set
invalidate io.ptw[5].customCSRs.csrs[1].stall
invalidate io.ptw[5].customCSRs.csrs[1].value
invalidate io.ptw[5].customCSRs.csrs[1].wdata
invalidate io.ptw[5].customCSRs.csrs[1].wen
invalidate io.ptw[5].customCSRs.csrs[1].ren
invalidate io.ptw[5].customCSRs.csrs[2].sdata
invalidate io.ptw[5].customCSRs.csrs[2].set
invalidate io.ptw[5].customCSRs.csrs[2].stall
invalidate io.ptw[5].customCSRs.csrs[2].value
invalidate io.ptw[5].customCSRs.csrs[2].wdata
invalidate io.ptw[5].customCSRs.csrs[2].wen
invalidate io.ptw[5].customCSRs.csrs[2].ren
invalidate io.ptw[5].customCSRs.csrs[3].sdata
invalidate io.ptw[5].customCSRs.csrs[3].set
invalidate io.ptw[5].customCSRs.csrs[3].stall
invalidate io.ptw[5].customCSRs.csrs[3].value
invalidate io.ptw[5].customCSRs.csrs[3].wdata
invalidate io.ptw[5].customCSRs.csrs[3].wen
invalidate io.ptw[5].customCSRs.csrs[3].ren
invalidate io.ptw[5].pmp[0].mask
invalidate io.ptw[5].pmp[0].addr
invalidate io.ptw[5].pmp[0].cfg.r
invalidate io.ptw[5].pmp[0].cfg.w
invalidate io.ptw[5].pmp[0].cfg.x
invalidate io.ptw[5].pmp[0].cfg.a
invalidate io.ptw[5].pmp[0].cfg.res
invalidate io.ptw[5].pmp[0].cfg.l
invalidate io.ptw[5].pmp[1].mask
invalidate io.ptw[5].pmp[1].addr
invalidate io.ptw[5].pmp[1].cfg.r
invalidate io.ptw[5].pmp[1].cfg.w
invalidate io.ptw[5].pmp[1].cfg.x
invalidate io.ptw[5].pmp[1].cfg.a
invalidate io.ptw[5].pmp[1].cfg.res
invalidate io.ptw[5].pmp[1].cfg.l
invalidate io.ptw[5].pmp[2].mask
invalidate io.ptw[5].pmp[2].addr
invalidate io.ptw[5].pmp[2].cfg.r
invalidate io.ptw[5].pmp[2].cfg.w
invalidate io.ptw[5].pmp[2].cfg.x
invalidate io.ptw[5].pmp[2].cfg.a
invalidate io.ptw[5].pmp[2].cfg.res
invalidate io.ptw[5].pmp[2].cfg.l
invalidate io.ptw[5].pmp[3].mask
invalidate io.ptw[5].pmp[3].addr
invalidate io.ptw[5].pmp[3].cfg.r
invalidate io.ptw[5].pmp[3].cfg.w
invalidate io.ptw[5].pmp[3].cfg.x
invalidate io.ptw[5].pmp[3].cfg.a
invalidate io.ptw[5].pmp[3].cfg.res
invalidate io.ptw[5].pmp[3].cfg.l
invalidate io.ptw[5].pmp[4].mask
invalidate io.ptw[5].pmp[4].addr
invalidate io.ptw[5].pmp[4].cfg.r
invalidate io.ptw[5].pmp[4].cfg.w
invalidate io.ptw[5].pmp[4].cfg.x
invalidate io.ptw[5].pmp[4].cfg.a
invalidate io.ptw[5].pmp[4].cfg.res
invalidate io.ptw[5].pmp[4].cfg.l
invalidate io.ptw[5].pmp[5].mask
invalidate io.ptw[5].pmp[5].addr
invalidate io.ptw[5].pmp[5].cfg.r
invalidate io.ptw[5].pmp[5].cfg.w
invalidate io.ptw[5].pmp[5].cfg.x
invalidate io.ptw[5].pmp[5].cfg.a
invalidate io.ptw[5].pmp[5].cfg.res
invalidate io.ptw[5].pmp[5].cfg.l
invalidate io.ptw[5].pmp[6].mask
invalidate io.ptw[5].pmp[6].addr
invalidate io.ptw[5].pmp[6].cfg.r
invalidate io.ptw[5].pmp[6].cfg.w
invalidate io.ptw[5].pmp[6].cfg.x
invalidate io.ptw[5].pmp[6].cfg.a
invalidate io.ptw[5].pmp[6].cfg.res
invalidate io.ptw[5].pmp[6].cfg.l
invalidate io.ptw[5].pmp[7].mask
invalidate io.ptw[5].pmp[7].addr
invalidate io.ptw[5].pmp[7].cfg.r
invalidate io.ptw[5].pmp[7].cfg.w
invalidate io.ptw[5].pmp[7].cfg.x
invalidate io.ptw[5].pmp[7].cfg.a
invalidate io.ptw[5].pmp[7].cfg.res
invalidate io.ptw[5].pmp[7].cfg.l
invalidate io.ptw[5].gstatus.uie
invalidate io.ptw[5].gstatus.sie
invalidate io.ptw[5].gstatus.hie
invalidate io.ptw[5].gstatus.mie
invalidate io.ptw[5].gstatus.upie
invalidate io.ptw[5].gstatus.spie
invalidate io.ptw[5].gstatus.ube
invalidate io.ptw[5].gstatus.mpie
invalidate io.ptw[5].gstatus.spp
invalidate io.ptw[5].gstatus.vs
invalidate io.ptw[5].gstatus.mpp
invalidate io.ptw[5].gstatus.fs
invalidate io.ptw[5].gstatus.xs
invalidate io.ptw[5].gstatus.mprv
invalidate io.ptw[5].gstatus.sum
invalidate io.ptw[5].gstatus.mxr
invalidate io.ptw[5].gstatus.tvm
invalidate io.ptw[5].gstatus.tw
invalidate io.ptw[5].gstatus.tsr
invalidate io.ptw[5].gstatus.zero1
invalidate io.ptw[5].gstatus.sd_rv32
invalidate io.ptw[5].gstatus.uxl
invalidate io.ptw[5].gstatus.sxl
invalidate io.ptw[5].gstatus.sbe
invalidate io.ptw[5].gstatus.mbe
invalidate io.ptw[5].gstatus.gva
invalidate io.ptw[5].gstatus.mpv
invalidate io.ptw[5].gstatus.zero2
invalidate io.ptw[5].gstatus.sd
invalidate io.ptw[5].gstatus.v
invalidate io.ptw[5].gstatus.prv
invalidate io.ptw[5].gstatus.dv
invalidate io.ptw[5].gstatus.dprv
invalidate io.ptw[5].gstatus.isa
invalidate io.ptw[5].gstatus.wfi
invalidate io.ptw[5].gstatus.cease
invalidate io.ptw[5].gstatus.debug
invalidate io.ptw[5].hstatus.zero1
invalidate io.ptw[5].hstatus.vsbe
invalidate io.ptw[5].hstatus.gva
invalidate io.ptw[5].hstatus.spv
invalidate io.ptw[5].hstatus.spvp
invalidate io.ptw[5].hstatus.hu
invalidate io.ptw[5].hstatus.zero2
invalidate io.ptw[5].hstatus.vgein
invalidate io.ptw[5].hstatus.zero3
invalidate io.ptw[5].hstatus.vtvm
invalidate io.ptw[5].hstatus.vtw
invalidate io.ptw[5].hstatus.vtsr
invalidate io.ptw[5].hstatus.zero5
invalidate io.ptw[5].hstatus.vsxl
invalidate io.ptw[5].hstatus.zero6
invalidate io.ptw[5].status.uie
invalidate io.ptw[5].status.sie
invalidate io.ptw[5].status.hie
invalidate io.ptw[5].status.mie
invalidate io.ptw[5].status.upie
invalidate io.ptw[5].status.spie
invalidate io.ptw[5].status.ube
invalidate io.ptw[5].status.mpie
invalidate io.ptw[5].status.spp
invalidate io.ptw[5].status.vs
invalidate io.ptw[5].status.mpp
invalidate io.ptw[5].status.fs
invalidate io.ptw[5].status.xs
invalidate io.ptw[5].status.mprv
invalidate io.ptw[5].status.sum
invalidate io.ptw[5].status.mxr
invalidate io.ptw[5].status.tvm
invalidate io.ptw[5].status.tw
invalidate io.ptw[5].status.tsr
invalidate io.ptw[5].status.zero1
invalidate io.ptw[5].status.sd_rv32
invalidate io.ptw[5].status.uxl
invalidate io.ptw[5].status.sxl
invalidate io.ptw[5].status.sbe
invalidate io.ptw[5].status.mbe
invalidate io.ptw[5].status.gva
invalidate io.ptw[5].status.mpv
invalidate io.ptw[5].status.zero2
invalidate io.ptw[5].status.sd
invalidate io.ptw[5].status.v
invalidate io.ptw[5].status.prv
invalidate io.ptw[5].status.dv
invalidate io.ptw[5].status.dprv
invalidate io.ptw[5].status.isa
invalidate io.ptw[5].status.wfi
invalidate io.ptw[5].status.cease
invalidate io.ptw[5].status.debug
invalidate io.ptw[5].vsatp.ppn
invalidate io.ptw[5].vsatp.asid
invalidate io.ptw[5].vsatp.mode
invalidate io.ptw[5].hgatp.ppn
invalidate io.ptw[5].hgatp.asid
invalidate io.ptw[5].hgatp.mode
invalidate io.ptw[5].ptbr.ppn
invalidate io.ptw[5].ptbr.asid
invalidate io.ptw[5].ptbr.mode
invalidate io.ptw[5].resp.bits.gpa_is_pte
invalidate io.ptw[5].resp.bits.gpa.bits
invalidate io.ptw[5].resp.bits.gpa.valid
invalidate io.ptw[5].resp.bits.homogeneous
invalidate io.ptw[5].resp.bits.fragmented_superpage
invalidate io.ptw[5].resp.bits.level
invalidate io.ptw[5].resp.bits.pte.v
invalidate io.ptw[5].resp.bits.pte.r
invalidate io.ptw[5].resp.bits.pte.w
invalidate io.ptw[5].resp.bits.pte.x
invalidate io.ptw[5].resp.bits.pte.u
invalidate io.ptw[5].resp.bits.pte.g
invalidate io.ptw[5].resp.bits.pte.a
invalidate io.ptw[5].resp.bits.pte.d
invalidate io.ptw[5].resp.bits.pte.reserved_for_software
invalidate io.ptw[5].resp.bits.pte.ppn
invalidate io.ptw[5].resp.bits.pte.reserved_for_future
invalidate io.ptw[5].resp.bits.hx
invalidate io.ptw[5].resp.bits.hw
invalidate io.ptw[5].resp.bits.hr
invalidate io.ptw[5].resp.bits.gf
invalidate io.ptw[5].resp.bits.pf
invalidate io.ptw[5].resp.bits.ae_final
invalidate io.ptw[5].resp.bits.ae_ptw
invalidate io.ptw[5].resp.valid
invalidate io.ptw[5].req.bits.bits.stage2
invalidate io.ptw[5].req.bits.bits.vstage1
invalidate io.ptw[5].req.bits.bits.need_gpa
invalidate io.ptw[5].req.bits.bits.addr
invalidate io.ptw[5].req.bits.valid
invalidate io.ptw[5].req.valid
invalidate io.ptw[5].req.ready
invalidate io.ptw[6].customCSRs.csrs[0].sdata
invalidate io.ptw[6].customCSRs.csrs[0].set
invalidate io.ptw[6].customCSRs.csrs[0].stall
invalidate io.ptw[6].customCSRs.csrs[0].value
invalidate io.ptw[6].customCSRs.csrs[0].wdata
invalidate io.ptw[6].customCSRs.csrs[0].wen
invalidate io.ptw[6].customCSRs.csrs[0].ren
invalidate io.ptw[6].customCSRs.csrs[1].sdata
invalidate io.ptw[6].customCSRs.csrs[1].set
invalidate io.ptw[6].customCSRs.csrs[1].stall
invalidate io.ptw[6].customCSRs.csrs[1].value
invalidate io.ptw[6].customCSRs.csrs[1].wdata
invalidate io.ptw[6].customCSRs.csrs[1].wen
invalidate io.ptw[6].customCSRs.csrs[1].ren
invalidate io.ptw[6].customCSRs.csrs[2].sdata
invalidate io.ptw[6].customCSRs.csrs[2].set
invalidate io.ptw[6].customCSRs.csrs[2].stall
invalidate io.ptw[6].customCSRs.csrs[2].value
invalidate io.ptw[6].customCSRs.csrs[2].wdata
invalidate io.ptw[6].customCSRs.csrs[2].wen
invalidate io.ptw[6].customCSRs.csrs[2].ren
invalidate io.ptw[6].customCSRs.csrs[3].sdata
invalidate io.ptw[6].customCSRs.csrs[3].set
invalidate io.ptw[6].customCSRs.csrs[3].stall
invalidate io.ptw[6].customCSRs.csrs[3].value
invalidate io.ptw[6].customCSRs.csrs[3].wdata
invalidate io.ptw[6].customCSRs.csrs[3].wen
invalidate io.ptw[6].customCSRs.csrs[3].ren
invalidate io.ptw[6].pmp[0].mask
invalidate io.ptw[6].pmp[0].addr
invalidate io.ptw[6].pmp[0].cfg.r
invalidate io.ptw[6].pmp[0].cfg.w
invalidate io.ptw[6].pmp[0].cfg.x
invalidate io.ptw[6].pmp[0].cfg.a
invalidate io.ptw[6].pmp[0].cfg.res
invalidate io.ptw[6].pmp[0].cfg.l
invalidate io.ptw[6].pmp[1].mask
invalidate io.ptw[6].pmp[1].addr
invalidate io.ptw[6].pmp[1].cfg.r
invalidate io.ptw[6].pmp[1].cfg.w
invalidate io.ptw[6].pmp[1].cfg.x
invalidate io.ptw[6].pmp[1].cfg.a
invalidate io.ptw[6].pmp[1].cfg.res
invalidate io.ptw[6].pmp[1].cfg.l
invalidate io.ptw[6].pmp[2].mask
invalidate io.ptw[6].pmp[2].addr
invalidate io.ptw[6].pmp[2].cfg.r
invalidate io.ptw[6].pmp[2].cfg.w
invalidate io.ptw[6].pmp[2].cfg.x
invalidate io.ptw[6].pmp[2].cfg.a
invalidate io.ptw[6].pmp[2].cfg.res
invalidate io.ptw[6].pmp[2].cfg.l
invalidate io.ptw[6].pmp[3].mask
invalidate io.ptw[6].pmp[3].addr
invalidate io.ptw[6].pmp[3].cfg.r
invalidate io.ptw[6].pmp[3].cfg.w
invalidate io.ptw[6].pmp[3].cfg.x
invalidate io.ptw[6].pmp[3].cfg.a
invalidate io.ptw[6].pmp[3].cfg.res
invalidate io.ptw[6].pmp[3].cfg.l
invalidate io.ptw[6].pmp[4].mask
invalidate io.ptw[6].pmp[4].addr
invalidate io.ptw[6].pmp[4].cfg.r
invalidate io.ptw[6].pmp[4].cfg.w
invalidate io.ptw[6].pmp[4].cfg.x
invalidate io.ptw[6].pmp[4].cfg.a
invalidate io.ptw[6].pmp[4].cfg.res
invalidate io.ptw[6].pmp[4].cfg.l
invalidate io.ptw[6].pmp[5].mask
invalidate io.ptw[6].pmp[5].addr
invalidate io.ptw[6].pmp[5].cfg.r
invalidate io.ptw[6].pmp[5].cfg.w
invalidate io.ptw[6].pmp[5].cfg.x
invalidate io.ptw[6].pmp[5].cfg.a
invalidate io.ptw[6].pmp[5].cfg.res
invalidate io.ptw[6].pmp[5].cfg.l
invalidate io.ptw[6].pmp[6].mask
invalidate io.ptw[6].pmp[6].addr
invalidate io.ptw[6].pmp[6].cfg.r
invalidate io.ptw[6].pmp[6].cfg.w
invalidate io.ptw[6].pmp[6].cfg.x
invalidate io.ptw[6].pmp[6].cfg.a
invalidate io.ptw[6].pmp[6].cfg.res
invalidate io.ptw[6].pmp[6].cfg.l
invalidate io.ptw[6].pmp[7].mask
invalidate io.ptw[6].pmp[7].addr
invalidate io.ptw[6].pmp[7].cfg.r
invalidate io.ptw[6].pmp[7].cfg.w
invalidate io.ptw[6].pmp[7].cfg.x
invalidate io.ptw[6].pmp[7].cfg.a
invalidate io.ptw[6].pmp[7].cfg.res
invalidate io.ptw[6].pmp[7].cfg.l
invalidate io.ptw[6].gstatus.uie
invalidate io.ptw[6].gstatus.sie
invalidate io.ptw[6].gstatus.hie
invalidate io.ptw[6].gstatus.mie
invalidate io.ptw[6].gstatus.upie
invalidate io.ptw[6].gstatus.spie
invalidate io.ptw[6].gstatus.ube
invalidate io.ptw[6].gstatus.mpie
invalidate io.ptw[6].gstatus.spp
invalidate io.ptw[6].gstatus.vs
invalidate io.ptw[6].gstatus.mpp
invalidate io.ptw[6].gstatus.fs
invalidate io.ptw[6].gstatus.xs
invalidate io.ptw[6].gstatus.mprv
invalidate io.ptw[6].gstatus.sum
invalidate io.ptw[6].gstatus.mxr
invalidate io.ptw[6].gstatus.tvm
invalidate io.ptw[6].gstatus.tw
invalidate io.ptw[6].gstatus.tsr
invalidate io.ptw[6].gstatus.zero1
invalidate io.ptw[6].gstatus.sd_rv32
invalidate io.ptw[6].gstatus.uxl
invalidate io.ptw[6].gstatus.sxl
invalidate io.ptw[6].gstatus.sbe
invalidate io.ptw[6].gstatus.mbe
invalidate io.ptw[6].gstatus.gva
invalidate io.ptw[6].gstatus.mpv
invalidate io.ptw[6].gstatus.zero2
invalidate io.ptw[6].gstatus.sd
invalidate io.ptw[6].gstatus.v
invalidate io.ptw[6].gstatus.prv
invalidate io.ptw[6].gstatus.dv
invalidate io.ptw[6].gstatus.dprv
invalidate io.ptw[6].gstatus.isa
invalidate io.ptw[6].gstatus.wfi
invalidate io.ptw[6].gstatus.cease
invalidate io.ptw[6].gstatus.debug
invalidate io.ptw[6].hstatus.zero1
invalidate io.ptw[6].hstatus.vsbe
invalidate io.ptw[6].hstatus.gva
invalidate io.ptw[6].hstatus.spv
invalidate io.ptw[6].hstatus.spvp
invalidate io.ptw[6].hstatus.hu
invalidate io.ptw[6].hstatus.zero2
invalidate io.ptw[6].hstatus.vgein
invalidate io.ptw[6].hstatus.zero3
invalidate io.ptw[6].hstatus.vtvm
invalidate io.ptw[6].hstatus.vtw
invalidate io.ptw[6].hstatus.vtsr
invalidate io.ptw[6].hstatus.zero5
invalidate io.ptw[6].hstatus.vsxl
invalidate io.ptw[6].hstatus.zero6
invalidate io.ptw[6].status.uie
invalidate io.ptw[6].status.sie
invalidate io.ptw[6].status.hie
invalidate io.ptw[6].status.mie
invalidate io.ptw[6].status.upie
invalidate io.ptw[6].status.spie
invalidate io.ptw[6].status.ube
invalidate io.ptw[6].status.mpie
invalidate io.ptw[6].status.spp
invalidate io.ptw[6].status.vs
invalidate io.ptw[6].status.mpp
invalidate io.ptw[6].status.fs
invalidate io.ptw[6].status.xs
invalidate io.ptw[6].status.mprv
invalidate io.ptw[6].status.sum
invalidate io.ptw[6].status.mxr
invalidate io.ptw[6].status.tvm
invalidate io.ptw[6].status.tw
invalidate io.ptw[6].status.tsr
invalidate io.ptw[6].status.zero1
invalidate io.ptw[6].status.sd_rv32
invalidate io.ptw[6].status.uxl
invalidate io.ptw[6].status.sxl
invalidate io.ptw[6].status.sbe
invalidate io.ptw[6].status.mbe
invalidate io.ptw[6].status.gva
invalidate io.ptw[6].status.mpv
invalidate io.ptw[6].status.zero2
invalidate io.ptw[6].status.sd
invalidate io.ptw[6].status.v
invalidate io.ptw[6].status.prv
invalidate io.ptw[6].status.dv
invalidate io.ptw[6].status.dprv
invalidate io.ptw[6].status.isa
invalidate io.ptw[6].status.wfi
invalidate io.ptw[6].status.cease
invalidate io.ptw[6].status.debug
invalidate io.ptw[6].vsatp.ppn
invalidate io.ptw[6].vsatp.asid
invalidate io.ptw[6].vsatp.mode
invalidate io.ptw[6].hgatp.ppn
invalidate io.ptw[6].hgatp.asid
invalidate io.ptw[6].hgatp.mode
invalidate io.ptw[6].ptbr.ppn
invalidate io.ptw[6].ptbr.asid
invalidate io.ptw[6].ptbr.mode
invalidate io.ptw[6].resp.bits.gpa_is_pte
invalidate io.ptw[6].resp.bits.gpa.bits
invalidate io.ptw[6].resp.bits.gpa.valid
invalidate io.ptw[6].resp.bits.homogeneous
invalidate io.ptw[6].resp.bits.fragmented_superpage
invalidate io.ptw[6].resp.bits.level
invalidate io.ptw[6].resp.bits.pte.v
invalidate io.ptw[6].resp.bits.pte.r
invalidate io.ptw[6].resp.bits.pte.w
invalidate io.ptw[6].resp.bits.pte.x
invalidate io.ptw[6].resp.bits.pte.u
invalidate io.ptw[6].resp.bits.pte.g
invalidate io.ptw[6].resp.bits.pte.a
invalidate io.ptw[6].resp.bits.pte.d
invalidate io.ptw[6].resp.bits.pte.reserved_for_software
invalidate io.ptw[6].resp.bits.pte.ppn
invalidate io.ptw[6].resp.bits.pte.reserved_for_future
invalidate io.ptw[6].resp.bits.hx
invalidate io.ptw[6].resp.bits.hw
invalidate io.ptw[6].resp.bits.hr
invalidate io.ptw[6].resp.bits.gf
invalidate io.ptw[6].resp.bits.pf
invalidate io.ptw[6].resp.bits.ae_final
invalidate io.ptw[6].resp.bits.ae_ptw
invalidate io.ptw[6].resp.valid
invalidate io.ptw[6].req.bits.bits.stage2
invalidate io.ptw[6].req.bits.bits.vstage1
invalidate io.ptw[6].req.bits.bits.need_gpa
invalidate io.ptw[6].req.bits.bits.addr
invalidate io.ptw[6].req.bits.valid
invalidate io.ptw[6].req.valid
invalidate io.ptw[6].req.ready
invalidate io.ptw[7].customCSRs.csrs[0].sdata
invalidate io.ptw[7].customCSRs.csrs[0].set
invalidate io.ptw[7].customCSRs.csrs[0].stall
invalidate io.ptw[7].customCSRs.csrs[0].value
invalidate io.ptw[7].customCSRs.csrs[0].wdata
invalidate io.ptw[7].customCSRs.csrs[0].wen
invalidate io.ptw[7].customCSRs.csrs[0].ren
invalidate io.ptw[7].customCSRs.csrs[1].sdata
invalidate io.ptw[7].customCSRs.csrs[1].set
invalidate io.ptw[7].customCSRs.csrs[1].stall
invalidate io.ptw[7].customCSRs.csrs[1].value
invalidate io.ptw[7].customCSRs.csrs[1].wdata
invalidate io.ptw[7].customCSRs.csrs[1].wen
invalidate io.ptw[7].customCSRs.csrs[1].ren
invalidate io.ptw[7].customCSRs.csrs[2].sdata
invalidate io.ptw[7].customCSRs.csrs[2].set
invalidate io.ptw[7].customCSRs.csrs[2].stall
invalidate io.ptw[7].customCSRs.csrs[2].value
invalidate io.ptw[7].customCSRs.csrs[2].wdata
invalidate io.ptw[7].customCSRs.csrs[2].wen
invalidate io.ptw[7].customCSRs.csrs[2].ren
invalidate io.ptw[7].customCSRs.csrs[3].sdata
invalidate io.ptw[7].customCSRs.csrs[3].set
invalidate io.ptw[7].customCSRs.csrs[3].stall
invalidate io.ptw[7].customCSRs.csrs[3].value
invalidate io.ptw[7].customCSRs.csrs[3].wdata
invalidate io.ptw[7].customCSRs.csrs[3].wen
invalidate io.ptw[7].customCSRs.csrs[3].ren
invalidate io.ptw[7].pmp[0].mask
invalidate io.ptw[7].pmp[0].addr
invalidate io.ptw[7].pmp[0].cfg.r
invalidate io.ptw[7].pmp[0].cfg.w
invalidate io.ptw[7].pmp[0].cfg.x
invalidate io.ptw[7].pmp[0].cfg.a
invalidate io.ptw[7].pmp[0].cfg.res
invalidate io.ptw[7].pmp[0].cfg.l
invalidate io.ptw[7].pmp[1].mask
invalidate io.ptw[7].pmp[1].addr
invalidate io.ptw[7].pmp[1].cfg.r
invalidate io.ptw[7].pmp[1].cfg.w
invalidate io.ptw[7].pmp[1].cfg.x
invalidate io.ptw[7].pmp[1].cfg.a
invalidate io.ptw[7].pmp[1].cfg.res
invalidate io.ptw[7].pmp[1].cfg.l
invalidate io.ptw[7].pmp[2].mask
invalidate io.ptw[7].pmp[2].addr
invalidate io.ptw[7].pmp[2].cfg.r
invalidate io.ptw[7].pmp[2].cfg.w
invalidate io.ptw[7].pmp[2].cfg.x
invalidate io.ptw[7].pmp[2].cfg.a
invalidate io.ptw[7].pmp[2].cfg.res
invalidate io.ptw[7].pmp[2].cfg.l
invalidate io.ptw[7].pmp[3].mask
invalidate io.ptw[7].pmp[3].addr
invalidate io.ptw[7].pmp[3].cfg.r
invalidate io.ptw[7].pmp[3].cfg.w
invalidate io.ptw[7].pmp[3].cfg.x
invalidate io.ptw[7].pmp[3].cfg.a
invalidate io.ptw[7].pmp[3].cfg.res
invalidate io.ptw[7].pmp[3].cfg.l
invalidate io.ptw[7].pmp[4].mask
invalidate io.ptw[7].pmp[4].addr
invalidate io.ptw[7].pmp[4].cfg.r
invalidate io.ptw[7].pmp[4].cfg.w
invalidate io.ptw[7].pmp[4].cfg.x
invalidate io.ptw[7].pmp[4].cfg.a
invalidate io.ptw[7].pmp[4].cfg.res
invalidate io.ptw[7].pmp[4].cfg.l
invalidate io.ptw[7].pmp[5].mask
invalidate io.ptw[7].pmp[5].addr
invalidate io.ptw[7].pmp[5].cfg.r
invalidate io.ptw[7].pmp[5].cfg.w
invalidate io.ptw[7].pmp[5].cfg.x
invalidate io.ptw[7].pmp[5].cfg.a
invalidate io.ptw[7].pmp[5].cfg.res
invalidate io.ptw[7].pmp[5].cfg.l
invalidate io.ptw[7].pmp[6].mask
invalidate io.ptw[7].pmp[6].addr
invalidate io.ptw[7].pmp[6].cfg.r
invalidate io.ptw[7].pmp[6].cfg.w
invalidate io.ptw[7].pmp[6].cfg.x
invalidate io.ptw[7].pmp[6].cfg.a
invalidate io.ptw[7].pmp[6].cfg.res
invalidate io.ptw[7].pmp[6].cfg.l
invalidate io.ptw[7].pmp[7].mask
invalidate io.ptw[7].pmp[7].addr
invalidate io.ptw[7].pmp[7].cfg.r
invalidate io.ptw[7].pmp[7].cfg.w
invalidate io.ptw[7].pmp[7].cfg.x
invalidate io.ptw[7].pmp[7].cfg.a
invalidate io.ptw[7].pmp[7].cfg.res
invalidate io.ptw[7].pmp[7].cfg.l
invalidate io.ptw[7].gstatus.uie
invalidate io.ptw[7].gstatus.sie
invalidate io.ptw[7].gstatus.hie
invalidate io.ptw[7].gstatus.mie
invalidate io.ptw[7].gstatus.upie
invalidate io.ptw[7].gstatus.spie
invalidate io.ptw[7].gstatus.ube
invalidate io.ptw[7].gstatus.mpie
invalidate io.ptw[7].gstatus.spp
invalidate io.ptw[7].gstatus.vs
invalidate io.ptw[7].gstatus.mpp
invalidate io.ptw[7].gstatus.fs
invalidate io.ptw[7].gstatus.xs
invalidate io.ptw[7].gstatus.mprv
invalidate io.ptw[7].gstatus.sum
invalidate io.ptw[7].gstatus.mxr
invalidate io.ptw[7].gstatus.tvm
invalidate io.ptw[7].gstatus.tw
invalidate io.ptw[7].gstatus.tsr
invalidate io.ptw[7].gstatus.zero1
invalidate io.ptw[7].gstatus.sd_rv32
invalidate io.ptw[7].gstatus.uxl
invalidate io.ptw[7].gstatus.sxl
invalidate io.ptw[7].gstatus.sbe
invalidate io.ptw[7].gstatus.mbe
invalidate io.ptw[7].gstatus.gva
invalidate io.ptw[7].gstatus.mpv
invalidate io.ptw[7].gstatus.zero2
invalidate io.ptw[7].gstatus.sd
invalidate io.ptw[7].gstatus.v
invalidate io.ptw[7].gstatus.prv
invalidate io.ptw[7].gstatus.dv
invalidate io.ptw[7].gstatus.dprv
invalidate io.ptw[7].gstatus.isa
invalidate io.ptw[7].gstatus.wfi
invalidate io.ptw[7].gstatus.cease
invalidate io.ptw[7].gstatus.debug
invalidate io.ptw[7].hstatus.zero1
invalidate io.ptw[7].hstatus.vsbe
invalidate io.ptw[7].hstatus.gva
invalidate io.ptw[7].hstatus.spv
invalidate io.ptw[7].hstatus.spvp
invalidate io.ptw[7].hstatus.hu
invalidate io.ptw[7].hstatus.zero2
invalidate io.ptw[7].hstatus.vgein
invalidate io.ptw[7].hstatus.zero3
invalidate io.ptw[7].hstatus.vtvm
invalidate io.ptw[7].hstatus.vtw
invalidate io.ptw[7].hstatus.vtsr
invalidate io.ptw[7].hstatus.zero5
invalidate io.ptw[7].hstatus.vsxl
invalidate io.ptw[7].hstatus.zero6
invalidate io.ptw[7].status.uie
invalidate io.ptw[7].status.sie
invalidate io.ptw[7].status.hie
invalidate io.ptw[7].status.mie
invalidate io.ptw[7].status.upie
invalidate io.ptw[7].status.spie
invalidate io.ptw[7].status.ube
invalidate io.ptw[7].status.mpie
invalidate io.ptw[7].status.spp
invalidate io.ptw[7].status.vs
invalidate io.ptw[7].status.mpp
invalidate io.ptw[7].status.fs
invalidate io.ptw[7].status.xs
invalidate io.ptw[7].status.mprv
invalidate io.ptw[7].status.sum
invalidate io.ptw[7].status.mxr
invalidate io.ptw[7].status.tvm
invalidate io.ptw[7].status.tw
invalidate io.ptw[7].status.tsr
invalidate io.ptw[7].status.zero1
invalidate io.ptw[7].status.sd_rv32
invalidate io.ptw[7].status.uxl
invalidate io.ptw[7].status.sxl
invalidate io.ptw[7].status.sbe
invalidate io.ptw[7].status.mbe
invalidate io.ptw[7].status.gva
invalidate io.ptw[7].status.mpv
invalidate io.ptw[7].status.zero2
invalidate io.ptw[7].status.sd
invalidate io.ptw[7].status.v
invalidate io.ptw[7].status.prv
invalidate io.ptw[7].status.dv
invalidate io.ptw[7].status.dprv
invalidate io.ptw[7].status.isa
invalidate io.ptw[7].status.wfi
invalidate io.ptw[7].status.cease
invalidate io.ptw[7].status.debug
invalidate io.ptw[7].vsatp.ppn
invalidate io.ptw[7].vsatp.asid
invalidate io.ptw[7].vsatp.mode
invalidate io.ptw[7].hgatp.ppn
invalidate io.ptw[7].hgatp.asid
invalidate io.ptw[7].hgatp.mode
invalidate io.ptw[7].ptbr.ppn
invalidate io.ptw[7].ptbr.asid
invalidate io.ptw[7].ptbr.mode
invalidate io.ptw[7].resp.bits.gpa_is_pte
invalidate io.ptw[7].resp.bits.gpa.bits
invalidate io.ptw[7].resp.bits.gpa.valid
invalidate io.ptw[7].resp.bits.homogeneous
invalidate io.ptw[7].resp.bits.fragmented_superpage
invalidate io.ptw[7].resp.bits.level
invalidate io.ptw[7].resp.bits.pte.v
invalidate io.ptw[7].resp.bits.pte.r
invalidate io.ptw[7].resp.bits.pte.w
invalidate io.ptw[7].resp.bits.pte.x
invalidate io.ptw[7].resp.bits.pte.u
invalidate io.ptw[7].resp.bits.pte.g
invalidate io.ptw[7].resp.bits.pte.a
invalidate io.ptw[7].resp.bits.pte.d
invalidate io.ptw[7].resp.bits.pte.reserved_for_software
invalidate io.ptw[7].resp.bits.pte.ppn
invalidate io.ptw[7].resp.bits.pte.reserved_for_future
invalidate io.ptw[7].resp.bits.hx
invalidate io.ptw[7].resp.bits.hw
invalidate io.ptw[7].resp.bits.hr
invalidate io.ptw[7].resp.bits.gf
invalidate io.ptw[7].resp.bits.pf
invalidate io.ptw[7].resp.bits.ae_final
invalidate io.ptw[7].resp.bits.ae_ptw
invalidate io.ptw[7].resp.valid
invalidate io.ptw[7].req.bits.bits.stage2
invalidate io.ptw[7].req.bits.bits.vstage1
invalidate io.ptw[7].req.bits.bits.need_gpa
invalidate io.ptw[7].req.bits.bits.addr
invalidate io.ptw[7].req.bits.valid
invalidate io.ptw[7].req.valid
invalidate io.ptw[7].req.ready
invalidate io.ptw[8].customCSRs.csrs[0].sdata
invalidate io.ptw[8].customCSRs.csrs[0].set
invalidate io.ptw[8].customCSRs.csrs[0].stall
invalidate io.ptw[8].customCSRs.csrs[0].value
invalidate io.ptw[8].customCSRs.csrs[0].wdata
invalidate io.ptw[8].customCSRs.csrs[0].wen
invalidate io.ptw[8].customCSRs.csrs[0].ren
invalidate io.ptw[8].customCSRs.csrs[1].sdata
invalidate io.ptw[8].customCSRs.csrs[1].set
invalidate io.ptw[8].customCSRs.csrs[1].stall
invalidate io.ptw[8].customCSRs.csrs[1].value
invalidate io.ptw[8].customCSRs.csrs[1].wdata
invalidate io.ptw[8].customCSRs.csrs[1].wen
invalidate io.ptw[8].customCSRs.csrs[1].ren
invalidate io.ptw[8].customCSRs.csrs[2].sdata
invalidate io.ptw[8].customCSRs.csrs[2].set
invalidate io.ptw[8].customCSRs.csrs[2].stall
invalidate io.ptw[8].customCSRs.csrs[2].value
invalidate io.ptw[8].customCSRs.csrs[2].wdata
invalidate io.ptw[8].customCSRs.csrs[2].wen
invalidate io.ptw[8].customCSRs.csrs[2].ren
invalidate io.ptw[8].customCSRs.csrs[3].sdata
invalidate io.ptw[8].customCSRs.csrs[3].set
invalidate io.ptw[8].customCSRs.csrs[3].stall
invalidate io.ptw[8].customCSRs.csrs[3].value
invalidate io.ptw[8].customCSRs.csrs[3].wdata
invalidate io.ptw[8].customCSRs.csrs[3].wen
invalidate io.ptw[8].customCSRs.csrs[3].ren
invalidate io.ptw[8].pmp[0].mask
invalidate io.ptw[8].pmp[0].addr
invalidate io.ptw[8].pmp[0].cfg.r
invalidate io.ptw[8].pmp[0].cfg.w
invalidate io.ptw[8].pmp[0].cfg.x
invalidate io.ptw[8].pmp[0].cfg.a
invalidate io.ptw[8].pmp[0].cfg.res
invalidate io.ptw[8].pmp[0].cfg.l
invalidate io.ptw[8].pmp[1].mask
invalidate io.ptw[8].pmp[1].addr
invalidate io.ptw[8].pmp[1].cfg.r
invalidate io.ptw[8].pmp[1].cfg.w
invalidate io.ptw[8].pmp[1].cfg.x
invalidate io.ptw[8].pmp[1].cfg.a
invalidate io.ptw[8].pmp[1].cfg.res
invalidate io.ptw[8].pmp[1].cfg.l
invalidate io.ptw[8].pmp[2].mask
invalidate io.ptw[8].pmp[2].addr
invalidate io.ptw[8].pmp[2].cfg.r
invalidate io.ptw[8].pmp[2].cfg.w
invalidate io.ptw[8].pmp[2].cfg.x
invalidate io.ptw[8].pmp[2].cfg.a
invalidate io.ptw[8].pmp[2].cfg.res
invalidate io.ptw[8].pmp[2].cfg.l
invalidate io.ptw[8].pmp[3].mask
invalidate io.ptw[8].pmp[3].addr
invalidate io.ptw[8].pmp[3].cfg.r
invalidate io.ptw[8].pmp[3].cfg.w
invalidate io.ptw[8].pmp[3].cfg.x
invalidate io.ptw[8].pmp[3].cfg.a
invalidate io.ptw[8].pmp[3].cfg.res
invalidate io.ptw[8].pmp[3].cfg.l
invalidate io.ptw[8].pmp[4].mask
invalidate io.ptw[8].pmp[4].addr
invalidate io.ptw[8].pmp[4].cfg.r
invalidate io.ptw[8].pmp[4].cfg.w
invalidate io.ptw[8].pmp[4].cfg.x
invalidate io.ptw[8].pmp[4].cfg.a
invalidate io.ptw[8].pmp[4].cfg.res
invalidate io.ptw[8].pmp[4].cfg.l
invalidate io.ptw[8].pmp[5].mask
invalidate io.ptw[8].pmp[5].addr
invalidate io.ptw[8].pmp[5].cfg.r
invalidate io.ptw[8].pmp[5].cfg.w
invalidate io.ptw[8].pmp[5].cfg.x
invalidate io.ptw[8].pmp[5].cfg.a
invalidate io.ptw[8].pmp[5].cfg.res
invalidate io.ptw[8].pmp[5].cfg.l
invalidate io.ptw[8].pmp[6].mask
invalidate io.ptw[8].pmp[6].addr
invalidate io.ptw[8].pmp[6].cfg.r
invalidate io.ptw[8].pmp[6].cfg.w
invalidate io.ptw[8].pmp[6].cfg.x
invalidate io.ptw[8].pmp[6].cfg.a
invalidate io.ptw[8].pmp[6].cfg.res
invalidate io.ptw[8].pmp[6].cfg.l
invalidate io.ptw[8].pmp[7].mask
invalidate io.ptw[8].pmp[7].addr
invalidate io.ptw[8].pmp[7].cfg.r
invalidate io.ptw[8].pmp[7].cfg.w
invalidate io.ptw[8].pmp[7].cfg.x
invalidate io.ptw[8].pmp[7].cfg.a
invalidate io.ptw[8].pmp[7].cfg.res
invalidate io.ptw[8].pmp[7].cfg.l
invalidate io.ptw[8].gstatus.uie
invalidate io.ptw[8].gstatus.sie
invalidate io.ptw[8].gstatus.hie
invalidate io.ptw[8].gstatus.mie
invalidate io.ptw[8].gstatus.upie
invalidate io.ptw[8].gstatus.spie
invalidate io.ptw[8].gstatus.ube
invalidate io.ptw[8].gstatus.mpie
invalidate io.ptw[8].gstatus.spp
invalidate io.ptw[8].gstatus.vs
invalidate io.ptw[8].gstatus.mpp
invalidate io.ptw[8].gstatus.fs
invalidate io.ptw[8].gstatus.xs
invalidate io.ptw[8].gstatus.mprv
invalidate io.ptw[8].gstatus.sum
invalidate io.ptw[8].gstatus.mxr
invalidate io.ptw[8].gstatus.tvm
invalidate io.ptw[8].gstatus.tw
invalidate io.ptw[8].gstatus.tsr
invalidate io.ptw[8].gstatus.zero1
invalidate io.ptw[8].gstatus.sd_rv32
invalidate io.ptw[8].gstatus.uxl
invalidate io.ptw[8].gstatus.sxl
invalidate io.ptw[8].gstatus.sbe
invalidate io.ptw[8].gstatus.mbe
invalidate io.ptw[8].gstatus.gva
invalidate io.ptw[8].gstatus.mpv
invalidate io.ptw[8].gstatus.zero2
invalidate io.ptw[8].gstatus.sd
invalidate io.ptw[8].gstatus.v
invalidate io.ptw[8].gstatus.prv
invalidate io.ptw[8].gstatus.dv
invalidate io.ptw[8].gstatus.dprv
invalidate io.ptw[8].gstatus.isa
invalidate io.ptw[8].gstatus.wfi
invalidate io.ptw[8].gstatus.cease
invalidate io.ptw[8].gstatus.debug
invalidate io.ptw[8].hstatus.zero1
invalidate io.ptw[8].hstatus.vsbe
invalidate io.ptw[8].hstatus.gva
invalidate io.ptw[8].hstatus.spv
invalidate io.ptw[8].hstatus.spvp
invalidate io.ptw[8].hstatus.hu
invalidate io.ptw[8].hstatus.zero2
invalidate io.ptw[8].hstatus.vgein
invalidate io.ptw[8].hstatus.zero3
invalidate io.ptw[8].hstatus.vtvm
invalidate io.ptw[8].hstatus.vtw
invalidate io.ptw[8].hstatus.vtsr
invalidate io.ptw[8].hstatus.zero5
invalidate io.ptw[8].hstatus.vsxl
invalidate io.ptw[8].hstatus.zero6
invalidate io.ptw[8].status.uie
invalidate io.ptw[8].status.sie
invalidate io.ptw[8].status.hie
invalidate io.ptw[8].status.mie
invalidate io.ptw[8].status.upie
invalidate io.ptw[8].status.spie
invalidate io.ptw[8].status.ube
invalidate io.ptw[8].status.mpie
invalidate io.ptw[8].status.spp
invalidate io.ptw[8].status.vs
invalidate io.ptw[8].status.mpp
invalidate io.ptw[8].status.fs
invalidate io.ptw[8].status.xs
invalidate io.ptw[8].status.mprv
invalidate io.ptw[8].status.sum
invalidate io.ptw[8].status.mxr
invalidate io.ptw[8].status.tvm
invalidate io.ptw[8].status.tw
invalidate io.ptw[8].status.tsr
invalidate io.ptw[8].status.zero1
invalidate io.ptw[8].status.sd_rv32
invalidate io.ptw[8].status.uxl
invalidate io.ptw[8].status.sxl
invalidate io.ptw[8].status.sbe
invalidate io.ptw[8].status.mbe
invalidate io.ptw[8].status.gva
invalidate io.ptw[8].status.mpv
invalidate io.ptw[8].status.zero2
invalidate io.ptw[8].status.sd
invalidate io.ptw[8].status.v
invalidate io.ptw[8].status.prv
invalidate io.ptw[8].status.dv
invalidate io.ptw[8].status.dprv
invalidate io.ptw[8].status.isa
invalidate io.ptw[8].status.wfi
invalidate io.ptw[8].status.cease
invalidate io.ptw[8].status.debug
invalidate io.ptw[8].vsatp.ppn
invalidate io.ptw[8].vsatp.asid
invalidate io.ptw[8].vsatp.mode
invalidate io.ptw[8].hgatp.ppn
invalidate io.ptw[8].hgatp.asid
invalidate io.ptw[8].hgatp.mode
invalidate io.ptw[8].ptbr.ppn
invalidate io.ptw[8].ptbr.asid
invalidate io.ptw[8].ptbr.mode
invalidate io.ptw[8].resp.bits.gpa_is_pte
invalidate io.ptw[8].resp.bits.gpa.bits
invalidate io.ptw[8].resp.bits.gpa.valid
invalidate io.ptw[8].resp.bits.homogeneous
invalidate io.ptw[8].resp.bits.fragmented_superpage
invalidate io.ptw[8].resp.bits.level
invalidate io.ptw[8].resp.bits.pte.v
invalidate io.ptw[8].resp.bits.pte.r
invalidate io.ptw[8].resp.bits.pte.w
invalidate io.ptw[8].resp.bits.pte.x
invalidate io.ptw[8].resp.bits.pte.u
invalidate io.ptw[8].resp.bits.pte.g
invalidate io.ptw[8].resp.bits.pte.a
invalidate io.ptw[8].resp.bits.pte.d
invalidate io.ptw[8].resp.bits.pte.reserved_for_software
invalidate io.ptw[8].resp.bits.pte.ppn
invalidate io.ptw[8].resp.bits.pte.reserved_for_future
invalidate io.ptw[8].resp.bits.hx
invalidate io.ptw[8].resp.bits.hw
invalidate io.ptw[8].resp.bits.hr
invalidate io.ptw[8].resp.bits.gf
invalidate io.ptw[8].resp.bits.pf
invalidate io.ptw[8].resp.bits.ae_final
invalidate io.ptw[8].resp.bits.ae_ptw
invalidate io.ptw[8].resp.valid
invalidate io.ptw[8].req.bits.bits.stage2
invalidate io.ptw[8].req.bits.bits.vstage1
invalidate io.ptw[8].req.bits.bits.need_gpa
invalidate io.ptw[8].req.bits.bits.addr
invalidate io.ptw[8].req.bits.valid
invalidate io.ptw[8].req.valid
invalidate io.ptw[8].req.ready
invalidate io.ptw[9].customCSRs.csrs[0].sdata
invalidate io.ptw[9].customCSRs.csrs[0].set
invalidate io.ptw[9].customCSRs.csrs[0].stall
invalidate io.ptw[9].customCSRs.csrs[0].value
invalidate io.ptw[9].customCSRs.csrs[0].wdata
invalidate io.ptw[9].customCSRs.csrs[0].wen
invalidate io.ptw[9].customCSRs.csrs[0].ren
invalidate io.ptw[9].customCSRs.csrs[1].sdata
invalidate io.ptw[9].customCSRs.csrs[1].set
invalidate io.ptw[9].customCSRs.csrs[1].stall
invalidate io.ptw[9].customCSRs.csrs[1].value
invalidate io.ptw[9].customCSRs.csrs[1].wdata
invalidate io.ptw[9].customCSRs.csrs[1].wen
invalidate io.ptw[9].customCSRs.csrs[1].ren
invalidate io.ptw[9].customCSRs.csrs[2].sdata
invalidate io.ptw[9].customCSRs.csrs[2].set
invalidate io.ptw[9].customCSRs.csrs[2].stall
invalidate io.ptw[9].customCSRs.csrs[2].value
invalidate io.ptw[9].customCSRs.csrs[2].wdata
invalidate io.ptw[9].customCSRs.csrs[2].wen
invalidate io.ptw[9].customCSRs.csrs[2].ren
invalidate io.ptw[9].customCSRs.csrs[3].sdata
invalidate io.ptw[9].customCSRs.csrs[3].set
invalidate io.ptw[9].customCSRs.csrs[3].stall
invalidate io.ptw[9].customCSRs.csrs[3].value
invalidate io.ptw[9].customCSRs.csrs[3].wdata
invalidate io.ptw[9].customCSRs.csrs[3].wen
invalidate io.ptw[9].customCSRs.csrs[3].ren
invalidate io.ptw[9].pmp[0].mask
invalidate io.ptw[9].pmp[0].addr
invalidate io.ptw[9].pmp[0].cfg.r
invalidate io.ptw[9].pmp[0].cfg.w
invalidate io.ptw[9].pmp[0].cfg.x
invalidate io.ptw[9].pmp[0].cfg.a
invalidate io.ptw[9].pmp[0].cfg.res
invalidate io.ptw[9].pmp[0].cfg.l
invalidate io.ptw[9].pmp[1].mask
invalidate io.ptw[9].pmp[1].addr
invalidate io.ptw[9].pmp[1].cfg.r
invalidate io.ptw[9].pmp[1].cfg.w
invalidate io.ptw[9].pmp[1].cfg.x
invalidate io.ptw[9].pmp[1].cfg.a
invalidate io.ptw[9].pmp[1].cfg.res
invalidate io.ptw[9].pmp[1].cfg.l
invalidate io.ptw[9].pmp[2].mask
invalidate io.ptw[9].pmp[2].addr
invalidate io.ptw[9].pmp[2].cfg.r
invalidate io.ptw[9].pmp[2].cfg.w
invalidate io.ptw[9].pmp[2].cfg.x
invalidate io.ptw[9].pmp[2].cfg.a
invalidate io.ptw[9].pmp[2].cfg.res
invalidate io.ptw[9].pmp[2].cfg.l
invalidate io.ptw[9].pmp[3].mask
invalidate io.ptw[9].pmp[3].addr
invalidate io.ptw[9].pmp[3].cfg.r
invalidate io.ptw[9].pmp[3].cfg.w
invalidate io.ptw[9].pmp[3].cfg.x
invalidate io.ptw[9].pmp[3].cfg.a
invalidate io.ptw[9].pmp[3].cfg.res
invalidate io.ptw[9].pmp[3].cfg.l
invalidate io.ptw[9].pmp[4].mask
invalidate io.ptw[9].pmp[4].addr
invalidate io.ptw[9].pmp[4].cfg.r
invalidate io.ptw[9].pmp[4].cfg.w
invalidate io.ptw[9].pmp[4].cfg.x
invalidate io.ptw[9].pmp[4].cfg.a
invalidate io.ptw[9].pmp[4].cfg.res
invalidate io.ptw[9].pmp[4].cfg.l
invalidate io.ptw[9].pmp[5].mask
invalidate io.ptw[9].pmp[5].addr
invalidate io.ptw[9].pmp[5].cfg.r
invalidate io.ptw[9].pmp[5].cfg.w
invalidate io.ptw[9].pmp[5].cfg.x
invalidate io.ptw[9].pmp[5].cfg.a
invalidate io.ptw[9].pmp[5].cfg.res
invalidate io.ptw[9].pmp[5].cfg.l
invalidate io.ptw[9].pmp[6].mask
invalidate io.ptw[9].pmp[6].addr
invalidate io.ptw[9].pmp[6].cfg.r
invalidate io.ptw[9].pmp[6].cfg.w
invalidate io.ptw[9].pmp[6].cfg.x
invalidate io.ptw[9].pmp[6].cfg.a
invalidate io.ptw[9].pmp[6].cfg.res
invalidate io.ptw[9].pmp[6].cfg.l
invalidate io.ptw[9].pmp[7].mask
invalidate io.ptw[9].pmp[7].addr
invalidate io.ptw[9].pmp[7].cfg.r
invalidate io.ptw[9].pmp[7].cfg.w
invalidate io.ptw[9].pmp[7].cfg.x
invalidate io.ptw[9].pmp[7].cfg.a
invalidate io.ptw[9].pmp[7].cfg.res
invalidate io.ptw[9].pmp[7].cfg.l
invalidate io.ptw[9].gstatus.uie
invalidate io.ptw[9].gstatus.sie
invalidate io.ptw[9].gstatus.hie
invalidate io.ptw[9].gstatus.mie
invalidate io.ptw[9].gstatus.upie
invalidate io.ptw[9].gstatus.spie
invalidate io.ptw[9].gstatus.ube
invalidate io.ptw[9].gstatus.mpie
invalidate io.ptw[9].gstatus.spp
invalidate io.ptw[9].gstatus.vs
invalidate io.ptw[9].gstatus.mpp
invalidate io.ptw[9].gstatus.fs
invalidate io.ptw[9].gstatus.xs
invalidate io.ptw[9].gstatus.mprv
invalidate io.ptw[9].gstatus.sum
invalidate io.ptw[9].gstatus.mxr
invalidate io.ptw[9].gstatus.tvm
invalidate io.ptw[9].gstatus.tw
invalidate io.ptw[9].gstatus.tsr
invalidate io.ptw[9].gstatus.zero1
invalidate io.ptw[9].gstatus.sd_rv32
invalidate io.ptw[9].gstatus.uxl
invalidate io.ptw[9].gstatus.sxl
invalidate io.ptw[9].gstatus.sbe
invalidate io.ptw[9].gstatus.mbe
invalidate io.ptw[9].gstatus.gva
invalidate io.ptw[9].gstatus.mpv
invalidate io.ptw[9].gstatus.zero2
invalidate io.ptw[9].gstatus.sd
invalidate io.ptw[9].gstatus.v
invalidate io.ptw[9].gstatus.prv
invalidate io.ptw[9].gstatus.dv
invalidate io.ptw[9].gstatus.dprv
invalidate io.ptw[9].gstatus.isa
invalidate io.ptw[9].gstatus.wfi
invalidate io.ptw[9].gstatus.cease
invalidate io.ptw[9].gstatus.debug
invalidate io.ptw[9].hstatus.zero1
invalidate io.ptw[9].hstatus.vsbe
invalidate io.ptw[9].hstatus.gva
invalidate io.ptw[9].hstatus.spv
invalidate io.ptw[9].hstatus.spvp
invalidate io.ptw[9].hstatus.hu
invalidate io.ptw[9].hstatus.zero2
invalidate io.ptw[9].hstatus.vgein
invalidate io.ptw[9].hstatus.zero3
invalidate io.ptw[9].hstatus.vtvm
invalidate io.ptw[9].hstatus.vtw
invalidate io.ptw[9].hstatus.vtsr
invalidate io.ptw[9].hstatus.zero5
invalidate io.ptw[9].hstatus.vsxl
invalidate io.ptw[9].hstatus.zero6
invalidate io.ptw[9].status.uie
invalidate io.ptw[9].status.sie
invalidate io.ptw[9].status.hie
invalidate io.ptw[9].status.mie
invalidate io.ptw[9].status.upie
invalidate io.ptw[9].status.spie
invalidate io.ptw[9].status.ube
invalidate io.ptw[9].status.mpie
invalidate io.ptw[9].status.spp
invalidate io.ptw[9].status.vs
invalidate io.ptw[9].status.mpp
invalidate io.ptw[9].status.fs
invalidate io.ptw[9].status.xs
invalidate io.ptw[9].status.mprv
invalidate io.ptw[9].status.sum
invalidate io.ptw[9].status.mxr
invalidate io.ptw[9].status.tvm
invalidate io.ptw[9].status.tw
invalidate io.ptw[9].status.tsr
invalidate io.ptw[9].status.zero1
invalidate io.ptw[9].status.sd_rv32
invalidate io.ptw[9].status.uxl
invalidate io.ptw[9].status.sxl
invalidate io.ptw[9].status.sbe
invalidate io.ptw[9].status.mbe
invalidate io.ptw[9].status.gva
invalidate io.ptw[9].status.mpv
invalidate io.ptw[9].status.zero2
invalidate io.ptw[9].status.sd
invalidate io.ptw[9].status.v
invalidate io.ptw[9].status.prv
invalidate io.ptw[9].status.dv
invalidate io.ptw[9].status.dprv
invalidate io.ptw[9].status.isa
invalidate io.ptw[9].status.wfi
invalidate io.ptw[9].status.cease
invalidate io.ptw[9].status.debug
invalidate io.ptw[9].vsatp.ppn
invalidate io.ptw[9].vsatp.asid
invalidate io.ptw[9].vsatp.mode
invalidate io.ptw[9].hgatp.ppn
invalidate io.ptw[9].hgatp.asid
invalidate io.ptw[9].hgatp.mode
invalidate io.ptw[9].ptbr.ppn
invalidate io.ptw[9].ptbr.asid
invalidate io.ptw[9].ptbr.mode
invalidate io.ptw[9].resp.bits.gpa_is_pte
invalidate io.ptw[9].resp.bits.gpa.bits
invalidate io.ptw[9].resp.bits.gpa.valid
invalidate io.ptw[9].resp.bits.homogeneous
invalidate io.ptw[9].resp.bits.fragmented_superpage
invalidate io.ptw[9].resp.bits.level
invalidate io.ptw[9].resp.bits.pte.v
invalidate io.ptw[9].resp.bits.pte.r
invalidate io.ptw[9].resp.bits.pte.w
invalidate io.ptw[9].resp.bits.pte.x
invalidate io.ptw[9].resp.bits.pte.u
invalidate io.ptw[9].resp.bits.pte.g
invalidate io.ptw[9].resp.bits.pte.a
invalidate io.ptw[9].resp.bits.pte.d
invalidate io.ptw[9].resp.bits.pte.reserved_for_software
invalidate io.ptw[9].resp.bits.pte.ppn
invalidate io.ptw[9].resp.bits.pte.reserved_for_future
invalidate io.ptw[9].resp.bits.hx
invalidate io.ptw[9].resp.bits.hw
invalidate io.ptw[9].resp.bits.hr
invalidate io.ptw[9].resp.bits.gf
invalidate io.ptw[9].resp.bits.pf
invalidate io.ptw[9].resp.bits.ae_final
invalidate io.ptw[9].resp.bits.ae_ptw
invalidate io.ptw[9].resp.valid
invalidate io.ptw[9].req.bits.bits.stage2
invalidate io.ptw[9].req.bits.bits.vstage1
invalidate io.ptw[9].req.bits.bits.need_gpa
invalidate io.ptw[9].req.bits.bits.addr
invalidate io.ptw[9].req.bits.valid
invalidate io.ptw[9].req.valid
invalidate io.ptw[9].req.ready
invalidate io.ptw[10].customCSRs.csrs[0].sdata
invalidate io.ptw[10].customCSRs.csrs[0].set
invalidate io.ptw[10].customCSRs.csrs[0].stall
invalidate io.ptw[10].customCSRs.csrs[0].value
invalidate io.ptw[10].customCSRs.csrs[0].wdata
invalidate io.ptw[10].customCSRs.csrs[0].wen
invalidate io.ptw[10].customCSRs.csrs[0].ren
invalidate io.ptw[10].customCSRs.csrs[1].sdata
invalidate io.ptw[10].customCSRs.csrs[1].set
invalidate io.ptw[10].customCSRs.csrs[1].stall
invalidate io.ptw[10].customCSRs.csrs[1].value
invalidate io.ptw[10].customCSRs.csrs[1].wdata
invalidate io.ptw[10].customCSRs.csrs[1].wen
invalidate io.ptw[10].customCSRs.csrs[1].ren
invalidate io.ptw[10].customCSRs.csrs[2].sdata
invalidate io.ptw[10].customCSRs.csrs[2].set
invalidate io.ptw[10].customCSRs.csrs[2].stall
invalidate io.ptw[10].customCSRs.csrs[2].value
invalidate io.ptw[10].customCSRs.csrs[2].wdata
invalidate io.ptw[10].customCSRs.csrs[2].wen
invalidate io.ptw[10].customCSRs.csrs[2].ren
invalidate io.ptw[10].customCSRs.csrs[3].sdata
invalidate io.ptw[10].customCSRs.csrs[3].set
invalidate io.ptw[10].customCSRs.csrs[3].stall
invalidate io.ptw[10].customCSRs.csrs[3].value
invalidate io.ptw[10].customCSRs.csrs[3].wdata
invalidate io.ptw[10].customCSRs.csrs[3].wen
invalidate io.ptw[10].customCSRs.csrs[3].ren
invalidate io.ptw[10].pmp[0].mask
invalidate io.ptw[10].pmp[0].addr
invalidate io.ptw[10].pmp[0].cfg.r
invalidate io.ptw[10].pmp[0].cfg.w
invalidate io.ptw[10].pmp[0].cfg.x
invalidate io.ptw[10].pmp[0].cfg.a
invalidate io.ptw[10].pmp[0].cfg.res
invalidate io.ptw[10].pmp[0].cfg.l
invalidate io.ptw[10].pmp[1].mask
invalidate io.ptw[10].pmp[1].addr
invalidate io.ptw[10].pmp[1].cfg.r
invalidate io.ptw[10].pmp[1].cfg.w
invalidate io.ptw[10].pmp[1].cfg.x
invalidate io.ptw[10].pmp[1].cfg.a
invalidate io.ptw[10].pmp[1].cfg.res
invalidate io.ptw[10].pmp[1].cfg.l
invalidate io.ptw[10].pmp[2].mask
invalidate io.ptw[10].pmp[2].addr
invalidate io.ptw[10].pmp[2].cfg.r
invalidate io.ptw[10].pmp[2].cfg.w
invalidate io.ptw[10].pmp[2].cfg.x
invalidate io.ptw[10].pmp[2].cfg.a
invalidate io.ptw[10].pmp[2].cfg.res
invalidate io.ptw[10].pmp[2].cfg.l
invalidate io.ptw[10].pmp[3].mask
invalidate io.ptw[10].pmp[3].addr
invalidate io.ptw[10].pmp[3].cfg.r
invalidate io.ptw[10].pmp[3].cfg.w
invalidate io.ptw[10].pmp[3].cfg.x
invalidate io.ptw[10].pmp[3].cfg.a
invalidate io.ptw[10].pmp[3].cfg.res
invalidate io.ptw[10].pmp[3].cfg.l
invalidate io.ptw[10].pmp[4].mask
invalidate io.ptw[10].pmp[4].addr
invalidate io.ptw[10].pmp[4].cfg.r
invalidate io.ptw[10].pmp[4].cfg.w
invalidate io.ptw[10].pmp[4].cfg.x
invalidate io.ptw[10].pmp[4].cfg.a
invalidate io.ptw[10].pmp[4].cfg.res
invalidate io.ptw[10].pmp[4].cfg.l
invalidate io.ptw[10].pmp[5].mask
invalidate io.ptw[10].pmp[5].addr
invalidate io.ptw[10].pmp[5].cfg.r
invalidate io.ptw[10].pmp[5].cfg.w
invalidate io.ptw[10].pmp[5].cfg.x
invalidate io.ptw[10].pmp[5].cfg.a
invalidate io.ptw[10].pmp[5].cfg.res
invalidate io.ptw[10].pmp[5].cfg.l
invalidate io.ptw[10].pmp[6].mask
invalidate io.ptw[10].pmp[6].addr
invalidate io.ptw[10].pmp[6].cfg.r
invalidate io.ptw[10].pmp[6].cfg.w
invalidate io.ptw[10].pmp[6].cfg.x
invalidate io.ptw[10].pmp[6].cfg.a
invalidate io.ptw[10].pmp[6].cfg.res
invalidate io.ptw[10].pmp[6].cfg.l
invalidate io.ptw[10].pmp[7].mask
invalidate io.ptw[10].pmp[7].addr
invalidate io.ptw[10].pmp[7].cfg.r
invalidate io.ptw[10].pmp[7].cfg.w
invalidate io.ptw[10].pmp[7].cfg.x
invalidate io.ptw[10].pmp[7].cfg.a
invalidate io.ptw[10].pmp[7].cfg.res
invalidate io.ptw[10].pmp[7].cfg.l
invalidate io.ptw[10].gstatus.uie
invalidate io.ptw[10].gstatus.sie
invalidate io.ptw[10].gstatus.hie
invalidate io.ptw[10].gstatus.mie
invalidate io.ptw[10].gstatus.upie
invalidate io.ptw[10].gstatus.spie
invalidate io.ptw[10].gstatus.ube
invalidate io.ptw[10].gstatus.mpie
invalidate io.ptw[10].gstatus.spp
invalidate io.ptw[10].gstatus.vs
invalidate io.ptw[10].gstatus.mpp
invalidate io.ptw[10].gstatus.fs
invalidate io.ptw[10].gstatus.xs
invalidate io.ptw[10].gstatus.mprv
invalidate io.ptw[10].gstatus.sum
invalidate io.ptw[10].gstatus.mxr
invalidate io.ptw[10].gstatus.tvm
invalidate io.ptw[10].gstatus.tw
invalidate io.ptw[10].gstatus.tsr
invalidate io.ptw[10].gstatus.zero1
invalidate io.ptw[10].gstatus.sd_rv32
invalidate io.ptw[10].gstatus.uxl
invalidate io.ptw[10].gstatus.sxl
invalidate io.ptw[10].gstatus.sbe
invalidate io.ptw[10].gstatus.mbe
invalidate io.ptw[10].gstatus.gva
invalidate io.ptw[10].gstatus.mpv
invalidate io.ptw[10].gstatus.zero2
invalidate io.ptw[10].gstatus.sd
invalidate io.ptw[10].gstatus.v
invalidate io.ptw[10].gstatus.prv
invalidate io.ptw[10].gstatus.dv
invalidate io.ptw[10].gstatus.dprv
invalidate io.ptw[10].gstatus.isa
invalidate io.ptw[10].gstatus.wfi
invalidate io.ptw[10].gstatus.cease
invalidate io.ptw[10].gstatus.debug
invalidate io.ptw[10].hstatus.zero1
invalidate io.ptw[10].hstatus.vsbe
invalidate io.ptw[10].hstatus.gva
invalidate io.ptw[10].hstatus.spv
invalidate io.ptw[10].hstatus.spvp
invalidate io.ptw[10].hstatus.hu
invalidate io.ptw[10].hstatus.zero2
invalidate io.ptw[10].hstatus.vgein
invalidate io.ptw[10].hstatus.zero3
invalidate io.ptw[10].hstatus.vtvm
invalidate io.ptw[10].hstatus.vtw
invalidate io.ptw[10].hstatus.vtsr
invalidate io.ptw[10].hstatus.zero5
invalidate io.ptw[10].hstatus.vsxl
invalidate io.ptw[10].hstatus.zero6
invalidate io.ptw[10].status.uie
invalidate io.ptw[10].status.sie
invalidate io.ptw[10].status.hie
invalidate io.ptw[10].status.mie
invalidate io.ptw[10].status.upie
invalidate io.ptw[10].status.spie
invalidate io.ptw[10].status.ube
invalidate io.ptw[10].status.mpie
invalidate io.ptw[10].status.spp
invalidate io.ptw[10].status.vs
invalidate io.ptw[10].status.mpp
invalidate io.ptw[10].status.fs
invalidate io.ptw[10].status.xs
invalidate io.ptw[10].status.mprv
invalidate io.ptw[10].status.sum
invalidate io.ptw[10].status.mxr
invalidate io.ptw[10].status.tvm
invalidate io.ptw[10].status.tw
invalidate io.ptw[10].status.tsr
invalidate io.ptw[10].status.zero1
invalidate io.ptw[10].status.sd_rv32
invalidate io.ptw[10].status.uxl
invalidate io.ptw[10].status.sxl
invalidate io.ptw[10].status.sbe
invalidate io.ptw[10].status.mbe
invalidate io.ptw[10].status.gva
invalidate io.ptw[10].status.mpv
invalidate io.ptw[10].status.zero2
invalidate io.ptw[10].status.sd
invalidate io.ptw[10].status.v
invalidate io.ptw[10].status.prv
invalidate io.ptw[10].status.dv
invalidate io.ptw[10].status.dprv
invalidate io.ptw[10].status.isa
invalidate io.ptw[10].status.wfi
invalidate io.ptw[10].status.cease
invalidate io.ptw[10].status.debug
invalidate io.ptw[10].vsatp.ppn
invalidate io.ptw[10].vsatp.asid
invalidate io.ptw[10].vsatp.mode
invalidate io.ptw[10].hgatp.ppn
invalidate io.ptw[10].hgatp.asid
invalidate io.ptw[10].hgatp.mode
invalidate io.ptw[10].ptbr.ppn
invalidate io.ptw[10].ptbr.asid
invalidate io.ptw[10].ptbr.mode
invalidate io.ptw[10].resp.bits.gpa_is_pte
invalidate io.ptw[10].resp.bits.gpa.bits
invalidate io.ptw[10].resp.bits.gpa.valid
invalidate io.ptw[10].resp.bits.homogeneous
invalidate io.ptw[10].resp.bits.fragmented_superpage
invalidate io.ptw[10].resp.bits.level
invalidate io.ptw[10].resp.bits.pte.v
invalidate io.ptw[10].resp.bits.pte.r
invalidate io.ptw[10].resp.bits.pte.w
invalidate io.ptw[10].resp.bits.pte.x
invalidate io.ptw[10].resp.bits.pte.u
invalidate io.ptw[10].resp.bits.pte.g
invalidate io.ptw[10].resp.bits.pte.a
invalidate io.ptw[10].resp.bits.pte.d
invalidate io.ptw[10].resp.bits.pte.reserved_for_software
invalidate io.ptw[10].resp.bits.pte.ppn
invalidate io.ptw[10].resp.bits.pte.reserved_for_future
invalidate io.ptw[10].resp.bits.hx
invalidate io.ptw[10].resp.bits.hw
invalidate io.ptw[10].resp.bits.hr
invalidate io.ptw[10].resp.bits.gf
invalidate io.ptw[10].resp.bits.pf
invalidate io.ptw[10].resp.bits.ae_final
invalidate io.ptw[10].resp.bits.ae_ptw
invalidate io.ptw[10].resp.valid
invalidate io.ptw[10].req.bits.bits.stage2
invalidate io.ptw[10].req.bits.bits.vstage1
invalidate io.ptw[10].req.bits.bits.need_gpa
invalidate io.ptw[10].req.bits.bits.addr
invalidate io.ptw[10].req.bits.valid
invalidate io.ptw[10].req.valid
invalidate io.ptw[10].req.ready
invalidate io.ptw[11].customCSRs.csrs[0].sdata
invalidate io.ptw[11].customCSRs.csrs[0].set
invalidate io.ptw[11].customCSRs.csrs[0].stall
invalidate io.ptw[11].customCSRs.csrs[0].value
invalidate io.ptw[11].customCSRs.csrs[0].wdata
invalidate io.ptw[11].customCSRs.csrs[0].wen
invalidate io.ptw[11].customCSRs.csrs[0].ren
invalidate io.ptw[11].customCSRs.csrs[1].sdata
invalidate io.ptw[11].customCSRs.csrs[1].set
invalidate io.ptw[11].customCSRs.csrs[1].stall
invalidate io.ptw[11].customCSRs.csrs[1].value
invalidate io.ptw[11].customCSRs.csrs[1].wdata
invalidate io.ptw[11].customCSRs.csrs[1].wen
invalidate io.ptw[11].customCSRs.csrs[1].ren
invalidate io.ptw[11].customCSRs.csrs[2].sdata
invalidate io.ptw[11].customCSRs.csrs[2].set
invalidate io.ptw[11].customCSRs.csrs[2].stall
invalidate io.ptw[11].customCSRs.csrs[2].value
invalidate io.ptw[11].customCSRs.csrs[2].wdata
invalidate io.ptw[11].customCSRs.csrs[2].wen
invalidate io.ptw[11].customCSRs.csrs[2].ren
invalidate io.ptw[11].customCSRs.csrs[3].sdata
invalidate io.ptw[11].customCSRs.csrs[3].set
invalidate io.ptw[11].customCSRs.csrs[3].stall
invalidate io.ptw[11].customCSRs.csrs[3].value
invalidate io.ptw[11].customCSRs.csrs[3].wdata
invalidate io.ptw[11].customCSRs.csrs[3].wen
invalidate io.ptw[11].customCSRs.csrs[3].ren
invalidate io.ptw[11].pmp[0].mask
invalidate io.ptw[11].pmp[0].addr
invalidate io.ptw[11].pmp[0].cfg.r
invalidate io.ptw[11].pmp[0].cfg.w
invalidate io.ptw[11].pmp[0].cfg.x
invalidate io.ptw[11].pmp[0].cfg.a
invalidate io.ptw[11].pmp[0].cfg.res
invalidate io.ptw[11].pmp[0].cfg.l
invalidate io.ptw[11].pmp[1].mask
invalidate io.ptw[11].pmp[1].addr
invalidate io.ptw[11].pmp[1].cfg.r
invalidate io.ptw[11].pmp[1].cfg.w
invalidate io.ptw[11].pmp[1].cfg.x
invalidate io.ptw[11].pmp[1].cfg.a
invalidate io.ptw[11].pmp[1].cfg.res
invalidate io.ptw[11].pmp[1].cfg.l
invalidate io.ptw[11].pmp[2].mask
invalidate io.ptw[11].pmp[2].addr
invalidate io.ptw[11].pmp[2].cfg.r
invalidate io.ptw[11].pmp[2].cfg.w
invalidate io.ptw[11].pmp[2].cfg.x
invalidate io.ptw[11].pmp[2].cfg.a
invalidate io.ptw[11].pmp[2].cfg.res
invalidate io.ptw[11].pmp[2].cfg.l
invalidate io.ptw[11].pmp[3].mask
invalidate io.ptw[11].pmp[3].addr
invalidate io.ptw[11].pmp[3].cfg.r
invalidate io.ptw[11].pmp[3].cfg.w
invalidate io.ptw[11].pmp[3].cfg.x
invalidate io.ptw[11].pmp[3].cfg.a
invalidate io.ptw[11].pmp[3].cfg.res
invalidate io.ptw[11].pmp[3].cfg.l
invalidate io.ptw[11].pmp[4].mask
invalidate io.ptw[11].pmp[4].addr
invalidate io.ptw[11].pmp[4].cfg.r
invalidate io.ptw[11].pmp[4].cfg.w
invalidate io.ptw[11].pmp[4].cfg.x
invalidate io.ptw[11].pmp[4].cfg.a
invalidate io.ptw[11].pmp[4].cfg.res
invalidate io.ptw[11].pmp[4].cfg.l
invalidate io.ptw[11].pmp[5].mask
invalidate io.ptw[11].pmp[5].addr
invalidate io.ptw[11].pmp[5].cfg.r
invalidate io.ptw[11].pmp[5].cfg.w
invalidate io.ptw[11].pmp[5].cfg.x
invalidate io.ptw[11].pmp[5].cfg.a
invalidate io.ptw[11].pmp[5].cfg.res
invalidate io.ptw[11].pmp[5].cfg.l
invalidate io.ptw[11].pmp[6].mask
invalidate io.ptw[11].pmp[6].addr
invalidate io.ptw[11].pmp[6].cfg.r
invalidate io.ptw[11].pmp[6].cfg.w
invalidate io.ptw[11].pmp[6].cfg.x
invalidate io.ptw[11].pmp[6].cfg.a
invalidate io.ptw[11].pmp[6].cfg.res
invalidate io.ptw[11].pmp[6].cfg.l
invalidate io.ptw[11].pmp[7].mask
invalidate io.ptw[11].pmp[7].addr
invalidate io.ptw[11].pmp[7].cfg.r
invalidate io.ptw[11].pmp[7].cfg.w
invalidate io.ptw[11].pmp[7].cfg.x
invalidate io.ptw[11].pmp[7].cfg.a
invalidate io.ptw[11].pmp[7].cfg.res
invalidate io.ptw[11].pmp[7].cfg.l
invalidate io.ptw[11].gstatus.uie
invalidate io.ptw[11].gstatus.sie
invalidate io.ptw[11].gstatus.hie
invalidate io.ptw[11].gstatus.mie
invalidate io.ptw[11].gstatus.upie
invalidate io.ptw[11].gstatus.spie
invalidate io.ptw[11].gstatus.ube
invalidate io.ptw[11].gstatus.mpie
invalidate io.ptw[11].gstatus.spp
invalidate io.ptw[11].gstatus.vs
invalidate io.ptw[11].gstatus.mpp
invalidate io.ptw[11].gstatus.fs
invalidate io.ptw[11].gstatus.xs
invalidate io.ptw[11].gstatus.mprv
invalidate io.ptw[11].gstatus.sum
invalidate io.ptw[11].gstatus.mxr
invalidate io.ptw[11].gstatus.tvm
invalidate io.ptw[11].gstatus.tw
invalidate io.ptw[11].gstatus.tsr
invalidate io.ptw[11].gstatus.zero1
invalidate io.ptw[11].gstatus.sd_rv32
invalidate io.ptw[11].gstatus.uxl
invalidate io.ptw[11].gstatus.sxl
invalidate io.ptw[11].gstatus.sbe
invalidate io.ptw[11].gstatus.mbe
invalidate io.ptw[11].gstatus.gva
invalidate io.ptw[11].gstatus.mpv
invalidate io.ptw[11].gstatus.zero2
invalidate io.ptw[11].gstatus.sd
invalidate io.ptw[11].gstatus.v
invalidate io.ptw[11].gstatus.prv
invalidate io.ptw[11].gstatus.dv
invalidate io.ptw[11].gstatus.dprv
invalidate io.ptw[11].gstatus.isa
invalidate io.ptw[11].gstatus.wfi
invalidate io.ptw[11].gstatus.cease
invalidate io.ptw[11].gstatus.debug
invalidate io.ptw[11].hstatus.zero1
invalidate io.ptw[11].hstatus.vsbe
invalidate io.ptw[11].hstatus.gva
invalidate io.ptw[11].hstatus.spv
invalidate io.ptw[11].hstatus.spvp
invalidate io.ptw[11].hstatus.hu
invalidate io.ptw[11].hstatus.zero2
invalidate io.ptw[11].hstatus.vgein
invalidate io.ptw[11].hstatus.zero3
invalidate io.ptw[11].hstatus.vtvm
invalidate io.ptw[11].hstatus.vtw
invalidate io.ptw[11].hstatus.vtsr
invalidate io.ptw[11].hstatus.zero5
invalidate io.ptw[11].hstatus.vsxl
invalidate io.ptw[11].hstatus.zero6
invalidate io.ptw[11].status.uie
invalidate io.ptw[11].status.sie
invalidate io.ptw[11].status.hie
invalidate io.ptw[11].status.mie
invalidate io.ptw[11].status.upie
invalidate io.ptw[11].status.spie
invalidate io.ptw[11].status.ube
invalidate io.ptw[11].status.mpie
invalidate io.ptw[11].status.spp
invalidate io.ptw[11].status.vs
invalidate io.ptw[11].status.mpp
invalidate io.ptw[11].status.fs
invalidate io.ptw[11].status.xs
invalidate io.ptw[11].status.mprv
invalidate io.ptw[11].status.sum
invalidate io.ptw[11].status.mxr
invalidate io.ptw[11].status.tvm
invalidate io.ptw[11].status.tw
invalidate io.ptw[11].status.tsr
invalidate io.ptw[11].status.zero1
invalidate io.ptw[11].status.sd_rv32
invalidate io.ptw[11].status.uxl
invalidate io.ptw[11].status.sxl
invalidate io.ptw[11].status.sbe
invalidate io.ptw[11].status.mbe
invalidate io.ptw[11].status.gva
invalidate io.ptw[11].status.mpv
invalidate io.ptw[11].status.zero2
invalidate io.ptw[11].status.sd
invalidate io.ptw[11].status.v
invalidate io.ptw[11].status.prv
invalidate io.ptw[11].status.dv
invalidate io.ptw[11].status.dprv
invalidate io.ptw[11].status.isa
invalidate io.ptw[11].status.wfi
invalidate io.ptw[11].status.cease
invalidate io.ptw[11].status.debug
invalidate io.ptw[11].vsatp.ppn
invalidate io.ptw[11].vsatp.asid
invalidate io.ptw[11].vsatp.mode
invalidate io.ptw[11].hgatp.ppn
invalidate io.ptw[11].hgatp.asid
invalidate io.ptw[11].hgatp.mode
invalidate io.ptw[11].ptbr.ppn
invalidate io.ptw[11].ptbr.asid
invalidate io.ptw[11].ptbr.mode
invalidate io.ptw[11].resp.bits.gpa_is_pte
invalidate io.ptw[11].resp.bits.gpa.bits
invalidate io.ptw[11].resp.bits.gpa.valid
invalidate io.ptw[11].resp.bits.homogeneous
invalidate io.ptw[11].resp.bits.fragmented_superpage
invalidate io.ptw[11].resp.bits.level
invalidate io.ptw[11].resp.bits.pte.v
invalidate io.ptw[11].resp.bits.pte.r
invalidate io.ptw[11].resp.bits.pte.w
invalidate io.ptw[11].resp.bits.pte.x
invalidate io.ptw[11].resp.bits.pte.u
invalidate io.ptw[11].resp.bits.pte.g
invalidate io.ptw[11].resp.bits.pte.a
invalidate io.ptw[11].resp.bits.pte.d
invalidate io.ptw[11].resp.bits.pte.reserved_for_software
invalidate io.ptw[11].resp.bits.pte.ppn
invalidate io.ptw[11].resp.bits.pte.reserved_for_future
invalidate io.ptw[11].resp.bits.hx
invalidate io.ptw[11].resp.bits.hw
invalidate io.ptw[11].resp.bits.hr
invalidate io.ptw[11].resp.bits.gf
invalidate io.ptw[11].resp.bits.pf
invalidate io.ptw[11].resp.bits.ae_final
invalidate io.ptw[11].resp.bits.ae_ptw
invalidate io.ptw[11].resp.valid
invalidate io.ptw[11].req.bits.bits.stage2
invalidate io.ptw[11].req.bits.bits.vstage1
invalidate io.ptw[11].req.bits.bits.need_gpa
invalidate io.ptw[11].req.bits.bits.addr
invalidate io.ptw[11].req.bits.valid
invalidate io.ptw[11].req.valid
invalidate io.ptw[11].req.ready
invalidate io.ptw[12].customCSRs.csrs[0].sdata
invalidate io.ptw[12].customCSRs.csrs[0].set
invalidate io.ptw[12].customCSRs.csrs[0].stall
invalidate io.ptw[12].customCSRs.csrs[0].value
invalidate io.ptw[12].customCSRs.csrs[0].wdata
invalidate io.ptw[12].customCSRs.csrs[0].wen
invalidate io.ptw[12].customCSRs.csrs[0].ren
invalidate io.ptw[12].customCSRs.csrs[1].sdata
invalidate io.ptw[12].customCSRs.csrs[1].set
invalidate io.ptw[12].customCSRs.csrs[1].stall
invalidate io.ptw[12].customCSRs.csrs[1].value
invalidate io.ptw[12].customCSRs.csrs[1].wdata
invalidate io.ptw[12].customCSRs.csrs[1].wen
invalidate io.ptw[12].customCSRs.csrs[1].ren
invalidate io.ptw[12].customCSRs.csrs[2].sdata
invalidate io.ptw[12].customCSRs.csrs[2].set
invalidate io.ptw[12].customCSRs.csrs[2].stall
invalidate io.ptw[12].customCSRs.csrs[2].value
invalidate io.ptw[12].customCSRs.csrs[2].wdata
invalidate io.ptw[12].customCSRs.csrs[2].wen
invalidate io.ptw[12].customCSRs.csrs[2].ren
invalidate io.ptw[12].customCSRs.csrs[3].sdata
invalidate io.ptw[12].customCSRs.csrs[3].set
invalidate io.ptw[12].customCSRs.csrs[3].stall
invalidate io.ptw[12].customCSRs.csrs[3].value
invalidate io.ptw[12].customCSRs.csrs[3].wdata
invalidate io.ptw[12].customCSRs.csrs[3].wen
invalidate io.ptw[12].customCSRs.csrs[3].ren
invalidate io.ptw[12].pmp[0].mask
invalidate io.ptw[12].pmp[0].addr
invalidate io.ptw[12].pmp[0].cfg.r
invalidate io.ptw[12].pmp[0].cfg.w
invalidate io.ptw[12].pmp[0].cfg.x
invalidate io.ptw[12].pmp[0].cfg.a
invalidate io.ptw[12].pmp[0].cfg.res
invalidate io.ptw[12].pmp[0].cfg.l
invalidate io.ptw[12].pmp[1].mask
invalidate io.ptw[12].pmp[1].addr
invalidate io.ptw[12].pmp[1].cfg.r
invalidate io.ptw[12].pmp[1].cfg.w
invalidate io.ptw[12].pmp[1].cfg.x
invalidate io.ptw[12].pmp[1].cfg.a
invalidate io.ptw[12].pmp[1].cfg.res
invalidate io.ptw[12].pmp[1].cfg.l
invalidate io.ptw[12].pmp[2].mask
invalidate io.ptw[12].pmp[2].addr
invalidate io.ptw[12].pmp[2].cfg.r
invalidate io.ptw[12].pmp[2].cfg.w
invalidate io.ptw[12].pmp[2].cfg.x
invalidate io.ptw[12].pmp[2].cfg.a
invalidate io.ptw[12].pmp[2].cfg.res
invalidate io.ptw[12].pmp[2].cfg.l
invalidate io.ptw[12].pmp[3].mask
invalidate io.ptw[12].pmp[3].addr
invalidate io.ptw[12].pmp[3].cfg.r
invalidate io.ptw[12].pmp[3].cfg.w
invalidate io.ptw[12].pmp[3].cfg.x
invalidate io.ptw[12].pmp[3].cfg.a
invalidate io.ptw[12].pmp[3].cfg.res
invalidate io.ptw[12].pmp[3].cfg.l
invalidate io.ptw[12].pmp[4].mask
invalidate io.ptw[12].pmp[4].addr
invalidate io.ptw[12].pmp[4].cfg.r
invalidate io.ptw[12].pmp[4].cfg.w
invalidate io.ptw[12].pmp[4].cfg.x
invalidate io.ptw[12].pmp[4].cfg.a
invalidate io.ptw[12].pmp[4].cfg.res
invalidate io.ptw[12].pmp[4].cfg.l
invalidate io.ptw[12].pmp[5].mask
invalidate io.ptw[12].pmp[5].addr
invalidate io.ptw[12].pmp[5].cfg.r
invalidate io.ptw[12].pmp[5].cfg.w
invalidate io.ptw[12].pmp[5].cfg.x
invalidate io.ptw[12].pmp[5].cfg.a
invalidate io.ptw[12].pmp[5].cfg.res
invalidate io.ptw[12].pmp[5].cfg.l
invalidate io.ptw[12].pmp[6].mask
invalidate io.ptw[12].pmp[6].addr
invalidate io.ptw[12].pmp[6].cfg.r
invalidate io.ptw[12].pmp[6].cfg.w
invalidate io.ptw[12].pmp[6].cfg.x
invalidate io.ptw[12].pmp[6].cfg.a
invalidate io.ptw[12].pmp[6].cfg.res
invalidate io.ptw[12].pmp[6].cfg.l
invalidate io.ptw[12].pmp[7].mask
invalidate io.ptw[12].pmp[7].addr
invalidate io.ptw[12].pmp[7].cfg.r
invalidate io.ptw[12].pmp[7].cfg.w
invalidate io.ptw[12].pmp[7].cfg.x
invalidate io.ptw[12].pmp[7].cfg.a
invalidate io.ptw[12].pmp[7].cfg.res
invalidate io.ptw[12].pmp[7].cfg.l
invalidate io.ptw[12].gstatus.uie
invalidate io.ptw[12].gstatus.sie
invalidate io.ptw[12].gstatus.hie
invalidate io.ptw[12].gstatus.mie
invalidate io.ptw[12].gstatus.upie
invalidate io.ptw[12].gstatus.spie
invalidate io.ptw[12].gstatus.ube
invalidate io.ptw[12].gstatus.mpie
invalidate io.ptw[12].gstatus.spp
invalidate io.ptw[12].gstatus.vs
invalidate io.ptw[12].gstatus.mpp
invalidate io.ptw[12].gstatus.fs
invalidate io.ptw[12].gstatus.xs
invalidate io.ptw[12].gstatus.mprv
invalidate io.ptw[12].gstatus.sum
invalidate io.ptw[12].gstatus.mxr
invalidate io.ptw[12].gstatus.tvm
invalidate io.ptw[12].gstatus.tw
invalidate io.ptw[12].gstatus.tsr
invalidate io.ptw[12].gstatus.zero1
invalidate io.ptw[12].gstatus.sd_rv32
invalidate io.ptw[12].gstatus.uxl
invalidate io.ptw[12].gstatus.sxl
invalidate io.ptw[12].gstatus.sbe
invalidate io.ptw[12].gstatus.mbe
invalidate io.ptw[12].gstatus.gva
invalidate io.ptw[12].gstatus.mpv
invalidate io.ptw[12].gstatus.zero2
invalidate io.ptw[12].gstatus.sd
invalidate io.ptw[12].gstatus.v
invalidate io.ptw[12].gstatus.prv
invalidate io.ptw[12].gstatus.dv
invalidate io.ptw[12].gstatus.dprv
invalidate io.ptw[12].gstatus.isa
invalidate io.ptw[12].gstatus.wfi
invalidate io.ptw[12].gstatus.cease
invalidate io.ptw[12].gstatus.debug
invalidate io.ptw[12].hstatus.zero1
invalidate io.ptw[12].hstatus.vsbe
invalidate io.ptw[12].hstatus.gva
invalidate io.ptw[12].hstatus.spv
invalidate io.ptw[12].hstatus.spvp
invalidate io.ptw[12].hstatus.hu
invalidate io.ptw[12].hstatus.zero2
invalidate io.ptw[12].hstatus.vgein
invalidate io.ptw[12].hstatus.zero3
invalidate io.ptw[12].hstatus.vtvm
invalidate io.ptw[12].hstatus.vtw
invalidate io.ptw[12].hstatus.vtsr
invalidate io.ptw[12].hstatus.zero5
invalidate io.ptw[12].hstatus.vsxl
invalidate io.ptw[12].hstatus.zero6
invalidate io.ptw[12].status.uie
invalidate io.ptw[12].status.sie
invalidate io.ptw[12].status.hie
invalidate io.ptw[12].status.mie
invalidate io.ptw[12].status.upie
invalidate io.ptw[12].status.spie
invalidate io.ptw[12].status.ube
invalidate io.ptw[12].status.mpie
invalidate io.ptw[12].status.spp
invalidate io.ptw[12].status.vs
invalidate io.ptw[12].status.mpp
invalidate io.ptw[12].status.fs
invalidate io.ptw[12].status.xs
invalidate io.ptw[12].status.mprv
invalidate io.ptw[12].status.sum
invalidate io.ptw[12].status.mxr
invalidate io.ptw[12].status.tvm
invalidate io.ptw[12].status.tw
invalidate io.ptw[12].status.tsr
invalidate io.ptw[12].status.zero1
invalidate io.ptw[12].status.sd_rv32
invalidate io.ptw[12].status.uxl
invalidate io.ptw[12].status.sxl
invalidate io.ptw[12].status.sbe
invalidate io.ptw[12].status.mbe
invalidate io.ptw[12].status.gva
invalidate io.ptw[12].status.mpv
invalidate io.ptw[12].status.zero2
invalidate io.ptw[12].status.sd
invalidate io.ptw[12].status.v
invalidate io.ptw[12].status.prv
invalidate io.ptw[12].status.dv
invalidate io.ptw[12].status.dprv
invalidate io.ptw[12].status.isa
invalidate io.ptw[12].status.wfi
invalidate io.ptw[12].status.cease
invalidate io.ptw[12].status.debug
invalidate io.ptw[12].vsatp.ppn
invalidate io.ptw[12].vsatp.asid
invalidate io.ptw[12].vsatp.mode
invalidate io.ptw[12].hgatp.ppn
invalidate io.ptw[12].hgatp.asid
invalidate io.ptw[12].hgatp.mode
invalidate io.ptw[12].ptbr.ppn
invalidate io.ptw[12].ptbr.asid
invalidate io.ptw[12].ptbr.mode
invalidate io.ptw[12].resp.bits.gpa_is_pte
invalidate io.ptw[12].resp.bits.gpa.bits
invalidate io.ptw[12].resp.bits.gpa.valid
invalidate io.ptw[12].resp.bits.homogeneous
invalidate io.ptw[12].resp.bits.fragmented_superpage
invalidate io.ptw[12].resp.bits.level
invalidate io.ptw[12].resp.bits.pte.v
invalidate io.ptw[12].resp.bits.pte.r
invalidate io.ptw[12].resp.bits.pte.w
invalidate io.ptw[12].resp.bits.pte.x
invalidate io.ptw[12].resp.bits.pte.u
invalidate io.ptw[12].resp.bits.pte.g
invalidate io.ptw[12].resp.bits.pte.a
invalidate io.ptw[12].resp.bits.pte.d
invalidate io.ptw[12].resp.bits.pte.reserved_for_software
invalidate io.ptw[12].resp.bits.pte.ppn
invalidate io.ptw[12].resp.bits.pte.reserved_for_future
invalidate io.ptw[12].resp.bits.hx
invalidate io.ptw[12].resp.bits.hw
invalidate io.ptw[12].resp.bits.hr
invalidate io.ptw[12].resp.bits.gf
invalidate io.ptw[12].resp.bits.pf
invalidate io.ptw[12].resp.bits.ae_final
invalidate io.ptw[12].resp.bits.ae_ptw
invalidate io.ptw[12].resp.valid
invalidate io.ptw[12].req.bits.bits.stage2
invalidate io.ptw[12].req.bits.bits.vstage1
invalidate io.ptw[12].req.bits.bits.need_gpa
invalidate io.ptw[12].req.bits.bits.addr
invalidate io.ptw[12].req.bits.valid
invalidate io.ptw[12].req.valid
invalidate io.ptw[12].req.ready
invalidate io.ptw[13].customCSRs.csrs[0].sdata
invalidate io.ptw[13].customCSRs.csrs[0].set
invalidate io.ptw[13].customCSRs.csrs[0].stall
invalidate io.ptw[13].customCSRs.csrs[0].value
invalidate io.ptw[13].customCSRs.csrs[0].wdata
invalidate io.ptw[13].customCSRs.csrs[0].wen
invalidate io.ptw[13].customCSRs.csrs[0].ren
invalidate io.ptw[13].customCSRs.csrs[1].sdata
invalidate io.ptw[13].customCSRs.csrs[1].set
invalidate io.ptw[13].customCSRs.csrs[1].stall
invalidate io.ptw[13].customCSRs.csrs[1].value
invalidate io.ptw[13].customCSRs.csrs[1].wdata
invalidate io.ptw[13].customCSRs.csrs[1].wen
invalidate io.ptw[13].customCSRs.csrs[1].ren
invalidate io.ptw[13].customCSRs.csrs[2].sdata
invalidate io.ptw[13].customCSRs.csrs[2].set
invalidate io.ptw[13].customCSRs.csrs[2].stall
invalidate io.ptw[13].customCSRs.csrs[2].value
invalidate io.ptw[13].customCSRs.csrs[2].wdata
invalidate io.ptw[13].customCSRs.csrs[2].wen
invalidate io.ptw[13].customCSRs.csrs[2].ren
invalidate io.ptw[13].customCSRs.csrs[3].sdata
invalidate io.ptw[13].customCSRs.csrs[3].set
invalidate io.ptw[13].customCSRs.csrs[3].stall
invalidate io.ptw[13].customCSRs.csrs[3].value
invalidate io.ptw[13].customCSRs.csrs[3].wdata
invalidate io.ptw[13].customCSRs.csrs[3].wen
invalidate io.ptw[13].customCSRs.csrs[3].ren
invalidate io.ptw[13].pmp[0].mask
invalidate io.ptw[13].pmp[0].addr
invalidate io.ptw[13].pmp[0].cfg.r
invalidate io.ptw[13].pmp[0].cfg.w
invalidate io.ptw[13].pmp[0].cfg.x
invalidate io.ptw[13].pmp[0].cfg.a
invalidate io.ptw[13].pmp[0].cfg.res
invalidate io.ptw[13].pmp[0].cfg.l
invalidate io.ptw[13].pmp[1].mask
invalidate io.ptw[13].pmp[1].addr
invalidate io.ptw[13].pmp[1].cfg.r
invalidate io.ptw[13].pmp[1].cfg.w
invalidate io.ptw[13].pmp[1].cfg.x
invalidate io.ptw[13].pmp[1].cfg.a
invalidate io.ptw[13].pmp[1].cfg.res
invalidate io.ptw[13].pmp[1].cfg.l
invalidate io.ptw[13].pmp[2].mask
invalidate io.ptw[13].pmp[2].addr
invalidate io.ptw[13].pmp[2].cfg.r
invalidate io.ptw[13].pmp[2].cfg.w
invalidate io.ptw[13].pmp[2].cfg.x
invalidate io.ptw[13].pmp[2].cfg.a
invalidate io.ptw[13].pmp[2].cfg.res
invalidate io.ptw[13].pmp[2].cfg.l
invalidate io.ptw[13].pmp[3].mask
invalidate io.ptw[13].pmp[3].addr
invalidate io.ptw[13].pmp[3].cfg.r
invalidate io.ptw[13].pmp[3].cfg.w
invalidate io.ptw[13].pmp[3].cfg.x
invalidate io.ptw[13].pmp[3].cfg.a
invalidate io.ptw[13].pmp[3].cfg.res
invalidate io.ptw[13].pmp[3].cfg.l
invalidate io.ptw[13].pmp[4].mask
invalidate io.ptw[13].pmp[4].addr
invalidate io.ptw[13].pmp[4].cfg.r
invalidate io.ptw[13].pmp[4].cfg.w
invalidate io.ptw[13].pmp[4].cfg.x
invalidate io.ptw[13].pmp[4].cfg.a
invalidate io.ptw[13].pmp[4].cfg.res
invalidate io.ptw[13].pmp[4].cfg.l
invalidate io.ptw[13].pmp[5].mask
invalidate io.ptw[13].pmp[5].addr
invalidate io.ptw[13].pmp[5].cfg.r
invalidate io.ptw[13].pmp[5].cfg.w
invalidate io.ptw[13].pmp[5].cfg.x
invalidate io.ptw[13].pmp[5].cfg.a
invalidate io.ptw[13].pmp[5].cfg.res
invalidate io.ptw[13].pmp[5].cfg.l
invalidate io.ptw[13].pmp[6].mask
invalidate io.ptw[13].pmp[6].addr
invalidate io.ptw[13].pmp[6].cfg.r
invalidate io.ptw[13].pmp[6].cfg.w
invalidate io.ptw[13].pmp[6].cfg.x
invalidate io.ptw[13].pmp[6].cfg.a
invalidate io.ptw[13].pmp[6].cfg.res
invalidate io.ptw[13].pmp[6].cfg.l
invalidate io.ptw[13].pmp[7].mask
invalidate io.ptw[13].pmp[7].addr
invalidate io.ptw[13].pmp[7].cfg.r
invalidate io.ptw[13].pmp[7].cfg.w
invalidate io.ptw[13].pmp[7].cfg.x
invalidate io.ptw[13].pmp[7].cfg.a
invalidate io.ptw[13].pmp[7].cfg.res
invalidate io.ptw[13].pmp[7].cfg.l
invalidate io.ptw[13].gstatus.uie
invalidate io.ptw[13].gstatus.sie
invalidate io.ptw[13].gstatus.hie
invalidate io.ptw[13].gstatus.mie
invalidate io.ptw[13].gstatus.upie
invalidate io.ptw[13].gstatus.spie
invalidate io.ptw[13].gstatus.ube
invalidate io.ptw[13].gstatus.mpie
invalidate io.ptw[13].gstatus.spp
invalidate io.ptw[13].gstatus.vs
invalidate io.ptw[13].gstatus.mpp
invalidate io.ptw[13].gstatus.fs
invalidate io.ptw[13].gstatus.xs
invalidate io.ptw[13].gstatus.mprv
invalidate io.ptw[13].gstatus.sum
invalidate io.ptw[13].gstatus.mxr
invalidate io.ptw[13].gstatus.tvm
invalidate io.ptw[13].gstatus.tw
invalidate io.ptw[13].gstatus.tsr
invalidate io.ptw[13].gstatus.zero1
invalidate io.ptw[13].gstatus.sd_rv32
invalidate io.ptw[13].gstatus.uxl
invalidate io.ptw[13].gstatus.sxl
invalidate io.ptw[13].gstatus.sbe
invalidate io.ptw[13].gstatus.mbe
invalidate io.ptw[13].gstatus.gva
invalidate io.ptw[13].gstatus.mpv
invalidate io.ptw[13].gstatus.zero2
invalidate io.ptw[13].gstatus.sd
invalidate io.ptw[13].gstatus.v
invalidate io.ptw[13].gstatus.prv
invalidate io.ptw[13].gstatus.dv
invalidate io.ptw[13].gstatus.dprv
invalidate io.ptw[13].gstatus.isa
invalidate io.ptw[13].gstatus.wfi
invalidate io.ptw[13].gstatus.cease
invalidate io.ptw[13].gstatus.debug
invalidate io.ptw[13].hstatus.zero1
invalidate io.ptw[13].hstatus.vsbe
invalidate io.ptw[13].hstatus.gva
invalidate io.ptw[13].hstatus.spv
invalidate io.ptw[13].hstatus.spvp
invalidate io.ptw[13].hstatus.hu
invalidate io.ptw[13].hstatus.zero2
invalidate io.ptw[13].hstatus.vgein
invalidate io.ptw[13].hstatus.zero3
invalidate io.ptw[13].hstatus.vtvm
invalidate io.ptw[13].hstatus.vtw
invalidate io.ptw[13].hstatus.vtsr
invalidate io.ptw[13].hstatus.zero5
invalidate io.ptw[13].hstatus.vsxl
invalidate io.ptw[13].hstatus.zero6
invalidate io.ptw[13].status.uie
invalidate io.ptw[13].status.sie
invalidate io.ptw[13].status.hie
invalidate io.ptw[13].status.mie
invalidate io.ptw[13].status.upie
invalidate io.ptw[13].status.spie
invalidate io.ptw[13].status.ube
invalidate io.ptw[13].status.mpie
invalidate io.ptw[13].status.spp
invalidate io.ptw[13].status.vs
invalidate io.ptw[13].status.mpp
invalidate io.ptw[13].status.fs
invalidate io.ptw[13].status.xs
invalidate io.ptw[13].status.mprv
invalidate io.ptw[13].status.sum
invalidate io.ptw[13].status.mxr
invalidate io.ptw[13].status.tvm
invalidate io.ptw[13].status.tw
invalidate io.ptw[13].status.tsr
invalidate io.ptw[13].status.zero1
invalidate io.ptw[13].status.sd_rv32
invalidate io.ptw[13].status.uxl
invalidate io.ptw[13].status.sxl
invalidate io.ptw[13].status.sbe
invalidate io.ptw[13].status.mbe
invalidate io.ptw[13].status.gva
invalidate io.ptw[13].status.mpv
invalidate io.ptw[13].status.zero2
invalidate io.ptw[13].status.sd
invalidate io.ptw[13].status.v
invalidate io.ptw[13].status.prv
invalidate io.ptw[13].status.dv
invalidate io.ptw[13].status.dprv
invalidate io.ptw[13].status.isa
invalidate io.ptw[13].status.wfi
invalidate io.ptw[13].status.cease
invalidate io.ptw[13].status.debug
invalidate io.ptw[13].vsatp.ppn
invalidate io.ptw[13].vsatp.asid
invalidate io.ptw[13].vsatp.mode
invalidate io.ptw[13].hgatp.ppn
invalidate io.ptw[13].hgatp.asid
invalidate io.ptw[13].hgatp.mode
invalidate io.ptw[13].ptbr.ppn
invalidate io.ptw[13].ptbr.asid
invalidate io.ptw[13].ptbr.mode
invalidate io.ptw[13].resp.bits.gpa_is_pte
invalidate io.ptw[13].resp.bits.gpa.bits
invalidate io.ptw[13].resp.bits.gpa.valid
invalidate io.ptw[13].resp.bits.homogeneous
invalidate io.ptw[13].resp.bits.fragmented_superpage
invalidate io.ptw[13].resp.bits.level
invalidate io.ptw[13].resp.bits.pte.v
invalidate io.ptw[13].resp.bits.pte.r
invalidate io.ptw[13].resp.bits.pte.w
invalidate io.ptw[13].resp.bits.pte.x
invalidate io.ptw[13].resp.bits.pte.u
invalidate io.ptw[13].resp.bits.pte.g
invalidate io.ptw[13].resp.bits.pte.a
invalidate io.ptw[13].resp.bits.pte.d
invalidate io.ptw[13].resp.bits.pte.reserved_for_software
invalidate io.ptw[13].resp.bits.pte.ppn
invalidate io.ptw[13].resp.bits.pte.reserved_for_future
invalidate io.ptw[13].resp.bits.hx
invalidate io.ptw[13].resp.bits.hw
invalidate io.ptw[13].resp.bits.hr
invalidate io.ptw[13].resp.bits.gf
invalidate io.ptw[13].resp.bits.pf
invalidate io.ptw[13].resp.bits.ae_final
invalidate io.ptw[13].resp.bits.ae_ptw
invalidate io.ptw[13].resp.valid
invalidate io.ptw[13].req.bits.bits.stage2
invalidate io.ptw[13].req.bits.bits.vstage1
invalidate io.ptw[13].req.bits.bits.need_gpa
invalidate io.ptw[13].req.bits.bits.addr
invalidate io.ptw[13].req.bits.valid
invalidate io.ptw[13].req.valid
invalidate io.ptw[13].req.ready
invalidate io.ptw[14].customCSRs.csrs[0].sdata
invalidate io.ptw[14].customCSRs.csrs[0].set
invalidate io.ptw[14].customCSRs.csrs[0].stall
invalidate io.ptw[14].customCSRs.csrs[0].value
invalidate io.ptw[14].customCSRs.csrs[0].wdata
invalidate io.ptw[14].customCSRs.csrs[0].wen
invalidate io.ptw[14].customCSRs.csrs[0].ren
invalidate io.ptw[14].customCSRs.csrs[1].sdata
invalidate io.ptw[14].customCSRs.csrs[1].set
invalidate io.ptw[14].customCSRs.csrs[1].stall
invalidate io.ptw[14].customCSRs.csrs[1].value
invalidate io.ptw[14].customCSRs.csrs[1].wdata
invalidate io.ptw[14].customCSRs.csrs[1].wen
invalidate io.ptw[14].customCSRs.csrs[1].ren
invalidate io.ptw[14].customCSRs.csrs[2].sdata
invalidate io.ptw[14].customCSRs.csrs[2].set
invalidate io.ptw[14].customCSRs.csrs[2].stall
invalidate io.ptw[14].customCSRs.csrs[2].value
invalidate io.ptw[14].customCSRs.csrs[2].wdata
invalidate io.ptw[14].customCSRs.csrs[2].wen
invalidate io.ptw[14].customCSRs.csrs[2].ren
invalidate io.ptw[14].customCSRs.csrs[3].sdata
invalidate io.ptw[14].customCSRs.csrs[3].set
invalidate io.ptw[14].customCSRs.csrs[3].stall
invalidate io.ptw[14].customCSRs.csrs[3].value
invalidate io.ptw[14].customCSRs.csrs[3].wdata
invalidate io.ptw[14].customCSRs.csrs[3].wen
invalidate io.ptw[14].customCSRs.csrs[3].ren
invalidate io.ptw[14].pmp[0].mask
invalidate io.ptw[14].pmp[0].addr
invalidate io.ptw[14].pmp[0].cfg.r
invalidate io.ptw[14].pmp[0].cfg.w
invalidate io.ptw[14].pmp[0].cfg.x
invalidate io.ptw[14].pmp[0].cfg.a
invalidate io.ptw[14].pmp[0].cfg.res
invalidate io.ptw[14].pmp[0].cfg.l
invalidate io.ptw[14].pmp[1].mask
invalidate io.ptw[14].pmp[1].addr
invalidate io.ptw[14].pmp[1].cfg.r
invalidate io.ptw[14].pmp[1].cfg.w
invalidate io.ptw[14].pmp[1].cfg.x
invalidate io.ptw[14].pmp[1].cfg.a
invalidate io.ptw[14].pmp[1].cfg.res
invalidate io.ptw[14].pmp[1].cfg.l
invalidate io.ptw[14].pmp[2].mask
invalidate io.ptw[14].pmp[2].addr
invalidate io.ptw[14].pmp[2].cfg.r
invalidate io.ptw[14].pmp[2].cfg.w
invalidate io.ptw[14].pmp[2].cfg.x
invalidate io.ptw[14].pmp[2].cfg.a
invalidate io.ptw[14].pmp[2].cfg.res
invalidate io.ptw[14].pmp[2].cfg.l
invalidate io.ptw[14].pmp[3].mask
invalidate io.ptw[14].pmp[3].addr
invalidate io.ptw[14].pmp[3].cfg.r
invalidate io.ptw[14].pmp[3].cfg.w
invalidate io.ptw[14].pmp[3].cfg.x
invalidate io.ptw[14].pmp[3].cfg.a
invalidate io.ptw[14].pmp[3].cfg.res
invalidate io.ptw[14].pmp[3].cfg.l
invalidate io.ptw[14].pmp[4].mask
invalidate io.ptw[14].pmp[4].addr
invalidate io.ptw[14].pmp[4].cfg.r
invalidate io.ptw[14].pmp[4].cfg.w
invalidate io.ptw[14].pmp[4].cfg.x
invalidate io.ptw[14].pmp[4].cfg.a
invalidate io.ptw[14].pmp[4].cfg.res
invalidate io.ptw[14].pmp[4].cfg.l
invalidate io.ptw[14].pmp[5].mask
invalidate io.ptw[14].pmp[5].addr
invalidate io.ptw[14].pmp[5].cfg.r
invalidate io.ptw[14].pmp[5].cfg.w
invalidate io.ptw[14].pmp[5].cfg.x
invalidate io.ptw[14].pmp[5].cfg.a
invalidate io.ptw[14].pmp[5].cfg.res
invalidate io.ptw[14].pmp[5].cfg.l
invalidate io.ptw[14].pmp[6].mask
invalidate io.ptw[14].pmp[6].addr
invalidate io.ptw[14].pmp[6].cfg.r
invalidate io.ptw[14].pmp[6].cfg.w
invalidate io.ptw[14].pmp[6].cfg.x
invalidate io.ptw[14].pmp[6].cfg.a
invalidate io.ptw[14].pmp[6].cfg.res
invalidate io.ptw[14].pmp[6].cfg.l
invalidate io.ptw[14].pmp[7].mask
invalidate io.ptw[14].pmp[7].addr
invalidate io.ptw[14].pmp[7].cfg.r
invalidate io.ptw[14].pmp[7].cfg.w
invalidate io.ptw[14].pmp[7].cfg.x
invalidate io.ptw[14].pmp[7].cfg.a
invalidate io.ptw[14].pmp[7].cfg.res
invalidate io.ptw[14].pmp[7].cfg.l
invalidate io.ptw[14].gstatus.uie
invalidate io.ptw[14].gstatus.sie
invalidate io.ptw[14].gstatus.hie
invalidate io.ptw[14].gstatus.mie
invalidate io.ptw[14].gstatus.upie
invalidate io.ptw[14].gstatus.spie
invalidate io.ptw[14].gstatus.ube
invalidate io.ptw[14].gstatus.mpie
invalidate io.ptw[14].gstatus.spp
invalidate io.ptw[14].gstatus.vs
invalidate io.ptw[14].gstatus.mpp
invalidate io.ptw[14].gstatus.fs
invalidate io.ptw[14].gstatus.xs
invalidate io.ptw[14].gstatus.mprv
invalidate io.ptw[14].gstatus.sum
invalidate io.ptw[14].gstatus.mxr
invalidate io.ptw[14].gstatus.tvm
invalidate io.ptw[14].gstatus.tw
invalidate io.ptw[14].gstatus.tsr
invalidate io.ptw[14].gstatus.zero1
invalidate io.ptw[14].gstatus.sd_rv32
invalidate io.ptw[14].gstatus.uxl
invalidate io.ptw[14].gstatus.sxl
invalidate io.ptw[14].gstatus.sbe
invalidate io.ptw[14].gstatus.mbe
invalidate io.ptw[14].gstatus.gva
invalidate io.ptw[14].gstatus.mpv
invalidate io.ptw[14].gstatus.zero2
invalidate io.ptw[14].gstatus.sd
invalidate io.ptw[14].gstatus.v
invalidate io.ptw[14].gstatus.prv
invalidate io.ptw[14].gstatus.dv
invalidate io.ptw[14].gstatus.dprv
invalidate io.ptw[14].gstatus.isa
invalidate io.ptw[14].gstatus.wfi
invalidate io.ptw[14].gstatus.cease
invalidate io.ptw[14].gstatus.debug
invalidate io.ptw[14].hstatus.zero1
invalidate io.ptw[14].hstatus.vsbe
invalidate io.ptw[14].hstatus.gva
invalidate io.ptw[14].hstatus.spv
invalidate io.ptw[14].hstatus.spvp
invalidate io.ptw[14].hstatus.hu
invalidate io.ptw[14].hstatus.zero2
invalidate io.ptw[14].hstatus.vgein
invalidate io.ptw[14].hstatus.zero3
invalidate io.ptw[14].hstatus.vtvm
invalidate io.ptw[14].hstatus.vtw
invalidate io.ptw[14].hstatus.vtsr
invalidate io.ptw[14].hstatus.zero5
invalidate io.ptw[14].hstatus.vsxl
invalidate io.ptw[14].hstatus.zero6
invalidate io.ptw[14].status.uie
invalidate io.ptw[14].status.sie
invalidate io.ptw[14].status.hie
invalidate io.ptw[14].status.mie
invalidate io.ptw[14].status.upie
invalidate io.ptw[14].status.spie
invalidate io.ptw[14].status.ube
invalidate io.ptw[14].status.mpie
invalidate io.ptw[14].status.spp
invalidate io.ptw[14].status.vs
invalidate io.ptw[14].status.mpp
invalidate io.ptw[14].status.fs
invalidate io.ptw[14].status.xs
invalidate io.ptw[14].status.mprv
invalidate io.ptw[14].status.sum
invalidate io.ptw[14].status.mxr
invalidate io.ptw[14].status.tvm
invalidate io.ptw[14].status.tw
invalidate io.ptw[14].status.tsr
invalidate io.ptw[14].status.zero1
invalidate io.ptw[14].status.sd_rv32
invalidate io.ptw[14].status.uxl
invalidate io.ptw[14].status.sxl
invalidate io.ptw[14].status.sbe
invalidate io.ptw[14].status.mbe
invalidate io.ptw[14].status.gva
invalidate io.ptw[14].status.mpv
invalidate io.ptw[14].status.zero2
invalidate io.ptw[14].status.sd
invalidate io.ptw[14].status.v
invalidate io.ptw[14].status.prv
invalidate io.ptw[14].status.dv
invalidate io.ptw[14].status.dprv
invalidate io.ptw[14].status.isa
invalidate io.ptw[14].status.wfi
invalidate io.ptw[14].status.cease
invalidate io.ptw[14].status.debug
invalidate io.ptw[14].vsatp.ppn
invalidate io.ptw[14].vsatp.asid
invalidate io.ptw[14].vsatp.mode
invalidate io.ptw[14].hgatp.ppn
invalidate io.ptw[14].hgatp.asid
invalidate io.ptw[14].hgatp.mode
invalidate io.ptw[14].ptbr.ppn
invalidate io.ptw[14].ptbr.asid
invalidate io.ptw[14].ptbr.mode
invalidate io.ptw[14].resp.bits.gpa_is_pte
invalidate io.ptw[14].resp.bits.gpa.bits
invalidate io.ptw[14].resp.bits.gpa.valid
invalidate io.ptw[14].resp.bits.homogeneous
invalidate io.ptw[14].resp.bits.fragmented_superpage
invalidate io.ptw[14].resp.bits.level
invalidate io.ptw[14].resp.bits.pte.v
invalidate io.ptw[14].resp.bits.pte.r
invalidate io.ptw[14].resp.bits.pte.w
invalidate io.ptw[14].resp.bits.pte.x
invalidate io.ptw[14].resp.bits.pte.u
invalidate io.ptw[14].resp.bits.pte.g
invalidate io.ptw[14].resp.bits.pte.a
invalidate io.ptw[14].resp.bits.pte.d
invalidate io.ptw[14].resp.bits.pte.reserved_for_software
invalidate io.ptw[14].resp.bits.pte.ppn
invalidate io.ptw[14].resp.bits.pte.reserved_for_future
invalidate io.ptw[14].resp.bits.hx
invalidate io.ptw[14].resp.bits.hw
invalidate io.ptw[14].resp.bits.hr
invalidate io.ptw[14].resp.bits.gf
invalidate io.ptw[14].resp.bits.pf
invalidate io.ptw[14].resp.bits.ae_final
invalidate io.ptw[14].resp.bits.ae_ptw
invalidate io.ptw[14].resp.valid
invalidate io.ptw[14].req.bits.bits.stage2
invalidate io.ptw[14].req.bits.bits.vstage1
invalidate io.ptw[14].req.bits.bits.need_gpa
invalidate io.ptw[14].req.bits.bits.addr
invalidate io.ptw[14].req.bits.valid
invalidate io.ptw[14].req.valid
invalidate io.ptw[14].req.ready
invalidate io.ptw[15].customCSRs.csrs[0].sdata
invalidate io.ptw[15].customCSRs.csrs[0].set
invalidate io.ptw[15].customCSRs.csrs[0].stall
invalidate io.ptw[15].customCSRs.csrs[0].value
invalidate io.ptw[15].customCSRs.csrs[0].wdata
invalidate io.ptw[15].customCSRs.csrs[0].wen
invalidate io.ptw[15].customCSRs.csrs[0].ren
invalidate io.ptw[15].customCSRs.csrs[1].sdata
invalidate io.ptw[15].customCSRs.csrs[1].set
invalidate io.ptw[15].customCSRs.csrs[1].stall
invalidate io.ptw[15].customCSRs.csrs[1].value
invalidate io.ptw[15].customCSRs.csrs[1].wdata
invalidate io.ptw[15].customCSRs.csrs[1].wen
invalidate io.ptw[15].customCSRs.csrs[1].ren
invalidate io.ptw[15].customCSRs.csrs[2].sdata
invalidate io.ptw[15].customCSRs.csrs[2].set
invalidate io.ptw[15].customCSRs.csrs[2].stall
invalidate io.ptw[15].customCSRs.csrs[2].value
invalidate io.ptw[15].customCSRs.csrs[2].wdata
invalidate io.ptw[15].customCSRs.csrs[2].wen
invalidate io.ptw[15].customCSRs.csrs[2].ren
invalidate io.ptw[15].customCSRs.csrs[3].sdata
invalidate io.ptw[15].customCSRs.csrs[3].set
invalidate io.ptw[15].customCSRs.csrs[3].stall
invalidate io.ptw[15].customCSRs.csrs[3].value
invalidate io.ptw[15].customCSRs.csrs[3].wdata
invalidate io.ptw[15].customCSRs.csrs[3].wen
invalidate io.ptw[15].customCSRs.csrs[3].ren
invalidate io.ptw[15].pmp[0].mask
invalidate io.ptw[15].pmp[0].addr
invalidate io.ptw[15].pmp[0].cfg.r
invalidate io.ptw[15].pmp[0].cfg.w
invalidate io.ptw[15].pmp[0].cfg.x
invalidate io.ptw[15].pmp[0].cfg.a
invalidate io.ptw[15].pmp[0].cfg.res
invalidate io.ptw[15].pmp[0].cfg.l
invalidate io.ptw[15].pmp[1].mask
invalidate io.ptw[15].pmp[1].addr
invalidate io.ptw[15].pmp[1].cfg.r
invalidate io.ptw[15].pmp[1].cfg.w
invalidate io.ptw[15].pmp[1].cfg.x
invalidate io.ptw[15].pmp[1].cfg.a
invalidate io.ptw[15].pmp[1].cfg.res
invalidate io.ptw[15].pmp[1].cfg.l
invalidate io.ptw[15].pmp[2].mask
invalidate io.ptw[15].pmp[2].addr
invalidate io.ptw[15].pmp[2].cfg.r
invalidate io.ptw[15].pmp[2].cfg.w
invalidate io.ptw[15].pmp[2].cfg.x
invalidate io.ptw[15].pmp[2].cfg.a
invalidate io.ptw[15].pmp[2].cfg.res
invalidate io.ptw[15].pmp[2].cfg.l
invalidate io.ptw[15].pmp[3].mask
invalidate io.ptw[15].pmp[3].addr
invalidate io.ptw[15].pmp[3].cfg.r
invalidate io.ptw[15].pmp[3].cfg.w
invalidate io.ptw[15].pmp[3].cfg.x
invalidate io.ptw[15].pmp[3].cfg.a
invalidate io.ptw[15].pmp[3].cfg.res
invalidate io.ptw[15].pmp[3].cfg.l
invalidate io.ptw[15].pmp[4].mask
invalidate io.ptw[15].pmp[4].addr
invalidate io.ptw[15].pmp[4].cfg.r
invalidate io.ptw[15].pmp[4].cfg.w
invalidate io.ptw[15].pmp[4].cfg.x
invalidate io.ptw[15].pmp[4].cfg.a
invalidate io.ptw[15].pmp[4].cfg.res
invalidate io.ptw[15].pmp[4].cfg.l
invalidate io.ptw[15].pmp[5].mask
invalidate io.ptw[15].pmp[5].addr
invalidate io.ptw[15].pmp[5].cfg.r
invalidate io.ptw[15].pmp[5].cfg.w
invalidate io.ptw[15].pmp[5].cfg.x
invalidate io.ptw[15].pmp[5].cfg.a
invalidate io.ptw[15].pmp[5].cfg.res
invalidate io.ptw[15].pmp[5].cfg.l
invalidate io.ptw[15].pmp[6].mask
invalidate io.ptw[15].pmp[6].addr
invalidate io.ptw[15].pmp[6].cfg.r
invalidate io.ptw[15].pmp[6].cfg.w
invalidate io.ptw[15].pmp[6].cfg.x
invalidate io.ptw[15].pmp[6].cfg.a
invalidate io.ptw[15].pmp[6].cfg.res
invalidate io.ptw[15].pmp[6].cfg.l
invalidate io.ptw[15].pmp[7].mask
invalidate io.ptw[15].pmp[7].addr
invalidate io.ptw[15].pmp[7].cfg.r
invalidate io.ptw[15].pmp[7].cfg.w
invalidate io.ptw[15].pmp[7].cfg.x
invalidate io.ptw[15].pmp[7].cfg.a
invalidate io.ptw[15].pmp[7].cfg.res
invalidate io.ptw[15].pmp[7].cfg.l
invalidate io.ptw[15].gstatus.uie
invalidate io.ptw[15].gstatus.sie
invalidate io.ptw[15].gstatus.hie
invalidate io.ptw[15].gstatus.mie
invalidate io.ptw[15].gstatus.upie
invalidate io.ptw[15].gstatus.spie
invalidate io.ptw[15].gstatus.ube
invalidate io.ptw[15].gstatus.mpie
invalidate io.ptw[15].gstatus.spp
invalidate io.ptw[15].gstatus.vs
invalidate io.ptw[15].gstatus.mpp
invalidate io.ptw[15].gstatus.fs
invalidate io.ptw[15].gstatus.xs
invalidate io.ptw[15].gstatus.mprv
invalidate io.ptw[15].gstatus.sum
invalidate io.ptw[15].gstatus.mxr
invalidate io.ptw[15].gstatus.tvm
invalidate io.ptw[15].gstatus.tw
invalidate io.ptw[15].gstatus.tsr
invalidate io.ptw[15].gstatus.zero1
invalidate io.ptw[15].gstatus.sd_rv32
invalidate io.ptw[15].gstatus.uxl
invalidate io.ptw[15].gstatus.sxl
invalidate io.ptw[15].gstatus.sbe
invalidate io.ptw[15].gstatus.mbe
invalidate io.ptw[15].gstatus.gva
invalidate io.ptw[15].gstatus.mpv
invalidate io.ptw[15].gstatus.zero2
invalidate io.ptw[15].gstatus.sd
invalidate io.ptw[15].gstatus.v
invalidate io.ptw[15].gstatus.prv
invalidate io.ptw[15].gstatus.dv
invalidate io.ptw[15].gstatus.dprv
invalidate io.ptw[15].gstatus.isa
invalidate io.ptw[15].gstatus.wfi
invalidate io.ptw[15].gstatus.cease
invalidate io.ptw[15].gstatus.debug
invalidate io.ptw[15].hstatus.zero1
invalidate io.ptw[15].hstatus.vsbe
invalidate io.ptw[15].hstatus.gva
invalidate io.ptw[15].hstatus.spv
invalidate io.ptw[15].hstatus.spvp
invalidate io.ptw[15].hstatus.hu
invalidate io.ptw[15].hstatus.zero2
invalidate io.ptw[15].hstatus.vgein
invalidate io.ptw[15].hstatus.zero3
invalidate io.ptw[15].hstatus.vtvm
invalidate io.ptw[15].hstatus.vtw
invalidate io.ptw[15].hstatus.vtsr
invalidate io.ptw[15].hstatus.zero5
invalidate io.ptw[15].hstatus.vsxl
invalidate io.ptw[15].hstatus.zero6
invalidate io.ptw[15].status.uie
invalidate io.ptw[15].status.sie
invalidate io.ptw[15].status.hie
invalidate io.ptw[15].status.mie
invalidate io.ptw[15].status.upie
invalidate io.ptw[15].status.spie
invalidate io.ptw[15].status.ube
invalidate io.ptw[15].status.mpie
invalidate io.ptw[15].status.spp
invalidate io.ptw[15].status.vs
invalidate io.ptw[15].status.mpp
invalidate io.ptw[15].status.fs
invalidate io.ptw[15].status.xs
invalidate io.ptw[15].status.mprv
invalidate io.ptw[15].status.sum
invalidate io.ptw[15].status.mxr
invalidate io.ptw[15].status.tvm
invalidate io.ptw[15].status.tw
invalidate io.ptw[15].status.tsr
invalidate io.ptw[15].status.zero1
invalidate io.ptw[15].status.sd_rv32
invalidate io.ptw[15].status.uxl
invalidate io.ptw[15].status.sxl
invalidate io.ptw[15].status.sbe
invalidate io.ptw[15].status.mbe
invalidate io.ptw[15].status.gva
invalidate io.ptw[15].status.mpv
invalidate io.ptw[15].status.zero2
invalidate io.ptw[15].status.sd
invalidate io.ptw[15].status.v
invalidate io.ptw[15].status.prv
invalidate io.ptw[15].status.dv
invalidate io.ptw[15].status.dprv
invalidate io.ptw[15].status.isa
invalidate io.ptw[15].status.wfi
invalidate io.ptw[15].status.cease
invalidate io.ptw[15].status.debug
invalidate io.ptw[15].vsatp.ppn
invalidate io.ptw[15].vsatp.asid
invalidate io.ptw[15].vsatp.mode
invalidate io.ptw[15].hgatp.ppn
invalidate io.ptw[15].hgatp.asid
invalidate io.ptw[15].hgatp.mode
invalidate io.ptw[15].ptbr.ppn
invalidate io.ptw[15].ptbr.asid
invalidate io.ptw[15].ptbr.mode
invalidate io.ptw[15].resp.bits.gpa_is_pte
invalidate io.ptw[15].resp.bits.gpa.bits
invalidate io.ptw[15].resp.bits.gpa.valid
invalidate io.ptw[15].resp.bits.homogeneous
invalidate io.ptw[15].resp.bits.fragmented_superpage
invalidate io.ptw[15].resp.bits.level
invalidate io.ptw[15].resp.bits.pte.v
invalidate io.ptw[15].resp.bits.pte.r
invalidate io.ptw[15].resp.bits.pte.w
invalidate io.ptw[15].resp.bits.pte.x
invalidate io.ptw[15].resp.bits.pte.u
invalidate io.ptw[15].resp.bits.pte.g
invalidate io.ptw[15].resp.bits.pte.a
invalidate io.ptw[15].resp.bits.pte.d
invalidate io.ptw[15].resp.bits.pte.reserved_for_software
invalidate io.ptw[15].resp.bits.pte.ppn
invalidate io.ptw[15].resp.bits.pte.reserved_for_future
invalidate io.ptw[15].resp.bits.hx
invalidate io.ptw[15].resp.bits.hw
invalidate io.ptw[15].resp.bits.hr
invalidate io.ptw[15].resp.bits.gf
invalidate io.ptw[15].resp.bits.pf
invalidate io.ptw[15].resp.bits.ae_final
invalidate io.ptw[15].resp.bits.ae_ptw
invalidate io.ptw[15].resp.valid
invalidate io.ptw[15].req.bits.bits.stage2
invalidate io.ptw[15].req.bits.bits.vstage1
invalidate io.ptw[15].req.bits.bits.need_gpa
invalidate io.ptw[15].req.bits.bits.addr
invalidate io.ptw[15].req.bits.valid
invalidate io.ptw[15].req.valid
invalidate io.ptw[15].req.ready
invalidate io.ptw[16].customCSRs.csrs[0].sdata
invalidate io.ptw[16].customCSRs.csrs[0].set
invalidate io.ptw[16].customCSRs.csrs[0].stall
invalidate io.ptw[16].customCSRs.csrs[0].value
invalidate io.ptw[16].customCSRs.csrs[0].wdata
invalidate io.ptw[16].customCSRs.csrs[0].wen
invalidate io.ptw[16].customCSRs.csrs[0].ren
invalidate io.ptw[16].customCSRs.csrs[1].sdata
invalidate io.ptw[16].customCSRs.csrs[1].set
invalidate io.ptw[16].customCSRs.csrs[1].stall
invalidate io.ptw[16].customCSRs.csrs[1].value
invalidate io.ptw[16].customCSRs.csrs[1].wdata
invalidate io.ptw[16].customCSRs.csrs[1].wen
invalidate io.ptw[16].customCSRs.csrs[1].ren
invalidate io.ptw[16].customCSRs.csrs[2].sdata
invalidate io.ptw[16].customCSRs.csrs[2].set
invalidate io.ptw[16].customCSRs.csrs[2].stall
invalidate io.ptw[16].customCSRs.csrs[2].value
invalidate io.ptw[16].customCSRs.csrs[2].wdata
invalidate io.ptw[16].customCSRs.csrs[2].wen
invalidate io.ptw[16].customCSRs.csrs[2].ren
invalidate io.ptw[16].customCSRs.csrs[3].sdata
invalidate io.ptw[16].customCSRs.csrs[3].set
invalidate io.ptw[16].customCSRs.csrs[3].stall
invalidate io.ptw[16].customCSRs.csrs[3].value
invalidate io.ptw[16].customCSRs.csrs[3].wdata
invalidate io.ptw[16].customCSRs.csrs[3].wen
invalidate io.ptw[16].customCSRs.csrs[3].ren
invalidate io.ptw[16].pmp[0].mask
invalidate io.ptw[16].pmp[0].addr
invalidate io.ptw[16].pmp[0].cfg.r
invalidate io.ptw[16].pmp[0].cfg.w
invalidate io.ptw[16].pmp[0].cfg.x
invalidate io.ptw[16].pmp[0].cfg.a
invalidate io.ptw[16].pmp[0].cfg.res
invalidate io.ptw[16].pmp[0].cfg.l
invalidate io.ptw[16].pmp[1].mask
invalidate io.ptw[16].pmp[1].addr
invalidate io.ptw[16].pmp[1].cfg.r
invalidate io.ptw[16].pmp[1].cfg.w
invalidate io.ptw[16].pmp[1].cfg.x
invalidate io.ptw[16].pmp[1].cfg.a
invalidate io.ptw[16].pmp[1].cfg.res
invalidate io.ptw[16].pmp[1].cfg.l
invalidate io.ptw[16].pmp[2].mask
invalidate io.ptw[16].pmp[2].addr
invalidate io.ptw[16].pmp[2].cfg.r
invalidate io.ptw[16].pmp[2].cfg.w
invalidate io.ptw[16].pmp[2].cfg.x
invalidate io.ptw[16].pmp[2].cfg.a
invalidate io.ptw[16].pmp[2].cfg.res
invalidate io.ptw[16].pmp[2].cfg.l
invalidate io.ptw[16].pmp[3].mask
invalidate io.ptw[16].pmp[3].addr
invalidate io.ptw[16].pmp[3].cfg.r
invalidate io.ptw[16].pmp[3].cfg.w
invalidate io.ptw[16].pmp[3].cfg.x
invalidate io.ptw[16].pmp[3].cfg.a
invalidate io.ptw[16].pmp[3].cfg.res
invalidate io.ptw[16].pmp[3].cfg.l
invalidate io.ptw[16].pmp[4].mask
invalidate io.ptw[16].pmp[4].addr
invalidate io.ptw[16].pmp[4].cfg.r
invalidate io.ptw[16].pmp[4].cfg.w
invalidate io.ptw[16].pmp[4].cfg.x
invalidate io.ptw[16].pmp[4].cfg.a
invalidate io.ptw[16].pmp[4].cfg.res
invalidate io.ptw[16].pmp[4].cfg.l
invalidate io.ptw[16].pmp[5].mask
invalidate io.ptw[16].pmp[5].addr
invalidate io.ptw[16].pmp[5].cfg.r
invalidate io.ptw[16].pmp[5].cfg.w
invalidate io.ptw[16].pmp[5].cfg.x
invalidate io.ptw[16].pmp[5].cfg.a
invalidate io.ptw[16].pmp[5].cfg.res
invalidate io.ptw[16].pmp[5].cfg.l
invalidate io.ptw[16].pmp[6].mask
invalidate io.ptw[16].pmp[6].addr
invalidate io.ptw[16].pmp[6].cfg.r
invalidate io.ptw[16].pmp[6].cfg.w
invalidate io.ptw[16].pmp[6].cfg.x
invalidate io.ptw[16].pmp[6].cfg.a
invalidate io.ptw[16].pmp[6].cfg.res
invalidate io.ptw[16].pmp[6].cfg.l
invalidate io.ptw[16].pmp[7].mask
invalidate io.ptw[16].pmp[7].addr
invalidate io.ptw[16].pmp[7].cfg.r
invalidate io.ptw[16].pmp[7].cfg.w
invalidate io.ptw[16].pmp[7].cfg.x
invalidate io.ptw[16].pmp[7].cfg.a
invalidate io.ptw[16].pmp[7].cfg.res
invalidate io.ptw[16].pmp[7].cfg.l
invalidate io.ptw[16].gstatus.uie
invalidate io.ptw[16].gstatus.sie
invalidate io.ptw[16].gstatus.hie
invalidate io.ptw[16].gstatus.mie
invalidate io.ptw[16].gstatus.upie
invalidate io.ptw[16].gstatus.spie
invalidate io.ptw[16].gstatus.ube
invalidate io.ptw[16].gstatus.mpie
invalidate io.ptw[16].gstatus.spp
invalidate io.ptw[16].gstatus.vs
invalidate io.ptw[16].gstatus.mpp
invalidate io.ptw[16].gstatus.fs
invalidate io.ptw[16].gstatus.xs
invalidate io.ptw[16].gstatus.mprv
invalidate io.ptw[16].gstatus.sum
invalidate io.ptw[16].gstatus.mxr
invalidate io.ptw[16].gstatus.tvm
invalidate io.ptw[16].gstatus.tw
invalidate io.ptw[16].gstatus.tsr
invalidate io.ptw[16].gstatus.zero1
invalidate io.ptw[16].gstatus.sd_rv32
invalidate io.ptw[16].gstatus.uxl
invalidate io.ptw[16].gstatus.sxl
invalidate io.ptw[16].gstatus.sbe
invalidate io.ptw[16].gstatus.mbe
invalidate io.ptw[16].gstatus.gva
invalidate io.ptw[16].gstatus.mpv
invalidate io.ptw[16].gstatus.zero2
invalidate io.ptw[16].gstatus.sd
invalidate io.ptw[16].gstatus.v
invalidate io.ptw[16].gstatus.prv
invalidate io.ptw[16].gstatus.dv
invalidate io.ptw[16].gstatus.dprv
invalidate io.ptw[16].gstatus.isa
invalidate io.ptw[16].gstatus.wfi
invalidate io.ptw[16].gstatus.cease
invalidate io.ptw[16].gstatus.debug
invalidate io.ptw[16].hstatus.zero1
invalidate io.ptw[16].hstatus.vsbe
invalidate io.ptw[16].hstatus.gva
invalidate io.ptw[16].hstatus.spv
invalidate io.ptw[16].hstatus.spvp
invalidate io.ptw[16].hstatus.hu
invalidate io.ptw[16].hstatus.zero2
invalidate io.ptw[16].hstatus.vgein
invalidate io.ptw[16].hstatus.zero3
invalidate io.ptw[16].hstatus.vtvm
invalidate io.ptw[16].hstatus.vtw
invalidate io.ptw[16].hstatus.vtsr
invalidate io.ptw[16].hstatus.zero5
invalidate io.ptw[16].hstatus.vsxl
invalidate io.ptw[16].hstatus.zero6
invalidate io.ptw[16].status.uie
invalidate io.ptw[16].status.sie
invalidate io.ptw[16].status.hie
invalidate io.ptw[16].status.mie
invalidate io.ptw[16].status.upie
invalidate io.ptw[16].status.spie
invalidate io.ptw[16].status.ube
invalidate io.ptw[16].status.mpie
invalidate io.ptw[16].status.spp
invalidate io.ptw[16].status.vs
invalidate io.ptw[16].status.mpp
invalidate io.ptw[16].status.fs
invalidate io.ptw[16].status.xs
invalidate io.ptw[16].status.mprv
invalidate io.ptw[16].status.sum
invalidate io.ptw[16].status.mxr
invalidate io.ptw[16].status.tvm
invalidate io.ptw[16].status.tw
invalidate io.ptw[16].status.tsr
invalidate io.ptw[16].status.zero1
invalidate io.ptw[16].status.sd_rv32
invalidate io.ptw[16].status.uxl
invalidate io.ptw[16].status.sxl
invalidate io.ptw[16].status.sbe
invalidate io.ptw[16].status.mbe
invalidate io.ptw[16].status.gva
invalidate io.ptw[16].status.mpv
invalidate io.ptw[16].status.zero2
invalidate io.ptw[16].status.sd
invalidate io.ptw[16].status.v
invalidate io.ptw[16].status.prv
invalidate io.ptw[16].status.dv
invalidate io.ptw[16].status.dprv
invalidate io.ptw[16].status.isa
invalidate io.ptw[16].status.wfi
invalidate io.ptw[16].status.cease
invalidate io.ptw[16].status.debug
invalidate io.ptw[16].vsatp.ppn
invalidate io.ptw[16].vsatp.asid
invalidate io.ptw[16].vsatp.mode
invalidate io.ptw[16].hgatp.ppn
invalidate io.ptw[16].hgatp.asid
invalidate io.ptw[16].hgatp.mode
invalidate io.ptw[16].ptbr.ppn
invalidate io.ptw[16].ptbr.asid
invalidate io.ptw[16].ptbr.mode
invalidate io.ptw[16].resp.bits.gpa_is_pte
invalidate io.ptw[16].resp.bits.gpa.bits
invalidate io.ptw[16].resp.bits.gpa.valid
invalidate io.ptw[16].resp.bits.homogeneous
invalidate io.ptw[16].resp.bits.fragmented_superpage
invalidate io.ptw[16].resp.bits.level
invalidate io.ptw[16].resp.bits.pte.v
invalidate io.ptw[16].resp.bits.pte.r
invalidate io.ptw[16].resp.bits.pte.w
invalidate io.ptw[16].resp.bits.pte.x
invalidate io.ptw[16].resp.bits.pte.u
invalidate io.ptw[16].resp.bits.pte.g
invalidate io.ptw[16].resp.bits.pte.a
invalidate io.ptw[16].resp.bits.pte.d
invalidate io.ptw[16].resp.bits.pte.reserved_for_software
invalidate io.ptw[16].resp.bits.pte.ppn
invalidate io.ptw[16].resp.bits.pte.reserved_for_future
invalidate io.ptw[16].resp.bits.hx
invalidate io.ptw[16].resp.bits.hw
invalidate io.ptw[16].resp.bits.hr
invalidate io.ptw[16].resp.bits.gf
invalidate io.ptw[16].resp.bits.pf
invalidate io.ptw[16].resp.bits.ae_final
invalidate io.ptw[16].resp.bits.ae_ptw
invalidate io.ptw[16].resp.valid
invalidate io.ptw[16].req.bits.bits.stage2
invalidate io.ptw[16].req.bits.bits.vstage1
invalidate io.ptw[16].req.bits.bits.need_gpa
invalidate io.ptw[16].req.bits.bits.addr
invalidate io.ptw[16].req.bits.valid
invalidate io.ptw[16].req.valid
invalidate io.ptw[16].req.ready
invalidate io.ptw[17].customCSRs.csrs[0].sdata
invalidate io.ptw[17].customCSRs.csrs[0].set
invalidate io.ptw[17].customCSRs.csrs[0].stall
invalidate io.ptw[17].customCSRs.csrs[0].value
invalidate io.ptw[17].customCSRs.csrs[0].wdata
invalidate io.ptw[17].customCSRs.csrs[0].wen
invalidate io.ptw[17].customCSRs.csrs[0].ren
invalidate io.ptw[17].customCSRs.csrs[1].sdata
invalidate io.ptw[17].customCSRs.csrs[1].set
invalidate io.ptw[17].customCSRs.csrs[1].stall
invalidate io.ptw[17].customCSRs.csrs[1].value
invalidate io.ptw[17].customCSRs.csrs[1].wdata
invalidate io.ptw[17].customCSRs.csrs[1].wen
invalidate io.ptw[17].customCSRs.csrs[1].ren
invalidate io.ptw[17].customCSRs.csrs[2].sdata
invalidate io.ptw[17].customCSRs.csrs[2].set
invalidate io.ptw[17].customCSRs.csrs[2].stall
invalidate io.ptw[17].customCSRs.csrs[2].value
invalidate io.ptw[17].customCSRs.csrs[2].wdata
invalidate io.ptw[17].customCSRs.csrs[2].wen
invalidate io.ptw[17].customCSRs.csrs[2].ren
invalidate io.ptw[17].customCSRs.csrs[3].sdata
invalidate io.ptw[17].customCSRs.csrs[3].set
invalidate io.ptw[17].customCSRs.csrs[3].stall
invalidate io.ptw[17].customCSRs.csrs[3].value
invalidate io.ptw[17].customCSRs.csrs[3].wdata
invalidate io.ptw[17].customCSRs.csrs[3].wen
invalidate io.ptw[17].customCSRs.csrs[3].ren
invalidate io.ptw[17].pmp[0].mask
invalidate io.ptw[17].pmp[0].addr
invalidate io.ptw[17].pmp[0].cfg.r
invalidate io.ptw[17].pmp[0].cfg.w
invalidate io.ptw[17].pmp[0].cfg.x
invalidate io.ptw[17].pmp[0].cfg.a
invalidate io.ptw[17].pmp[0].cfg.res
invalidate io.ptw[17].pmp[0].cfg.l
invalidate io.ptw[17].pmp[1].mask
invalidate io.ptw[17].pmp[1].addr
invalidate io.ptw[17].pmp[1].cfg.r
invalidate io.ptw[17].pmp[1].cfg.w
invalidate io.ptw[17].pmp[1].cfg.x
invalidate io.ptw[17].pmp[1].cfg.a
invalidate io.ptw[17].pmp[1].cfg.res
invalidate io.ptw[17].pmp[1].cfg.l
invalidate io.ptw[17].pmp[2].mask
invalidate io.ptw[17].pmp[2].addr
invalidate io.ptw[17].pmp[2].cfg.r
invalidate io.ptw[17].pmp[2].cfg.w
invalidate io.ptw[17].pmp[2].cfg.x
invalidate io.ptw[17].pmp[2].cfg.a
invalidate io.ptw[17].pmp[2].cfg.res
invalidate io.ptw[17].pmp[2].cfg.l
invalidate io.ptw[17].pmp[3].mask
invalidate io.ptw[17].pmp[3].addr
invalidate io.ptw[17].pmp[3].cfg.r
invalidate io.ptw[17].pmp[3].cfg.w
invalidate io.ptw[17].pmp[3].cfg.x
invalidate io.ptw[17].pmp[3].cfg.a
invalidate io.ptw[17].pmp[3].cfg.res
invalidate io.ptw[17].pmp[3].cfg.l
invalidate io.ptw[17].pmp[4].mask
invalidate io.ptw[17].pmp[4].addr
invalidate io.ptw[17].pmp[4].cfg.r
invalidate io.ptw[17].pmp[4].cfg.w
invalidate io.ptw[17].pmp[4].cfg.x
invalidate io.ptw[17].pmp[4].cfg.a
invalidate io.ptw[17].pmp[4].cfg.res
invalidate io.ptw[17].pmp[4].cfg.l
invalidate io.ptw[17].pmp[5].mask
invalidate io.ptw[17].pmp[5].addr
invalidate io.ptw[17].pmp[5].cfg.r
invalidate io.ptw[17].pmp[5].cfg.w
invalidate io.ptw[17].pmp[5].cfg.x
invalidate io.ptw[17].pmp[5].cfg.a
invalidate io.ptw[17].pmp[5].cfg.res
invalidate io.ptw[17].pmp[5].cfg.l
invalidate io.ptw[17].pmp[6].mask
invalidate io.ptw[17].pmp[6].addr
invalidate io.ptw[17].pmp[6].cfg.r
invalidate io.ptw[17].pmp[6].cfg.w
invalidate io.ptw[17].pmp[6].cfg.x
invalidate io.ptw[17].pmp[6].cfg.a
invalidate io.ptw[17].pmp[6].cfg.res
invalidate io.ptw[17].pmp[6].cfg.l
invalidate io.ptw[17].pmp[7].mask
invalidate io.ptw[17].pmp[7].addr
invalidate io.ptw[17].pmp[7].cfg.r
invalidate io.ptw[17].pmp[7].cfg.w
invalidate io.ptw[17].pmp[7].cfg.x
invalidate io.ptw[17].pmp[7].cfg.a
invalidate io.ptw[17].pmp[7].cfg.res
invalidate io.ptw[17].pmp[7].cfg.l
invalidate io.ptw[17].gstatus.uie
invalidate io.ptw[17].gstatus.sie
invalidate io.ptw[17].gstatus.hie
invalidate io.ptw[17].gstatus.mie
invalidate io.ptw[17].gstatus.upie
invalidate io.ptw[17].gstatus.spie
invalidate io.ptw[17].gstatus.ube
invalidate io.ptw[17].gstatus.mpie
invalidate io.ptw[17].gstatus.spp
invalidate io.ptw[17].gstatus.vs
invalidate io.ptw[17].gstatus.mpp
invalidate io.ptw[17].gstatus.fs
invalidate io.ptw[17].gstatus.xs
invalidate io.ptw[17].gstatus.mprv
invalidate io.ptw[17].gstatus.sum
invalidate io.ptw[17].gstatus.mxr
invalidate io.ptw[17].gstatus.tvm
invalidate io.ptw[17].gstatus.tw
invalidate io.ptw[17].gstatus.tsr
invalidate io.ptw[17].gstatus.zero1
invalidate io.ptw[17].gstatus.sd_rv32
invalidate io.ptw[17].gstatus.uxl
invalidate io.ptw[17].gstatus.sxl
invalidate io.ptw[17].gstatus.sbe
invalidate io.ptw[17].gstatus.mbe
invalidate io.ptw[17].gstatus.gva
invalidate io.ptw[17].gstatus.mpv
invalidate io.ptw[17].gstatus.zero2
invalidate io.ptw[17].gstatus.sd
invalidate io.ptw[17].gstatus.v
invalidate io.ptw[17].gstatus.prv
invalidate io.ptw[17].gstatus.dv
invalidate io.ptw[17].gstatus.dprv
invalidate io.ptw[17].gstatus.isa
invalidate io.ptw[17].gstatus.wfi
invalidate io.ptw[17].gstatus.cease
invalidate io.ptw[17].gstatus.debug
invalidate io.ptw[17].hstatus.zero1
invalidate io.ptw[17].hstatus.vsbe
invalidate io.ptw[17].hstatus.gva
invalidate io.ptw[17].hstatus.spv
invalidate io.ptw[17].hstatus.spvp
invalidate io.ptw[17].hstatus.hu
invalidate io.ptw[17].hstatus.zero2
invalidate io.ptw[17].hstatus.vgein
invalidate io.ptw[17].hstatus.zero3
invalidate io.ptw[17].hstatus.vtvm
invalidate io.ptw[17].hstatus.vtw
invalidate io.ptw[17].hstatus.vtsr
invalidate io.ptw[17].hstatus.zero5
invalidate io.ptw[17].hstatus.vsxl
invalidate io.ptw[17].hstatus.zero6
invalidate io.ptw[17].status.uie
invalidate io.ptw[17].status.sie
invalidate io.ptw[17].status.hie
invalidate io.ptw[17].status.mie
invalidate io.ptw[17].status.upie
invalidate io.ptw[17].status.spie
invalidate io.ptw[17].status.ube
invalidate io.ptw[17].status.mpie
invalidate io.ptw[17].status.spp
invalidate io.ptw[17].status.vs
invalidate io.ptw[17].status.mpp
invalidate io.ptw[17].status.fs
invalidate io.ptw[17].status.xs
invalidate io.ptw[17].status.mprv
invalidate io.ptw[17].status.sum
invalidate io.ptw[17].status.mxr
invalidate io.ptw[17].status.tvm
invalidate io.ptw[17].status.tw
invalidate io.ptw[17].status.tsr
invalidate io.ptw[17].status.zero1
invalidate io.ptw[17].status.sd_rv32
invalidate io.ptw[17].status.uxl
invalidate io.ptw[17].status.sxl
invalidate io.ptw[17].status.sbe
invalidate io.ptw[17].status.mbe
invalidate io.ptw[17].status.gva
invalidate io.ptw[17].status.mpv
invalidate io.ptw[17].status.zero2
invalidate io.ptw[17].status.sd
invalidate io.ptw[17].status.v
invalidate io.ptw[17].status.prv
invalidate io.ptw[17].status.dv
invalidate io.ptw[17].status.dprv
invalidate io.ptw[17].status.isa
invalidate io.ptw[17].status.wfi
invalidate io.ptw[17].status.cease
invalidate io.ptw[17].status.debug
invalidate io.ptw[17].vsatp.ppn
invalidate io.ptw[17].vsatp.asid
invalidate io.ptw[17].vsatp.mode
invalidate io.ptw[17].hgatp.ppn
invalidate io.ptw[17].hgatp.asid
invalidate io.ptw[17].hgatp.mode
invalidate io.ptw[17].ptbr.ppn
invalidate io.ptw[17].ptbr.asid
invalidate io.ptw[17].ptbr.mode
invalidate io.ptw[17].resp.bits.gpa_is_pte
invalidate io.ptw[17].resp.bits.gpa.bits
invalidate io.ptw[17].resp.bits.gpa.valid
invalidate io.ptw[17].resp.bits.homogeneous
invalidate io.ptw[17].resp.bits.fragmented_superpage
invalidate io.ptw[17].resp.bits.level
invalidate io.ptw[17].resp.bits.pte.v
invalidate io.ptw[17].resp.bits.pte.r
invalidate io.ptw[17].resp.bits.pte.w
invalidate io.ptw[17].resp.bits.pte.x
invalidate io.ptw[17].resp.bits.pte.u
invalidate io.ptw[17].resp.bits.pte.g
invalidate io.ptw[17].resp.bits.pte.a
invalidate io.ptw[17].resp.bits.pte.d
invalidate io.ptw[17].resp.bits.pte.reserved_for_software
invalidate io.ptw[17].resp.bits.pte.ppn
invalidate io.ptw[17].resp.bits.pte.reserved_for_future
invalidate io.ptw[17].resp.bits.hx
invalidate io.ptw[17].resp.bits.hw
invalidate io.ptw[17].resp.bits.hr
invalidate io.ptw[17].resp.bits.gf
invalidate io.ptw[17].resp.bits.pf
invalidate io.ptw[17].resp.bits.ae_final
invalidate io.ptw[17].resp.bits.ae_ptw
invalidate io.ptw[17].resp.valid
invalidate io.ptw[17].req.bits.bits.stage2
invalidate io.ptw[17].req.bits.bits.vstage1
invalidate io.ptw[17].req.bits.bits.need_gpa
invalidate io.ptw[17].req.bits.bits.addr
invalidate io.ptw[17].req.bits.valid
invalidate io.ptw[17].req.valid
invalidate io.ptw[17].req.ready
invalidate io.exception
invalidate io.interrupt
invalidate io.busy
invalidate io.mem.clock_enabled
invalidate io.mem.keep_clock_enabled
invalidate io.mem.perf.storeBufferEmptyAfterStore
invalidate io.mem.perf.storeBufferEmptyAfterLoad
invalidate io.mem.perf.canAcceptLoadThenLoad
invalidate io.mem.perf.canAcceptStoreThenRMW
invalidate io.mem.perf.canAcceptStoreThenLoad
invalidate io.mem.perf.blocked
invalidate io.mem.perf.tlbMiss
invalidate io.mem.perf.grant
invalidate io.mem.perf.release
invalidate io.mem.perf.acquire
invalidate io.mem.store_pending
invalidate io.mem.ordered
invalidate io.mem.s2_gpa_is_pte
invalidate io.mem.s2_gpa
invalidate io.mem.s2_xcpt.ae.st
invalidate io.mem.s2_xcpt.ae.ld
invalidate io.mem.s2_xcpt.gf.st
invalidate io.mem.s2_xcpt.gf.ld
invalidate io.mem.s2_xcpt.pf.st
invalidate io.mem.s2_xcpt.pf.ld
invalidate io.mem.s2_xcpt.ma.st
invalidate io.mem.s2_xcpt.ma.ld
invalidate io.mem.replay_next
invalidate io.mem.resp.bits.store_data
invalidate io.mem.resp.bits.data_raw
invalidate io.mem.resp.bits.data_word_bypass
invalidate io.mem.resp.bits.has_data
invalidate io.mem.resp.bits.replay
invalidate io.mem.resp.bits.mask
invalidate io.mem.resp.bits.data
invalidate io.mem.resp.bits.dv
invalidate io.mem.resp.bits.dprv
invalidate io.mem.resp.bits.signed
invalidate io.mem.resp.bits.size
invalidate io.mem.resp.bits.cmd
invalidate io.mem.resp.bits.tag
invalidate io.mem.resp.bits.addr
invalidate io.mem.resp.valid
invalidate io.mem.s2_paddr
invalidate io.mem.s2_uncached
invalidate io.mem.s2_kill
invalidate io.mem.s2_nack_cause_raw
invalidate io.mem.s2_nack
invalidate io.mem.s1_data.mask
invalidate io.mem.s1_data.data
invalidate io.mem.s1_kill
invalidate io.mem.req.bits.mask
invalidate io.mem.req.bits.data
invalidate io.mem.req.bits.no_xcpt
invalidate io.mem.req.bits.no_alloc
invalidate io.mem.req.bits.no_resp
invalidate io.mem.req.bits.phys
invalidate io.mem.req.bits.dv
invalidate io.mem.req.bits.dprv
invalidate io.mem.req.bits.signed
invalidate io.mem.req.bits.size
invalidate io.mem.req.bits.cmd
invalidate io.mem.req.bits.tag
invalidate io.mem.req.bits.addr
invalidate io.mem.req.valid
invalidate io.mem.req.ready
invalidate io.resp.bits.data
invalidate io.resp.bits.rd
invalidate io.resp.valid
invalidate io.resp.ready
invalidate io.cmd.bits.status.uie
invalidate io.cmd.bits.status.sie
invalidate io.cmd.bits.status.hie
invalidate io.cmd.bits.status.mie
invalidate io.cmd.bits.status.upie
invalidate io.cmd.bits.status.spie
invalidate io.cmd.bits.status.ube
invalidate io.cmd.bits.status.mpie
invalidate io.cmd.bits.status.spp
invalidate io.cmd.bits.status.vs
invalidate io.cmd.bits.status.mpp
invalidate io.cmd.bits.status.fs
invalidate io.cmd.bits.status.xs
invalidate io.cmd.bits.status.mprv
invalidate io.cmd.bits.status.sum
invalidate io.cmd.bits.status.mxr
invalidate io.cmd.bits.status.tvm
invalidate io.cmd.bits.status.tw
invalidate io.cmd.bits.status.tsr
invalidate io.cmd.bits.status.zero1
invalidate io.cmd.bits.status.sd_rv32
invalidate io.cmd.bits.status.uxl
invalidate io.cmd.bits.status.sxl
invalidate io.cmd.bits.status.sbe
invalidate io.cmd.bits.status.mbe
invalidate io.cmd.bits.status.gva
invalidate io.cmd.bits.status.mpv
invalidate io.cmd.bits.status.zero2
invalidate io.cmd.bits.status.sd
invalidate io.cmd.bits.status.v
invalidate io.cmd.bits.status.prv
invalidate io.cmd.bits.status.dv
invalidate io.cmd.bits.status.dprv
invalidate io.cmd.bits.status.isa
invalidate io.cmd.bits.status.wfi
invalidate io.cmd.bits.status.cease
invalidate io.cmd.bits.status.debug
invalidate io.cmd.bits.rs2
invalidate io.cmd.bits.rs1
invalidate io.cmd.bits.inst.opcode
invalidate io.cmd.bits.inst.rd
invalidate io.cmd.bits.inst.xs2
invalidate io.cmd.bits.inst.xs1
invalidate io.cmd.bits.inst.xd
invalidate io.cmd.bits.inst.rs1
invalidate io.cmd.bits.inst.rs2
invalidate io.cmd.bits.inst.funct
invalidate io.cmd.valid
invalidate io.cmd.ready
connect io.mem.req.valid, UInt<1>(0h0)
connect io.mem.s1_kill, UInt<1>(0h0)
connect io.mem.s2_kill, UInt<1>(0h0)
connect io.mem.keep_clock_enabled, UInt<1>(0h1)
connect io.interrupt, UInt<1>(0h0)
connect io.busy, UInt<1>(0h0)
inst cmd_router of ZstdCompressorCommandRouter
connect cmd_router.clock, clock
connect cmd_router.reset, reset
connect cmd_router.io.rocc_in, io.cmd
connect io.resp.bits, cmd_router.io.rocc_out.bits
connect io.resp.valid, cmd_router.io.rocc_out.valid
connect cmd_router.io.rocc_out.ready, io.resp.ready
inst controller of CompressorController
connect controller.clock, clock
connect controller.reset, reset
connect controller.io.ALGORITHM, cmd_router.io.ALGORITHM
connect controller.io.SNAPPY_MAX_OFFSET_ALLOWED, cmd_router.io.SNAPPY_MAX_OFFSET_ALLOWED
connect controller.io.SNAPPY_RUNTIME_HT_NUM_ENTRIES_LOG2, cmd_router.io.SNAPPY_RUNTIME_HT_NUM_ENTRIES_LOG2
connect controller.io.src_info, cmd_router.io.src_info
connect controller.io.dst_info, cmd_router.io.dst_info
connect controller.io.buff_info, cmd_router.io.buff_info
connect controller.io.clevel_info, cmd_router.io.clevel_info
connect cmd_router.io.zstd_finished_cnt, controller.io.zstd_finished_cnt
connect cmd_router.io.snappy_finished_cnt, controller.io.snappy_finished_cnt
connect l2_fhdr_writer.io.userif, controller.io.zstd_control.l2io.fhdr_l2userif
connect l2_bhdr_writer.io.userif, controller.io.zstd_control.l2io.bhdr_l2userif
inst matchfinder of ZstdMatchFinder
connect matchfinder.clock, clock
connect matchfinder.reset, reset
connect l2_mf_reader.io.userif, matchfinder.io.l2io.memloader_userif
connect l2_mf_seqwriter.io.userif, matchfinder.io.l2io.seq_memwriter_userif
connect l2_mf_litwriter.io.userif, matchfinder.io.l2io.lit_memwriter_userif
connect matchfinder.io.src, controller.io.shared_control.mf_src
connect matchfinder.io.dst, controller.io.shared_control.mf_dst
connect matchfinder.io.MAX_OFFSET_ALLOWED, cmd_router.io.SNAPPY_MAX_OFFSET_ALLOWED
connect matchfinder.io.RUNTIME_HT_NUM_ENTRIES_LOG2, cmd_router.io.SNAPPY_RUNTIME_HT_NUM_ENTRIES_LOG2
connect matchfinder.io.ALGORITHM, cmd_router.io.ALGORITHM
connect controller.io.shared_control.mf_buff_consumed, matchfinder.io.buff_consumed
inst lit_compressor of ZstdLiteralEncoder
connect lit_compressor.clock, clock
connect lit_compressor.reset, reset
connect l2_huf_lit_reader.io.userif, lit_compressor.io.l2if.lit_reader
connect l2_huf_dic_reader.io.userif, lit_compressor.io.l2if.dic_reader
connect l2_huf_dic_writer.io.userif, lit_compressor.io.l2if.dic_writer
connect l2_huf_hdr_writer.io.userif, lit_compressor.io.l2if.hdr_writer
connect l2_huf_jt_writer.io.userif, lit_compressor.io.l2if.jt_writer
connect l2_huf_lit_writer.io.userif, lit_compressor.io.l2if.lit_writer
connect lit_compressor.io.src_info, controller.io.zstd_control.litcpy_src
connect lit_compressor.io.src_info2, controller.io.zstd_control.litcpy_src2
connect lit_compressor.io.dst_info, controller.io.zstd_control.litcpy_dst
connect controller.io.zstd_control.litbytes_written, lit_compressor.io.bytes_written
inst raw_lit_encoder of ZstdRawLiteralEncoder
connect raw_lit_encoder.clock, clock
connect raw_lit_encoder.reset, reset
connect l2_raw_lit_reader.io.userif, raw_lit_encoder.io.l2io_read
connect l2_raw_lit_writer.io.userif, raw_lit_encoder.io.l2io_write
connect raw_lit_encoder.io.src_info, controller.io.zstd_control.raw_lit_src
connect raw_lit_encoder.io.dst_info, controller.io.zstd_control.raw_lit_dst
connect controller.io.zstd_control.raw_litbytes_written, raw_lit_encoder.io.bytes_written
inst raw_block_encoder of ZstdRawBlockMemcopy
connect raw_block_encoder.clock, clock
connect raw_block_encoder.reset, reset
connect l2_raw_block_reader.io.userif, raw_block_encoder.io.l2if.reader
connect l2_raw_block_writer.io.userif, raw_block_encoder.io.l2if.writer
connect raw_block_encoder.io.src_info, controller.io.zstd_control.raw_block_src
connect raw_block_encoder.io.dst_info, controller.io.zstd_control.raw_block_dst
connect controller.io.zstd_control.raw_blockbytes_written, raw_block_encoder.io.bytes_written
inst seq_compressor of ZstdSequenceEncoder
connect seq_compressor.clock, clock
connect seq_compressor.reset, reset
connect l2_seq_reader.io.userif, seq_compressor.io.l2if.seq_reader
connect l2_seq_reader2.io.userif, seq_compressor.io.l2if.seq_reader2
connect l2_seq_writer.io.userif, seq_compressor.io.l2if.seq_writer
connect seq_compressor.io.src_info, controller.io.zstd_control.seqcpy_src
connect seq_compressor.io.dst_info, controller.io.zstd_control.seqcpy_dst
connect controller.io.zstd_control.seqbytes_written, seq_compressor.io.bytes_written
connect l2_fhdr_writer.io.latency_inject_cycles, cmd_router.io.LATENCY_INJECTION_CYCLES
connect l2_bhdr_writer.io.latency_inject_cycles, cmd_router.io.LATENCY_INJECTION_CYCLES
connect l2_mf_reader.io.latency_inject_cycles, cmd_router.io.LATENCY_INJECTION_CYCLES
node _l2_mf_seqwriter_io_latency_inject_cycles_T = mux(cmd_router.io.HAS_INTERMEDIATE_CACHE, UInt<1>(0h0), cmd_router.io.LATENCY_INJECTION_CYCLES)
connect l2_mf_seqwriter.io.latency_inject_cycles, _l2_mf_seqwriter_io_latency_inject_cycles_T
node _l2_mf_litwriter_io_latency_inject_cycles_T = mux(cmd_router.io.HAS_INTERMEDIATE_CACHE, UInt<1>(0h0), cmd_router.io.LATENCY_INJECTION_CYCLES)
connect l2_mf_litwriter.io.latency_inject_cycles, _l2_mf_litwriter_io_latency_inject_cycles_T
node _l2_huf_lit_reader_io_latency_inject_cycles_T = mux(cmd_router.io.HAS_INTERMEDIATE_CACHE, UInt<1>(0h0), cmd_router.io.LATENCY_INJECTION_CYCLES)
connect l2_huf_lit_reader.io.latency_inject_cycles, _l2_huf_lit_reader_io_latency_inject_cycles_T
node _l2_huf_dic_reader_io_latency_inject_cycles_T = mux(cmd_router.io.HAS_INTERMEDIATE_CACHE, UInt<1>(0h0), cmd_router.io.LATENCY_INJECTION_CYCLES)
connect l2_huf_dic_reader.io.latency_inject_cycles, _l2_huf_dic_reader_io_latency_inject_cycles_T
connect l2_huf_dic_writer.io.latency_inject_cycles, cmd_router.io.LATENCY_INJECTION_CYCLES
connect l2_huf_hdr_writer.io.latency_inject_cycles, cmd_router.io.LATENCY_INJECTION_CYCLES
connect l2_huf_jt_writer.io.latency_inject_cycles, cmd_router.io.LATENCY_INJECTION_CYCLES
connect l2_huf_lit_writer.io.latency_inject_cycles, cmd_router.io.LATENCY_INJECTION_CYCLES
node _l2_seq_reader_io_latency_inject_cycles_T = mux(cmd_router.io.HAS_INTERMEDIATE_CACHE, UInt<1>(0h0), cmd_router.io.LATENCY_INJECTION_CYCLES)
connect l2_seq_reader.io.latency_inject_cycles, _l2_seq_reader_io_latency_inject_cycles_T
node _l2_seq_reader2_io_latency_inject_cycles_T = mux(cmd_router.io.HAS_INTERMEDIATE_CACHE, UInt<1>(0h0), cmd_router.io.LATENCY_INJECTION_CYCLES)
connect l2_seq_reader2.io.latency_inject_cycles, _l2_seq_reader2_io_latency_inject_cycles_T
connect l2_seq_writer.io.latency_inject_cycles, cmd_router.io.LATENCY_INJECTION_CYCLES
node _l2_raw_block_reader_io_latency_inject_cycles_T = mux(cmd_router.io.HAS_INTERMEDIATE_CACHE, UInt<1>(0h0), cmd_router.io.LATENCY_INJECTION_CYCLES)
connect l2_raw_block_reader.io.latency_inject_cycles, _l2_raw_block_reader_io_latency_inject_cycles_T
connect l2_raw_block_writer.io.latency_inject_cycles, cmd_router.io.LATENCY_INJECTION_CYCLES
node _l2_raw_lit_reader_io_latency_inject_cycles_T = mux(cmd_router.io.HAS_INTERMEDIATE_CACHE, UInt<1>(0h0), cmd_router.io.LATENCY_INJECTION_CYCLES)
connect l2_raw_lit_reader.io.latency_inject_cycles, _l2_raw_lit_reader_io_latency_inject_cycles_T
connect l2_raw_lit_writer.io.latency_inject_cycles, cmd_router.io.LATENCY_INJECTION_CYCLES
connect l2_fhdr_writer.io.sfence, cmd_router.io.sfence_out
connect l2_fhdr_writer.io.status.valid, cmd_router.io.dmem_status_out.valid
connect l2_fhdr_writer.io.status.bits.uie, cmd_router.io.dmem_status_out.bits.status.uie
connect l2_fhdr_writer.io.status.bits.sie, cmd_router.io.dmem_status_out.bits.status.sie
connect l2_fhdr_writer.io.status.bits.hie, cmd_router.io.dmem_status_out.bits.status.hie
connect l2_fhdr_writer.io.status.bits.mie, cmd_router.io.dmem_status_out.bits.status.mie
connect l2_fhdr_writer.io.status.bits.upie, cmd_router.io.dmem_status_out.bits.status.upie
connect l2_fhdr_writer.io.status.bits.spie, cmd_router.io.dmem_status_out.bits.status.spie
connect l2_fhdr_writer.io.status.bits.ube, cmd_router.io.dmem_status_out.bits.status.ube
connect l2_fhdr_writer.io.status.bits.mpie, cmd_router.io.dmem_status_out.bits.status.mpie
connect l2_fhdr_writer.io.status.bits.spp, cmd_router.io.dmem_status_out.bits.status.spp
connect l2_fhdr_writer.io.status.bits.vs, cmd_router.io.dmem_status_out.bits.status.vs
connect l2_fhdr_writer.io.status.bits.mpp, cmd_router.io.dmem_status_out.bits.status.mpp
connect l2_fhdr_writer.io.status.bits.fs, cmd_router.io.dmem_status_out.bits.status.fs
connect l2_fhdr_writer.io.status.bits.xs, cmd_router.io.dmem_status_out.bits.status.xs
connect l2_fhdr_writer.io.status.bits.mprv, cmd_router.io.dmem_status_out.bits.status.mprv
connect l2_fhdr_writer.io.status.bits.sum, cmd_router.io.dmem_status_out.bits.status.sum
connect l2_fhdr_writer.io.status.bits.mxr, cmd_router.io.dmem_status_out.bits.status.mxr
connect l2_fhdr_writer.io.status.bits.tvm, cmd_router.io.dmem_status_out.bits.status.tvm
connect l2_fhdr_writer.io.status.bits.tw, cmd_router.io.dmem_status_out.bits.status.tw
connect l2_fhdr_writer.io.status.bits.tsr, cmd_router.io.dmem_status_out.bits.status.tsr
connect l2_fhdr_writer.io.status.bits.zero1, cmd_router.io.dmem_status_out.bits.status.zero1
connect l2_fhdr_writer.io.status.bits.sd_rv32, cmd_router.io.dmem_status_out.bits.status.sd_rv32
connect l2_fhdr_writer.io.status.bits.uxl, cmd_router.io.dmem_status_out.bits.status.uxl
connect l2_fhdr_writer.io.status.bits.sxl, cmd_router.io.dmem_status_out.bits.status.sxl
connect l2_fhdr_writer.io.status.bits.sbe, cmd_router.io.dmem_status_out.bits.status.sbe
connect l2_fhdr_writer.io.status.bits.mbe, cmd_router.io.dmem_status_out.bits.status.mbe
connect l2_fhdr_writer.io.status.bits.gva, cmd_router.io.dmem_status_out.bits.status.gva
connect l2_fhdr_writer.io.status.bits.mpv, cmd_router.io.dmem_status_out.bits.status.mpv
connect l2_fhdr_writer.io.status.bits.zero2, cmd_router.io.dmem_status_out.bits.status.zero2
connect l2_fhdr_writer.io.status.bits.sd, cmd_router.io.dmem_status_out.bits.status.sd
connect l2_fhdr_writer.io.status.bits.v, cmd_router.io.dmem_status_out.bits.status.v
connect l2_fhdr_writer.io.status.bits.prv, cmd_router.io.dmem_status_out.bits.status.prv
connect l2_fhdr_writer.io.status.bits.dv, cmd_router.io.dmem_status_out.bits.status.dv
connect l2_fhdr_writer.io.status.bits.dprv, cmd_router.io.dmem_status_out.bits.status.dprv
connect l2_fhdr_writer.io.status.bits.isa, cmd_router.io.dmem_status_out.bits.status.isa
connect l2_fhdr_writer.io.status.bits.wfi, cmd_router.io.dmem_status_out.bits.status.wfi
connect l2_fhdr_writer.io.status.bits.cease, cmd_router.io.dmem_status_out.bits.status.cease
connect l2_fhdr_writer.io.status.bits.debug, cmd_router.io.dmem_status_out.bits.status.debug
connect l2_fhdr_writer.io.ptw.customCSRs, io.ptw[0].customCSRs
connect l2_fhdr_writer.io.ptw.pmp[0], io.ptw[0].pmp[0]
connect l2_fhdr_writer.io.ptw.pmp[1], io.ptw[0].pmp[1]
connect l2_fhdr_writer.io.ptw.pmp[2], io.ptw[0].pmp[2]
connect l2_fhdr_writer.io.ptw.pmp[3], io.ptw[0].pmp[3]
connect l2_fhdr_writer.io.ptw.pmp[4], io.ptw[0].pmp[4]
connect l2_fhdr_writer.io.ptw.pmp[5], io.ptw[0].pmp[5]
connect l2_fhdr_writer.io.ptw.pmp[6], io.ptw[0].pmp[6]
connect l2_fhdr_writer.io.ptw.pmp[7], io.ptw[0].pmp[7]
connect l2_fhdr_writer.io.ptw.gstatus, io.ptw[0].gstatus
connect l2_fhdr_writer.io.ptw.hstatus, io.ptw[0].hstatus
connect l2_fhdr_writer.io.ptw.status, io.ptw[0].status
connect l2_fhdr_writer.io.ptw.vsatp, io.ptw[0].vsatp
connect l2_fhdr_writer.io.ptw.hgatp, io.ptw[0].hgatp
connect l2_fhdr_writer.io.ptw.ptbr, io.ptw[0].ptbr
connect l2_fhdr_writer.io.ptw.resp, io.ptw[0].resp
connect io.ptw[0].req.bits, l2_fhdr_writer.io.ptw.req.bits
connect io.ptw[0].req.valid, l2_fhdr_writer.io.ptw.req.valid
connect l2_fhdr_writer.io.ptw.req.ready, io.ptw[0].req.ready
connect l2_bhdr_writer.io.sfence, cmd_router.io.sfence_out
connect l2_bhdr_writer.io.status.valid, cmd_router.io.dmem_status_out.valid
connect l2_bhdr_writer.io.status.bits.uie, cmd_router.io.dmem_status_out.bits.status.uie
connect l2_bhdr_writer.io.status.bits.sie, cmd_router.io.dmem_status_out.bits.status.sie
connect l2_bhdr_writer.io.status.bits.hie, cmd_router.io.dmem_status_out.bits.status.hie
connect l2_bhdr_writer.io.status.bits.mie, cmd_router.io.dmem_status_out.bits.status.mie
connect l2_bhdr_writer.io.status.bits.upie, cmd_router.io.dmem_status_out.bits.status.upie
connect l2_bhdr_writer.io.status.bits.spie, cmd_router.io.dmem_status_out.bits.status.spie
connect l2_bhdr_writer.io.status.bits.ube, cmd_router.io.dmem_status_out.bits.status.ube
connect l2_bhdr_writer.io.status.bits.mpie, cmd_router.io.dmem_status_out.bits.status.mpie
connect l2_bhdr_writer.io.status.bits.spp, cmd_router.io.dmem_status_out.bits.status.spp
connect l2_bhdr_writer.io.status.bits.vs, cmd_router.io.dmem_status_out.bits.status.vs
connect l2_bhdr_writer.io.status.bits.mpp, cmd_router.io.dmem_status_out.bits.status.mpp
connect l2_bhdr_writer.io.status.bits.fs, cmd_router.io.dmem_status_out.bits.status.fs
connect l2_bhdr_writer.io.status.bits.xs, cmd_router.io.dmem_status_out.bits.status.xs
connect l2_bhdr_writer.io.status.bits.mprv, cmd_router.io.dmem_status_out.bits.status.mprv
connect l2_bhdr_writer.io.status.bits.sum, cmd_router.io.dmem_status_out.bits.status.sum
connect l2_bhdr_writer.io.status.bits.mxr, cmd_router.io.dmem_status_out.bits.status.mxr
connect l2_bhdr_writer.io.status.bits.tvm, cmd_router.io.dmem_status_out.bits.status.tvm
connect l2_bhdr_writer.io.status.bits.tw, cmd_router.io.dmem_status_out.bits.status.tw
connect l2_bhdr_writer.io.status.bits.tsr, cmd_router.io.dmem_status_out.bits.status.tsr
connect l2_bhdr_writer.io.status.bits.zero1, cmd_router.io.dmem_status_out.bits.status.zero1
connect l2_bhdr_writer.io.status.bits.sd_rv32, cmd_router.io.dmem_status_out.bits.status.sd_rv32
connect l2_bhdr_writer.io.status.bits.uxl, cmd_router.io.dmem_status_out.bits.status.uxl
connect l2_bhdr_writer.io.status.bits.sxl, cmd_router.io.dmem_status_out.bits.status.sxl
connect l2_bhdr_writer.io.status.bits.sbe, cmd_router.io.dmem_status_out.bits.status.sbe
connect l2_bhdr_writer.io.status.bits.mbe, cmd_router.io.dmem_status_out.bits.status.mbe
connect l2_bhdr_writer.io.status.bits.gva, cmd_router.io.dmem_status_out.bits.status.gva
connect l2_bhdr_writer.io.status.bits.mpv, cmd_router.io.dmem_status_out.bits.status.mpv
connect l2_bhdr_writer.io.status.bits.zero2, cmd_router.io.dmem_status_out.bits.status.zero2
connect l2_bhdr_writer.io.status.bits.sd, cmd_router.io.dmem_status_out.bits.status.sd
connect l2_bhdr_writer.io.status.bits.v, cmd_router.io.dmem_status_out.bits.status.v
connect l2_bhdr_writer.io.status.bits.prv, cmd_router.io.dmem_status_out.bits.status.prv
connect l2_bhdr_writer.io.status.bits.dv, cmd_router.io.dmem_status_out.bits.status.dv
connect l2_bhdr_writer.io.status.bits.dprv, cmd_router.io.dmem_status_out.bits.status.dprv
connect l2_bhdr_writer.io.status.bits.isa, cmd_router.io.dmem_status_out.bits.status.isa
connect l2_bhdr_writer.io.status.bits.wfi, cmd_router.io.dmem_status_out.bits.status.wfi
connect l2_bhdr_writer.io.status.bits.cease, cmd_router.io.dmem_status_out.bits.status.cease
connect l2_bhdr_writer.io.status.bits.debug, cmd_router.io.dmem_status_out.bits.status.debug
connect l2_bhdr_writer.io.ptw.customCSRs, io.ptw[1].customCSRs
connect l2_bhdr_writer.io.ptw.pmp[0], io.ptw[1].pmp[0]
connect l2_bhdr_writer.io.ptw.pmp[1], io.ptw[1].pmp[1]
connect l2_bhdr_writer.io.ptw.pmp[2], io.ptw[1].pmp[2]
connect l2_bhdr_writer.io.ptw.pmp[3], io.ptw[1].pmp[3]
connect l2_bhdr_writer.io.ptw.pmp[4], io.ptw[1].pmp[4]
connect l2_bhdr_writer.io.ptw.pmp[5], io.ptw[1].pmp[5]
connect l2_bhdr_writer.io.ptw.pmp[6], io.ptw[1].pmp[6]
connect l2_bhdr_writer.io.ptw.pmp[7], io.ptw[1].pmp[7]
connect l2_bhdr_writer.io.ptw.gstatus, io.ptw[1].gstatus
connect l2_bhdr_writer.io.ptw.hstatus, io.ptw[1].hstatus
connect l2_bhdr_writer.io.ptw.status, io.ptw[1].status
connect l2_bhdr_writer.io.ptw.vsatp, io.ptw[1].vsatp
connect l2_bhdr_writer.io.ptw.hgatp, io.ptw[1].hgatp
connect l2_bhdr_writer.io.ptw.ptbr, io.ptw[1].ptbr
connect l2_bhdr_writer.io.ptw.resp, io.ptw[1].resp
connect io.ptw[1].req.bits, l2_bhdr_writer.io.ptw.req.bits
connect io.ptw[1].req.valid, l2_bhdr_writer.io.ptw.req.valid
connect l2_bhdr_writer.io.ptw.req.ready, io.ptw[1].req.ready
connect l2_mf_reader.io.sfence, cmd_router.io.sfence_out
connect l2_mf_reader.io.status.valid, cmd_router.io.dmem_status_out.valid
connect l2_mf_reader.io.status.bits.uie, cmd_router.io.dmem_status_out.bits.status.uie
connect l2_mf_reader.io.status.bits.sie, cmd_router.io.dmem_status_out.bits.status.sie
connect l2_mf_reader.io.status.bits.hie, cmd_router.io.dmem_status_out.bits.status.hie
connect l2_mf_reader.io.status.bits.mie, cmd_router.io.dmem_status_out.bits.status.mie
connect l2_mf_reader.io.status.bits.upie, cmd_router.io.dmem_status_out.bits.status.upie
connect l2_mf_reader.io.status.bits.spie, cmd_router.io.dmem_status_out.bits.status.spie
connect l2_mf_reader.io.status.bits.ube, cmd_router.io.dmem_status_out.bits.status.ube
connect l2_mf_reader.io.status.bits.mpie, cmd_router.io.dmem_status_out.bits.status.mpie
connect l2_mf_reader.io.status.bits.spp, cmd_router.io.dmem_status_out.bits.status.spp
connect l2_mf_reader.io.status.bits.vs, cmd_router.io.dmem_status_out.bits.status.vs
connect l2_mf_reader.io.status.bits.mpp, cmd_router.io.dmem_status_out.bits.status.mpp
connect l2_mf_reader.io.status.bits.fs, cmd_router.io.dmem_status_out.bits.status.fs
connect l2_mf_reader.io.status.bits.xs, cmd_router.io.dmem_status_out.bits.status.xs
connect l2_mf_reader.io.status.bits.mprv, cmd_router.io.dmem_status_out.bits.status.mprv
connect l2_mf_reader.io.status.bits.sum, cmd_router.io.dmem_status_out.bits.status.sum
connect l2_mf_reader.io.status.bits.mxr, cmd_router.io.dmem_status_out.bits.status.mxr
connect l2_mf_reader.io.status.bits.tvm, cmd_router.io.dmem_status_out.bits.status.tvm
connect l2_mf_reader.io.status.bits.tw, cmd_router.io.dmem_status_out.bits.status.tw
connect l2_mf_reader.io.status.bits.tsr, cmd_router.io.dmem_status_out.bits.status.tsr
connect l2_mf_reader.io.status.bits.zero1, cmd_router.io.dmem_status_out.bits.status.zero1
connect l2_mf_reader.io.status.bits.sd_rv32, cmd_router.io.dmem_status_out.bits.status.sd_rv32
connect l2_mf_reader.io.status.bits.uxl, cmd_router.io.dmem_status_out.bits.status.uxl
connect l2_mf_reader.io.status.bits.sxl, cmd_router.io.dmem_status_out.bits.status.sxl
connect l2_mf_reader.io.status.bits.sbe, cmd_router.io.dmem_status_out.bits.status.sbe
connect l2_mf_reader.io.status.bits.mbe, cmd_router.io.dmem_status_out.bits.status.mbe
connect l2_mf_reader.io.status.bits.gva, cmd_router.io.dmem_status_out.bits.status.gva
connect l2_mf_reader.io.status.bits.mpv, cmd_router.io.dmem_status_out.bits.status.mpv
connect l2_mf_reader.io.status.bits.zero2, cmd_router.io.dmem_status_out.bits.status.zero2
connect l2_mf_reader.io.status.bits.sd, cmd_router.io.dmem_status_out.bits.status.sd
connect l2_mf_reader.io.status.bits.v, cmd_router.io.dmem_status_out.bits.status.v
connect l2_mf_reader.io.status.bits.prv, cmd_router.io.dmem_status_out.bits.status.prv
connect l2_mf_reader.io.status.bits.dv, cmd_router.io.dmem_status_out.bits.status.dv
connect l2_mf_reader.io.status.bits.dprv, cmd_router.io.dmem_status_out.bits.status.dprv
connect l2_mf_reader.io.status.bits.isa, cmd_router.io.dmem_status_out.bits.status.isa
connect l2_mf_reader.io.status.bits.wfi, cmd_router.io.dmem_status_out.bits.status.wfi
connect l2_mf_reader.io.status.bits.cease, cmd_router.io.dmem_status_out.bits.status.cease
connect l2_mf_reader.io.status.bits.debug, cmd_router.io.dmem_status_out.bits.status.debug
connect l2_mf_reader.io.ptw.customCSRs, io.ptw[2].customCSRs
connect l2_mf_reader.io.ptw.pmp[0], io.ptw[2].pmp[0]
connect l2_mf_reader.io.ptw.pmp[1], io.ptw[2].pmp[1]
connect l2_mf_reader.io.ptw.pmp[2], io.ptw[2].pmp[2]
connect l2_mf_reader.io.ptw.pmp[3], io.ptw[2].pmp[3]
connect l2_mf_reader.io.ptw.pmp[4], io.ptw[2].pmp[4]
connect l2_mf_reader.io.ptw.pmp[5], io.ptw[2].pmp[5]
connect l2_mf_reader.io.ptw.pmp[6], io.ptw[2].pmp[6]
connect l2_mf_reader.io.ptw.pmp[7], io.ptw[2].pmp[7]
connect l2_mf_reader.io.ptw.gstatus, io.ptw[2].gstatus
connect l2_mf_reader.io.ptw.hstatus, io.ptw[2].hstatus
connect l2_mf_reader.io.ptw.status, io.ptw[2].status
connect l2_mf_reader.io.ptw.vsatp, io.ptw[2].vsatp
connect l2_mf_reader.io.ptw.hgatp, io.ptw[2].hgatp
connect l2_mf_reader.io.ptw.ptbr, io.ptw[2].ptbr
connect l2_mf_reader.io.ptw.resp, io.ptw[2].resp
connect io.ptw[2].req.bits, l2_mf_reader.io.ptw.req.bits
connect io.ptw[2].req.valid, l2_mf_reader.io.ptw.req.valid
connect l2_mf_reader.io.ptw.req.ready, io.ptw[2].req.ready
connect l2_mf_seqwriter.io.sfence, cmd_router.io.sfence_out
connect l2_mf_seqwriter.io.status.valid, cmd_router.io.dmem_status_out.valid
connect l2_mf_seqwriter.io.status.bits.uie, cmd_router.io.dmem_status_out.bits.status.uie
connect l2_mf_seqwriter.io.status.bits.sie, cmd_router.io.dmem_status_out.bits.status.sie
connect l2_mf_seqwriter.io.status.bits.hie, cmd_router.io.dmem_status_out.bits.status.hie
connect l2_mf_seqwriter.io.status.bits.mie, cmd_router.io.dmem_status_out.bits.status.mie
connect l2_mf_seqwriter.io.status.bits.upie, cmd_router.io.dmem_status_out.bits.status.upie
connect l2_mf_seqwriter.io.status.bits.spie, cmd_router.io.dmem_status_out.bits.status.spie
connect l2_mf_seqwriter.io.status.bits.ube, cmd_router.io.dmem_status_out.bits.status.ube
connect l2_mf_seqwriter.io.status.bits.mpie, cmd_router.io.dmem_status_out.bits.status.mpie
connect l2_mf_seqwriter.io.status.bits.spp, cmd_router.io.dmem_status_out.bits.status.spp
connect l2_mf_seqwriter.io.status.bits.vs, cmd_router.io.dmem_status_out.bits.status.vs
connect l2_mf_seqwriter.io.status.bits.mpp, cmd_router.io.dmem_status_out.bits.status.mpp
connect l2_mf_seqwriter.io.status.bits.fs, cmd_router.io.dmem_status_out.bits.status.fs
connect l2_mf_seqwriter.io.status.bits.xs, cmd_router.io.dmem_status_out.bits.status.xs
connect l2_mf_seqwriter.io.status.bits.mprv, cmd_router.io.dmem_status_out.bits.status.mprv
connect l2_mf_seqwriter.io.status.bits.sum, cmd_router.io.dmem_status_out.bits.status.sum
connect l2_mf_seqwriter.io.status.bits.mxr, cmd_router.io.dmem_status_out.bits.status.mxr
connect l2_mf_seqwriter.io.status.bits.tvm, cmd_router.io.dmem_status_out.bits.status.tvm
connect l2_mf_seqwriter.io.status.bits.tw, cmd_router.io.dmem_status_out.bits.status.tw
connect l2_mf_seqwriter.io.status.bits.tsr, cmd_router.io.dmem_status_out.bits.status.tsr
connect l2_mf_seqwriter.io.status.bits.zero1, cmd_router.io.dmem_status_out.bits.status.zero1
connect l2_mf_seqwriter.io.status.bits.sd_rv32, cmd_router.io.dmem_status_out.bits.status.sd_rv32
connect l2_mf_seqwriter.io.status.bits.uxl, cmd_router.io.dmem_status_out.bits.status.uxl
connect l2_mf_seqwriter.io.status.bits.sxl, cmd_router.io.dmem_status_out.bits.status.sxl
connect l2_mf_seqwriter.io.status.bits.sbe, cmd_router.io.dmem_status_out.bits.status.sbe
connect l2_mf_seqwriter.io.status.bits.mbe, cmd_router.io.dmem_status_out.bits.status.mbe
connect l2_mf_seqwriter.io.status.bits.gva, cmd_router.io.dmem_status_out.bits.status.gva
connect l2_mf_seqwriter.io.status.bits.mpv, cmd_router.io.dmem_status_out.bits.status.mpv
connect l2_mf_seqwriter.io.status.bits.zero2, cmd_router.io.dmem_status_out.bits.status.zero2
connect l2_mf_seqwriter.io.status.bits.sd, cmd_router.io.dmem_status_out.bits.status.sd
connect l2_mf_seqwriter.io.status.bits.v, cmd_router.io.dmem_status_out.bits.status.v
connect l2_mf_seqwriter.io.status.bits.prv, cmd_router.io.dmem_status_out.bits.status.prv
connect l2_mf_seqwriter.io.status.bits.dv, cmd_router.io.dmem_status_out.bits.status.dv
connect l2_mf_seqwriter.io.status.bits.dprv, cmd_router.io.dmem_status_out.bits.status.dprv
connect l2_mf_seqwriter.io.status.bits.isa, cmd_router.io.dmem_status_out.bits.status.isa
connect l2_mf_seqwriter.io.status.bits.wfi, cmd_router.io.dmem_status_out.bits.status.wfi
connect l2_mf_seqwriter.io.status.bits.cease, cmd_router.io.dmem_status_out.bits.status.cease
connect l2_mf_seqwriter.io.status.bits.debug, cmd_router.io.dmem_status_out.bits.status.debug
connect l2_mf_seqwriter.io.ptw.customCSRs, io.ptw[3].customCSRs
connect l2_mf_seqwriter.io.ptw.pmp[0], io.ptw[3].pmp[0]
connect l2_mf_seqwriter.io.ptw.pmp[1], io.ptw[3].pmp[1]
connect l2_mf_seqwriter.io.ptw.pmp[2], io.ptw[3].pmp[2]
connect l2_mf_seqwriter.io.ptw.pmp[3], io.ptw[3].pmp[3]
connect l2_mf_seqwriter.io.ptw.pmp[4], io.ptw[3].pmp[4]
connect l2_mf_seqwriter.io.ptw.pmp[5], io.ptw[3].pmp[5]
connect l2_mf_seqwriter.io.ptw.pmp[6], io.ptw[3].pmp[6]
connect l2_mf_seqwriter.io.ptw.pmp[7], io.ptw[3].pmp[7]
connect l2_mf_seqwriter.io.ptw.gstatus, io.ptw[3].gstatus
connect l2_mf_seqwriter.io.ptw.hstatus, io.ptw[3].hstatus
connect l2_mf_seqwriter.io.ptw.status, io.ptw[3].status
connect l2_mf_seqwriter.io.ptw.vsatp, io.ptw[3].vsatp
connect l2_mf_seqwriter.io.ptw.hgatp, io.ptw[3].hgatp
connect l2_mf_seqwriter.io.ptw.ptbr, io.ptw[3].ptbr
connect l2_mf_seqwriter.io.ptw.resp, io.ptw[3].resp
connect io.ptw[3].req.bits, l2_mf_seqwriter.io.ptw.req.bits
connect io.ptw[3].req.valid, l2_mf_seqwriter.io.ptw.req.valid
connect l2_mf_seqwriter.io.ptw.req.ready, io.ptw[3].req.ready
connect l2_mf_litwriter.io.sfence, cmd_router.io.sfence_out
connect l2_mf_litwriter.io.status.valid, cmd_router.io.dmem_status_out.valid
connect l2_mf_litwriter.io.status.bits.uie, cmd_router.io.dmem_status_out.bits.status.uie
connect l2_mf_litwriter.io.status.bits.sie, cmd_router.io.dmem_status_out.bits.status.sie
connect l2_mf_litwriter.io.status.bits.hie, cmd_router.io.dmem_status_out.bits.status.hie
connect l2_mf_litwriter.io.status.bits.mie, cmd_router.io.dmem_status_out.bits.status.mie
connect l2_mf_litwriter.io.status.bits.upie, cmd_router.io.dmem_status_out.bits.status.upie
connect l2_mf_litwriter.io.status.bits.spie, cmd_router.io.dmem_status_out.bits.status.spie
connect l2_mf_litwriter.io.status.bits.ube, cmd_router.io.dmem_status_out.bits.status.ube
connect l2_mf_litwriter.io.status.bits.mpie, cmd_router.io.dmem_status_out.bits.status.mpie
connect l2_mf_litwriter.io.status.bits.spp, cmd_router.io.dmem_status_out.bits.status.spp
connect l2_mf_litwriter.io.status.bits.vs, cmd_router.io.dmem_status_out.bits.status.vs
connect l2_mf_litwriter.io.status.bits.mpp, cmd_router.io.dmem_status_out.bits.status.mpp
connect l2_mf_litwriter.io.status.bits.fs, cmd_router.io.dmem_status_out.bits.status.fs
connect l2_mf_litwriter.io.status.bits.xs, cmd_router.io.dmem_status_out.bits.status.xs
connect l2_mf_litwriter.io.status.bits.mprv, cmd_router.io.dmem_status_out.bits.status.mprv
connect l2_mf_litwriter.io.status.bits.sum, cmd_router.io.dmem_status_out.bits.status.sum
connect l2_mf_litwriter.io.status.bits.mxr, cmd_router.io.dmem_status_out.bits.status.mxr
connect l2_mf_litwriter.io.status.bits.tvm, cmd_router.io.dmem_status_out.bits.status.tvm
connect l2_mf_litwriter.io.status.bits.tw, cmd_router.io.dmem_status_out.bits.status.tw
connect l2_mf_litwriter.io.status.bits.tsr, cmd_router.io.dmem_status_out.bits.status.tsr
connect l2_mf_litwriter.io.status.bits.zero1, cmd_router.io.dmem_status_out.bits.status.zero1
connect l2_mf_litwriter.io.status.bits.sd_rv32, cmd_router.io.dmem_status_out.bits.status.sd_rv32
connect l2_mf_litwriter.io.status.bits.uxl, cmd_router.io.dmem_status_out.bits.status.uxl
connect l2_mf_litwriter.io.status.bits.sxl, cmd_router.io.dmem_status_out.bits.status.sxl
connect l2_mf_litwriter.io.status.bits.sbe, cmd_router.io.dmem_status_out.bits.status.sbe
connect l2_mf_litwriter.io.status.bits.mbe, cmd_router.io.dmem_status_out.bits.status.mbe
connect l2_mf_litwriter.io.status.bits.gva, cmd_router.io.dmem_status_out.bits.status.gva
connect l2_mf_litwriter.io.status.bits.mpv, cmd_router.io.dmem_status_out.bits.status.mpv
connect l2_mf_litwriter.io.status.bits.zero2, cmd_router.io.dmem_status_out.bits.status.zero2
connect l2_mf_litwriter.io.status.bits.sd, cmd_router.io.dmem_status_out.bits.status.sd
connect l2_mf_litwriter.io.status.bits.v, cmd_router.io.dmem_status_out.bits.status.v
connect l2_mf_litwriter.io.status.bits.prv, cmd_router.io.dmem_status_out.bits.status.prv
connect l2_mf_litwriter.io.status.bits.dv, cmd_router.io.dmem_status_out.bits.status.dv
connect l2_mf_litwriter.io.status.bits.dprv, cmd_router.io.dmem_status_out.bits.status.dprv
connect l2_mf_litwriter.io.status.bits.isa, cmd_router.io.dmem_status_out.bits.status.isa
connect l2_mf_litwriter.io.status.bits.wfi, cmd_router.io.dmem_status_out.bits.status.wfi
connect l2_mf_litwriter.io.status.bits.cease, cmd_router.io.dmem_status_out.bits.status.cease
connect l2_mf_litwriter.io.status.bits.debug, cmd_router.io.dmem_status_out.bits.status.debug
connect l2_mf_litwriter.io.ptw.customCSRs, io.ptw[4].customCSRs
connect l2_mf_litwriter.io.ptw.pmp[0], io.ptw[4].pmp[0]
connect l2_mf_litwriter.io.ptw.pmp[1], io.ptw[4].pmp[1]
connect l2_mf_litwriter.io.ptw.pmp[2], io.ptw[4].pmp[2]
connect l2_mf_litwriter.io.ptw.pmp[3], io.ptw[4].pmp[3]
connect l2_mf_litwriter.io.ptw.pmp[4], io.ptw[4].pmp[4]
connect l2_mf_litwriter.io.ptw.pmp[5], io.ptw[4].pmp[5]
connect l2_mf_litwriter.io.ptw.pmp[6], io.ptw[4].pmp[6]
connect l2_mf_litwriter.io.ptw.pmp[7], io.ptw[4].pmp[7]
connect l2_mf_litwriter.io.ptw.gstatus, io.ptw[4].gstatus
connect l2_mf_litwriter.io.ptw.hstatus, io.ptw[4].hstatus
connect l2_mf_litwriter.io.ptw.status, io.ptw[4].status
connect l2_mf_litwriter.io.ptw.vsatp, io.ptw[4].vsatp
connect l2_mf_litwriter.io.ptw.hgatp, io.ptw[4].hgatp
connect l2_mf_litwriter.io.ptw.ptbr, io.ptw[4].ptbr
connect l2_mf_litwriter.io.ptw.resp, io.ptw[4].resp
connect io.ptw[4].req.bits, l2_mf_litwriter.io.ptw.req.bits
connect io.ptw[4].req.valid, l2_mf_litwriter.io.ptw.req.valid
connect l2_mf_litwriter.io.ptw.req.ready, io.ptw[4].req.ready
connect l2_huf_lit_reader.io.sfence, cmd_router.io.sfence_out
connect l2_huf_lit_reader.io.status.valid, cmd_router.io.dmem_status_out.valid
connect l2_huf_lit_reader.io.status.bits.uie, cmd_router.io.dmem_status_out.bits.status.uie
connect l2_huf_lit_reader.io.status.bits.sie, cmd_router.io.dmem_status_out.bits.status.sie
connect l2_huf_lit_reader.io.status.bits.hie, cmd_router.io.dmem_status_out.bits.status.hie
connect l2_huf_lit_reader.io.status.bits.mie, cmd_router.io.dmem_status_out.bits.status.mie
connect l2_huf_lit_reader.io.status.bits.upie, cmd_router.io.dmem_status_out.bits.status.upie
connect l2_huf_lit_reader.io.status.bits.spie, cmd_router.io.dmem_status_out.bits.status.spie
connect l2_huf_lit_reader.io.status.bits.ube, cmd_router.io.dmem_status_out.bits.status.ube
connect l2_huf_lit_reader.io.status.bits.mpie, cmd_router.io.dmem_status_out.bits.status.mpie
connect l2_huf_lit_reader.io.status.bits.spp, cmd_router.io.dmem_status_out.bits.status.spp
connect l2_huf_lit_reader.io.status.bits.vs, cmd_router.io.dmem_status_out.bits.status.vs
connect l2_huf_lit_reader.io.status.bits.mpp, cmd_router.io.dmem_status_out.bits.status.mpp
connect l2_huf_lit_reader.io.status.bits.fs, cmd_router.io.dmem_status_out.bits.status.fs
connect l2_huf_lit_reader.io.status.bits.xs, cmd_router.io.dmem_status_out.bits.status.xs
connect l2_huf_lit_reader.io.status.bits.mprv, cmd_router.io.dmem_status_out.bits.status.mprv
connect l2_huf_lit_reader.io.status.bits.sum, cmd_router.io.dmem_status_out.bits.status.sum
connect l2_huf_lit_reader.io.status.bits.mxr, cmd_router.io.dmem_status_out.bits.status.mxr
connect l2_huf_lit_reader.io.status.bits.tvm, cmd_router.io.dmem_status_out.bits.status.tvm
connect l2_huf_lit_reader.io.status.bits.tw, cmd_router.io.dmem_status_out.bits.status.tw
connect l2_huf_lit_reader.io.status.bits.tsr, cmd_router.io.dmem_status_out.bits.status.tsr
connect l2_huf_lit_reader.io.status.bits.zero1, cmd_router.io.dmem_status_out.bits.status.zero1
connect l2_huf_lit_reader.io.status.bits.sd_rv32, cmd_router.io.dmem_status_out.bits.status.sd_rv32
connect l2_huf_lit_reader.io.status.bits.uxl, cmd_router.io.dmem_status_out.bits.status.uxl
connect l2_huf_lit_reader.io.status.bits.sxl, cmd_router.io.dmem_status_out.bits.status.sxl
connect l2_huf_lit_reader.io.status.bits.sbe, cmd_router.io.dmem_status_out.bits.status.sbe
connect l2_huf_lit_reader.io.status.bits.mbe, cmd_router.io.dmem_status_out.bits.status.mbe
connect l2_huf_lit_reader.io.status.bits.gva, cmd_router.io.dmem_status_out.bits.status.gva
connect l2_huf_lit_reader.io.status.bits.mpv, cmd_router.io.dmem_status_out.bits.status.mpv
connect l2_huf_lit_reader.io.status.bits.zero2, cmd_router.io.dmem_status_out.bits.status.zero2
connect l2_huf_lit_reader.io.status.bits.sd, cmd_router.io.dmem_status_out.bits.status.sd
connect l2_huf_lit_reader.io.status.bits.v, cmd_router.io.dmem_status_out.bits.status.v
connect l2_huf_lit_reader.io.status.bits.prv, cmd_router.io.dmem_status_out.bits.status.prv
connect l2_huf_lit_reader.io.status.bits.dv, cmd_router.io.dmem_status_out.bits.status.dv
connect l2_huf_lit_reader.io.status.bits.dprv, cmd_router.io.dmem_status_out.bits.status.dprv
connect l2_huf_lit_reader.io.status.bits.isa, cmd_router.io.dmem_status_out.bits.status.isa
connect l2_huf_lit_reader.io.status.bits.wfi, cmd_router.io.dmem_status_out.bits.status.wfi
connect l2_huf_lit_reader.io.status.bits.cease, cmd_router.io.dmem_status_out.bits.status.cease
connect l2_huf_lit_reader.io.status.bits.debug, cmd_router.io.dmem_status_out.bits.status.debug
connect l2_huf_lit_reader.io.ptw.customCSRs, io.ptw[5].customCSRs
connect l2_huf_lit_reader.io.ptw.pmp[0], io.ptw[5].pmp[0]
connect l2_huf_lit_reader.io.ptw.pmp[1], io.ptw[5].pmp[1]
connect l2_huf_lit_reader.io.ptw.pmp[2], io.ptw[5].pmp[2]
connect l2_huf_lit_reader.io.ptw.pmp[3], io.ptw[5].pmp[3]
connect l2_huf_lit_reader.io.ptw.pmp[4], io.ptw[5].pmp[4]
connect l2_huf_lit_reader.io.ptw.pmp[5], io.ptw[5].pmp[5]
connect l2_huf_lit_reader.io.ptw.pmp[6], io.ptw[5].pmp[6]
connect l2_huf_lit_reader.io.ptw.pmp[7], io.ptw[5].pmp[7]
connect l2_huf_lit_reader.io.ptw.gstatus, io.ptw[5].gstatus
connect l2_huf_lit_reader.io.ptw.hstatus, io.ptw[5].hstatus
connect l2_huf_lit_reader.io.ptw.status, io.ptw[5].status
connect l2_huf_lit_reader.io.ptw.vsatp, io.ptw[5].vsatp
connect l2_huf_lit_reader.io.ptw.hgatp, io.ptw[5].hgatp
connect l2_huf_lit_reader.io.ptw.ptbr, io.ptw[5].ptbr
connect l2_huf_lit_reader.io.ptw.resp, io.ptw[5].resp
connect io.ptw[5].req.bits, l2_huf_lit_reader.io.ptw.req.bits
connect io.ptw[5].req.valid, l2_huf_lit_reader.io.ptw.req.valid
connect l2_huf_lit_reader.io.ptw.req.ready, io.ptw[5].req.ready
connect l2_huf_dic_reader.io.sfence, cmd_router.io.sfence_out
connect l2_huf_dic_reader.io.status.valid, cmd_router.io.dmem_status_out.valid
connect l2_huf_dic_reader.io.status.bits.uie, cmd_router.io.dmem_status_out.bits.status.uie
connect l2_huf_dic_reader.io.status.bits.sie, cmd_router.io.dmem_status_out.bits.status.sie
connect l2_huf_dic_reader.io.status.bits.hie, cmd_router.io.dmem_status_out.bits.status.hie
connect l2_huf_dic_reader.io.status.bits.mie, cmd_router.io.dmem_status_out.bits.status.mie
connect l2_huf_dic_reader.io.status.bits.upie, cmd_router.io.dmem_status_out.bits.status.upie
connect l2_huf_dic_reader.io.status.bits.spie, cmd_router.io.dmem_status_out.bits.status.spie
connect l2_huf_dic_reader.io.status.bits.ube, cmd_router.io.dmem_status_out.bits.status.ube
connect l2_huf_dic_reader.io.status.bits.mpie, cmd_router.io.dmem_status_out.bits.status.mpie
connect l2_huf_dic_reader.io.status.bits.spp, cmd_router.io.dmem_status_out.bits.status.spp
connect l2_huf_dic_reader.io.status.bits.vs, cmd_router.io.dmem_status_out.bits.status.vs
connect l2_huf_dic_reader.io.status.bits.mpp, cmd_router.io.dmem_status_out.bits.status.mpp
connect l2_huf_dic_reader.io.status.bits.fs, cmd_router.io.dmem_status_out.bits.status.fs
connect l2_huf_dic_reader.io.status.bits.xs, cmd_router.io.dmem_status_out.bits.status.xs
connect l2_huf_dic_reader.io.status.bits.mprv, cmd_router.io.dmem_status_out.bits.status.mprv
connect l2_huf_dic_reader.io.status.bits.sum, cmd_router.io.dmem_status_out.bits.status.sum
connect l2_huf_dic_reader.io.status.bits.mxr, cmd_router.io.dmem_status_out.bits.status.mxr
connect l2_huf_dic_reader.io.status.bits.tvm, cmd_router.io.dmem_status_out.bits.status.tvm
connect l2_huf_dic_reader.io.status.bits.tw, cmd_router.io.dmem_status_out.bits.status.tw
connect l2_huf_dic_reader.io.status.bits.tsr, cmd_router.io.dmem_status_out.bits.status.tsr
connect l2_huf_dic_reader.io.status.bits.zero1, cmd_router.io.dmem_status_out.bits.status.zero1
connect l2_huf_dic_reader.io.status.bits.sd_rv32, cmd_router.io.dmem_status_out.bits.status.sd_rv32
connect l2_huf_dic_reader.io.status.bits.uxl, cmd_router.io.dmem_status_out.bits.status.uxl
connect l2_huf_dic_reader.io.status.bits.sxl, cmd_router.io.dmem_status_out.bits.status.sxl
connect l2_huf_dic_reader.io.status.bits.sbe, cmd_router.io.dmem_status_out.bits.status.sbe
connect l2_huf_dic_reader.io.status.bits.mbe, cmd_router.io.dmem_status_out.bits.status.mbe
connect l2_huf_dic_reader.io.status.bits.gva, cmd_router.io.dmem_status_out.bits.status.gva
connect l2_huf_dic_reader.io.status.bits.mpv, cmd_router.io.dmem_status_out.bits.status.mpv
connect l2_huf_dic_reader.io.status.bits.zero2, cmd_router.io.dmem_status_out.bits.status.zero2
connect l2_huf_dic_reader.io.status.bits.sd, cmd_router.io.dmem_status_out.bits.status.sd
connect l2_huf_dic_reader.io.status.bits.v, cmd_router.io.dmem_status_out.bits.status.v
connect l2_huf_dic_reader.io.status.bits.prv, cmd_router.io.dmem_status_out.bits.status.prv
connect l2_huf_dic_reader.io.status.bits.dv, cmd_router.io.dmem_status_out.bits.status.dv
connect l2_huf_dic_reader.io.status.bits.dprv, cmd_router.io.dmem_status_out.bits.status.dprv
connect l2_huf_dic_reader.io.status.bits.isa, cmd_router.io.dmem_status_out.bits.status.isa
connect l2_huf_dic_reader.io.status.bits.wfi, cmd_router.io.dmem_status_out.bits.status.wfi
connect l2_huf_dic_reader.io.status.bits.cease, cmd_router.io.dmem_status_out.bits.status.cease
connect l2_huf_dic_reader.io.status.bits.debug, cmd_router.io.dmem_status_out.bits.status.debug
connect l2_huf_dic_reader.io.ptw.customCSRs, io.ptw[6].customCSRs
connect l2_huf_dic_reader.io.ptw.pmp[0], io.ptw[6].pmp[0]
connect l2_huf_dic_reader.io.ptw.pmp[1], io.ptw[6].pmp[1]
connect l2_huf_dic_reader.io.ptw.pmp[2], io.ptw[6].pmp[2]
connect l2_huf_dic_reader.io.ptw.pmp[3], io.ptw[6].pmp[3]
connect l2_huf_dic_reader.io.ptw.pmp[4], io.ptw[6].pmp[4]
connect l2_huf_dic_reader.io.ptw.pmp[5], io.ptw[6].pmp[5]
connect l2_huf_dic_reader.io.ptw.pmp[6], io.ptw[6].pmp[6]
connect l2_huf_dic_reader.io.ptw.pmp[7], io.ptw[6].pmp[7]
connect l2_huf_dic_reader.io.ptw.gstatus, io.ptw[6].gstatus
connect l2_huf_dic_reader.io.ptw.hstatus, io.ptw[6].hstatus
connect l2_huf_dic_reader.io.ptw.status, io.ptw[6].status
connect l2_huf_dic_reader.io.ptw.vsatp, io.ptw[6].vsatp
connect l2_huf_dic_reader.io.ptw.hgatp, io.ptw[6].hgatp
connect l2_huf_dic_reader.io.ptw.ptbr, io.ptw[6].ptbr
connect l2_huf_dic_reader.io.ptw.resp, io.ptw[6].resp
connect io.ptw[6].req.bits, l2_huf_dic_reader.io.ptw.req.bits
connect io.ptw[6].req.valid, l2_huf_dic_reader.io.ptw.req.valid
connect l2_huf_dic_reader.io.ptw.req.ready, io.ptw[6].req.ready
connect l2_huf_dic_writer.io.sfence, cmd_router.io.sfence_out
connect l2_huf_dic_writer.io.status.valid, cmd_router.io.dmem_status_out.valid
connect l2_huf_dic_writer.io.status.bits.uie, cmd_router.io.dmem_status_out.bits.status.uie
connect l2_huf_dic_writer.io.status.bits.sie, cmd_router.io.dmem_status_out.bits.status.sie
connect l2_huf_dic_writer.io.status.bits.hie, cmd_router.io.dmem_status_out.bits.status.hie
connect l2_huf_dic_writer.io.status.bits.mie, cmd_router.io.dmem_status_out.bits.status.mie
connect l2_huf_dic_writer.io.status.bits.upie, cmd_router.io.dmem_status_out.bits.status.upie
connect l2_huf_dic_writer.io.status.bits.spie, cmd_router.io.dmem_status_out.bits.status.spie
connect l2_huf_dic_writer.io.status.bits.ube, cmd_router.io.dmem_status_out.bits.status.ube
connect l2_huf_dic_writer.io.status.bits.mpie, cmd_router.io.dmem_status_out.bits.status.mpie
connect l2_huf_dic_writer.io.status.bits.spp, cmd_router.io.dmem_status_out.bits.status.spp
connect l2_huf_dic_writer.io.status.bits.vs, cmd_router.io.dmem_status_out.bits.status.vs
connect l2_huf_dic_writer.io.status.bits.mpp, cmd_router.io.dmem_status_out.bits.status.mpp
connect l2_huf_dic_writer.io.status.bits.fs, cmd_router.io.dmem_status_out.bits.status.fs
connect l2_huf_dic_writer.io.status.bits.xs, cmd_router.io.dmem_status_out.bits.status.xs
connect l2_huf_dic_writer.io.status.bits.mprv, cmd_router.io.dmem_status_out.bits.status.mprv
connect l2_huf_dic_writer.io.status.bits.sum, cmd_router.io.dmem_status_out.bits.status.sum
connect l2_huf_dic_writer.io.status.bits.mxr, cmd_router.io.dmem_status_out.bits.status.mxr
connect l2_huf_dic_writer.io.status.bits.tvm, cmd_router.io.dmem_status_out.bits.status.tvm
connect l2_huf_dic_writer.io.status.bits.tw, cmd_router.io.dmem_status_out.bits.status.tw
connect l2_huf_dic_writer.io.status.bits.tsr, cmd_router.io.dmem_status_out.bits.status.tsr
connect l2_huf_dic_writer.io.status.bits.zero1, cmd_router.io.dmem_status_out.bits.status.zero1
connect l2_huf_dic_writer.io.status.bits.sd_rv32, cmd_router.io.dmem_status_out.bits.status.sd_rv32
connect l2_huf_dic_writer.io.status.bits.uxl, cmd_router.io.dmem_status_out.bits.status.uxl
connect l2_huf_dic_writer.io.status.bits.sxl, cmd_router.io.dmem_status_out.bits.status.sxl
connect l2_huf_dic_writer.io.status.bits.sbe, cmd_router.io.dmem_status_out.bits.status.sbe
connect l2_huf_dic_writer.io.status.bits.mbe, cmd_router.io.dmem_status_out.bits.status.mbe
connect l2_huf_dic_writer.io.status.bits.gva, cmd_router.io.dmem_status_out.bits.status.gva
connect l2_huf_dic_writer.io.status.bits.mpv, cmd_router.io.dmem_status_out.bits.status.mpv
connect l2_huf_dic_writer.io.status.bits.zero2, cmd_router.io.dmem_status_out.bits.status.zero2
connect l2_huf_dic_writer.io.status.bits.sd, cmd_router.io.dmem_status_out.bits.status.sd
connect l2_huf_dic_writer.io.status.bits.v, cmd_router.io.dmem_status_out.bits.status.v
connect l2_huf_dic_writer.io.status.bits.prv, cmd_router.io.dmem_status_out.bits.status.prv
connect l2_huf_dic_writer.io.status.bits.dv, cmd_router.io.dmem_status_out.bits.status.dv
connect l2_huf_dic_writer.io.status.bits.dprv, cmd_router.io.dmem_status_out.bits.status.dprv
connect l2_huf_dic_writer.io.status.bits.isa, cmd_router.io.dmem_status_out.bits.status.isa
connect l2_huf_dic_writer.io.status.bits.wfi, cmd_router.io.dmem_status_out.bits.status.wfi
connect l2_huf_dic_writer.io.status.bits.cease, cmd_router.io.dmem_status_out.bits.status.cease
connect l2_huf_dic_writer.io.status.bits.debug, cmd_router.io.dmem_status_out.bits.status.debug
connect l2_huf_dic_writer.io.ptw.customCSRs, io.ptw[7].customCSRs
connect l2_huf_dic_writer.io.ptw.pmp[0], io.ptw[7].pmp[0]
connect l2_huf_dic_writer.io.ptw.pmp[1], io.ptw[7].pmp[1]
connect l2_huf_dic_writer.io.ptw.pmp[2], io.ptw[7].pmp[2]
connect l2_huf_dic_writer.io.ptw.pmp[3], io.ptw[7].pmp[3]
connect l2_huf_dic_writer.io.ptw.pmp[4], io.ptw[7].pmp[4]
connect l2_huf_dic_writer.io.ptw.pmp[5], io.ptw[7].pmp[5]
connect l2_huf_dic_writer.io.ptw.pmp[6], io.ptw[7].pmp[6]
connect l2_huf_dic_writer.io.ptw.pmp[7], io.ptw[7].pmp[7]
connect l2_huf_dic_writer.io.ptw.gstatus, io.ptw[7].gstatus
connect l2_huf_dic_writer.io.ptw.hstatus, io.ptw[7].hstatus
connect l2_huf_dic_writer.io.ptw.status, io.ptw[7].status
connect l2_huf_dic_writer.io.ptw.vsatp, io.ptw[7].vsatp
connect l2_huf_dic_writer.io.ptw.hgatp, io.ptw[7].hgatp
connect l2_huf_dic_writer.io.ptw.ptbr, io.ptw[7].ptbr
connect l2_huf_dic_writer.io.ptw.resp, io.ptw[7].resp
connect io.ptw[7].req.bits, l2_huf_dic_writer.io.ptw.req.bits
connect io.ptw[7].req.valid, l2_huf_dic_writer.io.ptw.req.valid
connect l2_huf_dic_writer.io.ptw.req.ready, io.ptw[7].req.ready
connect l2_huf_hdr_writer.io.sfence, cmd_router.io.sfence_out
connect l2_huf_hdr_writer.io.status.valid, cmd_router.io.dmem_status_out.valid
connect l2_huf_hdr_writer.io.status.bits.uie, cmd_router.io.dmem_status_out.bits.status.uie
connect l2_huf_hdr_writer.io.status.bits.sie, cmd_router.io.dmem_status_out.bits.status.sie
connect l2_huf_hdr_writer.io.status.bits.hie, cmd_router.io.dmem_status_out.bits.status.hie
connect l2_huf_hdr_writer.io.status.bits.mie, cmd_router.io.dmem_status_out.bits.status.mie
connect l2_huf_hdr_writer.io.status.bits.upie, cmd_router.io.dmem_status_out.bits.status.upie
connect l2_huf_hdr_writer.io.status.bits.spie, cmd_router.io.dmem_status_out.bits.status.spie
connect l2_huf_hdr_writer.io.status.bits.ube, cmd_router.io.dmem_status_out.bits.status.ube
connect l2_huf_hdr_writer.io.status.bits.mpie, cmd_router.io.dmem_status_out.bits.status.mpie
connect l2_huf_hdr_writer.io.status.bits.spp, cmd_router.io.dmem_status_out.bits.status.spp
connect l2_huf_hdr_writer.io.status.bits.vs, cmd_router.io.dmem_status_out.bits.status.vs
connect l2_huf_hdr_writer.io.status.bits.mpp, cmd_router.io.dmem_status_out.bits.status.mpp
connect l2_huf_hdr_writer.io.status.bits.fs, cmd_router.io.dmem_status_out.bits.status.fs
connect l2_huf_hdr_writer.io.status.bits.xs, cmd_router.io.dmem_status_out.bits.status.xs
connect l2_huf_hdr_writer.io.status.bits.mprv, cmd_router.io.dmem_status_out.bits.status.mprv
connect l2_huf_hdr_writer.io.status.bits.sum, cmd_router.io.dmem_status_out.bits.status.sum
connect l2_huf_hdr_writer.io.status.bits.mxr, cmd_router.io.dmem_status_out.bits.status.mxr
connect l2_huf_hdr_writer.io.status.bits.tvm, cmd_router.io.dmem_status_out.bits.status.tvm
connect l2_huf_hdr_writer.io.status.bits.tw, cmd_router.io.dmem_status_out.bits.status.tw
connect l2_huf_hdr_writer.io.status.bits.tsr, cmd_router.io.dmem_status_out.bits.status.tsr
connect l2_huf_hdr_writer.io.status.bits.zero1, cmd_router.io.dmem_status_out.bits.status.zero1
connect l2_huf_hdr_writer.io.status.bits.sd_rv32, cmd_router.io.dmem_status_out.bits.status.sd_rv32
connect l2_huf_hdr_writer.io.status.bits.uxl, cmd_router.io.dmem_status_out.bits.status.uxl
connect l2_huf_hdr_writer.io.status.bits.sxl, cmd_router.io.dmem_status_out.bits.status.sxl
connect l2_huf_hdr_writer.io.status.bits.sbe, cmd_router.io.dmem_status_out.bits.status.sbe
connect l2_huf_hdr_writer.io.status.bits.mbe, cmd_router.io.dmem_status_out.bits.status.mbe
connect l2_huf_hdr_writer.io.status.bits.gva, cmd_router.io.dmem_status_out.bits.status.gva
connect l2_huf_hdr_writer.io.status.bits.mpv, cmd_router.io.dmem_status_out.bits.status.mpv
connect l2_huf_hdr_writer.io.status.bits.zero2, cmd_router.io.dmem_status_out.bits.status.zero2
connect l2_huf_hdr_writer.io.status.bits.sd, cmd_router.io.dmem_status_out.bits.status.sd
connect l2_huf_hdr_writer.io.status.bits.v, cmd_router.io.dmem_status_out.bits.status.v
connect l2_huf_hdr_writer.io.status.bits.prv, cmd_router.io.dmem_status_out.bits.status.prv
connect l2_huf_hdr_writer.io.status.bits.dv, cmd_router.io.dmem_status_out.bits.status.dv
connect l2_huf_hdr_writer.io.status.bits.dprv, cmd_router.io.dmem_status_out.bits.status.dprv
connect l2_huf_hdr_writer.io.status.bits.isa, cmd_router.io.dmem_status_out.bits.status.isa
connect l2_huf_hdr_writer.io.status.bits.wfi, cmd_router.io.dmem_status_out.bits.status.wfi
connect l2_huf_hdr_writer.io.status.bits.cease, cmd_router.io.dmem_status_out.bits.status.cease
connect l2_huf_hdr_writer.io.status.bits.debug, cmd_router.io.dmem_status_out.bits.status.debug
connect l2_huf_hdr_writer.io.ptw.customCSRs, io.ptw[8].customCSRs
connect l2_huf_hdr_writer.io.ptw.pmp[0], io.ptw[8].pmp[0]
connect l2_huf_hdr_writer.io.ptw.pmp[1], io.ptw[8].pmp[1]
connect l2_huf_hdr_writer.io.ptw.pmp[2], io.ptw[8].pmp[2]
connect l2_huf_hdr_writer.io.ptw.pmp[3], io.ptw[8].pmp[3]
connect l2_huf_hdr_writer.io.ptw.pmp[4], io.ptw[8].pmp[4]
connect l2_huf_hdr_writer.io.ptw.pmp[5], io.ptw[8].pmp[5]
connect l2_huf_hdr_writer.io.ptw.pmp[6], io.ptw[8].pmp[6]
connect l2_huf_hdr_writer.io.ptw.pmp[7], io.ptw[8].pmp[7]
connect l2_huf_hdr_writer.io.ptw.gstatus, io.ptw[8].gstatus
connect l2_huf_hdr_writer.io.ptw.hstatus, io.ptw[8].hstatus
connect l2_huf_hdr_writer.io.ptw.status, io.ptw[8].status
connect l2_huf_hdr_writer.io.ptw.vsatp, io.ptw[8].vsatp
connect l2_huf_hdr_writer.io.ptw.hgatp, io.ptw[8].hgatp
connect l2_huf_hdr_writer.io.ptw.ptbr, io.ptw[8].ptbr
connect l2_huf_hdr_writer.io.ptw.resp, io.ptw[8].resp
connect io.ptw[8].req.bits, l2_huf_hdr_writer.io.ptw.req.bits
connect io.ptw[8].req.valid, l2_huf_hdr_writer.io.ptw.req.valid
connect l2_huf_hdr_writer.io.ptw.req.ready, io.ptw[8].req.ready
connect l2_huf_jt_writer.io.sfence, cmd_router.io.sfence_out
connect l2_huf_jt_writer.io.status.valid, cmd_router.io.dmem_status_out.valid
connect l2_huf_jt_writer.io.status.bits.uie, cmd_router.io.dmem_status_out.bits.status.uie
connect l2_huf_jt_writer.io.status.bits.sie, cmd_router.io.dmem_status_out.bits.status.sie
connect l2_huf_jt_writer.io.status.bits.hie, cmd_router.io.dmem_status_out.bits.status.hie
connect l2_huf_jt_writer.io.status.bits.mie, cmd_router.io.dmem_status_out.bits.status.mie
connect l2_huf_jt_writer.io.status.bits.upie, cmd_router.io.dmem_status_out.bits.status.upie
connect l2_huf_jt_writer.io.status.bits.spie, cmd_router.io.dmem_status_out.bits.status.spie
connect l2_huf_jt_writer.io.status.bits.ube, cmd_router.io.dmem_status_out.bits.status.ube
connect l2_huf_jt_writer.io.status.bits.mpie, cmd_router.io.dmem_status_out.bits.status.mpie
connect l2_huf_jt_writer.io.status.bits.spp, cmd_router.io.dmem_status_out.bits.status.spp
connect l2_huf_jt_writer.io.status.bits.vs, cmd_router.io.dmem_status_out.bits.status.vs
connect l2_huf_jt_writer.io.status.bits.mpp, cmd_router.io.dmem_status_out.bits.status.mpp
connect l2_huf_jt_writer.io.status.bits.fs, cmd_router.io.dmem_status_out.bits.status.fs
connect l2_huf_jt_writer.io.status.bits.xs, cmd_router.io.dmem_status_out.bits.status.xs
connect l2_huf_jt_writer.io.status.bits.mprv, cmd_router.io.dmem_status_out.bits.status.mprv
connect l2_huf_jt_writer.io.status.bits.sum, cmd_router.io.dmem_status_out.bits.status.sum
connect l2_huf_jt_writer.io.status.bits.mxr, cmd_router.io.dmem_status_out.bits.status.mxr
connect l2_huf_jt_writer.io.status.bits.tvm, cmd_router.io.dmem_status_out.bits.status.tvm
connect l2_huf_jt_writer.io.status.bits.tw, cmd_router.io.dmem_status_out.bits.status.tw
connect l2_huf_jt_writer.io.status.bits.tsr, cmd_router.io.dmem_status_out.bits.status.tsr
connect l2_huf_jt_writer.io.status.bits.zero1, cmd_router.io.dmem_status_out.bits.status.zero1
connect l2_huf_jt_writer.io.status.bits.sd_rv32, cmd_router.io.dmem_status_out.bits.status.sd_rv32
connect l2_huf_jt_writer.io.status.bits.uxl, cmd_router.io.dmem_status_out.bits.status.uxl
connect l2_huf_jt_writer.io.status.bits.sxl, cmd_router.io.dmem_status_out.bits.status.sxl
connect l2_huf_jt_writer.io.status.bits.sbe, cmd_router.io.dmem_status_out.bits.status.sbe
connect l2_huf_jt_writer.io.status.bits.mbe, cmd_router.io.dmem_status_out.bits.status.mbe
connect l2_huf_jt_writer.io.status.bits.gva, cmd_router.io.dmem_status_out.bits.status.gva
connect l2_huf_jt_writer.io.status.bits.mpv, cmd_router.io.dmem_status_out.bits.status.mpv
connect l2_huf_jt_writer.io.status.bits.zero2, cmd_router.io.dmem_status_out.bits.status.zero2
connect l2_huf_jt_writer.io.status.bits.sd, cmd_router.io.dmem_status_out.bits.status.sd
connect l2_huf_jt_writer.io.status.bits.v, cmd_router.io.dmem_status_out.bits.status.v
connect l2_huf_jt_writer.io.status.bits.prv, cmd_router.io.dmem_status_out.bits.status.prv
connect l2_huf_jt_writer.io.status.bits.dv, cmd_router.io.dmem_status_out.bits.status.dv
connect l2_huf_jt_writer.io.status.bits.dprv, cmd_router.io.dmem_status_out.bits.status.dprv
connect l2_huf_jt_writer.io.status.bits.isa, cmd_router.io.dmem_status_out.bits.status.isa
connect l2_huf_jt_writer.io.status.bits.wfi, cmd_router.io.dmem_status_out.bits.status.wfi
connect l2_huf_jt_writer.io.status.bits.cease, cmd_router.io.dmem_status_out.bits.status.cease
connect l2_huf_jt_writer.io.status.bits.debug, cmd_router.io.dmem_status_out.bits.status.debug
connect l2_huf_jt_writer.io.ptw.customCSRs, io.ptw[9].customCSRs
connect l2_huf_jt_writer.io.ptw.pmp[0], io.ptw[9].pmp[0]
connect l2_huf_jt_writer.io.ptw.pmp[1], io.ptw[9].pmp[1]
connect l2_huf_jt_writer.io.ptw.pmp[2], io.ptw[9].pmp[2]
connect l2_huf_jt_writer.io.ptw.pmp[3], io.ptw[9].pmp[3]
connect l2_huf_jt_writer.io.ptw.pmp[4], io.ptw[9].pmp[4]
connect l2_huf_jt_writer.io.ptw.pmp[5], io.ptw[9].pmp[5]
connect l2_huf_jt_writer.io.ptw.pmp[6], io.ptw[9].pmp[6]
connect l2_huf_jt_writer.io.ptw.pmp[7], io.ptw[9].pmp[7]
connect l2_huf_jt_writer.io.ptw.gstatus, io.ptw[9].gstatus
connect l2_huf_jt_writer.io.ptw.hstatus, io.ptw[9].hstatus
connect l2_huf_jt_writer.io.ptw.status, io.ptw[9].status
connect l2_huf_jt_writer.io.ptw.vsatp, io.ptw[9].vsatp
connect l2_huf_jt_writer.io.ptw.hgatp, io.ptw[9].hgatp
connect l2_huf_jt_writer.io.ptw.ptbr, io.ptw[9].ptbr
connect l2_huf_jt_writer.io.ptw.resp, io.ptw[9].resp
connect io.ptw[9].req.bits, l2_huf_jt_writer.io.ptw.req.bits
connect io.ptw[9].req.valid, l2_huf_jt_writer.io.ptw.req.valid
connect l2_huf_jt_writer.io.ptw.req.ready, io.ptw[9].req.ready
connect l2_huf_lit_writer.io.sfence, cmd_router.io.sfence_out
connect l2_huf_lit_writer.io.status.valid, cmd_router.io.dmem_status_out.valid
connect l2_huf_lit_writer.io.status.bits.uie, cmd_router.io.dmem_status_out.bits.status.uie
connect l2_huf_lit_writer.io.status.bits.sie, cmd_router.io.dmem_status_out.bits.status.sie
connect l2_huf_lit_writer.io.status.bits.hie, cmd_router.io.dmem_status_out.bits.status.hie
connect l2_huf_lit_writer.io.status.bits.mie, cmd_router.io.dmem_status_out.bits.status.mie
connect l2_huf_lit_writer.io.status.bits.upie, cmd_router.io.dmem_status_out.bits.status.upie
connect l2_huf_lit_writer.io.status.bits.spie, cmd_router.io.dmem_status_out.bits.status.spie
connect l2_huf_lit_writer.io.status.bits.ube, cmd_router.io.dmem_status_out.bits.status.ube
connect l2_huf_lit_writer.io.status.bits.mpie, cmd_router.io.dmem_status_out.bits.status.mpie
connect l2_huf_lit_writer.io.status.bits.spp, cmd_router.io.dmem_status_out.bits.status.spp
connect l2_huf_lit_writer.io.status.bits.vs, cmd_router.io.dmem_status_out.bits.status.vs
connect l2_huf_lit_writer.io.status.bits.mpp, cmd_router.io.dmem_status_out.bits.status.mpp
connect l2_huf_lit_writer.io.status.bits.fs, cmd_router.io.dmem_status_out.bits.status.fs
connect l2_huf_lit_writer.io.status.bits.xs, cmd_router.io.dmem_status_out.bits.status.xs
connect l2_huf_lit_writer.io.status.bits.mprv, cmd_router.io.dmem_status_out.bits.status.mprv
connect l2_huf_lit_writer.io.status.bits.sum, cmd_router.io.dmem_status_out.bits.status.sum
connect l2_huf_lit_writer.io.status.bits.mxr, cmd_router.io.dmem_status_out.bits.status.mxr
connect l2_huf_lit_writer.io.status.bits.tvm, cmd_router.io.dmem_status_out.bits.status.tvm
connect l2_huf_lit_writer.io.status.bits.tw, cmd_router.io.dmem_status_out.bits.status.tw
connect l2_huf_lit_writer.io.status.bits.tsr, cmd_router.io.dmem_status_out.bits.status.tsr
connect l2_huf_lit_writer.io.status.bits.zero1, cmd_router.io.dmem_status_out.bits.status.zero1
connect l2_huf_lit_writer.io.status.bits.sd_rv32, cmd_router.io.dmem_status_out.bits.status.sd_rv32
connect l2_huf_lit_writer.io.status.bits.uxl, cmd_router.io.dmem_status_out.bits.status.uxl
connect l2_huf_lit_writer.io.status.bits.sxl, cmd_router.io.dmem_status_out.bits.status.sxl
connect l2_huf_lit_writer.io.status.bits.sbe, cmd_router.io.dmem_status_out.bits.status.sbe
connect l2_huf_lit_writer.io.status.bits.mbe, cmd_router.io.dmem_status_out.bits.status.mbe
connect l2_huf_lit_writer.io.status.bits.gva, cmd_router.io.dmem_status_out.bits.status.gva
connect l2_huf_lit_writer.io.status.bits.mpv, cmd_router.io.dmem_status_out.bits.status.mpv
connect l2_huf_lit_writer.io.status.bits.zero2, cmd_router.io.dmem_status_out.bits.status.zero2
connect l2_huf_lit_writer.io.status.bits.sd, cmd_router.io.dmem_status_out.bits.status.sd
connect l2_huf_lit_writer.io.status.bits.v, cmd_router.io.dmem_status_out.bits.status.v
connect l2_huf_lit_writer.io.status.bits.prv, cmd_router.io.dmem_status_out.bits.status.prv
connect l2_huf_lit_writer.io.status.bits.dv, cmd_router.io.dmem_status_out.bits.status.dv
connect l2_huf_lit_writer.io.status.bits.dprv, cmd_router.io.dmem_status_out.bits.status.dprv
connect l2_huf_lit_writer.io.status.bits.isa, cmd_router.io.dmem_status_out.bits.status.isa
connect l2_huf_lit_writer.io.status.bits.wfi, cmd_router.io.dmem_status_out.bits.status.wfi
connect l2_huf_lit_writer.io.status.bits.cease, cmd_router.io.dmem_status_out.bits.status.cease
connect l2_huf_lit_writer.io.status.bits.debug, cmd_router.io.dmem_status_out.bits.status.debug
connect l2_huf_lit_writer.io.ptw.customCSRs, io.ptw[10].customCSRs
connect l2_huf_lit_writer.io.ptw.pmp[0], io.ptw[10].pmp[0]
connect l2_huf_lit_writer.io.ptw.pmp[1], io.ptw[10].pmp[1]
connect l2_huf_lit_writer.io.ptw.pmp[2], io.ptw[10].pmp[2]
connect l2_huf_lit_writer.io.ptw.pmp[3], io.ptw[10].pmp[3]
connect l2_huf_lit_writer.io.ptw.pmp[4], io.ptw[10].pmp[4]
connect l2_huf_lit_writer.io.ptw.pmp[5], io.ptw[10].pmp[5]
connect l2_huf_lit_writer.io.ptw.pmp[6], io.ptw[10].pmp[6]
connect l2_huf_lit_writer.io.ptw.pmp[7], io.ptw[10].pmp[7]
connect l2_huf_lit_writer.io.ptw.gstatus, io.ptw[10].gstatus
connect l2_huf_lit_writer.io.ptw.hstatus, io.ptw[10].hstatus
connect l2_huf_lit_writer.io.ptw.status, io.ptw[10].status
connect l2_huf_lit_writer.io.ptw.vsatp, io.ptw[10].vsatp
connect l2_huf_lit_writer.io.ptw.hgatp, io.ptw[10].hgatp
connect l2_huf_lit_writer.io.ptw.ptbr, io.ptw[10].ptbr
connect l2_huf_lit_writer.io.ptw.resp, io.ptw[10].resp
connect io.ptw[10].req.bits, l2_huf_lit_writer.io.ptw.req.bits
connect io.ptw[10].req.valid, l2_huf_lit_writer.io.ptw.req.valid
connect l2_huf_lit_writer.io.ptw.req.ready, io.ptw[10].req.ready
connect l2_seq_reader.io.sfence, cmd_router.io.sfence_out
connect l2_seq_reader.io.status.valid, cmd_router.io.dmem_status_out.valid
connect l2_seq_reader.io.status.bits.uie, cmd_router.io.dmem_status_out.bits.status.uie
connect l2_seq_reader.io.status.bits.sie, cmd_router.io.dmem_status_out.bits.status.sie
connect l2_seq_reader.io.status.bits.hie, cmd_router.io.dmem_status_out.bits.status.hie
connect l2_seq_reader.io.status.bits.mie, cmd_router.io.dmem_status_out.bits.status.mie
connect l2_seq_reader.io.status.bits.upie, cmd_router.io.dmem_status_out.bits.status.upie
connect l2_seq_reader.io.status.bits.spie, cmd_router.io.dmem_status_out.bits.status.spie
connect l2_seq_reader.io.status.bits.ube, cmd_router.io.dmem_status_out.bits.status.ube
connect l2_seq_reader.io.status.bits.mpie, cmd_router.io.dmem_status_out.bits.status.mpie
connect l2_seq_reader.io.status.bits.spp, cmd_router.io.dmem_status_out.bits.status.spp
connect l2_seq_reader.io.status.bits.vs, cmd_router.io.dmem_status_out.bits.status.vs
connect l2_seq_reader.io.status.bits.mpp, cmd_router.io.dmem_status_out.bits.status.mpp
connect l2_seq_reader.io.status.bits.fs, cmd_router.io.dmem_status_out.bits.status.fs
connect l2_seq_reader.io.status.bits.xs, cmd_router.io.dmem_status_out.bits.status.xs
connect l2_seq_reader.io.status.bits.mprv, cmd_router.io.dmem_status_out.bits.status.mprv
connect l2_seq_reader.io.status.bits.sum, cmd_router.io.dmem_status_out.bits.status.sum
connect l2_seq_reader.io.status.bits.mxr, cmd_router.io.dmem_status_out.bits.status.mxr
connect l2_seq_reader.io.status.bits.tvm, cmd_router.io.dmem_status_out.bits.status.tvm
connect l2_seq_reader.io.status.bits.tw, cmd_router.io.dmem_status_out.bits.status.tw
connect l2_seq_reader.io.status.bits.tsr, cmd_router.io.dmem_status_out.bits.status.tsr
connect l2_seq_reader.io.status.bits.zero1, cmd_router.io.dmem_status_out.bits.status.zero1
connect l2_seq_reader.io.status.bits.sd_rv32, cmd_router.io.dmem_status_out.bits.status.sd_rv32
connect l2_seq_reader.io.status.bits.uxl, cmd_router.io.dmem_status_out.bits.status.uxl
connect l2_seq_reader.io.status.bits.sxl, cmd_router.io.dmem_status_out.bits.status.sxl
connect l2_seq_reader.io.status.bits.sbe, cmd_router.io.dmem_status_out.bits.status.sbe
connect l2_seq_reader.io.status.bits.mbe, cmd_router.io.dmem_status_out.bits.status.mbe
connect l2_seq_reader.io.status.bits.gva, cmd_router.io.dmem_status_out.bits.status.gva
connect l2_seq_reader.io.status.bits.mpv, cmd_router.io.dmem_status_out.bits.status.mpv
connect l2_seq_reader.io.status.bits.zero2, cmd_router.io.dmem_status_out.bits.status.zero2
connect l2_seq_reader.io.status.bits.sd, cmd_router.io.dmem_status_out.bits.status.sd
connect l2_seq_reader.io.status.bits.v, cmd_router.io.dmem_status_out.bits.status.v
connect l2_seq_reader.io.status.bits.prv, cmd_router.io.dmem_status_out.bits.status.prv
connect l2_seq_reader.io.status.bits.dv, cmd_router.io.dmem_status_out.bits.status.dv
connect l2_seq_reader.io.status.bits.dprv, cmd_router.io.dmem_status_out.bits.status.dprv
connect l2_seq_reader.io.status.bits.isa, cmd_router.io.dmem_status_out.bits.status.isa
connect l2_seq_reader.io.status.bits.wfi, cmd_router.io.dmem_status_out.bits.status.wfi
connect l2_seq_reader.io.status.bits.cease, cmd_router.io.dmem_status_out.bits.status.cease
connect l2_seq_reader.io.status.bits.debug, cmd_router.io.dmem_status_out.bits.status.debug
connect l2_seq_reader.io.ptw.customCSRs, io.ptw[11].customCSRs
connect l2_seq_reader.io.ptw.pmp[0], io.ptw[11].pmp[0]
connect l2_seq_reader.io.ptw.pmp[1], io.ptw[11].pmp[1]
connect l2_seq_reader.io.ptw.pmp[2], io.ptw[11].pmp[2]
connect l2_seq_reader.io.ptw.pmp[3], io.ptw[11].pmp[3]
connect l2_seq_reader.io.ptw.pmp[4], io.ptw[11].pmp[4]
connect l2_seq_reader.io.ptw.pmp[5], io.ptw[11].pmp[5]
connect l2_seq_reader.io.ptw.pmp[6], io.ptw[11].pmp[6]
connect l2_seq_reader.io.ptw.pmp[7], io.ptw[11].pmp[7]
connect l2_seq_reader.io.ptw.gstatus, io.ptw[11].gstatus
connect l2_seq_reader.io.ptw.hstatus, io.ptw[11].hstatus
connect l2_seq_reader.io.ptw.status, io.ptw[11].status
connect l2_seq_reader.io.ptw.vsatp, io.ptw[11].vsatp
connect l2_seq_reader.io.ptw.hgatp, io.ptw[11].hgatp
connect l2_seq_reader.io.ptw.ptbr, io.ptw[11].ptbr
connect l2_seq_reader.io.ptw.resp, io.ptw[11].resp
connect io.ptw[11].req.bits, l2_seq_reader.io.ptw.req.bits
connect io.ptw[11].req.valid, l2_seq_reader.io.ptw.req.valid
connect l2_seq_reader.io.ptw.req.ready, io.ptw[11].req.ready
connect l2_seq_reader2.io.sfence, cmd_router.io.sfence_out
connect l2_seq_reader2.io.status.valid, cmd_router.io.dmem_status_out.valid
connect l2_seq_reader2.io.status.bits.uie, cmd_router.io.dmem_status_out.bits.status.uie
connect l2_seq_reader2.io.status.bits.sie, cmd_router.io.dmem_status_out.bits.status.sie
connect l2_seq_reader2.io.status.bits.hie, cmd_router.io.dmem_status_out.bits.status.hie
connect l2_seq_reader2.io.status.bits.mie, cmd_router.io.dmem_status_out.bits.status.mie
connect l2_seq_reader2.io.status.bits.upie, cmd_router.io.dmem_status_out.bits.status.upie
connect l2_seq_reader2.io.status.bits.spie, cmd_router.io.dmem_status_out.bits.status.spie
connect l2_seq_reader2.io.status.bits.ube, cmd_router.io.dmem_status_out.bits.status.ube
connect l2_seq_reader2.io.status.bits.mpie, cmd_router.io.dmem_status_out.bits.status.mpie
connect l2_seq_reader2.io.status.bits.spp, cmd_router.io.dmem_status_out.bits.status.spp
connect l2_seq_reader2.io.status.bits.vs, cmd_router.io.dmem_status_out.bits.status.vs
connect l2_seq_reader2.io.status.bits.mpp, cmd_router.io.dmem_status_out.bits.status.mpp
connect l2_seq_reader2.io.status.bits.fs, cmd_router.io.dmem_status_out.bits.status.fs
connect l2_seq_reader2.io.status.bits.xs, cmd_router.io.dmem_status_out.bits.status.xs
connect l2_seq_reader2.io.status.bits.mprv, cmd_router.io.dmem_status_out.bits.status.mprv
connect l2_seq_reader2.io.status.bits.sum, cmd_router.io.dmem_status_out.bits.status.sum
connect l2_seq_reader2.io.status.bits.mxr, cmd_router.io.dmem_status_out.bits.status.mxr
connect l2_seq_reader2.io.status.bits.tvm, cmd_router.io.dmem_status_out.bits.status.tvm
connect l2_seq_reader2.io.status.bits.tw, cmd_router.io.dmem_status_out.bits.status.tw
connect l2_seq_reader2.io.status.bits.tsr, cmd_router.io.dmem_status_out.bits.status.tsr
connect l2_seq_reader2.io.status.bits.zero1, cmd_router.io.dmem_status_out.bits.status.zero1
connect l2_seq_reader2.io.status.bits.sd_rv32, cmd_router.io.dmem_status_out.bits.status.sd_rv32
connect l2_seq_reader2.io.status.bits.uxl, cmd_router.io.dmem_status_out.bits.status.uxl
connect l2_seq_reader2.io.status.bits.sxl, cmd_router.io.dmem_status_out.bits.status.sxl
connect l2_seq_reader2.io.status.bits.sbe, cmd_router.io.dmem_status_out.bits.status.sbe
connect l2_seq_reader2.io.status.bits.mbe, cmd_router.io.dmem_status_out.bits.status.mbe
connect l2_seq_reader2.io.status.bits.gva, cmd_router.io.dmem_status_out.bits.status.gva
connect l2_seq_reader2.io.status.bits.mpv, cmd_router.io.dmem_status_out.bits.status.mpv
connect l2_seq_reader2.io.status.bits.zero2, cmd_router.io.dmem_status_out.bits.status.zero2
connect l2_seq_reader2.io.status.bits.sd, cmd_router.io.dmem_status_out.bits.status.sd
connect l2_seq_reader2.io.status.bits.v, cmd_router.io.dmem_status_out.bits.status.v
connect l2_seq_reader2.io.status.bits.prv, cmd_router.io.dmem_status_out.bits.status.prv
connect l2_seq_reader2.io.status.bits.dv, cmd_router.io.dmem_status_out.bits.status.dv
connect l2_seq_reader2.io.status.bits.dprv, cmd_router.io.dmem_status_out.bits.status.dprv
connect l2_seq_reader2.io.status.bits.isa, cmd_router.io.dmem_status_out.bits.status.isa
connect l2_seq_reader2.io.status.bits.wfi, cmd_router.io.dmem_status_out.bits.status.wfi
connect l2_seq_reader2.io.status.bits.cease, cmd_router.io.dmem_status_out.bits.status.cease
connect l2_seq_reader2.io.status.bits.debug, cmd_router.io.dmem_status_out.bits.status.debug
connect l2_seq_reader2.io.ptw.customCSRs, io.ptw[12].customCSRs
connect l2_seq_reader2.io.ptw.pmp[0], io.ptw[12].pmp[0]
connect l2_seq_reader2.io.ptw.pmp[1], io.ptw[12].pmp[1]
connect l2_seq_reader2.io.ptw.pmp[2], io.ptw[12].pmp[2]
connect l2_seq_reader2.io.ptw.pmp[3], io.ptw[12].pmp[3]
connect l2_seq_reader2.io.ptw.pmp[4], io.ptw[12].pmp[4]
connect l2_seq_reader2.io.ptw.pmp[5], io.ptw[12].pmp[5]
connect l2_seq_reader2.io.ptw.pmp[6], io.ptw[12].pmp[6]
connect l2_seq_reader2.io.ptw.pmp[7], io.ptw[12].pmp[7]
connect l2_seq_reader2.io.ptw.gstatus, io.ptw[12].gstatus
connect l2_seq_reader2.io.ptw.hstatus, io.ptw[12].hstatus
connect l2_seq_reader2.io.ptw.status, io.ptw[12].status
connect l2_seq_reader2.io.ptw.vsatp, io.ptw[12].vsatp
connect l2_seq_reader2.io.ptw.hgatp, io.ptw[12].hgatp
connect l2_seq_reader2.io.ptw.ptbr, io.ptw[12].ptbr
connect l2_seq_reader2.io.ptw.resp, io.ptw[12].resp
connect io.ptw[12].req.bits, l2_seq_reader2.io.ptw.req.bits
connect io.ptw[12].req.valid, l2_seq_reader2.io.ptw.req.valid
connect l2_seq_reader2.io.ptw.req.ready, io.ptw[12].req.ready
connect l2_seq_writer.io.sfence, cmd_router.io.sfence_out
connect l2_seq_writer.io.status.valid, cmd_router.io.dmem_status_out.valid
connect l2_seq_writer.io.status.bits.uie, cmd_router.io.dmem_status_out.bits.status.uie
connect l2_seq_writer.io.status.bits.sie, cmd_router.io.dmem_status_out.bits.status.sie
connect l2_seq_writer.io.status.bits.hie, cmd_router.io.dmem_status_out.bits.status.hie
connect l2_seq_writer.io.status.bits.mie, cmd_router.io.dmem_status_out.bits.status.mie
connect l2_seq_writer.io.status.bits.upie, cmd_router.io.dmem_status_out.bits.status.upie
connect l2_seq_writer.io.status.bits.spie, cmd_router.io.dmem_status_out.bits.status.spie
connect l2_seq_writer.io.status.bits.ube, cmd_router.io.dmem_status_out.bits.status.ube
connect l2_seq_writer.io.status.bits.mpie, cmd_router.io.dmem_status_out.bits.status.mpie
connect l2_seq_writer.io.status.bits.spp, cmd_router.io.dmem_status_out.bits.status.spp
connect l2_seq_writer.io.status.bits.vs, cmd_router.io.dmem_status_out.bits.status.vs
connect l2_seq_writer.io.status.bits.mpp, cmd_router.io.dmem_status_out.bits.status.mpp
connect l2_seq_writer.io.status.bits.fs, cmd_router.io.dmem_status_out.bits.status.fs
connect l2_seq_writer.io.status.bits.xs, cmd_router.io.dmem_status_out.bits.status.xs
connect l2_seq_writer.io.status.bits.mprv, cmd_router.io.dmem_status_out.bits.status.mprv
connect l2_seq_writer.io.status.bits.sum, cmd_router.io.dmem_status_out.bits.status.sum
connect l2_seq_writer.io.status.bits.mxr, cmd_router.io.dmem_status_out.bits.status.mxr
connect l2_seq_writer.io.status.bits.tvm, cmd_router.io.dmem_status_out.bits.status.tvm
connect l2_seq_writer.io.status.bits.tw, cmd_router.io.dmem_status_out.bits.status.tw
connect l2_seq_writer.io.status.bits.tsr, cmd_router.io.dmem_status_out.bits.status.tsr
connect l2_seq_writer.io.status.bits.zero1, cmd_router.io.dmem_status_out.bits.status.zero1
connect l2_seq_writer.io.status.bits.sd_rv32, cmd_router.io.dmem_status_out.bits.status.sd_rv32
connect l2_seq_writer.io.status.bits.uxl, cmd_router.io.dmem_status_out.bits.status.uxl
connect l2_seq_writer.io.status.bits.sxl, cmd_router.io.dmem_status_out.bits.status.sxl
connect l2_seq_writer.io.status.bits.sbe, cmd_router.io.dmem_status_out.bits.status.sbe
connect l2_seq_writer.io.status.bits.mbe, cmd_router.io.dmem_status_out.bits.status.mbe
connect l2_seq_writer.io.status.bits.gva, cmd_router.io.dmem_status_out.bits.status.gva
connect l2_seq_writer.io.status.bits.mpv, cmd_router.io.dmem_status_out.bits.status.mpv
connect l2_seq_writer.io.status.bits.zero2, cmd_router.io.dmem_status_out.bits.status.zero2
connect l2_seq_writer.io.status.bits.sd, cmd_router.io.dmem_status_out.bits.status.sd
connect l2_seq_writer.io.status.bits.v, cmd_router.io.dmem_status_out.bits.status.v
connect l2_seq_writer.io.status.bits.prv, cmd_router.io.dmem_status_out.bits.status.prv
connect l2_seq_writer.io.status.bits.dv, cmd_router.io.dmem_status_out.bits.status.dv
connect l2_seq_writer.io.status.bits.dprv, cmd_router.io.dmem_status_out.bits.status.dprv
connect l2_seq_writer.io.status.bits.isa, cmd_router.io.dmem_status_out.bits.status.isa
connect l2_seq_writer.io.status.bits.wfi, cmd_router.io.dmem_status_out.bits.status.wfi
connect l2_seq_writer.io.status.bits.cease, cmd_router.io.dmem_status_out.bits.status.cease
connect l2_seq_writer.io.status.bits.debug, cmd_router.io.dmem_status_out.bits.status.debug
connect l2_seq_writer.io.ptw.customCSRs, io.ptw[13].customCSRs
connect l2_seq_writer.io.ptw.pmp[0], io.ptw[13].pmp[0]
connect l2_seq_writer.io.ptw.pmp[1], io.ptw[13].pmp[1]
connect l2_seq_writer.io.ptw.pmp[2], io.ptw[13].pmp[2]
connect l2_seq_writer.io.ptw.pmp[3], io.ptw[13].pmp[3]
connect l2_seq_writer.io.ptw.pmp[4], io.ptw[13].pmp[4]
connect l2_seq_writer.io.ptw.pmp[5], io.ptw[13].pmp[5]
connect l2_seq_writer.io.ptw.pmp[6], io.ptw[13].pmp[6]
connect l2_seq_writer.io.ptw.pmp[7], io.ptw[13].pmp[7]
connect l2_seq_writer.io.ptw.gstatus, io.ptw[13].gstatus
connect l2_seq_writer.io.ptw.hstatus, io.ptw[13].hstatus
connect l2_seq_writer.io.ptw.status, io.ptw[13].status
connect l2_seq_writer.io.ptw.vsatp, io.ptw[13].vsatp
connect l2_seq_writer.io.ptw.hgatp, io.ptw[13].hgatp
connect l2_seq_writer.io.ptw.ptbr, io.ptw[13].ptbr
connect l2_seq_writer.io.ptw.resp, io.ptw[13].resp
connect io.ptw[13].req.bits, l2_seq_writer.io.ptw.req.bits
connect io.ptw[13].req.valid, l2_seq_writer.io.ptw.req.valid
connect l2_seq_writer.io.ptw.req.ready, io.ptw[13].req.ready
connect l2_raw_block_reader.io.sfence, cmd_router.io.sfence_out
connect l2_raw_block_reader.io.status.valid, cmd_router.io.dmem_status_out.valid
connect l2_raw_block_reader.io.status.bits.uie, cmd_router.io.dmem_status_out.bits.status.uie
connect l2_raw_block_reader.io.status.bits.sie, cmd_router.io.dmem_status_out.bits.status.sie
connect l2_raw_block_reader.io.status.bits.hie, cmd_router.io.dmem_status_out.bits.status.hie
connect l2_raw_block_reader.io.status.bits.mie, cmd_router.io.dmem_status_out.bits.status.mie
connect l2_raw_block_reader.io.status.bits.upie, cmd_router.io.dmem_status_out.bits.status.upie
connect l2_raw_block_reader.io.status.bits.spie, cmd_router.io.dmem_status_out.bits.status.spie
connect l2_raw_block_reader.io.status.bits.ube, cmd_router.io.dmem_status_out.bits.status.ube
connect l2_raw_block_reader.io.status.bits.mpie, cmd_router.io.dmem_status_out.bits.status.mpie
connect l2_raw_block_reader.io.status.bits.spp, cmd_router.io.dmem_status_out.bits.status.spp
connect l2_raw_block_reader.io.status.bits.vs, cmd_router.io.dmem_status_out.bits.status.vs
connect l2_raw_block_reader.io.status.bits.mpp, cmd_router.io.dmem_status_out.bits.status.mpp
connect l2_raw_block_reader.io.status.bits.fs, cmd_router.io.dmem_status_out.bits.status.fs
connect l2_raw_block_reader.io.status.bits.xs, cmd_router.io.dmem_status_out.bits.status.xs
connect l2_raw_block_reader.io.status.bits.mprv, cmd_router.io.dmem_status_out.bits.status.mprv
connect l2_raw_block_reader.io.status.bits.sum, cmd_router.io.dmem_status_out.bits.status.sum
connect l2_raw_block_reader.io.status.bits.mxr, cmd_router.io.dmem_status_out.bits.status.mxr
connect l2_raw_block_reader.io.status.bits.tvm, cmd_router.io.dmem_status_out.bits.status.tvm
connect l2_raw_block_reader.io.status.bits.tw, cmd_router.io.dmem_status_out.bits.status.tw
connect l2_raw_block_reader.io.status.bits.tsr, cmd_router.io.dmem_status_out.bits.status.tsr
connect l2_raw_block_reader.io.status.bits.zero1, cmd_router.io.dmem_status_out.bits.status.zero1
connect l2_raw_block_reader.io.status.bits.sd_rv32, cmd_router.io.dmem_status_out.bits.status.sd_rv32
connect l2_raw_block_reader.io.status.bits.uxl, cmd_router.io.dmem_status_out.bits.status.uxl
connect l2_raw_block_reader.io.status.bits.sxl, cmd_router.io.dmem_status_out.bits.status.sxl
connect l2_raw_block_reader.io.status.bits.sbe, cmd_router.io.dmem_status_out.bits.status.sbe
connect l2_raw_block_reader.io.status.bits.mbe, cmd_router.io.dmem_status_out.bits.status.mbe
connect l2_raw_block_reader.io.status.bits.gva, cmd_router.io.dmem_status_out.bits.status.gva
connect l2_raw_block_reader.io.status.bits.mpv, cmd_router.io.dmem_status_out.bits.status.mpv
connect l2_raw_block_reader.io.status.bits.zero2, cmd_router.io.dmem_status_out.bits.status.zero2
connect l2_raw_block_reader.io.status.bits.sd, cmd_router.io.dmem_status_out.bits.status.sd
connect l2_raw_block_reader.io.status.bits.v, cmd_router.io.dmem_status_out.bits.status.v
connect l2_raw_block_reader.io.status.bits.prv, cmd_router.io.dmem_status_out.bits.status.prv
connect l2_raw_block_reader.io.status.bits.dv, cmd_router.io.dmem_status_out.bits.status.dv
connect l2_raw_block_reader.io.status.bits.dprv, cmd_router.io.dmem_status_out.bits.status.dprv
connect l2_raw_block_reader.io.status.bits.isa, cmd_router.io.dmem_status_out.bits.status.isa
connect l2_raw_block_reader.io.status.bits.wfi, cmd_router.io.dmem_status_out.bits.status.wfi
connect l2_raw_block_reader.io.status.bits.cease, cmd_router.io.dmem_status_out.bits.status.cease
connect l2_raw_block_reader.io.status.bits.debug, cmd_router.io.dmem_status_out.bits.status.debug
connect l2_raw_block_reader.io.ptw.customCSRs, io.ptw[14].customCSRs
connect l2_raw_block_reader.io.ptw.pmp[0], io.ptw[14].pmp[0]
connect l2_raw_block_reader.io.ptw.pmp[1], io.ptw[14].pmp[1]
connect l2_raw_block_reader.io.ptw.pmp[2], io.ptw[14].pmp[2]
connect l2_raw_block_reader.io.ptw.pmp[3], io.ptw[14].pmp[3]
connect l2_raw_block_reader.io.ptw.pmp[4], io.ptw[14].pmp[4]
connect l2_raw_block_reader.io.ptw.pmp[5], io.ptw[14].pmp[5]
connect l2_raw_block_reader.io.ptw.pmp[6], io.ptw[14].pmp[6]
connect l2_raw_block_reader.io.ptw.pmp[7], io.ptw[14].pmp[7]
connect l2_raw_block_reader.io.ptw.gstatus, io.ptw[14].gstatus
connect l2_raw_block_reader.io.ptw.hstatus, io.ptw[14].hstatus
connect l2_raw_block_reader.io.ptw.status, io.ptw[14].status
connect l2_raw_block_reader.io.ptw.vsatp, io.ptw[14].vsatp
connect l2_raw_block_reader.io.ptw.hgatp, io.ptw[14].hgatp
connect l2_raw_block_reader.io.ptw.ptbr, io.ptw[14].ptbr
connect l2_raw_block_reader.io.ptw.resp, io.ptw[14].resp
connect io.ptw[14].req.bits, l2_raw_block_reader.io.ptw.req.bits
connect io.ptw[14].req.valid, l2_raw_block_reader.io.ptw.req.valid
connect l2_raw_block_reader.io.ptw.req.ready, io.ptw[14].req.ready
connect l2_raw_block_writer.io.sfence, cmd_router.io.sfence_out
connect l2_raw_block_writer.io.status.valid, cmd_router.io.dmem_status_out.valid
connect l2_raw_block_writer.io.status.bits.uie, cmd_router.io.dmem_status_out.bits.status.uie
connect l2_raw_block_writer.io.status.bits.sie, cmd_router.io.dmem_status_out.bits.status.sie
connect l2_raw_block_writer.io.status.bits.hie, cmd_router.io.dmem_status_out.bits.status.hie
connect l2_raw_block_writer.io.status.bits.mie, cmd_router.io.dmem_status_out.bits.status.mie
connect l2_raw_block_writer.io.status.bits.upie, cmd_router.io.dmem_status_out.bits.status.upie
connect l2_raw_block_writer.io.status.bits.spie, cmd_router.io.dmem_status_out.bits.status.spie
connect l2_raw_block_writer.io.status.bits.ube, cmd_router.io.dmem_status_out.bits.status.ube
connect l2_raw_block_writer.io.status.bits.mpie, cmd_router.io.dmem_status_out.bits.status.mpie
connect l2_raw_block_writer.io.status.bits.spp, cmd_router.io.dmem_status_out.bits.status.spp
connect l2_raw_block_writer.io.status.bits.vs, cmd_router.io.dmem_status_out.bits.status.vs
connect l2_raw_block_writer.io.status.bits.mpp, cmd_router.io.dmem_status_out.bits.status.mpp
connect l2_raw_block_writer.io.status.bits.fs, cmd_router.io.dmem_status_out.bits.status.fs
connect l2_raw_block_writer.io.status.bits.xs, cmd_router.io.dmem_status_out.bits.status.xs
connect l2_raw_block_writer.io.status.bits.mprv, cmd_router.io.dmem_status_out.bits.status.mprv
connect l2_raw_block_writer.io.status.bits.sum, cmd_router.io.dmem_status_out.bits.status.sum
connect l2_raw_block_writer.io.status.bits.mxr, cmd_router.io.dmem_status_out.bits.status.mxr
connect l2_raw_block_writer.io.status.bits.tvm, cmd_router.io.dmem_status_out.bits.status.tvm
connect l2_raw_block_writer.io.status.bits.tw, cmd_router.io.dmem_status_out.bits.status.tw
connect l2_raw_block_writer.io.status.bits.tsr, cmd_router.io.dmem_status_out.bits.status.tsr
connect l2_raw_block_writer.io.status.bits.zero1, cmd_router.io.dmem_status_out.bits.status.zero1
connect l2_raw_block_writer.io.status.bits.sd_rv32, cmd_router.io.dmem_status_out.bits.status.sd_rv32
connect l2_raw_block_writer.io.status.bits.uxl, cmd_router.io.dmem_status_out.bits.status.uxl
connect l2_raw_block_writer.io.status.bits.sxl, cmd_router.io.dmem_status_out.bits.status.sxl
connect l2_raw_block_writer.io.status.bits.sbe, cmd_router.io.dmem_status_out.bits.status.sbe
connect l2_raw_block_writer.io.status.bits.mbe, cmd_router.io.dmem_status_out.bits.status.mbe
connect l2_raw_block_writer.io.status.bits.gva, cmd_router.io.dmem_status_out.bits.status.gva
connect l2_raw_block_writer.io.status.bits.mpv, cmd_router.io.dmem_status_out.bits.status.mpv
connect l2_raw_block_writer.io.status.bits.zero2, cmd_router.io.dmem_status_out.bits.status.zero2
connect l2_raw_block_writer.io.status.bits.sd, cmd_router.io.dmem_status_out.bits.status.sd
connect l2_raw_block_writer.io.status.bits.v, cmd_router.io.dmem_status_out.bits.status.v
connect l2_raw_block_writer.io.status.bits.prv, cmd_router.io.dmem_status_out.bits.status.prv
connect l2_raw_block_writer.io.status.bits.dv, cmd_router.io.dmem_status_out.bits.status.dv
connect l2_raw_block_writer.io.status.bits.dprv, cmd_router.io.dmem_status_out.bits.status.dprv
connect l2_raw_block_writer.io.status.bits.isa, cmd_router.io.dmem_status_out.bits.status.isa
connect l2_raw_block_writer.io.status.bits.wfi, cmd_router.io.dmem_status_out.bits.status.wfi
connect l2_raw_block_writer.io.status.bits.cease, cmd_router.io.dmem_status_out.bits.status.cease
connect l2_raw_block_writer.io.status.bits.debug, cmd_router.io.dmem_status_out.bits.status.debug
connect l2_raw_block_writer.io.ptw.customCSRs, io.ptw[15].customCSRs
connect l2_raw_block_writer.io.ptw.pmp[0], io.ptw[15].pmp[0]
connect l2_raw_block_writer.io.ptw.pmp[1], io.ptw[15].pmp[1]
connect l2_raw_block_writer.io.ptw.pmp[2], io.ptw[15].pmp[2]
connect l2_raw_block_writer.io.ptw.pmp[3], io.ptw[15].pmp[3]
connect l2_raw_block_writer.io.ptw.pmp[4], io.ptw[15].pmp[4]
connect l2_raw_block_writer.io.ptw.pmp[5], io.ptw[15].pmp[5]
connect l2_raw_block_writer.io.ptw.pmp[6], io.ptw[15].pmp[6]
connect l2_raw_block_writer.io.ptw.pmp[7], io.ptw[15].pmp[7]
connect l2_raw_block_writer.io.ptw.gstatus, io.ptw[15].gstatus
connect l2_raw_block_writer.io.ptw.hstatus, io.ptw[15].hstatus
connect l2_raw_block_writer.io.ptw.status, io.ptw[15].status
connect l2_raw_block_writer.io.ptw.vsatp, io.ptw[15].vsatp
connect l2_raw_block_writer.io.ptw.hgatp, io.ptw[15].hgatp
connect l2_raw_block_writer.io.ptw.ptbr, io.ptw[15].ptbr
connect l2_raw_block_writer.io.ptw.resp, io.ptw[15].resp
connect io.ptw[15].req.bits, l2_raw_block_writer.io.ptw.req.bits
connect io.ptw[15].req.valid, l2_raw_block_writer.io.ptw.req.valid
connect l2_raw_block_writer.io.ptw.req.ready, io.ptw[15].req.ready
connect l2_raw_lit_reader.io.sfence, cmd_router.io.sfence_out
connect l2_raw_lit_reader.io.status.valid, cmd_router.io.dmem_status_out.valid
connect l2_raw_lit_reader.io.status.bits.uie, cmd_router.io.dmem_status_out.bits.status.uie
connect l2_raw_lit_reader.io.status.bits.sie, cmd_router.io.dmem_status_out.bits.status.sie
connect l2_raw_lit_reader.io.status.bits.hie, cmd_router.io.dmem_status_out.bits.status.hie
connect l2_raw_lit_reader.io.status.bits.mie, cmd_router.io.dmem_status_out.bits.status.mie
connect l2_raw_lit_reader.io.status.bits.upie, cmd_router.io.dmem_status_out.bits.status.upie
connect l2_raw_lit_reader.io.status.bits.spie, cmd_router.io.dmem_status_out.bits.status.spie
connect l2_raw_lit_reader.io.status.bits.ube, cmd_router.io.dmem_status_out.bits.status.ube
connect l2_raw_lit_reader.io.status.bits.mpie, cmd_router.io.dmem_status_out.bits.status.mpie
connect l2_raw_lit_reader.io.status.bits.spp, cmd_router.io.dmem_status_out.bits.status.spp
connect l2_raw_lit_reader.io.status.bits.vs, cmd_router.io.dmem_status_out.bits.status.vs
connect l2_raw_lit_reader.io.status.bits.mpp, cmd_router.io.dmem_status_out.bits.status.mpp
connect l2_raw_lit_reader.io.status.bits.fs, cmd_router.io.dmem_status_out.bits.status.fs
connect l2_raw_lit_reader.io.status.bits.xs, cmd_router.io.dmem_status_out.bits.status.xs
connect l2_raw_lit_reader.io.status.bits.mprv, cmd_router.io.dmem_status_out.bits.status.mprv
connect l2_raw_lit_reader.io.status.bits.sum, cmd_router.io.dmem_status_out.bits.status.sum
connect l2_raw_lit_reader.io.status.bits.mxr, cmd_router.io.dmem_status_out.bits.status.mxr
connect l2_raw_lit_reader.io.status.bits.tvm, cmd_router.io.dmem_status_out.bits.status.tvm
connect l2_raw_lit_reader.io.status.bits.tw, cmd_router.io.dmem_status_out.bits.status.tw
connect l2_raw_lit_reader.io.status.bits.tsr, cmd_router.io.dmem_status_out.bits.status.tsr
connect l2_raw_lit_reader.io.status.bits.zero1, cmd_router.io.dmem_status_out.bits.status.zero1
connect l2_raw_lit_reader.io.status.bits.sd_rv32, cmd_router.io.dmem_status_out.bits.status.sd_rv32
connect l2_raw_lit_reader.io.status.bits.uxl, cmd_router.io.dmem_status_out.bits.status.uxl
connect l2_raw_lit_reader.io.status.bits.sxl, cmd_router.io.dmem_status_out.bits.status.sxl
connect l2_raw_lit_reader.io.status.bits.sbe, cmd_router.io.dmem_status_out.bits.status.sbe
connect l2_raw_lit_reader.io.status.bits.mbe, cmd_router.io.dmem_status_out.bits.status.mbe
connect l2_raw_lit_reader.io.status.bits.gva, cmd_router.io.dmem_status_out.bits.status.gva
connect l2_raw_lit_reader.io.status.bits.mpv, cmd_router.io.dmem_status_out.bits.status.mpv
connect l2_raw_lit_reader.io.status.bits.zero2, cmd_router.io.dmem_status_out.bits.status.zero2
connect l2_raw_lit_reader.io.status.bits.sd, cmd_router.io.dmem_status_out.bits.status.sd
connect l2_raw_lit_reader.io.status.bits.v, cmd_router.io.dmem_status_out.bits.status.v
connect l2_raw_lit_reader.io.status.bits.prv, cmd_router.io.dmem_status_out.bits.status.prv
connect l2_raw_lit_reader.io.status.bits.dv, cmd_router.io.dmem_status_out.bits.status.dv
connect l2_raw_lit_reader.io.status.bits.dprv, cmd_router.io.dmem_status_out.bits.status.dprv
connect l2_raw_lit_reader.io.status.bits.isa, cmd_router.io.dmem_status_out.bits.status.isa
connect l2_raw_lit_reader.io.status.bits.wfi, cmd_router.io.dmem_status_out.bits.status.wfi
connect l2_raw_lit_reader.io.status.bits.cease, cmd_router.io.dmem_status_out.bits.status.cease
connect l2_raw_lit_reader.io.status.bits.debug, cmd_router.io.dmem_status_out.bits.status.debug
connect l2_raw_lit_reader.io.ptw.customCSRs, io.ptw[16].customCSRs
connect l2_raw_lit_reader.io.ptw.pmp[0], io.ptw[16].pmp[0]
connect l2_raw_lit_reader.io.ptw.pmp[1], io.ptw[16].pmp[1]
connect l2_raw_lit_reader.io.ptw.pmp[2], io.ptw[16].pmp[2]
connect l2_raw_lit_reader.io.ptw.pmp[3], io.ptw[16].pmp[3]
connect l2_raw_lit_reader.io.ptw.pmp[4], io.ptw[16].pmp[4]
connect l2_raw_lit_reader.io.ptw.pmp[5], io.ptw[16].pmp[5]
connect l2_raw_lit_reader.io.ptw.pmp[6], io.ptw[16].pmp[6]
connect l2_raw_lit_reader.io.ptw.pmp[7], io.ptw[16].pmp[7]
connect l2_raw_lit_reader.io.ptw.gstatus, io.ptw[16].gstatus
connect l2_raw_lit_reader.io.ptw.hstatus, io.ptw[16].hstatus
connect l2_raw_lit_reader.io.ptw.status, io.ptw[16].status
connect l2_raw_lit_reader.io.ptw.vsatp, io.ptw[16].vsatp
connect l2_raw_lit_reader.io.ptw.hgatp, io.ptw[16].hgatp
connect l2_raw_lit_reader.io.ptw.ptbr, io.ptw[16].ptbr
connect l2_raw_lit_reader.io.ptw.resp, io.ptw[16].resp
connect io.ptw[16].req.bits, l2_raw_lit_reader.io.ptw.req.bits
connect io.ptw[16].req.valid, l2_raw_lit_reader.io.ptw.req.valid
connect l2_raw_lit_reader.io.ptw.req.ready, io.ptw[16].req.ready
connect l2_raw_lit_writer.io.sfence, cmd_router.io.sfence_out
connect l2_raw_lit_writer.io.status.valid, cmd_router.io.dmem_status_out.valid
connect l2_raw_lit_writer.io.status.bits.uie, cmd_router.io.dmem_status_out.bits.status.uie
connect l2_raw_lit_writer.io.status.bits.sie, cmd_router.io.dmem_status_out.bits.status.sie
connect l2_raw_lit_writer.io.status.bits.hie, cmd_router.io.dmem_status_out.bits.status.hie
connect l2_raw_lit_writer.io.status.bits.mie, cmd_router.io.dmem_status_out.bits.status.mie
connect l2_raw_lit_writer.io.status.bits.upie, cmd_router.io.dmem_status_out.bits.status.upie
connect l2_raw_lit_writer.io.status.bits.spie, cmd_router.io.dmem_status_out.bits.status.spie
connect l2_raw_lit_writer.io.status.bits.ube, cmd_router.io.dmem_status_out.bits.status.ube
connect l2_raw_lit_writer.io.status.bits.mpie, cmd_router.io.dmem_status_out.bits.status.mpie
connect l2_raw_lit_writer.io.status.bits.spp, cmd_router.io.dmem_status_out.bits.status.spp
connect l2_raw_lit_writer.io.status.bits.vs, cmd_router.io.dmem_status_out.bits.status.vs
connect l2_raw_lit_writer.io.status.bits.mpp, cmd_router.io.dmem_status_out.bits.status.mpp
connect l2_raw_lit_writer.io.status.bits.fs, cmd_router.io.dmem_status_out.bits.status.fs
connect l2_raw_lit_writer.io.status.bits.xs, cmd_router.io.dmem_status_out.bits.status.xs
connect l2_raw_lit_writer.io.status.bits.mprv, cmd_router.io.dmem_status_out.bits.status.mprv
connect l2_raw_lit_writer.io.status.bits.sum, cmd_router.io.dmem_status_out.bits.status.sum
connect l2_raw_lit_writer.io.status.bits.mxr, cmd_router.io.dmem_status_out.bits.status.mxr
connect l2_raw_lit_writer.io.status.bits.tvm, cmd_router.io.dmem_status_out.bits.status.tvm
connect l2_raw_lit_writer.io.status.bits.tw, cmd_router.io.dmem_status_out.bits.status.tw
connect l2_raw_lit_writer.io.status.bits.tsr, cmd_router.io.dmem_status_out.bits.status.tsr
connect l2_raw_lit_writer.io.status.bits.zero1, cmd_router.io.dmem_status_out.bits.status.zero1
connect l2_raw_lit_writer.io.status.bits.sd_rv32, cmd_router.io.dmem_status_out.bits.status.sd_rv32
connect l2_raw_lit_writer.io.status.bits.uxl, cmd_router.io.dmem_status_out.bits.status.uxl
connect l2_raw_lit_writer.io.status.bits.sxl, cmd_router.io.dmem_status_out.bits.status.sxl
connect l2_raw_lit_writer.io.status.bits.sbe, cmd_router.io.dmem_status_out.bits.status.sbe
connect l2_raw_lit_writer.io.status.bits.mbe, cmd_router.io.dmem_status_out.bits.status.mbe
connect l2_raw_lit_writer.io.status.bits.gva, cmd_router.io.dmem_status_out.bits.status.gva
connect l2_raw_lit_writer.io.status.bits.mpv, cmd_router.io.dmem_status_out.bits.status.mpv
connect l2_raw_lit_writer.io.status.bits.zero2, cmd_router.io.dmem_status_out.bits.status.zero2
connect l2_raw_lit_writer.io.status.bits.sd, cmd_router.io.dmem_status_out.bits.status.sd
connect l2_raw_lit_writer.io.status.bits.v, cmd_router.io.dmem_status_out.bits.status.v
connect l2_raw_lit_writer.io.status.bits.prv, cmd_router.io.dmem_status_out.bits.status.prv
connect l2_raw_lit_writer.io.status.bits.dv, cmd_router.io.dmem_status_out.bits.status.dv
connect l2_raw_lit_writer.io.status.bits.dprv, cmd_router.io.dmem_status_out.bits.status.dprv
connect l2_raw_lit_writer.io.status.bits.isa, cmd_router.io.dmem_status_out.bits.status.isa
connect l2_raw_lit_writer.io.status.bits.wfi, cmd_router.io.dmem_status_out.bits.status.wfi
connect l2_raw_lit_writer.io.status.bits.cease, cmd_router.io.dmem_status_out.bits.status.cease
connect l2_raw_lit_writer.io.status.bits.debug, cmd_router.io.dmem_status_out.bits.status.debug
connect l2_raw_lit_writer.io.ptw.customCSRs, io.ptw[17].customCSRs
connect l2_raw_lit_writer.io.ptw.pmp[0], io.ptw[17].pmp[0]
connect l2_raw_lit_writer.io.ptw.pmp[1], io.ptw[17].pmp[1]
connect l2_raw_lit_writer.io.ptw.pmp[2], io.ptw[17].pmp[2]
connect l2_raw_lit_writer.io.ptw.pmp[3], io.ptw[17].pmp[3]
connect l2_raw_lit_writer.io.ptw.pmp[4], io.ptw[17].pmp[4]
connect l2_raw_lit_writer.io.ptw.pmp[5], io.ptw[17].pmp[5]
connect l2_raw_lit_writer.io.ptw.pmp[6], io.ptw[17].pmp[6]
connect l2_raw_lit_writer.io.ptw.pmp[7], io.ptw[17].pmp[7]
connect l2_raw_lit_writer.io.ptw.gstatus, io.ptw[17].gstatus
connect l2_raw_lit_writer.io.ptw.hstatus, io.ptw[17].hstatus
connect l2_raw_lit_writer.io.ptw.status, io.ptw[17].status
connect l2_raw_lit_writer.io.ptw.vsatp, io.ptw[17].vsatp
connect l2_raw_lit_writer.io.ptw.hgatp, io.ptw[17].hgatp
connect l2_raw_lit_writer.io.ptw.ptbr, io.ptw[17].ptbr
connect l2_raw_lit_writer.io.ptw.resp, io.ptw[17].resp
connect io.ptw[17].req.bits, l2_raw_lit_writer.io.ptw.req.bits
connect io.ptw[17].req.valid, l2_raw_lit_writer.io.ptw.req.valid
connect l2_raw_lit_writer.io.ptw.req.ready, io.ptw[17].req.ready | module ZstdCompressor( // @[ZstdCompressor.scala:95:7]
input clock, // @[ZstdCompressor.scala:95:7]
input reset, // @[ZstdCompressor.scala:95:7]
input auto_tl_out_17_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_17_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_out_17_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_out_17_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_tl_out_17_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_tl_out_17_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_tl_out_17_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_tl_out_17_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_tl_out_17_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_17_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_17_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_17_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_out_17_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_tl_out_17_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_tl_out_17_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_tl_out_17_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_out_17_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_17_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_tl_out_17_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_17_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_16_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_16_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_out_16_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_out_16_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_tl_out_16_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_tl_out_16_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_tl_out_16_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_tl_out_16_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_tl_out_16_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_16_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_16_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_16_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_out_16_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_tl_out_16_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_tl_out_16_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_tl_out_16_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_out_16_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_16_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_tl_out_16_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_16_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_15_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_15_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_out_15_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_out_15_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_tl_out_15_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_tl_out_15_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_tl_out_15_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_tl_out_15_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_tl_out_15_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_15_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_15_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_15_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_out_15_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_tl_out_15_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_tl_out_15_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_tl_out_15_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_out_15_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_15_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_tl_out_15_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_15_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_14_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_14_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_out_14_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_out_14_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_tl_out_14_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_tl_out_14_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_tl_out_14_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_tl_out_14_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_tl_out_14_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_14_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_14_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_14_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_out_14_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_tl_out_14_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_tl_out_14_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_tl_out_14_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_out_14_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_14_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_tl_out_14_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_14_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_13_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_13_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_out_13_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_out_13_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_tl_out_13_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_tl_out_13_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_tl_out_13_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_tl_out_13_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_tl_out_13_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_13_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_13_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_13_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_out_13_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_tl_out_13_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_tl_out_13_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_tl_out_13_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_out_13_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_13_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_tl_out_13_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_13_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_12_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_12_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_out_12_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_out_12_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_tl_out_12_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_tl_out_12_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_tl_out_12_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_tl_out_12_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_tl_out_12_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_12_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_12_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_12_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_out_12_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_tl_out_12_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_tl_out_12_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_tl_out_12_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_out_12_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_12_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_tl_out_12_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_12_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_11_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_11_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_out_11_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_out_11_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_tl_out_11_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_tl_out_11_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_tl_out_11_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_tl_out_11_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_tl_out_11_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_11_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_11_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_11_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_out_11_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_tl_out_11_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_tl_out_11_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_tl_out_11_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_out_11_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_11_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_tl_out_11_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_11_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_10_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_10_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_out_10_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_out_10_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_tl_out_10_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_tl_out_10_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_tl_out_10_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_tl_out_10_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_tl_out_10_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_10_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_10_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_10_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_out_10_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_tl_out_10_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_tl_out_10_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_tl_out_10_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_out_10_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_10_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_tl_out_10_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_10_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_9_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_9_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_out_9_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_out_9_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_tl_out_9_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_tl_out_9_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_tl_out_9_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_tl_out_9_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_tl_out_9_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_9_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_9_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_9_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_out_9_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_tl_out_9_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_tl_out_9_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_tl_out_9_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_out_9_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_9_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_tl_out_9_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_9_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_8_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_8_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_out_8_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_out_8_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_tl_out_8_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_tl_out_8_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_tl_out_8_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_tl_out_8_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_tl_out_8_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_8_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_8_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_8_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_out_8_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_tl_out_8_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_tl_out_8_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_tl_out_8_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_out_8_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_8_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_tl_out_8_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_8_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_7_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_7_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_out_7_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_out_7_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_tl_out_7_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_tl_out_7_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_tl_out_7_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_tl_out_7_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_tl_out_7_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_7_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_7_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_7_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_out_7_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_tl_out_7_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_tl_out_7_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_tl_out_7_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_out_7_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_7_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_tl_out_7_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_7_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_6_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_6_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_out_6_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_out_6_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_tl_out_6_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_tl_out_6_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_tl_out_6_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_tl_out_6_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_tl_out_6_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_6_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_6_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_6_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_out_6_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_tl_out_6_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_tl_out_6_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_tl_out_6_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_out_6_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_6_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_tl_out_6_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_6_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_5_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_5_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_out_5_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_out_5_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_tl_out_5_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_tl_out_5_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_tl_out_5_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_tl_out_5_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_tl_out_5_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_5_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_5_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_5_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_out_5_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_tl_out_5_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_tl_out_5_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_tl_out_5_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_out_5_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_5_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_tl_out_5_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_5_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_4_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_4_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_out_4_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_out_4_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_tl_out_4_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_tl_out_4_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_tl_out_4_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_tl_out_4_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_tl_out_4_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_4_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_4_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_4_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_out_4_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_tl_out_4_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_tl_out_4_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_tl_out_4_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_out_4_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_4_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_tl_out_4_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_4_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_3_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_3_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_out_3_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_out_3_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_tl_out_3_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_tl_out_3_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_tl_out_3_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_tl_out_3_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_tl_out_3_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_3_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_3_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_3_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_out_3_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_tl_out_3_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_tl_out_3_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_tl_out_3_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_out_3_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_3_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_tl_out_3_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_3_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_2_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_2_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_out_2_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_out_2_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_tl_out_2_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_tl_out_2_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_tl_out_2_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_tl_out_2_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_tl_out_2_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_2_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_2_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_2_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_out_2_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_tl_out_2_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_tl_out_2_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_tl_out_2_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_out_2_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_2_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_tl_out_2_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_2_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_1_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_1_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_tl_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_tl_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_tl_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_tl_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_tl_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_1_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_1_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_tl_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_tl_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_tl_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_tl_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_0_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_0_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_tl_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_tl_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_tl_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_tl_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_tl_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_0_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_0_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_tl_out_0_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_tl_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_tl_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_out_0_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_tl_out_0_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output io_cmd_ready, // @[LazyRoCC.scala:78:14]
input io_cmd_valid, // @[LazyRoCC.scala:78:14]
input [6:0] io_cmd_bits_inst_funct, // @[LazyRoCC.scala:78:14]
input [4:0] io_cmd_bits_inst_rs2, // @[LazyRoCC.scala:78:14]
input [4:0] io_cmd_bits_inst_rs1, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_inst_xd, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_inst_xs1, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_inst_xs2, // @[LazyRoCC.scala:78:14]
input [4:0] io_cmd_bits_inst_rd, // @[LazyRoCC.scala:78:14]
input [6:0] io_cmd_bits_inst_opcode, // @[LazyRoCC.scala:78:14]
input [63:0] io_cmd_bits_rs1, // @[LazyRoCC.scala:78:14]
input [63:0] io_cmd_bits_rs2, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_debug, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_cease, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_wfi, // @[LazyRoCC.scala:78:14]
input [31:0] io_cmd_bits_status_isa, // @[LazyRoCC.scala:78:14]
input [1:0] io_cmd_bits_status_dprv, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_dv, // @[LazyRoCC.scala:78:14]
input [1:0] io_cmd_bits_status_prv, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_v, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_sd, // @[LazyRoCC.scala:78:14]
input [22:0] io_cmd_bits_status_zero2, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_mpv, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_gva, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_mbe, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_sbe, // @[LazyRoCC.scala:78:14]
input [1:0] io_cmd_bits_status_sxl, // @[LazyRoCC.scala:78:14]
input [1:0] io_cmd_bits_status_uxl, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_sd_rv32, // @[LazyRoCC.scala:78:14]
input [7:0] io_cmd_bits_status_zero1, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_tsr, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_tw, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_tvm, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_mxr, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_sum, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_mprv, // @[LazyRoCC.scala:78:14]
input [1:0] io_cmd_bits_status_xs, // @[LazyRoCC.scala:78:14]
input [1:0] io_cmd_bits_status_fs, // @[LazyRoCC.scala:78:14]
input [1:0] io_cmd_bits_status_mpp, // @[LazyRoCC.scala:78:14]
input [1:0] io_cmd_bits_status_vs, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_spp, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_mpie, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_ube, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_spie, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_upie, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_mie, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_hie, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_sie, // @[LazyRoCC.scala:78:14]
input io_cmd_bits_status_uie, // @[LazyRoCC.scala:78:14]
input io_resp_ready, // @[LazyRoCC.scala:78:14]
output io_resp_valid, // @[LazyRoCC.scala:78:14]
output [4:0] io_resp_bits_rd, // @[LazyRoCC.scala:78:14]
output [63:0] io_resp_bits_data, // @[LazyRoCC.scala:78:14]
input io_mem_req_ready, // @[LazyRoCC.scala:78:14]
input io_mem_resp_valid, // @[LazyRoCC.scala:78:14]
input [39:0] io_mem_resp_bits_addr, // @[LazyRoCC.scala:78:14]
input [7:0] io_mem_resp_bits_tag, // @[LazyRoCC.scala:78:14]
input [4:0] io_mem_resp_bits_cmd, // @[LazyRoCC.scala:78:14]
input [1:0] io_mem_resp_bits_size, // @[LazyRoCC.scala:78:14]
input io_mem_resp_bits_signed, // @[LazyRoCC.scala:78:14]
input [1:0] io_mem_resp_bits_dprv, // @[LazyRoCC.scala:78:14]
input io_mem_resp_bits_dv, // @[LazyRoCC.scala:78:14]
input [63:0] io_mem_resp_bits_data, // @[LazyRoCC.scala:78:14]
input [7:0] io_mem_resp_bits_mask, // @[LazyRoCC.scala:78:14]
input io_mem_resp_bits_replay, // @[LazyRoCC.scala:78:14]
input io_mem_resp_bits_has_data, // @[LazyRoCC.scala:78:14]
input [63:0] io_mem_resp_bits_data_word_bypass, // @[LazyRoCC.scala:78:14]
input [63:0] io_mem_resp_bits_data_raw, // @[LazyRoCC.scala:78:14]
input [63:0] io_mem_resp_bits_store_data, // @[LazyRoCC.scala:78:14]
input io_exception, // @[LazyRoCC.scala:78:14]
input io_ptw_0_req_ready, // @[LazyRoCC.scala:78:14]
output io_ptw_0_req_valid, // @[LazyRoCC.scala:78:14]
output [26:0] io_ptw_0_req_bits_bits_addr, // @[LazyRoCC.scala:78:14]
output io_ptw_0_req_bits_bits_need_gpa, // @[LazyRoCC.scala:78:14]
input io_ptw_0_resp_valid, // @[LazyRoCC.scala:78:14]
input io_ptw_0_resp_bits_ae_ptw, // @[LazyRoCC.scala:78:14]
input io_ptw_0_resp_bits_ae_final, // @[LazyRoCC.scala:78:14]
input io_ptw_0_resp_bits_pf, // @[LazyRoCC.scala:78:14]
input io_ptw_0_resp_bits_gf, // @[LazyRoCC.scala:78:14]
input io_ptw_0_resp_bits_hr, // @[LazyRoCC.scala:78:14]
input io_ptw_0_resp_bits_hw, // @[LazyRoCC.scala:78:14]
input io_ptw_0_resp_bits_hx, // @[LazyRoCC.scala:78:14]
input [9:0] io_ptw_0_resp_bits_pte_reserved_for_future, // @[LazyRoCC.scala:78:14]
input [43:0] io_ptw_0_resp_bits_pte_ppn, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_0_resp_bits_pte_reserved_for_software, // @[LazyRoCC.scala:78:14]
input io_ptw_0_resp_bits_pte_d, // @[LazyRoCC.scala:78:14]
input io_ptw_0_resp_bits_pte_a, // @[LazyRoCC.scala:78:14]
input io_ptw_0_resp_bits_pte_g, // @[LazyRoCC.scala:78:14]
input io_ptw_0_resp_bits_pte_u, // @[LazyRoCC.scala:78:14]
input io_ptw_0_resp_bits_pte_x, // @[LazyRoCC.scala:78:14]
input io_ptw_0_resp_bits_pte_w, // @[LazyRoCC.scala:78:14]
input io_ptw_0_resp_bits_pte_r, // @[LazyRoCC.scala:78:14]
input io_ptw_0_resp_bits_pte_v, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_0_resp_bits_level, // @[LazyRoCC.scala:78:14]
input io_ptw_0_resp_bits_homogeneous, // @[LazyRoCC.scala:78:14]
input io_ptw_0_resp_bits_gpa_valid, // @[LazyRoCC.scala:78:14]
input [38:0] io_ptw_0_resp_bits_gpa_bits, // @[LazyRoCC.scala:78:14]
input io_ptw_0_resp_bits_gpa_is_pte, // @[LazyRoCC.scala:78:14]
input [3:0] io_ptw_0_ptbr_mode, // @[LazyRoCC.scala:78:14]
input [43:0] io_ptw_0_ptbr_ppn, // @[LazyRoCC.scala:78:14]
input io_ptw_0_status_debug, // @[LazyRoCC.scala:78:14]
input io_ptw_0_status_cease, // @[LazyRoCC.scala:78:14]
input io_ptw_0_status_wfi, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_0_status_isa, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_0_status_dprv, // @[LazyRoCC.scala:78:14]
input io_ptw_0_status_dv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_0_status_prv, // @[LazyRoCC.scala:78:14]
input io_ptw_0_status_v, // @[LazyRoCC.scala:78:14]
input io_ptw_0_status_mpv, // @[LazyRoCC.scala:78:14]
input io_ptw_0_status_gva, // @[LazyRoCC.scala:78:14]
input io_ptw_0_status_tsr, // @[LazyRoCC.scala:78:14]
input io_ptw_0_status_tw, // @[LazyRoCC.scala:78:14]
input io_ptw_0_status_tvm, // @[LazyRoCC.scala:78:14]
input io_ptw_0_status_mxr, // @[LazyRoCC.scala:78:14]
input io_ptw_0_status_sum, // @[LazyRoCC.scala:78:14]
input io_ptw_0_status_mprv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_0_status_fs, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_0_status_mpp, // @[LazyRoCC.scala:78:14]
input io_ptw_0_status_spp, // @[LazyRoCC.scala:78:14]
input io_ptw_0_status_mpie, // @[LazyRoCC.scala:78:14]
input io_ptw_0_status_spie, // @[LazyRoCC.scala:78:14]
input io_ptw_0_status_mie, // @[LazyRoCC.scala:78:14]
input io_ptw_0_status_sie, // @[LazyRoCC.scala:78:14]
input io_ptw_0_hstatus_spvp, // @[LazyRoCC.scala:78:14]
input io_ptw_0_hstatus_spv, // @[LazyRoCC.scala:78:14]
input io_ptw_0_hstatus_gva, // @[LazyRoCC.scala:78:14]
input io_ptw_0_gstatus_debug, // @[LazyRoCC.scala:78:14]
input io_ptw_0_gstatus_cease, // @[LazyRoCC.scala:78:14]
input io_ptw_0_gstatus_wfi, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_0_gstatus_isa, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_0_gstatus_dprv, // @[LazyRoCC.scala:78:14]
input io_ptw_0_gstatus_dv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_0_gstatus_prv, // @[LazyRoCC.scala:78:14]
input io_ptw_0_gstatus_v, // @[LazyRoCC.scala:78:14]
input [22:0] io_ptw_0_gstatus_zero2, // @[LazyRoCC.scala:78:14]
input io_ptw_0_gstatus_mpv, // @[LazyRoCC.scala:78:14]
input io_ptw_0_gstatus_gva, // @[LazyRoCC.scala:78:14]
input io_ptw_0_gstatus_mbe, // @[LazyRoCC.scala:78:14]
input io_ptw_0_gstatus_sbe, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_0_gstatus_sxl, // @[LazyRoCC.scala:78:14]
input [7:0] io_ptw_0_gstatus_zero1, // @[LazyRoCC.scala:78:14]
input io_ptw_0_gstatus_tsr, // @[LazyRoCC.scala:78:14]
input io_ptw_0_gstatus_tw, // @[LazyRoCC.scala:78:14]
input io_ptw_0_gstatus_tvm, // @[LazyRoCC.scala:78:14]
input io_ptw_0_gstatus_mxr, // @[LazyRoCC.scala:78:14]
input io_ptw_0_gstatus_sum, // @[LazyRoCC.scala:78:14]
input io_ptw_0_gstatus_mprv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_0_gstatus_fs, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_0_gstatus_mpp, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_0_gstatus_vs, // @[LazyRoCC.scala:78:14]
input io_ptw_0_gstatus_spp, // @[LazyRoCC.scala:78:14]
input io_ptw_0_gstatus_mpie, // @[LazyRoCC.scala:78:14]
input io_ptw_0_gstatus_ube, // @[LazyRoCC.scala:78:14]
input io_ptw_0_gstatus_spie, // @[LazyRoCC.scala:78:14]
input io_ptw_0_gstatus_upie, // @[LazyRoCC.scala:78:14]
input io_ptw_0_gstatus_mie, // @[LazyRoCC.scala:78:14]
input io_ptw_0_gstatus_hie, // @[LazyRoCC.scala:78:14]
input io_ptw_0_gstatus_sie, // @[LazyRoCC.scala:78:14]
input io_ptw_0_gstatus_uie, // @[LazyRoCC.scala:78:14]
input io_ptw_0_pmp_0_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_0_pmp_0_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_0_pmp_0_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_0_pmp_0_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_0_pmp_0_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_0_pmp_0_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_0_pmp_0_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_0_pmp_1_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_0_pmp_1_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_0_pmp_1_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_0_pmp_1_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_0_pmp_1_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_0_pmp_1_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_0_pmp_1_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_0_pmp_2_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_0_pmp_2_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_0_pmp_2_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_0_pmp_2_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_0_pmp_2_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_0_pmp_2_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_0_pmp_2_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_0_pmp_3_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_0_pmp_3_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_0_pmp_3_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_0_pmp_3_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_0_pmp_3_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_0_pmp_3_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_0_pmp_3_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_0_pmp_4_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_0_pmp_4_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_0_pmp_4_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_0_pmp_4_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_0_pmp_4_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_0_pmp_4_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_0_pmp_4_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_0_pmp_5_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_0_pmp_5_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_0_pmp_5_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_0_pmp_5_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_0_pmp_5_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_0_pmp_5_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_0_pmp_5_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_0_pmp_6_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_0_pmp_6_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_0_pmp_6_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_0_pmp_6_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_0_pmp_6_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_0_pmp_6_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_0_pmp_6_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_0_pmp_7_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_0_pmp_7_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_0_pmp_7_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_0_pmp_7_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_0_pmp_7_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_0_pmp_7_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_0_pmp_7_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_0_customCSRs_csrs_0_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_0_customCSRs_csrs_0_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_0_customCSRs_csrs_0_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_0_customCSRs_csrs_0_value, // @[LazyRoCC.scala:78:14]
input io_ptw_0_customCSRs_csrs_1_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_0_customCSRs_csrs_1_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_0_customCSRs_csrs_1_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_0_customCSRs_csrs_1_value, // @[LazyRoCC.scala:78:14]
input io_ptw_0_customCSRs_csrs_2_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_0_customCSRs_csrs_2_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_0_customCSRs_csrs_2_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_0_customCSRs_csrs_2_value, // @[LazyRoCC.scala:78:14]
input io_ptw_0_customCSRs_csrs_3_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_0_customCSRs_csrs_3_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_0_customCSRs_csrs_3_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_0_customCSRs_csrs_3_value, // @[LazyRoCC.scala:78:14]
input io_ptw_1_req_ready, // @[LazyRoCC.scala:78:14]
output io_ptw_1_req_valid, // @[LazyRoCC.scala:78:14]
output [26:0] io_ptw_1_req_bits_bits_addr, // @[LazyRoCC.scala:78:14]
output io_ptw_1_req_bits_bits_need_gpa, // @[LazyRoCC.scala:78:14]
input io_ptw_1_resp_valid, // @[LazyRoCC.scala:78:14]
input io_ptw_1_resp_bits_ae_ptw, // @[LazyRoCC.scala:78:14]
input io_ptw_1_resp_bits_ae_final, // @[LazyRoCC.scala:78:14]
input io_ptw_1_resp_bits_pf, // @[LazyRoCC.scala:78:14]
input io_ptw_1_resp_bits_gf, // @[LazyRoCC.scala:78:14]
input io_ptw_1_resp_bits_hr, // @[LazyRoCC.scala:78:14]
input io_ptw_1_resp_bits_hw, // @[LazyRoCC.scala:78:14]
input io_ptw_1_resp_bits_hx, // @[LazyRoCC.scala:78:14]
input [9:0] io_ptw_1_resp_bits_pte_reserved_for_future, // @[LazyRoCC.scala:78:14]
input [43:0] io_ptw_1_resp_bits_pte_ppn, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_1_resp_bits_pte_reserved_for_software, // @[LazyRoCC.scala:78:14]
input io_ptw_1_resp_bits_pte_d, // @[LazyRoCC.scala:78:14]
input io_ptw_1_resp_bits_pte_a, // @[LazyRoCC.scala:78:14]
input io_ptw_1_resp_bits_pte_g, // @[LazyRoCC.scala:78:14]
input io_ptw_1_resp_bits_pte_u, // @[LazyRoCC.scala:78:14]
input io_ptw_1_resp_bits_pte_x, // @[LazyRoCC.scala:78:14]
input io_ptw_1_resp_bits_pte_w, // @[LazyRoCC.scala:78:14]
input io_ptw_1_resp_bits_pte_r, // @[LazyRoCC.scala:78:14]
input io_ptw_1_resp_bits_pte_v, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_1_resp_bits_level, // @[LazyRoCC.scala:78:14]
input io_ptw_1_resp_bits_homogeneous, // @[LazyRoCC.scala:78:14]
input io_ptw_1_resp_bits_gpa_valid, // @[LazyRoCC.scala:78:14]
input [38:0] io_ptw_1_resp_bits_gpa_bits, // @[LazyRoCC.scala:78:14]
input io_ptw_1_resp_bits_gpa_is_pte, // @[LazyRoCC.scala:78:14]
input [3:0] io_ptw_1_ptbr_mode, // @[LazyRoCC.scala:78:14]
input [43:0] io_ptw_1_ptbr_ppn, // @[LazyRoCC.scala:78:14]
input io_ptw_1_status_debug, // @[LazyRoCC.scala:78:14]
input io_ptw_1_status_cease, // @[LazyRoCC.scala:78:14]
input io_ptw_1_status_wfi, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_1_status_isa, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_1_status_dprv, // @[LazyRoCC.scala:78:14]
input io_ptw_1_status_dv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_1_status_prv, // @[LazyRoCC.scala:78:14]
input io_ptw_1_status_v, // @[LazyRoCC.scala:78:14]
input io_ptw_1_status_mpv, // @[LazyRoCC.scala:78:14]
input io_ptw_1_status_gva, // @[LazyRoCC.scala:78:14]
input io_ptw_1_status_tsr, // @[LazyRoCC.scala:78:14]
input io_ptw_1_status_tw, // @[LazyRoCC.scala:78:14]
input io_ptw_1_status_tvm, // @[LazyRoCC.scala:78:14]
input io_ptw_1_status_mxr, // @[LazyRoCC.scala:78:14]
input io_ptw_1_status_sum, // @[LazyRoCC.scala:78:14]
input io_ptw_1_status_mprv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_1_status_fs, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_1_status_mpp, // @[LazyRoCC.scala:78:14]
input io_ptw_1_status_spp, // @[LazyRoCC.scala:78:14]
input io_ptw_1_status_mpie, // @[LazyRoCC.scala:78:14]
input io_ptw_1_status_spie, // @[LazyRoCC.scala:78:14]
input io_ptw_1_status_mie, // @[LazyRoCC.scala:78:14]
input io_ptw_1_status_sie, // @[LazyRoCC.scala:78:14]
input io_ptw_1_hstatus_spvp, // @[LazyRoCC.scala:78:14]
input io_ptw_1_hstatus_spv, // @[LazyRoCC.scala:78:14]
input io_ptw_1_hstatus_gva, // @[LazyRoCC.scala:78:14]
input io_ptw_1_gstatus_debug, // @[LazyRoCC.scala:78:14]
input io_ptw_1_gstatus_cease, // @[LazyRoCC.scala:78:14]
input io_ptw_1_gstatus_wfi, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_1_gstatus_isa, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_1_gstatus_dprv, // @[LazyRoCC.scala:78:14]
input io_ptw_1_gstatus_dv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_1_gstatus_prv, // @[LazyRoCC.scala:78:14]
input io_ptw_1_gstatus_v, // @[LazyRoCC.scala:78:14]
input [22:0] io_ptw_1_gstatus_zero2, // @[LazyRoCC.scala:78:14]
input io_ptw_1_gstatus_mpv, // @[LazyRoCC.scala:78:14]
input io_ptw_1_gstatus_gva, // @[LazyRoCC.scala:78:14]
input io_ptw_1_gstatus_mbe, // @[LazyRoCC.scala:78:14]
input io_ptw_1_gstatus_sbe, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_1_gstatus_sxl, // @[LazyRoCC.scala:78:14]
input [7:0] io_ptw_1_gstatus_zero1, // @[LazyRoCC.scala:78:14]
input io_ptw_1_gstatus_tsr, // @[LazyRoCC.scala:78:14]
input io_ptw_1_gstatus_tw, // @[LazyRoCC.scala:78:14]
input io_ptw_1_gstatus_tvm, // @[LazyRoCC.scala:78:14]
input io_ptw_1_gstatus_mxr, // @[LazyRoCC.scala:78:14]
input io_ptw_1_gstatus_sum, // @[LazyRoCC.scala:78:14]
input io_ptw_1_gstatus_mprv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_1_gstatus_fs, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_1_gstatus_mpp, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_1_gstatus_vs, // @[LazyRoCC.scala:78:14]
input io_ptw_1_gstatus_spp, // @[LazyRoCC.scala:78:14]
input io_ptw_1_gstatus_mpie, // @[LazyRoCC.scala:78:14]
input io_ptw_1_gstatus_ube, // @[LazyRoCC.scala:78:14]
input io_ptw_1_gstatus_spie, // @[LazyRoCC.scala:78:14]
input io_ptw_1_gstatus_upie, // @[LazyRoCC.scala:78:14]
input io_ptw_1_gstatus_mie, // @[LazyRoCC.scala:78:14]
input io_ptw_1_gstatus_hie, // @[LazyRoCC.scala:78:14]
input io_ptw_1_gstatus_sie, // @[LazyRoCC.scala:78:14]
input io_ptw_1_gstatus_uie, // @[LazyRoCC.scala:78:14]
input io_ptw_1_pmp_0_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_1_pmp_0_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_1_pmp_0_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_1_pmp_0_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_1_pmp_0_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_1_pmp_0_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_1_pmp_0_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_1_pmp_1_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_1_pmp_1_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_1_pmp_1_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_1_pmp_1_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_1_pmp_1_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_1_pmp_1_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_1_pmp_1_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_1_pmp_2_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_1_pmp_2_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_1_pmp_2_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_1_pmp_2_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_1_pmp_2_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_1_pmp_2_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_1_pmp_2_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_1_pmp_3_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_1_pmp_3_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_1_pmp_3_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_1_pmp_3_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_1_pmp_3_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_1_pmp_3_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_1_pmp_3_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_1_pmp_4_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_1_pmp_4_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_1_pmp_4_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_1_pmp_4_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_1_pmp_4_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_1_pmp_4_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_1_pmp_4_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_1_pmp_5_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_1_pmp_5_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_1_pmp_5_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_1_pmp_5_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_1_pmp_5_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_1_pmp_5_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_1_pmp_5_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_1_pmp_6_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_1_pmp_6_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_1_pmp_6_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_1_pmp_6_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_1_pmp_6_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_1_pmp_6_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_1_pmp_6_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_1_pmp_7_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_1_pmp_7_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_1_pmp_7_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_1_pmp_7_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_1_pmp_7_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_1_pmp_7_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_1_pmp_7_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_1_customCSRs_csrs_0_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_1_customCSRs_csrs_0_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_1_customCSRs_csrs_0_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_1_customCSRs_csrs_0_value, // @[LazyRoCC.scala:78:14]
input io_ptw_1_customCSRs_csrs_1_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_1_customCSRs_csrs_1_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_1_customCSRs_csrs_1_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_1_customCSRs_csrs_1_value, // @[LazyRoCC.scala:78:14]
input io_ptw_1_customCSRs_csrs_2_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_1_customCSRs_csrs_2_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_1_customCSRs_csrs_2_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_1_customCSRs_csrs_2_value, // @[LazyRoCC.scala:78:14]
input io_ptw_1_customCSRs_csrs_3_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_1_customCSRs_csrs_3_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_1_customCSRs_csrs_3_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_1_customCSRs_csrs_3_value, // @[LazyRoCC.scala:78:14]
input io_ptw_2_req_ready, // @[LazyRoCC.scala:78:14]
output io_ptw_2_req_valid, // @[LazyRoCC.scala:78:14]
output [26:0] io_ptw_2_req_bits_bits_addr, // @[LazyRoCC.scala:78:14]
output io_ptw_2_req_bits_bits_need_gpa, // @[LazyRoCC.scala:78:14]
input io_ptw_2_resp_valid, // @[LazyRoCC.scala:78:14]
input io_ptw_2_resp_bits_ae_ptw, // @[LazyRoCC.scala:78:14]
input io_ptw_2_resp_bits_ae_final, // @[LazyRoCC.scala:78:14]
input io_ptw_2_resp_bits_pf, // @[LazyRoCC.scala:78:14]
input io_ptw_2_resp_bits_gf, // @[LazyRoCC.scala:78:14]
input io_ptw_2_resp_bits_hr, // @[LazyRoCC.scala:78:14]
input io_ptw_2_resp_bits_hw, // @[LazyRoCC.scala:78:14]
input io_ptw_2_resp_bits_hx, // @[LazyRoCC.scala:78:14]
input [9:0] io_ptw_2_resp_bits_pte_reserved_for_future, // @[LazyRoCC.scala:78:14]
input [43:0] io_ptw_2_resp_bits_pte_ppn, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_2_resp_bits_pte_reserved_for_software, // @[LazyRoCC.scala:78:14]
input io_ptw_2_resp_bits_pte_d, // @[LazyRoCC.scala:78:14]
input io_ptw_2_resp_bits_pte_a, // @[LazyRoCC.scala:78:14]
input io_ptw_2_resp_bits_pte_g, // @[LazyRoCC.scala:78:14]
input io_ptw_2_resp_bits_pte_u, // @[LazyRoCC.scala:78:14]
input io_ptw_2_resp_bits_pte_x, // @[LazyRoCC.scala:78:14]
input io_ptw_2_resp_bits_pte_w, // @[LazyRoCC.scala:78:14]
input io_ptw_2_resp_bits_pte_r, // @[LazyRoCC.scala:78:14]
input io_ptw_2_resp_bits_pte_v, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_2_resp_bits_level, // @[LazyRoCC.scala:78:14]
input io_ptw_2_resp_bits_homogeneous, // @[LazyRoCC.scala:78:14]
input io_ptw_2_resp_bits_gpa_valid, // @[LazyRoCC.scala:78:14]
input [38:0] io_ptw_2_resp_bits_gpa_bits, // @[LazyRoCC.scala:78:14]
input io_ptw_2_resp_bits_gpa_is_pte, // @[LazyRoCC.scala:78:14]
input [3:0] io_ptw_2_ptbr_mode, // @[LazyRoCC.scala:78:14]
input [43:0] io_ptw_2_ptbr_ppn, // @[LazyRoCC.scala:78:14]
input io_ptw_2_status_debug, // @[LazyRoCC.scala:78:14]
input io_ptw_2_status_cease, // @[LazyRoCC.scala:78:14]
input io_ptw_2_status_wfi, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_2_status_isa, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_2_status_dprv, // @[LazyRoCC.scala:78:14]
input io_ptw_2_status_dv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_2_status_prv, // @[LazyRoCC.scala:78:14]
input io_ptw_2_status_v, // @[LazyRoCC.scala:78:14]
input io_ptw_2_status_mpv, // @[LazyRoCC.scala:78:14]
input io_ptw_2_status_gva, // @[LazyRoCC.scala:78:14]
input io_ptw_2_status_tsr, // @[LazyRoCC.scala:78:14]
input io_ptw_2_status_tw, // @[LazyRoCC.scala:78:14]
input io_ptw_2_status_tvm, // @[LazyRoCC.scala:78:14]
input io_ptw_2_status_mxr, // @[LazyRoCC.scala:78:14]
input io_ptw_2_status_sum, // @[LazyRoCC.scala:78:14]
input io_ptw_2_status_mprv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_2_status_fs, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_2_status_mpp, // @[LazyRoCC.scala:78:14]
input io_ptw_2_status_spp, // @[LazyRoCC.scala:78:14]
input io_ptw_2_status_mpie, // @[LazyRoCC.scala:78:14]
input io_ptw_2_status_spie, // @[LazyRoCC.scala:78:14]
input io_ptw_2_status_mie, // @[LazyRoCC.scala:78:14]
input io_ptw_2_status_sie, // @[LazyRoCC.scala:78:14]
input io_ptw_2_hstatus_spvp, // @[LazyRoCC.scala:78:14]
input io_ptw_2_hstatus_spv, // @[LazyRoCC.scala:78:14]
input io_ptw_2_hstatus_gva, // @[LazyRoCC.scala:78:14]
input io_ptw_2_gstatus_debug, // @[LazyRoCC.scala:78:14]
input io_ptw_2_gstatus_cease, // @[LazyRoCC.scala:78:14]
input io_ptw_2_gstatus_wfi, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_2_gstatus_isa, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_2_gstatus_dprv, // @[LazyRoCC.scala:78:14]
input io_ptw_2_gstatus_dv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_2_gstatus_prv, // @[LazyRoCC.scala:78:14]
input io_ptw_2_gstatus_v, // @[LazyRoCC.scala:78:14]
input [22:0] io_ptw_2_gstatus_zero2, // @[LazyRoCC.scala:78:14]
input io_ptw_2_gstatus_mpv, // @[LazyRoCC.scala:78:14]
input io_ptw_2_gstatus_gva, // @[LazyRoCC.scala:78:14]
input io_ptw_2_gstatus_mbe, // @[LazyRoCC.scala:78:14]
input io_ptw_2_gstatus_sbe, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_2_gstatus_sxl, // @[LazyRoCC.scala:78:14]
input [7:0] io_ptw_2_gstatus_zero1, // @[LazyRoCC.scala:78:14]
input io_ptw_2_gstatus_tsr, // @[LazyRoCC.scala:78:14]
input io_ptw_2_gstatus_tw, // @[LazyRoCC.scala:78:14]
input io_ptw_2_gstatus_tvm, // @[LazyRoCC.scala:78:14]
input io_ptw_2_gstatus_mxr, // @[LazyRoCC.scala:78:14]
input io_ptw_2_gstatus_sum, // @[LazyRoCC.scala:78:14]
input io_ptw_2_gstatus_mprv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_2_gstatus_fs, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_2_gstatus_mpp, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_2_gstatus_vs, // @[LazyRoCC.scala:78:14]
input io_ptw_2_gstatus_spp, // @[LazyRoCC.scala:78:14]
input io_ptw_2_gstatus_mpie, // @[LazyRoCC.scala:78:14]
input io_ptw_2_gstatus_ube, // @[LazyRoCC.scala:78:14]
input io_ptw_2_gstatus_spie, // @[LazyRoCC.scala:78:14]
input io_ptw_2_gstatus_upie, // @[LazyRoCC.scala:78:14]
input io_ptw_2_gstatus_mie, // @[LazyRoCC.scala:78:14]
input io_ptw_2_gstatus_hie, // @[LazyRoCC.scala:78:14]
input io_ptw_2_gstatus_sie, // @[LazyRoCC.scala:78:14]
input io_ptw_2_gstatus_uie, // @[LazyRoCC.scala:78:14]
input io_ptw_2_pmp_0_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_2_pmp_0_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_2_pmp_0_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_2_pmp_0_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_2_pmp_0_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_2_pmp_0_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_2_pmp_0_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_2_pmp_1_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_2_pmp_1_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_2_pmp_1_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_2_pmp_1_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_2_pmp_1_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_2_pmp_1_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_2_pmp_1_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_2_pmp_2_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_2_pmp_2_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_2_pmp_2_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_2_pmp_2_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_2_pmp_2_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_2_pmp_2_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_2_pmp_2_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_2_pmp_3_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_2_pmp_3_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_2_pmp_3_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_2_pmp_3_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_2_pmp_3_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_2_pmp_3_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_2_pmp_3_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_2_pmp_4_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_2_pmp_4_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_2_pmp_4_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_2_pmp_4_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_2_pmp_4_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_2_pmp_4_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_2_pmp_4_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_2_pmp_5_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_2_pmp_5_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_2_pmp_5_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_2_pmp_5_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_2_pmp_5_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_2_pmp_5_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_2_pmp_5_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_2_pmp_6_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_2_pmp_6_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_2_pmp_6_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_2_pmp_6_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_2_pmp_6_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_2_pmp_6_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_2_pmp_6_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_2_pmp_7_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_2_pmp_7_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_2_pmp_7_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_2_pmp_7_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_2_pmp_7_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_2_pmp_7_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_2_pmp_7_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_2_customCSRs_csrs_0_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_2_customCSRs_csrs_0_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_2_customCSRs_csrs_0_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_2_customCSRs_csrs_0_value, // @[LazyRoCC.scala:78:14]
input io_ptw_2_customCSRs_csrs_1_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_2_customCSRs_csrs_1_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_2_customCSRs_csrs_1_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_2_customCSRs_csrs_1_value, // @[LazyRoCC.scala:78:14]
input io_ptw_2_customCSRs_csrs_2_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_2_customCSRs_csrs_2_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_2_customCSRs_csrs_2_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_2_customCSRs_csrs_2_value, // @[LazyRoCC.scala:78:14]
input io_ptw_2_customCSRs_csrs_3_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_2_customCSRs_csrs_3_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_2_customCSRs_csrs_3_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_2_customCSRs_csrs_3_value, // @[LazyRoCC.scala:78:14]
input io_ptw_3_req_ready, // @[LazyRoCC.scala:78:14]
output io_ptw_3_req_valid, // @[LazyRoCC.scala:78:14]
output [26:0] io_ptw_3_req_bits_bits_addr, // @[LazyRoCC.scala:78:14]
output io_ptw_3_req_bits_bits_need_gpa, // @[LazyRoCC.scala:78:14]
input io_ptw_3_resp_valid, // @[LazyRoCC.scala:78:14]
input io_ptw_3_resp_bits_ae_ptw, // @[LazyRoCC.scala:78:14]
input io_ptw_3_resp_bits_ae_final, // @[LazyRoCC.scala:78:14]
input io_ptw_3_resp_bits_pf, // @[LazyRoCC.scala:78:14]
input io_ptw_3_resp_bits_gf, // @[LazyRoCC.scala:78:14]
input io_ptw_3_resp_bits_hr, // @[LazyRoCC.scala:78:14]
input io_ptw_3_resp_bits_hw, // @[LazyRoCC.scala:78:14]
input io_ptw_3_resp_bits_hx, // @[LazyRoCC.scala:78:14]
input [9:0] io_ptw_3_resp_bits_pte_reserved_for_future, // @[LazyRoCC.scala:78:14]
input [43:0] io_ptw_3_resp_bits_pte_ppn, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_3_resp_bits_pte_reserved_for_software, // @[LazyRoCC.scala:78:14]
input io_ptw_3_resp_bits_pte_d, // @[LazyRoCC.scala:78:14]
input io_ptw_3_resp_bits_pte_a, // @[LazyRoCC.scala:78:14]
input io_ptw_3_resp_bits_pte_g, // @[LazyRoCC.scala:78:14]
input io_ptw_3_resp_bits_pte_u, // @[LazyRoCC.scala:78:14]
input io_ptw_3_resp_bits_pte_x, // @[LazyRoCC.scala:78:14]
input io_ptw_3_resp_bits_pte_w, // @[LazyRoCC.scala:78:14]
input io_ptw_3_resp_bits_pte_r, // @[LazyRoCC.scala:78:14]
input io_ptw_3_resp_bits_pte_v, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_3_resp_bits_level, // @[LazyRoCC.scala:78:14]
input io_ptw_3_resp_bits_homogeneous, // @[LazyRoCC.scala:78:14]
input io_ptw_3_resp_bits_gpa_valid, // @[LazyRoCC.scala:78:14]
input [38:0] io_ptw_3_resp_bits_gpa_bits, // @[LazyRoCC.scala:78:14]
input io_ptw_3_resp_bits_gpa_is_pte, // @[LazyRoCC.scala:78:14]
input [3:0] io_ptw_3_ptbr_mode, // @[LazyRoCC.scala:78:14]
input [43:0] io_ptw_3_ptbr_ppn, // @[LazyRoCC.scala:78:14]
input io_ptw_3_status_debug, // @[LazyRoCC.scala:78:14]
input io_ptw_3_status_cease, // @[LazyRoCC.scala:78:14]
input io_ptw_3_status_wfi, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_3_status_isa, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_3_status_dprv, // @[LazyRoCC.scala:78:14]
input io_ptw_3_status_dv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_3_status_prv, // @[LazyRoCC.scala:78:14]
input io_ptw_3_status_v, // @[LazyRoCC.scala:78:14]
input io_ptw_3_status_mpv, // @[LazyRoCC.scala:78:14]
input io_ptw_3_status_gva, // @[LazyRoCC.scala:78:14]
input io_ptw_3_status_tsr, // @[LazyRoCC.scala:78:14]
input io_ptw_3_status_tw, // @[LazyRoCC.scala:78:14]
input io_ptw_3_status_tvm, // @[LazyRoCC.scala:78:14]
input io_ptw_3_status_mxr, // @[LazyRoCC.scala:78:14]
input io_ptw_3_status_sum, // @[LazyRoCC.scala:78:14]
input io_ptw_3_status_mprv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_3_status_fs, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_3_status_mpp, // @[LazyRoCC.scala:78:14]
input io_ptw_3_status_spp, // @[LazyRoCC.scala:78:14]
input io_ptw_3_status_mpie, // @[LazyRoCC.scala:78:14]
input io_ptw_3_status_spie, // @[LazyRoCC.scala:78:14]
input io_ptw_3_status_mie, // @[LazyRoCC.scala:78:14]
input io_ptw_3_status_sie, // @[LazyRoCC.scala:78:14]
input io_ptw_3_hstatus_spvp, // @[LazyRoCC.scala:78:14]
input io_ptw_3_hstatus_spv, // @[LazyRoCC.scala:78:14]
input io_ptw_3_hstatus_gva, // @[LazyRoCC.scala:78:14]
input io_ptw_3_gstatus_debug, // @[LazyRoCC.scala:78:14]
input io_ptw_3_gstatus_cease, // @[LazyRoCC.scala:78:14]
input io_ptw_3_gstatus_wfi, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_3_gstatus_isa, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_3_gstatus_dprv, // @[LazyRoCC.scala:78:14]
input io_ptw_3_gstatus_dv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_3_gstatus_prv, // @[LazyRoCC.scala:78:14]
input io_ptw_3_gstatus_v, // @[LazyRoCC.scala:78:14]
input [22:0] io_ptw_3_gstatus_zero2, // @[LazyRoCC.scala:78:14]
input io_ptw_3_gstatus_mpv, // @[LazyRoCC.scala:78:14]
input io_ptw_3_gstatus_gva, // @[LazyRoCC.scala:78:14]
input io_ptw_3_gstatus_mbe, // @[LazyRoCC.scala:78:14]
input io_ptw_3_gstatus_sbe, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_3_gstatus_sxl, // @[LazyRoCC.scala:78:14]
input [7:0] io_ptw_3_gstatus_zero1, // @[LazyRoCC.scala:78:14]
input io_ptw_3_gstatus_tsr, // @[LazyRoCC.scala:78:14]
input io_ptw_3_gstatus_tw, // @[LazyRoCC.scala:78:14]
input io_ptw_3_gstatus_tvm, // @[LazyRoCC.scala:78:14]
input io_ptw_3_gstatus_mxr, // @[LazyRoCC.scala:78:14]
input io_ptw_3_gstatus_sum, // @[LazyRoCC.scala:78:14]
input io_ptw_3_gstatus_mprv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_3_gstatus_fs, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_3_gstatus_mpp, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_3_gstatus_vs, // @[LazyRoCC.scala:78:14]
input io_ptw_3_gstatus_spp, // @[LazyRoCC.scala:78:14]
input io_ptw_3_gstatus_mpie, // @[LazyRoCC.scala:78:14]
input io_ptw_3_gstatus_ube, // @[LazyRoCC.scala:78:14]
input io_ptw_3_gstatus_spie, // @[LazyRoCC.scala:78:14]
input io_ptw_3_gstatus_upie, // @[LazyRoCC.scala:78:14]
input io_ptw_3_gstatus_mie, // @[LazyRoCC.scala:78:14]
input io_ptw_3_gstatus_hie, // @[LazyRoCC.scala:78:14]
input io_ptw_3_gstatus_sie, // @[LazyRoCC.scala:78:14]
input io_ptw_3_gstatus_uie, // @[LazyRoCC.scala:78:14]
input io_ptw_3_pmp_0_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_3_pmp_0_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_3_pmp_0_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_3_pmp_0_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_3_pmp_0_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_3_pmp_0_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_3_pmp_0_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_3_pmp_1_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_3_pmp_1_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_3_pmp_1_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_3_pmp_1_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_3_pmp_1_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_3_pmp_1_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_3_pmp_1_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_3_pmp_2_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_3_pmp_2_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_3_pmp_2_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_3_pmp_2_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_3_pmp_2_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_3_pmp_2_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_3_pmp_2_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_3_pmp_3_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_3_pmp_3_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_3_pmp_3_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_3_pmp_3_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_3_pmp_3_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_3_pmp_3_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_3_pmp_3_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_3_pmp_4_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_3_pmp_4_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_3_pmp_4_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_3_pmp_4_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_3_pmp_4_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_3_pmp_4_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_3_pmp_4_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_3_pmp_5_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_3_pmp_5_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_3_pmp_5_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_3_pmp_5_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_3_pmp_5_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_3_pmp_5_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_3_pmp_5_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_3_pmp_6_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_3_pmp_6_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_3_pmp_6_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_3_pmp_6_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_3_pmp_6_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_3_pmp_6_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_3_pmp_6_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_3_pmp_7_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_3_pmp_7_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_3_pmp_7_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_3_pmp_7_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_3_pmp_7_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_3_pmp_7_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_3_pmp_7_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_3_customCSRs_csrs_0_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_3_customCSRs_csrs_0_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_3_customCSRs_csrs_0_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_3_customCSRs_csrs_0_value, // @[LazyRoCC.scala:78:14]
input io_ptw_3_customCSRs_csrs_1_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_3_customCSRs_csrs_1_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_3_customCSRs_csrs_1_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_3_customCSRs_csrs_1_value, // @[LazyRoCC.scala:78:14]
input io_ptw_3_customCSRs_csrs_2_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_3_customCSRs_csrs_2_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_3_customCSRs_csrs_2_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_3_customCSRs_csrs_2_value, // @[LazyRoCC.scala:78:14]
input io_ptw_3_customCSRs_csrs_3_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_3_customCSRs_csrs_3_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_3_customCSRs_csrs_3_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_3_customCSRs_csrs_3_value, // @[LazyRoCC.scala:78:14]
input io_ptw_4_req_ready, // @[LazyRoCC.scala:78:14]
output io_ptw_4_req_valid, // @[LazyRoCC.scala:78:14]
output [26:0] io_ptw_4_req_bits_bits_addr, // @[LazyRoCC.scala:78:14]
output io_ptw_4_req_bits_bits_need_gpa, // @[LazyRoCC.scala:78:14]
input io_ptw_4_resp_valid, // @[LazyRoCC.scala:78:14]
input io_ptw_4_resp_bits_ae_ptw, // @[LazyRoCC.scala:78:14]
input io_ptw_4_resp_bits_ae_final, // @[LazyRoCC.scala:78:14]
input io_ptw_4_resp_bits_pf, // @[LazyRoCC.scala:78:14]
input io_ptw_4_resp_bits_gf, // @[LazyRoCC.scala:78:14]
input io_ptw_4_resp_bits_hr, // @[LazyRoCC.scala:78:14]
input io_ptw_4_resp_bits_hw, // @[LazyRoCC.scala:78:14]
input io_ptw_4_resp_bits_hx, // @[LazyRoCC.scala:78:14]
input [9:0] io_ptw_4_resp_bits_pte_reserved_for_future, // @[LazyRoCC.scala:78:14]
input [43:0] io_ptw_4_resp_bits_pte_ppn, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_4_resp_bits_pte_reserved_for_software, // @[LazyRoCC.scala:78:14]
input io_ptw_4_resp_bits_pte_d, // @[LazyRoCC.scala:78:14]
input io_ptw_4_resp_bits_pte_a, // @[LazyRoCC.scala:78:14]
input io_ptw_4_resp_bits_pte_g, // @[LazyRoCC.scala:78:14]
input io_ptw_4_resp_bits_pte_u, // @[LazyRoCC.scala:78:14]
input io_ptw_4_resp_bits_pte_x, // @[LazyRoCC.scala:78:14]
input io_ptw_4_resp_bits_pte_w, // @[LazyRoCC.scala:78:14]
input io_ptw_4_resp_bits_pte_r, // @[LazyRoCC.scala:78:14]
input io_ptw_4_resp_bits_pte_v, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_4_resp_bits_level, // @[LazyRoCC.scala:78:14]
input io_ptw_4_resp_bits_homogeneous, // @[LazyRoCC.scala:78:14]
input io_ptw_4_resp_bits_gpa_valid, // @[LazyRoCC.scala:78:14]
input [38:0] io_ptw_4_resp_bits_gpa_bits, // @[LazyRoCC.scala:78:14]
input io_ptw_4_resp_bits_gpa_is_pte, // @[LazyRoCC.scala:78:14]
input [3:0] io_ptw_4_ptbr_mode, // @[LazyRoCC.scala:78:14]
input [43:0] io_ptw_4_ptbr_ppn, // @[LazyRoCC.scala:78:14]
input io_ptw_4_status_debug, // @[LazyRoCC.scala:78:14]
input io_ptw_4_status_cease, // @[LazyRoCC.scala:78:14]
input io_ptw_4_status_wfi, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_4_status_isa, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_4_status_dprv, // @[LazyRoCC.scala:78:14]
input io_ptw_4_status_dv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_4_status_prv, // @[LazyRoCC.scala:78:14]
input io_ptw_4_status_v, // @[LazyRoCC.scala:78:14]
input io_ptw_4_status_mpv, // @[LazyRoCC.scala:78:14]
input io_ptw_4_status_gva, // @[LazyRoCC.scala:78:14]
input io_ptw_4_status_tsr, // @[LazyRoCC.scala:78:14]
input io_ptw_4_status_tw, // @[LazyRoCC.scala:78:14]
input io_ptw_4_status_tvm, // @[LazyRoCC.scala:78:14]
input io_ptw_4_status_mxr, // @[LazyRoCC.scala:78:14]
input io_ptw_4_status_sum, // @[LazyRoCC.scala:78:14]
input io_ptw_4_status_mprv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_4_status_fs, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_4_status_mpp, // @[LazyRoCC.scala:78:14]
input io_ptw_4_status_spp, // @[LazyRoCC.scala:78:14]
input io_ptw_4_status_mpie, // @[LazyRoCC.scala:78:14]
input io_ptw_4_status_spie, // @[LazyRoCC.scala:78:14]
input io_ptw_4_status_mie, // @[LazyRoCC.scala:78:14]
input io_ptw_4_status_sie, // @[LazyRoCC.scala:78:14]
input io_ptw_4_hstatus_spvp, // @[LazyRoCC.scala:78:14]
input io_ptw_4_hstatus_spv, // @[LazyRoCC.scala:78:14]
input io_ptw_4_hstatus_gva, // @[LazyRoCC.scala:78:14]
input io_ptw_4_gstatus_debug, // @[LazyRoCC.scala:78:14]
input io_ptw_4_gstatus_cease, // @[LazyRoCC.scala:78:14]
input io_ptw_4_gstatus_wfi, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_4_gstatus_isa, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_4_gstatus_dprv, // @[LazyRoCC.scala:78:14]
input io_ptw_4_gstatus_dv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_4_gstatus_prv, // @[LazyRoCC.scala:78:14]
input io_ptw_4_gstatus_v, // @[LazyRoCC.scala:78:14]
input [22:0] io_ptw_4_gstatus_zero2, // @[LazyRoCC.scala:78:14]
input io_ptw_4_gstatus_mpv, // @[LazyRoCC.scala:78:14]
input io_ptw_4_gstatus_gva, // @[LazyRoCC.scala:78:14]
input io_ptw_4_gstatus_mbe, // @[LazyRoCC.scala:78:14]
input io_ptw_4_gstatus_sbe, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_4_gstatus_sxl, // @[LazyRoCC.scala:78:14]
input [7:0] io_ptw_4_gstatus_zero1, // @[LazyRoCC.scala:78:14]
input io_ptw_4_gstatus_tsr, // @[LazyRoCC.scala:78:14]
input io_ptw_4_gstatus_tw, // @[LazyRoCC.scala:78:14]
input io_ptw_4_gstatus_tvm, // @[LazyRoCC.scala:78:14]
input io_ptw_4_gstatus_mxr, // @[LazyRoCC.scala:78:14]
input io_ptw_4_gstatus_sum, // @[LazyRoCC.scala:78:14]
input io_ptw_4_gstatus_mprv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_4_gstatus_fs, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_4_gstatus_mpp, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_4_gstatus_vs, // @[LazyRoCC.scala:78:14]
input io_ptw_4_gstatus_spp, // @[LazyRoCC.scala:78:14]
input io_ptw_4_gstatus_mpie, // @[LazyRoCC.scala:78:14]
input io_ptw_4_gstatus_ube, // @[LazyRoCC.scala:78:14]
input io_ptw_4_gstatus_spie, // @[LazyRoCC.scala:78:14]
input io_ptw_4_gstatus_upie, // @[LazyRoCC.scala:78:14]
input io_ptw_4_gstatus_mie, // @[LazyRoCC.scala:78:14]
input io_ptw_4_gstatus_hie, // @[LazyRoCC.scala:78:14]
input io_ptw_4_gstatus_sie, // @[LazyRoCC.scala:78:14]
input io_ptw_4_gstatus_uie, // @[LazyRoCC.scala:78:14]
input io_ptw_4_pmp_0_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_4_pmp_0_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_4_pmp_0_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_4_pmp_0_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_4_pmp_0_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_4_pmp_0_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_4_pmp_0_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_4_pmp_1_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_4_pmp_1_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_4_pmp_1_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_4_pmp_1_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_4_pmp_1_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_4_pmp_1_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_4_pmp_1_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_4_pmp_2_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_4_pmp_2_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_4_pmp_2_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_4_pmp_2_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_4_pmp_2_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_4_pmp_2_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_4_pmp_2_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_4_pmp_3_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_4_pmp_3_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_4_pmp_3_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_4_pmp_3_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_4_pmp_3_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_4_pmp_3_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_4_pmp_3_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_4_pmp_4_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_4_pmp_4_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_4_pmp_4_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_4_pmp_4_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_4_pmp_4_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_4_pmp_4_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_4_pmp_4_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_4_pmp_5_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_4_pmp_5_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_4_pmp_5_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_4_pmp_5_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_4_pmp_5_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_4_pmp_5_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_4_pmp_5_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_4_pmp_6_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_4_pmp_6_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_4_pmp_6_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_4_pmp_6_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_4_pmp_6_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_4_pmp_6_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_4_pmp_6_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_4_pmp_7_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_4_pmp_7_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_4_pmp_7_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_4_pmp_7_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_4_pmp_7_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_4_pmp_7_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_4_pmp_7_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_4_customCSRs_csrs_0_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_4_customCSRs_csrs_0_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_4_customCSRs_csrs_0_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_4_customCSRs_csrs_0_value, // @[LazyRoCC.scala:78:14]
input io_ptw_4_customCSRs_csrs_1_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_4_customCSRs_csrs_1_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_4_customCSRs_csrs_1_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_4_customCSRs_csrs_1_value, // @[LazyRoCC.scala:78:14]
input io_ptw_4_customCSRs_csrs_2_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_4_customCSRs_csrs_2_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_4_customCSRs_csrs_2_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_4_customCSRs_csrs_2_value, // @[LazyRoCC.scala:78:14]
input io_ptw_4_customCSRs_csrs_3_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_4_customCSRs_csrs_3_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_4_customCSRs_csrs_3_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_4_customCSRs_csrs_3_value, // @[LazyRoCC.scala:78:14]
input io_ptw_5_req_ready, // @[LazyRoCC.scala:78:14]
output io_ptw_5_req_valid, // @[LazyRoCC.scala:78:14]
output [26:0] io_ptw_5_req_bits_bits_addr, // @[LazyRoCC.scala:78:14]
output io_ptw_5_req_bits_bits_need_gpa, // @[LazyRoCC.scala:78:14]
input io_ptw_5_resp_valid, // @[LazyRoCC.scala:78:14]
input io_ptw_5_resp_bits_ae_ptw, // @[LazyRoCC.scala:78:14]
input io_ptw_5_resp_bits_ae_final, // @[LazyRoCC.scala:78:14]
input io_ptw_5_resp_bits_pf, // @[LazyRoCC.scala:78:14]
input io_ptw_5_resp_bits_gf, // @[LazyRoCC.scala:78:14]
input io_ptw_5_resp_bits_hr, // @[LazyRoCC.scala:78:14]
input io_ptw_5_resp_bits_hw, // @[LazyRoCC.scala:78:14]
input io_ptw_5_resp_bits_hx, // @[LazyRoCC.scala:78:14]
input [9:0] io_ptw_5_resp_bits_pte_reserved_for_future, // @[LazyRoCC.scala:78:14]
input [43:0] io_ptw_5_resp_bits_pte_ppn, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_5_resp_bits_pte_reserved_for_software, // @[LazyRoCC.scala:78:14]
input io_ptw_5_resp_bits_pte_d, // @[LazyRoCC.scala:78:14]
input io_ptw_5_resp_bits_pte_a, // @[LazyRoCC.scala:78:14]
input io_ptw_5_resp_bits_pte_g, // @[LazyRoCC.scala:78:14]
input io_ptw_5_resp_bits_pte_u, // @[LazyRoCC.scala:78:14]
input io_ptw_5_resp_bits_pte_x, // @[LazyRoCC.scala:78:14]
input io_ptw_5_resp_bits_pte_w, // @[LazyRoCC.scala:78:14]
input io_ptw_5_resp_bits_pte_r, // @[LazyRoCC.scala:78:14]
input io_ptw_5_resp_bits_pte_v, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_5_resp_bits_level, // @[LazyRoCC.scala:78:14]
input io_ptw_5_resp_bits_homogeneous, // @[LazyRoCC.scala:78:14]
input io_ptw_5_resp_bits_gpa_valid, // @[LazyRoCC.scala:78:14]
input [38:0] io_ptw_5_resp_bits_gpa_bits, // @[LazyRoCC.scala:78:14]
input io_ptw_5_resp_bits_gpa_is_pte, // @[LazyRoCC.scala:78:14]
input [3:0] io_ptw_5_ptbr_mode, // @[LazyRoCC.scala:78:14]
input [43:0] io_ptw_5_ptbr_ppn, // @[LazyRoCC.scala:78:14]
input io_ptw_5_status_debug, // @[LazyRoCC.scala:78:14]
input io_ptw_5_status_cease, // @[LazyRoCC.scala:78:14]
input io_ptw_5_status_wfi, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_5_status_isa, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_5_status_dprv, // @[LazyRoCC.scala:78:14]
input io_ptw_5_status_dv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_5_status_prv, // @[LazyRoCC.scala:78:14]
input io_ptw_5_status_v, // @[LazyRoCC.scala:78:14]
input io_ptw_5_status_mpv, // @[LazyRoCC.scala:78:14]
input io_ptw_5_status_gva, // @[LazyRoCC.scala:78:14]
input io_ptw_5_status_tsr, // @[LazyRoCC.scala:78:14]
input io_ptw_5_status_tw, // @[LazyRoCC.scala:78:14]
input io_ptw_5_status_tvm, // @[LazyRoCC.scala:78:14]
input io_ptw_5_status_mxr, // @[LazyRoCC.scala:78:14]
input io_ptw_5_status_sum, // @[LazyRoCC.scala:78:14]
input io_ptw_5_status_mprv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_5_status_fs, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_5_status_mpp, // @[LazyRoCC.scala:78:14]
input io_ptw_5_status_spp, // @[LazyRoCC.scala:78:14]
input io_ptw_5_status_mpie, // @[LazyRoCC.scala:78:14]
input io_ptw_5_status_spie, // @[LazyRoCC.scala:78:14]
input io_ptw_5_status_mie, // @[LazyRoCC.scala:78:14]
input io_ptw_5_status_sie, // @[LazyRoCC.scala:78:14]
input io_ptw_5_hstatus_spvp, // @[LazyRoCC.scala:78:14]
input io_ptw_5_hstatus_spv, // @[LazyRoCC.scala:78:14]
input io_ptw_5_hstatus_gva, // @[LazyRoCC.scala:78:14]
input io_ptw_5_gstatus_debug, // @[LazyRoCC.scala:78:14]
input io_ptw_5_gstatus_cease, // @[LazyRoCC.scala:78:14]
input io_ptw_5_gstatus_wfi, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_5_gstatus_isa, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_5_gstatus_dprv, // @[LazyRoCC.scala:78:14]
input io_ptw_5_gstatus_dv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_5_gstatus_prv, // @[LazyRoCC.scala:78:14]
input io_ptw_5_gstatus_v, // @[LazyRoCC.scala:78:14]
input [22:0] io_ptw_5_gstatus_zero2, // @[LazyRoCC.scala:78:14]
input io_ptw_5_gstatus_mpv, // @[LazyRoCC.scala:78:14]
input io_ptw_5_gstatus_gva, // @[LazyRoCC.scala:78:14]
input io_ptw_5_gstatus_mbe, // @[LazyRoCC.scala:78:14]
input io_ptw_5_gstatus_sbe, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_5_gstatus_sxl, // @[LazyRoCC.scala:78:14]
input [7:0] io_ptw_5_gstatus_zero1, // @[LazyRoCC.scala:78:14]
input io_ptw_5_gstatus_tsr, // @[LazyRoCC.scala:78:14]
input io_ptw_5_gstatus_tw, // @[LazyRoCC.scala:78:14]
input io_ptw_5_gstatus_tvm, // @[LazyRoCC.scala:78:14]
input io_ptw_5_gstatus_mxr, // @[LazyRoCC.scala:78:14]
input io_ptw_5_gstatus_sum, // @[LazyRoCC.scala:78:14]
input io_ptw_5_gstatus_mprv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_5_gstatus_fs, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_5_gstatus_mpp, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_5_gstatus_vs, // @[LazyRoCC.scala:78:14]
input io_ptw_5_gstatus_spp, // @[LazyRoCC.scala:78:14]
input io_ptw_5_gstatus_mpie, // @[LazyRoCC.scala:78:14]
input io_ptw_5_gstatus_ube, // @[LazyRoCC.scala:78:14]
input io_ptw_5_gstatus_spie, // @[LazyRoCC.scala:78:14]
input io_ptw_5_gstatus_upie, // @[LazyRoCC.scala:78:14]
input io_ptw_5_gstatus_mie, // @[LazyRoCC.scala:78:14]
input io_ptw_5_gstatus_hie, // @[LazyRoCC.scala:78:14]
input io_ptw_5_gstatus_sie, // @[LazyRoCC.scala:78:14]
input io_ptw_5_gstatus_uie, // @[LazyRoCC.scala:78:14]
input io_ptw_5_pmp_0_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_5_pmp_0_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_5_pmp_0_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_5_pmp_0_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_5_pmp_0_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_5_pmp_0_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_5_pmp_0_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_5_pmp_1_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_5_pmp_1_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_5_pmp_1_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_5_pmp_1_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_5_pmp_1_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_5_pmp_1_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_5_pmp_1_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_5_pmp_2_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_5_pmp_2_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_5_pmp_2_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_5_pmp_2_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_5_pmp_2_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_5_pmp_2_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_5_pmp_2_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_5_pmp_3_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_5_pmp_3_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_5_pmp_3_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_5_pmp_3_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_5_pmp_3_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_5_pmp_3_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_5_pmp_3_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_5_pmp_4_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_5_pmp_4_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_5_pmp_4_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_5_pmp_4_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_5_pmp_4_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_5_pmp_4_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_5_pmp_4_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_5_pmp_5_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_5_pmp_5_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_5_pmp_5_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_5_pmp_5_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_5_pmp_5_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_5_pmp_5_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_5_pmp_5_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_5_pmp_6_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_5_pmp_6_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_5_pmp_6_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_5_pmp_6_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_5_pmp_6_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_5_pmp_6_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_5_pmp_6_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_5_pmp_7_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_5_pmp_7_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_5_pmp_7_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_5_pmp_7_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_5_pmp_7_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_5_pmp_7_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_5_pmp_7_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_5_customCSRs_csrs_0_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_5_customCSRs_csrs_0_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_5_customCSRs_csrs_0_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_5_customCSRs_csrs_0_value, // @[LazyRoCC.scala:78:14]
input io_ptw_5_customCSRs_csrs_1_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_5_customCSRs_csrs_1_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_5_customCSRs_csrs_1_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_5_customCSRs_csrs_1_value, // @[LazyRoCC.scala:78:14]
input io_ptw_5_customCSRs_csrs_2_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_5_customCSRs_csrs_2_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_5_customCSRs_csrs_2_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_5_customCSRs_csrs_2_value, // @[LazyRoCC.scala:78:14]
input io_ptw_5_customCSRs_csrs_3_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_5_customCSRs_csrs_3_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_5_customCSRs_csrs_3_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_5_customCSRs_csrs_3_value, // @[LazyRoCC.scala:78:14]
input io_ptw_6_req_ready, // @[LazyRoCC.scala:78:14]
output io_ptw_6_req_valid, // @[LazyRoCC.scala:78:14]
output [26:0] io_ptw_6_req_bits_bits_addr, // @[LazyRoCC.scala:78:14]
output io_ptw_6_req_bits_bits_need_gpa, // @[LazyRoCC.scala:78:14]
input io_ptw_6_resp_valid, // @[LazyRoCC.scala:78:14]
input io_ptw_6_resp_bits_ae_ptw, // @[LazyRoCC.scala:78:14]
input io_ptw_6_resp_bits_ae_final, // @[LazyRoCC.scala:78:14]
input io_ptw_6_resp_bits_pf, // @[LazyRoCC.scala:78:14]
input io_ptw_6_resp_bits_gf, // @[LazyRoCC.scala:78:14]
input io_ptw_6_resp_bits_hr, // @[LazyRoCC.scala:78:14]
input io_ptw_6_resp_bits_hw, // @[LazyRoCC.scala:78:14]
input io_ptw_6_resp_bits_hx, // @[LazyRoCC.scala:78:14]
input [9:0] io_ptw_6_resp_bits_pte_reserved_for_future, // @[LazyRoCC.scala:78:14]
input [43:0] io_ptw_6_resp_bits_pte_ppn, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_6_resp_bits_pte_reserved_for_software, // @[LazyRoCC.scala:78:14]
input io_ptw_6_resp_bits_pte_d, // @[LazyRoCC.scala:78:14]
input io_ptw_6_resp_bits_pte_a, // @[LazyRoCC.scala:78:14]
input io_ptw_6_resp_bits_pte_g, // @[LazyRoCC.scala:78:14]
input io_ptw_6_resp_bits_pte_u, // @[LazyRoCC.scala:78:14]
input io_ptw_6_resp_bits_pte_x, // @[LazyRoCC.scala:78:14]
input io_ptw_6_resp_bits_pte_w, // @[LazyRoCC.scala:78:14]
input io_ptw_6_resp_bits_pte_r, // @[LazyRoCC.scala:78:14]
input io_ptw_6_resp_bits_pte_v, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_6_resp_bits_level, // @[LazyRoCC.scala:78:14]
input io_ptw_6_resp_bits_homogeneous, // @[LazyRoCC.scala:78:14]
input io_ptw_6_resp_bits_gpa_valid, // @[LazyRoCC.scala:78:14]
input [38:0] io_ptw_6_resp_bits_gpa_bits, // @[LazyRoCC.scala:78:14]
input io_ptw_6_resp_bits_gpa_is_pte, // @[LazyRoCC.scala:78:14]
input [3:0] io_ptw_6_ptbr_mode, // @[LazyRoCC.scala:78:14]
input [43:0] io_ptw_6_ptbr_ppn, // @[LazyRoCC.scala:78:14]
input io_ptw_6_status_debug, // @[LazyRoCC.scala:78:14]
input io_ptw_6_status_cease, // @[LazyRoCC.scala:78:14]
input io_ptw_6_status_wfi, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_6_status_isa, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_6_status_dprv, // @[LazyRoCC.scala:78:14]
input io_ptw_6_status_dv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_6_status_prv, // @[LazyRoCC.scala:78:14]
input io_ptw_6_status_v, // @[LazyRoCC.scala:78:14]
input io_ptw_6_status_mpv, // @[LazyRoCC.scala:78:14]
input io_ptw_6_status_gva, // @[LazyRoCC.scala:78:14]
input io_ptw_6_status_tsr, // @[LazyRoCC.scala:78:14]
input io_ptw_6_status_tw, // @[LazyRoCC.scala:78:14]
input io_ptw_6_status_tvm, // @[LazyRoCC.scala:78:14]
input io_ptw_6_status_mxr, // @[LazyRoCC.scala:78:14]
input io_ptw_6_status_sum, // @[LazyRoCC.scala:78:14]
input io_ptw_6_status_mprv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_6_status_fs, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_6_status_mpp, // @[LazyRoCC.scala:78:14]
input io_ptw_6_status_spp, // @[LazyRoCC.scala:78:14]
input io_ptw_6_status_mpie, // @[LazyRoCC.scala:78:14]
input io_ptw_6_status_spie, // @[LazyRoCC.scala:78:14]
input io_ptw_6_status_mie, // @[LazyRoCC.scala:78:14]
input io_ptw_6_status_sie, // @[LazyRoCC.scala:78:14]
input io_ptw_6_hstatus_spvp, // @[LazyRoCC.scala:78:14]
input io_ptw_6_hstatus_spv, // @[LazyRoCC.scala:78:14]
input io_ptw_6_hstatus_gva, // @[LazyRoCC.scala:78:14]
input io_ptw_6_gstatus_debug, // @[LazyRoCC.scala:78:14]
input io_ptw_6_gstatus_cease, // @[LazyRoCC.scala:78:14]
input io_ptw_6_gstatus_wfi, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_6_gstatus_isa, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_6_gstatus_dprv, // @[LazyRoCC.scala:78:14]
input io_ptw_6_gstatus_dv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_6_gstatus_prv, // @[LazyRoCC.scala:78:14]
input io_ptw_6_gstatus_v, // @[LazyRoCC.scala:78:14]
input [22:0] io_ptw_6_gstatus_zero2, // @[LazyRoCC.scala:78:14]
input io_ptw_6_gstatus_mpv, // @[LazyRoCC.scala:78:14]
input io_ptw_6_gstatus_gva, // @[LazyRoCC.scala:78:14]
input io_ptw_6_gstatus_mbe, // @[LazyRoCC.scala:78:14]
input io_ptw_6_gstatus_sbe, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_6_gstatus_sxl, // @[LazyRoCC.scala:78:14]
input [7:0] io_ptw_6_gstatus_zero1, // @[LazyRoCC.scala:78:14]
input io_ptw_6_gstatus_tsr, // @[LazyRoCC.scala:78:14]
input io_ptw_6_gstatus_tw, // @[LazyRoCC.scala:78:14]
input io_ptw_6_gstatus_tvm, // @[LazyRoCC.scala:78:14]
input io_ptw_6_gstatus_mxr, // @[LazyRoCC.scala:78:14]
input io_ptw_6_gstatus_sum, // @[LazyRoCC.scala:78:14]
input io_ptw_6_gstatus_mprv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_6_gstatus_fs, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_6_gstatus_mpp, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_6_gstatus_vs, // @[LazyRoCC.scala:78:14]
input io_ptw_6_gstatus_spp, // @[LazyRoCC.scala:78:14]
input io_ptw_6_gstatus_mpie, // @[LazyRoCC.scala:78:14]
input io_ptw_6_gstatus_ube, // @[LazyRoCC.scala:78:14]
input io_ptw_6_gstatus_spie, // @[LazyRoCC.scala:78:14]
input io_ptw_6_gstatus_upie, // @[LazyRoCC.scala:78:14]
input io_ptw_6_gstatus_mie, // @[LazyRoCC.scala:78:14]
input io_ptw_6_gstatus_hie, // @[LazyRoCC.scala:78:14]
input io_ptw_6_gstatus_sie, // @[LazyRoCC.scala:78:14]
input io_ptw_6_gstatus_uie, // @[LazyRoCC.scala:78:14]
input io_ptw_6_pmp_0_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_6_pmp_0_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_6_pmp_0_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_6_pmp_0_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_6_pmp_0_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_6_pmp_0_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_6_pmp_0_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_6_pmp_1_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_6_pmp_1_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_6_pmp_1_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_6_pmp_1_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_6_pmp_1_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_6_pmp_1_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_6_pmp_1_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_6_pmp_2_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_6_pmp_2_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_6_pmp_2_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_6_pmp_2_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_6_pmp_2_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_6_pmp_2_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_6_pmp_2_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_6_pmp_3_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_6_pmp_3_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_6_pmp_3_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_6_pmp_3_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_6_pmp_3_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_6_pmp_3_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_6_pmp_3_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_6_pmp_4_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_6_pmp_4_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_6_pmp_4_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_6_pmp_4_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_6_pmp_4_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_6_pmp_4_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_6_pmp_4_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_6_pmp_5_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_6_pmp_5_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_6_pmp_5_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_6_pmp_5_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_6_pmp_5_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_6_pmp_5_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_6_pmp_5_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_6_pmp_6_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_6_pmp_6_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_6_pmp_6_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_6_pmp_6_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_6_pmp_6_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_6_pmp_6_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_6_pmp_6_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_6_pmp_7_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_6_pmp_7_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_6_pmp_7_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_6_pmp_7_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_6_pmp_7_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_6_pmp_7_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_6_pmp_7_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_6_customCSRs_csrs_0_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_6_customCSRs_csrs_0_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_6_customCSRs_csrs_0_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_6_customCSRs_csrs_0_value, // @[LazyRoCC.scala:78:14]
input io_ptw_6_customCSRs_csrs_1_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_6_customCSRs_csrs_1_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_6_customCSRs_csrs_1_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_6_customCSRs_csrs_1_value, // @[LazyRoCC.scala:78:14]
input io_ptw_6_customCSRs_csrs_2_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_6_customCSRs_csrs_2_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_6_customCSRs_csrs_2_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_6_customCSRs_csrs_2_value, // @[LazyRoCC.scala:78:14]
input io_ptw_6_customCSRs_csrs_3_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_6_customCSRs_csrs_3_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_6_customCSRs_csrs_3_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_6_customCSRs_csrs_3_value, // @[LazyRoCC.scala:78:14]
input io_ptw_7_req_ready, // @[LazyRoCC.scala:78:14]
output io_ptw_7_req_valid, // @[LazyRoCC.scala:78:14]
output [26:0] io_ptw_7_req_bits_bits_addr, // @[LazyRoCC.scala:78:14]
output io_ptw_7_req_bits_bits_need_gpa, // @[LazyRoCC.scala:78:14]
input io_ptw_7_resp_valid, // @[LazyRoCC.scala:78:14]
input io_ptw_7_resp_bits_ae_ptw, // @[LazyRoCC.scala:78:14]
input io_ptw_7_resp_bits_ae_final, // @[LazyRoCC.scala:78:14]
input io_ptw_7_resp_bits_pf, // @[LazyRoCC.scala:78:14]
input io_ptw_7_resp_bits_gf, // @[LazyRoCC.scala:78:14]
input io_ptw_7_resp_bits_hr, // @[LazyRoCC.scala:78:14]
input io_ptw_7_resp_bits_hw, // @[LazyRoCC.scala:78:14]
input io_ptw_7_resp_bits_hx, // @[LazyRoCC.scala:78:14]
input [9:0] io_ptw_7_resp_bits_pte_reserved_for_future, // @[LazyRoCC.scala:78:14]
input [43:0] io_ptw_7_resp_bits_pte_ppn, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_7_resp_bits_pte_reserved_for_software, // @[LazyRoCC.scala:78:14]
input io_ptw_7_resp_bits_pte_d, // @[LazyRoCC.scala:78:14]
input io_ptw_7_resp_bits_pte_a, // @[LazyRoCC.scala:78:14]
input io_ptw_7_resp_bits_pte_g, // @[LazyRoCC.scala:78:14]
input io_ptw_7_resp_bits_pte_u, // @[LazyRoCC.scala:78:14]
input io_ptw_7_resp_bits_pte_x, // @[LazyRoCC.scala:78:14]
input io_ptw_7_resp_bits_pte_w, // @[LazyRoCC.scala:78:14]
input io_ptw_7_resp_bits_pte_r, // @[LazyRoCC.scala:78:14]
input io_ptw_7_resp_bits_pte_v, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_7_resp_bits_level, // @[LazyRoCC.scala:78:14]
input io_ptw_7_resp_bits_homogeneous, // @[LazyRoCC.scala:78:14]
input io_ptw_7_resp_bits_gpa_valid, // @[LazyRoCC.scala:78:14]
input [38:0] io_ptw_7_resp_bits_gpa_bits, // @[LazyRoCC.scala:78:14]
input io_ptw_7_resp_bits_gpa_is_pte, // @[LazyRoCC.scala:78:14]
input [3:0] io_ptw_7_ptbr_mode, // @[LazyRoCC.scala:78:14]
input [43:0] io_ptw_7_ptbr_ppn, // @[LazyRoCC.scala:78:14]
input io_ptw_7_status_debug, // @[LazyRoCC.scala:78:14]
input io_ptw_7_status_cease, // @[LazyRoCC.scala:78:14]
input io_ptw_7_status_wfi, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_7_status_isa, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_7_status_dprv, // @[LazyRoCC.scala:78:14]
input io_ptw_7_status_dv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_7_status_prv, // @[LazyRoCC.scala:78:14]
input io_ptw_7_status_v, // @[LazyRoCC.scala:78:14]
input io_ptw_7_status_mpv, // @[LazyRoCC.scala:78:14]
input io_ptw_7_status_gva, // @[LazyRoCC.scala:78:14]
input io_ptw_7_status_tsr, // @[LazyRoCC.scala:78:14]
input io_ptw_7_status_tw, // @[LazyRoCC.scala:78:14]
input io_ptw_7_status_tvm, // @[LazyRoCC.scala:78:14]
input io_ptw_7_status_mxr, // @[LazyRoCC.scala:78:14]
input io_ptw_7_status_sum, // @[LazyRoCC.scala:78:14]
input io_ptw_7_status_mprv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_7_status_fs, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_7_status_mpp, // @[LazyRoCC.scala:78:14]
input io_ptw_7_status_spp, // @[LazyRoCC.scala:78:14]
input io_ptw_7_status_mpie, // @[LazyRoCC.scala:78:14]
input io_ptw_7_status_spie, // @[LazyRoCC.scala:78:14]
input io_ptw_7_status_mie, // @[LazyRoCC.scala:78:14]
input io_ptw_7_status_sie, // @[LazyRoCC.scala:78:14]
input io_ptw_7_hstatus_spvp, // @[LazyRoCC.scala:78:14]
input io_ptw_7_hstatus_spv, // @[LazyRoCC.scala:78:14]
input io_ptw_7_hstatus_gva, // @[LazyRoCC.scala:78:14]
input io_ptw_7_gstatus_debug, // @[LazyRoCC.scala:78:14]
input io_ptw_7_gstatus_cease, // @[LazyRoCC.scala:78:14]
input io_ptw_7_gstatus_wfi, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_7_gstatus_isa, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_7_gstatus_dprv, // @[LazyRoCC.scala:78:14]
input io_ptw_7_gstatus_dv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_7_gstatus_prv, // @[LazyRoCC.scala:78:14]
input io_ptw_7_gstatus_v, // @[LazyRoCC.scala:78:14]
input [22:0] io_ptw_7_gstatus_zero2, // @[LazyRoCC.scala:78:14]
input io_ptw_7_gstatus_mpv, // @[LazyRoCC.scala:78:14]
input io_ptw_7_gstatus_gva, // @[LazyRoCC.scala:78:14]
input io_ptw_7_gstatus_mbe, // @[LazyRoCC.scala:78:14]
input io_ptw_7_gstatus_sbe, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_7_gstatus_sxl, // @[LazyRoCC.scala:78:14]
input [7:0] io_ptw_7_gstatus_zero1, // @[LazyRoCC.scala:78:14]
input io_ptw_7_gstatus_tsr, // @[LazyRoCC.scala:78:14]
input io_ptw_7_gstatus_tw, // @[LazyRoCC.scala:78:14]
input io_ptw_7_gstatus_tvm, // @[LazyRoCC.scala:78:14]
input io_ptw_7_gstatus_mxr, // @[LazyRoCC.scala:78:14]
input io_ptw_7_gstatus_sum, // @[LazyRoCC.scala:78:14]
input io_ptw_7_gstatus_mprv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_7_gstatus_fs, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_7_gstatus_mpp, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_7_gstatus_vs, // @[LazyRoCC.scala:78:14]
input io_ptw_7_gstatus_spp, // @[LazyRoCC.scala:78:14]
input io_ptw_7_gstatus_mpie, // @[LazyRoCC.scala:78:14]
input io_ptw_7_gstatus_ube, // @[LazyRoCC.scala:78:14]
input io_ptw_7_gstatus_spie, // @[LazyRoCC.scala:78:14]
input io_ptw_7_gstatus_upie, // @[LazyRoCC.scala:78:14]
input io_ptw_7_gstatus_mie, // @[LazyRoCC.scala:78:14]
input io_ptw_7_gstatus_hie, // @[LazyRoCC.scala:78:14]
input io_ptw_7_gstatus_sie, // @[LazyRoCC.scala:78:14]
input io_ptw_7_gstatus_uie, // @[LazyRoCC.scala:78:14]
input io_ptw_7_pmp_0_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_7_pmp_0_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_7_pmp_0_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_7_pmp_0_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_7_pmp_0_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_7_pmp_0_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_7_pmp_0_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_7_pmp_1_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_7_pmp_1_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_7_pmp_1_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_7_pmp_1_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_7_pmp_1_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_7_pmp_1_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_7_pmp_1_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_7_pmp_2_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_7_pmp_2_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_7_pmp_2_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_7_pmp_2_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_7_pmp_2_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_7_pmp_2_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_7_pmp_2_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_7_pmp_3_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_7_pmp_3_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_7_pmp_3_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_7_pmp_3_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_7_pmp_3_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_7_pmp_3_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_7_pmp_3_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_7_pmp_4_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_7_pmp_4_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_7_pmp_4_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_7_pmp_4_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_7_pmp_4_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_7_pmp_4_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_7_pmp_4_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_7_pmp_5_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_7_pmp_5_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_7_pmp_5_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_7_pmp_5_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_7_pmp_5_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_7_pmp_5_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_7_pmp_5_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_7_pmp_6_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_7_pmp_6_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_7_pmp_6_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_7_pmp_6_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_7_pmp_6_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_7_pmp_6_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_7_pmp_6_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_7_pmp_7_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_7_pmp_7_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_7_pmp_7_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_7_pmp_7_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_7_pmp_7_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_7_pmp_7_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_7_pmp_7_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_7_customCSRs_csrs_0_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_7_customCSRs_csrs_0_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_7_customCSRs_csrs_0_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_7_customCSRs_csrs_0_value, // @[LazyRoCC.scala:78:14]
input io_ptw_7_customCSRs_csrs_1_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_7_customCSRs_csrs_1_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_7_customCSRs_csrs_1_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_7_customCSRs_csrs_1_value, // @[LazyRoCC.scala:78:14]
input io_ptw_7_customCSRs_csrs_2_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_7_customCSRs_csrs_2_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_7_customCSRs_csrs_2_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_7_customCSRs_csrs_2_value, // @[LazyRoCC.scala:78:14]
input io_ptw_7_customCSRs_csrs_3_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_7_customCSRs_csrs_3_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_7_customCSRs_csrs_3_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_7_customCSRs_csrs_3_value, // @[LazyRoCC.scala:78:14]
input io_ptw_8_req_ready, // @[LazyRoCC.scala:78:14]
output io_ptw_8_req_valid, // @[LazyRoCC.scala:78:14]
output [26:0] io_ptw_8_req_bits_bits_addr, // @[LazyRoCC.scala:78:14]
output io_ptw_8_req_bits_bits_need_gpa, // @[LazyRoCC.scala:78:14]
input io_ptw_8_resp_valid, // @[LazyRoCC.scala:78:14]
input io_ptw_8_resp_bits_ae_ptw, // @[LazyRoCC.scala:78:14]
input io_ptw_8_resp_bits_ae_final, // @[LazyRoCC.scala:78:14]
input io_ptw_8_resp_bits_pf, // @[LazyRoCC.scala:78:14]
input io_ptw_8_resp_bits_gf, // @[LazyRoCC.scala:78:14]
input io_ptw_8_resp_bits_hr, // @[LazyRoCC.scala:78:14]
input io_ptw_8_resp_bits_hw, // @[LazyRoCC.scala:78:14]
input io_ptw_8_resp_bits_hx, // @[LazyRoCC.scala:78:14]
input [9:0] io_ptw_8_resp_bits_pte_reserved_for_future, // @[LazyRoCC.scala:78:14]
input [43:0] io_ptw_8_resp_bits_pte_ppn, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_8_resp_bits_pte_reserved_for_software, // @[LazyRoCC.scala:78:14]
input io_ptw_8_resp_bits_pte_d, // @[LazyRoCC.scala:78:14]
input io_ptw_8_resp_bits_pte_a, // @[LazyRoCC.scala:78:14]
input io_ptw_8_resp_bits_pte_g, // @[LazyRoCC.scala:78:14]
input io_ptw_8_resp_bits_pte_u, // @[LazyRoCC.scala:78:14]
input io_ptw_8_resp_bits_pte_x, // @[LazyRoCC.scala:78:14]
input io_ptw_8_resp_bits_pte_w, // @[LazyRoCC.scala:78:14]
input io_ptw_8_resp_bits_pte_r, // @[LazyRoCC.scala:78:14]
input io_ptw_8_resp_bits_pte_v, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_8_resp_bits_level, // @[LazyRoCC.scala:78:14]
input io_ptw_8_resp_bits_homogeneous, // @[LazyRoCC.scala:78:14]
input io_ptw_8_resp_bits_gpa_valid, // @[LazyRoCC.scala:78:14]
input [38:0] io_ptw_8_resp_bits_gpa_bits, // @[LazyRoCC.scala:78:14]
input io_ptw_8_resp_bits_gpa_is_pte, // @[LazyRoCC.scala:78:14]
input [3:0] io_ptw_8_ptbr_mode, // @[LazyRoCC.scala:78:14]
input [43:0] io_ptw_8_ptbr_ppn, // @[LazyRoCC.scala:78:14]
input io_ptw_8_status_debug, // @[LazyRoCC.scala:78:14]
input io_ptw_8_status_cease, // @[LazyRoCC.scala:78:14]
input io_ptw_8_status_wfi, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_8_status_isa, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_8_status_dprv, // @[LazyRoCC.scala:78:14]
input io_ptw_8_status_dv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_8_status_prv, // @[LazyRoCC.scala:78:14]
input io_ptw_8_status_v, // @[LazyRoCC.scala:78:14]
input io_ptw_8_status_mpv, // @[LazyRoCC.scala:78:14]
input io_ptw_8_status_gva, // @[LazyRoCC.scala:78:14]
input io_ptw_8_status_tsr, // @[LazyRoCC.scala:78:14]
input io_ptw_8_status_tw, // @[LazyRoCC.scala:78:14]
input io_ptw_8_status_tvm, // @[LazyRoCC.scala:78:14]
input io_ptw_8_status_mxr, // @[LazyRoCC.scala:78:14]
input io_ptw_8_status_sum, // @[LazyRoCC.scala:78:14]
input io_ptw_8_status_mprv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_8_status_fs, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_8_status_mpp, // @[LazyRoCC.scala:78:14]
input io_ptw_8_status_spp, // @[LazyRoCC.scala:78:14]
input io_ptw_8_status_mpie, // @[LazyRoCC.scala:78:14]
input io_ptw_8_status_spie, // @[LazyRoCC.scala:78:14]
input io_ptw_8_status_mie, // @[LazyRoCC.scala:78:14]
input io_ptw_8_status_sie, // @[LazyRoCC.scala:78:14]
input io_ptw_8_hstatus_spvp, // @[LazyRoCC.scala:78:14]
input io_ptw_8_hstatus_spv, // @[LazyRoCC.scala:78:14]
input io_ptw_8_hstatus_gva, // @[LazyRoCC.scala:78:14]
input io_ptw_8_gstatus_debug, // @[LazyRoCC.scala:78:14]
input io_ptw_8_gstatus_cease, // @[LazyRoCC.scala:78:14]
input io_ptw_8_gstatus_wfi, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_8_gstatus_isa, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_8_gstatus_dprv, // @[LazyRoCC.scala:78:14]
input io_ptw_8_gstatus_dv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_8_gstatus_prv, // @[LazyRoCC.scala:78:14]
input io_ptw_8_gstatus_v, // @[LazyRoCC.scala:78:14]
input [22:0] io_ptw_8_gstatus_zero2, // @[LazyRoCC.scala:78:14]
input io_ptw_8_gstatus_mpv, // @[LazyRoCC.scala:78:14]
input io_ptw_8_gstatus_gva, // @[LazyRoCC.scala:78:14]
input io_ptw_8_gstatus_mbe, // @[LazyRoCC.scala:78:14]
input io_ptw_8_gstatus_sbe, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_8_gstatus_sxl, // @[LazyRoCC.scala:78:14]
input [7:0] io_ptw_8_gstatus_zero1, // @[LazyRoCC.scala:78:14]
input io_ptw_8_gstatus_tsr, // @[LazyRoCC.scala:78:14]
input io_ptw_8_gstatus_tw, // @[LazyRoCC.scala:78:14]
input io_ptw_8_gstatus_tvm, // @[LazyRoCC.scala:78:14]
input io_ptw_8_gstatus_mxr, // @[LazyRoCC.scala:78:14]
input io_ptw_8_gstatus_sum, // @[LazyRoCC.scala:78:14]
input io_ptw_8_gstatus_mprv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_8_gstatus_fs, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_8_gstatus_mpp, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_8_gstatus_vs, // @[LazyRoCC.scala:78:14]
input io_ptw_8_gstatus_spp, // @[LazyRoCC.scala:78:14]
input io_ptw_8_gstatus_mpie, // @[LazyRoCC.scala:78:14]
input io_ptw_8_gstatus_ube, // @[LazyRoCC.scala:78:14]
input io_ptw_8_gstatus_spie, // @[LazyRoCC.scala:78:14]
input io_ptw_8_gstatus_upie, // @[LazyRoCC.scala:78:14]
input io_ptw_8_gstatus_mie, // @[LazyRoCC.scala:78:14]
input io_ptw_8_gstatus_hie, // @[LazyRoCC.scala:78:14]
input io_ptw_8_gstatus_sie, // @[LazyRoCC.scala:78:14]
input io_ptw_8_gstatus_uie, // @[LazyRoCC.scala:78:14]
input io_ptw_8_pmp_0_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_8_pmp_0_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_8_pmp_0_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_8_pmp_0_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_8_pmp_0_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_8_pmp_0_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_8_pmp_0_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_8_pmp_1_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_8_pmp_1_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_8_pmp_1_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_8_pmp_1_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_8_pmp_1_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_8_pmp_1_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_8_pmp_1_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_8_pmp_2_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_8_pmp_2_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_8_pmp_2_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_8_pmp_2_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_8_pmp_2_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_8_pmp_2_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_8_pmp_2_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_8_pmp_3_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_8_pmp_3_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_8_pmp_3_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_8_pmp_3_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_8_pmp_3_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_8_pmp_3_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_8_pmp_3_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_8_pmp_4_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_8_pmp_4_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_8_pmp_4_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_8_pmp_4_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_8_pmp_4_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_8_pmp_4_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_8_pmp_4_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_8_pmp_5_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_8_pmp_5_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_8_pmp_5_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_8_pmp_5_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_8_pmp_5_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_8_pmp_5_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_8_pmp_5_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_8_pmp_6_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_8_pmp_6_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_8_pmp_6_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_8_pmp_6_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_8_pmp_6_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_8_pmp_6_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_8_pmp_6_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_8_pmp_7_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_8_pmp_7_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_8_pmp_7_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_8_pmp_7_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_8_pmp_7_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_8_pmp_7_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_8_pmp_7_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_8_customCSRs_csrs_0_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_8_customCSRs_csrs_0_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_8_customCSRs_csrs_0_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_8_customCSRs_csrs_0_value, // @[LazyRoCC.scala:78:14]
input io_ptw_8_customCSRs_csrs_1_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_8_customCSRs_csrs_1_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_8_customCSRs_csrs_1_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_8_customCSRs_csrs_1_value, // @[LazyRoCC.scala:78:14]
input io_ptw_8_customCSRs_csrs_2_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_8_customCSRs_csrs_2_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_8_customCSRs_csrs_2_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_8_customCSRs_csrs_2_value, // @[LazyRoCC.scala:78:14]
input io_ptw_8_customCSRs_csrs_3_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_8_customCSRs_csrs_3_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_8_customCSRs_csrs_3_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_8_customCSRs_csrs_3_value, // @[LazyRoCC.scala:78:14]
input io_ptw_9_req_ready, // @[LazyRoCC.scala:78:14]
output io_ptw_9_req_valid, // @[LazyRoCC.scala:78:14]
output [26:0] io_ptw_9_req_bits_bits_addr, // @[LazyRoCC.scala:78:14]
output io_ptw_9_req_bits_bits_need_gpa, // @[LazyRoCC.scala:78:14]
input io_ptw_9_resp_valid, // @[LazyRoCC.scala:78:14]
input io_ptw_9_resp_bits_ae_ptw, // @[LazyRoCC.scala:78:14]
input io_ptw_9_resp_bits_ae_final, // @[LazyRoCC.scala:78:14]
input io_ptw_9_resp_bits_pf, // @[LazyRoCC.scala:78:14]
input io_ptw_9_resp_bits_gf, // @[LazyRoCC.scala:78:14]
input io_ptw_9_resp_bits_hr, // @[LazyRoCC.scala:78:14]
input io_ptw_9_resp_bits_hw, // @[LazyRoCC.scala:78:14]
input io_ptw_9_resp_bits_hx, // @[LazyRoCC.scala:78:14]
input [9:0] io_ptw_9_resp_bits_pte_reserved_for_future, // @[LazyRoCC.scala:78:14]
input [43:0] io_ptw_9_resp_bits_pte_ppn, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_9_resp_bits_pte_reserved_for_software, // @[LazyRoCC.scala:78:14]
input io_ptw_9_resp_bits_pte_d, // @[LazyRoCC.scala:78:14]
input io_ptw_9_resp_bits_pte_a, // @[LazyRoCC.scala:78:14]
input io_ptw_9_resp_bits_pte_g, // @[LazyRoCC.scala:78:14]
input io_ptw_9_resp_bits_pte_u, // @[LazyRoCC.scala:78:14]
input io_ptw_9_resp_bits_pte_x, // @[LazyRoCC.scala:78:14]
input io_ptw_9_resp_bits_pte_w, // @[LazyRoCC.scala:78:14]
input io_ptw_9_resp_bits_pte_r, // @[LazyRoCC.scala:78:14]
input io_ptw_9_resp_bits_pte_v, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_9_resp_bits_level, // @[LazyRoCC.scala:78:14]
input io_ptw_9_resp_bits_homogeneous, // @[LazyRoCC.scala:78:14]
input io_ptw_9_resp_bits_gpa_valid, // @[LazyRoCC.scala:78:14]
input [38:0] io_ptw_9_resp_bits_gpa_bits, // @[LazyRoCC.scala:78:14]
input io_ptw_9_resp_bits_gpa_is_pte, // @[LazyRoCC.scala:78:14]
input [3:0] io_ptw_9_ptbr_mode, // @[LazyRoCC.scala:78:14]
input [43:0] io_ptw_9_ptbr_ppn, // @[LazyRoCC.scala:78:14]
input io_ptw_9_status_debug, // @[LazyRoCC.scala:78:14]
input io_ptw_9_status_cease, // @[LazyRoCC.scala:78:14]
input io_ptw_9_status_wfi, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_9_status_isa, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_9_status_dprv, // @[LazyRoCC.scala:78:14]
input io_ptw_9_status_dv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_9_status_prv, // @[LazyRoCC.scala:78:14]
input io_ptw_9_status_v, // @[LazyRoCC.scala:78:14]
input io_ptw_9_status_mpv, // @[LazyRoCC.scala:78:14]
input io_ptw_9_status_gva, // @[LazyRoCC.scala:78:14]
input io_ptw_9_status_tsr, // @[LazyRoCC.scala:78:14]
input io_ptw_9_status_tw, // @[LazyRoCC.scala:78:14]
input io_ptw_9_status_tvm, // @[LazyRoCC.scala:78:14]
input io_ptw_9_status_mxr, // @[LazyRoCC.scala:78:14]
input io_ptw_9_status_sum, // @[LazyRoCC.scala:78:14]
input io_ptw_9_status_mprv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_9_status_fs, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_9_status_mpp, // @[LazyRoCC.scala:78:14]
input io_ptw_9_status_spp, // @[LazyRoCC.scala:78:14]
input io_ptw_9_status_mpie, // @[LazyRoCC.scala:78:14]
input io_ptw_9_status_spie, // @[LazyRoCC.scala:78:14]
input io_ptw_9_status_mie, // @[LazyRoCC.scala:78:14]
input io_ptw_9_status_sie, // @[LazyRoCC.scala:78:14]
input io_ptw_9_hstatus_spvp, // @[LazyRoCC.scala:78:14]
input io_ptw_9_hstatus_spv, // @[LazyRoCC.scala:78:14]
input io_ptw_9_hstatus_gva, // @[LazyRoCC.scala:78:14]
input io_ptw_9_gstatus_debug, // @[LazyRoCC.scala:78:14]
input io_ptw_9_gstatus_cease, // @[LazyRoCC.scala:78:14]
input io_ptw_9_gstatus_wfi, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_9_gstatus_isa, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_9_gstatus_dprv, // @[LazyRoCC.scala:78:14]
input io_ptw_9_gstatus_dv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_9_gstatus_prv, // @[LazyRoCC.scala:78:14]
input io_ptw_9_gstatus_v, // @[LazyRoCC.scala:78:14]
input [22:0] io_ptw_9_gstatus_zero2, // @[LazyRoCC.scala:78:14]
input io_ptw_9_gstatus_mpv, // @[LazyRoCC.scala:78:14]
input io_ptw_9_gstatus_gva, // @[LazyRoCC.scala:78:14]
input io_ptw_9_gstatus_mbe, // @[LazyRoCC.scala:78:14]
input io_ptw_9_gstatus_sbe, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_9_gstatus_sxl, // @[LazyRoCC.scala:78:14]
input [7:0] io_ptw_9_gstatus_zero1, // @[LazyRoCC.scala:78:14]
input io_ptw_9_gstatus_tsr, // @[LazyRoCC.scala:78:14]
input io_ptw_9_gstatus_tw, // @[LazyRoCC.scala:78:14]
input io_ptw_9_gstatus_tvm, // @[LazyRoCC.scala:78:14]
input io_ptw_9_gstatus_mxr, // @[LazyRoCC.scala:78:14]
input io_ptw_9_gstatus_sum, // @[LazyRoCC.scala:78:14]
input io_ptw_9_gstatus_mprv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_9_gstatus_fs, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_9_gstatus_mpp, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_9_gstatus_vs, // @[LazyRoCC.scala:78:14]
input io_ptw_9_gstatus_spp, // @[LazyRoCC.scala:78:14]
input io_ptw_9_gstatus_mpie, // @[LazyRoCC.scala:78:14]
input io_ptw_9_gstatus_ube, // @[LazyRoCC.scala:78:14]
input io_ptw_9_gstatus_spie, // @[LazyRoCC.scala:78:14]
input io_ptw_9_gstatus_upie, // @[LazyRoCC.scala:78:14]
input io_ptw_9_gstatus_mie, // @[LazyRoCC.scala:78:14]
input io_ptw_9_gstatus_hie, // @[LazyRoCC.scala:78:14]
input io_ptw_9_gstatus_sie, // @[LazyRoCC.scala:78:14]
input io_ptw_9_gstatus_uie, // @[LazyRoCC.scala:78:14]
input io_ptw_9_pmp_0_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_9_pmp_0_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_9_pmp_0_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_9_pmp_0_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_9_pmp_0_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_9_pmp_0_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_9_pmp_0_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_9_pmp_1_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_9_pmp_1_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_9_pmp_1_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_9_pmp_1_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_9_pmp_1_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_9_pmp_1_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_9_pmp_1_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_9_pmp_2_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_9_pmp_2_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_9_pmp_2_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_9_pmp_2_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_9_pmp_2_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_9_pmp_2_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_9_pmp_2_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_9_pmp_3_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_9_pmp_3_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_9_pmp_3_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_9_pmp_3_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_9_pmp_3_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_9_pmp_3_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_9_pmp_3_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_9_pmp_4_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_9_pmp_4_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_9_pmp_4_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_9_pmp_4_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_9_pmp_4_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_9_pmp_4_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_9_pmp_4_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_9_pmp_5_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_9_pmp_5_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_9_pmp_5_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_9_pmp_5_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_9_pmp_5_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_9_pmp_5_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_9_pmp_5_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_9_pmp_6_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_9_pmp_6_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_9_pmp_6_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_9_pmp_6_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_9_pmp_6_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_9_pmp_6_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_9_pmp_6_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_9_pmp_7_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_9_pmp_7_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_9_pmp_7_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_9_pmp_7_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_9_pmp_7_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_9_pmp_7_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_9_pmp_7_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_9_customCSRs_csrs_0_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_9_customCSRs_csrs_0_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_9_customCSRs_csrs_0_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_9_customCSRs_csrs_0_value, // @[LazyRoCC.scala:78:14]
input io_ptw_9_customCSRs_csrs_1_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_9_customCSRs_csrs_1_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_9_customCSRs_csrs_1_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_9_customCSRs_csrs_1_value, // @[LazyRoCC.scala:78:14]
input io_ptw_9_customCSRs_csrs_2_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_9_customCSRs_csrs_2_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_9_customCSRs_csrs_2_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_9_customCSRs_csrs_2_value, // @[LazyRoCC.scala:78:14]
input io_ptw_9_customCSRs_csrs_3_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_9_customCSRs_csrs_3_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_9_customCSRs_csrs_3_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_9_customCSRs_csrs_3_value, // @[LazyRoCC.scala:78:14]
input io_ptw_10_req_ready, // @[LazyRoCC.scala:78:14]
output io_ptw_10_req_valid, // @[LazyRoCC.scala:78:14]
output [26:0] io_ptw_10_req_bits_bits_addr, // @[LazyRoCC.scala:78:14]
output io_ptw_10_req_bits_bits_need_gpa, // @[LazyRoCC.scala:78:14]
input io_ptw_10_resp_valid, // @[LazyRoCC.scala:78:14]
input io_ptw_10_resp_bits_ae_ptw, // @[LazyRoCC.scala:78:14]
input io_ptw_10_resp_bits_ae_final, // @[LazyRoCC.scala:78:14]
input io_ptw_10_resp_bits_pf, // @[LazyRoCC.scala:78:14]
input io_ptw_10_resp_bits_gf, // @[LazyRoCC.scala:78:14]
input io_ptw_10_resp_bits_hr, // @[LazyRoCC.scala:78:14]
input io_ptw_10_resp_bits_hw, // @[LazyRoCC.scala:78:14]
input io_ptw_10_resp_bits_hx, // @[LazyRoCC.scala:78:14]
input [9:0] io_ptw_10_resp_bits_pte_reserved_for_future, // @[LazyRoCC.scala:78:14]
input [43:0] io_ptw_10_resp_bits_pte_ppn, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_10_resp_bits_pte_reserved_for_software, // @[LazyRoCC.scala:78:14]
input io_ptw_10_resp_bits_pte_d, // @[LazyRoCC.scala:78:14]
input io_ptw_10_resp_bits_pte_a, // @[LazyRoCC.scala:78:14]
input io_ptw_10_resp_bits_pte_g, // @[LazyRoCC.scala:78:14]
input io_ptw_10_resp_bits_pte_u, // @[LazyRoCC.scala:78:14]
input io_ptw_10_resp_bits_pte_x, // @[LazyRoCC.scala:78:14]
input io_ptw_10_resp_bits_pte_w, // @[LazyRoCC.scala:78:14]
input io_ptw_10_resp_bits_pte_r, // @[LazyRoCC.scala:78:14]
input io_ptw_10_resp_bits_pte_v, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_10_resp_bits_level, // @[LazyRoCC.scala:78:14]
input io_ptw_10_resp_bits_homogeneous, // @[LazyRoCC.scala:78:14]
input io_ptw_10_resp_bits_gpa_valid, // @[LazyRoCC.scala:78:14]
input [38:0] io_ptw_10_resp_bits_gpa_bits, // @[LazyRoCC.scala:78:14]
input io_ptw_10_resp_bits_gpa_is_pte, // @[LazyRoCC.scala:78:14]
input [3:0] io_ptw_10_ptbr_mode, // @[LazyRoCC.scala:78:14]
input [43:0] io_ptw_10_ptbr_ppn, // @[LazyRoCC.scala:78:14]
input io_ptw_10_status_debug, // @[LazyRoCC.scala:78:14]
input io_ptw_10_status_cease, // @[LazyRoCC.scala:78:14]
input io_ptw_10_status_wfi, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_10_status_isa, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_10_status_dprv, // @[LazyRoCC.scala:78:14]
input io_ptw_10_status_dv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_10_status_prv, // @[LazyRoCC.scala:78:14]
input io_ptw_10_status_v, // @[LazyRoCC.scala:78:14]
input io_ptw_10_status_mpv, // @[LazyRoCC.scala:78:14]
input io_ptw_10_status_gva, // @[LazyRoCC.scala:78:14]
input io_ptw_10_status_tsr, // @[LazyRoCC.scala:78:14]
input io_ptw_10_status_tw, // @[LazyRoCC.scala:78:14]
input io_ptw_10_status_tvm, // @[LazyRoCC.scala:78:14]
input io_ptw_10_status_mxr, // @[LazyRoCC.scala:78:14]
input io_ptw_10_status_sum, // @[LazyRoCC.scala:78:14]
input io_ptw_10_status_mprv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_10_status_fs, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_10_status_mpp, // @[LazyRoCC.scala:78:14]
input io_ptw_10_status_spp, // @[LazyRoCC.scala:78:14]
input io_ptw_10_status_mpie, // @[LazyRoCC.scala:78:14]
input io_ptw_10_status_spie, // @[LazyRoCC.scala:78:14]
input io_ptw_10_status_mie, // @[LazyRoCC.scala:78:14]
input io_ptw_10_status_sie, // @[LazyRoCC.scala:78:14]
input io_ptw_10_hstatus_spvp, // @[LazyRoCC.scala:78:14]
input io_ptw_10_hstatus_spv, // @[LazyRoCC.scala:78:14]
input io_ptw_10_hstatus_gva, // @[LazyRoCC.scala:78:14]
input io_ptw_10_gstatus_debug, // @[LazyRoCC.scala:78:14]
input io_ptw_10_gstatus_cease, // @[LazyRoCC.scala:78:14]
input io_ptw_10_gstatus_wfi, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_10_gstatus_isa, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_10_gstatus_dprv, // @[LazyRoCC.scala:78:14]
input io_ptw_10_gstatus_dv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_10_gstatus_prv, // @[LazyRoCC.scala:78:14]
input io_ptw_10_gstatus_v, // @[LazyRoCC.scala:78:14]
input [22:0] io_ptw_10_gstatus_zero2, // @[LazyRoCC.scala:78:14]
input io_ptw_10_gstatus_mpv, // @[LazyRoCC.scala:78:14]
input io_ptw_10_gstatus_gva, // @[LazyRoCC.scala:78:14]
input io_ptw_10_gstatus_mbe, // @[LazyRoCC.scala:78:14]
input io_ptw_10_gstatus_sbe, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_10_gstatus_sxl, // @[LazyRoCC.scala:78:14]
input [7:0] io_ptw_10_gstatus_zero1, // @[LazyRoCC.scala:78:14]
input io_ptw_10_gstatus_tsr, // @[LazyRoCC.scala:78:14]
input io_ptw_10_gstatus_tw, // @[LazyRoCC.scala:78:14]
input io_ptw_10_gstatus_tvm, // @[LazyRoCC.scala:78:14]
input io_ptw_10_gstatus_mxr, // @[LazyRoCC.scala:78:14]
input io_ptw_10_gstatus_sum, // @[LazyRoCC.scala:78:14]
input io_ptw_10_gstatus_mprv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_10_gstatus_fs, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_10_gstatus_mpp, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_10_gstatus_vs, // @[LazyRoCC.scala:78:14]
input io_ptw_10_gstatus_spp, // @[LazyRoCC.scala:78:14]
input io_ptw_10_gstatus_mpie, // @[LazyRoCC.scala:78:14]
input io_ptw_10_gstatus_ube, // @[LazyRoCC.scala:78:14]
input io_ptw_10_gstatus_spie, // @[LazyRoCC.scala:78:14]
input io_ptw_10_gstatus_upie, // @[LazyRoCC.scala:78:14]
input io_ptw_10_gstatus_mie, // @[LazyRoCC.scala:78:14]
input io_ptw_10_gstatus_hie, // @[LazyRoCC.scala:78:14]
input io_ptw_10_gstatus_sie, // @[LazyRoCC.scala:78:14]
input io_ptw_10_gstatus_uie, // @[LazyRoCC.scala:78:14]
input io_ptw_10_pmp_0_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_10_pmp_0_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_10_pmp_0_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_10_pmp_0_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_10_pmp_0_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_10_pmp_0_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_10_pmp_0_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_10_pmp_1_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_10_pmp_1_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_10_pmp_1_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_10_pmp_1_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_10_pmp_1_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_10_pmp_1_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_10_pmp_1_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_10_pmp_2_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_10_pmp_2_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_10_pmp_2_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_10_pmp_2_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_10_pmp_2_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_10_pmp_2_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_10_pmp_2_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_10_pmp_3_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_10_pmp_3_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_10_pmp_3_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_10_pmp_3_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_10_pmp_3_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_10_pmp_3_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_10_pmp_3_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_10_pmp_4_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_10_pmp_4_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_10_pmp_4_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_10_pmp_4_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_10_pmp_4_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_10_pmp_4_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_10_pmp_4_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_10_pmp_5_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_10_pmp_5_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_10_pmp_5_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_10_pmp_5_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_10_pmp_5_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_10_pmp_5_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_10_pmp_5_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_10_pmp_6_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_10_pmp_6_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_10_pmp_6_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_10_pmp_6_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_10_pmp_6_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_10_pmp_6_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_10_pmp_6_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_10_pmp_7_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_10_pmp_7_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_10_pmp_7_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_10_pmp_7_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_10_pmp_7_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_10_pmp_7_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_10_pmp_7_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_10_customCSRs_csrs_0_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_10_customCSRs_csrs_0_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_10_customCSRs_csrs_0_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_10_customCSRs_csrs_0_value, // @[LazyRoCC.scala:78:14]
input io_ptw_10_customCSRs_csrs_1_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_10_customCSRs_csrs_1_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_10_customCSRs_csrs_1_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_10_customCSRs_csrs_1_value, // @[LazyRoCC.scala:78:14]
input io_ptw_10_customCSRs_csrs_2_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_10_customCSRs_csrs_2_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_10_customCSRs_csrs_2_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_10_customCSRs_csrs_2_value, // @[LazyRoCC.scala:78:14]
input io_ptw_10_customCSRs_csrs_3_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_10_customCSRs_csrs_3_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_10_customCSRs_csrs_3_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_10_customCSRs_csrs_3_value, // @[LazyRoCC.scala:78:14]
input io_ptw_11_req_ready, // @[LazyRoCC.scala:78:14]
output io_ptw_11_req_valid, // @[LazyRoCC.scala:78:14]
output [26:0] io_ptw_11_req_bits_bits_addr, // @[LazyRoCC.scala:78:14]
output io_ptw_11_req_bits_bits_need_gpa, // @[LazyRoCC.scala:78:14]
input io_ptw_11_resp_valid, // @[LazyRoCC.scala:78:14]
input io_ptw_11_resp_bits_ae_ptw, // @[LazyRoCC.scala:78:14]
input io_ptw_11_resp_bits_ae_final, // @[LazyRoCC.scala:78:14]
input io_ptw_11_resp_bits_pf, // @[LazyRoCC.scala:78:14]
input io_ptw_11_resp_bits_gf, // @[LazyRoCC.scala:78:14]
input io_ptw_11_resp_bits_hr, // @[LazyRoCC.scala:78:14]
input io_ptw_11_resp_bits_hw, // @[LazyRoCC.scala:78:14]
input io_ptw_11_resp_bits_hx, // @[LazyRoCC.scala:78:14]
input [9:0] io_ptw_11_resp_bits_pte_reserved_for_future, // @[LazyRoCC.scala:78:14]
input [43:0] io_ptw_11_resp_bits_pte_ppn, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_11_resp_bits_pte_reserved_for_software, // @[LazyRoCC.scala:78:14]
input io_ptw_11_resp_bits_pte_d, // @[LazyRoCC.scala:78:14]
input io_ptw_11_resp_bits_pte_a, // @[LazyRoCC.scala:78:14]
input io_ptw_11_resp_bits_pte_g, // @[LazyRoCC.scala:78:14]
input io_ptw_11_resp_bits_pte_u, // @[LazyRoCC.scala:78:14]
input io_ptw_11_resp_bits_pte_x, // @[LazyRoCC.scala:78:14]
input io_ptw_11_resp_bits_pte_w, // @[LazyRoCC.scala:78:14]
input io_ptw_11_resp_bits_pte_r, // @[LazyRoCC.scala:78:14]
input io_ptw_11_resp_bits_pte_v, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_11_resp_bits_level, // @[LazyRoCC.scala:78:14]
input io_ptw_11_resp_bits_homogeneous, // @[LazyRoCC.scala:78:14]
input io_ptw_11_resp_bits_gpa_valid, // @[LazyRoCC.scala:78:14]
input [38:0] io_ptw_11_resp_bits_gpa_bits, // @[LazyRoCC.scala:78:14]
input io_ptw_11_resp_bits_gpa_is_pte, // @[LazyRoCC.scala:78:14]
input [3:0] io_ptw_11_ptbr_mode, // @[LazyRoCC.scala:78:14]
input [43:0] io_ptw_11_ptbr_ppn, // @[LazyRoCC.scala:78:14]
input io_ptw_11_status_debug, // @[LazyRoCC.scala:78:14]
input io_ptw_11_status_cease, // @[LazyRoCC.scala:78:14]
input io_ptw_11_status_wfi, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_11_status_isa, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_11_status_dprv, // @[LazyRoCC.scala:78:14]
input io_ptw_11_status_dv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_11_status_prv, // @[LazyRoCC.scala:78:14]
input io_ptw_11_status_v, // @[LazyRoCC.scala:78:14]
input io_ptw_11_status_mpv, // @[LazyRoCC.scala:78:14]
input io_ptw_11_status_gva, // @[LazyRoCC.scala:78:14]
input io_ptw_11_status_tsr, // @[LazyRoCC.scala:78:14]
input io_ptw_11_status_tw, // @[LazyRoCC.scala:78:14]
input io_ptw_11_status_tvm, // @[LazyRoCC.scala:78:14]
input io_ptw_11_status_mxr, // @[LazyRoCC.scala:78:14]
input io_ptw_11_status_sum, // @[LazyRoCC.scala:78:14]
input io_ptw_11_status_mprv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_11_status_fs, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_11_status_mpp, // @[LazyRoCC.scala:78:14]
input io_ptw_11_status_spp, // @[LazyRoCC.scala:78:14]
input io_ptw_11_status_mpie, // @[LazyRoCC.scala:78:14]
input io_ptw_11_status_spie, // @[LazyRoCC.scala:78:14]
input io_ptw_11_status_mie, // @[LazyRoCC.scala:78:14]
input io_ptw_11_status_sie, // @[LazyRoCC.scala:78:14]
input io_ptw_11_hstatus_spvp, // @[LazyRoCC.scala:78:14]
input io_ptw_11_hstatus_spv, // @[LazyRoCC.scala:78:14]
input io_ptw_11_hstatus_gva, // @[LazyRoCC.scala:78:14]
input io_ptw_11_gstatus_debug, // @[LazyRoCC.scala:78:14]
input io_ptw_11_gstatus_cease, // @[LazyRoCC.scala:78:14]
input io_ptw_11_gstatus_wfi, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_11_gstatus_isa, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_11_gstatus_dprv, // @[LazyRoCC.scala:78:14]
input io_ptw_11_gstatus_dv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_11_gstatus_prv, // @[LazyRoCC.scala:78:14]
input io_ptw_11_gstatus_v, // @[LazyRoCC.scala:78:14]
input [22:0] io_ptw_11_gstatus_zero2, // @[LazyRoCC.scala:78:14]
input io_ptw_11_gstatus_mpv, // @[LazyRoCC.scala:78:14]
input io_ptw_11_gstatus_gva, // @[LazyRoCC.scala:78:14]
input io_ptw_11_gstatus_mbe, // @[LazyRoCC.scala:78:14]
input io_ptw_11_gstatus_sbe, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_11_gstatus_sxl, // @[LazyRoCC.scala:78:14]
input [7:0] io_ptw_11_gstatus_zero1, // @[LazyRoCC.scala:78:14]
input io_ptw_11_gstatus_tsr, // @[LazyRoCC.scala:78:14]
input io_ptw_11_gstatus_tw, // @[LazyRoCC.scala:78:14]
input io_ptw_11_gstatus_tvm, // @[LazyRoCC.scala:78:14]
input io_ptw_11_gstatus_mxr, // @[LazyRoCC.scala:78:14]
input io_ptw_11_gstatus_sum, // @[LazyRoCC.scala:78:14]
input io_ptw_11_gstatus_mprv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_11_gstatus_fs, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_11_gstatus_mpp, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_11_gstatus_vs, // @[LazyRoCC.scala:78:14]
input io_ptw_11_gstatus_spp, // @[LazyRoCC.scala:78:14]
input io_ptw_11_gstatus_mpie, // @[LazyRoCC.scala:78:14]
input io_ptw_11_gstatus_ube, // @[LazyRoCC.scala:78:14]
input io_ptw_11_gstatus_spie, // @[LazyRoCC.scala:78:14]
input io_ptw_11_gstatus_upie, // @[LazyRoCC.scala:78:14]
input io_ptw_11_gstatus_mie, // @[LazyRoCC.scala:78:14]
input io_ptw_11_gstatus_hie, // @[LazyRoCC.scala:78:14]
input io_ptw_11_gstatus_sie, // @[LazyRoCC.scala:78:14]
input io_ptw_11_gstatus_uie, // @[LazyRoCC.scala:78:14]
input io_ptw_11_pmp_0_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_11_pmp_0_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_11_pmp_0_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_11_pmp_0_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_11_pmp_0_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_11_pmp_0_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_11_pmp_0_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_11_pmp_1_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_11_pmp_1_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_11_pmp_1_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_11_pmp_1_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_11_pmp_1_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_11_pmp_1_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_11_pmp_1_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_11_pmp_2_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_11_pmp_2_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_11_pmp_2_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_11_pmp_2_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_11_pmp_2_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_11_pmp_2_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_11_pmp_2_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_11_pmp_3_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_11_pmp_3_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_11_pmp_3_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_11_pmp_3_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_11_pmp_3_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_11_pmp_3_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_11_pmp_3_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_11_pmp_4_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_11_pmp_4_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_11_pmp_4_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_11_pmp_4_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_11_pmp_4_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_11_pmp_4_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_11_pmp_4_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_11_pmp_5_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_11_pmp_5_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_11_pmp_5_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_11_pmp_5_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_11_pmp_5_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_11_pmp_5_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_11_pmp_5_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_11_pmp_6_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_11_pmp_6_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_11_pmp_6_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_11_pmp_6_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_11_pmp_6_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_11_pmp_6_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_11_pmp_6_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_11_pmp_7_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_11_pmp_7_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_11_pmp_7_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_11_pmp_7_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_11_pmp_7_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_11_pmp_7_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_11_pmp_7_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_11_customCSRs_csrs_0_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_11_customCSRs_csrs_0_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_11_customCSRs_csrs_0_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_11_customCSRs_csrs_0_value, // @[LazyRoCC.scala:78:14]
input io_ptw_11_customCSRs_csrs_1_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_11_customCSRs_csrs_1_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_11_customCSRs_csrs_1_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_11_customCSRs_csrs_1_value, // @[LazyRoCC.scala:78:14]
input io_ptw_11_customCSRs_csrs_2_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_11_customCSRs_csrs_2_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_11_customCSRs_csrs_2_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_11_customCSRs_csrs_2_value, // @[LazyRoCC.scala:78:14]
input io_ptw_11_customCSRs_csrs_3_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_11_customCSRs_csrs_3_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_11_customCSRs_csrs_3_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_11_customCSRs_csrs_3_value, // @[LazyRoCC.scala:78:14]
input io_ptw_12_req_ready, // @[LazyRoCC.scala:78:14]
output io_ptw_12_req_valid, // @[LazyRoCC.scala:78:14]
output [26:0] io_ptw_12_req_bits_bits_addr, // @[LazyRoCC.scala:78:14]
output io_ptw_12_req_bits_bits_need_gpa, // @[LazyRoCC.scala:78:14]
input io_ptw_12_resp_valid, // @[LazyRoCC.scala:78:14]
input io_ptw_12_resp_bits_ae_ptw, // @[LazyRoCC.scala:78:14]
input io_ptw_12_resp_bits_ae_final, // @[LazyRoCC.scala:78:14]
input io_ptw_12_resp_bits_pf, // @[LazyRoCC.scala:78:14]
input io_ptw_12_resp_bits_gf, // @[LazyRoCC.scala:78:14]
input io_ptw_12_resp_bits_hr, // @[LazyRoCC.scala:78:14]
input io_ptw_12_resp_bits_hw, // @[LazyRoCC.scala:78:14]
input io_ptw_12_resp_bits_hx, // @[LazyRoCC.scala:78:14]
input [9:0] io_ptw_12_resp_bits_pte_reserved_for_future, // @[LazyRoCC.scala:78:14]
input [43:0] io_ptw_12_resp_bits_pte_ppn, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_12_resp_bits_pte_reserved_for_software, // @[LazyRoCC.scala:78:14]
input io_ptw_12_resp_bits_pte_d, // @[LazyRoCC.scala:78:14]
input io_ptw_12_resp_bits_pte_a, // @[LazyRoCC.scala:78:14]
input io_ptw_12_resp_bits_pte_g, // @[LazyRoCC.scala:78:14]
input io_ptw_12_resp_bits_pte_u, // @[LazyRoCC.scala:78:14]
input io_ptw_12_resp_bits_pte_x, // @[LazyRoCC.scala:78:14]
input io_ptw_12_resp_bits_pte_w, // @[LazyRoCC.scala:78:14]
input io_ptw_12_resp_bits_pte_r, // @[LazyRoCC.scala:78:14]
input io_ptw_12_resp_bits_pte_v, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_12_resp_bits_level, // @[LazyRoCC.scala:78:14]
input io_ptw_12_resp_bits_homogeneous, // @[LazyRoCC.scala:78:14]
input io_ptw_12_resp_bits_gpa_valid, // @[LazyRoCC.scala:78:14]
input [38:0] io_ptw_12_resp_bits_gpa_bits, // @[LazyRoCC.scala:78:14]
input io_ptw_12_resp_bits_gpa_is_pte, // @[LazyRoCC.scala:78:14]
input [3:0] io_ptw_12_ptbr_mode, // @[LazyRoCC.scala:78:14]
input [43:0] io_ptw_12_ptbr_ppn, // @[LazyRoCC.scala:78:14]
input io_ptw_12_status_debug, // @[LazyRoCC.scala:78:14]
input io_ptw_12_status_cease, // @[LazyRoCC.scala:78:14]
input io_ptw_12_status_wfi, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_12_status_isa, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_12_status_dprv, // @[LazyRoCC.scala:78:14]
input io_ptw_12_status_dv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_12_status_prv, // @[LazyRoCC.scala:78:14]
input io_ptw_12_status_v, // @[LazyRoCC.scala:78:14]
input io_ptw_12_status_mpv, // @[LazyRoCC.scala:78:14]
input io_ptw_12_status_gva, // @[LazyRoCC.scala:78:14]
input io_ptw_12_status_tsr, // @[LazyRoCC.scala:78:14]
input io_ptw_12_status_tw, // @[LazyRoCC.scala:78:14]
input io_ptw_12_status_tvm, // @[LazyRoCC.scala:78:14]
input io_ptw_12_status_mxr, // @[LazyRoCC.scala:78:14]
input io_ptw_12_status_sum, // @[LazyRoCC.scala:78:14]
input io_ptw_12_status_mprv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_12_status_fs, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_12_status_mpp, // @[LazyRoCC.scala:78:14]
input io_ptw_12_status_spp, // @[LazyRoCC.scala:78:14]
input io_ptw_12_status_mpie, // @[LazyRoCC.scala:78:14]
input io_ptw_12_status_spie, // @[LazyRoCC.scala:78:14]
input io_ptw_12_status_mie, // @[LazyRoCC.scala:78:14]
input io_ptw_12_status_sie, // @[LazyRoCC.scala:78:14]
input io_ptw_12_hstatus_spvp, // @[LazyRoCC.scala:78:14]
input io_ptw_12_hstatus_spv, // @[LazyRoCC.scala:78:14]
input io_ptw_12_hstatus_gva, // @[LazyRoCC.scala:78:14]
input io_ptw_12_gstatus_debug, // @[LazyRoCC.scala:78:14]
input io_ptw_12_gstatus_cease, // @[LazyRoCC.scala:78:14]
input io_ptw_12_gstatus_wfi, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_12_gstatus_isa, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_12_gstatus_dprv, // @[LazyRoCC.scala:78:14]
input io_ptw_12_gstatus_dv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_12_gstatus_prv, // @[LazyRoCC.scala:78:14]
input io_ptw_12_gstatus_v, // @[LazyRoCC.scala:78:14]
input [22:0] io_ptw_12_gstatus_zero2, // @[LazyRoCC.scala:78:14]
input io_ptw_12_gstatus_mpv, // @[LazyRoCC.scala:78:14]
input io_ptw_12_gstatus_gva, // @[LazyRoCC.scala:78:14]
input io_ptw_12_gstatus_mbe, // @[LazyRoCC.scala:78:14]
input io_ptw_12_gstatus_sbe, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_12_gstatus_sxl, // @[LazyRoCC.scala:78:14]
input [7:0] io_ptw_12_gstatus_zero1, // @[LazyRoCC.scala:78:14]
input io_ptw_12_gstatus_tsr, // @[LazyRoCC.scala:78:14]
input io_ptw_12_gstatus_tw, // @[LazyRoCC.scala:78:14]
input io_ptw_12_gstatus_tvm, // @[LazyRoCC.scala:78:14]
input io_ptw_12_gstatus_mxr, // @[LazyRoCC.scala:78:14]
input io_ptw_12_gstatus_sum, // @[LazyRoCC.scala:78:14]
input io_ptw_12_gstatus_mprv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_12_gstatus_fs, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_12_gstatus_mpp, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_12_gstatus_vs, // @[LazyRoCC.scala:78:14]
input io_ptw_12_gstatus_spp, // @[LazyRoCC.scala:78:14]
input io_ptw_12_gstatus_mpie, // @[LazyRoCC.scala:78:14]
input io_ptw_12_gstatus_ube, // @[LazyRoCC.scala:78:14]
input io_ptw_12_gstatus_spie, // @[LazyRoCC.scala:78:14]
input io_ptw_12_gstatus_upie, // @[LazyRoCC.scala:78:14]
input io_ptw_12_gstatus_mie, // @[LazyRoCC.scala:78:14]
input io_ptw_12_gstatus_hie, // @[LazyRoCC.scala:78:14]
input io_ptw_12_gstatus_sie, // @[LazyRoCC.scala:78:14]
input io_ptw_12_gstatus_uie, // @[LazyRoCC.scala:78:14]
input io_ptw_12_pmp_0_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_12_pmp_0_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_12_pmp_0_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_12_pmp_0_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_12_pmp_0_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_12_pmp_0_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_12_pmp_0_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_12_pmp_1_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_12_pmp_1_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_12_pmp_1_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_12_pmp_1_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_12_pmp_1_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_12_pmp_1_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_12_pmp_1_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_12_pmp_2_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_12_pmp_2_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_12_pmp_2_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_12_pmp_2_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_12_pmp_2_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_12_pmp_2_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_12_pmp_2_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_12_pmp_3_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_12_pmp_3_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_12_pmp_3_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_12_pmp_3_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_12_pmp_3_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_12_pmp_3_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_12_pmp_3_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_12_pmp_4_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_12_pmp_4_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_12_pmp_4_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_12_pmp_4_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_12_pmp_4_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_12_pmp_4_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_12_pmp_4_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_12_pmp_5_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_12_pmp_5_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_12_pmp_5_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_12_pmp_5_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_12_pmp_5_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_12_pmp_5_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_12_pmp_5_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_12_pmp_6_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_12_pmp_6_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_12_pmp_6_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_12_pmp_6_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_12_pmp_6_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_12_pmp_6_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_12_pmp_6_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_12_pmp_7_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_12_pmp_7_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_12_pmp_7_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_12_pmp_7_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_12_pmp_7_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_12_pmp_7_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_12_pmp_7_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_12_customCSRs_csrs_0_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_12_customCSRs_csrs_0_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_12_customCSRs_csrs_0_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_12_customCSRs_csrs_0_value, // @[LazyRoCC.scala:78:14]
input io_ptw_12_customCSRs_csrs_1_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_12_customCSRs_csrs_1_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_12_customCSRs_csrs_1_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_12_customCSRs_csrs_1_value, // @[LazyRoCC.scala:78:14]
input io_ptw_12_customCSRs_csrs_2_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_12_customCSRs_csrs_2_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_12_customCSRs_csrs_2_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_12_customCSRs_csrs_2_value, // @[LazyRoCC.scala:78:14]
input io_ptw_12_customCSRs_csrs_3_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_12_customCSRs_csrs_3_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_12_customCSRs_csrs_3_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_12_customCSRs_csrs_3_value, // @[LazyRoCC.scala:78:14]
input io_ptw_13_req_ready, // @[LazyRoCC.scala:78:14]
output io_ptw_13_req_valid, // @[LazyRoCC.scala:78:14]
output [26:0] io_ptw_13_req_bits_bits_addr, // @[LazyRoCC.scala:78:14]
output io_ptw_13_req_bits_bits_need_gpa, // @[LazyRoCC.scala:78:14]
input io_ptw_13_resp_valid, // @[LazyRoCC.scala:78:14]
input io_ptw_13_resp_bits_ae_ptw, // @[LazyRoCC.scala:78:14]
input io_ptw_13_resp_bits_ae_final, // @[LazyRoCC.scala:78:14]
input io_ptw_13_resp_bits_pf, // @[LazyRoCC.scala:78:14]
input io_ptw_13_resp_bits_gf, // @[LazyRoCC.scala:78:14]
input io_ptw_13_resp_bits_hr, // @[LazyRoCC.scala:78:14]
input io_ptw_13_resp_bits_hw, // @[LazyRoCC.scala:78:14]
input io_ptw_13_resp_bits_hx, // @[LazyRoCC.scala:78:14]
input [9:0] io_ptw_13_resp_bits_pte_reserved_for_future, // @[LazyRoCC.scala:78:14]
input [43:0] io_ptw_13_resp_bits_pte_ppn, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_13_resp_bits_pte_reserved_for_software, // @[LazyRoCC.scala:78:14]
input io_ptw_13_resp_bits_pte_d, // @[LazyRoCC.scala:78:14]
input io_ptw_13_resp_bits_pte_a, // @[LazyRoCC.scala:78:14]
input io_ptw_13_resp_bits_pte_g, // @[LazyRoCC.scala:78:14]
input io_ptw_13_resp_bits_pte_u, // @[LazyRoCC.scala:78:14]
input io_ptw_13_resp_bits_pte_x, // @[LazyRoCC.scala:78:14]
input io_ptw_13_resp_bits_pte_w, // @[LazyRoCC.scala:78:14]
input io_ptw_13_resp_bits_pte_r, // @[LazyRoCC.scala:78:14]
input io_ptw_13_resp_bits_pte_v, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_13_resp_bits_level, // @[LazyRoCC.scala:78:14]
input io_ptw_13_resp_bits_homogeneous, // @[LazyRoCC.scala:78:14]
input io_ptw_13_resp_bits_gpa_valid, // @[LazyRoCC.scala:78:14]
input [38:0] io_ptw_13_resp_bits_gpa_bits, // @[LazyRoCC.scala:78:14]
input io_ptw_13_resp_bits_gpa_is_pte, // @[LazyRoCC.scala:78:14]
input [3:0] io_ptw_13_ptbr_mode, // @[LazyRoCC.scala:78:14]
input [43:0] io_ptw_13_ptbr_ppn, // @[LazyRoCC.scala:78:14]
input io_ptw_13_status_debug, // @[LazyRoCC.scala:78:14]
input io_ptw_13_status_cease, // @[LazyRoCC.scala:78:14]
input io_ptw_13_status_wfi, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_13_status_isa, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_13_status_dprv, // @[LazyRoCC.scala:78:14]
input io_ptw_13_status_dv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_13_status_prv, // @[LazyRoCC.scala:78:14]
input io_ptw_13_status_v, // @[LazyRoCC.scala:78:14]
input io_ptw_13_status_mpv, // @[LazyRoCC.scala:78:14]
input io_ptw_13_status_gva, // @[LazyRoCC.scala:78:14]
input io_ptw_13_status_tsr, // @[LazyRoCC.scala:78:14]
input io_ptw_13_status_tw, // @[LazyRoCC.scala:78:14]
input io_ptw_13_status_tvm, // @[LazyRoCC.scala:78:14]
input io_ptw_13_status_mxr, // @[LazyRoCC.scala:78:14]
input io_ptw_13_status_sum, // @[LazyRoCC.scala:78:14]
input io_ptw_13_status_mprv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_13_status_fs, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_13_status_mpp, // @[LazyRoCC.scala:78:14]
input io_ptw_13_status_spp, // @[LazyRoCC.scala:78:14]
input io_ptw_13_status_mpie, // @[LazyRoCC.scala:78:14]
input io_ptw_13_status_spie, // @[LazyRoCC.scala:78:14]
input io_ptw_13_status_mie, // @[LazyRoCC.scala:78:14]
input io_ptw_13_status_sie, // @[LazyRoCC.scala:78:14]
input io_ptw_13_hstatus_spvp, // @[LazyRoCC.scala:78:14]
input io_ptw_13_hstatus_spv, // @[LazyRoCC.scala:78:14]
input io_ptw_13_hstatus_gva, // @[LazyRoCC.scala:78:14]
input io_ptw_13_gstatus_debug, // @[LazyRoCC.scala:78:14]
input io_ptw_13_gstatus_cease, // @[LazyRoCC.scala:78:14]
input io_ptw_13_gstatus_wfi, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_13_gstatus_isa, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_13_gstatus_dprv, // @[LazyRoCC.scala:78:14]
input io_ptw_13_gstatus_dv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_13_gstatus_prv, // @[LazyRoCC.scala:78:14]
input io_ptw_13_gstatus_v, // @[LazyRoCC.scala:78:14]
input [22:0] io_ptw_13_gstatus_zero2, // @[LazyRoCC.scala:78:14]
input io_ptw_13_gstatus_mpv, // @[LazyRoCC.scala:78:14]
input io_ptw_13_gstatus_gva, // @[LazyRoCC.scala:78:14]
input io_ptw_13_gstatus_mbe, // @[LazyRoCC.scala:78:14]
input io_ptw_13_gstatus_sbe, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_13_gstatus_sxl, // @[LazyRoCC.scala:78:14]
input [7:0] io_ptw_13_gstatus_zero1, // @[LazyRoCC.scala:78:14]
input io_ptw_13_gstatus_tsr, // @[LazyRoCC.scala:78:14]
input io_ptw_13_gstatus_tw, // @[LazyRoCC.scala:78:14]
input io_ptw_13_gstatus_tvm, // @[LazyRoCC.scala:78:14]
input io_ptw_13_gstatus_mxr, // @[LazyRoCC.scala:78:14]
input io_ptw_13_gstatus_sum, // @[LazyRoCC.scala:78:14]
input io_ptw_13_gstatus_mprv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_13_gstatus_fs, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_13_gstatus_mpp, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_13_gstatus_vs, // @[LazyRoCC.scala:78:14]
input io_ptw_13_gstatus_spp, // @[LazyRoCC.scala:78:14]
input io_ptw_13_gstatus_mpie, // @[LazyRoCC.scala:78:14]
input io_ptw_13_gstatus_ube, // @[LazyRoCC.scala:78:14]
input io_ptw_13_gstatus_spie, // @[LazyRoCC.scala:78:14]
input io_ptw_13_gstatus_upie, // @[LazyRoCC.scala:78:14]
input io_ptw_13_gstatus_mie, // @[LazyRoCC.scala:78:14]
input io_ptw_13_gstatus_hie, // @[LazyRoCC.scala:78:14]
input io_ptw_13_gstatus_sie, // @[LazyRoCC.scala:78:14]
input io_ptw_13_gstatus_uie, // @[LazyRoCC.scala:78:14]
input io_ptw_13_pmp_0_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_13_pmp_0_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_13_pmp_0_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_13_pmp_0_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_13_pmp_0_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_13_pmp_0_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_13_pmp_0_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_13_pmp_1_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_13_pmp_1_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_13_pmp_1_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_13_pmp_1_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_13_pmp_1_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_13_pmp_1_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_13_pmp_1_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_13_pmp_2_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_13_pmp_2_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_13_pmp_2_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_13_pmp_2_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_13_pmp_2_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_13_pmp_2_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_13_pmp_2_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_13_pmp_3_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_13_pmp_3_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_13_pmp_3_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_13_pmp_3_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_13_pmp_3_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_13_pmp_3_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_13_pmp_3_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_13_pmp_4_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_13_pmp_4_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_13_pmp_4_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_13_pmp_4_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_13_pmp_4_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_13_pmp_4_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_13_pmp_4_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_13_pmp_5_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_13_pmp_5_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_13_pmp_5_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_13_pmp_5_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_13_pmp_5_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_13_pmp_5_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_13_pmp_5_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_13_pmp_6_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_13_pmp_6_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_13_pmp_6_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_13_pmp_6_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_13_pmp_6_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_13_pmp_6_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_13_pmp_6_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_13_pmp_7_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_13_pmp_7_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_13_pmp_7_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_13_pmp_7_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_13_pmp_7_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_13_pmp_7_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_13_pmp_7_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_13_customCSRs_csrs_0_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_13_customCSRs_csrs_0_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_13_customCSRs_csrs_0_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_13_customCSRs_csrs_0_value, // @[LazyRoCC.scala:78:14]
input io_ptw_13_customCSRs_csrs_1_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_13_customCSRs_csrs_1_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_13_customCSRs_csrs_1_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_13_customCSRs_csrs_1_value, // @[LazyRoCC.scala:78:14]
input io_ptw_13_customCSRs_csrs_2_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_13_customCSRs_csrs_2_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_13_customCSRs_csrs_2_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_13_customCSRs_csrs_2_value, // @[LazyRoCC.scala:78:14]
input io_ptw_13_customCSRs_csrs_3_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_13_customCSRs_csrs_3_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_13_customCSRs_csrs_3_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_13_customCSRs_csrs_3_value, // @[LazyRoCC.scala:78:14]
input io_ptw_14_req_ready, // @[LazyRoCC.scala:78:14]
output io_ptw_14_req_valid, // @[LazyRoCC.scala:78:14]
output [26:0] io_ptw_14_req_bits_bits_addr, // @[LazyRoCC.scala:78:14]
output io_ptw_14_req_bits_bits_need_gpa, // @[LazyRoCC.scala:78:14]
input io_ptw_14_resp_valid, // @[LazyRoCC.scala:78:14]
input io_ptw_14_resp_bits_ae_ptw, // @[LazyRoCC.scala:78:14]
input io_ptw_14_resp_bits_ae_final, // @[LazyRoCC.scala:78:14]
input io_ptw_14_resp_bits_pf, // @[LazyRoCC.scala:78:14]
input io_ptw_14_resp_bits_gf, // @[LazyRoCC.scala:78:14]
input io_ptw_14_resp_bits_hr, // @[LazyRoCC.scala:78:14]
input io_ptw_14_resp_bits_hw, // @[LazyRoCC.scala:78:14]
input io_ptw_14_resp_bits_hx, // @[LazyRoCC.scala:78:14]
input [9:0] io_ptw_14_resp_bits_pte_reserved_for_future, // @[LazyRoCC.scala:78:14]
input [43:0] io_ptw_14_resp_bits_pte_ppn, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_14_resp_bits_pte_reserved_for_software, // @[LazyRoCC.scala:78:14]
input io_ptw_14_resp_bits_pte_d, // @[LazyRoCC.scala:78:14]
input io_ptw_14_resp_bits_pte_a, // @[LazyRoCC.scala:78:14]
input io_ptw_14_resp_bits_pte_g, // @[LazyRoCC.scala:78:14]
input io_ptw_14_resp_bits_pte_u, // @[LazyRoCC.scala:78:14]
input io_ptw_14_resp_bits_pte_x, // @[LazyRoCC.scala:78:14]
input io_ptw_14_resp_bits_pte_w, // @[LazyRoCC.scala:78:14]
input io_ptw_14_resp_bits_pte_r, // @[LazyRoCC.scala:78:14]
input io_ptw_14_resp_bits_pte_v, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_14_resp_bits_level, // @[LazyRoCC.scala:78:14]
input io_ptw_14_resp_bits_homogeneous, // @[LazyRoCC.scala:78:14]
input io_ptw_14_resp_bits_gpa_valid, // @[LazyRoCC.scala:78:14]
input [38:0] io_ptw_14_resp_bits_gpa_bits, // @[LazyRoCC.scala:78:14]
input io_ptw_14_resp_bits_gpa_is_pte, // @[LazyRoCC.scala:78:14]
input [3:0] io_ptw_14_ptbr_mode, // @[LazyRoCC.scala:78:14]
input [43:0] io_ptw_14_ptbr_ppn, // @[LazyRoCC.scala:78:14]
input io_ptw_14_status_debug, // @[LazyRoCC.scala:78:14]
input io_ptw_14_status_cease, // @[LazyRoCC.scala:78:14]
input io_ptw_14_status_wfi, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_14_status_isa, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_14_status_dprv, // @[LazyRoCC.scala:78:14]
input io_ptw_14_status_dv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_14_status_prv, // @[LazyRoCC.scala:78:14]
input io_ptw_14_status_v, // @[LazyRoCC.scala:78:14]
input io_ptw_14_status_mpv, // @[LazyRoCC.scala:78:14]
input io_ptw_14_status_gva, // @[LazyRoCC.scala:78:14]
input io_ptw_14_status_tsr, // @[LazyRoCC.scala:78:14]
input io_ptw_14_status_tw, // @[LazyRoCC.scala:78:14]
input io_ptw_14_status_tvm, // @[LazyRoCC.scala:78:14]
input io_ptw_14_status_mxr, // @[LazyRoCC.scala:78:14]
input io_ptw_14_status_sum, // @[LazyRoCC.scala:78:14]
input io_ptw_14_status_mprv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_14_status_fs, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_14_status_mpp, // @[LazyRoCC.scala:78:14]
input io_ptw_14_status_spp, // @[LazyRoCC.scala:78:14]
input io_ptw_14_status_mpie, // @[LazyRoCC.scala:78:14]
input io_ptw_14_status_spie, // @[LazyRoCC.scala:78:14]
input io_ptw_14_status_mie, // @[LazyRoCC.scala:78:14]
input io_ptw_14_status_sie, // @[LazyRoCC.scala:78:14]
input io_ptw_14_hstatus_spvp, // @[LazyRoCC.scala:78:14]
input io_ptw_14_hstatus_spv, // @[LazyRoCC.scala:78:14]
input io_ptw_14_hstatus_gva, // @[LazyRoCC.scala:78:14]
input io_ptw_14_gstatus_debug, // @[LazyRoCC.scala:78:14]
input io_ptw_14_gstatus_cease, // @[LazyRoCC.scala:78:14]
input io_ptw_14_gstatus_wfi, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_14_gstatus_isa, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_14_gstatus_dprv, // @[LazyRoCC.scala:78:14]
input io_ptw_14_gstatus_dv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_14_gstatus_prv, // @[LazyRoCC.scala:78:14]
input io_ptw_14_gstatus_v, // @[LazyRoCC.scala:78:14]
input [22:0] io_ptw_14_gstatus_zero2, // @[LazyRoCC.scala:78:14]
input io_ptw_14_gstatus_mpv, // @[LazyRoCC.scala:78:14]
input io_ptw_14_gstatus_gva, // @[LazyRoCC.scala:78:14]
input io_ptw_14_gstatus_mbe, // @[LazyRoCC.scala:78:14]
input io_ptw_14_gstatus_sbe, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_14_gstatus_sxl, // @[LazyRoCC.scala:78:14]
input [7:0] io_ptw_14_gstatus_zero1, // @[LazyRoCC.scala:78:14]
input io_ptw_14_gstatus_tsr, // @[LazyRoCC.scala:78:14]
input io_ptw_14_gstatus_tw, // @[LazyRoCC.scala:78:14]
input io_ptw_14_gstatus_tvm, // @[LazyRoCC.scala:78:14]
input io_ptw_14_gstatus_mxr, // @[LazyRoCC.scala:78:14]
input io_ptw_14_gstatus_sum, // @[LazyRoCC.scala:78:14]
input io_ptw_14_gstatus_mprv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_14_gstatus_fs, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_14_gstatus_mpp, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_14_gstatus_vs, // @[LazyRoCC.scala:78:14]
input io_ptw_14_gstatus_spp, // @[LazyRoCC.scala:78:14]
input io_ptw_14_gstatus_mpie, // @[LazyRoCC.scala:78:14]
input io_ptw_14_gstatus_ube, // @[LazyRoCC.scala:78:14]
input io_ptw_14_gstatus_spie, // @[LazyRoCC.scala:78:14]
input io_ptw_14_gstatus_upie, // @[LazyRoCC.scala:78:14]
input io_ptw_14_gstatus_mie, // @[LazyRoCC.scala:78:14]
input io_ptw_14_gstatus_hie, // @[LazyRoCC.scala:78:14]
input io_ptw_14_gstatus_sie, // @[LazyRoCC.scala:78:14]
input io_ptw_14_gstatus_uie, // @[LazyRoCC.scala:78:14]
input io_ptw_14_pmp_0_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_14_pmp_0_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_14_pmp_0_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_14_pmp_0_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_14_pmp_0_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_14_pmp_0_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_14_pmp_0_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_14_pmp_1_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_14_pmp_1_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_14_pmp_1_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_14_pmp_1_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_14_pmp_1_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_14_pmp_1_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_14_pmp_1_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_14_pmp_2_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_14_pmp_2_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_14_pmp_2_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_14_pmp_2_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_14_pmp_2_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_14_pmp_2_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_14_pmp_2_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_14_pmp_3_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_14_pmp_3_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_14_pmp_3_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_14_pmp_3_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_14_pmp_3_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_14_pmp_3_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_14_pmp_3_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_14_pmp_4_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_14_pmp_4_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_14_pmp_4_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_14_pmp_4_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_14_pmp_4_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_14_pmp_4_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_14_pmp_4_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_14_pmp_5_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_14_pmp_5_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_14_pmp_5_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_14_pmp_5_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_14_pmp_5_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_14_pmp_5_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_14_pmp_5_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_14_pmp_6_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_14_pmp_6_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_14_pmp_6_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_14_pmp_6_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_14_pmp_6_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_14_pmp_6_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_14_pmp_6_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_14_pmp_7_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_14_pmp_7_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_14_pmp_7_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_14_pmp_7_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_14_pmp_7_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_14_pmp_7_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_14_pmp_7_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_14_customCSRs_csrs_0_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_14_customCSRs_csrs_0_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_14_customCSRs_csrs_0_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_14_customCSRs_csrs_0_value, // @[LazyRoCC.scala:78:14]
input io_ptw_14_customCSRs_csrs_1_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_14_customCSRs_csrs_1_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_14_customCSRs_csrs_1_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_14_customCSRs_csrs_1_value, // @[LazyRoCC.scala:78:14]
input io_ptw_14_customCSRs_csrs_2_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_14_customCSRs_csrs_2_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_14_customCSRs_csrs_2_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_14_customCSRs_csrs_2_value, // @[LazyRoCC.scala:78:14]
input io_ptw_14_customCSRs_csrs_3_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_14_customCSRs_csrs_3_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_14_customCSRs_csrs_3_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_14_customCSRs_csrs_3_value, // @[LazyRoCC.scala:78:14]
input io_ptw_15_req_ready, // @[LazyRoCC.scala:78:14]
output io_ptw_15_req_valid, // @[LazyRoCC.scala:78:14]
output [26:0] io_ptw_15_req_bits_bits_addr, // @[LazyRoCC.scala:78:14]
output io_ptw_15_req_bits_bits_need_gpa, // @[LazyRoCC.scala:78:14]
input io_ptw_15_resp_valid, // @[LazyRoCC.scala:78:14]
input io_ptw_15_resp_bits_ae_ptw, // @[LazyRoCC.scala:78:14]
input io_ptw_15_resp_bits_ae_final, // @[LazyRoCC.scala:78:14]
input io_ptw_15_resp_bits_pf, // @[LazyRoCC.scala:78:14]
input io_ptw_15_resp_bits_gf, // @[LazyRoCC.scala:78:14]
input io_ptw_15_resp_bits_hr, // @[LazyRoCC.scala:78:14]
input io_ptw_15_resp_bits_hw, // @[LazyRoCC.scala:78:14]
input io_ptw_15_resp_bits_hx, // @[LazyRoCC.scala:78:14]
input [9:0] io_ptw_15_resp_bits_pte_reserved_for_future, // @[LazyRoCC.scala:78:14]
input [43:0] io_ptw_15_resp_bits_pte_ppn, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_15_resp_bits_pte_reserved_for_software, // @[LazyRoCC.scala:78:14]
input io_ptw_15_resp_bits_pte_d, // @[LazyRoCC.scala:78:14]
input io_ptw_15_resp_bits_pte_a, // @[LazyRoCC.scala:78:14]
input io_ptw_15_resp_bits_pte_g, // @[LazyRoCC.scala:78:14]
input io_ptw_15_resp_bits_pte_u, // @[LazyRoCC.scala:78:14]
input io_ptw_15_resp_bits_pte_x, // @[LazyRoCC.scala:78:14]
input io_ptw_15_resp_bits_pte_w, // @[LazyRoCC.scala:78:14]
input io_ptw_15_resp_bits_pte_r, // @[LazyRoCC.scala:78:14]
input io_ptw_15_resp_bits_pte_v, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_15_resp_bits_level, // @[LazyRoCC.scala:78:14]
input io_ptw_15_resp_bits_homogeneous, // @[LazyRoCC.scala:78:14]
input io_ptw_15_resp_bits_gpa_valid, // @[LazyRoCC.scala:78:14]
input [38:0] io_ptw_15_resp_bits_gpa_bits, // @[LazyRoCC.scala:78:14]
input io_ptw_15_resp_bits_gpa_is_pte, // @[LazyRoCC.scala:78:14]
input [3:0] io_ptw_15_ptbr_mode, // @[LazyRoCC.scala:78:14]
input [43:0] io_ptw_15_ptbr_ppn, // @[LazyRoCC.scala:78:14]
input io_ptw_15_status_debug, // @[LazyRoCC.scala:78:14]
input io_ptw_15_status_cease, // @[LazyRoCC.scala:78:14]
input io_ptw_15_status_wfi, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_15_status_isa, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_15_status_dprv, // @[LazyRoCC.scala:78:14]
input io_ptw_15_status_dv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_15_status_prv, // @[LazyRoCC.scala:78:14]
input io_ptw_15_status_v, // @[LazyRoCC.scala:78:14]
input io_ptw_15_status_mpv, // @[LazyRoCC.scala:78:14]
input io_ptw_15_status_gva, // @[LazyRoCC.scala:78:14]
input io_ptw_15_status_tsr, // @[LazyRoCC.scala:78:14]
input io_ptw_15_status_tw, // @[LazyRoCC.scala:78:14]
input io_ptw_15_status_tvm, // @[LazyRoCC.scala:78:14]
input io_ptw_15_status_mxr, // @[LazyRoCC.scala:78:14]
input io_ptw_15_status_sum, // @[LazyRoCC.scala:78:14]
input io_ptw_15_status_mprv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_15_status_fs, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_15_status_mpp, // @[LazyRoCC.scala:78:14]
input io_ptw_15_status_spp, // @[LazyRoCC.scala:78:14]
input io_ptw_15_status_mpie, // @[LazyRoCC.scala:78:14]
input io_ptw_15_status_spie, // @[LazyRoCC.scala:78:14]
input io_ptw_15_status_mie, // @[LazyRoCC.scala:78:14]
input io_ptw_15_status_sie, // @[LazyRoCC.scala:78:14]
input io_ptw_15_hstatus_spvp, // @[LazyRoCC.scala:78:14]
input io_ptw_15_hstatus_spv, // @[LazyRoCC.scala:78:14]
input io_ptw_15_hstatus_gva, // @[LazyRoCC.scala:78:14]
input io_ptw_15_gstatus_debug, // @[LazyRoCC.scala:78:14]
input io_ptw_15_gstatus_cease, // @[LazyRoCC.scala:78:14]
input io_ptw_15_gstatus_wfi, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_15_gstatus_isa, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_15_gstatus_dprv, // @[LazyRoCC.scala:78:14]
input io_ptw_15_gstatus_dv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_15_gstatus_prv, // @[LazyRoCC.scala:78:14]
input io_ptw_15_gstatus_v, // @[LazyRoCC.scala:78:14]
input [22:0] io_ptw_15_gstatus_zero2, // @[LazyRoCC.scala:78:14]
input io_ptw_15_gstatus_mpv, // @[LazyRoCC.scala:78:14]
input io_ptw_15_gstatus_gva, // @[LazyRoCC.scala:78:14]
input io_ptw_15_gstatus_mbe, // @[LazyRoCC.scala:78:14]
input io_ptw_15_gstatus_sbe, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_15_gstatus_sxl, // @[LazyRoCC.scala:78:14]
input [7:0] io_ptw_15_gstatus_zero1, // @[LazyRoCC.scala:78:14]
input io_ptw_15_gstatus_tsr, // @[LazyRoCC.scala:78:14]
input io_ptw_15_gstatus_tw, // @[LazyRoCC.scala:78:14]
input io_ptw_15_gstatus_tvm, // @[LazyRoCC.scala:78:14]
input io_ptw_15_gstatus_mxr, // @[LazyRoCC.scala:78:14]
input io_ptw_15_gstatus_sum, // @[LazyRoCC.scala:78:14]
input io_ptw_15_gstatus_mprv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_15_gstatus_fs, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_15_gstatus_mpp, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_15_gstatus_vs, // @[LazyRoCC.scala:78:14]
input io_ptw_15_gstatus_spp, // @[LazyRoCC.scala:78:14]
input io_ptw_15_gstatus_mpie, // @[LazyRoCC.scala:78:14]
input io_ptw_15_gstatus_ube, // @[LazyRoCC.scala:78:14]
input io_ptw_15_gstatus_spie, // @[LazyRoCC.scala:78:14]
input io_ptw_15_gstatus_upie, // @[LazyRoCC.scala:78:14]
input io_ptw_15_gstatus_mie, // @[LazyRoCC.scala:78:14]
input io_ptw_15_gstatus_hie, // @[LazyRoCC.scala:78:14]
input io_ptw_15_gstatus_sie, // @[LazyRoCC.scala:78:14]
input io_ptw_15_gstatus_uie, // @[LazyRoCC.scala:78:14]
input io_ptw_15_pmp_0_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_15_pmp_0_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_15_pmp_0_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_15_pmp_0_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_15_pmp_0_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_15_pmp_0_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_15_pmp_0_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_15_pmp_1_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_15_pmp_1_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_15_pmp_1_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_15_pmp_1_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_15_pmp_1_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_15_pmp_1_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_15_pmp_1_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_15_pmp_2_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_15_pmp_2_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_15_pmp_2_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_15_pmp_2_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_15_pmp_2_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_15_pmp_2_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_15_pmp_2_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_15_pmp_3_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_15_pmp_3_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_15_pmp_3_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_15_pmp_3_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_15_pmp_3_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_15_pmp_3_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_15_pmp_3_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_15_pmp_4_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_15_pmp_4_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_15_pmp_4_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_15_pmp_4_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_15_pmp_4_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_15_pmp_4_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_15_pmp_4_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_15_pmp_5_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_15_pmp_5_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_15_pmp_5_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_15_pmp_5_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_15_pmp_5_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_15_pmp_5_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_15_pmp_5_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_15_pmp_6_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_15_pmp_6_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_15_pmp_6_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_15_pmp_6_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_15_pmp_6_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_15_pmp_6_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_15_pmp_6_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_15_pmp_7_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_15_pmp_7_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_15_pmp_7_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_15_pmp_7_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_15_pmp_7_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_15_pmp_7_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_15_pmp_7_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_15_customCSRs_csrs_0_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_15_customCSRs_csrs_0_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_15_customCSRs_csrs_0_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_15_customCSRs_csrs_0_value, // @[LazyRoCC.scala:78:14]
input io_ptw_15_customCSRs_csrs_1_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_15_customCSRs_csrs_1_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_15_customCSRs_csrs_1_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_15_customCSRs_csrs_1_value, // @[LazyRoCC.scala:78:14]
input io_ptw_15_customCSRs_csrs_2_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_15_customCSRs_csrs_2_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_15_customCSRs_csrs_2_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_15_customCSRs_csrs_2_value, // @[LazyRoCC.scala:78:14]
input io_ptw_15_customCSRs_csrs_3_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_15_customCSRs_csrs_3_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_15_customCSRs_csrs_3_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_15_customCSRs_csrs_3_value, // @[LazyRoCC.scala:78:14]
input io_ptw_16_req_ready, // @[LazyRoCC.scala:78:14]
output io_ptw_16_req_valid, // @[LazyRoCC.scala:78:14]
output [26:0] io_ptw_16_req_bits_bits_addr, // @[LazyRoCC.scala:78:14]
output io_ptw_16_req_bits_bits_need_gpa, // @[LazyRoCC.scala:78:14]
input io_ptw_16_resp_valid, // @[LazyRoCC.scala:78:14]
input io_ptw_16_resp_bits_ae_ptw, // @[LazyRoCC.scala:78:14]
input io_ptw_16_resp_bits_ae_final, // @[LazyRoCC.scala:78:14]
input io_ptw_16_resp_bits_pf, // @[LazyRoCC.scala:78:14]
input io_ptw_16_resp_bits_gf, // @[LazyRoCC.scala:78:14]
input io_ptw_16_resp_bits_hr, // @[LazyRoCC.scala:78:14]
input io_ptw_16_resp_bits_hw, // @[LazyRoCC.scala:78:14]
input io_ptw_16_resp_bits_hx, // @[LazyRoCC.scala:78:14]
input [9:0] io_ptw_16_resp_bits_pte_reserved_for_future, // @[LazyRoCC.scala:78:14]
input [43:0] io_ptw_16_resp_bits_pte_ppn, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_16_resp_bits_pte_reserved_for_software, // @[LazyRoCC.scala:78:14]
input io_ptw_16_resp_bits_pte_d, // @[LazyRoCC.scala:78:14]
input io_ptw_16_resp_bits_pte_a, // @[LazyRoCC.scala:78:14]
input io_ptw_16_resp_bits_pte_g, // @[LazyRoCC.scala:78:14]
input io_ptw_16_resp_bits_pte_u, // @[LazyRoCC.scala:78:14]
input io_ptw_16_resp_bits_pte_x, // @[LazyRoCC.scala:78:14]
input io_ptw_16_resp_bits_pte_w, // @[LazyRoCC.scala:78:14]
input io_ptw_16_resp_bits_pte_r, // @[LazyRoCC.scala:78:14]
input io_ptw_16_resp_bits_pte_v, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_16_resp_bits_level, // @[LazyRoCC.scala:78:14]
input io_ptw_16_resp_bits_homogeneous, // @[LazyRoCC.scala:78:14]
input io_ptw_16_resp_bits_gpa_valid, // @[LazyRoCC.scala:78:14]
input [38:0] io_ptw_16_resp_bits_gpa_bits, // @[LazyRoCC.scala:78:14]
input io_ptw_16_resp_bits_gpa_is_pte, // @[LazyRoCC.scala:78:14]
input [3:0] io_ptw_16_ptbr_mode, // @[LazyRoCC.scala:78:14]
input [43:0] io_ptw_16_ptbr_ppn, // @[LazyRoCC.scala:78:14]
input io_ptw_16_status_debug, // @[LazyRoCC.scala:78:14]
input io_ptw_16_status_cease, // @[LazyRoCC.scala:78:14]
input io_ptw_16_status_wfi, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_16_status_isa, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_16_status_dprv, // @[LazyRoCC.scala:78:14]
input io_ptw_16_status_dv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_16_status_prv, // @[LazyRoCC.scala:78:14]
input io_ptw_16_status_v, // @[LazyRoCC.scala:78:14]
input io_ptw_16_status_mpv, // @[LazyRoCC.scala:78:14]
input io_ptw_16_status_gva, // @[LazyRoCC.scala:78:14]
input io_ptw_16_status_tsr, // @[LazyRoCC.scala:78:14]
input io_ptw_16_status_tw, // @[LazyRoCC.scala:78:14]
input io_ptw_16_status_tvm, // @[LazyRoCC.scala:78:14]
input io_ptw_16_status_mxr, // @[LazyRoCC.scala:78:14]
input io_ptw_16_status_sum, // @[LazyRoCC.scala:78:14]
input io_ptw_16_status_mprv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_16_status_fs, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_16_status_mpp, // @[LazyRoCC.scala:78:14]
input io_ptw_16_status_spp, // @[LazyRoCC.scala:78:14]
input io_ptw_16_status_mpie, // @[LazyRoCC.scala:78:14]
input io_ptw_16_status_spie, // @[LazyRoCC.scala:78:14]
input io_ptw_16_status_mie, // @[LazyRoCC.scala:78:14]
input io_ptw_16_status_sie, // @[LazyRoCC.scala:78:14]
input io_ptw_16_hstatus_spvp, // @[LazyRoCC.scala:78:14]
input io_ptw_16_hstatus_spv, // @[LazyRoCC.scala:78:14]
input io_ptw_16_hstatus_gva, // @[LazyRoCC.scala:78:14]
input io_ptw_16_gstatus_debug, // @[LazyRoCC.scala:78:14]
input io_ptw_16_gstatus_cease, // @[LazyRoCC.scala:78:14]
input io_ptw_16_gstatus_wfi, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_16_gstatus_isa, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_16_gstatus_dprv, // @[LazyRoCC.scala:78:14]
input io_ptw_16_gstatus_dv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_16_gstatus_prv, // @[LazyRoCC.scala:78:14]
input io_ptw_16_gstatus_v, // @[LazyRoCC.scala:78:14]
input [22:0] io_ptw_16_gstatus_zero2, // @[LazyRoCC.scala:78:14]
input io_ptw_16_gstatus_mpv, // @[LazyRoCC.scala:78:14]
input io_ptw_16_gstatus_gva, // @[LazyRoCC.scala:78:14]
input io_ptw_16_gstatus_mbe, // @[LazyRoCC.scala:78:14]
input io_ptw_16_gstatus_sbe, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_16_gstatus_sxl, // @[LazyRoCC.scala:78:14]
input [7:0] io_ptw_16_gstatus_zero1, // @[LazyRoCC.scala:78:14]
input io_ptw_16_gstatus_tsr, // @[LazyRoCC.scala:78:14]
input io_ptw_16_gstatus_tw, // @[LazyRoCC.scala:78:14]
input io_ptw_16_gstatus_tvm, // @[LazyRoCC.scala:78:14]
input io_ptw_16_gstatus_mxr, // @[LazyRoCC.scala:78:14]
input io_ptw_16_gstatus_sum, // @[LazyRoCC.scala:78:14]
input io_ptw_16_gstatus_mprv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_16_gstatus_fs, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_16_gstatus_mpp, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_16_gstatus_vs, // @[LazyRoCC.scala:78:14]
input io_ptw_16_gstatus_spp, // @[LazyRoCC.scala:78:14]
input io_ptw_16_gstatus_mpie, // @[LazyRoCC.scala:78:14]
input io_ptw_16_gstatus_ube, // @[LazyRoCC.scala:78:14]
input io_ptw_16_gstatus_spie, // @[LazyRoCC.scala:78:14]
input io_ptw_16_gstatus_upie, // @[LazyRoCC.scala:78:14]
input io_ptw_16_gstatus_mie, // @[LazyRoCC.scala:78:14]
input io_ptw_16_gstatus_hie, // @[LazyRoCC.scala:78:14]
input io_ptw_16_gstatus_sie, // @[LazyRoCC.scala:78:14]
input io_ptw_16_gstatus_uie, // @[LazyRoCC.scala:78:14]
input io_ptw_16_pmp_0_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_16_pmp_0_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_16_pmp_0_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_16_pmp_0_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_16_pmp_0_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_16_pmp_0_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_16_pmp_0_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_16_pmp_1_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_16_pmp_1_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_16_pmp_1_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_16_pmp_1_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_16_pmp_1_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_16_pmp_1_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_16_pmp_1_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_16_pmp_2_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_16_pmp_2_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_16_pmp_2_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_16_pmp_2_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_16_pmp_2_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_16_pmp_2_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_16_pmp_2_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_16_pmp_3_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_16_pmp_3_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_16_pmp_3_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_16_pmp_3_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_16_pmp_3_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_16_pmp_3_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_16_pmp_3_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_16_pmp_4_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_16_pmp_4_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_16_pmp_4_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_16_pmp_4_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_16_pmp_4_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_16_pmp_4_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_16_pmp_4_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_16_pmp_5_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_16_pmp_5_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_16_pmp_5_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_16_pmp_5_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_16_pmp_5_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_16_pmp_5_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_16_pmp_5_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_16_pmp_6_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_16_pmp_6_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_16_pmp_6_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_16_pmp_6_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_16_pmp_6_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_16_pmp_6_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_16_pmp_6_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_16_pmp_7_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_16_pmp_7_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_16_pmp_7_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_16_pmp_7_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_16_pmp_7_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_16_pmp_7_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_16_pmp_7_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_16_customCSRs_csrs_0_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_16_customCSRs_csrs_0_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_16_customCSRs_csrs_0_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_16_customCSRs_csrs_0_value, // @[LazyRoCC.scala:78:14]
input io_ptw_16_customCSRs_csrs_1_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_16_customCSRs_csrs_1_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_16_customCSRs_csrs_1_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_16_customCSRs_csrs_1_value, // @[LazyRoCC.scala:78:14]
input io_ptw_16_customCSRs_csrs_2_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_16_customCSRs_csrs_2_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_16_customCSRs_csrs_2_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_16_customCSRs_csrs_2_value, // @[LazyRoCC.scala:78:14]
input io_ptw_16_customCSRs_csrs_3_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_16_customCSRs_csrs_3_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_16_customCSRs_csrs_3_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_16_customCSRs_csrs_3_value, // @[LazyRoCC.scala:78:14]
input io_ptw_17_req_ready, // @[LazyRoCC.scala:78:14]
output io_ptw_17_req_valid, // @[LazyRoCC.scala:78:14]
output [26:0] io_ptw_17_req_bits_bits_addr, // @[LazyRoCC.scala:78:14]
output io_ptw_17_req_bits_bits_need_gpa, // @[LazyRoCC.scala:78:14]
input io_ptw_17_resp_valid, // @[LazyRoCC.scala:78:14]
input io_ptw_17_resp_bits_ae_ptw, // @[LazyRoCC.scala:78:14]
input io_ptw_17_resp_bits_ae_final, // @[LazyRoCC.scala:78:14]
input io_ptw_17_resp_bits_pf, // @[LazyRoCC.scala:78:14]
input io_ptw_17_resp_bits_gf, // @[LazyRoCC.scala:78:14]
input io_ptw_17_resp_bits_hr, // @[LazyRoCC.scala:78:14]
input io_ptw_17_resp_bits_hw, // @[LazyRoCC.scala:78:14]
input io_ptw_17_resp_bits_hx, // @[LazyRoCC.scala:78:14]
input [9:0] io_ptw_17_resp_bits_pte_reserved_for_future, // @[LazyRoCC.scala:78:14]
input [43:0] io_ptw_17_resp_bits_pte_ppn, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_17_resp_bits_pte_reserved_for_software, // @[LazyRoCC.scala:78:14]
input io_ptw_17_resp_bits_pte_d, // @[LazyRoCC.scala:78:14]
input io_ptw_17_resp_bits_pte_a, // @[LazyRoCC.scala:78:14]
input io_ptw_17_resp_bits_pte_g, // @[LazyRoCC.scala:78:14]
input io_ptw_17_resp_bits_pte_u, // @[LazyRoCC.scala:78:14]
input io_ptw_17_resp_bits_pte_x, // @[LazyRoCC.scala:78:14]
input io_ptw_17_resp_bits_pte_w, // @[LazyRoCC.scala:78:14]
input io_ptw_17_resp_bits_pte_r, // @[LazyRoCC.scala:78:14]
input io_ptw_17_resp_bits_pte_v, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_17_resp_bits_level, // @[LazyRoCC.scala:78:14]
input io_ptw_17_resp_bits_homogeneous, // @[LazyRoCC.scala:78:14]
input io_ptw_17_resp_bits_gpa_valid, // @[LazyRoCC.scala:78:14]
input [38:0] io_ptw_17_resp_bits_gpa_bits, // @[LazyRoCC.scala:78:14]
input io_ptw_17_resp_bits_gpa_is_pte, // @[LazyRoCC.scala:78:14]
input [3:0] io_ptw_17_ptbr_mode, // @[LazyRoCC.scala:78:14]
input [43:0] io_ptw_17_ptbr_ppn, // @[LazyRoCC.scala:78:14]
input io_ptw_17_status_debug, // @[LazyRoCC.scala:78:14]
input io_ptw_17_status_cease, // @[LazyRoCC.scala:78:14]
input io_ptw_17_status_wfi, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_17_status_isa, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_17_status_dprv, // @[LazyRoCC.scala:78:14]
input io_ptw_17_status_dv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_17_status_prv, // @[LazyRoCC.scala:78:14]
input io_ptw_17_status_v, // @[LazyRoCC.scala:78:14]
input io_ptw_17_status_mpv, // @[LazyRoCC.scala:78:14]
input io_ptw_17_status_gva, // @[LazyRoCC.scala:78:14]
input io_ptw_17_status_tsr, // @[LazyRoCC.scala:78:14]
input io_ptw_17_status_tw, // @[LazyRoCC.scala:78:14]
input io_ptw_17_status_tvm, // @[LazyRoCC.scala:78:14]
input io_ptw_17_status_mxr, // @[LazyRoCC.scala:78:14]
input io_ptw_17_status_sum, // @[LazyRoCC.scala:78:14]
input io_ptw_17_status_mprv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_17_status_fs, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_17_status_mpp, // @[LazyRoCC.scala:78:14]
input io_ptw_17_status_spp, // @[LazyRoCC.scala:78:14]
input io_ptw_17_status_mpie, // @[LazyRoCC.scala:78:14]
input io_ptw_17_status_spie, // @[LazyRoCC.scala:78:14]
input io_ptw_17_status_mie, // @[LazyRoCC.scala:78:14]
input io_ptw_17_status_sie, // @[LazyRoCC.scala:78:14]
input io_ptw_17_hstatus_spvp, // @[LazyRoCC.scala:78:14]
input io_ptw_17_hstatus_spv, // @[LazyRoCC.scala:78:14]
input io_ptw_17_hstatus_gva, // @[LazyRoCC.scala:78:14]
input io_ptw_17_gstatus_debug, // @[LazyRoCC.scala:78:14]
input io_ptw_17_gstatus_cease, // @[LazyRoCC.scala:78:14]
input io_ptw_17_gstatus_wfi, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_17_gstatus_isa, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_17_gstatus_dprv, // @[LazyRoCC.scala:78:14]
input io_ptw_17_gstatus_dv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_17_gstatus_prv, // @[LazyRoCC.scala:78:14]
input io_ptw_17_gstatus_v, // @[LazyRoCC.scala:78:14]
input [22:0] io_ptw_17_gstatus_zero2, // @[LazyRoCC.scala:78:14]
input io_ptw_17_gstatus_mpv, // @[LazyRoCC.scala:78:14]
input io_ptw_17_gstatus_gva, // @[LazyRoCC.scala:78:14]
input io_ptw_17_gstatus_mbe, // @[LazyRoCC.scala:78:14]
input io_ptw_17_gstatus_sbe, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_17_gstatus_sxl, // @[LazyRoCC.scala:78:14]
input [7:0] io_ptw_17_gstatus_zero1, // @[LazyRoCC.scala:78:14]
input io_ptw_17_gstatus_tsr, // @[LazyRoCC.scala:78:14]
input io_ptw_17_gstatus_tw, // @[LazyRoCC.scala:78:14]
input io_ptw_17_gstatus_tvm, // @[LazyRoCC.scala:78:14]
input io_ptw_17_gstatus_mxr, // @[LazyRoCC.scala:78:14]
input io_ptw_17_gstatus_sum, // @[LazyRoCC.scala:78:14]
input io_ptw_17_gstatus_mprv, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_17_gstatus_fs, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_17_gstatus_mpp, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_17_gstatus_vs, // @[LazyRoCC.scala:78:14]
input io_ptw_17_gstatus_spp, // @[LazyRoCC.scala:78:14]
input io_ptw_17_gstatus_mpie, // @[LazyRoCC.scala:78:14]
input io_ptw_17_gstatus_ube, // @[LazyRoCC.scala:78:14]
input io_ptw_17_gstatus_spie, // @[LazyRoCC.scala:78:14]
input io_ptw_17_gstatus_upie, // @[LazyRoCC.scala:78:14]
input io_ptw_17_gstatus_mie, // @[LazyRoCC.scala:78:14]
input io_ptw_17_gstatus_hie, // @[LazyRoCC.scala:78:14]
input io_ptw_17_gstatus_sie, // @[LazyRoCC.scala:78:14]
input io_ptw_17_gstatus_uie, // @[LazyRoCC.scala:78:14]
input io_ptw_17_pmp_0_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_17_pmp_0_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_17_pmp_0_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_17_pmp_0_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_17_pmp_0_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_17_pmp_0_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_17_pmp_0_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_17_pmp_1_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_17_pmp_1_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_17_pmp_1_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_17_pmp_1_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_17_pmp_1_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_17_pmp_1_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_17_pmp_1_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_17_pmp_2_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_17_pmp_2_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_17_pmp_2_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_17_pmp_2_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_17_pmp_2_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_17_pmp_2_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_17_pmp_2_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_17_pmp_3_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_17_pmp_3_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_17_pmp_3_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_17_pmp_3_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_17_pmp_3_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_17_pmp_3_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_17_pmp_3_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_17_pmp_4_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_17_pmp_4_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_17_pmp_4_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_17_pmp_4_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_17_pmp_4_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_17_pmp_4_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_17_pmp_4_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_17_pmp_5_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_17_pmp_5_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_17_pmp_5_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_17_pmp_5_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_17_pmp_5_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_17_pmp_5_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_17_pmp_5_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_17_pmp_6_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_17_pmp_6_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_17_pmp_6_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_17_pmp_6_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_17_pmp_6_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_17_pmp_6_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_17_pmp_6_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_17_pmp_7_cfg_l, // @[LazyRoCC.scala:78:14]
input [1:0] io_ptw_17_pmp_7_cfg_a, // @[LazyRoCC.scala:78:14]
input io_ptw_17_pmp_7_cfg_x, // @[LazyRoCC.scala:78:14]
input io_ptw_17_pmp_7_cfg_w, // @[LazyRoCC.scala:78:14]
input io_ptw_17_pmp_7_cfg_r, // @[LazyRoCC.scala:78:14]
input [29:0] io_ptw_17_pmp_7_addr, // @[LazyRoCC.scala:78:14]
input [31:0] io_ptw_17_pmp_7_mask, // @[LazyRoCC.scala:78:14]
input io_ptw_17_customCSRs_csrs_0_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_17_customCSRs_csrs_0_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_17_customCSRs_csrs_0_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_17_customCSRs_csrs_0_value, // @[LazyRoCC.scala:78:14]
input io_ptw_17_customCSRs_csrs_1_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_17_customCSRs_csrs_1_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_17_customCSRs_csrs_1_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_17_customCSRs_csrs_1_value, // @[LazyRoCC.scala:78:14]
input io_ptw_17_customCSRs_csrs_2_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_17_customCSRs_csrs_2_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_17_customCSRs_csrs_2_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_17_customCSRs_csrs_2_value, // @[LazyRoCC.scala:78:14]
input io_ptw_17_customCSRs_csrs_3_ren, // @[LazyRoCC.scala:78:14]
input io_ptw_17_customCSRs_csrs_3_wen, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_17_customCSRs_csrs_3_wdata, // @[LazyRoCC.scala:78:14]
input [63:0] io_ptw_17_customCSRs_csrs_3_value // @[LazyRoCC.scala:78:14]
);
wire _seq_compressor_io_src_info_ready; // @[ZstdCompressor.scala:168:30]
wire _seq_compressor_io_dst_info_ready; // @[ZstdCompressor.scala:168:30]
wire _seq_compressor_io_bytes_written_valid; // @[ZstdCompressor.scala:168:30]
wire [63:0] _seq_compressor_io_bytes_written_bits; // @[ZstdCompressor.scala:168:30]
wire _seq_compressor_io_l2if_seq_reader_req_valid; // @[ZstdCompressor.scala:168:30]
wire [70:0] _seq_compressor_io_l2if_seq_reader_req_bits_addr; // @[ZstdCompressor.scala:168:30]
wire [2:0] _seq_compressor_io_l2if_seq_reader_req_bits_size; // @[ZstdCompressor.scala:168:30]
wire [255:0] _seq_compressor_io_l2if_seq_reader_req_bits_data; // @[ZstdCompressor.scala:168:30]
wire _seq_compressor_io_l2if_seq_reader_req_bits_cmd; // @[ZstdCompressor.scala:168:30]
wire _seq_compressor_io_l2if_seq_reader_resp_ready; // @[ZstdCompressor.scala:168:30]
wire _seq_compressor_io_l2if_seq_reader2_req_valid; // @[ZstdCompressor.scala:168:30]
wire [70:0] _seq_compressor_io_l2if_seq_reader2_req_bits_addr; // @[ZstdCompressor.scala:168:30]
wire [2:0] _seq_compressor_io_l2if_seq_reader2_req_bits_size; // @[ZstdCompressor.scala:168:30]
wire [255:0] _seq_compressor_io_l2if_seq_reader2_req_bits_data; // @[ZstdCompressor.scala:168:30]
wire _seq_compressor_io_l2if_seq_reader2_req_bits_cmd; // @[ZstdCompressor.scala:168:30]
wire _seq_compressor_io_l2if_seq_reader2_resp_ready; // @[ZstdCompressor.scala:168:30]
wire _seq_compressor_io_l2if_seq_writer_req_valid; // @[ZstdCompressor.scala:168:30]
wire [63:0] _seq_compressor_io_l2if_seq_writer_req_bits_addr; // @[ZstdCompressor.scala:168:30]
wire [2:0] _seq_compressor_io_l2if_seq_writer_req_bits_size; // @[ZstdCompressor.scala:168:30]
wire [255:0] _seq_compressor_io_l2if_seq_writer_req_bits_data; // @[ZstdCompressor.scala:168:30]
wire _seq_compressor_io_l2if_seq_writer_req_bits_cmd; // @[ZstdCompressor.scala:168:30]
wire _seq_compressor_io_l2if_seq_writer_resp_ready; // @[ZstdCompressor.scala:168:30]
wire _raw_block_encoder_io_src_info_ready; // @[ZstdCompressor.scala:161:33]
wire _raw_block_encoder_io_dst_info_ready; // @[ZstdCompressor.scala:161:33]
wire _raw_block_encoder_io_bytes_written_valid; // @[ZstdCompressor.scala:161:33]
wire [63:0] _raw_block_encoder_io_bytes_written_bits; // @[ZstdCompressor.scala:161:33]
wire _raw_block_encoder_io_l2if_reader_req_valid; // @[ZstdCompressor.scala:161:33]
wire [70:0] _raw_block_encoder_io_l2if_reader_req_bits_addr; // @[ZstdCompressor.scala:161:33]
wire _raw_block_encoder_io_l2if_reader_resp_ready; // @[ZstdCompressor.scala:161:33]
wire _raw_block_encoder_io_l2if_writer_req_valid; // @[ZstdCompressor.scala:161:33]
wire [63:0] _raw_block_encoder_io_l2if_writer_req_bits_addr; // @[ZstdCompressor.scala:161:33]
wire [2:0] _raw_block_encoder_io_l2if_writer_req_bits_size; // @[ZstdCompressor.scala:161:33]
wire [255:0] _raw_block_encoder_io_l2if_writer_req_bits_data; // @[ZstdCompressor.scala:161:33]
wire _raw_lit_encoder_io_l2io_read_req_valid; // @[ZstdCompressor.scala:154:31]
wire [70:0] _raw_lit_encoder_io_l2io_read_req_bits_addr; // @[ZstdCompressor.scala:154:31]
wire _raw_lit_encoder_io_l2io_read_resp_ready; // @[ZstdCompressor.scala:154:31]
wire _raw_lit_encoder_io_src_info_ready; // @[ZstdCompressor.scala:154:31]
wire _raw_lit_encoder_io_dst_info_ready; // @[ZstdCompressor.scala:154:31]
wire _raw_lit_encoder_io_l2io_write_req_valid; // @[ZstdCompressor.scala:154:31]
wire [63:0] _raw_lit_encoder_io_l2io_write_req_bits_addr; // @[ZstdCompressor.scala:154:31]
wire [2:0] _raw_lit_encoder_io_l2io_write_req_bits_size; // @[ZstdCompressor.scala:154:31]
wire [255:0] _raw_lit_encoder_io_l2io_write_req_bits_data; // @[ZstdCompressor.scala:154:31]
wire _raw_lit_encoder_io_bytes_written_valid; // @[ZstdCompressor.scala:154:31]
wire [63:0] _raw_lit_encoder_io_bytes_written_bits; // @[ZstdCompressor.scala:154:31]
wire _lit_compressor_io_src_info_ready; // @[ZstdCompressor.scala:140:30]
wire _lit_compressor_io_src_info2_ready; // @[ZstdCompressor.scala:140:30]
wire _lit_compressor_io_dst_info_ready; // @[ZstdCompressor.scala:140:30]
wire _lit_compressor_io_bytes_written_valid; // @[ZstdCompressor.scala:140:30]
wire [63:0] _lit_compressor_io_bytes_written_bits; // @[ZstdCompressor.scala:140:30]
wire _lit_compressor_io_l2if_lit_reader_req_valid; // @[ZstdCompressor.scala:140:30]
wire [70:0] _lit_compressor_io_l2if_lit_reader_req_bits_addr; // @[ZstdCompressor.scala:140:30]
wire [2:0] _lit_compressor_io_l2if_lit_reader_req_bits_size; // @[ZstdCompressor.scala:140:30]
wire [255:0] _lit_compressor_io_l2if_lit_reader_req_bits_data; // @[ZstdCompressor.scala:140:30]
wire _lit_compressor_io_l2if_lit_reader_req_bits_cmd; // @[ZstdCompressor.scala:140:30]
wire _lit_compressor_io_l2if_lit_reader_resp_ready; // @[ZstdCompressor.scala:140:30]
wire _lit_compressor_io_l2if_dic_reader_req_valid; // @[ZstdCompressor.scala:140:30]
wire [70:0] _lit_compressor_io_l2if_dic_reader_req_bits_addr; // @[ZstdCompressor.scala:140:30]
wire [2:0] _lit_compressor_io_l2if_dic_reader_req_bits_size; // @[ZstdCompressor.scala:140:30]
wire [255:0] _lit_compressor_io_l2if_dic_reader_req_bits_data; // @[ZstdCompressor.scala:140:30]
wire _lit_compressor_io_l2if_dic_reader_req_bits_cmd; // @[ZstdCompressor.scala:140:30]
wire _lit_compressor_io_l2if_dic_reader_resp_ready; // @[ZstdCompressor.scala:140:30]
wire _lit_compressor_io_l2if_dic_writer_req_valid; // @[ZstdCompressor.scala:140:30]
wire [63:0] _lit_compressor_io_l2if_dic_writer_req_bits_addr; // @[ZstdCompressor.scala:140:30]
wire [2:0] _lit_compressor_io_l2if_dic_writer_req_bits_size; // @[ZstdCompressor.scala:140:30]
wire [255:0] _lit_compressor_io_l2if_dic_writer_req_bits_data; // @[ZstdCompressor.scala:140:30]
wire _lit_compressor_io_l2if_dic_writer_req_bits_cmd; // @[ZstdCompressor.scala:140:30]
wire _lit_compressor_io_l2if_dic_writer_resp_ready; // @[ZstdCompressor.scala:140:30]
wire _lit_compressor_io_l2if_hdr_writer_req_valid; // @[ZstdCompressor.scala:140:30]
wire [63:0] _lit_compressor_io_l2if_hdr_writer_req_bits_addr; // @[ZstdCompressor.scala:140:30]
wire [2:0] _lit_compressor_io_l2if_hdr_writer_req_bits_size; // @[ZstdCompressor.scala:140:30]
wire [255:0] _lit_compressor_io_l2if_hdr_writer_req_bits_data; // @[ZstdCompressor.scala:140:30]
wire _lit_compressor_io_l2if_hdr_writer_req_bits_cmd; // @[ZstdCompressor.scala:140:30]
wire _lit_compressor_io_l2if_hdr_writer_resp_ready; // @[ZstdCompressor.scala:140:30]
wire _lit_compressor_io_l2if_jt_writer_req_valid; // @[ZstdCompressor.scala:140:30]
wire [63:0] _lit_compressor_io_l2if_jt_writer_req_bits_addr; // @[ZstdCompressor.scala:140:30]
wire [2:0] _lit_compressor_io_l2if_jt_writer_req_bits_size; // @[ZstdCompressor.scala:140:30]
wire [255:0] _lit_compressor_io_l2if_jt_writer_req_bits_data; // @[ZstdCompressor.scala:140:30]
wire _lit_compressor_io_l2if_jt_writer_req_bits_cmd; // @[ZstdCompressor.scala:140:30]
wire _lit_compressor_io_l2if_jt_writer_resp_ready; // @[ZstdCompressor.scala:140:30]
wire _lit_compressor_io_l2if_lit_writer_req_valid; // @[ZstdCompressor.scala:140:30]
wire [63:0] _lit_compressor_io_l2if_lit_writer_req_bits_addr; // @[ZstdCompressor.scala:140:30]
wire [2:0] _lit_compressor_io_l2if_lit_writer_req_bits_size; // @[ZstdCompressor.scala:140:30]
wire [255:0] _lit_compressor_io_l2if_lit_writer_req_bits_data; // @[ZstdCompressor.scala:140:30]
wire _lit_compressor_io_l2if_lit_writer_req_bits_cmd; // @[ZstdCompressor.scala:140:30]
wire _lit_compressor_io_l2if_lit_writer_resp_ready; // @[ZstdCompressor.scala:140:30]
wire _matchfinder_io_l2io_memloader_userif_req_valid; // @[ZstdCompressor.scala:129:27]
wire [70:0] _matchfinder_io_l2io_memloader_userif_req_bits_addr; // @[ZstdCompressor.scala:129:27]
wire _matchfinder_io_l2io_memloader_userif_resp_ready; // @[ZstdCompressor.scala:129:27]
wire _matchfinder_io_l2io_lit_memwriter_userif_req_valid; // @[ZstdCompressor.scala:129:27]
wire [63:0] _matchfinder_io_l2io_lit_memwriter_userif_req_bits_addr; // @[ZstdCompressor.scala:129:27]
wire [2:0] _matchfinder_io_l2io_lit_memwriter_userif_req_bits_size; // @[ZstdCompressor.scala:129:27]
wire [255:0] _matchfinder_io_l2io_lit_memwriter_userif_req_bits_data; // @[ZstdCompressor.scala:129:27]
wire _matchfinder_io_l2io_seq_memwriter_userif_req_valid; // @[ZstdCompressor.scala:129:27]
wire [63:0] _matchfinder_io_l2io_seq_memwriter_userif_req_bits_addr; // @[ZstdCompressor.scala:129:27]
wire [2:0] _matchfinder_io_l2io_seq_memwriter_userif_req_bits_size; // @[ZstdCompressor.scala:129:27]
wire [255:0] _matchfinder_io_l2io_seq_memwriter_userif_req_bits_data; // @[ZstdCompressor.scala:129:27]
wire _matchfinder_io_src_compress_src_info_ready; // @[ZstdCompressor.scala:129:27]
wire _matchfinder_io_src_compress_src_info2_ready; // @[ZstdCompressor.scala:129:27]
wire _matchfinder_io_dst_lit_dst_info_ready; // @[ZstdCompressor.scala:129:27]
wire _matchfinder_io_dst_seq_dst_info_ready; // @[ZstdCompressor.scala:129:27]
wire _matchfinder_io_buff_consumed_lit_consumed_bytes_valid; // @[ZstdCompressor.scala:129:27]
wire [63:0] _matchfinder_io_buff_consumed_lit_consumed_bytes_bits; // @[ZstdCompressor.scala:129:27]
wire _matchfinder_io_buff_consumed_seq_consumed_bytes_valid; // @[ZstdCompressor.scala:129:27]
wire [63:0] _matchfinder_io_buff_consumed_seq_consumed_bytes_bits; // @[ZstdCompressor.scala:129:27]
wire _controller_io_src_info_ready; // @[ZstdCompressor.scala:116:26]
wire _controller_io_dst_info_ready; // @[ZstdCompressor.scala:116:26]
wire _controller_io_buff_info_lit_ready; // @[ZstdCompressor.scala:116:26]
wire _controller_io_buff_info_seq_ready; // @[ZstdCompressor.scala:116:26]
wire _controller_io_clevel_info_ready; // @[ZstdCompressor.scala:116:26]
wire _controller_io_zstd_control_l2io_fhdr_l2userif_req_valid; // @[ZstdCompressor.scala:116:26]
wire [63:0] _controller_io_zstd_control_l2io_fhdr_l2userif_req_bits_addr; // @[ZstdCompressor.scala:116:26]
wire [2:0] _controller_io_zstd_control_l2io_fhdr_l2userif_req_bits_size; // @[ZstdCompressor.scala:116:26]
wire [255:0] _controller_io_zstd_control_l2io_fhdr_l2userif_req_bits_data; // @[ZstdCompressor.scala:116:26]
wire _controller_io_zstd_control_l2io_bhdr_l2userif_req_valid; // @[ZstdCompressor.scala:116:26]
wire [63:0] _controller_io_zstd_control_l2io_bhdr_l2userif_req_bits_addr; // @[ZstdCompressor.scala:116:26]
wire [2:0] _controller_io_zstd_control_l2io_bhdr_l2userif_req_bits_size; // @[ZstdCompressor.scala:116:26]
wire [255:0] _controller_io_zstd_control_l2io_bhdr_l2userif_req_bits_data; // @[ZstdCompressor.scala:116:26]
wire _controller_io_zstd_control_litcpy_src_valid; // @[ZstdCompressor.scala:116:26]
wire [63:0] _controller_io_zstd_control_litcpy_src_bits_ip; // @[ZstdCompressor.scala:116:26]
wire [63:0] _controller_io_zstd_control_litcpy_src_bits_isize; // @[ZstdCompressor.scala:116:26]
wire _controller_io_zstd_control_litcpy_src2_valid; // @[ZstdCompressor.scala:116:26]
wire [63:0] _controller_io_zstd_control_litcpy_src2_bits_ip; // @[ZstdCompressor.scala:116:26]
wire [63:0] _controller_io_zstd_control_litcpy_src2_bits_isize; // @[ZstdCompressor.scala:116:26]
wire _controller_io_zstd_control_litcpy_dst_valid; // @[ZstdCompressor.scala:116:26]
wire [63:0] _controller_io_zstd_control_litcpy_dst_bits_op; // @[ZstdCompressor.scala:116:26]
wire [63:0] _controller_io_zstd_control_litcpy_dst_bits_cmpflag; // @[ZstdCompressor.scala:116:26]
wire [63:0] _controller_io_zstd_control_litcpy_dst_bits_cmpval; // @[ZstdCompressor.scala:116:26]
wire _controller_io_zstd_control_litbytes_written_ready; // @[ZstdCompressor.scala:116:26]
wire _controller_io_zstd_control_raw_lit_src_valid; // @[ZstdCompressor.scala:116:26]
wire [63:0] _controller_io_zstd_control_raw_lit_src_bits_ip; // @[ZstdCompressor.scala:116:26]
wire [63:0] _controller_io_zstd_control_raw_lit_src_bits_isize; // @[ZstdCompressor.scala:116:26]
wire _controller_io_zstd_control_raw_lit_dst_valid; // @[ZstdCompressor.scala:116:26]
wire [63:0] _controller_io_zstd_control_raw_lit_dst_bits_op; // @[ZstdCompressor.scala:116:26]
wire [63:0] _controller_io_zstd_control_raw_lit_dst_bits_cmpflag; // @[ZstdCompressor.scala:116:26]
wire [63:0] _controller_io_zstd_control_raw_lit_dst_bits_cmpval; // @[ZstdCompressor.scala:116:26]
wire _controller_io_zstd_control_raw_litbytes_written_ready; // @[ZstdCompressor.scala:116:26]
wire _controller_io_zstd_control_raw_block_src_valid; // @[ZstdCompressor.scala:116:26]
wire [63:0] _controller_io_zstd_control_raw_block_src_bits_ip; // @[ZstdCompressor.scala:116:26]
wire [63:0] _controller_io_zstd_control_raw_block_src_bits_isize; // @[ZstdCompressor.scala:116:26]
wire _controller_io_zstd_control_raw_block_dst_valid; // @[ZstdCompressor.scala:116:26]
wire [63:0] _controller_io_zstd_control_raw_block_dst_bits_op; // @[ZstdCompressor.scala:116:26]
wire [63:0] _controller_io_zstd_control_raw_block_dst_bits_cmpflag; // @[ZstdCompressor.scala:116:26]
wire [63:0] _controller_io_zstd_control_raw_block_dst_bits_cmpval; // @[ZstdCompressor.scala:116:26]
wire _controller_io_zstd_control_raw_blockbytes_written_ready; // @[ZstdCompressor.scala:116:26]
wire _controller_io_zstd_control_seqcpy_src_valid; // @[ZstdCompressor.scala:116:26]
wire [63:0] _controller_io_zstd_control_seqcpy_src_bits_ip; // @[ZstdCompressor.scala:116:26]
wire [63:0] _controller_io_zstd_control_seqcpy_src_bits_isize; // @[ZstdCompressor.scala:116:26]
wire _controller_io_zstd_control_seqcpy_dst_valid; // @[ZstdCompressor.scala:116:26]
wire [63:0] _controller_io_zstd_control_seqcpy_dst_bits_op; // @[ZstdCompressor.scala:116:26]
wire [63:0] _controller_io_zstd_control_seqcpy_dst_bits_cmpflag; // @[ZstdCompressor.scala:116:26]
wire [63:0] _controller_io_zstd_control_seqcpy_dst_bits_cmpval; // @[ZstdCompressor.scala:116:26]
wire _controller_io_zstd_control_seqbytes_written_ready; // @[ZstdCompressor.scala:116:26]
wire _controller_io_shared_control_mf_src_compress_src_info_valid; // @[ZstdCompressor.scala:116:26]
wire [63:0] _controller_io_shared_control_mf_src_compress_src_info_bits_ip; // @[ZstdCompressor.scala:116:26]
wire [63:0] _controller_io_shared_control_mf_src_compress_src_info_bits_isize; // @[ZstdCompressor.scala:116:26]
wire _controller_io_shared_control_mf_src_compress_src_info2_valid; // @[ZstdCompressor.scala:116:26]
wire [63:0] _controller_io_shared_control_mf_src_compress_src_info2_bits_ip; // @[ZstdCompressor.scala:116:26]
wire [63:0] _controller_io_shared_control_mf_src_compress_src_info2_bits_isize; // @[ZstdCompressor.scala:116:26]
wire _controller_io_shared_control_mf_dst_lit_dst_info_valid; // @[ZstdCompressor.scala:116:26]
wire [63:0] _controller_io_shared_control_mf_dst_lit_dst_info_bits_op; // @[ZstdCompressor.scala:116:26]
wire [63:0] _controller_io_shared_control_mf_dst_lit_dst_info_bits_cmpflag; // @[ZstdCompressor.scala:116:26]
wire _controller_io_shared_control_mf_dst_seq_dst_info_valid; // @[ZstdCompressor.scala:116:26]
wire [63:0] _controller_io_shared_control_mf_dst_seq_dst_info_bits_op; // @[ZstdCompressor.scala:116:26]
wire [63:0] _controller_io_shared_control_mf_dst_seq_dst_info_bits_cmpflag; // @[ZstdCompressor.scala:116:26]
wire _controller_io_shared_control_mf_buff_consumed_lit_consumed_bytes_ready; // @[ZstdCompressor.scala:116:26]
wire _controller_io_shared_control_mf_buff_consumed_seq_consumed_bytes_ready; // @[ZstdCompressor.scala:116:26]
wire _controller_io_zstd_finished_cnt_valid; // @[ZstdCompressor.scala:116:26]
wire [63:0] _controller_io_zstd_finished_cnt_bits; // @[ZstdCompressor.scala:116:26]
wire _controller_io_snappy_finished_cnt_valid; // @[ZstdCompressor.scala:116:26]
wire [63:0] _controller_io_snappy_finished_cnt_bits; // @[ZstdCompressor.scala:116:26]
wire _cmd_router_io_dmem_status_out_valid; // @[ZstdCompressor.scala:112:26]
wire _cmd_router_io_dmem_status_out_bits_status_debug; // @[ZstdCompressor.scala:112:26]
wire _cmd_router_io_dmem_status_out_bits_status_cease; // @[ZstdCompressor.scala:112:26]
wire _cmd_router_io_dmem_status_out_bits_status_wfi; // @[ZstdCompressor.scala:112:26]
wire [31:0] _cmd_router_io_dmem_status_out_bits_status_isa; // @[ZstdCompressor.scala:112:26]
wire [1:0] _cmd_router_io_dmem_status_out_bits_status_dprv; // @[ZstdCompressor.scala:112:26]
wire _cmd_router_io_dmem_status_out_bits_status_dv; // @[ZstdCompressor.scala:112:26]
wire [1:0] _cmd_router_io_dmem_status_out_bits_status_prv; // @[ZstdCompressor.scala:112:26]
wire _cmd_router_io_dmem_status_out_bits_status_v; // @[ZstdCompressor.scala:112:26]
wire _cmd_router_io_dmem_status_out_bits_status_sd; // @[ZstdCompressor.scala:112:26]
wire [22:0] _cmd_router_io_dmem_status_out_bits_status_zero2; // @[ZstdCompressor.scala:112:26]
wire _cmd_router_io_dmem_status_out_bits_status_mpv; // @[ZstdCompressor.scala:112:26]
wire _cmd_router_io_dmem_status_out_bits_status_gva; // @[ZstdCompressor.scala:112:26]
wire _cmd_router_io_dmem_status_out_bits_status_mbe; // @[ZstdCompressor.scala:112:26]
wire _cmd_router_io_dmem_status_out_bits_status_sbe; // @[ZstdCompressor.scala:112:26]
wire [1:0] _cmd_router_io_dmem_status_out_bits_status_sxl; // @[ZstdCompressor.scala:112:26]
wire [1:0] _cmd_router_io_dmem_status_out_bits_status_uxl; // @[ZstdCompressor.scala:112:26]
wire _cmd_router_io_dmem_status_out_bits_status_sd_rv32; // @[ZstdCompressor.scala:112:26]
wire [7:0] _cmd_router_io_dmem_status_out_bits_status_zero1; // @[ZstdCompressor.scala:112:26]
wire _cmd_router_io_dmem_status_out_bits_status_tsr; // @[ZstdCompressor.scala:112:26]
wire _cmd_router_io_dmem_status_out_bits_status_tw; // @[ZstdCompressor.scala:112:26]
wire _cmd_router_io_dmem_status_out_bits_status_tvm; // @[ZstdCompressor.scala:112:26]
wire _cmd_router_io_dmem_status_out_bits_status_mxr; // @[ZstdCompressor.scala:112:26]
wire _cmd_router_io_dmem_status_out_bits_status_sum; // @[ZstdCompressor.scala:112:26]
wire _cmd_router_io_dmem_status_out_bits_status_mprv; // @[ZstdCompressor.scala:112:26]
wire [1:0] _cmd_router_io_dmem_status_out_bits_status_xs; // @[ZstdCompressor.scala:112:26]
wire [1:0] _cmd_router_io_dmem_status_out_bits_status_fs; // @[ZstdCompressor.scala:112:26]
wire [1:0] _cmd_router_io_dmem_status_out_bits_status_mpp; // @[ZstdCompressor.scala:112:26]
wire [1:0] _cmd_router_io_dmem_status_out_bits_status_vs; // @[ZstdCompressor.scala:112:26]
wire _cmd_router_io_dmem_status_out_bits_status_spp; // @[ZstdCompressor.scala:112:26]
wire _cmd_router_io_dmem_status_out_bits_status_mpie; // @[ZstdCompressor.scala:112:26]
wire _cmd_router_io_dmem_status_out_bits_status_ube; // @[ZstdCompressor.scala:112:26]
wire _cmd_router_io_dmem_status_out_bits_status_spie; // @[ZstdCompressor.scala:112:26]
wire _cmd_router_io_dmem_status_out_bits_status_upie; // @[ZstdCompressor.scala:112:26]
wire _cmd_router_io_dmem_status_out_bits_status_mie; // @[ZstdCompressor.scala:112:26]
wire _cmd_router_io_dmem_status_out_bits_status_hie; // @[ZstdCompressor.scala:112:26]
wire _cmd_router_io_dmem_status_out_bits_status_sie; // @[ZstdCompressor.scala:112:26]
wire _cmd_router_io_dmem_status_out_bits_status_uie; // @[ZstdCompressor.scala:112:26]
wire _cmd_router_io_sfence_out; // @[ZstdCompressor.scala:112:26]
wire _cmd_router_io_ALGORITHM; // @[ZstdCompressor.scala:112:26]
wire _cmd_router_io_src_info_valid; // @[ZstdCompressor.scala:112:26]
wire [63:0] _cmd_router_io_src_info_bits_ip; // @[ZstdCompressor.scala:112:26]
wire [63:0] _cmd_router_io_src_info_bits_isize; // @[ZstdCompressor.scala:112:26]
wire _cmd_router_io_dst_info_valid; // @[ZstdCompressor.scala:112:26]
wire [63:0] _cmd_router_io_dst_info_bits_op; // @[ZstdCompressor.scala:112:26]
wire [63:0] _cmd_router_io_dst_info_bits_cmpflag; // @[ZstdCompressor.scala:112:26]
wire _cmd_router_io_buff_info_lit_valid; // @[ZstdCompressor.scala:112:26]
wire [63:0] _cmd_router_io_buff_info_lit_bits_ip; // @[ZstdCompressor.scala:112:26]
wire [63:0] _cmd_router_io_buff_info_lit_bits_isize; // @[ZstdCompressor.scala:112:26]
wire _cmd_router_io_buff_info_seq_valid; // @[ZstdCompressor.scala:112:26]
wire [63:0] _cmd_router_io_buff_info_seq_bits_ip; // @[ZstdCompressor.scala:112:26]
wire [63:0] _cmd_router_io_buff_info_seq_bits_isize; // @[ZstdCompressor.scala:112:26]
wire _cmd_router_io_clevel_info_valid; // @[ZstdCompressor.scala:112:26]
wire [4:0] _cmd_router_io_clevel_info_bits; // @[ZstdCompressor.scala:112:26]
wire [63:0] _cmd_router_io_SNAPPY_MAX_OFFSET_ALLOWED; // @[ZstdCompressor.scala:112:26]
wire [4:0] _cmd_router_io_SNAPPY_RUNTIME_HT_NUM_ENTRIES_LOG2; // @[ZstdCompressor.scala:112:26]
wire [63:0] _cmd_router_io_LATENCY_INJECTION_CYCLES; // @[ZstdCompressor.scala:112:26]
wire _cmd_router_io_HAS_INTERMEDIATE_CACHE; // @[ZstdCompressor.scala:112:26]
wire _cmd_router_io_zstd_finished_cnt_ready; // @[ZstdCompressor.scala:112:26]
wire _cmd_router_io_snappy_finished_cnt_ready; // @[ZstdCompressor.scala:112:26]
wire _widget_17_auto_anon_in_a_ready; // @[WidthWidget.scala:230:28]
wire _widget_17_auto_anon_in_d_valid; // @[WidthWidget.scala:230:28]
wire [2:0] _widget_17_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:230:28]
wire [1:0] _widget_17_auto_anon_in_d_bits_param; // @[WidthWidget.scala:230:28]
wire [3:0] _widget_17_auto_anon_in_d_bits_size; // @[WidthWidget.scala:230:28]
wire [4:0] _widget_17_auto_anon_in_d_bits_source; // @[WidthWidget.scala:230:28]
wire [2:0] _widget_17_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:230:28]
wire _widget_17_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:230:28]
wire [255:0] _widget_17_auto_anon_in_d_bits_data; // @[WidthWidget.scala:230:28]
wire _widget_17_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:230:28]
wire _l2_raw_lit_writer_auto_master_out_a_valid; // @[ZstdCompressor.scala:91:37]
wire [2:0] _l2_raw_lit_writer_auto_master_out_a_bits_opcode; // @[ZstdCompressor.scala:91:37]
wire [2:0] _l2_raw_lit_writer_auto_master_out_a_bits_param; // @[ZstdCompressor.scala:91:37]
wire [3:0] _l2_raw_lit_writer_auto_master_out_a_bits_size; // @[ZstdCompressor.scala:91:37]
wire [4:0] _l2_raw_lit_writer_auto_master_out_a_bits_source; // @[ZstdCompressor.scala:91:37]
wire [31:0] _l2_raw_lit_writer_auto_master_out_a_bits_address; // @[ZstdCompressor.scala:91:37]
wire [31:0] _l2_raw_lit_writer_auto_master_out_a_bits_mask; // @[ZstdCompressor.scala:91:37]
wire [255:0] _l2_raw_lit_writer_auto_master_out_a_bits_data; // @[ZstdCompressor.scala:91:37]
wire _l2_raw_lit_writer_auto_master_out_a_bits_corrupt; // @[ZstdCompressor.scala:91:37]
wire _l2_raw_lit_writer_auto_master_out_d_ready; // @[ZstdCompressor.scala:91:37]
wire _l2_raw_lit_writer_io_userif_req_ready; // @[ZstdCompressor.scala:91:37]
wire _l2_raw_lit_writer_io_userif_resp_valid; // @[ZstdCompressor.scala:91:37]
wire [255:0] _l2_raw_lit_writer_io_userif_resp_bits_data; // @[ZstdCompressor.scala:91:37]
wire _l2_raw_lit_writer_io_userif_no_memops_inflight; // @[ZstdCompressor.scala:91:37]
wire _widget_16_auto_anon_in_a_ready; // @[WidthWidget.scala:230:28]
wire _widget_16_auto_anon_in_d_valid; // @[WidthWidget.scala:230:28]
wire [2:0] _widget_16_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:230:28]
wire [1:0] _widget_16_auto_anon_in_d_bits_param; // @[WidthWidget.scala:230:28]
wire [3:0] _widget_16_auto_anon_in_d_bits_size; // @[WidthWidget.scala:230:28]
wire [4:0] _widget_16_auto_anon_in_d_bits_source; // @[WidthWidget.scala:230:28]
wire [2:0] _widget_16_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:230:28]
wire _widget_16_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:230:28]
wire [255:0] _widget_16_auto_anon_in_d_bits_data; // @[WidthWidget.scala:230:28]
wire _widget_16_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:230:28]
wire _l2_raw_lit_reader_auto_master_out_a_valid; // @[ZstdCompressor.scala:88:37]
wire [2:0] _l2_raw_lit_reader_auto_master_out_a_bits_opcode; // @[ZstdCompressor.scala:88:37]
wire [2:0] _l2_raw_lit_reader_auto_master_out_a_bits_param; // @[ZstdCompressor.scala:88:37]
wire [3:0] _l2_raw_lit_reader_auto_master_out_a_bits_size; // @[ZstdCompressor.scala:88:37]
wire [4:0] _l2_raw_lit_reader_auto_master_out_a_bits_source; // @[ZstdCompressor.scala:88:37]
wire [31:0] _l2_raw_lit_reader_auto_master_out_a_bits_address; // @[ZstdCompressor.scala:88:37]
wire [31:0] _l2_raw_lit_reader_auto_master_out_a_bits_mask; // @[ZstdCompressor.scala:88:37]
wire [255:0] _l2_raw_lit_reader_auto_master_out_a_bits_data; // @[ZstdCompressor.scala:88:37]
wire _l2_raw_lit_reader_auto_master_out_a_bits_corrupt; // @[ZstdCompressor.scala:88:37]
wire _l2_raw_lit_reader_auto_master_out_d_ready; // @[ZstdCompressor.scala:88:37]
wire _l2_raw_lit_reader_io_userif_req_ready; // @[ZstdCompressor.scala:88:37]
wire _l2_raw_lit_reader_io_userif_resp_valid; // @[ZstdCompressor.scala:88:37]
wire [255:0] _l2_raw_lit_reader_io_userif_resp_bits_data; // @[ZstdCompressor.scala:88:37]
wire _l2_raw_lit_reader_io_userif_no_memops_inflight; // @[ZstdCompressor.scala:88:37]
wire _widget_15_auto_anon_in_a_ready; // @[WidthWidget.scala:230:28]
wire _widget_15_auto_anon_in_d_valid; // @[WidthWidget.scala:230:28]
wire [2:0] _widget_15_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:230:28]
wire [1:0] _widget_15_auto_anon_in_d_bits_param; // @[WidthWidget.scala:230:28]
wire [3:0] _widget_15_auto_anon_in_d_bits_size; // @[WidthWidget.scala:230:28]
wire [4:0] _widget_15_auto_anon_in_d_bits_source; // @[WidthWidget.scala:230:28]
wire [2:0] _widget_15_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:230:28]
wire _widget_15_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:230:28]
wire [255:0] _widget_15_auto_anon_in_d_bits_data; // @[WidthWidget.scala:230:28]
wire _widget_15_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:230:28]
wire _l2_raw_block_writer_auto_master_out_a_valid; // @[ZstdCompressor.scala:85:39]
wire [2:0] _l2_raw_block_writer_auto_master_out_a_bits_opcode; // @[ZstdCompressor.scala:85:39]
wire [2:0] _l2_raw_block_writer_auto_master_out_a_bits_param; // @[ZstdCompressor.scala:85:39]
wire [3:0] _l2_raw_block_writer_auto_master_out_a_bits_size; // @[ZstdCompressor.scala:85:39]
wire [4:0] _l2_raw_block_writer_auto_master_out_a_bits_source; // @[ZstdCompressor.scala:85:39]
wire [31:0] _l2_raw_block_writer_auto_master_out_a_bits_address; // @[ZstdCompressor.scala:85:39]
wire [31:0] _l2_raw_block_writer_auto_master_out_a_bits_mask; // @[ZstdCompressor.scala:85:39]
wire [255:0] _l2_raw_block_writer_auto_master_out_a_bits_data; // @[ZstdCompressor.scala:85:39]
wire _l2_raw_block_writer_auto_master_out_a_bits_corrupt; // @[ZstdCompressor.scala:85:39]
wire _l2_raw_block_writer_auto_master_out_d_ready; // @[ZstdCompressor.scala:85:39]
wire _l2_raw_block_writer_io_userif_req_ready; // @[ZstdCompressor.scala:85:39]
wire _l2_raw_block_writer_io_userif_resp_valid; // @[ZstdCompressor.scala:85:39]
wire [255:0] _l2_raw_block_writer_io_userif_resp_bits_data; // @[ZstdCompressor.scala:85:39]
wire _l2_raw_block_writer_io_userif_no_memops_inflight; // @[ZstdCompressor.scala:85:39]
wire _widget_14_auto_anon_in_a_ready; // @[WidthWidget.scala:230:28]
wire _widget_14_auto_anon_in_d_valid; // @[WidthWidget.scala:230:28]
wire [2:0] _widget_14_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:230:28]
wire [1:0] _widget_14_auto_anon_in_d_bits_param; // @[WidthWidget.scala:230:28]
wire [3:0] _widget_14_auto_anon_in_d_bits_size; // @[WidthWidget.scala:230:28]
wire [4:0] _widget_14_auto_anon_in_d_bits_source; // @[WidthWidget.scala:230:28]
wire [2:0] _widget_14_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:230:28]
wire _widget_14_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:230:28]
wire [255:0] _widget_14_auto_anon_in_d_bits_data; // @[WidthWidget.scala:230:28]
wire _widget_14_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:230:28]
wire _l2_raw_block_reader_auto_master_out_a_valid; // @[ZstdCompressor.scala:82:39]
wire [2:0] _l2_raw_block_reader_auto_master_out_a_bits_opcode; // @[ZstdCompressor.scala:82:39]
wire [2:0] _l2_raw_block_reader_auto_master_out_a_bits_param; // @[ZstdCompressor.scala:82:39]
wire [3:0] _l2_raw_block_reader_auto_master_out_a_bits_size; // @[ZstdCompressor.scala:82:39]
wire [4:0] _l2_raw_block_reader_auto_master_out_a_bits_source; // @[ZstdCompressor.scala:82:39]
wire [31:0] _l2_raw_block_reader_auto_master_out_a_bits_address; // @[ZstdCompressor.scala:82:39]
wire [31:0] _l2_raw_block_reader_auto_master_out_a_bits_mask; // @[ZstdCompressor.scala:82:39]
wire [255:0] _l2_raw_block_reader_auto_master_out_a_bits_data; // @[ZstdCompressor.scala:82:39]
wire _l2_raw_block_reader_auto_master_out_a_bits_corrupt; // @[ZstdCompressor.scala:82:39]
wire _l2_raw_block_reader_auto_master_out_d_ready; // @[ZstdCompressor.scala:82:39]
wire _l2_raw_block_reader_io_userif_req_ready; // @[ZstdCompressor.scala:82:39]
wire _l2_raw_block_reader_io_userif_resp_valid; // @[ZstdCompressor.scala:82:39]
wire [255:0] _l2_raw_block_reader_io_userif_resp_bits_data; // @[ZstdCompressor.scala:82:39]
wire _l2_raw_block_reader_io_userif_no_memops_inflight; // @[ZstdCompressor.scala:82:39]
wire _widget_13_auto_anon_in_a_ready; // @[WidthWidget.scala:230:28]
wire _widget_13_auto_anon_in_d_valid; // @[WidthWidget.scala:230:28]
wire [2:0] _widget_13_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:230:28]
wire [1:0] _widget_13_auto_anon_in_d_bits_param; // @[WidthWidget.scala:230:28]
wire [3:0] _widget_13_auto_anon_in_d_bits_size; // @[WidthWidget.scala:230:28]
wire [4:0] _widget_13_auto_anon_in_d_bits_source; // @[WidthWidget.scala:230:28]
wire [2:0] _widget_13_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:230:28]
wire _widget_13_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:230:28]
wire [255:0] _widget_13_auto_anon_in_d_bits_data; // @[WidthWidget.scala:230:28]
wire _widget_13_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:230:28]
wire _l2_seq_writer_auto_master_out_a_valid; // @[ZstdCompressor.scala:79:33]
wire [2:0] _l2_seq_writer_auto_master_out_a_bits_opcode; // @[ZstdCompressor.scala:79:33]
wire [2:0] _l2_seq_writer_auto_master_out_a_bits_param; // @[ZstdCompressor.scala:79:33]
wire [3:0] _l2_seq_writer_auto_master_out_a_bits_size; // @[ZstdCompressor.scala:79:33]
wire [4:0] _l2_seq_writer_auto_master_out_a_bits_source; // @[ZstdCompressor.scala:79:33]
wire [31:0] _l2_seq_writer_auto_master_out_a_bits_address; // @[ZstdCompressor.scala:79:33]
wire [31:0] _l2_seq_writer_auto_master_out_a_bits_mask; // @[ZstdCompressor.scala:79:33]
wire [255:0] _l2_seq_writer_auto_master_out_a_bits_data; // @[ZstdCompressor.scala:79:33]
wire _l2_seq_writer_auto_master_out_a_bits_corrupt; // @[ZstdCompressor.scala:79:33]
wire _l2_seq_writer_auto_master_out_d_ready; // @[ZstdCompressor.scala:79:33]
wire _l2_seq_writer_io_userif_req_ready; // @[ZstdCompressor.scala:79:33]
wire _l2_seq_writer_io_userif_resp_valid; // @[ZstdCompressor.scala:79:33]
wire [255:0] _l2_seq_writer_io_userif_resp_bits_data; // @[ZstdCompressor.scala:79:33]
wire _l2_seq_writer_io_userif_no_memops_inflight; // @[ZstdCompressor.scala:79:33]
wire _widget_12_auto_anon_in_a_ready; // @[WidthWidget.scala:230:28]
wire _widget_12_auto_anon_in_d_valid; // @[WidthWidget.scala:230:28]
wire [2:0] _widget_12_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:230:28]
wire [1:0] _widget_12_auto_anon_in_d_bits_param; // @[WidthWidget.scala:230:28]
wire [3:0] _widget_12_auto_anon_in_d_bits_size; // @[WidthWidget.scala:230:28]
wire [4:0] _widget_12_auto_anon_in_d_bits_source; // @[WidthWidget.scala:230:28]
wire [2:0] _widget_12_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:230:28]
wire _widget_12_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:230:28]
wire [255:0] _widget_12_auto_anon_in_d_bits_data; // @[WidthWidget.scala:230:28]
wire _widget_12_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:230:28]
wire _l2_seq_reader2_auto_master_out_a_valid; // @[ZstdCompressor.scala:76:34]
wire [2:0] _l2_seq_reader2_auto_master_out_a_bits_opcode; // @[ZstdCompressor.scala:76:34]
wire [2:0] _l2_seq_reader2_auto_master_out_a_bits_param; // @[ZstdCompressor.scala:76:34]
wire [3:0] _l2_seq_reader2_auto_master_out_a_bits_size; // @[ZstdCompressor.scala:76:34]
wire [4:0] _l2_seq_reader2_auto_master_out_a_bits_source; // @[ZstdCompressor.scala:76:34]
wire [31:0] _l2_seq_reader2_auto_master_out_a_bits_address; // @[ZstdCompressor.scala:76:34]
wire [31:0] _l2_seq_reader2_auto_master_out_a_bits_mask; // @[ZstdCompressor.scala:76:34]
wire [255:0] _l2_seq_reader2_auto_master_out_a_bits_data; // @[ZstdCompressor.scala:76:34]
wire _l2_seq_reader2_auto_master_out_a_bits_corrupt; // @[ZstdCompressor.scala:76:34]
wire _l2_seq_reader2_auto_master_out_d_ready; // @[ZstdCompressor.scala:76:34]
wire _l2_seq_reader2_io_userif_req_ready; // @[ZstdCompressor.scala:76:34]
wire _l2_seq_reader2_io_userif_resp_valid; // @[ZstdCompressor.scala:76:34]
wire [255:0] _l2_seq_reader2_io_userif_resp_bits_data; // @[ZstdCompressor.scala:76:34]
wire _l2_seq_reader2_io_userif_no_memops_inflight; // @[ZstdCompressor.scala:76:34]
wire _widget_11_auto_anon_in_a_ready; // @[WidthWidget.scala:230:28]
wire _widget_11_auto_anon_in_d_valid; // @[WidthWidget.scala:230:28]
wire [2:0] _widget_11_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:230:28]
wire [1:0] _widget_11_auto_anon_in_d_bits_param; // @[WidthWidget.scala:230:28]
wire [3:0] _widget_11_auto_anon_in_d_bits_size; // @[WidthWidget.scala:230:28]
wire [4:0] _widget_11_auto_anon_in_d_bits_source; // @[WidthWidget.scala:230:28]
wire [2:0] _widget_11_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:230:28]
wire _widget_11_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:230:28]
wire [255:0] _widget_11_auto_anon_in_d_bits_data; // @[WidthWidget.scala:230:28]
wire _widget_11_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:230:28]
wire _l2_seq_reader_auto_master_out_a_valid; // @[ZstdCompressor.scala:73:33]
wire [2:0] _l2_seq_reader_auto_master_out_a_bits_opcode; // @[ZstdCompressor.scala:73:33]
wire [2:0] _l2_seq_reader_auto_master_out_a_bits_param; // @[ZstdCompressor.scala:73:33]
wire [3:0] _l2_seq_reader_auto_master_out_a_bits_size; // @[ZstdCompressor.scala:73:33]
wire [4:0] _l2_seq_reader_auto_master_out_a_bits_source; // @[ZstdCompressor.scala:73:33]
wire [31:0] _l2_seq_reader_auto_master_out_a_bits_address; // @[ZstdCompressor.scala:73:33]
wire [31:0] _l2_seq_reader_auto_master_out_a_bits_mask; // @[ZstdCompressor.scala:73:33]
wire [255:0] _l2_seq_reader_auto_master_out_a_bits_data; // @[ZstdCompressor.scala:73:33]
wire _l2_seq_reader_auto_master_out_a_bits_corrupt; // @[ZstdCompressor.scala:73:33]
wire _l2_seq_reader_auto_master_out_d_ready; // @[ZstdCompressor.scala:73:33]
wire _l2_seq_reader_io_userif_req_ready; // @[ZstdCompressor.scala:73:33]
wire _l2_seq_reader_io_userif_resp_valid; // @[ZstdCompressor.scala:73:33]
wire [255:0] _l2_seq_reader_io_userif_resp_bits_data; // @[ZstdCompressor.scala:73:33]
wire _l2_seq_reader_io_userif_no_memops_inflight; // @[ZstdCompressor.scala:73:33]
wire _widget_10_auto_anon_in_a_ready; // @[WidthWidget.scala:230:28]
wire _widget_10_auto_anon_in_d_valid; // @[WidthWidget.scala:230:28]
wire [2:0] _widget_10_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:230:28]
wire [1:0] _widget_10_auto_anon_in_d_bits_param; // @[WidthWidget.scala:230:28]
wire [3:0] _widget_10_auto_anon_in_d_bits_size; // @[WidthWidget.scala:230:28]
wire [4:0] _widget_10_auto_anon_in_d_bits_source; // @[WidthWidget.scala:230:28]
wire [2:0] _widget_10_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:230:28]
wire _widget_10_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:230:28]
wire [255:0] _widget_10_auto_anon_in_d_bits_data; // @[WidthWidget.scala:230:28]
wire _widget_10_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:230:28]
wire _l2_huf_lit_writer_auto_master_out_a_valid; // @[ZstdCompressor.scala:70:37]
wire [2:0] _l2_huf_lit_writer_auto_master_out_a_bits_opcode; // @[ZstdCompressor.scala:70:37]
wire [2:0] _l2_huf_lit_writer_auto_master_out_a_bits_param; // @[ZstdCompressor.scala:70:37]
wire [3:0] _l2_huf_lit_writer_auto_master_out_a_bits_size; // @[ZstdCompressor.scala:70:37]
wire [4:0] _l2_huf_lit_writer_auto_master_out_a_bits_source; // @[ZstdCompressor.scala:70:37]
wire [31:0] _l2_huf_lit_writer_auto_master_out_a_bits_address; // @[ZstdCompressor.scala:70:37]
wire [31:0] _l2_huf_lit_writer_auto_master_out_a_bits_mask; // @[ZstdCompressor.scala:70:37]
wire [255:0] _l2_huf_lit_writer_auto_master_out_a_bits_data; // @[ZstdCompressor.scala:70:37]
wire _l2_huf_lit_writer_auto_master_out_a_bits_corrupt; // @[ZstdCompressor.scala:70:37]
wire _l2_huf_lit_writer_auto_master_out_d_ready; // @[ZstdCompressor.scala:70:37]
wire _l2_huf_lit_writer_io_userif_req_ready; // @[ZstdCompressor.scala:70:37]
wire _l2_huf_lit_writer_io_userif_resp_valid; // @[ZstdCompressor.scala:70:37]
wire [255:0] _l2_huf_lit_writer_io_userif_resp_bits_data; // @[ZstdCompressor.scala:70:37]
wire _l2_huf_lit_writer_io_userif_no_memops_inflight; // @[ZstdCompressor.scala:70:37]
wire _widget_9_auto_anon_in_a_ready; // @[WidthWidget.scala:230:28]
wire _widget_9_auto_anon_in_d_valid; // @[WidthWidget.scala:230:28]
wire [2:0] _widget_9_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:230:28]
wire [1:0] _widget_9_auto_anon_in_d_bits_param; // @[WidthWidget.scala:230:28]
wire [3:0] _widget_9_auto_anon_in_d_bits_size; // @[WidthWidget.scala:230:28]
wire [1:0] _widget_9_auto_anon_in_d_bits_source; // @[WidthWidget.scala:230:28]
wire [2:0] _widget_9_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:230:28]
wire _widget_9_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:230:28]
wire [255:0] _widget_9_auto_anon_in_d_bits_data; // @[WidthWidget.scala:230:28]
wire _widget_9_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:230:28]
wire _l2_huf_jt_writer_auto_master_out_a_valid; // @[ZstdCompressor.scala:67:36]
wire [2:0] _l2_huf_jt_writer_auto_master_out_a_bits_opcode; // @[ZstdCompressor.scala:67:36]
wire [2:0] _l2_huf_jt_writer_auto_master_out_a_bits_param; // @[ZstdCompressor.scala:67:36]
wire [3:0] _l2_huf_jt_writer_auto_master_out_a_bits_size; // @[ZstdCompressor.scala:67:36]
wire [1:0] _l2_huf_jt_writer_auto_master_out_a_bits_source; // @[ZstdCompressor.scala:67:36]
wire [31:0] _l2_huf_jt_writer_auto_master_out_a_bits_address; // @[ZstdCompressor.scala:67:36]
wire [31:0] _l2_huf_jt_writer_auto_master_out_a_bits_mask; // @[ZstdCompressor.scala:67:36]
wire [255:0] _l2_huf_jt_writer_auto_master_out_a_bits_data; // @[ZstdCompressor.scala:67:36]
wire _l2_huf_jt_writer_auto_master_out_a_bits_corrupt; // @[ZstdCompressor.scala:67:36]
wire _l2_huf_jt_writer_auto_master_out_d_ready; // @[ZstdCompressor.scala:67:36]
wire _l2_huf_jt_writer_io_userif_req_ready; // @[ZstdCompressor.scala:67:36]
wire _l2_huf_jt_writer_io_userif_resp_valid; // @[ZstdCompressor.scala:67:36]
wire [255:0] _l2_huf_jt_writer_io_userif_resp_bits_data; // @[ZstdCompressor.scala:67:36]
wire _l2_huf_jt_writer_io_userif_no_memops_inflight; // @[ZstdCompressor.scala:67:36]
wire _widget_8_auto_anon_in_a_ready; // @[WidthWidget.scala:230:28]
wire _widget_8_auto_anon_in_d_valid; // @[WidthWidget.scala:230:28]
wire [2:0] _widget_8_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:230:28]
wire [1:0] _widget_8_auto_anon_in_d_bits_param; // @[WidthWidget.scala:230:28]
wire [3:0] _widget_8_auto_anon_in_d_bits_size; // @[WidthWidget.scala:230:28]
wire [1:0] _widget_8_auto_anon_in_d_bits_source; // @[WidthWidget.scala:230:28]
wire [2:0] _widget_8_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:230:28]
wire _widget_8_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:230:28]
wire [255:0] _widget_8_auto_anon_in_d_bits_data; // @[WidthWidget.scala:230:28]
wire _widget_8_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:230:28]
wire _l2_huf_hdr_writer_auto_master_out_a_valid; // @[ZstdCompressor.scala:64:37]
wire [2:0] _l2_huf_hdr_writer_auto_master_out_a_bits_opcode; // @[ZstdCompressor.scala:64:37]
wire [2:0] _l2_huf_hdr_writer_auto_master_out_a_bits_param; // @[ZstdCompressor.scala:64:37]
wire [3:0] _l2_huf_hdr_writer_auto_master_out_a_bits_size; // @[ZstdCompressor.scala:64:37]
wire [1:0] _l2_huf_hdr_writer_auto_master_out_a_bits_source; // @[ZstdCompressor.scala:64:37]
wire [31:0] _l2_huf_hdr_writer_auto_master_out_a_bits_address; // @[ZstdCompressor.scala:64:37]
wire [31:0] _l2_huf_hdr_writer_auto_master_out_a_bits_mask; // @[ZstdCompressor.scala:64:37]
wire [255:0] _l2_huf_hdr_writer_auto_master_out_a_bits_data; // @[ZstdCompressor.scala:64:37]
wire _l2_huf_hdr_writer_auto_master_out_a_bits_corrupt; // @[ZstdCompressor.scala:64:37]
wire _l2_huf_hdr_writer_auto_master_out_d_ready; // @[ZstdCompressor.scala:64:37]
wire _l2_huf_hdr_writer_io_userif_req_ready; // @[ZstdCompressor.scala:64:37]
wire _l2_huf_hdr_writer_io_userif_resp_valid; // @[ZstdCompressor.scala:64:37]
wire [255:0] _l2_huf_hdr_writer_io_userif_resp_bits_data; // @[ZstdCompressor.scala:64:37]
wire _l2_huf_hdr_writer_io_userif_no_memops_inflight; // @[ZstdCompressor.scala:64:37]
wire _widget_7_auto_anon_in_a_ready; // @[WidthWidget.scala:230:28]
wire _widget_7_auto_anon_in_d_valid; // @[WidthWidget.scala:230:28]
wire [2:0] _widget_7_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:230:28]
wire [1:0] _widget_7_auto_anon_in_d_bits_param; // @[WidthWidget.scala:230:28]
wire [3:0] _widget_7_auto_anon_in_d_bits_size; // @[WidthWidget.scala:230:28]
wire [4:0] _widget_7_auto_anon_in_d_bits_source; // @[WidthWidget.scala:230:28]
wire [2:0] _widget_7_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:230:28]
wire _widget_7_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:230:28]
wire [255:0] _widget_7_auto_anon_in_d_bits_data; // @[WidthWidget.scala:230:28]
wire _widget_7_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:230:28]
wire _l2_huf_dic_writer_auto_master_out_a_valid; // @[ZstdCompressor.scala:61:37]
wire [2:0] _l2_huf_dic_writer_auto_master_out_a_bits_opcode; // @[ZstdCompressor.scala:61:37]
wire [2:0] _l2_huf_dic_writer_auto_master_out_a_bits_param; // @[ZstdCompressor.scala:61:37]
wire [3:0] _l2_huf_dic_writer_auto_master_out_a_bits_size; // @[ZstdCompressor.scala:61:37]
wire [4:0] _l2_huf_dic_writer_auto_master_out_a_bits_source; // @[ZstdCompressor.scala:61:37]
wire [31:0] _l2_huf_dic_writer_auto_master_out_a_bits_address; // @[ZstdCompressor.scala:61:37]
wire [31:0] _l2_huf_dic_writer_auto_master_out_a_bits_mask; // @[ZstdCompressor.scala:61:37]
wire [255:0] _l2_huf_dic_writer_auto_master_out_a_bits_data; // @[ZstdCompressor.scala:61:37]
wire _l2_huf_dic_writer_auto_master_out_a_bits_corrupt; // @[ZstdCompressor.scala:61:37]
wire _l2_huf_dic_writer_auto_master_out_d_ready; // @[ZstdCompressor.scala:61:37]
wire _l2_huf_dic_writer_io_userif_req_ready; // @[ZstdCompressor.scala:61:37]
wire _l2_huf_dic_writer_io_userif_resp_valid; // @[ZstdCompressor.scala:61:37]
wire [255:0] _l2_huf_dic_writer_io_userif_resp_bits_data; // @[ZstdCompressor.scala:61:37]
wire _l2_huf_dic_writer_io_userif_no_memops_inflight; // @[ZstdCompressor.scala:61:37]
wire _widget_6_auto_anon_in_a_ready; // @[WidthWidget.scala:230:28]
wire _widget_6_auto_anon_in_d_valid; // @[WidthWidget.scala:230:28]
wire [2:0] _widget_6_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:230:28]
wire [1:0] _widget_6_auto_anon_in_d_bits_param; // @[WidthWidget.scala:230:28]
wire [3:0] _widget_6_auto_anon_in_d_bits_size; // @[WidthWidget.scala:230:28]
wire [4:0] _widget_6_auto_anon_in_d_bits_source; // @[WidthWidget.scala:230:28]
wire [2:0] _widget_6_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:230:28]
wire _widget_6_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:230:28]
wire [255:0] _widget_6_auto_anon_in_d_bits_data; // @[WidthWidget.scala:230:28]
wire _widget_6_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:230:28]
wire _l2_huf_dic_reader_auto_master_out_a_valid; // @[ZstdCompressor.scala:58:37]
wire [2:0] _l2_huf_dic_reader_auto_master_out_a_bits_opcode; // @[ZstdCompressor.scala:58:37]
wire [2:0] _l2_huf_dic_reader_auto_master_out_a_bits_param; // @[ZstdCompressor.scala:58:37]
wire [3:0] _l2_huf_dic_reader_auto_master_out_a_bits_size; // @[ZstdCompressor.scala:58:37]
wire [4:0] _l2_huf_dic_reader_auto_master_out_a_bits_source; // @[ZstdCompressor.scala:58:37]
wire [31:0] _l2_huf_dic_reader_auto_master_out_a_bits_address; // @[ZstdCompressor.scala:58:37]
wire [31:0] _l2_huf_dic_reader_auto_master_out_a_bits_mask; // @[ZstdCompressor.scala:58:37]
wire [255:0] _l2_huf_dic_reader_auto_master_out_a_bits_data; // @[ZstdCompressor.scala:58:37]
wire _l2_huf_dic_reader_auto_master_out_a_bits_corrupt; // @[ZstdCompressor.scala:58:37]
wire _l2_huf_dic_reader_auto_master_out_d_ready; // @[ZstdCompressor.scala:58:37]
wire _l2_huf_dic_reader_io_userif_req_ready; // @[ZstdCompressor.scala:58:37]
wire _l2_huf_dic_reader_io_userif_resp_valid; // @[ZstdCompressor.scala:58:37]
wire [255:0] _l2_huf_dic_reader_io_userif_resp_bits_data; // @[ZstdCompressor.scala:58:37]
wire _l2_huf_dic_reader_io_userif_no_memops_inflight; // @[ZstdCompressor.scala:58:37]
wire _widget_5_auto_anon_in_a_ready; // @[WidthWidget.scala:230:28]
wire _widget_5_auto_anon_in_d_valid; // @[WidthWidget.scala:230:28]
wire [2:0] _widget_5_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:230:28]
wire [1:0] _widget_5_auto_anon_in_d_bits_param; // @[WidthWidget.scala:230:28]
wire [3:0] _widget_5_auto_anon_in_d_bits_size; // @[WidthWidget.scala:230:28]
wire [4:0] _widget_5_auto_anon_in_d_bits_source; // @[WidthWidget.scala:230:28]
wire [2:0] _widget_5_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:230:28]
wire _widget_5_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:230:28]
wire [255:0] _widget_5_auto_anon_in_d_bits_data; // @[WidthWidget.scala:230:28]
wire _widget_5_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:230:28]
wire _l2_huf_lit_reader_auto_master_out_a_valid; // @[ZstdCompressor.scala:55:37]
wire [2:0] _l2_huf_lit_reader_auto_master_out_a_bits_opcode; // @[ZstdCompressor.scala:55:37]
wire [2:0] _l2_huf_lit_reader_auto_master_out_a_bits_param; // @[ZstdCompressor.scala:55:37]
wire [3:0] _l2_huf_lit_reader_auto_master_out_a_bits_size; // @[ZstdCompressor.scala:55:37]
wire [4:0] _l2_huf_lit_reader_auto_master_out_a_bits_source; // @[ZstdCompressor.scala:55:37]
wire [31:0] _l2_huf_lit_reader_auto_master_out_a_bits_address; // @[ZstdCompressor.scala:55:37]
wire [31:0] _l2_huf_lit_reader_auto_master_out_a_bits_mask; // @[ZstdCompressor.scala:55:37]
wire [255:0] _l2_huf_lit_reader_auto_master_out_a_bits_data; // @[ZstdCompressor.scala:55:37]
wire _l2_huf_lit_reader_auto_master_out_a_bits_corrupt; // @[ZstdCompressor.scala:55:37]
wire _l2_huf_lit_reader_auto_master_out_d_ready; // @[ZstdCompressor.scala:55:37]
wire _l2_huf_lit_reader_io_userif_req_ready; // @[ZstdCompressor.scala:55:37]
wire _l2_huf_lit_reader_io_userif_resp_valid; // @[ZstdCompressor.scala:55:37]
wire [255:0] _l2_huf_lit_reader_io_userif_resp_bits_data; // @[ZstdCompressor.scala:55:37]
wire _l2_huf_lit_reader_io_userif_no_memops_inflight; // @[ZstdCompressor.scala:55:37]
wire _widget_4_auto_anon_in_a_ready; // @[WidthWidget.scala:230:28]
wire _widget_4_auto_anon_in_d_valid; // @[WidthWidget.scala:230:28]
wire [2:0] _widget_4_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:230:28]
wire [1:0] _widget_4_auto_anon_in_d_bits_param; // @[WidthWidget.scala:230:28]
wire [3:0] _widget_4_auto_anon_in_d_bits_size; // @[WidthWidget.scala:230:28]
wire [4:0] _widget_4_auto_anon_in_d_bits_source; // @[WidthWidget.scala:230:28]
wire [2:0] _widget_4_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:230:28]
wire _widget_4_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:230:28]
wire [255:0] _widget_4_auto_anon_in_d_bits_data; // @[WidthWidget.scala:230:28]
wire _widget_4_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:230:28]
wire _l2_mf_litwriter_auto_master_out_a_valid; // @[ZstdCompressor.scala:52:35]
wire [2:0] _l2_mf_litwriter_auto_master_out_a_bits_opcode; // @[ZstdCompressor.scala:52:35]
wire [2:0] _l2_mf_litwriter_auto_master_out_a_bits_param; // @[ZstdCompressor.scala:52:35]
wire [3:0] _l2_mf_litwriter_auto_master_out_a_bits_size; // @[ZstdCompressor.scala:52:35]
wire [4:0] _l2_mf_litwriter_auto_master_out_a_bits_source; // @[ZstdCompressor.scala:52:35]
wire [31:0] _l2_mf_litwriter_auto_master_out_a_bits_address; // @[ZstdCompressor.scala:52:35]
wire [31:0] _l2_mf_litwriter_auto_master_out_a_bits_mask; // @[ZstdCompressor.scala:52:35]
wire [255:0] _l2_mf_litwriter_auto_master_out_a_bits_data; // @[ZstdCompressor.scala:52:35]
wire _l2_mf_litwriter_auto_master_out_a_bits_corrupt; // @[ZstdCompressor.scala:52:35]
wire _l2_mf_litwriter_auto_master_out_d_ready; // @[ZstdCompressor.scala:52:35]
wire _l2_mf_litwriter_io_userif_req_ready; // @[ZstdCompressor.scala:52:35]
wire _l2_mf_litwriter_io_userif_resp_valid; // @[ZstdCompressor.scala:52:35]
wire [255:0] _l2_mf_litwriter_io_userif_resp_bits_data; // @[ZstdCompressor.scala:52:35]
wire _l2_mf_litwriter_io_userif_no_memops_inflight; // @[ZstdCompressor.scala:52:35]
wire _widget_3_auto_anon_in_a_ready; // @[WidthWidget.scala:230:28]
wire _widget_3_auto_anon_in_d_valid; // @[WidthWidget.scala:230:28]
wire [2:0] _widget_3_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:230:28]
wire [1:0] _widget_3_auto_anon_in_d_bits_param; // @[WidthWidget.scala:230:28]
wire [3:0] _widget_3_auto_anon_in_d_bits_size; // @[WidthWidget.scala:230:28]
wire [4:0] _widget_3_auto_anon_in_d_bits_source; // @[WidthWidget.scala:230:28]
wire [2:0] _widget_3_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:230:28]
wire _widget_3_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:230:28]
wire [255:0] _widget_3_auto_anon_in_d_bits_data; // @[WidthWidget.scala:230:28]
wire _widget_3_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:230:28]
wire _l2_mf_seqwriter_auto_master_out_a_valid; // @[ZstdCompressor.scala:49:35]
wire [2:0] _l2_mf_seqwriter_auto_master_out_a_bits_opcode; // @[ZstdCompressor.scala:49:35]
wire [2:0] _l2_mf_seqwriter_auto_master_out_a_bits_param; // @[ZstdCompressor.scala:49:35]
wire [3:0] _l2_mf_seqwriter_auto_master_out_a_bits_size; // @[ZstdCompressor.scala:49:35]
wire [4:0] _l2_mf_seqwriter_auto_master_out_a_bits_source; // @[ZstdCompressor.scala:49:35]
wire [31:0] _l2_mf_seqwriter_auto_master_out_a_bits_address; // @[ZstdCompressor.scala:49:35]
wire [31:0] _l2_mf_seqwriter_auto_master_out_a_bits_mask; // @[ZstdCompressor.scala:49:35]
wire [255:0] _l2_mf_seqwriter_auto_master_out_a_bits_data; // @[ZstdCompressor.scala:49:35]
wire _l2_mf_seqwriter_auto_master_out_a_bits_corrupt; // @[ZstdCompressor.scala:49:35]
wire _l2_mf_seqwriter_auto_master_out_d_ready; // @[ZstdCompressor.scala:49:35]
wire _l2_mf_seqwriter_io_userif_req_ready; // @[ZstdCompressor.scala:49:35]
wire _l2_mf_seqwriter_io_userif_resp_valid; // @[ZstdCompressor.scala:49:35]
wire [255:0] _l2_mf_seqwriter_io_userif_resp_bits_data; // @[ZstdCompressor.scala:49:35]
wire _l2_mf_seqwriter_io_userif_no_memops_inflight; // @[ZstdCompressor.scala:49:35]
wire _widget_2_auto_anon_in_a_ready; // @[WidthWidget.scala:230:28]
wire _widget_2_auto_anon_in_d_valid; // @[WidthWidget.scala:230:28]
wire [2:0] _widget_2_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:230:28]
wire [1:0] _widget_2_auto_anon_in_d_bits_param; // @[WidthWidget.scala:230:28]
wire [3:0] _widget_2_auto_anon_in_d_bits_size; // @[WidthWidget.scala:230:28]
wire [4:0] _widget_2_auto_anon_in_d_bits_source; // @[WidthWidget.scala:230:28]
wire [2:0] _widget_2_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:230:28]
wire _widget_2_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:230:28]
wire [255:0] _widget_2_auto_anon_in_d_bits_data; // @[WidthWidget.scala:230:28]
wire _widget_2_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:230:28]
wire _l2_mf_reader_auto_master_out_a_valid; // @[ZstdCompressor.scala:46:32]
wire [2:0] _l2_mf_reader_auto_master_out_a_bits_opcode; // @[ZstdCompressor.scala:46:32]
wire [2:0] _l2_mf_reader_auto_master_out_a_bits_param; // @[ZstdCompressor.scala:46:32]
wire [3:0] _l2_mf_reader_auto_master_out_a_bits_size; // @[ZstdCompressor.scala:46:32]
wire [4:0] _l2_mf_reader_auto_master_out_a_bits_source; // @[ZstdCompressor.scala:46:32]
wire [31:0] _l2_mf_reader_auto_master_out_a_bits_address; // @[ZstdCompressor.scala:46:32]
wire [31:0] _l2_mf_reader_auto_master_out_a_bits_mask; // @[ZstdCompressor.scala:46:32]
wire [255:0] _l2_mf_reader_auto_master_out_a_bits_data; // @[ZstdCompressor.scala:46:32]
wire _l2_mf_reader_auto_master_out_a_bits_corrupt; // @[ZstdCompressor.scala:46:32]
wire _l2_mf_reader_auto_master_out_d_ready; // @[ZstdCompressor.scala:46:32]
wire _l2_mf_reader_io_userif_req_ready; // @[ZstdCompressor.scala:46:32]
wire _l2_mf_reader_io_userif_resp_valid; // @[ZstdCompressor.scala:46:32]
wire [255:0] _l2_mf_reader_io_userif_resp_bits_data; // @[ZstdCompressor.scala:46:32]
wire _l2_mf_reader_io_userif_no_memops_inflight; // @[ZstdCompressor.scala:46:32]
wire _widget_1_auto_anon_in_a_ready; // @[WidthWidget.scala:230:28]
wire _widget_1_auto_anon_in_d_valid; // @[WidthWidget.scala:230:28]
wire [2:0] _widget_1_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:230:28]
wire [1:0] _widget_1_auto_anon_in_d_bits_param; // @[WidthWidget.scala:230:28]
wire [3:0] _widget_1_auto_anon_in_d_bits_size; // @[WidthWidget.scala:230:28]
wire [1:0] _widget_1_auto_anon_in_d_bits_source; // @[WidthWidget.scala:230:28]
wire [2:0] _widget_1_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:230:28]
wire _widget_1_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:230:28]
wire [255:0] _widget_1_auto_anon_in_d_bits_data; // @[WidthWidget.scala:230:28]
wire _widget_1_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:230:28]
wire _l2_bhdr_writer_auto_master_out_a_valid; // @[ZstdCompressor.scala:42:34]
wire [2:0] _l2_bhdr_writer_auto_master_out_a_bits_opcode; // @[ZstdCompressor.scala:42:34]
wire [2:0] _l2_bhdr_writer_auto_master_out_a_bits_param; // @[ZstdCompressor.scala:42:34]
wire [3:0] _l2_bhdr_writer_auto_master_out_a_bits_size; // @[ZstdCompressor.scala:42:34]
wire [1:0] _l2_bhdr_writer_auto_master_out_a_bits_source; // @[ZstdCompressor.scala:42:34]
wire [31:0] _l2_bhdr_writer_auto_master_out_a_bits_address; // @[ZstdCompressor.scala:42:34]
wire [31:0] _l2_bhdr_writer_auto_master_out_a_bits_mask; // @[ZstdCompressor.scala:42:34]
wire [255:0] _l2_bhdr_writer_auto_master_out_a_bits_data; // @[ZstdCompressor.scala:42:34]
wire _l2_bhdr_writer_auto_master_out_a_bits_corrupt; // @[ZstdCompressor.scala:42:34]
wire _l2_bhdr_writer_auto_master_out_d_ready; // @[ZstdCompressor.scala:42:34]
wire _l2_bhdr_writer_io_userif_req_ready; // @[ZstdCompressor.scala:42:34]
wire _l2_bhdr_writer_io_userif_resp_valid; // @[ZstdCompressor.scala:42:34]
wire [255:0] _l2_bhdr_writer_io_userif_resp_bits_data; // @[ZstdCompressor.scala:42:34]
wire _l2_bhdr_writer_io_userif_no_memops_inflight; // @[ZstdCompressor.scala:42:34]
wire _widget_auto_anon_in_a_ready; // @[WidthWidget.scala:230:28]
wire _widget_auto_anon_in_d_valid; // @[WidthWidget.scala:230:28]
wire [2:0] _widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:230:28]
wire [1:0] _widget_auto_anon_in_d_bits_param; // @[WidthWidget.scala:230:28]
wire [3:0] _widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:230:28]
wire [1:0] _widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:230:28]
wire [2:0] _widget_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:230:28]
wire _widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:230:28]
wire [255:0] _widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:230:28]
wire _widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:230:28]
wire _l2_fhdr_writer_auto_master_out_a_valid; // @[ZstdCompressor.scala:38:34]
wire [2:0] _l2_fhdr_writer_auto_master_out_a_bits_opcode; // @[ZstdCompressor.scala:38:34]
wire [2:0] _l2_fhdr_writer_auto_master_out_a_bits_param; // @[ZstdCompressor.scala:38:34]
wire [3:0] _l2_fhdr_writer_auto_master_out_a_bits_size; // @[ZstdCompressor.scala:38:34]
wire [1:0] _l2_fhdr_writer_auto_master_out_a_bits_source; // @[ZstdCompressor.scala:38:34]
wire [31:0] _l2_fhdr_writer_auto_master_out_a_bits_address; // @[ZstdCompressor.scala:38:34]
wire [31:0] _l2_fhdr_writer_auto_master_out_a_bits_mask; // @[ZstdCompressor.scala:38:34]
wire [255:0] _l2_fhdr_writer_auto_master_out_a_bits_data; // @[ZstdCompressor.scala:38:34]
wire _l2_fhdr_writer_auto_master_out_a_bits_corrupt; // @[ZstdCompressor.scala:38:34]
wire _l2_fhdr_writer_auto_master_out_d_ready; // @[ZstdCompressor.scala:38:34]
wire _l2_fhdr_writer_io_userif_req_ready; // @[ZstdCompressor.scala:38:34]
wire _l2_fhdr_writer_io_userif_resp_valid; // @[ZstdCompressor.scala:38:34]
wire [255:0] _l2_fhdr_writer_io_userif_resp_bits_data; // @[ZstdCompressor.scala:38:34]
wire _l2_fhdr_writer_io_userif_no_memops_inflight; // @[ZstdCompressor.scala:38:34]
wire auto_tl_out_17_a_ready_0 = auto_tl_out_17_a_ready; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_17_d_valid_0 = auto_tl_out_17_d_valid; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_17_d_bits_opcode_0 = auto_tl_out_17_d_bits_opcode; // @[ZstdCompressor.scala:95:7]
wire [1:0] auto_tl_out_17_d_bits_param_0 = auto_tl_out_17_d_bits_param; // @[ZstdCompressor.scala:95:7]
wire [3:0] auto_tl_out_17_d_bits_size_0 = auto_tl_out_17_d_bits_size; // @[ZstdCompressor.scala:95:7]
wire [4:0] auto_tl_out_17_d_bits_source_0 = auto_tl_out_17_d_bits_source; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_17_d_bits_sink_0 = auto_tl_out_17_d_bits_sink; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_17_d_bits_denied_0 = auto_tl_out_17_d_bits_denied; // @[ZstdCompressor.scala:95:7]
wire [63:0] auto_tl_out_17_d_bits_data_0 = auto_tl_out_17_d_bits_data; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_17_d_bits_corrupt_0 = auto_tl_out_17_d_bits_corrupt; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_16_a_ready_0 = auto_tl_out_16_a_ready; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_16_d_valid_0 = auto_tl_out_16_d_valid; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_16_d_bits_opcode_0 = auto_tl_out_16_d_bits_opcode; // @[ZstdCompressor.scala:95:7]
wire [1:0] auto_tl_out_16_d_bits_param_0 = auto_tl_out_16_d_bits_param; // @[ZstdCompressor.scala:95:7]
wire [3:0] auto_tl_out_16_d_bits_size_0 = auto_tl_out_16_d_bits_size; // @[ZstdCompressor.scala:95:7]
wire [4:0] auto_tl_out_16_d_bits_source_0 = auto_tl_out_16_d_bits_source; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_16_d_bits_sink_0 = auto_tl_out_16_d_bits_sink; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_16_d_bits_denied_0 = auto_tl_out_16_d_bits_denied; // @[ZstdCompressor.scala:95:7]
wire [63:0] auto_tl_out_16_d_bits_data_0 = auto_tl_out_16_d_bits_data; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_16_d_bits_corrupt_0 = auto_tl_out_16_d_bits_corrupt; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_15_a_ready_0 = auto_tl_out_15_a_ready; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_15_d_valid_0 = auto_tl_out_15_d_valid; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_15_d_bits_opcode_0 = auto_tl_out_15_d_bits_opcode; // @[ZstdCompressor.scala:95:7]
wire [1:0] auto_tl_out_15_d_bits_param_0 = auto_tl_out_15_d_bits_param; // @[ZstdCompressor.scala:95:7]
wire [3:0] auto_tl_out_15_d_bits_size_0 = auto_tl_out_15_d_bits_size; // @[ZstdCompressor.scala:95:7]
wire [4:0] auto_tl_out_15_d_bits_source_0 = auto_tl_out_15_d_bits_source; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_15_d_bits_sink_0 = auto_tl_out_15_d_bits_sink; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_15_d_bits_denied_0 = auto_tl_out_15_d_bits_denied; // @[ZstdCompressor.scala:95:7]
wire [63:0] auto_tl_out_15_d_bits_data_0 = auto_tl_out_15_d_bits_data; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_15_d_bits_corrupt_0 = auto_tl_out_15_d_bits_corrupt; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_14_a_ready_0 = auto_tl_out_14_a_ready; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_14_d_valid_0 = auto_tl_out_14_d_valid; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_14_d_bits_opcode_0 = auto_tl_out_14_d_bits_opcode; // @[ZstdCompressor.scala:95:7]
wire [1:0] auto_tl_out_14_d_bits_param_0 = auto_tl_out_14_d_bits_param; // @[ZstdCompressor.scala:95:7]
wire [3:0] auto_tl_out_14_d_bits_size_0 = auto_tl_out_14_d_bits_size; // @[ZstdCompressor.scala:95:7]
wire [4:0] auto_tl_out_14_d_bits_source_0 = auto_tl_out_14_d_bits_source; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_14_d_bits_sink_0 = auto_tl_out_14_d_bits_sink; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_14_d_bits_denied_0 = auto_tl_out_14_d_bits_denied; // @[ZstdCompressor.scala:95:7]
wire [63:0] auto_tl_out_14_d_bits_data_0 = auto_tl_out_14_d_bits_data; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_14_d_bits_corrupt_0 = auto_tl_out_14_d_bits_corrupt; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_13_a_ready_0 = auto_tl_out_13_a_ready; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_13_d_valid_0 = auto_tl_out_13_d_valid; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_13_d_bits_opcode_0 = auto_tl_out_13_d_bits_opcode; // @[ZstdCompressor.scala:95:7]
wire [1:0] auto_tl_out_13_d_bits_param_0 = auto_tl_out_13_d_bits_param; // @[ZstdCompressor.scala:95:7]
wire [3:0] auto_tl_out_13_d_bits_size_0 = auto_tl_out_13_d_bits_size; // @[ZstdCompressor.scala:95:7]
wire [4:0] auto_tl_out_13_d_bits_source_0 = auto_tl_out_13_d_bits_source; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_13_d_bits_sink_0 = auto_tl_out_13_d_bits_sink; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_13_d_bits_denied_0 = auto_tl_out_13_d_bits_denied; // @[ZstdCompressor.scala:95:7]
wire [63:0] auto_tl_out_13_d_bits_data_0 = auto_tl_out_13_d_bits_data; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_13_d_bits_corrupt_0 = auto_tl_out_13_d_bits_corrupt; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_12_a_ready_0 = auto_tl_out_12_a_ready; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_12_d_valid_0 = auto_tl_out_12_d_valid; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_12_d_bits_opcode_0 = auto_tl_out_12_d_bits_opcode; // @[ZstdCompressor.scala:95:7]
wire [1:0] auto_tl_out_12_d_bits_param_0 = auto_tl_out_12_d_bits_param; // @[ZstdCompressor.scala:95:7]
wire [3:0] auto_tl_out_12_d_bits_size_0 = auto_tl_out_12_d_bits_size; // @[ZstdCompressor.scala:95:7]
wire [4:0] auto_tl_out_12_d_bits_source_0 = auto_tl_out_12_d_bits_source; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_12_d_bits_sink_0 = auto_tl_out_12_d_bits_sink; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_12_d_bits_denied_0 = auto_tl_out_12_d_bits_denied; // @[ZstdCompressor.scala:95:7]
wire [63:0] auto_tl_out_12_d_bits_data_0 = auto_tl_out_12_d_bits_data; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_12_d_bits_corrupt_0 = auto_tl_out_12_d_bits_corrupt; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_11_a_ready_0 = auto_tl_out_11_a_ready; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_11_d_valid_0 = auto_tl_out_11_d_valid; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_11_d_bits_opcode_0 = auto_tl_out_11_d_bits_opcode; // @[ZstdCompressor.scala:95:7]
wire [1:0] auto_tl_out_11_d_bits_param_0 = auto_tl_out_11_d_bits_param; // @[ZstdCompressor.scala:95:7]
wire [3:0] auto_tl_out_11_d_bits_size_0 = auto_tl_out_11_d_bits_size; // @[ZstdCompressor.scala:95:7]
wire [4:0] auto_tl_out_11_d_bits_source_0 = auto_tl_out_11_d_bits_source; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_11_d_bits_sink_0 = auto_tl_out_11_d_bits_sink; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_11_d_bits_denied_0 = auto_tl_out_11_d_bits_denied; // @[ZstdCompressor.scala:95:7]
wire [63:0] auto_tl_out_11_d_bits_data_0 = auto_tl_out_11_d_bits_data; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_11_d_bits_corrupt_0 = auto_tl_out_11_d_bits_corrupt; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_10_a_ready_0 = auto_tl_out_10_a_ready; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_10_d_valid_0 = auto_tl_out_10_d_valid; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_10_d_bits_opcode_0 = auto_tl_out_10_d_bits_opcode; // @[ZstdCompressor.scala:95:7]
wire [1:0] auto_tl_out_10_d_bits_param_0 = auto_tl_out_10_d_bits_param; // @[ZstdCompressor.scala:95:7]
wire [3:0] auto_tl_out_10_d_bits_size_0 = auto_tl_out_10_d_bits_size; // @[ZstdCompressor.scala:95:7]
wire [4:0] auto_tl_out_10_d_bits_source_0 = auto_tl_out_10_d_bits_source; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_10_d_bits_sink_0 = auto_tl_out_10_d_bits_sink; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_10_d_bits_denied_0 = auto_tl_out_10_d_bits_denied; // @[ZstdCompressor.scala:95:7]
wire [63:0] auto_tl_out_10_d_bits_data_0 = auto_tl_out_10_d_bits_data; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_10_d_bits_corrupt_0 = auto_tl_out_10_d_bits_corrupt; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_9_a_ready_0 = auto_tl_out_9_a_ready; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_9_d_valid_0 = auto_tl_out_9_d_valid; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_9_d_bits_opcode_0 = auto_tl_out_9_d_bits_opcode; // @[ZstdCompressor.scala:95:7]
wire [1:0] auto_tl_out_9_d_bits_param_0 = auto_tl_out_9_d_bits_param; // @[ZstdCompressor.scala:95:7]
wire [3:0] auto_tl_out_9_d_bits_size_0 = auto_tl_out_9_d_bits_size; // @[ZstdCompressor.scala:95:7]
wire [1:0] auto_tl_out_9_d_bits_source_0 = auto_tl_out_9_d_bits_source; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_9_d_bits_sink_0 = auto_tl_out_9_d_bits_sink; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_9_d_bits_denied_0 = auto_tl_out_9_d_bits_denied; // @[ZstdCompressor.scala:95:7]
wire [63:0] auto_tl_out_9_d_bits_data_0 = auto_tl_out_9_d_bits_data; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_9_d_bits_corrupt_0 = auto_tl_out_9_d_bits_corrupt; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_8_a_ready_0 = auto_tl_out_8_a_ready; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_8_d_valid_0 = auto_tl_out_8_d_valid; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_8_d_bits_opcode_0 = auto_tl_out_8_d_bits_opcode; // @[ZstdCompressor.scala:95:7]
wire [1:0] auto_tl_out_8_d_bits_param_0 = auto_tl_out_8_d_bits_param; // @[ZstdCompressor.scala:95:7]
wire [3:0] auto_tl_out_8_d_bits_size_0 = auto_tl_out_8_d_bits_size; // @[ZstdCompressor.scala:95:7]
wire [1:0] auto_tl_out_8_d_bits_source_0 = auto_tl_out_8_d_bits_source; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_8_d_bits_sink_0 = auto_tl_out_8_d_bits_sink; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_8_d_bits_denied_0 = auto_tl_out_8_d_bits_denied; // @[ZstdCompressor.scala:95:7]
wire [63:0] auto_tl_out_8_d_bits_data_0 = auto_tl_out_8_d_bits_data; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_8_d_bits_corrupt_0 = auto_tl_out_8_d_bits_corrupt; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_7_a_ready_0 = auto_tl_out_7_a_ready; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_7_d_valid_0 = auto_tl_out_7_d_valid; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_7_d_bits_opcode_0 = auto_tl_out_7_d_bits_opcode; // @[ZstdCompressor.scala:95:7]
wire [1:0] auto_tl_out_7_d_bits_param_0 = auto_tl_out_7_d_bits_param; // @[ZstdCompressor.scala:95:7]
wire [3:0] auto_tl_out_7_d_bits_size_0 = auto_tl_out_7_d_bits_size; // @[ZstdCompressor.scala:95:7]
wire [4:0] auto_tl_out_7_d_bits_source_0 = auto_tl_out_7_d_bits_source; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_7_d_bits_sink_0 = auto_tl_out_7_d_bits_sink; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_7_d_bits_denied_0 = auto_tl_out_7_d_bits_denied; // @[ZstdCompressor.scala:95:7]
wire [63:0] auto_tl_out_7_d_bits_data_0 = auto_tl_out_7_d_bits_data; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_7_d_bits_corrupt_0 = auto_tl_out_7_d_bits_corrupt; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_6_a_ready_0 = auto_tl_out_6_a_ready; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_6_d_valid_0 = auto_tl_out_6_d_valid; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_6_d_bits_opcode_0 = auto_tl_out_6_d_bits_opcode; // @[ZstdCompressor.scala:95:7]
wire [1:0] auto_tl_out_6_d_bits_param_0 = auto_tl_out_6_d_bits_param; // @[ZstdCompressor.scala:95:7]
wire [3:0] auto_tl_out_6_d_bits_size_0 = auto_tl_out_6_d_bits_size; // @[ZstdCompressor.scala:95:7]
wire [4:0] auto_tl_out_6_d_bits_source_0 = auto_tl_out_6_d_bits_source; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_6_d_bits_sink_0 = auto_tl_out_6_d_bits_sink; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_6_d_bits_denied_0 = auto_tl_out_6_d_bits_denied; // @[ZstdCompressor.scala:95:7]
wire [63:0] auto_tl_out_6_d_bits_data_0 = auto_tl_out_6_d_bits_data; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_6_d_bits_corrupt_0 = auto_tl_out_6_d_bits_corrupt; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_5_a_ready_0 = auto_tl_out_5_a_ready; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_5_d_valid_0 = auto_tl_out_5_d_valid; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_5_d_bits_opcode_0 = auto_tl_out_5_d_bits_opcode; // @[ZstdCompressor.scala:95:7]
wire [1:0] auto_tl_out_5_d_bits_param_0 = auto_tl_out_5_d_bits_param; // @[ZstdCompressor.scala:95:7]
wire [3:0] auto_tl_out_5_d_bits_size_0 = auto_tl_out_5_d_bits_size; // @[ZstdCompressor.scala:95:7]
wire [4:0] auto_tl_out_5_d_bits_source_0 = auto_tl_out_5_d_bits_source; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_5_d_bits_sink_0 = auto_tl_out_5_d_bits_sink; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_5_d_bits_denied_0 = auto_tl_out_5_d_bits_denied; // @[ZstdCompressor.scala:95:7]
wire [63:0] auto_tl_out_5_d_bits_data_0 = auto_tl_out_5_d_bits_data; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_5_d_bits_corrupt_0 = auto_tl_out_5_d_bits_corrupt; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_4_a_ready_0 = auto_tl_out_4_a_ready; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_4_d_valid_0 = auto_tl_out_4_d_valid; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_4_d_bits_opcode_0 = auto_tl_out_4_d_bits_opcode; // @[ZstdCompressor.scala:95:7]
wire [1:0] auto_tl_out_4_d_bits_param_0 = auto_tl_out_4_d_bits_param; // @[ZstdCompressor.scala:95:7]
wire [3:0] auto_tl_out_4_d_bits_size_0 = auto_tl_out_4_d_bits_size; // @[ZstdCompressor.scala:95:7]
wire [4:0] auto_tl_out_4_d_bits_source_0 = auto_tl_out_4_d_bits_source; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_4_d_bits_sink_0 = auto_tl_out_4_d_bits_sink; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_4_d_bits_denied_0 = auto_tl_out_4_d_bits_denied; // @[ZstdCompressor.scala:95:7]
wire [63:0] auto_tl_out_4_d_bits_data_0 = auto_tl_out_4_d_bits_data; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_4_d_bits_corrupt_0 = auto_tl_out_4_d_bits_corrupt; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_3_a_ready_0 = auto_tl_out_3_a_ready; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_3_d_valid_0 = auto_tl_out_3_d_valid; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_3_d_bits_opcode_0 = auto_tl_out_3_d_bits_opcode; // @[ZstdCompressor.scala:95:7]
wire [1:0] auto_tl_out_3_d_bits_param_0 = auto_tl_out_3_d_bits_param; // @[ZstdCompressor.scala:95:7]
wire [3:0] auto_tl_out_3_d_bits_size_0 = auto_tl_out_3_d_bits_size; // @[ZstdCompressor.scala:95:7]
wire [4:0] auto_tl_out_3_d_bits_source_0 = auto_tl_out_3_d_bits_source; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_3_d_bits_sink_0 = auto_tl_out_3_d_bits_sink; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_3_d_bits_denied_0 = auto_tl_out_3_d_bits_denied; // @[ZstdCompressor.scala:95:7]
wire [63:0] auto_tl_out_3_d_bits_data_0 = auto_tl_out_3_d_bits_data; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_3_d_bits_corrupt_0 = auto_tl_out_3_d_bits_corrupt; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_2_a_ready_0 = auto_tl_out_2_a_ready; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_2_d_valid_0 = auto_tl_out_2_d_valid; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_2_d_bits_opcode_0 = auto_tl_out_2_d_bits_opcode; // @[ZstdCompressor.scala:95:7]
wire [1:0] auto_tl_out_2_d_bits_param_0 = auto_tl_out_2_d_bits_param; // @[ZstdCompressor.scala:95:7]
wire [3:0] auto_tl_out_2_d_bits_size_0 = auto_tl_out_2_d_bits_size; // @[ZstdCompressor.scala:95:7]
wire [4:0] auto_tl_out_2_d_bits_source_0 = auto_tl_out_2_d_bits_source; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_2_d_bits_sink_0 = auto_tl_out_2_d_bits_sink; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_2_d_bits_denied_0 = auto_tl_out_2_d_bits_denied; // @[ZstdCompressor.scala:95:7]
wire [63:0] auto_tl_out_2_d_bits_data_0 = auto_tl_out_2_d_bits_data; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_2_d_bits_corrupt_0 = auto_tl_out_2_d_bits_corrupt; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_1_a_ready_0 = auto_tl_out_1_a_ready; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_1_d_valid_0 = auto_tl_out_1_d_valid; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_1_d_bits_opcode_0 = auto_tl_out_1_d_bits_opcode; // @[ZstdCompressor.scala:95:7]
wire [1:0] auto_tl_out_1_d_bits_param_0 = auto_tl_out_1_d_bits_param; // @[ZstdCompressor.scala:95:7]
wire [3:0] auto_tl_out_1_d_bits_size_0 = auto_tl_out_1_d_bits_size; // @[ZstdCompressor.scala:95:7]
wire [1:0] auto_tl_out_1_d_bits_source_0 = auto_tl_out_1_d_bits_source; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_1_d_bits_sink_0 = auto_tl_out_1_d_bits_sink; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_1_d_bits_denied_0 = auto_tl_out_1_d_bits_denied; // @[ZstdCompressor.scala:95:7]
wire [63:0] auto_tl_out_1_d_bits_data_0 = auto_tl_out_1_d_bits_data; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_1_d_bits_corrupt_0 = auto_tl_out_1_d_bits_corrupt; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_0_a_ready_0 = auto_tl_out_0_a_ready; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_0_d_valid_0 = auto_tl_out_0_d_valid; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_0_d_bits_opcode_0 = auto_tl_out_0_d_bits_opcode; // @[ZstdCompressor.scala:95:7]
wire [1:0] auto_tl_out_0_d_bits_param_0 = auto_tl_out_0_d_bits_param; // @[ZstdCompressor.scala:95:7]
wire [3:0] auto_tl_out_0_d_bits_size_0 = auto_tl_out_0_d_bits_size; // @[ZstdCompressor.scala:95:7]
wire [1:0] auto_tl_out_0_d_bits_source_0 = auto_tl_out_0_d_bits_source; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_0_d_bits_sink_0 = auto_tl_out_0_d_bits_sink; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_0_d_bits_denied_0 = auto_tl_out_0_d_bits_denied; // @[ZstdCompressor.scala:95:7]
wire [63:0] auto_tl_out_0_d_bits_data_0 = auto_tl_out_0_d_bits_data; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_0_d_bits_corrupt_0 = auto_tl_out_0_d_bits_corrupt; // @[ZstdCompressor.scala:95:7]
wire io_cmd_valid_0 = io_cmd_valid; // @[ZstdCompressor.scala:95:7]
wire [6:0] io_cmd_bits_inst_funct_0 = io_cmd_bits_inst_funct; // @[ZstdCompressor.scala:95:7]
wire [4:0] io_cmd_bits_inst_rs2_0 = io_cmd_bits_inst_rs2; // @[ZstdCompressor.scala:95:7]
wire [4:0] io_cmd_bits_inst_rs1_0 = io_cmd_bits_inst_rs1; // @[ZstdCompressor.scala:95:7]
wire io_cmd_bits_inst_xd_0 = io_cmd_bits_inst_xd; // @[ZstdCompressor.scala:95:7]
wire io_cmd_bits_inst_xs1_0 = io_cmd_bits_inst_xs1; // @[ZstdCompressor.scala:95:7]
wire io_cmd_bits_inst_xs2_0 = io_cmd_bits_inst_xs2; // @[ZstdCompressor.scala:95:7]
wire [4:0] io_cmd_bits_inst_rd_0 = io_cmd_bits_inst_rd; // @[ZstdCompressor.scala:95:7]
wire [6:0] io_cmd_bits_inst_opcode_0 = io_cmd_bits_inst_opcode; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_cmd_bits_rs1_0 = io_cmd_bits_rs1; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_cmd_bits_rs2_0 = io_cmd_bits_rs2; // @[ZstdCompressor.scala:95:7]
wire io_cmd_bits_status_debug_0 = io_cmd_bits_status_debug; // @[ZstdCompressor.scala:95:7]
wire io_cmd_bits_status_cease_0 = io_cmd_bits_status_cease; // @[ZstdCompressor.scala:95:7]
wire io_cmd_bits_status_wfi_0 = io_cmd_bits_status_wfi; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_cmd_bits_status_isa_0 = io_cmd_bits_status_isa; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_cmd_bits_status_dprv_0 = io_cmd_bits_status_dprv; // @[ZstdCompressor.scala:95:7]
wire io_cmd_bits_status_dv_0 = io_cmd_bits_status_dv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_cmd_bits_status_prv_0 = io_cmd_bits_status_prv; // @[ZstdCompressor.scala:95:7]
wire io_cmd_bits_status_v_0 = io_cmd_bits_status_v; // @[ZstdCompressor.scala:95:7]
wire io_cmd_bits_status_sd_0 = io_cmd_bits_status_sd; // @[ZstdCompressor.scala:95:7]
wire [22:0] io_cmd_bits_status_zero2_0 = io_cmd_bits_status_zero2; // @[ZstdCompressor.scala:95:7]
wire io_cmd_bits_status_mpv_0 = io_cmd_bits_status_mpv; // @[ZstdCompressor.scala:95:7]
wire io_cmd_bits_status_gva_0 = io_cmd_bits_status_gva; // @[ZstdCompressor.scala:95:7]
wire io_cmd_bits_status_mbe_0 = io_cmd_bits_status_mbe; // @[ZstdCompressor.scala:95:7]
wire io_cmd_bits_status_sbe_0 = io_cmd_bits_status_sbe; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_cmd_bits_status_sxl_0 = io_cmd_bits_status_sxl; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_cmd_bits_status_uxl_0 = io_cmd_bits_status_uxl; // @[ZstdCompressor.scala:95:7]
wire io_cmd_bits_status_sd_rv32_0 = io_cmd_bits_status_sd_rv32; // @[ZstdCompressor.scala:95:7]
wire [7:0] io_cmd_bits_status_zero1_0 = io_cmd_bits_status_zero1; // @[ZstdCompressor.scala:95:7]
wire io_cmd_bits_status_tsr_0 = io_cmd_bits_status_tsr; // @[ZstdCompressor.scala:95:7]
wire io_cmd_bits_status_tw_0 = io_cmd_bits_status_tw; // @[ZstdCompressor.scala:95:7]
wire io_cmd_bits_status_tvm_0 = io_cmd_bits_status_tvm; // @[ZstdCompressor.scala:95:7]
wire io_cmd_bits_status_mxr_0 = io_cmd_bits_status_mxr; // @[ZstdCompressor.scala:95:7]
wire io_cmd_bits_status_sum_0 = io_cmd_bits_status_sum; // @[ZstdCompressor.scala:95:7]
wire io_cmd_bits_status_mprv_0 = io_cmd_bits_status_mprv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_cmd_bits_status_xs_0 = io_cmd_bits_status_xs; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_cmd_bits_status_fs_0 = io_cmd_bits_status_fs; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_cmd_bits_status_mpp_0 = io_cmd_bits_status_mpp; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_cmd_bits_status_vs_0 = io_cmd_bits_status_vs; // @[ZstdCompressor.scala:95:7]
wire io_cmd_bits_status_spp_0 = io_cmd_bits_status_spp; // @[ZstdCompressor.scala:95:7]
wire io_cmd_bits_status_mpie_0 = io_cmd_bits_status_mpie; // @[ZstdCompressor.scala:95:7]
wire io_cmd_bits_status_ube_0 = io_cmd_bits_status_ube; // @[ZstdCompressor.scala:95:7]
wire io_cmd_bits_status_spie_0 = io_cmd_bits_status_spie; // @[ZstdCompressor.scala:95:7]
wire io_cmd_bits_status_upie_0 = io_cmd_bits_status_upie; // @[ZstdCompressor.scala:95:7]
wire io_cmd_bits_status_mie_0 = io_cmd_bits_status_mie; // @[ZstdCompressor.scala:95:7]
wire io_cmd_bits_status_hie_0 = io_cmd_bits_status_hie; // @[ZstdCompressor.scala:95:7]
wire io_cmd_bits_status_sie_0 = io_cmd_bits_status_sie; // @[ZstdCompressor.scala:95:7]
wire io_cmd_bits_status_uie_0 = io_cmd_bits_status_uie; // @[ZstdCompressor.scala:95:7]
wire io_resp_ready_0 = io_resp_ready; // @[ZstdCompressor.scala:95:7]
wire io_mem_req_ready_0 = io_mem_req_ready; // @[ZstdCompressor.scala:95:7]
wire io_mem_resp_valid_0 = io_mem_resp_valid; // @[ZstdCompressor.scala:95:7]
wire [39:0] io_mem_resp_bits_addr_0 = io_mem_resp_bits_addr; // @[ZstdCompressor.scala:95:7]
wire [7:0] io_mem_resp_bits_tag_0 = io_mem_resp_bits_tag; // @[ZstdCompressor.scala:95:7]
wire [4:0] io_mem_resp_bits_cmd_0 = io_mem_resp_bits_cmd; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_mem_resp_bits_size_0 = io_mem_resp_bits_size; // @[ZstdCompressor.scala:95:7]
wire io_mem_resp_bits_signed_0 = io_mem_resp_bits_signed; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_mem_resp_bits_dprv_0 = io_mem_resp_bits_dprv; // @[ZstdCompressor.scala:95:7]
wire io_mem_resp_bits_dv_0 = io_mem_resp_bits_dv; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_mem_resp_bits_data_0 = io_mem_resp_bits_data; // @[ZstdCompressor.scala:95:7]
wire [7:0] io_mem_resp_bits_mask_0 = io_mem_resp_bits_mask; // @[ZstdCompressor.scala:95:7]
wire io_mem_resp_bits_replay_0 = io_mem_resp_bits_replay; // @[ZstdCompressor.scala:95:7]
wire io_mem_resp_bits_has_data_0 = io_mem_resp_bits_has_data; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_mem_resp_bits_data_word_bypass_0 = io_mem_resp_bits_data_word_bypass; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_mem_resp_bits_data_raw_0 = io_mem_resp_bits_data_raw; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_mem_resp_bits_store_data_0 = io_mem_resp_bits_store_data; // @[ZstdCompressor.scala:95:7]
wire io_exception_0 = io_exception; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_req_ready_0 = io_ptw_0_req_ready; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_resp_valid_0 = io_ptw_0_resp_valid; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_resp_bits_ae_ptw_0 = io_ptw_0_resp_bits_ae_ptw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_resp_bits_ae_final_0 = io_ptw_0_resp_bits_ae_final; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_resp_bits_pf_0 = io_ptw_0_resp_bits_pf; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_resp_bits_gf_0 = io_ptw_0_resp_bits_gf; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_resp_bits_hr_0 = io_ptw_0_resp_bits_hr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_resp_bits_hw_0 = io_ptw_0_resp_bits_hw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_resp_bits_hx_0 = io_ptw_0_resp_bits_hx; // @[ZstdCompressor.scala:95:7]
wire [9:0] io_ptw_0_resp_bits_pte_reserved_for_future_0 = io_ptw_0_resp_bits_pte_reserved_for_future; // @[ZstdCompressor.scala:95:7]
wire [43:0] io_ptw_0_resp_bits_pte_ppn_0 = io_ptw_0_resp_bits_pte_ppn; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_0_resp_bits_pte_reserved_for_software_0 = io_ptw_0_resp_bits_pte_reserved_for_software; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_resp_bits_pte_d_0 = io_ptw_0_resp_bits_pte_d; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_resp_bits_pte_a_0 = io_ptw_0_resp_bits_pte_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_resp_bits_pte_g_0 = io_ptw_0_resp_bits_pte_g; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_resp_bits_pte_u_0 = io_ptw_0_resp_bits_pte_u; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_resp_bits_pte_x_0 = io_ptw_0_resp_bits_pte_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_resp_bits_pte_w_0 = io_ptw_0_resp_bits_pte_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_resp_bits_pte_r_0 = io_ptw_0_resp_bits_pte_r; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_resp_bits_pte_v_0 = io_ptw_0_resp_bits_pte_v; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_0_resp_bits_level_0 = io_ptw_0_resp_bits_level; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_resp_bits_homogeneous_0 = io_ptw_0_resp_bits_homogeneous; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_resp_bits_gpa_valid_0 = io_ptw_0_resp_bits_gpa_valid; // @[ZstdCompressor.scala:95:7]
wire [38:0] io_ptw_0_resp_bits_gpa_bits_0 = io_ptw_0_resp_bits_gpa_bits; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_resp_bits_gpa_is_pte_0 = io_ptw_0_resp_bits_gpa_is_pte; // @[ZstdCompressor.scala:95:7]
wire [3:0] io_ptw_0_ptbr_mode_0 = io_ptw_0_ptbr_mode; // @[ZstdCompressor.scala:95:7]
wire [43:0] io_ptw_0_ptbr_ppn_0 = io_ptw_0_ptbr_ppn; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_status_debug_0 = io_ptw_0_status_debug; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_status_cease_0 = io_ptw_0_status_cease; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_status_wfi_0 = io_ptw_0_status_wfi; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_0_status_isa_0 = io_ptw_0_status_isa; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_0_status_dprv_0 = io_ptw_0_status_dprv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_status_dv_0 = io_ptw_0_status_dv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_0_status_prv_0 = io_ptw_0_status_prv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_status_v_0 = io_ptw_0_status_v; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_status_mpv_0 = io_ptw_0_status_mpv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_status_gva_0 = io_ptw_0_status_gva; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_status_tsr_0 = io_ptw_0_status_tsr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_status_tw_0 = io_ptw_0_status_tw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_status_tvm_0 = io_ptw_0_status_tvm; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_status_mxr_0 = io_ptw_0_status_mxr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_status_sum_0 = io_ptw_0_status_sum; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_status_mprv_0 = io_ptw_0_status_mprv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_0_status_fs_0 = io_ptw_0_status_fs; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_0_status_mpp_0 = io_ptw_0_status_mpp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_status_spp_0 = io_ptw_0_status_spp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_status_mpie_0 = io_ptw_0_status_mpie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_status_spie_0 = io_ptw_0_status_spie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_status_mie_0 = io_ptw_0_status_mie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_status_sie_0 = io_ptw_0_status_sie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_hstatus_spvp_0 = io_ptw_0_hstatus_spvp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_hstatus_spv_0 = io_ptw_0_hstatus_spv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_hstatus_gva_0 = io_ptw_0_hstatus_gva; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_gstatus_debug_0 = io_ptw_0_gstatus_debug; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_gstatus_cease_0 = io_ptw_0_gstatus_cease; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_gstatus_wfi_0 = io_ptw_0_gstatus_wfi; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_0_gstatus_isa_0 = io_ptw_0_gstatus_isa; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_0_gstatus_dprv_0 = io_ptw_0_gstatus_dprv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_gstatus_dv_0 = io_ptw_0_gstatus_dv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_0_gstatus_prv_0 = io_ptw_0_gstatus_prv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_gstatus_v_0 = io_ptw_0_gstatus_v; // @[ZstdCompressor.scala:95:7]
wire [22:0] io_ptw_0_gstatus_zero2_0 = io_ptw_0_gstatus_zero2; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_gstatus_mpv_0 = io_ptw_0_gstatus_mpv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_gstatus_gva_0 = io_ptw_0_gstatus_gva; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_gstatus_mbe_0 = io_ptw_0_gstatus_mbe; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_gstatus_sbe_0 = io_ptw_0_gstatus_sbe; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_0_gstatus_sxl_0 = io_ptw_0_gstatus_sxl; // @[ZstdCompressor.scala:95:7]
wire [7:0] io_ptw_0_gstatus_zero1_0 = io_ptw_0_gstatus_zero1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_gstatus_tsr_0 = io_ptw_0_gstatus_tsr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_gstatus_tw_0 = io_ptw_0_gstatus_tw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_gstatus_tvm_0 = io_ptw_0_gstatus_tvm; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_gstatus_mxr_0 = io_ptw_0_gstatus_mxr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_gstatus_sum_0 = io_ptw_0_gstatus_sum; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_gstatus_mprv_0 = io_ptw_0_gstatus_mprv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_0_gstatus_fs_0 = io_ptw_0_gstatus_fs; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_0_gstatus_mpp_0 = io_ptw_0_gstatus_mpp; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_0_gstatus_vs_0 = io_ptw_0_gstatus_vs; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_gstatus_spp_0 = io_ptw_0_gstatus_spp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_gstatus_mpie_0 = io_ptw_0_gstatus_mpie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_gstatus_ube_0 = io_ptw_0_gstatus_ube; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_gstatus_spie_0 = io_ptw_0_gstatus_spie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_gstatus_upie_0 = io_ptw_0_gstatus_upie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_gstatus_mie_0 = io_ptw_0_gstatus_mie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_gstatus_hie_0 = io_ptw_0_gstatus_hie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_gstatus_sie_0 = io_ptw_0_gstatus_sie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_gstatus_uie_0 = io_ptw_0_gstatus_uie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_pmp_0_cfg_l_0 = io_ptw_0_pmp_0_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_0_pmp_0_cfg_a_0 = io_ptw_0_pmp_0_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_pmp_0_cfg_x_0 = io_ptw_0_pmp_0_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_pmp_0_cfg_w_0 = io_ptw_0_pmp_0_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_pmp_0_cfg_r_0 = io_ptw_0_pmp_0_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_0_pmp_0_addr_0 = io_ptw_0_pmp_0_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_0_pmp_0_mask_0 = io_ptw_0_pmp_0_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_pmp_1_cfg_l_0 = io_ptw_0_pmp_1_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_0_pmp_1_cfg_a_0 = io_ptw_0_pmp_1_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_pmp_1_cfg_x_0 = io_ptw_0_pmp_1_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_pmp_1_cfg_w_0 = io_ptw_0_pmp_1_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_pmp_1_cfg_r_0 = io_ptw_0_pmp_1_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_0_pmp_1_addr_0 = io_ptw_0_pmp_1_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_0_pmp_1_mask_0 = io_ptw_0_pmp_1_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_pmp_2_cfg_l_0 = io_ptw_0_pmp_2_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_0_pmp_2_cfg_a_0 = io_ptw_0_pmp_2_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_pmp_2_cfg_x_0 = io_ptw_0_pmp_2_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_pmp_2_cfg_w_0 = io_ptw_0_pmp_2_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_pmp_2_cfg_r_0 = io_ptw_0_pmp_2_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_0_pmp_2_addr_0 = io_ptw_0_pmp_2_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_0_pmp_2_mask_0 = io_ptw_0_pmp_2_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_pmp_3_cfg_l_0 = io_ptw_0_pmp_3_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_0_pmp_3_cfg_a_0 = io_ptw_0_pmp_3_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_pmp_3_cfg_x_0 = io_ptw_0_pmp_3_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_pmp_3_cfg_w_0 = io_ptw_0_pmp_3_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_pmp_3_cfg_r_0 = io_ptw_0_pmp_3_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_0_pmp_3_addr_0 = io_ptw_0_pmp_3_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_0_pmp_3_mask_0 = io_ptw_0_pmp_3_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_pmp_4_cfg_l_0 = io_ptw_0_pmp_4_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_0_pmp_4_cfg_a_0 = io_ptw_0_pmp_4_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_pmp_4_cfg_x_0 = io_ptw_0_pmp_4_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_pmp_4_cfg_w_0 = io_ptw_0_pmp_4_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_pmp_4_cfg_r_0 = io_ptw_0_pmp_4_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_0_pmp_4_addr_0 = io_ptw_0_pmp_4_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_0_pmp_4_mask_0 = io_ptw_0_pmp_4_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_pmp_5_cfg_l_0 = io_ptw_0_pmp_5_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_0_pmp_5_cfg_a_0 = io_ptw_0_pmp_5_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_pmp_5_cfg_x_0 = io_ptw_0_pmp_5_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_pmp_5_cfg_w_0 = io_ptw_0_pmp_5_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_pmp_5_cfg_r_0 = io_ptw_0_pmp_5_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_0_pmp_5_addr_0 = io_ptw_0_pmp_5_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_0_pmp_5_mask_0 = io_ptw_0_pmp_5_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_pmp_6_cfg_l_0 = io_ptw_0_pmp_6_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_0_pmp_6_cfg_a_0 = io_ptw_0_pmp_6_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_pmp_6_cfg_x_0 = io_ptw_0_pmp_6_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_pmp_6_cfg_w_0 = io_ptw_0_pmp_6_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_pmp_6_cfg_r_0 = io_ptw_0_pmp_6_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_0_pmp_6_addr_0 = io_ptw_0_pmp_6_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_0_pmp_6_mask_0 = io_ptw_0_pmp_6_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_pmp_7_cfg_l_0 = io_ptw_0_pmp_7_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_0_pmp_7_cfg_a_0 = io_ptw_0_pmp_7_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_pmp_7_cfg_x_0 = io_ptw_0_pmp_7_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_pmp_7_cfg_w_0 = io_ptw_0_pmp_7_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_pmp_7_cfg_r_0 = io_ptw_0_pmp_7_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_0_pmp_7_addr_0 = io_ptw_0_pmp_7_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_0_pmp_7_mask_0 = io_ptw_0_pmp_7_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_customCSRs_csrs_0_ren_0 = io_ptw_0_customCSRs_csrs_0_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_customCSRs_csrs_0_wen_0 = io_ptw_0_customCSRs_csrs_0_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_0_customCSRs_csrs_0_wdata_0 = io_ptw_0_customCSRs_csrs_0_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_0_customCSRs_csrs_0_value_0 = io_ptw_0_customCSRs_csrs_0_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_customCSRs_csrs_1_ren_0 = io_ptw_0_customCSRs_csrs_1_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_customCSRs_csrs_1_wen_0 = io_ptw_0_customCSRs_csrs_1_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_0_customCSRs_csrs_1_wdata_0 = io_ptw_0_customCSRs_csrs_1_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_0_customCSRs_csrs_1_value_0 = io_ptw_0_customCSRs_csrs_1_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_customCSRs_csrs_2_ren_0 = io_ptw_0_customCSRs_csrs_2_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_customCSRs_csrs_2_wen_0 = io_ptw_0_customCSRs_csrs_2_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_0_customCSRs_csrs_2_wdata_0 = io_ptw_0_customCSRs_csrs_2_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_0_customCSRs_csrs_2_value_0 = io_ptw_0_customCSRs_csrs_2_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_customCSRs_csrs_3_ren_0 = io_ptw_0_customCSRs_csrs_3_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_customCSRs_csrs_3_wen_0 = io_ptw_0_customCSRs_csrs_3_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_0_customCSRs_csrs_3_wdata_0 = io_ptw_0_customCSRs_csrs_3_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_0_customCSRs_csrs_3_value_0 = io_ptw_0_customCSRs_csrs_3_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_req_ready_0 = io_ptw_1_req_ready; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_resp_valid_0 = io_ptw_1_resp_valid; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_resp_bits_ae_ptw_0 = io_ptw_1_resp_bits_ae_ptw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_resp_bits_ae_final_0 = io_ptw_1_resp_bits_ae_final; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_resp_bits_pf_0 = io_ptw_1_resp_bits_pf; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_resp_bits_gf_0 = io_ptw_1_resp_bits_gf; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_resp_bits_hr_0 = io_ptw_1_resp_bits_hr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_resp_bits_hw_0 = io_ptw_1_resp_bits_hw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_resp_bits_hx_0 = io_ptw_1_resp_bits_hx; // @[ZstdCompressor.scala:95:7]
wire [9:0] io_ptw_1_resp_bits_pte_reserved_for_future_0 = io_ptw_1_resp_bits_pte_reserved_for_future; // @[ZstdCompressor.scala:95:7]
wire [43:0] io_ptw_1_resp_bits_pte_ppn_0 = io_ptw_1_resp_bits_pte_ppn; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_1_resp_bits_pte_reserved_for_software_0 = io_ptw_1_resp_bits_pte_reserved_for_software; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_resp_bits_pte_d_0 = io_ptw_1_resp_bits_pte_d; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_resp_bits_pte_a_0 = io_ptw_1_resp_bits_pte_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_resp_bits_pte_g_0 = io_ptw_1_resp_bits_pte_g; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_resp_bits_pte_u_0 = io_ptw_1_resp_bits_pte_u; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_resp_bits_pte_x_0 = io_ptw_1_resp_bits_pte_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_resp_bits_pte_w_0 = io_ptw_1_resp_bits_pte_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_resp_bits_pte_r_0 = io_ptw_1_resp_bits_pte_r; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_resp_bits_pte_v_0 = io_ptw_1_resp_bits_pte_v; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_1_resp_bits_level_0 = io_ptw_1_resp_bits_level; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_resp_bits_homogeneous_0 = io_ptw_1_resp_bits_homogeneous; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_resp_bits_gpa_valid_0 = io_ptw_1_resp_bits_gpa_valid; // @[ZstdCompressor.scala:95:7]
wire [38:0] io_ptw_1_resp_bits_gpa_bits_0 = io_ptw_1_resp_bits_gpa_bits; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_resp_bits_gpa_is_pte_0 = io_ptw_1_resp_bits_gpa_is_pte; // @[ZstdCompressor.scala:95:7]
wire [3:0] io_ptw_1_ptbr_mode_0 = io_ptw_1_ptbr_mode; // @[ZstdCompressor.scala:95:7]
wire [43:0] io_ptw_1_ptbr_ppn_0 = io_ptw_1_ptbr_ppn; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_status_debug_0 = io_ptw_1_status_debug; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_status_cease_0 = io_ptw_1_status_cease; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_status_wfi_0 = io_ptw_1_status_wfi; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_1_status_isa_0 = io_ptw_1_status_isa; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_1_status_dprv_0 = io_ptw_1_status_dprv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_status_dv_0 = io_ptw_1_status_dv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_1_status_prv_0 = io_ptw_1_status_prv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_status_v_0 = io_ptw_1_status_v; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_status_mpv_0 = io_ptw_1_status_mpv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_status_gva_0 = io_ptw_1_status_gva; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_status_tsr_0 = io_ptw_1_status_tsr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_status_tw_0 = io_ptw_1_status_tw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_status_tvm_0 = io_ptw_1_status_tvm; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_status_mxr_0 = io_ptw_1_status_mxr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_status_sum_0 = io_ptw_1_status_sum; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_status_mprv_0 = io_ptw_1_status_mprv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_1_status_fs_0 = io_ptw_1_status_fs; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_1_status_mpp_0 = io_ptw_1_status_mpp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_status_spp_0 = io_ptw_1_status_spp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_status_mpie_0 = io_ptw_1_status_mpie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_status_spie_0 = io_ptw_1_status_spie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_status_mie_0 = io_ptw_1_status_mie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_status_sie_0 = io_ptw_1_status_sie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_hstatus_spvp_0 = io_ptw_1_hstatus_spvp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_hstatus_spv_0 = io_ptw_1_hstatus_spv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_hstatus_gva_0 = io_ptw_1_hstatus_gva; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_gstatus_debug_0 = io_ptw_1_gstatus_debug; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_gstatus_cease_0 = io_ptw_1_gstatus_cease; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_gstatus_wfi_0 = io_ptw_1_gstatus_wfi; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_1_gstatus_isa_0 = io_ptw_1_gstatus_isa; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_1_gstatus_dprv_0 = io_ptw_1_gstatus_dprv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_gstatus_dv_0 = io_ptw_1_gstatus_dv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_1_gstatus_prv_0 = io_ptw_1_gstatus_prv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_gstatus_v_0 = io_ptw_1_gstatus_v; // @[ZstdCompressor.scala:95:7]
wire [22:0] io_ptw_1_gstatus_zero2_0 = io_ptw_1_gstatus_zero2; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_gstatus_mpv_0 = io_ptw_1_gstatus_mpv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_gstatus_gva_0 = io_ptw_1_gstatus_gva; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_gstatus_mbe_0 = io_ptw_1_gstatus_mbe; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_gstatus_sbe_0 = io_ptw_1_gstatus_sbe; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_1_gstatus_sxl_0 = io_ptw_1_gstatus_sxl; // @[ZstdCompressor.scala:95:7]
wire [7:0] io_ptw_1_gstatus_zero1_0 = io_ptw_1_gstatus_zero1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_gstatus_tsr_0 = io_ptw_1_gstatus_tsr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_gstatus_tw_0 = io_ptw_1_gstatus_tw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_gstatus_tvm_0 = io_ptw_1_gstatus_tvm; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_gstatus_mxr_0 = io_ptw_1_gstatus_mxr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_gstatus_sum_0 = io_ptw_1_gstatus_sum; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_gstatus_mprv_0 = io_ptw_1_gstatus_mprv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_1_gstatus_fs_0 = io_ptw_1_gstatus_fs; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_1_gstatus_mpp_0 = io_ptw_1_gstatus_mpp; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_1_gstatus_vs_0 = io_ptw_1_gstatus_vs; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_gstatus_spp_0 = io_ptw_1_gstatus_spp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_gstatus_mpie_0 = io_ptw_1_gstatus_mpie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_gstatus_ube_0 = io_ptw_1_gstatus_ube; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_gstatus_spie_0 = io_ptw_1_gstatus_spie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_gstatus_upie_0 = io_ptw_1_gstatus_upie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_gstatus_mie_0 = io_ptw_1_gstatus_mie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_gstatus_hie_0 = io_ptw_1_gstatus_hie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_gstatus_sie_0 = io_ptw_1_gstatus_sie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_gstatus_uie_0 = io_ptw_1_gstatus_uie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_pmp_0_cfg_l_0 = io_ptw_1_pmp_0_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_1_pmp_0_cfg_a_0 = io_ptw_1_pmp_0_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_pmp_0_cfg_x_0 = io_ptw_1_pmp_0_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_pmp_0_cfg_w_0 = io_ptw_1_pmp_0_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_pmp_0_cfg_r_0 = io_ptw_1_pmp_0_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_1_pmp_0_addr_0 = io_ptw_1_pmp_0_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_1_pmp_0_mask_0 = io_ptw_1_pmp_0_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_pmp_1_cfg_l_0 = io_ptw_1_pmp_1_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_1_pmp_1_cfg_a_0 = io_ptw_1_pmp_1_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_pmp_1_cfg_x_0 = io_ptw_1_pmp_1_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_pmp_1_cfg_w_0 = io_ptw_1_pmp_1_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_pmp_1_cfg_r_0 = io_ptw_1_pmp_1_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_1_pmp_1_addr_0 = io_ptw_1_pmp_1_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_1_pmp_1_mask_0 = io_ptw_1_pmp_1_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_pmp_2_cfg_l_0 = io_ptw_1_pmp_2_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_1_pmp_2_cfg_a_0 = io_ptw_1_pmp_2_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_pmp_2_cfg_x_0 = io_ptw_1_pmp_2_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_pmp_2_cfg_w_0 = io_ptw_1_pmp_2_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_pmp_2_cfg_r_0 = io_ptw_1_pmp_2_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_1_pmp_2_addr_0 = io_ptw_1_pmp_2_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_1_pmp_2_mask_0 = io_ptw_1_pmp_2_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_pmp_3_cfg_l_0 = io_ptw_1_pmp_3_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_1_pmp_3_cfg_a_0 = io_ptw_1_pmp_3_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_pmp_3_cfg_x_0 = io_ptw_1_pmp_3_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_pmp_3_cfg_w_0 = io_ptw_1_pmp_3_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_pmp_3_cfg_r_0 = io_ptw_1_pmp_3_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_1_pmp_3_addr_0 = io_ptw_1_pmp_3_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_1_pmp_3_mask_0 = io_ptw_1_pmp_3_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_pmp_4_cfg_l_0 = io_ptw_1_pmp_4_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_1_pmp_4_cfg_a_0 = io_ptw_1_pmp_4_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_pmp_4_cfg_x_0 = io_ptw_1_pmp_4_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_pmp_4_cfg_w_0 = io_ptw_1_pmp_4_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_pmp_4_cfg_r_0 = io_ptw_1_pmp_4_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_1_pmp_4_addr_0 = io_ptw_1_pmp_4_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_1_pmp_4_mask_0 = io_ptw_1_pmp_4_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_pmp_5_cfg_l_0 = io_ptw_1_pmp_5_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_1_pmp_5_cfg_a_0 = io_ptw_1_pmp_5_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_pmp_5_cfg_x_0 = io_ptw_1_pmp_5_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_pmp_5_cfg_w_0 = io_ptw_1_pmp_5_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_pmp_5_cfg_r_0 = io_ptw_1_pmp_5_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_1_pmp_5_addr_0 = io_ptw_1_pmp_5_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_1_pmp_5_mask_0 = io_ptw_1_pmp_5_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_pmp_6_cfg_l_0 = io_ptw_1_pmp_6_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_1_pmp_6_cfg_a_0 = io_ptw_1_pmp_6_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_pmp_6_cfg_x_0 = io_ptw_1_pmp_6_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_pmp_6_cfg_w_0 = io_ptw_1_pmp_6_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_pmp_6_cfg_r_0 = io_ptw_1_pmp_6_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_1_pmp_6_addr_0 = io_ptw_1_pmp_6_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_1_pmp_6_mask_0 = io_ptw_1_pmp_6_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_pmp_7_cfg_l_0 = io_ptw_1_pmp_7_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_1_pmp_7_cfg_a_0 = io_ptw_1_pmp_7_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_pmp_7_cfg_x_0 = io_ptw_1_pmp_7_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_pmp_7_cfg_w_0 = io_ptw_1_pmp_7_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_pmp_7_cfg_r_0 = io_ptw_1_pmp_7_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_1_pmp_7_addr_0 = io_ptw_1_pmp_7_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_1_pmp_7_mask_0 = io_ptw_1_pmp_7_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_customCSRs_csrs_0_ren_0 = io_ptw_1_customCSRs_csrs_0_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_customCSRs_csrs_0_wen_0 = io_ptw_1_customCSRs_csrs_0_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_1_customCSRs_csrs_0_wdata_0 = io_ptw_1_customCSRs_csrs_0_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_1_customCSRs_csrs_0_value_0 = io_ptw_1_customCSRs_csrs_0_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_customCSRs_csrs_1_ren_0 = io_ptw_1_customCSRs_csrs_1_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_customCSRs_csrs_1_wen_0 = io_ptw_1_customCSRs_csrs_1_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_1_customCSRs_csrs_1_wdata_0 = io_ptw_1_customCSRs_csrs_1_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_1_customCSRs_csrs_1_value_0 = io_ptw_1_customCSRs_csrs_1_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_customCSRs_csrs_2_ren_0 = io_ptw_1_customCSRs_csrs_2_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_customCSRs_csrs_2_wen_0 = io_ptw_1_customCSRs_csrs_2_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_1_customCSRs_csrs_2_wdata_0 = io_ptw_1_customCSRs_csrs_2_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_1_customCSRs_csrs_2_value_0 = io_ptw_1_customCSRs_csrs_2_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_customCSRs_csrs_3_ren_0 = io_ptw_1_customCSRs_csrs_3_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_customCSRs_csrs_3_wen_0 = io_ptw_1_customCSRs_csrs_3_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_1_customCSRs_csrs_3_wdata_0 = io_ptw_1_customCSRs_csrs_3_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_1_customCSRs_csrs_3_value_0 = io_ptw_1_customCSRs_csrs_3_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_req_ready_0 = io_ptw_2_req_ready; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_resp_valid_0 = io_ptw_2_resp_valid; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_resp_bits_ae_ptw_0 = io_ptw_2_resp_bits_ae_ptw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_resp_bits_ae_final_0 = io_ptw_2_resp_bits_ae_final; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_resp_bits_pf_0 = io_ptw_2_resp_bits_pf; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_resp_bits_gf_0 = io_ptw_2_resp_bits_gf; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_resp_bits_hr_0 = io_ptw_2_resp_bits_hr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_resp_bits_hw_0 = io_ptw_2_resp_bits_hw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_resp_bits_hx_0 = io_ptw_2_resp_bits_hx; // @[ZstdCompressor.scala:95:7]
wire [9:0] io_ptw_2_resp_bits_pte_reserved_for_future_0 = io_ptw_2_resp_bits_pte_reserved_for_future; // @[ZstdCompressor.scala:95:7]
wire [43:0] io_ptw_2_resp_bits_pte_ppn_0 = io_ptw_2_resp_bits_pte_ppn; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_2_resp_bits_pte_reserved_for_software_0 = io_ptw_2_resp_bits_pte_reserved_for_software; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_resp_bits_pte_d_0 = io_ptw_2_resp_bits_pte_d; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_resp_bits_pte_a_0 = io_ptw_2_resp_bits_pte_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_resp_bits_pte_g_0 = io_ptw_2_resp_bits_pte_g; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_resp_bits_pte_u_0 = io_ptw_2_resp_bits_pte_u; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_resp_bits_pte_x_0 = io_ptw_2_resp_bits_pte_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_resp_bits_pte_w_0 = io_ptw_2_resp_bits_pte_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_resp_bits_pte_r_0 = io_ptw_2_resp_bits_pte_r; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_resp_bits_pte_v_0 = io_ptw_2_resp_bits_pte_v; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_2_resp_bits_level_0 = io_ptw_2_resp_bits_level; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_resp_bits_homogeneous_0 = io_ptw_2_resp_bits_homogeneous; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_resp_bits_gpa_valid_0 = io_ptw_2_resp_bits_gpa_valid; // @[ZstdCompressor.scala:95:7]
wire [38:0] io_ptw_2_resp_bits_gpa_bits_0 = io_ptw_2_resp_bits_gpa_bits; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_resp_bits_gpa_is_pte_0 = io_ptw_2_resp_bits_gpa_is_pte; // @[ZstdCompressor.scala:95:7]
wire [3:0] io_ptw_2_ptbr_mode_0 = io_ptw_2_ptbr_mode; // @[ZstdCompressor.scala:95:7]
wire [43:0] io_ptw_2_ptbr_ppn_0 = io_ptw_2_ptbr_ppn; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_status_debug_0 = io_ptw_2_status_debug; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_status_cease_0 = io_ptw_2_status_cease; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_status_wfi_0 = io_ptw_2_status_wfi; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_2_status_isa_0 = io_ptw_2_status_isa; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_2_status_dprv_0 = io_ptw_2_status_dprv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_status_dv_0 = io_ptw_2_status_dv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_2_status_prv_0 = io_ptw_2_status_prv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_status_v_0 = io_ptw_2_status_v; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_status_mpv_0 = io_ptw_2_status_mpv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_status_gva_0 = io_ptw_2_status_gva; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_status_tsr_0 = io_ptw_2_status_tsr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_status_tw_0 = io_ptw_2_status_tw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_status_tvm_0 = io_ptw_2_status_tvm; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_status_mxr_0 = io_ptw_2_status_mxr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_status_sum_0 = io_ptw_2_status_sum; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_status_mprv_0 = io_ptw_2_status_mprv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_2_status_fs_0 = io_ptw_2_status_fs; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_2_status_mpp_0 = io_ptw_2_status_mpp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_status_spp_0 = io_ptw_2_status_spp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_status_mpie_0 = io_ptw_2_status_mpie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_status_spie_0 = io_ptw_2_status_spie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_status_mie_0 = io_ptw_2_status_mie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_status_sie_0 = io_ptw_2_status_sie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_hstatus_spvp_0 = io_ptw_2_hstatus_spvp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_hstatus_spv_0 = io_ptw_2_hstatus_spv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_hstatus_gva_0 = io_ptw_2_hstatus_gva; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_gstatus_debug_0 = io_ptw_2_gstatus_debug; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_gstatus_cease_0 = io_ptw_2_gstatus_cease; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_gstatus_wfi_0 = io_ptw_2_gstatus_wfi; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_2_gstatus_isa_0 = io_ptw_2_gstatus_isa; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_2_gstatus_dprv_0 = io_ptw_2_gstatus_dprv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_gstatus_dv_0 = io_ptw_2_gstatus_dv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_2_gstatus_prv_0 = io_ptw_2_gstatus_prv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_gstatus_v_0 = io_ptw_2_gstatus_v; // @[ZstdCompressor.scala:95:7]
wire [22:0] io_ptw_2_gstatus_zero2_0 = io_ptw_2_gstatus_zero2; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_gstatus_mpv_0 = io_ptw_2_gstatus_mpv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_gstatus_gva_0 = io_ptw_2_gstatus_gva; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_gstatus_mbe_0 = io_ptw_2_gstatus_mbe; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_gstatus_sbe_0 = io_ptw_2_gstatus_sbe; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_2_gstatus_sxl_0 = io_ptw_2_gstatus_sxl; // @[ZstdCompressor.scala:95:7]
wire [7:0] io_ptw_2_gstatus_zero1_0 = io_ptw_2_gstatus_zero1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_gstatus_tsr_0 = io_ptw_2_gstatus_tsr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_gstatus_tw_0 = io_ptw_2_gstatus_tw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_gstatus_tvm_0 = io_ptw_2_gstatus_tvm; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_gstatus_mxr_0 = io_ptw_2_gstatus_mxr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_gstatus_sum_0 = io_ptw_2_gstatus_sum; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_gstatus_mprv_0 = io_ptw_2_gstatus_mprv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_2_gstatus_fs_0 = io_ptw_2_gstatus_fs; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_2_gstatus_mpp_0 = io_ptw_2_gstatus_mpp; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_2_gstatus_vs_0 = io_ptw_2_gstatus_vs; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_gstatus_spp_0 = io_ptw_2_gstatus_spp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_gstatus_mpie_0 = io_ptw_2_gstatus_mpie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_gstatus_ube_0 = io_ptw_2_gstatus_ube; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_gstatus_spie_0 = io_ptw_2_gstatus_spie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_gstatus_upie_0 = io_ptw_2_gstatus_upie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_gstatus_mie_0 = io_ptw_2_gstatus_mie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_gstatus_hie_0 = io_ptw_2_gstatus_hie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_gstatus_sie_0 = io_ptw_2_gstatus_sie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_gstatus_uie_0 = io_ptw_2_gstatus_uie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_pmp_0_cfg_l_0 = io_ptw_2_pmp_0_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_2_pmp_0_cfg_a_0 = io_ptw_2_pmp_0_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_pmp_0_cfg_x_0 = io_ptw_2_pmp_0_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_pmp_0_cfg_w_0 = io_ptw_2_pmp_0_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_pmp_0_cfg_r_0 = io_ptw_2_pmp_0_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_2_pmp_0_addr_0 = io_ptw_2_pmp_0_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_2_pmp_0_mask_0 = io_ptw_2_pmp_0_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_pmp_1_cfg_l_0 = io_ptw_2_pmp_1_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_2_pmp_1_cfg_a_0 = io_ptw_2_pmp_1_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_pmp_1_cfg_x_0 = io_ptw_2_pmp_1_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_pmp_1_cfg_w_0 = io_ptw_2_pmp_1_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_pmp_1_cfg_r_0 = io_ptw_2_pmp_1_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_2_pmp_1_addr_0 = io_ptw_2_pmp_1_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_2_pmp_1_mask_0 = io_ptw_2_pmp_1_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_pmp_2_cfg_l_0 = io_ptw_2_pmp_2_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_2_pmp_2_cfg_a_0 = io_ptw_2_pmp_2_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_pmp_2_cfg_x_0 = io_ptw_2_pmp_2_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_pmp_2_cfg_w_0 = io_ptw_2_pmp_2_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_pmp_2_cfg_r_0 = io_ptw_2_pmp_2_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_2_pmp_2_addr_0 = io_ptw_2_pmp_2_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_2_pmp_2_mask_0 = io_ptw_2_pmp_2_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_pmp_3_cfg_l_0 = io_ptw_2_pmp_3_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_2_pmp_3_cfg_a_0 = io_ptw_2_pmp_3_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_pmp_3_cfg_x_0 = io_ptw_2_pmp_3_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_pmp_3_cfg_w_0 = io_ptw_2_pmp_3_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_pmp_3_cfg_r_0 = io_ptw_2_pmp_3_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_2_pmp_3_addr_0 = io_ptw_2_pmp_3_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_2_pmp_3_mask_0 = io_ptw_2_pmp_3_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_pmp_4_cfg_l_0 = io_ptw_2_pmp_4_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_2_pmp_4_cfg_a_0 = io_ptw_2_pmp_4_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_pmp_4_cfg_x_0 = io_ptw_2_pmp_4_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_pmp_4_cfg_w_0 = io_ptw_2_pmp_4_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_pmp_4_cfg_r_0 = io_ptw_2_pmp_4_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_2_pmp_4_addr_0 = io_ptw_2_pmp_4_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_2_pmp_4_mask_0 = io_ptw_2_pmp_4_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_pmp_5_cfg_l_0 = io_ptw_2_pmp_5_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_2_pmp_5_cfg_a_0 = io_ptw_2_pmp_5_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_pmp_5_cfg_x_0 = io_ptw_2_pmp_5_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_pmp_5_cfg_w_0 = io_ptw_2_pmp_5_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_pmp_5_cfg_r_0 = io_ptw_2_pmp_5_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_2_pmp_5_addr_0 = io_ptw_2_pmp_5_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_2_pmp_5_mask_0 = io_ptw_2_pmp_5_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_pmp_6_cfg_l_0 = io_ptw_2_pmp_6_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_2_pmp_6_cfg_a_0 = io_ptw_2_pmp_6_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_pmp_6_cfg_x_0 = io_ptw_2_pmp_6_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_pmp_6_cfg_w_0 = io_ptw_2_pmp_6_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_pmp_6_cfg_r_0 = io_ptw_2_pmp_6_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_2_pmp_6_addr_0 = io_ptw_2_pmp_6_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_2_pmp_6_mask_0 = io_ptw_2_pmp_6_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_pmp_7_cfg_l_0 = io_ptw_2_pmp_7_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_2_pmp_7_cfg_a_0 = io_ptw_2_pmp_7_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_pmp_7_cfg_x_0 = io_ptw_2_pmp_7_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_pmp_7_cfg_w_0 = io_ptw_2_pmp_7_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_pmp_7_cfg_r_0 = io_ptw_2_pmp_7_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_2_pmp_7_addr_0 = io_ptw_2_pmp_7_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_2_pmp_7_mask_0 = io_ptw_2_pmp_7_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_customCSRs_csrs_0_ren_0 = io_ptw_2_customCSRs_csrs_0_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_customCSRs_csrs_0_wen_0 = io_ptw_2_customCSRs_csrs_0_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_2_customCSRs_csrs_0_wdata_0 = io_ptw_2_customCSRs_csrs_0_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_2_customCSRs_csrs_0_value_0 = io_ptw_2_customCSRs_csrs_0_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_customCSRs_csrs_1_ren_0 = io_ptw_2_customCSRs_csrs_1_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_customCSRs_csrs_1_wen_0 = io_ptw_2_customCSRs_csrs_1_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_2_customCSRs_csrs_1_wdata_0 = io_ptw_2_customCSRs_csrs_1_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_2_customCSRs_csrs_1_value_0 = io_ptw_2_customCSRs_csrs_1_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_customCSRs_csrs_2_ren_0 = io_ptw_2_customCSRs_csrs_2_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_customCSRs_csrs_2_wen_0 = io_ptw_2_customCSRs_csrs_2_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_2_customCSRs_csrs_2_wdata_0 = io_ptw_2_customCSRs_csrs_2_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_2_customCSRs_csrs_2_value_0 = io_ptw_2_customCSRs_csrs_2_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_customCSRs_csrs_3_ren_0 = io_ptw_2_customCSRs_csrs_3_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_customCSRs_csrs_3_wen_0 = io_ptw_2_customCSRs_csrs_3_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_2_customCSRs_csrs_3_wdata_0 = io_ptw_2_customCSRs_csrs_3_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_2_customCSRs_csrs_3_value_0 = io_ptw_2_customCSRs_csrs_3_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_req_ready_0 = io_ptw_3_req_ready; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_resp_valid_0 = io_ptw_3_resp_valid; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_resp_bits_ae_ptw_0 = io_ptw_3_resp_bits_ae_ptw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_resp_bits_ae_final_0 = io_ptw_3_resp_bits_ae_final; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_resp_bits_pf_0 = io_ptw_3_resp_bits_pf; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_resp_bits_gf_0 = io_ptw_3_resp_bits_gf; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_resp_bits_hr_0 = io_ptw_3_resp_bits_hr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_resp_bits_hw_0 = io_ptw_3_resp_bits_hw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_resp_bits_hx_0 = io_ptw_3_resp_bits_hx; // @[ZstdCompressor.scala:95:7]
wire [9:0] io_ptw_3_resp_bits_pte_reserved_for_future_0 = io_ptw_3_resp_bits_pte_reserved_for_future; // @[ZstdCompressor.scala:95:7]
wire [43:0] io_ptw_3_resp_bits_pte_ppn_0 = io_ptw_3_resp_bits_pte_ppn; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_3_resp_bits_pte_reserved_for_software_0 = io_ptw_3_resp_bits_pte_reserved_for_software; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_resp_bits_pte_d_0 = io_ptw_3_resp_bits_pte_d; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_resp_bits_pte_a_0 = io_ptw_3_resp_bits_pte_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_resp_bits_pte_g_0 = io_ptw_3_resp_bits_pte_g; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_resp_bits_pte_u_0 = io_ptw_3_resp_bits_pte_u; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_resp_bits_pte_x_0 = io_ptw_3_resp_bits_pte_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_resp_bits_pte_w_0 = io_ptw_3_resp_bits_pte_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_resp_bits_pte_r_0 = io_ptw_3_resp_bits_pte_r; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_resp_bits_pte_v_0 = io_ptw_3_resp_bits_pte_v; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_3_resp_bits_level_0 = io_ptw_3_resp_bits_level; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_resp_bits_homogeneous_0 = io_ptw_3_resp_bits_homogeneous; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_resp_bits_gpa_valid_0 = io_ptw_3_resp_bits_gpa_valid; // @[ZstdCompressor.scala:95:7]
wire [38:0] io_ptw_3_resp_bits_gpa_bits_0 = io_ptw_3_resp_bits_gpa_bits; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_resp_bits_gpa_is_pte_0 = io_ptw_3_resp_bits_gpa_is_pte; // @[ZstdCompressor.scala:95:7]
wire [3:0] io_ptw_3_ptbr_mode_0 = io_ptw_3_ptbr_mode; // @[ZstdCompressor.scala:95:7]
wire [43:0] io_ptw_3_ptbr_ppn_0 = io_ptw_3_ptbr_ppn; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_status_debug_0 = io_ptw_3_status_debug; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_status_cease_0 = io_ptw_3_status_cease; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_status_wfi_0 = io_ptw_3_status_wfi; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_3_status_isa_0 = io_ptw_3_status_isa; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_3_status_dprv_0 = io_ptw_3_status_dprv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_status_dv_0 = io_ptw_3_status_dv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_3_status_prv_0 = io_ptw_3_status_prv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_status_v_0 = io_ptw_3_status_v; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_status_mpv_0 = io_ptw_3_status_mpv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_status_gva_0 = io_ptw_3_status_gva; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_status_tsr_0 = io_ptw_3_status_tsr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_status_tw_0 = io_ptw_3_status_tw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_status_tvm_0 = io_ptw_3_status_tvm; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_status_mxr_0 = io_ptw_3_status_mxr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_status_sum_0 = io_ptw_3_status_sum; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_status_mprv_0 = io_ptw_3_status_mprv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_3_status_fs_0 = io_ptw_3_status_fs; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_3_status_mpp_0 = io_ptw_3_status_mpp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_status_spp_0 = io_ptw_3_status_spp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_status_mpie_0 = io_ptw_3_status_mpie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_status_spie_0 = io_ptw_3_status_spie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_status_mie_0 = io_ptw_3_status_mie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_status_sie_0 = io_ptw_3_status_sie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_hstatus_spvp_0 = io_ptw_3_hstatus_spvp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_hstatus_spv_0 = io_ptw_3_hstatus_spv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_hstatus_gva_0 = io_ptw_3_hstatus_gva; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_gstatus_debug_0 = io_ptw_3_gstatus_debug; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_gstatus_cease_0 = io_ptw_3_gstatus_cease; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_gstatus_wfi_0 = io_ptw_3_gstatus_wfi; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_3_gstatus_isa_0 = io_ptw_3_gstatus_isa; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_3_gstatus_dprv_0 = io_ptw_3_gstatus_dprv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_gstatus_dv_0 = io_ptw_3_gstatus_dv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_3_gstatus_prv_0 = io_ptw_3_gstatus_prv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_gstatus_v_0 = io_ptw_3_gstatus_v; // @[ZstdCompressor.scala:95:7]
wire [22:0] io_ptw_3_gstatus_zero2_0 = io_ptw_3_gstatus_zero2; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_gstatus_mpv_0 = io_ptw_3_gstatus_mpv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_gstatus_gva_0 = io_ptw_3_gstatus_gva; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_gstatus_mbe_0 = io_ptw_3_gstatus_mbe; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_gstatus_sbe_0 = io_ptw_3_gstatus_sbe; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_3_gstatus_sxl_0 = io_ptw_3_gstatus_sxl; // @[ZstdCompressor.scala:95:7]
wire [7:0] io_ptw_3_gstatus_zero1_0 = io_ptw_3_gstatus_zero1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_gstatus_tsr_0 = io_ptw_3_gstatus_tsr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_gstatus_tw_0 = io_ptw_3_gstatus_tw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_gstatus_tvm_0 = io_ptw_3_gstatus_tvm; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_gstatus_mxr_0 = io_ptw_3_gstatus_mxr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_gstatus_sum_0 = io_ptw_3_gstatus_sum; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_gstatus_mprv_0 = io_ptw_3_gstatus_mprv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_3_gstatus_fs_0 = io_ptw_3_gstatus_fs; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_3_gstatus_mpp_0 = io_ptw_3_gstatus_mpp; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_3_gstatus_vs_0 = io_ptw_3_gstatus_vs; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_gstatus_spp_0 = io_ptw_3_gstatus_spp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_gstatus_mpie_0 = io_ptw_3_gstatus_mpie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_gstatus_ube_0 = io_ptw_3_gstatus_ube; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_gstatus_spie_0 = io_ptw_3_gstatus_spie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_gstatus_upie_0 = io_ptw_3_gstatus_upie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_gstatus_mie_0 = io_ptw_3_gstatus_mie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_gstatus_hie_0 = io_ptw_3_gstatus_hie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_gstatus_sie_0 = io_ptw_3_gstatus_sie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_gstatus_uie_0 = io_ptw_3_gstatus_uie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_pmp_0_cfg_l_0 = io_ptw_3_pmp_0_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_3_pmp_0_cfg_a_0 = io_ptw_3_pmp_0_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_pmp_0_cfg_x_0 = io_ptw_3_pmp_0_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_pmp_0_cfg_w_0 = io_ptw_3_pmp_0_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_pmp_0_cfg_r_0 = io_ptw_3_pmp_0_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_3_pmp_0_addr_0 = io_ptw_3_pmp_0_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_3_pmp_0_mask_0 = io_ptw_3_pmp_0_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_pmp_1_cfg_l_0 = io_ptw_3_pmp_1_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_3_pmp_1_cfg_a_0 = io_ptw_3_pmp_1_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_pmp_1_cfg_x_0 = io_ptw_3_pmp_1_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_pmp_1_cfg_w_0 = io_ptw_3_pmp_1_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_pmp_1_cfg_r_0 = io_ptw_3_pmp_1_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_3_pmp_1_addr_0 = io_ptw_3_pmp_1_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_3_pmp_1_mask_0 = io_ptw_3_pmp_1_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_pmp_2_cfg_l_0 = io_ptw_3_pmp_2_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_3_pmp_2_cfg_a_0 = io_ptw_3_pmp_2_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_pmp_2_cfg_x_0 = io_ptw_3_pmp_2_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_pmp_2_cfg_w_0 = io_ptw_3_pmp_2_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_pmp_2_cfg_r_0 = io_ptw_3_pmp_2_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_3_pmp_2_addr_0 = io_ptw_3_pmp_2_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_3_pmp_2_mask_0 = io_ptw_3_pmp_2_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_pmp_3_cfg_l_0 = io_ptw_3_pmp_3_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_3_pmp_3_cfg_a_0 = io_ptw_3_pmp_3_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_pmp_3_cfg_x_0 = io_ptw_3_pmp_3_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_pmp_3_cfg_w_0 = io_ptw_3_pmp_3_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_pmp_3_cfg_r_0 = io_ptw_3_pmp_3_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_3_pmp_3_addr_0 = io_ptw_3_pmp_3_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_3_pmp_3_mask_0 = io_ptw_3_pmp_3_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_pmp_4_cfg_l_0 = io_ptw_3_pmp_4_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_3_pmp_4_cfg_a_0 = io_ptw_3_pmp_4_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_pmp_4_cfg_x_0 = io_ptw_3_pmp_4_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_pmp_4_cfg_w_0 = io_ptw_3_pmp_4_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_pmp_4_cfg_r_0 = io_ptw_3_pmp_4_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_3_pmp_4_addr_0 = io_ptw_3_pmp_4_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_3_pmp_4_mask_0 = io_ptw_3_pmp_4_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_pmp_5_cfg_l_0 = io_ptw_3_pmp_5_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_3_pmp_5_cfg_a_0 = io_ptw_3_pmp_5_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_pmp_5_cfg_x_0 = io_ptw_3_pmp_5_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_pmp_5_cfg_w_0 = io_ptw_3_pmp_5_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_pmp_5_cfg_r_0 = io_ptw_3_pmp_5_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_3_pmp_5_addr_0 = io_ptw_3_pmp_5_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_3_pmp_5_mask_0 = io_ptw_3_pmp_5_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_pmp_6_cfg_l_0 = io_ptw_3_pmp_6_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_3_pmp_6_cfg_a_0 = io_ptw_3_pmp_6_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_pmp_6_cfg_x_0 = io_ptw_3_pmp_6_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_pmp_6_cfg_w_0 = io_ptw_3_pmp_6_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_pmp_6_cfg_r_0 = io_ptw_3_pmp_6_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_3_pmp_6_addr_0 = io_ptw_3_pmp_6_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_3_pmp_6_mask_0 = io_ptw_3_pmp_6_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_pmp_7_cfg_l_0 = io_ptw_3_pmp_7_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_3_pmp_7_cfg_a_0 = io_ptw_3_pmp_7_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_pmp_7_cfg_x_0 = io_ptw_3_pmp_7_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_pmp_7_cfg_w_0 = io_ptw_3_pmp_7_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_pmp_7_cfg_r_0 = io_ptw_3_pmp_7_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_3_pmp_7_addr_0 = io_ptw_3_pmp_7_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_3_pmp_7_mask_0 = io_ptw_3_pmp_7_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_customCSRs_csrs_0_ren_0 = io_ptw_3_customCSRs_csrs_0_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_customCSRs_csrs_0_wen_0 = io_ptw_3_customCSRs_csrs_0_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_3_customCSRs_csrs_0_wdata_0 = io_ptw_3_customCSRs_csrs_0_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_3_customCSRs_csrs_0_value_0 = io_ptw_3_customCSRs_csrs_0_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_customCSRs_csrs_1_ren_0 = io_ptw_3_customCSRs_csrs_1_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_customCSRs_csrs_1_wen_0 = io_ptw_3_customCSRs_csrs_1_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_3_customCSRs_csrs_1_wdata_0 = io_ptw_3_customCSRs_csrs_1_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_3_customCSRs_csrs_1_value_0 = io_ptw_3_customCSRs_csrs_1_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_customCSRs_csrs_2_ren_0 = io_ptw_3_customCSRs_csrs_2_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_customCSRs_csrs_2_wen_0 = io_ptw_3_customCSRs_csrs_2_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_3_customCSRs_csrs_2_wdata_0 = io_ptw_3_customCSRs_csrs_2_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_3_customCSRs_csrs_2_value_0 = io_ptw_3_customCSRs_csrs_2_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_customCSRs_csrs_3_ren_0 = io_ptw_3_customCSRs_csrs_3_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_customCSRs_csrs_3_wen_0 = io_ptw_3_customCSRs_csrs_3_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_3_customCSRs_csrs_3_wdata_0 = io_ptw_3_customCSRs_csrs_3_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_3_customCSRs_csrs_3_value_0 = io_ptw_3_customCSRs_csrs_3_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_req_ready_0 = io_ptw_4_req_ready; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_resp_valid_0 = io_ptw_4_resp_valid; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_resp_bits_ae_ptw_0 = io_ptw_4_resp_bits_ae_ptw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_resp_bits_ae_final_0 = io_ptw_4_resp_bits_ae_final; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_resp_bits_pf_0 = io_ptw_4_resp_bits_pf; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_resp_bits_gf_0 = io_ptw_4_resp_bits_gf; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_resp_bits_hr_0 = io_ptw_4_resp_bits_hr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_resp_bits_hw_0 = io_ptw_4_resp_bits_hw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_resp_bits_hx_0 = io_ptw_4_resp_bits_hx; // @[ZstdCompressor.scala:95:7]
wire [9:0] io_ptw_4_resp_bits_pte_reserved_for_future_0 = io_ptw_4_resp_bits_pte_reserved_for_future; // @[ZstdCompressor.scala:95:7]
wire [43:0] io_ptw_4_resp_bits_pte_ppn_0 = io_ptw_4_resp_bits_pte_ppn; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_4_resp_bits_pte_reserved_for_software_0 = io_ptw_4_resp_bits_pte_reserved_for_software; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_resp_bits_pte_d_0 = io_ptw_4_resp_bits_pte_d; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_resp_bits_pte_a_0 = io_ptw_4_resp_bits_pte_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_resp_bits_pte_g_0 = io_ptw_4_resp_bits_pte_g; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_resp_bits_pte_u_0 = io_ptw_4_resp_bits_pte_u; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_resp_bits_pte_x_0 = io_ptw_4_resp_bits_pte_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_resp_bits_pte_w_0 = io_ptw_4_resp_bits_pte_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_resp_bits_pte_r_0 = io_ptw_4_resp_bits_pte_r; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_resp_bits_pte_v_0 = io_ptw_4_resp_bits_pte_v; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_4_resp_bits_level_0 = io_ptw_4_resp_bits_level; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_resp_bits_homogeneous_0 = io_ptw_4_resp_bits_homogeneous; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_resp_bits_gpa_valid_0 = io_ptw_4_resp_bits_gpa_valid; // @[ZstdCompressor.scala:95:7]
wire [38:0] io_ptw_4_resp_bits_gpa_bits_0 = io_ptw_4_resp_bits_gpa_bits; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_resp_bits_gpa_is_pte_0 = io_ptw_4_resp_bits_gpa_is_pte; // @[ZstdCompressor.scala:95:7]
wire [3:0] io_ptw_4_ptbr_mode_0 = io_ptw_4_ptbr_mode; // @[ZstdCompressor.scala:95:7]
wire [43:0] io_ptw_4_ptbr_ppn_0 = io_ptw_4_ptbr_ppn; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_status_debug_0 = io_ptw_4_status_debug; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_status_cease_0 = io_ptw_4_status_cease; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_status_wfi_0 = io_ptw_4_status_wfi; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_4_status_isa_0 = io_ptw_4_status_isa; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_4_status_dprv_0 = io_ptw_4_status_dprv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_status_dv_0 = io_ptw_4_status_dv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_4_status_prv_0 = io_ptw_4_status_prv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_status_v_0 = io_ptw_4_status_v; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_status_mpv_0 = io_ptw_4_status_mpv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_status_gva_0 = io_ptw_4_status_gva; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_status_tsr_0 = io_ptw_4_status_tsr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_status_tw_0 = io_ptw_4_status_tw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_status_tvm_0 = io_ptw_4_status_tvm; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_status_mxr_0 = io_ptw_4_status_mxr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_status_sum_0 = io_ptw_4_status_sum; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_status_mprv_0 = io_ptw_4_status_mprv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_4_status_fs_0 = io_ptw_4_status_fs; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_4_status_mpp_0 = io_ptw_4_status_mpp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_status_spp_0 = io_ptw_4_status_spp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_status_mpie_0 = io_ptw_4_status_mpie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_status_spie_0 = io_ptw_4_status_spie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_status_mie_0 = io_ptw_4_status_mie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_status_sie_0 = io_ptw_4_status_sie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_hstatus_spvp_0 = io_ptw_4_hstatus_spvp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_hstatus_spv_0 = io_ptw_4_hstatus_spv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_hstatus_gva_0 = io_ptw_4_hstatus_gva; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_gstatus_debug_0 = io_ptw_4_gstatus_debug; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_gstatus_cease_0 = io_ptw_4_gstatus_cease; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_gstatus_wfi_0 = io_ptw_4_gstatus_wfi; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_4_gstatus_isa_0 = io_ptw_4_gstatus_isa; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_4_gstatus_dprv_0 = io_ptw_4_gstatus_dprv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_gstatus_dv_0 = io_ptw_4_gstatus_dv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_4_gstatus_prv_0 = io_ptw_4_gstatus_prv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_gstatus_v_0 = io_ptw_4_gstatus_v; // @[ZstdCompressor.scala:95:7]
wire [22:0] io_ptw_4_gstatus_zero2_0 = io_ptw_4_gstatus_zero2; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_gstatus_mpv_0 = io_ptw_4_gstatus_mpv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_gstatus_gva_0 = io_ptw_4_gstatus_gva; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_gstatus_mbe_0 = io_ptw_4_gstatus_mbe; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_gstatus_sbe_0 = io_ptw_4_gstatus_sbe; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_4_gstatus_sxl_0 = io_ptw_4_gstatus_sxl; // @[ZstdCompressor.scala:95:7]
wire [7:0] io_ptw_4_gstatus_zero1_0 = io_ptw_4_gstatus_zero1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_gstatus_tsr_0 = io_ptw_4_gstatus_tsr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_gstatus_tw_0 = io_ptw_4_gstatus_tw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_gstatus_tvm_0 = io_ptw_4_gstatus_tvm; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_gstatus_mxr_0 = io_ptw_4_gstatus_mxr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_gstatus_sum_0 = io_ptw_4_gstatus_sum; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_gstatus_mprv_0 = io_ptw_4_gstatus_mprv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_4_gstatus_fs_0 = io_ptw_4_gstatus_fs; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_4_gstatus_mpp_0 = io_ptw_4_gstatus_mpp; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_4_gstatus_vs_0 = io_ptw_4_gstatus_vs; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_gstatus_spp_0 = io_ptw_4_gstatus_spp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_gstatus_mpie_0 = io_ptw_4_gstatus_mpie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_gstatus_ube_0 = io_ptw_4_gstatus_ube; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_gstatus_spie_0 = io_ptw_4_gstatus_spie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_gstatus_upie_0 = io_ptw_4_gstatus_upie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_gstatus_mie_0 = io_ptw_4_gstatus_mie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_gstatus_hie_0 = io_ptw_4_gstatus_hie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_gstatus_sie_0 = io_ptw_4_gstatus_sie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_gstatus_uie_0 = io_ptw_4_gstatus_uie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_pmp_0_cfg_l_0 = io_ptw_4_pmp_0_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_4_pmp_0_cfg_a_0 = io_ptw_4_pmp_0_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_pmp_0_cfg_x_0 = io_ptw_4_pmp_0_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_pmp_0_cfg_w_0 = io_ptw_4_pmp_0_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_pmp_0_cfg_r_0 = io_ptw_4_pmp_0_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_4_pmp_0_addr_0 = io_ptw_4_pmp_0_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_4_pmp_0_mask_0 = io_ptw_4_pmp_0_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_pmp_1_cfg_l_0 = io_ptw_4_pmp_1_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_4_pmp_1_cfg_a_0 = io_ptw_4_pmp_1_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_pmp_1_cfg_x_0 = io_ptw_4_pmp_1_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_pmp_1_cfg_w_0 = io_ptw_4_pmp_1_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_pmp_1_cfg_r_0 = io_ptw_4_pmp_1_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_4_pmp_1_addr_0 = io_ptw_4_pmp_1_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_4_pmp_1_mask_0 = io_ptw_4_pmp_1_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_pmp_2_cfg_l_0 = io_ptw_4_pmp_2_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_4_pmp_2_cfg_a_0 = io_ptw_4_pmp_2_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_pmp_2_cfg_x_0 = io_ptw_4_pmp_2_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_pmp_2_cfg_w_0 = io_ptw_4_pmp_2_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_pmp_2_cfg_r_0 = io_ptw_4_pmp_2_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_4_pmp_2_addr_0 = io_ptw_4_pmp_2_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_4_pmp_2_mask_0 = io_ptw_4_pmp_2_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_pmp_3_cfg_l_0 = io_ptw_4_pmp_3_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_4_pmp_3_cfg_a_0 = io_ptw_4_pmp_3_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_pmp_3_cfg_x_0 = io_ptw_4_pmp_3_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_pmp_3_cfg_w_0 = io_ptw_4_pmp_3_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_pmp_3_cfg_r_0 = io_ptw_4_pmp_3_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_4_pmp_3_addr_0 = io_ptw_4_pmp_3_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_4_pmp_3_mask_0 = io_ptw_4_pmp_3_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_pmp_4_cfg_l_0 = io_ptw_4_pmp_4_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_4_pmp_4_cfg_a_0 = io_ptw_4_pmp_4_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_pmp_4_cfg_x_0 = io_ptw_4_pmp_4_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_pmp_4_cfg_w_0 = io_ptw_4_pmp_4_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_pmp_4_cfg_r_0 = io_ptw_4_pmp_4_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_4_pmp_4_addr_0 = io_ptw_4_pmp_4_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_4_pmp_4_mask_0 = io_ptw_4_pmp_4_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_pmp_5_cfg_l_0 = io_ptw_4_pmp_5_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_4_pmp_5_cfg_a_0 = io_ptw_4_pmp_5_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_pmp_5_cfg_x_0 = io_ptw_4_pmp_5_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_pmp_5_cfg_w_0 = io_ptw_4_pmp_5_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_pmp_5_cfg_r_0 = io_ptw_4_pmp_5_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_4_pmp_5_addr_0 = io_ptw_4_pmp_5_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_4_pmp_5_mask_0 = io_ptw_4_pmp_5_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_pmp_6_cfg_l_0 = io_ptw_4_pmp_6_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_4_pmp_6_cfg_a_0 = io_ptw_4_pmp_6_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_pmp_6_cfg_x_0 = io_ptw_4_pmp_6_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_pmp_6_cfg_w_0 = io_ptw_4_pmp_6_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_pmp_6_cfg_r_0 = io_ptw_4_pmp_6_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_4_pmp_6_addr_0 = io_ptw_4_pmp_6_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_4_pmp_6_mask_0 = io_ptw_4_pmp_6_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_pmp_7_cfg_l_0 = io_ptw_4_pmp_7_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_4_pmp_7_cfg_a_0 = io_ptw_4_pmp_7_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_pmp_7_cfg_x_0 = io_ptw_4_pmp_7_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_pmp_7_cfg_w_0 = io_ptw_4_pmp_7_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_pmp_7_cfg_r_0 = io_ptw_4_pmp_7_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_4_pmp_7_addr_0 = io_ptw_4_pmp_7_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_4_pmp_7_mask_0 = io_ptw_4_pmp_7_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_customCSRs_csrs_0_ren_0 = io_ptw_4_customCSRs_csrs_0_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_customCSRs_csrs_0_wen_0 = io_ptw_4_customCSRs_csrs_0_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_4_customCSRs_csrs_0_wdata_0 = io_ptw_4_customCSRs_csrs_0_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_4_customCSRs_csrs_0_value_0 = io_ptw_4_customCSRs_csrs_0_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_customCSRs_csrs_1_ren_0 = io_ptw_4_customCSRs_csrs_1_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_customCSRs_csrs_1_wen_0 = io_ptw_4_customCSRs_csrs_1_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_4_customCSRs_csrs_1_wdata_0 = io_ptw_4_customCSRs_csrs_1_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_4_customCSRs_csrs_1_value_0 = io_ptw_4_customCSRs_csrs_1_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_customCSRs_csrs_2_ren_0 = io_ptw_4_customCSRs_csrs_2_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_customCSRs_csrs_2_wen_0 = io_ptw_4_customCSRs_csrs_2_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_4_customCSRs_csrs_2_wdata_0 = io_ptw_4_customCSRs_csrs_2_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_4_customCSRs_csrs_2_value_0 = io_ptw_4_customCSRs_csrs_2_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_customCSRs_csrs_3_ren_0 = io_ptw_4_customCSRs_csrs_3_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_customCSRs_csrs_3_wen_0 = io_ptw_4_customCSRs_csrs_3_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_4_customCSRs_csrs_3_wdata_0 = io_ptw_4_customCSRs_csrs_3_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_4_customCSRs_csrs_3_value_0 = io_ptw_4_customCSRs_csrs_3_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_req_ready_0 = io_ptw_5_req_ready; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_resp_valid_0 = io_ptw_5_resp_valid; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_resp_bits_ae_ptw_0 = io_ptw_5_resp_bits_ae_ptw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_resp_bits_ae_final_0 = io_ptw_5_resp_bits_ae_final; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_resp_bits_pf_0 = io_ptw_5_resp_bits_pf; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_resp_bits_gf_0 = io_ptw_5_resp_bits_gf; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_resp_bits_hr_0 = io_ptw_5_resp_bits_hr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_resp_bits_hw_0 = io_ptw_5_resp_bits_hw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_resp_bits_hx_0 = io_ptw_5_resp_bits_hx; // @[ZstdCompressor.scala:95:7]
wire [9:0] io_ptw_5_resp_bits_pte_reserved_for_future_0 = io_ptw_5_resp_bits_pte_reserved_for_future; // @[ZstdCompressor.scala:95:7]
wire [43:0] io_ptw_5_resp_bits_pte_ppn_0 = io_ptw_5_resp_bits_pte_ppn; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_5_resp_bits_pte_reserved_for_software_0 = io_ptw_5_resp_bits_pte_reserved_for_software; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_resp_bits_pte_d_0 = io_ptw_5_resp_bits_pte_d; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_resp_bits_pte_a_0 = io_ptw_5_resp_bits_pte_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_resp_bits_pte_g_0 = io_ptw_5_resp_bits_pte_g; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_resp_bits_pte_u_0 = io_ptw_5_resp_bits_pte_u; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_resp_bits_pte_x_0 = io_ptw_5_resp_bits_pte_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_resp_bits_pte_w_0 = io_ptw_5_resp_bits_pte_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_resp_bits_pte_r_0 = io_ptw_5_resp_bits_pte_r; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_resp_bits_pte_v_0 = io_ptw_5_resp_bits_pte_v; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_5_resp_bits_level_0 = io_ptw_5_resp_bits_level; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_resp_bits_homogeneous_0 = io_ptw_5_resp_bits_homogeneous; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_resp_bits_gpa_valid_0 = io_ptw_5_resp_bits_gpa_valid; // @[ZstdCompressor.scala:95:7]
wire [38:0] io_ptw_5_resp_bits_gpa_bits_0 = io_ptw_5_resp_bits_gpa_bits; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_resp_bits_gpa_is_pte_0 = io_ptw_5_resp_bits_gpa_is_pte; // @[ZstdCompressor.scala:95:7]
wire [3:0] io_ptw_5_ptbr_mode_0 = io_ptw_5_ptbr_mode; // @[ZstdCompressor.scala:95:7]
wire [43:0] io_ptw_5_ptbr_ppn_0 = io_ptw_5_ptbr_ppn; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_status_debug_0 = io_ptw_5_status_debug; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_status_cease_0 = io_ptw_5_status_cease; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_status_wfi_0 = io_ptw_5_status_wfi; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_5_status_isa_0 = io_ptw_5_status_isa; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_5_status_dprv_0 = io_ptw_5_status_dprv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_status_dv_0 = io_ptw_5_status_dv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_5_status_prv_0 = io_ptw_5_status_prv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_status_v_0 = io_ptw_5_status_v; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_status_mpv_0 = io_ptw_5_status_mpv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_status_gva_0 = io_ptw_5_status_gva; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_status_tsr_0 = io_ptw_5_status_tsr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_status_tw_0 = io_ptw_5_status_tw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_status_tvm_0 = io_ptw_5_status_tvm; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_status_mxr_0 = io_ptw_5_status_mxr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_status_sum_0 = io_ptw_5_status_sum; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_status_mprv_0 = io_ptw_5_status_mprv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_5_status_fs_0 = io_ptw_5_status_fs; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_5_status_mpp_0 = io_ptw_5_status_mpp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_status_spp_0 = io_ptw_5_status_spp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_status_mpie_0 = io_ptw_5_status_mpie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_status_spie_0 = io_ptw_5_status_spie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_status_mie_0 = io_ptw_5_status_mie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_status_sie_0 = io_ptw_5_status_sie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_hstatus_spvp_0 = io_ptw_5_hstatus_spvp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_hstatus_spv_0 = io_ptw_5_hstatus_spv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_hstatus_gva_0 = io_ptw_5_hstatus_gva; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_gstatus_debug_0 = io_ptw_5_gstatus_debug; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_gstatus_cease_0 = io_ptw_5_gstatus_cease; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_gstatus_wfi_0 = io_ptw_5_gstatus_wfi; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_5_gstatus_isa_0 = io_ptw_5_gstatus_isa; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_5_gstatus_dprv_0 = io_ptw_5_gstatus_dprv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_gstatus_dv_0 = io_ptw_5_gstatus_dv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_5_gstatus_prv_0 = io_ptw_5_gstatus_prv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_gstatus_v_0 = io_ptw_5_gstatus_v; // @[ZstdCompressor.scala:95:7]
wire [22:0] io_ptw_5_gstatus_zero2_0 = io_ptw_5_gstatus_zero2; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_gstatus_mpv_0 = io_ptw_5_gstatus_mpv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_gstatus_gva_0 = io_ptw_5_gstatus_gva; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_gstatus_mbe_0 = io_ptw_5_gstatus_mbe; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_gstatus_sbe_0 = io_ptw_5_gstatus_sbe; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_5_gstatus_sxl_0 = io_ptw_5_gstatus_sxl; // @[ZstdCompressor.scala:95:7]
wire [7:0] io_ptw_5_gstatus_zero1_0 = io_ptw_5_gstatus_zero1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_gstatus_tsr_0 = io_ptw_5_gstatus_tsr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_gstatus_tw_0 = io_ptw_5_gstatus_tw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_gstatus_tvm_0 = io_ptw_5_gstatus_tvm; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_gstatus_mxr_0 = io_ptw_5_gstatus_mxr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_gstatus_sum_0 = io_ptw_5_gstatus_sum; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_gstatus_mprv_0 = io_ptw_5_gstatus_mprv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_5_gstatus_fs_0 = io_ptw_5_gstatus_fs; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_5_gstatus_mpp_0 = io_ptw_5_gstatus_mpp; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_5_gstatus_vs_0 = io_ptw_5_gstatus_vs; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_gstatus_spp_0 = io_ptw_5_gstatus_spp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_gstatus_mpie_0 = io_ptw_5_gstatus_mpie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_gstatus_ube_0 = io_ptw_5_gstatus_ube; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_gstatus_spie_0 = io_ptw_5_gstatus_spie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_gstatus_upie_0 = io_ptw_5_gstatus_upie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_gstatus_mie_0 = io_ptw_5_gstatus_mie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_gstatus_hie_0 = io_ptw_5_gstatus_hie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_gstatus_sie_0 = io_ptw_5_gstatus_sie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_gstatus_uie_0 = io_ptw_5_gstatus_uie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_pmp_0_cfg_l_0 = io_ptw_5_pmp_0_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_5_pmp_0_cfg_a_0 = io_ptw_5_pmp_0_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_pmp_0_cfg_x_0 = io_ptw_5_pmp_0_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_pmp_0_cfg_w_0 = io_ptw_5_pmp_0_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_pmp_0_cfg_r_0 = io_ptw_5_pmp_0_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_5_pmp_0_addr_0 = io_ptw_5_pmp_0_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_5_pmp_0_mask_0 = io_ptw_5_pmp_0_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_pmp_1_cfg_l_0 = io_ptw_5_pmp_1_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_5_pmp_1_cfg_a_0 = io_ptw_5_pmp_1_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_pmp_1_cfg_x_0 = io_ptw_5_pmp_1_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_pmp_1_cfg_w_0 = io_ptw_5_pmp_1_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_pmp_1_cfg_r_0 = io_ptw_5_pmp_1_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_5_pmp_1_addr_0 = io_ptw_5_pmp_1_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_5_pmp_1_mask_0 = io_ptw_5_pmp_1_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_pmp_2_cfg_l_0 = io_ptw_5_pmp_2_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_5_pmp_2_cfg_a_0 = io_ptw_5_pmp_2_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_pmp_2_cfg_x_0 = io_ptw_5_pmp_2_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_pmp_2_cfg_w_0 = io_ptw_5_pmp_2_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_pmp_2_cfg_r_0 = io_ptw_5_pmp_2_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_5_pmp_2_addr_0 = io_ptw_5_pmp_2_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_5_pmp_2_mask_0 = io_ptw_5_pmp_2_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_pmp_3_cfg_l_0 = io_ptw_5_pmp_3_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_5_pmp_3_cfg_a_0 = io_ptw_5_pmp_3_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_pmp_3_cfg_x_0 = io_ptw_5_pmp_3_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_pmp_3_cfg_w_0 = io_ptw_5_pmp_3_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_pmp_3_cfg_r_0 = io_ptw_5_pmp_3_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_5_pmp_3_addr_0 = io_ptw_5_pmp_3_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_5_pmp_3_mask_0 = io_ptw_5_pmp_3_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_pmp_4_cfg_l_0 = io_ptw_5_pmp_4_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_5_pmp_4_cfg_a_0 = io_ptw_5_pmp_4_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_pmp_4_cfg_x_0 = io_ptw_5_pmp_4_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_pmp_4_cfg_w_0 = io_ptw_5_pmp_4_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_pmp_4_cfg_r_0 = io_ptw_5_pmp_4_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_5_pmp_4_addr_0 = io_ptw_5_pmp_4_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_5_pmp_4_mask_0 = io_ptw_5_pmp_4_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_pmp_5_cfg_l_0 = io_ptw_5_pmp_5_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_5_pmp_5_cfg_a_0 = io_ptw_5_pmp_5_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_pmp_5_cfg_x_0 = io_ptw_5_pmp_5_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_pmp_5_cfg_w_0 = io_ptw_5_pmp_5_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_pmp_5_cfg_r_0 = io_ptw_5_pmp_5_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_5_pmp_5_addr_0 = io_ptw_5_pmp_5_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_5_pmp_5_mask_0 = io_ptw_5_pmp_5_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_pmp_6_cfg_l_0 = io_ptw_5_pmp_6_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_5_pmp_6_cfg_a_0 = io_ptw_5_pmp_6_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_pmp_6_cfg_x_0 = io_ptw_5_pmp_6_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_pmp_6_cfg_w_0 = io_ptw_5_pmp_6_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_pmp_6_cfg_r_0 = io_ptw_5_pmp_6_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_5_pmp_6_addr_0 = io_ptw_5_pmp_6_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_5_pmp_6_mask_0 = io_ptw_5_pmp_6_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_pmp_7_cfg_l_0 = io_ptw_5_pmp_7_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_5_pmp_7_cfg_a_0 = io_ptw_5_pmp_7_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_pmp_7_cfg_x_0 = io_ptw_5_pmp_7_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_pmp_7_cfg_w_0 = io_ptw_5_pmp_7_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_pmp_7_cfg_r_0 = io_ptw_5_pmp_7_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_5_pmp_7_addr_0 = io_ptw_5_pmp_7_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_5_pmp_7_mask_0 = io_ptw_5_pmp_7_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_customCSRs_csrs_0_ren_0 = io_ptw_5_customCSRs_csrs_0_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_customCSRs_csrs_0_wen_0 = io_ptw_5_customCSRs_csrs_0_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_5_customCSRs_csrs_0_wdata_0 = io_ptw_5_customCSRs_csrs_0_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_5_customCSRs_csrs_0_value_0 = io_ptw_5_customCSRs_csrs_0_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_customCSRs_csrs_1_ren_0 = io_ptw_5_customCSRs_csrs_1_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_customCSRs_csrs_1_wen_0 = io_ptw_5_customCSRs_csrs_1_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_5_customCSRs_csrs_1_wdata_0 = io_ptw_5_customCSRs_csrs_1_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_5_customCSRs_csrs_1_value_0 = io_ptw_5_customCSRs_csrs_1_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_customCSRs_csrs_2_ren_0 = io_ptw_5_customCSRs_csrs_2_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_customCSRs_csrs_2_wen_0 = io_ptw_5_customCSRs_csrs_2_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_5_customCSRs_csrs_2_wdata_0 = io_ptw_5_customCSRs_csrs_2_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_5_customCSRs_csrs_2_value_0 = io_ptw_5_customCSRs_csrs_2_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_customCSRs_csrs_3_ren_0 = io_ptw_5_customCSRs_csrs_3_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_customCSRs_csrs_3_wen_0 = io_ptw_5_customCSRs_csrs_3_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_5_customCSRs_csrs_3_wdata_0 = io_ptw_5_customCSRs_csrs_3_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_5_customCSRs_csrs_3_value_0 = io_ptw_5_customCSRs_csrs_3_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_req_ready_0 = io_ptw_6_req_ready; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_resp_valid_0 = io_ptw_6_resp_valid; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_resp_bits_ae_ptw_0 = io_ptw_6_resp_bits_ae_ptw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_resp_bits_ae_final_0 = io_ptw_6_resp_bits_ae_final; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_resp_bits_pf_0 = io_ptw_6_resp_bits_pf; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_resp_bits_gf_0 = io_ptw_6_resp_bits_gf; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_resp_bits_hr_0 = io_ptw_6_resp_bits_hr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_resp_bits_hw_0 = io_ptw_6_resp_bits_hw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_resp_bits_hx_0 = io_ptw_6_resp_bits_hx; // @[ZstdCompressor.scala:95:7]
wire [9:0] io_ptw_6_resp_bits_pte_reserved_for_future_0 = io_ptw_6_resp_bits_pte_reserved_for_future; // @[ZstdCompressor.scala:95:7]
wire [43:0] io_ptw_6_resp_bits_pte_ppn_0 = io_ptw_6_resp_bits_pte_ppn; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_6_resp_bits_pte_reserved_for_software_0 = io_ptw_6_resp_bits_pte_reserved_for_software; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_resp_bits_pte_d_0 = io_ptw_6_resp_bits_pte_d; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_resp_bits_pte_a_0 = io_ptw_6_resp_bits_pte_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_resp_bits_pte_g_0 = io_ptw_6_resp_bits_pte_g; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_resp_bits_pte_u_0 = io_ptw_6_resp_bits_pte_u; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_resp_bits_pte_x_0 = io_ptw_6_resp_bits_pte_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_resp_bits_pte_w_0 = io_ptw_6_resp_bits_pte_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_resp_bits_pte_r_0 = io_ptw_6_resp_bits_pte_r; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_resp_bits_pte_v_0 = io_ptw_6_resp_bits_pte_v; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_6_resp_bits_level_0 = io_ptw_6_resp_bits_level; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_resp_bits_homogeneous_0 = io_ptw_6_resp_bits_homogeneous; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_resp_bits_gpa_valid_0 = io_ptw_6_resp_bits_gpa_valid; // @[ZstdCompressor.scala:95:7]
wire [38:0] io_ptw_6_resp_bits_gpa_bits_0 = io_ptw_6_resp_bits_gpa_bits; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_resp_bits_gpa_is_pte_0 = io_ptw_6_resp_bits_gpa_is_pte; // @[ZstdCompressor.scala:95:7]
wire [3:0] io_ptw_6_ptbr_mode_0 = io_ptw_6_ptbr_mode; // @[ZstdCompressor.scala:95:7]
wire [43:0] io_ptw_6_ptbr_ppn_0 = io_ptw_6_ptbr_ppn; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_status_debug_0 = io_ptw_6_status_debug; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_status_cease_0 = io_ptw_6_status_cease; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_status_wfi_0 = io_ptw_6_status_wfi; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_6_status_isa_0 = io_ptw_6_status_isa; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_6_status_dprv_0 = io_ptw_6_status_dprv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_status_dv_0 = io_ptw_6_status_dv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_6_status_prv_0 = io_ptw_6_status_prv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_status_v_0 = io_ptw_6_status_v; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_status_mpv_0 = io_ptw_6_status_mpv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_status_gva_0 = io_ptw_6_status_gva; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_status_tsr_0 = io_ptw_6_status_tsr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_status_tw_0 = io_ptw_6_status_tw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_status_tvm_0 = io_ptw_6_status_tvm; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_status_mxr_0 = io_ptw_6_status_mxr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_status_sum_0 = io_ptw_6_status_sum; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_status_mprv_0 = io_ptw_6_status_mprv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_6_status_fs_0 = io_ptw_6_status_fs; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_6_status_mpp_0 = io_ptw_6_status_mpp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_status_spp_0 = io_ptw_6_status_spp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_status_mpie_0 = io_ptw_6_status_mpie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_status_spie_0 = io_ptw_6_status_spie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_status_mie_0 = io_ptw_6_status_mie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_status_sie_0 = io_ptw_6_status_sie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_hstatus_spvp_0 = io_ptw_6_hstatus_spvp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_hstatus_spv_0 = io_ptw_6_hstatus_spv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_hstatus_gva_0 = io_ptw_6_hstatus_gva; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_gstatus_debug_0 = io_ptw_6_gstatus_debug; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_gstatus_cease_0 = io_ptw_6_gstatus_cease; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_gstatus_wfi_0 = io_ptw_6_gstatus_wfi; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_6_gstatus_isa_0 = io_ptw_6_gstatus_isa; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_6_gstatus_dprv_0 = io_ptw_6_gstatus_dprv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_gstatus_dv_0 = io_ptw_6_gstatus_dv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_6_gstatus_prv_0 = io_ptw_6_gstatus_prv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_gstatus_v_0 = io_ptw_6_gstatus_v; // @[ZstdCompressor.scala:95:7]
wire [22:0] io_ptw_6_gstatus_zero2_0 = io_ptw_6_gstatus_zero2; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_gstatus_mpv_0 = io_ptw_6_gstatus_mpv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_gstatus_gva_0 = io_ptw_6_gstatus_gva; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_gstatus_mbe_0 = io_ptw_6_gstatus_mbe; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_gstatus_sbe_0 = io_ptw_6_gstatus_sbe; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_6_gstatus_sxl_0 = io_ptw_6_gstatus_sxl; // @[ZstdCompressor.scala:95:7]
wire [7:0] io_ptw_6_gstatus_zero1_0 = io_ptw_6_gstatus_zero1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_gstatus_tsr_0 = io_ptw_6_gstatus_tsr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_gstatus_tw_0 = io_ptw_6_gstatus_tw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_gstatus_tvm_0 = io_ptw_6_gstatus_tvm; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_gstatus_mxr_0 = io_ptw_6_gstatus_mxr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_gstatus_sum_0 = io_ptw_6_gstatus_sum; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_gstatus_mprv_0 = io_ptw_6_gstatus_mprv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_6_gstatus_fs_0 = io_ptw_6_gstatus_fs; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_6_gstatus_mpp_0 = io_ptw_6_gstatus_mpp; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_6_gstatus_vs_0 = io_ptw_6_gstatus_vs; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_gstatus_spp_0 = io_ptw_6_gstatus_spp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_gstatus_mpie_0 = io_ptw_6_gstatus_mpie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_gstatus_ube_0 = io_ptw_6_gstatus_ube; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_gstatus_spie_0 = io_ptw_6_gstatus_spie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_gstatus_upie_0 = io_ptw_6_gstatus_upie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_gstatus_mie_0 = io_ptw_6_gstatus_mie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_gstatus_hie_0 = io_ptw_6_gstatus_hie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_gstatus_sie_0 = io_ptw_6_gstatus_sie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_gstatus_uie_0 = io_ptw_6_gstatus_uie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_pmp_0_cfg_l_0 = io_ptw_6_pmp_0_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_6_pmp_0_cfg_a_0 = io_ptw_6_pmp_0_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_pmp_0_cfg_x_0 = io_ptw_6_pmp_0_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_pmp_0_cfg_w_0 = io_ptw_6_pmp_0_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_pmp_0_cfg_r_0 = io_ptw_6_pmp_0_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_6_pmp_0_addr_0 = io_ptw_6_pmp_0_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_6_pmp_0_mask_0 = io_ptw_6_pmp_0_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_pmp_1_cfg_l_0 = io_ptw_6_pmp_1_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_6_pmp_1_cfg_a_0 = io_ptw_6_pmp_1_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_pmp_1_cfg_x_0 = io_ptw_6_pmp_1_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_pmp_1_cfg_w_0 = io_ptw_6_pmp_1_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_pmp_1_cfg_r_0 = io_ptw_6_pmp_1_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_6_pmp_1_addr_0 = io_ptw_6_pmp_1_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_6_pmp_1_mask_0 = io_ptw_6_pmp_1_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_pmp_2_cfg_l_0 = io_ptw_6_pmp_2_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_6_pmp_2_cfg_a_0 = io_ptw_6_pmp_2_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_pmp_2_cfg_x_0 = io_ptw_6_pmp_2_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_pmp_2_cfg_w_0 = io_ptw_6_pmp_2_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_pmp_2_cfg_r_0 = io_ptw_6_pmp_2_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_6_pmp_2_addr_0 = io_ptw_6_pmp_2_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_6_pmp_2_mask_0 = io_ptw_6_pmp_2_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_pmp_3_cfg_l_0 = io_ptw_6_pmp_3_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_6_pmp_3_cfg_a_0 = io_ptw_6_pmp_3_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_pmp_3_cfg_x_0 = io_ptw_6_pmp_3_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_pmp_3_cfg_w_0 = io_ptw_6_pmp_3_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_pmp_3_cfg_r_0 = io_ptw_6_pmp_3_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_6_pmp_3_addr_0 = io_ptw_6_pmp_3_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_6_pmp_3_mask_0 = io_ptw_6_pmp_3_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_pmp_4_cfg_l_0 = io_ptw_6_pmp_4_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_6_pmp_4_cfg_a_0 = io_ptw_6_pmp_4_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_pmp_4_cfg_x_0 = io_ptw_6_pmp_4_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_pmp_4_cfg_w_0 = io_ptw_6_pmp_4_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_pmp_4_cfg_r_0 = io_ptw_6_pmp_4_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_6_pmp_4_addr_0 = io_ptw_6_pmp_4_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_6_pmp_4_mask_0 = io_ptw_6_pmp_4_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_pmp_5_cfg_l_0 = io_ptw_6_pmp_5_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_6_pmp_5_cfg_a_0 = io_ptw_6_pmp_5_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_pmp_5_cfg_x_0 = io_ptw_6_pmp_5_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_pmp_5_cfg_w_0 = io_ptw_6_pmp_5_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_pmp_5_cfg_r_0 = io_ptw_6_pmp_5_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_6_pmp_5_addr_0 = io_ptw_6_pmp_5_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_6_pmp_5_mask_0 = io_ptw_6_pmp_5_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_pmp_6_cfg_l_0 = io_ptw_6_pmp_6_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_6_pmp_6_cfg_a_0 = io_ptw_6_pmp_6_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_pmp_6_cfg_x_0 = io_ptw_6_pmp_6_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_pmp_6_cfg_w_0 = io_ptw_6_pmp_6_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_pmp_6_cfg_r_0 = io_ptw_6_pmp_6_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_6_pmp_6_addr_0 = io_ptw_6_pmp_6_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_6_pmp_6_mask_0 = io_ptw_6_pmp_6_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_pmp_7_cfg_l_0 = io_ptw_6_pmp_7_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_6_pmp_7_cfg_a_0 = io_ptw_6_pmp_7_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_pmp_7_cfg_x_0 = io_ptw_6_pmp_7_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_pmp_7_cfg_w_0 = io_ptw_6_pmp_7_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_pmp_7_cfg_r_0 = io_ptw_6_pmp_7_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_6_pmp_7_addr_0 = io_ptw_6_pmp_7_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_6_pmp_7_mask_0 = io_ptw_6_pmp_7_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_customCSRs_csrs_0_ren_0 = io_ptw_6_customCSRs_csrs_0_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_customCSRs_csrs_0_wen_0 = io_ptw_6_customCSRs_csrs_0_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_6_customCSRs_csrs_0_wdata_0 = io_ptw_6_customCSRs_csrs_0_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_6_customCSRs_csrs_0_value_0 = io_ptw_6_customCSRs_csrs_0_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_customCSRs_csrs_1_ren_0 = io_ptw_6_customCSRs_csrs_1_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_customCSRs_csrs_1_wen_0 = io_ptw_6_customCSRs_csrs_1_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_6_customCSRs_csrs_1_wdata_0 = io_ptw_6_customCSRs_csrs_1_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_6_customCSRs_csrs_1_value_0 = io_ptw_6_customCSRs_csrs_1_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_customCSRs_csrs_2_ren_0 = io_ptw_6_customCSRs_csrs_2_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_customCSRs_csrs_2_wen_0 = io_ptw_6_customCSRs_csrs_2_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_6_customCSRs_csrs_2_wdata_0 = io_ptw_6_customCSRs_csrs_2_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_6_customCSRs_csrs_2_value_0 = io_ptw_6_customCSRs_csrs_2_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_customCSRs_csrs_3_ren_0 = io_ptw_6_customCSRs_csrs_3_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_customCSRs_csrs_3_wen_0 = io_ptw_6_customCSRs_csrs_3_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_6_customCSRs_csrs_3_wdata_0 = io_ptw_6_customCSRs_csrs_3_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_6_customCSRs_csrs_3_value_0 = io_ptw_6_customCSRs_csrs_3_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_req_ready_0 = io_ptw_7_req_ready; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_resp_valid_0 = io_ptw_7_resp_valid; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_resp_bits_ae_ptw_0 = io_ptw_7_resp_bits_ae_ptw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_resp_bits_ae_final_0 = io_ptw_7_resp_bits_ae_final; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_resp_bits_pf_0 = io_ptw_7_resp_bits_pf; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_resp_bits_gf_0 = io_ptw_7_resp_bits_gf; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_resp_bits_hr_0 = io_ptw_7_resp_bits_hr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_resp_bits_hw_0 = io_ptw_7_resp_bits_hw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_resp_bits_hx_0 = io_ptw_7_resp_bits_hx; // @[ZstdCompressor.scala:95:7]
wire [9:0] io_ptw_7_resp_bits_pte_reserved_for_future_0 = io_ptw_7_resp_bits_pte_reserved_for_future; // @[ZstdCompressor.scala:95:7]
wire [43:0] io_ptw_7_resp_bits_pte_ppn_0 = io_ptw_7_resp_bits_pte_ppn; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_7_resp_bits_pte_reserved_for_software_0 = io_ptw_7_resp_bits_pte_reserved_for_software; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_resp_bits_pte_d_0 = io_ptw_7_resp_bits_pte_d; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_resp_bits_pte_a_0 = io_ptw_7_resp_bits_pte_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_resp_bits_pte_g_0 = io_ptw_7_resp_bits_pte_g; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_resp_bits_pte_u_0 = io_ptw_7_resp_bits_pte_u; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_resp_bits_pte_x_0 = io_ptw_7_resp_bits_pte_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_resp_bits_pte_w_0 = io_ptw_7_resp_bits_pte_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_resp_bits_pte_r_0 = io_ptw_7_resp_bits_pte_r; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_resp_bits_pte_v_0 = io_ptw_7_resp_bits_pte_v; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_7_resp_bits_level_0 = io_ptw_7_resp_bits_level; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_resp_bits_homogeneous_0 = io_ptw_7_resp_bits_homogeneous; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_resp_bits_gpa_valid_0 = io_ptw_7_resp_bits_gpa_valid; // @[ZstdCompressor.scala:95:7]
wire [38:0] io_ptw_7_resp_bits_gpa_bits_0 = io_ptw_7_resp_bits_gpa_bits; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_resp_bits_gpa_is_pte_0 = io_ptw_7_resp_bits_gpa_is_pte; // @[ZstdCompressor.scala:95:7]
wire [3:0] io_ptw_7_ptbr_mode_0 = io_ptw_7_ptbr_mode; // @[ZstdCompressor.scala:95:7]
wire [43:0] io_ptw_7_ptbr_ppn_0 = io_ptw_7_ptbr_ppn; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_status_debug_0 = io_ptw_7_status_debug; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_status_cease_0 = io_ptw_7_status_cease; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_status_wfi_0 = io_ptw_7_status_wfi; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_7_status_isa_0 = io_ptw_7_status_isa; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_7_status_dprv_0 = io_ptw_7_status_dprv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_status_dv_0 = io_ptw_7_status_dv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_7_status_prv_0 = io_ptw_7_status_prv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_status_v_0 = io_ptw_7_status_v; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_status_mpv_0 = io_ptw_7_status_mpv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_status_gva_0 = io_ptw_7_status_gva; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_status_tsr_0 = io_ptw_7_status_tsr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_status_tw_0 = io_ptw_7_status_tw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_status_tvm_0 = io_ptw_7_status_tvm; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_status_mxr_0 = io_ptw_7_status_mxr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_status_sum_0 = io_ptw_7_status_sum; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_status_mprv_0 = io_ptw_7_status_mprv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_7_status_fs_0 = io_ptw_7_status_fs; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_7_status_mpp_0 = io_ptw_7_status_mpp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_status_spp_0 = io_ptw_7_status_spp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_status_mpie_0 = io_ptw_7_status_mpie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_status_spie_0 = io_ptw_7_status_spie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_status_mie_0 = io_ptw_7_status_mie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_status_sie_0 = io_ptw_7_status_sie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_hstatus_spvp_0 = io_ptw_7_hstatus_spvp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_hstatus_spv_0 = io_ptw_7_hstatus_spv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_hstatus_gva_0 = io_ptw_7_hstatus_gva; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_gstatus_debug_0 = io_ptw_7_gstatus_debug; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_gstatus_cease_0 = io_ptw_7_gstatus_cease; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_gstatus_wfi_0 = io_ptw_7_gstatus_wfi; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_7_gstatus_isa_0 = io_ptw_7_gstatus_isa; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_7_gstatus_dprv_0 = io_ptw_7_gstatus_dprv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_gstatus_dv_0 = io_ptw_7_gstatus_dv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_7_gstatus_prv_0 = io_ptw_7_gstatus_prv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_gstatus_v_0 = io_ptw_7_gstatus_v; // @[ZstdCompressor.scala:95:7]
wire [22:0] io_ptw_7_gstatus_zero2_0 = io_ptw_7_gstatus_zero2; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_gstatus_mpv_0 = io_ptw_7_gstatus_mpv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_gstatus_gva_0 = io_ptw_7_gstatus_gva; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_gstatus_mbe_0 = io_ptw_7_gstatus_mbe; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_gstatus_sbe_0 = io_ptw_7_gstatus_sbe; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_7_gstatus_sxl_0 = io_ptw_7_gstatus_sxl; // @[ZstdCompressor.scala:95:7]
wire [7:0] io_ptw_7_gstatus_zero1_0 = io_ptw_7_gstatus_zero1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_gstatus_tsr_0 = io_ptw_7_gstatus_tsr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_gstatus_tw_0 = io_ptw_7_gstatus_tw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_gstatus_tvm_0 = io_ptw_7_gstatus_tvm; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_gstatus_mxr_0 = io_ptw_7_gstatus_mxr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_gstatus_sum_0 = io_ptw_7_gstatus_sum; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_gstatus_mprv_0 = io_ptw_7_gstatus_mprv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_7_gstatus_fs_0 = io_ptw_7_gstatus_fs; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_7_gstatus_mpp_0 = io_ptw_7_gstatus_mpp; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_7_gstatus_vs_0 = io_ptw_7_gstatus_vs; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_gstatus_spp_0 = io_ptw_7_gstatus_spp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_gstatus_mpie_0 = io_ptw_7_gstatus_mpie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_gstatus_ube_0 = io_ptw_7_gstatus_ube; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_gstatus_spie_0 = io_ptw_7_gstatus_spie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_gstatus_upie_0 = io_ptw_7_gstatus_upie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_gstatus_mie_0 = io_ptw_7_gstatus_mie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_gstatus_hie_0 = io_ptw_7_gstatus_hie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_gstatus_sie_0 = io_ptw_7_gstatus_sie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_gstatus_uie_0 = io_ptw_7_gstatus_uie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_pmp_0_cfg_l_0 = io_ptw_7_pmp_0_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_7_pmp_0_cfg_a_0 = io_ptw_7_pmp_0_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_pmp_0_cfg_x_0 = io_ptw_7_pmp_0_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_pmp_0_cfg_w_0 = io_ptw_7_pmp_0_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_pmp_0_cfg_r_0 = io_ptw_7_pmp_0_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_7_pmp_0_addr_0 = io_ptw_7_pmp_0_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_7_pmp_0_mask_0 = io_ptw_7_pmp_0_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_pmp_1_cfg_l_0 = io_ptw_7_pmp_1_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_7_pmp_1_cfg_a_0 = io_ptw_7_pmp_1_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_pmp_1_cfg_x_0 = io_ptw_7_pmp_1_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_pmp_1_cfg_w_0 = io_ptw_7_pmp_1_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_pmp_1_cfg_r_0 = io_ptw_7_pmp_1_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_7_pmp_1_addr_0 = io_ptw_7_pmp_1_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_7_pmp_1_mask_0 = io_ptw_7_pmp_1_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_pmp_2_cfg_l_0 = io_ptw_7_pmp_2_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_7_pmp_2_cfg_a_0 = io_ptw_7_pmp_2_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_pmp_2_cfg_x_0 = io_ptw_7_pmp_2_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_pmp_2_cfg_w_0 = io_ptw_7_pmp_2_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_pmp_2_cfg_r_0 = io_ptw_7_pmp_2_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_7_pmp_2_addr_0 = io_ptw_7_pmp_2_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_7_pmp_2_mask_0 = io_ptw_7_pmp_2_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_pmp_3_cfg_l_0 = io_ptw_7_pmp_3_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_7_pmp_3_cfg_a_0 = io_ptw_7_pmp_3_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_pmp_3_cfg_x_0 = io_ptw_7_pmp_3_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_pmp_3_cfg_w_0 = io_ptw_7_pmp_3_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_pmp_3_cfg_r_0 = io_ptw_7_pmp_3_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_7_pmp_3_addr_0 = io_ptw_7_pmp_3_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_7_pmp_3_mask_0 = io_ptw_7_pmp_3_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_pmp_4_cfg_l_0 = io_ptw_7_pmp_4_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_7_pmp_4_cfg_a_0 = io_ptw_7_pmp_4_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_pmp_4_cfg_x_0 = io_ptw_7_pmp_4_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_pmp_4_cfg_w_0 = io_ptw_7_pmp_4_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_pmp_4_cfg_r_0 = io_ptw_7_pmp_4_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_7_pmp_4_addr_0 = io_ptw_7_pmp_4_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_7_pmp_4_mask_0 = io_ptw_7_pmp_4_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_pmp_5_cfg_l_0 = io_ptw_7_pmp_5_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_7_pmp_5_cfg_a_0 = io_ptw_7_pmp_5_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_pmp_5_cfg_x_0 = io_ptw_7_pmp_5_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_pmp_5_cfg_w_0 = io_ptw_7_pmp_5_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_pmp_5_cfg_r_0 = io_ptw_7_pmp_5_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_7_pmp_5_addr_0 = io_ptw_7_pmp_5_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_7_pmp_5_mask_0 = io_ptw_7_pmp_5_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_pmp_6_cfg_l_0 = io_ptw_7_pmp_6_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_7_pmp_6_cfg_a_0 = io_ptw_7_pmp_6_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_pmp_6_cfg_x_0 = io_ptw_7_pmp_6_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_pmp_6_cfg_w_0 = io_ptw_7_pmp_6_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_pmp_6_cfg_r_0 = io_ptw_7_pmp_6_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_7_pmp_6_addr_0 = io_ptw_7_pmp_6_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_7_pmp_6_mask_0 = io_ptw_7_pmp_6_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_pmp_7_cfg_l_0 = io_ptw_7_pmp_7_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_7_pmp_7_cfg_a_0 = io_ptw_7_pmp_7_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_pmp_7_cfg_x_0 = io_ptw_7_pmp_7_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_pmp_7_cfg_w_0 = io_ptw_7_pmp_7_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_pmp_7_cfg_r_0 = io_ptw_7_pmp_7_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_7_pmp_7_addr_0 = io_ptw_7_pmp_7_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_7_pmp_7_mask_0 = io_ptw_7_pmp_7_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_customCSRs_csrs_0_ren_0 = io_ptw_7_customCSRs_csrs_0_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_customCSRs_csrs_0_wen_0 = io_ptw_7_customCSRs_csrs_0_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_7_customCSRs_csrs_0_wdata_0 = io_ptw_7_customCSRs_csrs_0_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_7_customCSRs_csrs_0_value_0 = io_ptw_7_customCSRs_csrs_0_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_customCSRs_csrs_1_ren_0 = io_ptw_7_customCSRs_csrs_1_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_customCSRs_csrs_1_wen_0 = io_ptw_7_customCSRs_csrs_1_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_7_customCSRs_csrs_1_wdata_0 = io_ptw_7_customCSRs_csrs_1_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_7_customCSRs_csrs_1_value_0 = io_ptw_7_customCSRs_csrs_1_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_customCSRs_csrs_2_ren_0 = io_ptw_7_customCSRs_csrs_2_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_customCSRs_csrs_2_wen_0 = io_ptw_7_customCSRs_csrs_2_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_7_customCSRs_csrs_2_wdata_0 = io_ptw_7_customCSRs_csrs_2_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_7_customCSRs_csrs_2_value_0 = io_ptw_7_customCSRs_csrs_2_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_customCSRs_csrs_3_ren_0 = io_ptw_7_customCSRs_csrs_3_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_customCSRs_csrs_3_wen_0 = io_ptw_7_customCSRs_csrs_3_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_7_customCSRs_csrs_3_wdata_0 = io_ptw_7_customCSRs_csrs_3_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_7_customCSRs_csrs_3_value_0 = io_ptw_7_customCSRs_csrs_3_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_req_ready_0 = io_ptw_8_req_ready; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_resp_valid_0 = io_ptw_8_resp_valid; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_resp_bits_ae_ptw_0 = io_ptw_8_resp_bits_ae_ptw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_resp_bits_ae_final_0 = io_ptw_8_resp_bits_ae_final; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_resp_bits_pf_0 = io_ptw_8_resp_bits_pf; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_resp_bits_gf_0 = io_ptw_8_resp_bits_gf; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_resp_bits_hr_0 = io_ptw_8_resp_bits_hr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_resp_bits_hw_0 = io_ptw_8_resp_bits_hw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_resp_bits_hx_0 = io_ptw_8_resp_bits_hx; // @[ZstdCompressor.scala:95:7]
wire [9:0] io_ptw_8_resp_bits_pte_reserved_for_future_0 = io_ptw_8_resp_bits_pte_reserved_for_future; // @[ZstdCompressor.scala:95:7]
wire [43:0] io_ptw_8_resp_bits_pte_ppn_0 = io_ptw_8_resp_bits_pte_ppn; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_8_resp_bits_pte_reserved_for_software_0 = io_ptw_8_resp_bits_pte_reserved_for_software; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_resp_bits_pte_d_0 = io_ptw_8_resp_bits_pte_d; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_resp_bits_pte_a_0 = io_ptw_8_resp_bits_pte_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_resp_bits_pte_g_0 = io_ptw_8_resp_bits_pte_g; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_resp_bits_pte_u_0 = io_ptw_8_resp_bits_pte_u; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_resp_bits_pte_x_0 = io_ptw_8_resp_bits_pte_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_resp_bits_pte_w_0 = io_ptw_8_resp_bits_pte_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_resp_bits_pte_r_0 = io_ptw_8_resp_bits_pte_r; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_resp_bits_pte_v_0 = io_ptw_8_resp_bits_pte_v; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_8_resp_bits_level_0 = io_ptw_8_resp_bits_level; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_resp_bits_homogeneous_0 = io_ptw_8_resp_bits_homogeneous; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_resp_bits_gpa_valid_0 = io_ptw_8_resp_bits_gpa_valid; // @[ZstdCompressor.scala:95:7]
wire [38:0] io_ptw_8_resp_bits_gpa_bits_0 = io_ptw_8_resp_bits_gpa_bits; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_resp_bits_gpa_is_pte_0 = io_ptw_8_resp_bits_gpa_is_pte; // @[ZstdCompressor.scala:95:7]
wire [3:0] io_ptw_8_ptbr_mode_0 = io_ptw_8_ptbr_mode; // @[ZstdCompressor.scala:95:7]
wire [43:0] io_ptw_8_ptbr_ppn_0 = io_ptw_8_ptbr_ppn; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_status_debug_0 = io_ptw_8_status_debug; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_status_cease_0 = io_ptw_8_status_cease; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_status_wfi_0 = io_ptw_8_status_wfi; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_8_status_isa_0 = io_ptw_8_status_isa; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_8_status_dprv_0 = io_ptw_8_status_dprv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_status_dv_0 = io_ptw_8_status_dv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_8_status_prv_0 = io_ptw_8_status_prv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_status_v_0 = io_ptw_8_status_v; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_status_mpv_0 = io_ptw_8_status_mpv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_status_gva_0 = io_ptw_8_status_gva; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_status_tsr_0 = io_ptw_8_status_tsr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_status_tw_0 = io_ptw_8_status_tw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_status_tvm_0 = io_ptw_8_status_tvm; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_status_mxr_0 = io_ptw_8_status_mxr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_status_sum_0 = io_ptw_8_status_sum; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_status_mprv_0 = io_ptw_8_status_mprv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_8_status_fs_0 = io_ptw_8_status_fs; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_8_status_mpp_0 = io_ptw_8_status_mpp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_status_spp_0 = io_ptw_8_status_spp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_status_mpie_0 = io_ptw_8_status_mpie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_status_spie_0 = io_ptw_8_status_spie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_status_mie_0 = io_ptw_8_status_mie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_status_sie_0 = io_ptw_8_status_sie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_hstatus_spvp_0 = io_ptw_8_hstatus_spvp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_hstatus_spv_0 = io_ptw_8_hstatus_spv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_hstatus_gva_0 = io_ptw_8_hstatus_gva; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_gstatus_debug_0 = io_ptw_8_gstatus_debug; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_gstatus_cease_0 = io_ptw_8_gstatus_cease; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_gstatus_wfi_0 = io_ptw_8_gstatus_wfi; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_8_gstatus_isa_0 = io_ptw_8_gstatus_isa; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_8_gstatus_dprv_0 = io_ptw_8_gstatus_dprv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_gstatus_dv_0 = io_ptw_8_gstatus_dv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_8_gstatus_prv_0 = io_ptw_8_gstatus_prv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_gstatus_v_0 = io_ptw_8_gstatus_v; // @[ZstdCompressor.scala:95:7]
wire [22:0] io_ptw_8_gstatus_zero2_0 = io_ptw_8_gstatus_zero2; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_gstatus_mpv_0 = io_ptw_8_gstatus_mpv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_gstatus_gva_0 = io_ptw_8_gstatus_gva; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_gstatus_mbe_0 = io_ptw_8_gstatus_mbe; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_gstatus_sbe_0 = io_ptw_8_gstatus_sbe; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_8_gstatus_sxl_0 = io_ptw_8_gstatus_sxl; // @[ZstdCompressor.scala:95:7]
wire [7:0] io_ptw_8_gstatus_zero1_0 = io_ptw_8_gstatus_zero1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_gstatus_tsr_0 = io_ptw_8_gstatus_tsr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_gstatus_tw_0 = io_ptw_8_gstatus_tw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_gstatus_tvm_0 = io_ptw_8_gstatus_tvm; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_gstatus_mxr_0 = io_ptw_8_gstatus_mxr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_gstatus_sum_0 = io_ptw_8_gstatus_sum; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_gstatus_mprv_0 = io_ptw_8_gstatus_mprv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_8_gstatus_fs_0 = io_ptw_8_gstatus_fs; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_8_gstatus_mpp_0 = io_ptw_8_gstatus_mpp; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_8_gstatus_vs_0 = io_ptw_8_gstatus_vs; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_gstatus_spp_0 = io_ptw_8_gstatus_spp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_gstatus_mpie_0 = io_ptw_8_gstatus_mpie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_gstatus_ube_0 = io_ptw_8_gstatus_ube; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_gstatus_spie_0 = io_ptw_8_gstatus_spie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_gstatus_upie_0 = io_ptw_8_gstatus_upie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_gstatus_mie_0 = io_ptw_8_gstatus_mie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_gstatus_hie_0 = io_ptw_8_gstatus_hie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_gstatus_sie_0 = io_ptw_8_gstatus_sie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_gstatus_uie_0 = io_ptw_8_gstatus_uie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_pmp_0_cfg_l_0 = io_ptw_8_pmp_0_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_8_pmp_0_cfg_a_0 = io_ptw_8_pmp_0_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_pmp_0_cfg_x_0 = io_ptw_8_pmp_0_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_pmp_0_cfg_w_0 = io_ptw_8_pmp_0_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_pmp_0_cfg_r_0 = io_ptw_8_pmp_0_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_8_pmp_0_addr_0 = io_ptw_8_pmp_0_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_8_pmp_0_mask_0 = io_ptw_8_pmp_0_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_pmp_1_cfg_l_0 = io_ptw_8_pmp_1_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_8_pmp_1_cfg_a_0 = io_ptw_8_pmp_1_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_pmp_1_cfg_x_0 = io_ptw_8_pmp_1_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_pmp_1_cfg_w_0 = io_ptw_8_pmp_1_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_pmp_1_cfg_r_0 = io_ptw_8_pmp_1_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_8_pmp_1_addr_0 = io_ptw_8_pmp_1_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_8_pmp_1_mask_0 = io_ptw_8_pmp_1_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_pmp_2_cfg_l_0 = io_ptw_8_pmp_2_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_8_pmp_2_cfg_a_0 = io_ptw_8_pmp_2_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_pmp_2_cfg_x_0 = io_ptw_8_pmp_2_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_pmp_2_cfg_w_0 = io_ptw_8_pmp_2_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_pmp_2_cfg_r_0 = io_ptw_8_pmp_2_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_8_pmp_2_addr_0 = io_ptw_8_pmp_2_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_8_pmp_2_mask_0 = io_ptw_8_pmp_2_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_pmp_3_cfg_l_0 = io_ptw_8_pmp_3_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_8_pmp_3_cfg_a_0 = io_ptw_8_pmp_3_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_pmp_3_cfg_x_0 = io_ptw_8_pmp_3_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_pmp_3_cfg_w_0 = io_ptw_8_pmp_3_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_pmp_3_cfg_r_0 = io_ptw_8_pmp_3_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_8_pmp_3_addr_0 = io_ptw_8_pmp_3_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_8_pmp_3_mask_0 = io_ptw_8_pmp_3_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_pmp_4_cfg_l_0 = io_ptw_8_pmp_4_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_8_pmp_4_cfg_a_0 = io_ptw_8_pmp_4_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_pmp_4_cfg_x_0 = io_ptw_8_pmp_4_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_pmp_4_cfg_w_0 = io_ptw_8_pmp_4_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_pmp_4_cfg_r_0 = io_ptw_8_pmp_4_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_8_pmp_4_addr_0 = io_ptw_8_pmp_4_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_8_pmp_4_mask_0 = io_ptw_8_pmp_4_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_pmp_5_cfg_l_0 = io_ptw_8_pmp_5_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_8_pmp_5_cfg_a_0 = io_ptw_8_pmp_5_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_pmp_5_cfg_x_0 = io_ptw_8_pmp_5_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_pmp_5_cfg_w_0 = io_ptw_8_pmp_5_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_pmp_5_cfg_r_0 = io_ptw_8_pmp_5_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_8_pmp_5_addr_0 = io_ptw_8_pmp_5_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_8_pmp_5_mask_0 = io_ptw_8_pmp_5_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_pmp_6_cfg_l_0 = io_ptw_8_pmp_6_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_8_pmp_6_cfg_a_0 = io_ptw_8_pmp_6_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_pmp_6_cfg_x_0 = io_ptw_8_pmp_6_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_pmp_6_cfg_w_0 = io_ptw_8_pmp_6_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_pmp_6_cfg_r_0 = io_ptw_8_pmp_6_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_8_pmp_6_addr_0 = io_ptw_8_pmp_6_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_8_pmp_6_mask_0 = io_ptw_8_pmp_6_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_pmp_7_cfg_l_0 = io_ptw_8_pmp_7_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_8_pmp_7_cfg_a_0 = io_ptw_8_pmp_7_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_pmp_7_cfg_x_0 = io_ptw_8_pmp_7_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_pmp_7_cfg_w_0 = io_ptw_8_pmp_7_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_pmp_7_cfg_r_0 = io_ptw_8_pmp_7_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_8_pmp_7_addr_0 = io_ptw_8_pmp_7_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_8_pmp_7_mask_0 = io_ptw_8_pmp_7_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_customCSRs_csrs_0_ren_0 = io_ptw_8_customCSRs_csrs_0_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_customCSRs_csrs_0_wen_0 = io_ptw_8_customCSRs_csrs_0_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_8_customCSRs_csrs_0_wdata_0 = io_ptw_8_customCSRs_csrs_0_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_8_customCSRs_csrs_0_value_0 = io_ptw_8_customCSRs_csrs_0_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_customCSRs_csrs_1_ren_0 = io_ptw_8_customCSRs_csrs_1_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_customCSRs_csrs_1_wen_0 = io_ptw_8_customCSRs_csrs_1_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_8_customCSRs_csrs_1_wdata_0 = io_ptw_8_customCSRs_csrs_1_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_8_customCSRs_csrs_1_value_0 = io_ptw_8_customCSRs_csrs_1_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_customCSRs_csrs_2_ren_0 = io_ptw_8_customCSRs_csrs_2_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_customCSRs_csrs_2_wen_0 = io_ptw_8_customCSRs_csrs_2_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_8_customCSRs_csrs_2_wdata_0 = io_ptw_8_customCSRs_csrs_2_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_8_customCSRs_csrs_2_value_0 = io_ptw_8_customCSRs_csrs_2_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_customCSRs_csrs_3_ren_0 = io_ptw_8_customCSRs_csrs_3_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_customCSRs_csrs_3_wen_0 = io_ptw_8_customCSRs_csrs_3_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_8_customCSRs_csrs_3_wdata_0 = io_ptw_8_customCSRs_csrs_3_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_8_customCSRs_csrs_3_value_0 = io_ptw_8_customCSRs_csrs_3_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_req_ready_0 = io_ptw_9_req_ready; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_resp_valid_0 = io_ptw_9_resp_valid; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_resp_bits_ae_ptw_0 = io_ptw_9_resp_bits_ae_ptw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_resp_bits_ae_final_0 = io_ptw_9_resp_bits_ae_final; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_resp_bits_pf_0 = io_ptw_9_resp_bits_pf; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_resp_bits_gf_0 = io_ptw_9_resp_bits_gf; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_resp_bits_hr_0 = io_ptw_9_resp_bits_hr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_resp_bits_hw_0 = io_ptw_9_resp_bits_hw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_resp_bits_hx_0 = io_ptw_9_resp_bits_hx; // @[ZstdCompressor.scala:95:7]
wire [9:0] io_ptw_9_resp_bits_pte_reserved_for_future_0 = io_ptw_9_resp_bits_pte_reserved_for_future; // @[ZstdCompressor.scala:95:7]
wire [43:0] io_ptw_9_resp_bits_pte_ppn_0 = io_ptw_9_resp_bits_pte_ppn; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_9_resp_bits_pte_reserved_for_software_0 = io_ptw_9_resp_bits_pte_reserved_for_software; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_resp_bits_pte_d_0 = io_ptw_9_resp_bits_pte_d; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_resp_bits_pte_a_0 = io_ptw_9_resp_bits_pte_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_resp_bits_pte_g_0 = io_ptw_9_resp_bits_pte_g; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_resp_bits_pte_u_0 = io_ptw_9_resp_bits_pte_u; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_resp_bits_pte_x_0 = io_ptw_9_resp_bits_pte_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_resp_bits_pte_w_0 = io_ptw_9_resp_bits_pte_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_resp_bits_pte_r_0 = io_ptw_9_resp_bits_pte_r; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_resp_bits_pte_v_0 = io_ptw_9_resp_bits_pte_v; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_9_resp_bits_level_0 = io_ptw_9_resp_bits_level; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_resp_bits_homogeneous_0 = io_ptw_9_resp_bits_homogeneous; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_resp_bits_gpa_valid_0 = io_ptw_9_resp_bits_gpa_valid; // @[ZstdCompressor.scala:95:7]
wire [38:0] io_ptw_9_resp_bits_gpa_bits_0 = io_ptw_9_resp_bits_gpa_bits; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_resp_bits_gpa_is_pte_0 = io_ptw_9_resp_bits_gpa_is_pte; // @[ZstdCompressor.scala:95:7]
wire [3:0] io_ptw_9_ptbr_mode_0 = io_ptw_9_ptbr_mode; // @[ZstdCompressor.scala:95:7]
wire [43:0] io_ptw_9_ptbr_ppn_0 = io_ptw_9_ptbr_ppn; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_status_debug_0 = io_ptw_9_status_debug; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_status_cease_0 = io_ptw_9_status_cease; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_status_wfi_0 = io_ptw_9_status_wfi; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_9_status_isa_0 = io_ptw_9_status_isa; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_9_status_dprv_0 = io_ptw_9_status_dprv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_status_dv_0 = io_ptw_9_status_dv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_9_status_prv_0 = io_ptw_9_status_prv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_status_v_0 = io_ptw_9_status_v; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_status_mpv_0 = io_ptw_9_status_mpv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_status_gva_0 = io_ptw_9_status_gva; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_status_tsr_0 = io_ptw_9_status_tsr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_status_tw_0 = io_ptw_9_status_tw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_status_tvm_0 = io_ptw_9_status_tvm; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_status_mxr_0 = io_ptw_9_status_mxr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_status_sum_0 = io_ptw_9_status_sum; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_status_mprv_0 = io_ptw_9_status_mprv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_9_status_fs_0 = io_ptw_9_status_fs; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_9_status_mpp_0 = io_ptw_9_status_mpp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_status_spp_0 = io_ptw_9_status_spp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_status_mpie_0 = io_ptw_9_status_mpie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_status_spie_0 = io_ptw_9_status_spie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_status_mie_0 = io_ptw_9_status_mie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_status_sie_0 = io_ptw_9_status_sie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_hstatus_spvp_0 = io_ptw_9_hstatus_spvp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_hstatus_spv_0 = io_ptw_9_hstatus_spv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_hstatus_gva_0 = io_ptw_9_hstatus_gva; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_gstatus_debug_0 = io_ptw_9_gstatus_debug; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_gstatus_cease_0 = io_ptw_9_gstatus_cease; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_gstatus_wfi_0 = io_ptw_9_gstatus_wfi; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_9_gstatus_isa_0 = io_ptw_9_gstatus_isa; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_9_gstatus_dprv_0 = io_ptw_9_gstatus_dprv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_gstatus_dv_0 = io_ptw_9_gstatus_dv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_9_gstatus_prv_0 = io_ptw_9_gstatus_prv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_gstatus_v_0 = io_ptw_9_gstatus_v; // @[ZstdCompressor.scala:95:7]
wire [22:0] io_ptw_9_gstatus_zero2_0 = io_ptw_9_gstatus_zero2; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_gstatus_mpv_0 = io_ptw_9_gstatus_mpv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_gstatus_gva_0 = io_ptw_9_gstatus_gva; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_gstatus_mbe_0 = io_ptw_9_gstatus_mbe; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_gstatus_sbe_0 = io_ptw_9_gstatus_sbe; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_9_gstatus_sxl_0 = io_ptw_9_gstatus_sxl; // @[ZstdCompressor.scala:95:7]
wire [7:0] io_ptw_9_gstatus_zero1_0 = io_ptw_9_gstatus_zero1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_gstatus_tsr_0 = io_ptw_9_gstatus_tsr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_gstatus_tw_0 = io_ptw_9_gstatus_tw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_gstatus_tvm_0 = io_ptw_9_gstatus_tvm; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_gstatus_mxr_0 = io_ptw_9_gstatus_mxr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_gstatus_sum_0 = io_ptw_9_gstatus_sum; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_gstatus_mprv_0 = io_ptw_9_gstatus_mprv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_9_gstatus_fs_0 = io_ptw_9_gstatus_fs; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_9_gstatus_mpp_0 = io_ptw_9_gstatus_mpp; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_9_gstatus_vs_0 = io_ptw_9_gstatus_vs; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_gstatus_spp_0 = io_ptw_9_gstatus_spp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_gstatus_mpie_0 = io_ptw_9_gstatus_mpie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_gstatus_ube_0 = io_ptw_9_gstatus_ube; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_gstatus_spie_0 = io_ptw_9_gstatus_spie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_gstatus_upie_0 = io_ptw_9_gstatus_upie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_gstatus_mie_0 = io_ptw_9_gstatus_mie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_gstatus_hie_0 = io_ptw_9_gstatus_hie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_gstatus_sie_0 = io_ptw_9_gstatus_sie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_gstatus_uie_0 = io_ptw_9_gstatus_uie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_pmp_0_cfg_l_0 = io_ptw_9_pmp_0_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_9_pmp_0_cfg_a_0 = io_ptw_9_pmp_0_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_pmp_0_cfg_x_0 = io_ptw_9_pmp_0_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_pmp_0_cfg_w_0 = io_ptw_9_pmp_0_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_pmp_0_cfg_r_0 = io_ptw_9_pmp_0_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_9_pmp_0_addr_0 = io_ptw_9_pmp_0_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_9_pmp_0_mask_0 = io_ptw_9_pmp_0_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_pmp_1_cfg_l_0 = io_ptw_9_pmp_1_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_9_pmp_1_cfg_a_0 = io_ptw_9_pmp_1_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_pmp_1_cfg_x_0 = io_ptw_9_pmp_1_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_pmp_1_cfg_w_0 = io_ptw_9_pmp_1_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_pmp_1_cfg_r_0 = io_ptw_9_pmp_1_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_9_pmp_1_addr_0 = io_ptw_9_pmp_1_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_9_pmp_1_mask_0 = io_ptw_9_pmp_1_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_pmp_2_cfg_l_0 = io_ptw_9_pmp_2_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_9_pmp_2_cfg_a_0 = io_ptw_9_pmp_2_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_pmp_2_cfg_x_0 = io_ptw_9_pmp_2_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_pmp_2_cfg_w_0 = io_ptw_9_pmp_2_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_pmp_2_cfg_r_0 = io_ptw_9_pmp_2_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_9_pmp_2_addr_0 = io_ptw_9_pmp_2_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_9_pmp_2_mask_0 = io_ptw_9_pmp_2_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_pmp_3_cfg_l_0 = io_ptw_9_pmp_3_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_9_pmp_3_cfg_a_0 = io_ptw_9_pmp_3_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_pmp_3_cfg_x_0 = io_ptw_9_pmp_3_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_pmp_3_cfg_w_0 = io_ptw_9_pmp_3_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_pmp_3_cfg_r_0 = io_ptw_9_pmp_3_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_9_pmp_3_addr_0 = io_ptw_9_pmp_3_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_9_pmp_3_mask_0 = io_ptw_9_pmp_3_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_pmp_4_cfg_l_0 = io_ptw_9_pmp_4_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_9_pmp_4_cfg_a_0 = io_ptw_9_pmp_4_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_pmp_4_cfg_x_0 = io_ptw_9_pmp_4_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_pmp_4_cfg_w_0 = io_ptw_9_pmp_4_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_pmp_4_cfg_r_0 = io_ptw_9_pmp_4_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_9_pmp_4_addr_0 = io_ptw_9_pmp_4_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_9_pmp_4_mask_0 = io_ptw_9_pmp_4_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_pmp_5_cfg_l_0 = io_ptw_9_pmp_5_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_9_pmp_5_cfg_a_0 = io_ptw_9_pmp_5_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_pmp_5_cfg_x_0 = io_ptw_9_pmp_5_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_pmp_5_cfg_w_0 = io_ptw_9_pmp_5_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_pmp_5_cfg_r_0 = io_ptw_9_pmp_5_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_9_pmp_5_addr_0 = io_ptw_9_pmp_5_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_9_pmp_5_mask_0 = io_ptw_9_pmp_5_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_pmp_6_cfg_l_0 = io_ptw_9_pmp_6_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_9_pmp_6_cfg_a_0 = io_ptw_9_pmp_6_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_pmp_6_cfg_x_0 = io_ptw_9_pmp_6_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_pmp_6_cfg_w_0 = io_ptw_9_pmp_6_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_pmp_6_cfg_r_0 = io_ptw_9_pmp_6_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_9_pmp_6_addr_0 = io_ptw_9_pmp_6_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_9_pmp_6_mask_0 = io_ptw_9_pmp_6_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_pmp_7_cfg_l_0 = io_ptw_9_pmp_7_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_9_pmp_7_cfg_a_0 = io_ptw_9_pmp_7_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_pmp_7_cfg_x_0 = io_ptw_9_pmp_7_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_pmp_7_cfg_w_0 = io_ptw_9_pmp_7_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_pmp_7_cfg_r_0 = io_ptw_9_pmp_7_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_9_pmp_7_addr_0 = io_ptw_9_pmp_7_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_9_pmp_7_mask_0 = io_ptw_9_pmp_7_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_customCSRs_csrs_0_ren_0 = io_ptw_9_customCSRs_csrs_0_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_customCSRs_csrs_0_wen_0 = io_ptw_9_customCSRs_csrs_0_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_9_customCSRs_csrs_0_wdata_0 = io_ptw_9_customCSRs_csrs_0_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_9_customCSRs_csrs_0_value_0 = io_ptw_9_customCSRs_csrs_0_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_customCSRs_csrs_1_ren_0 = io_ptw_9_customCSRs_csrs_1_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_customCSRs_csrs_1_wen_0 = io_ptw_9_customCSRs_csrs_1_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_9_customCSRs_csrs_1_wdata_0 = io_ptw_9_customCSRs_csrs_1_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_9_customCSRs_csrs_1_value_0 = io_ptw_9_customCSRs_csrs_1_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_customCSRs_csrs_2_ren_0 = io_ptw_9_customCSRs_csrs_2_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_customCSRs_csrs_2_wen_0 = io_ptw_9_customCSRs_csrs_2_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_9_customCSRs_csrs_2_wdata_0 = io_ptw_9_customCSRs_csrs_2_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_9_customCSRs_csrs_2_value_0 = io_ptw_9_customCSRs_csrs_2_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_customCSRs_csrs_3_ren_0 = io_ptw_9_customCSRs_csrs_3_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_customCSRs_csrs_3_wen_0 = io_ptw_9_customCSRs_csrs_3_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_9_customCSRs_csrs_3_wdata_0 = io_ptw_9_customCSRs_csrs_3_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_9_customCSRs_csrs_3_value_0 = io_ptw_9_customCSRs_csrs_3_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_req_ready_0 = io_ptw_10_req_ready; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_resp_valid_0 = io_ptw_10_resp_valid; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_resp_bits_ae_ptw_0 = io_ptw_10_resp_bits_ae_ptw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_resp_bits_ae_final_0 = io_ptw_10_resp_bits_ae_final; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_resp_bits_pf_0 = io_ptw_10_resp_bits_pf; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_resp_bits_gf_0 = io_ptw_10_resp_bits_gf; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_resp_bits_hr_0 = io_ptw_10_resp_bits_hr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_resp_bits_hw_0 = io_ptw_10_resp_bits_hw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_resp_bits_hx_0 = io_ptw_10_resp_bits_hx; // @[ZstdCompressor.scala:95:7]
wire [9:0] io_ptw_10_resp_bits_pte_reserved_for_future_0 = io_ptw_10_resp_bits_pte_reserved_for_future; // @[ZstdCompressor.scala:95:7]
wire [43:0] io_ptw_10_resp_bits_pte_ppn_0 = io_ptw_10_resp_bits_pte_ppn; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_10_resp_bits_pte_reserved_for_software_0 = io_ptw_10_resp_bits_pte_reserved_for_software; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_resp_bits_pte_d_0 = io_ptw_10_resp_bits_pte_d; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_resp_bits_pte_a_0 = io_ptw_10_resp_bits_pte_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_resp_bits_pte_g_0 = io_ptw_10_resp_bits_pte_g; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_resp_bits_pte_u_0 = io_ptw_10_resp_bits_pte_u; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_resp_bits_pte_x_0 = io_ptw_10_resp_bits_pte_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_resp_bits_pte_w_0 = io_ptw_10_resp_bits_pte_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_resp_bits_pte_r_0 = io_ptw_10_resp_bits_pte_r; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_resp_bits_pte_v_0 = io_ptw_10_resp_bits_pte_v; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_10_resp_bits_level_0 = io_ptw_10_resp_bits_level; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_resp_bits_homogeneous_0 = io_ptw_10_resp_bits_homogeneous; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_resp_bits_gpa_valid_0 = io_ptw_10_resp_bits_gpa_valid; // @[ZstdCompressor.scala:95:7]
wire [38:0] io_ptw_10_resp_bits_gpa_bits_0 = io_ptw_10_resp_bits_gpa_bits; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_resp_bits_gpa_is_pte_0 = io_ptw_10_resp_bits_gpa_is_pte; // @[ZstdCompressor.scala:95:7]
wire [3:0] io_ptw_10_ptbr_mode_0 = io_ptw_10_ptbr_mode; // @[ZstdCompressor.scala:95:7]
wire [43:0] io_ptw_10_ptbr_ppn_0 = io_ptw_10_ptbr_ppn; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_status_debug_0 = io_ptw_10_status_debug; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_status_cease_0 = io_ptw_10_status_cease; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_status_wfi_0 = io_ptw_10_status_wfi; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_10_status_isa_0 = io_ptw_10_status_isa; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_10_status_dprv_0 = io_ptw_10_status_dprv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_status_dv_0 = io_ptw_10_status_dv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_10_status_prv_0 = io_ptw_10_status_prv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_status_v_0 = io_ptw_10_status_v; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_status_mpv_0 = io_ptw_10_status_mpv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_status_gva_0 = io_ptw_10_status_gva; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_status_tsr_0 = io_ptw_10_status_tsr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_status_tw_0 = io_ptw_10_status_tw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_status_tvm_0 = io_ptw_10_status_tvm; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_status_mxr_0 = io_ptw_10_status_mxr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_status_sum_0 = io_ptw_10_status_sum; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_status_mprv_0 = io_ptw_10_status_mprv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_10_status_fs_0 = io_ptw_10_status_fs; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_10_status_mpp_0 = io_ptw_10_status_mpp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_status_spp_0 = io_ptw_10_status_spp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_status_mpie_0 = io_ptw_10_status_mpie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_status_spie_0 = io_ptw_10_status_spie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_status_mie_0 = io_ptw_10_status_mie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_status_sie_0 = io_ptw_10_status_sie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_hstatus_spvp_0 = io_ptw_10_hstatus_spvp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_hstatus_spv_0 = io_ptw_10_hstatus_spv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_hstatus_gva_0 = io_ptw_10_hstatus_gva; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_gstatus_debug_0 = io_ptw_10_gstatus_debug; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_gstatus_cease_0 = io_ptw_10_gstatus_cease; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_gstatus_wfi_0 = io_ptw_10_gstatus_wfi; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_10_gstatus_isa_0 = io_ptw_10_gstatus_isa; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_10_gstatus_dprv_0 = io_ptw_10_gstatus_dprv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_gstatus_dv_0 = io_ptw_10_gstatus_dv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_10_gstatus_prv_0 = io_ptw_10_gstatus_prv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_gstatus_v_0 = io_ptw_10_gstatus_v; // @[ZstdCompressor.scala:95:7]
wire [22:0] io_ptw_10_gstatus_zero2_0 = io_ptw_10_gstatus_zero2; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_gstatus_mpv_0 = io_ptw_10_gstatus_mpv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_gstatus_gva_0 = io_ptw_10_gstatus_gva; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_gstatus_mbe_0 = io_ptw_10_gstatus_mbe; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_gstatus_sbe_0 = io_ptw_10_gstatus_sbe; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_10_gstatus_sxl_0 = io_ptw_10_gstatus_sxl; // @[ZstdCompressor.scala:95:7]
wire [7:0] io_ptw_10_gstatus_zero1_0 = io_ptw_10_gstatus_zero1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_gstatus_tsr_0 = io_ptw_10_gstatus_tsr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_gstatus_tw_0 = io_ptw_10_gstatus_tw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_gstatus_tvm_0 = io_ptw_10_gstatus_tvm; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_gstatus_mxr_0 = io_ptw_10_gstatus_mxr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_gstatus_sum_0 = io_ptw_10_gstatus_sum; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_gstatus_mprv_0 = io_ptw_10_gstatus_mprv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_10_gstatus_fs_0 = io_ptw_10_gstatus_fs; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_10_gstatus_mpp_0 = io_ptw_10_gstatus_mpp; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_10_gstatus_vs_0 = io_ptw_10_gstatus_vs; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_gstatus_spp_0 = io_ptw_10_gstatus_spp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_gstatus_mpie_0 = io_ptw_10_gstatus_mpie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_gstatus_ube_0 = io_ptw_10_gstatus_ube; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_gstatus_spie_0 = io_ptw_10_gstatus_spie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_gstatus_upie_0 = io_ptw_10_gstatus_upie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_gstatus_mie_0 = io_ptw_10_gstatus_mie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_gstatus_hie_0 = io_ptw_10_gstatus_hie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_gstatus_sie_0 = io_ptw_10_gstatus_sie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_gstatus_uie_0 = io_ptw_10_gstatus_uie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_pmp_0_cfg_l_0 = io_ptw_10_pmp_0_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_10_pmp_0_cfg_a_0 = io_ptw_10_pmp_0_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_pmp_0_cfg_x_0 = io_ptw_10_pmp_0_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_pmp_0_cfg_w_0 = io_ptw_10_pmp_0_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_pmp_0_cfg_r_0 = io_ptw_10_pmp_0_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_10_pmp_0_addr_0 = io_ptw_10_pmp_0_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_10_pmp_0_mask_0 = io_ptw_10_pmp_0_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_pmp_1_cfg_l_0 = io_ptw_10_pmp_1_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_10_pmp_1_cfg_a_0 = io_ptw_10_pmp_1_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_pmp_1_cfg_x_0 = io_ptw_10_pmp_1_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_pmp_1_cfg_w_0 = io_ptw_10_pmp_1_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_pmp_1_cfg_r_0 = io_ptw_10_pmp_1_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_10_pmp_1_addr_0 = io_ptw_10_pmp_1_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_10_pmp_1_mask_0 = io_ptw_10_pmp_1_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_pmp_2_cfg_l_0 = io_ptw_10_pmp_2_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_10_pmp_2_cfg_a_0 = io_ptw_10_pmp_2_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_pmp_2_cfg_x_0 = io_ptw_10_pmp_2_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_pmp_2_cfg_w_0 = io_ptw_10_pmp_2_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_pmp_2_cfg_r_0 = io_ptw_10_pmp_2_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_10_pmp_2_addr_0 = io_ptw_10_pmp_2_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_10_pmp_2_mask_0 = io_ptw_10_pmp_2_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_pmp_3_cfg_l_0 = io_ptw_10_pmp_3_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_10_pmp_3_cfg_a_0 = io_ptw_10_pmp_3_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_pmp_3_cfg_x_0 = io_ptw_10_pmp_3_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_pmp_3_cfg_w_0 = io_ptw_10_pmp_3_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_pmp_3_cfg_r_0 = io_ptw_10_pmp_3_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_10_pmp_3_addr_0 = io_ptw_10_pmp_3_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_10_pmp_3_mask_0 = io_ptw_10_pmp_3_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_pmp_4_cfg_l_0 = io_ptw_10_pmp_4_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_10_pmp_4_cfg_a_0 = io_ptw_10_pmp_4_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_pmp_4_cfg_x_0 = io_ptw_10_pmp_4_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_pmp_4_cfg_w_0 = io_ptw_10_pmp_4_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_pmp_4_cfg_r_0 = io_ptw_10_pmp_4_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_10_pmp_4_addr_0 = io_ptw_10_pmp_4_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_10_pmp_4_mask_0 = io_ptw_10_pmp_4_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_pmp_5_cfg_l_0 = io_ptw_10_pmp_5_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_10_pmp_5_cfg_a_0 = io_ptw_10_pmp_5_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_pmp_5_cfg_x_0 = io_ptw_10_pmp_5_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_pmp_5_cfg_w_0 = io_ptw_10_pmp_5_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_pmp_5_cfg_r_0 = io_ptw_10_pmp_5_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_10_pmp_5_addr_0 = io_ptw_10_pmp_5_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_10_pmp_5_mask_0 = io_ptw_10_pmp_5_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_pmp_6_cfg_l_0 = io_ptw_10_pmp_6_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_10_pmp_6_cfg_a_0 = io_ptw_10_pmp_6_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_pmp_6_cfg_x_0 = io_ptw_10_pmp_6_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_pmp_6_cfg_w_0 = io_ptw_10_pmp_6_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_pmp_6_cfg_r_0 = io_ptw_10_pmp_6_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_10_pmp_6_addr_0 = io_ptw_10_pmp_6_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_10_pmp_6_mask_0 = io_ptw_10_pmp_6_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_pmp_7_cfg_l_0 = io_ptw_10_pmp_7_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_10_pmp_7_cfg_a_0 = io_ptw_10_pmp_7_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_pmp_7_cfg_x_0 = io_ptw_10_pmp_7_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_pmp_7_cfg_w_0 = io_ptw_10_pmp_7_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_pmp_7_cfg_r_0 = io_ptw_10_pmp_7_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_10_pmp_7_addr_0 = io_ptw_10_pmp_7_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_10_pmp_7_mask_0 = io_ptw_10_pmp_7_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_customCSRs_csrs_0_ren_0 = io_ptw_10_customCSRs_csrs_0_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_customCSRs_csrs_0_wen_0 = io_ptw_10_customCSRs_csrs_0_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_10_customCSRs_csrs_0_wdata_0 = io_ptw_10_customCSRs_csrs_0_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_10_customCSRs_csrs_0_value_0 = io_ptw_10_customCSRs_csrs_0_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_customCSRs_csrs_1_ren_0 = io_ptw_10_customCSRs_csrs_1_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_customCSRs_csrs_1_wen_0 = io_ptw_10_customCSRs_csrs_1_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_10_customCSRs_csrs_1_wdata_0 = io_ptw_10_customCSRs_csrs_1_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_10_customCSRs_csrs_1_value_0 = io_ptw_10_customCSRs_csrs_1_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_customCSRs_csrs_2_ren_0 = io_ptw_10_customCSRs_csrs_2_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_customCSRs_csrs_2_wen_0 = io_ptw_10_customCSRs_csrs_2_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_10_customCSRs_csrs_2_wdata_0 = io_ptw_10_customCSRs_csrs_2_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_10_customCSRs_csrs_2_value_0 = io_ptw_10_customCSRs_csrs_2_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_customCSRs_csrs_3_ren_0 = io_ptw_10_customCSRs_csrs_3_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_customCSRs_csrs_3_wen_0 = io_ptw_10_customCSRs_csrs_3_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_10_customCSRs_csrs_3_wdata_0 = io_ptw_10_customCSRs_csrs_3_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_10_customCSRs_csrs_3_value_0 = io_ptw_10_customCSRs_csrs_3_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_req_ready_0 = io_ptw_11_req_ready; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_resp_valid_0 = io_ptw_11_resp_valid; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_resp_bits_ae_ptw_0 = io_ptw_11_resp_bits_ae_ptw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_resp_bits_ae_final_0 = io_ptw_11_resp_bits_ae_final; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_resp_bits_pf_0 = io_ptw_11_resp_bits_pf; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_resp_bits_gf_0 = io_ptw_11_resp_bits_gf; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_resp_bits_hr_0 = io_ptw_11_resp_bits_hr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_resp_bits_hw_0 = io_ptw_11_resp_bits_hw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_resp_bits_hx_0 = io_ptw_11_resp_bits_hx; // @[ZstdCompressor.scala:95:7]
wire [9:0] io_ptw_11_resp_bits_pte_reserved_for_future_0 = io_ptw_11_resp_bits_pte_reserved_for_future; // @[ZstdCompressor.scala:95:7]
wire [43:0] io_ptw_11_resp_bits_pte_ppn_0 = io_ptw_11_resp_bits_pte_ppn; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_11_resp_bits_pte_reserved_for_software_0 = io_ptw_11_resp_bits_pte_reserved_for_software; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_resp_bits_pte_d_0 = io_ptw_11_resp_bits_pte_d; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_resp_bits_pte_a_0 = io_ptw_11_resp_bits_pte_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_resp_bits_pte_g_0 = io_ptw_11_resp_bits_pte_g; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_resp_bits_pte_u_0 = io_ptw_11_resp_bits_pte_u; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_resp_bits_pte_x_0 = io_ptw_11_resp_bits_pte_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_resp_bits_pte_w_0 = io_ptw_11_resp_bits_pte_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_resp_bits_pte_r_0 = io_ptw_11_resp_bits_pte_r; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_resp_bits_pte_v_0 = io_ptw_11_resp_bits_pte_v; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_11_resp_bits_level_0 = io_ptw_11_resp_bits_level; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_resp_bits_homogeneous_0 = io_ptw_11_resp_bits_homogeneous; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_resp_bits_gpa_valid_0 = io_ptw_11_resp_bits_gpa_valid; // @[ZstdCompressor.scala:95:7]
wire [38:0] io_ptw_11_resp_bits_gpa_bits_0 = io_ptw_11_resp_bits_gpa_bits; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_resp_bits_gpa_is_pte_0 = io_ptw_11_resp_bits_gpa_is_pte; // @[ZstdCompressor.scala:95:7]
wire [3:0] io_ptw_11_ptbr_mode_0 = io_ptw_11_ptbr_mode; // @[ZstdCompressor.scala:95:7]
wire [43:0] io_ptw_11_ptbr_ppn_0 = io_ptw_11_ptbr_ppn; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_status_debug_0 = io_ptw_11_status_debug; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_status_cease_0 = io_ptw_11_status_cease; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_status_wfi_0 = io_ptw_11_status_wfi; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_11_status_isa_0 = io_ptw_11_status_isa; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_11_status_dprv_0 = io_ptw_11_status_dprv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_status_dv_0 = io_ptw_11_status_dv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_11_status_prv_0 = io_ptw_11_status_prv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_status_v_0 = io_ptw_11_status_v; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_status_mpv_0 = io_ptw_11_status_mpv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_status_gva_0 = io_ptw_11_status_gva; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_status_tsr_0 = io_ptw_11_status_tsr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_status_tw_0 = io_ptw_11_status_tw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_status_tvm_0 = io_ptw_11_status_tvm; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_status_mxr_0 = io_ptw_11_status_mxr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_status_sum_0 = io_ptw_11_status_sum; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_status_mprv_0 = io_ptw_11_status_mprv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_11_status_fs_0 = io_ptw_11_status_fs; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_11_status_mpp_0 = io_ptw_11_status_mpp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_status_spp_0 = io_ptw_11_status_spp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_status_mpie_0 = io_ptw_11_status_mpie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_status_spie_0 = io_ptw_11_status_spie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_status_mie_0 = io_ptw_11_status_mie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_status_sie_0 = io_ptw_11_status_sie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_hstatus_spvp_0 = io_ptw_11_hstatus_spvp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_hstatus_spv_0 = io_ptw_11_hstatus_spv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_hstatus_gva_0 = io_ptw_11_hstatus_gva; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_gstatus_debug_0 = io_ptw_11_gstatus_debug; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_gstatus_cease_0 = io_ptw_11_gstatus_cease; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_gstatus_wfi_0 = io_ptw_11_gstatus_wfi; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_11_gstatus_isa_0 = io_ptw_11_gstatus_isa; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_11_gstatus_dprv_0 = io_ptw_11_gstatus_dprv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_gstatus_dv_0 = io_ptw_11_gstatus_dv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_11_gstatus_prv_0 = io_ptw_11_gstatus_prv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_gstatus_v_0 = io_ptw_11_gstatus_v; // @[ZstdCompressor.scala:95:7]
wire [22:0] io_ptw_11_gstatus_zero2_0 = io_ptw_11_gstatus_zero2; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_gstatus_mpv_0 = io_ptw_11_gstatus_mpv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_gstatus_gva_0 = io_ptw_11_gstatus_gva; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_gstatus_mbe_0 = io_ptw_11_gstatus_mbe; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_gstatus_sbe_0 = io_ptw_11_gstatus_sbe; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_11_gstatus_sxl_0 = io_ptw_11_gstatus_sxl; // @[ZstdCompressor.scala:95:7]
wire [7:0] io_ptw_11_gstatus_zero1_0 = io_ptw_11_gstatus_zero1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_gstatus_tsr_0 = io_ptw_11_gstatus_tsr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_gstatus_tw_0 = io_ptw_11_gstatus_tw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_gstatus_tvm_0 = io_ptw_11_gstatus_tvm; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_gstatus_mxr_0 = io_ptw_11_gstatus_mxr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_gstatus_sum_0 = io_ptw_11_gstatus_sum; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_gstatus_mprv_0 = io_ptw_11_gstatus_mprv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_11_gstatus_fs_0 = io_ptw_11_gstatus_fs; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_11_gstatus_mpp_0 = io_ptw_11_gstatus_mpp; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_11_gstatus_vs_0 = io_ptw_11_gstatus_vs; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_gstatus_spp_0 = io_ptw_11_gstatus_spp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_gstatus_mpie_0 = io_ptw_11_gstatus_mpie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_gstatus_ube_0 = io_ptw_11_gstatus_ube; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_gstatus_spie_0 = io_ptw_11_gstatus_spie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_gstatus_upie_0 = io_ptw_11_gstatus_upie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_gstatus_mie_0 = io_ptw_11_gstatus_mie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_gstatus_hie_0 = io_ptw_11_gstatus_hie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_gstatus_sie_0 = io_ptw_11_gstatus_sie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_gstatus_uie_0 = io_ptw_11_gstatus_uie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_pmp_0_cfg_l_0 = io_ptw_11_pmp_0_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_11_pmp_0_cfg_a_0 = io_ptw_11_pmp_0_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_pmp_0_cfg_x_0 = io_ptw_11_pmp_0_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_pmp_0_cfg_w_0 = io_ptw_11_pmp_0_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_pmp_0_cfg_r_0 = io_ptw_11_pmp_0_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_11_pmp_0_addr_0 = io_ptw_11_pmp_0_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_11_pmp_0_mask_0 = io_ptw_11_pmp_0_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_pmp_1_cfg_l_0 = io_ptw_11_pmp_1_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_11_pmp_1_cfg_a_0 = io_ptw_11_pmp_1_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_pmp_1_cfg_x_0 = io_ptw_11_pmp_1_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_pmp_1_cfg_w_0 = io_ptw_11_pmp_1_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_pmp_1_cfg_r_0 = io_ptw_11_pmp_1_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_11_pmp_1_addr_0 = io_ptw_11_pmp_1_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_11_pmp_1_mask_0 = io_ptw_11_pmp_1_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_pmp_2_cfg_l_0 = io_ptw_11_pmp_2_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_11_pmp_2_cfg_a_0 = io_ptw_11_pmp_2_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_pmp_2_cfg_x_0 = io_ptw_11_pmp_2_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_pmp_2_cfg_w_0 = io_ptw_11_pmp_2_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_pmp_2_cfg_r_0 = io_ptw_11_pmp_2_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_11_pmp_2_addr_0 = io_ptw_11_pmp_2_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_11_pmp_2_mask_0 = io_ptw_11_pmp_2_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_pmp_3_cfg_l_0 = io_ptw_11_pmp_3_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_11_pmp_3_cfg_a_0 = io_ptw_11_pmp_3_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_pmp_3_cfg_x_0 = io_ptw_11_pmp_3_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_pmp_3_cfg_w_0 = io_ptw_11_pmp_3_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_pmp_3_cfg_r_0 = io_ptw_11_pmp_3_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_11_pmp_3_addr_0 = io_ptw_11_pmp_3_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_11_pmp_3_mask_0 = io_ptw_11_pmp_3_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_pmp_4_cfg_l_0 = io_ptw_11_pmp_4_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_11_pmp_4_cfg_a_0 = io_ptw_11_pmp_4_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_pmp_4_cfg_x_0 = io_ptw_11_pmp_4_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_pmp_4_cfg_w_0 = io_ptw_11_pmp_4_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_pmp_4_cfg_r_0 = io_ptw_11_pmp_4_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_11_pmp_4_addr_0 = io_ptw_11_pmp_4_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_11_pmp_4_mask_0 = io_ptw_11_pmp_4_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_pmp_5_cfg_l_0 = io_ptw_11_pmp_5_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_11_pmp_5_cfg_a_0 = io_ptw_11_pmp_5_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_pmp_5_cfg_x_0 = io_ptw_11_pmp_5_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_pmp_5_cfg_w_0 = io_ptw_11_pmp_5_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_pmp_5_cfg_r_0 = io_ptw_11_pmp_5_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_11_pmp_5_addr_0 = io_ptw_11_pmp_5_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_11_pmp_5_mask_0 = io_ptw_11_pmp_5_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_pmp_6_cfg_l_0 = io_ptw_11_pmp_6_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_11_pmp_6_cfg_a_0 = io_ptw_11_pmp_6_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_pmp_6_cfg_x_0 = io_ptw_11_pmp_6_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_pmp_6_cfg_w_0 = io_ptw_11_pmp_6_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_pmp_6_cfg_r_0 = io_ptw_11_pmp_6_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_11_pmp_6_addr_0 = io_ptw_11_pmp_6_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_11_pmp_6_mask_0 = io_ptw_11_pmp_6_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_pmp_7_cfg_l_0 = io_ptw_11_pmp_7_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_11_pmp_7_cfg_a_0 = io_ptw_11_pmp_7_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_pmp_7_cfg_x_0 = io_ptw_11_pmp_7_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_pmp_7_cfg_w_0 = io_ptw_11_pmp_7_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_pmp_7_cfg_r_0 = io_ptw_11_pmp_7_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_11_pmp_7_addr_0 = io_ptw_11_pmp_7_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_11_pmp_7_mask_0 = io_ptw_11_pmp_7_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_customCSRs_csrs_0_ren_0 = io_ptw_11_customCSRs_csrs_0_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_customCSRs_csrs_0_wen_0 = io_ptw_11_customCSRs_csrs_0_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_11_customCSRs_csrs_0_wdata_0 = io_ptw_11_customCSRs_csrs_0_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_11_customCSRs_csrs_0_value_0 = io_ptw_11_customCSRs_csrs_0_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_customCSRs_csrs_1_ren_0 = io_ptw_11_customCSRs_csrs_1_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_customCSRs_csrs_1_wen_0 = io_ptw_11_customCSRs_csrs_1_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_11_customCSRs_csrs_1_wdata_0 = io_ptw_11_customCSRs_csrs_1_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_11_customCSRs_csrs_1_value_0 = io_ptw_11_customCSRs_csrs_1_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_customCSRs_csrs_2_ren_0 = io_ptw_11_customCSRs_csrs_2_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_customCSRs_csrs_2_wen_0 = io_ptw_11_customCSRs_csrs_2_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_11_customCSRs_csrs_2_wdata_0 = io_ptw_11_customCSRs_csrs_2_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_11_customCSRs_csrs_2_value_0 = io_ptw_11_customCSRs_csrs_2_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_customCSRs_csrs_3_ren_0 = io_ptw_11_customCSRs_csrs_3_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_customCSRs_csrs_3_wen_0 = io_ptw_11_customCSRs_csrs_3_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_11_customCSRs_csrs_3_wdata_0 = io_ptw_11_customCSRs_csrs_3_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_11_customCSRs_csrs_3_value_0 = io_ptw_11_customCSRs_csrs_3_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_req_ready_0 = io_ptw_12_req_ready; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_resp_valid_0 = io_ptw_12_resp_valid; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_resp_bits_ae_ptw_0 = io_ptw_12_resp_bits_ae_ptw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_resp_bits_ae_final_0 = io_ptw_12_resp_bits_ae_final; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_resp_bits_pf_0 = io_ptw_12_resp_bits_pf; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_resp_bits_gf_0 = io_ptw_12_resp_bits_gf; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_resp_bits_hr_0 = io_ptw_12_resp_bits_hr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_resp_bits_hw_0 = io_ptw_12_resp_bits_hw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_resp_bits_hx_0 = io_ptw_12_resp_bits_hx; // @[ZstdCompressor.scala:95:7]
wire [9:0] io_ptw_12_resp_bits_pte_reserved_for_future_0 = io_ptw_12_resp_bits_pte_reserved_for_future; // @[ZstdCompressor.scala:95:7]
wire [43:0] io_ptw_12_resp_bits_pte_ppn_0 = io_ptw_12_resp_bits_pte_ppn; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_12_resp_bits_pte_reserved_for_software_0 = io_ptw_12_resp_bits_pte_reserved_for_software; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_resp_bits_pte_d_0 = io_ptw_12_resp_bits_pte_d; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_resp_bits_pte_a_0 = io_ptw_12_resp_bits_pte_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_resp_bits_pte_g_0 = io_ptw_12_resp_bits_pte_g; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_resp_bits_pte_u_0 = io_ptw_12_resp_bits_pte_u; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_resp_bits_pte_x_0 = io_ptw_12_resp_bits_pte_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_resp_bits_pte_w_0 = io_ptw_12_resp_bits_pte_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_resp_bits_pte_r_0 = io_ptw_12_resp_bits_pte_r; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_resp_bits_pte_v_0 = io_ptw_12_resp_bits_pte_v; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_12_resp_bits_level_0 = io_ptw_12_resp_bits_level; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_resp_bits_homogeneous_0 = io_ptw_12_resp_bits_homogeneous; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_resp_bits_gpa_valid_0 = io_ptw_12_resp_bits_gpa_valid; // @[ZstdCompressor.scala:95:7]
wire [38:0] io_ptw_12_resp_bits_gpa_bits_0 = io_ptw_12_resp_bits_gpa_bits; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_resp_bits_gpa_is_pte_0 = io_ptw_12_resp_bits_gpa_is_pte; // @[ZstdCompressor.scala:95:7]
wire [3:0] io_ptw_12_ptbr_mode_0 = io_ptw_12_ptbr_mode; // @[ZstdCompressor.scala:95:7]
wire [43:0] io_ptw_12_ptbr_ppn_0 = io_ptw_12_ptbr_ppn; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_status_debug_0 = io_ptw_12_status_debug; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_status_cease_0 = io_ptw_12_status_cease; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_status_wfi_0 = io_ptw_12_status_wfi; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_12_status_isa_0 = io_ptw_12_status_isa; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_12_status_dprv_0 = io_ptw_12_status_dprv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_status_dv_0 = io_ptw_12_status_dv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_12_status_prv_0 = io_ptw_12_status_prv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_status_v_0 = io_ptw_12_status_v; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_status_mpv_0 = io_ptw_12_status_mpv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_status_gva_0 = io_ptw_12_status_gva; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_status_tsr_0 = io_ptw_12_status_tsr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_status_tw_0 = io_ptw_12_status_tw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_status_tvm_0 = io_ptw_12_status_tvm; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_status_mxr_0 = io_ptw_12_status_mxr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_status_sum_0 = io_ptw_12_status_sum; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_status_mprv_0 = io_ptw_12_status_mprv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_12_status_fs_0 = io_ptw_12_status_fs; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_12_status_mpp_0 = io_ptw_12_status_mpp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_status_spp_0 = io_ptw_12_status_spp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_status_mpie_0 = io_ptw_12_status_mpie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_status_spie_0 = io_ptw_12_status_spie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_status_mie_0 = io_ptw_12_status_mie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_status_sie_0 = io_ptw_12_status_sie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_hstatus_spvp_0 = io_ptw_12_hstatus_spvp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_hstatus_spv_0 = io_ptw_12_hstatus_spv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_hstatus_gva_0 = io_ptw_12_hstatus_gva; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_gstatus_debug_0 = io_ptw_12_gstatus_debug; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_gstatus_cease_0 = io_ptw_12_gstatus_cease; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_gstatus_wfi_0 = io_ptw_12_gstatus_wfi; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_12_gstatus_isa_0 = io_ptw_12_gstatus_isa; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_12_gstatus_dprv_0 = io_ptw_12_gstatus_dprv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_gstatus_dv_0 = io_ptw_12_gstatus_dv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_12_gstatus_prv_0 = io_ptw_12_gstatus_prv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_gstatus_v_0 = io_ptw_12_gstatus_v; // @[ZstdCompressor.scala:95:7]
wire [22:0] io_ptw_12_gstatus_zero2_0 = io_ptw_12_gstatus_zero2; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_gstatus_mpv_0 = io_ptw_12_gstatus_mpv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_gstatus_gva_0 = io_ptw_12_gstatus_gva; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_gstatus_mbe_0 = io_ptw_12_gstatus_mbe; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_gstatus_sbe_0 = io_ptw_12_gstatus_sbe; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_12_gstatus_sxl_0 = io_ptw_12_gstatus_sxl; // @[ZstdCompressor.scala:95:7]
wire [7:0] io_ptw_12_gstatus_zero1_0 = io_ptw_12_gstatus_zero1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_gstatus_tsr_0 = io_ptw_12_gstatus_tsr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_gstatus_tw_0 = io_ptw_12_gstatus_tw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_gstatus_tvm_0 = io_ptw_12_gstatus_tvm; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_gstatus_mxr_0 = io_ptw_12_gstatus_mxr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_gstatus_sum_0 = io_ptw_12_gstatus_sum; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_gstatus_mprv_0 = io_ptw_12_gstatus_mprv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_12_gstatus_fs_0 = io_ptw_12_gstatus_fs; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_12_gstatus_mpp_0 = io_ptw_12_gstatus_mpp; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_12_gstatus_vs_0 = io_ptw_12_gstatus_vs; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_gstatus_spp_0 = io_ptw_12_gstatus_spp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_gstatus_mpie_0 = io_ptw_12_gstatus_mpie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_gstatus_ube_0 = io_ptw_12_gstatus_ube; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_gstatus_spie_0 = io_ptw_12_gstatus_spie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_gstatus_upie_0 = io_ptw_12_gstatus_upie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_gstatus_mie_0 = io_ptw_12_gstatus_mie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_gstatus_hie_0 = io_ptw_12_gstatus_hie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_gstatus_sie_0 = io_ptw_12_gstatus_sie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_gstatus_uie_0 = io_ptw_12_gstatus_uie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_pmp_0_cfg_l_0 = io_ptw_12_pmp_0_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_12_pmp_0_cfg_a_0 = io_ptw_12_pmp_0_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_pmp_0_cfg_x_0 = io_ptw_12_pmp_0_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_pmp_0_cfg_w_0 = io_ptw_12_pmp_0_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_pmp_0_cfg_r_0 = io_ptw_12_pmp_0_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_12_pmp_0_addr_0 = io_ptw_12_pmp_0_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_12_pmp_0_mask_0 = io_ptw_12_pmp_0_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_pmp_1_cfg_l_0 = io_ptw_12_pmp_1_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_12_pmp_1_cfg_a_0 = io_ptw_12_pmp_1_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_pmp_1_cfg_x_0 = io_ptw_12_pmp_1_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_pmp_1_cfg_w_0 = io_ptw_12_pmp_1_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_pmp_1_cfg_r_0 = io_ptw_12_pmp_1_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_12_pmp_1_addr_0 = io_ptw_12_pmp_1_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_12_pmp_1_mask_0 = io_ptw_12_pmp_1_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_pmp_2_cfg_l_0 = io_ptw_12_pmp_2_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_12_pmp_2_cfg_a_0 = io_ptw_12_pmp_2_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_pmp_2_cfg_x_0 = io_ptw_12_pmp_2_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_pmp_2_cfg_w_0 = io_ptw_12_pmp_2_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_pmp_2_cfg_r_0 = io_ptw_12_pmp_2_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_12_pmp_2_addr_0 = io_ptw_12_pmp_2_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_12_pmp_2_mask_0 = io_ptw_12_pmp_2_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_pmp_3_cfg_l_0 = io_ptw_12_pmp_3_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_12_pmp_3_cfg_a_0 = io_ptw_12_pmp_3_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_pmp_3_cfg_x_0 = io_ptw_12_pmp_3_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_pmp_3_cfg_w_0 = io_ptw_12_pmp_3_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_pmp_3_cfg_r_0 = io_ptw_12_pmp_3_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_12_pmp_3_addr_0 = io_ptw_12_pmp_3_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_12_pmp_3_mask_0 = io_ptw_12_pmp_3_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_pmp_4_cfg_l_0 = io_ptw_12_pmp_4_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_12_pmp_4_cfg_a_0 = io_ptw_12_pmp_4_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_pmp_4_cfg_x_0 = io_ptw_12_pmp_4_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_pmp_4_cfg_w_0 = io_ptw_12_pmp_4_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_pmp_4_cfg_r_0 = io_ptw_12_pmp_4_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_12_pmp_4_addr_0 = io_ptw_12_pmp_4_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_12_pmp_4_mask_0 = io_ptw_12_pmp_4_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_pmp_5_cfg_l_0 = io_ptw_12_pmp_5_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_12_pmp_5_cfg_a_0 = io_ptw_12_pmp_5_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_pmp_5_cfg_x_0 = io_ptw_12_pmp_5_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_pmp_5_cfg_w_0 = io_ptw_12_pmp_5_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_pmp_5_cfg_r_0 = io_ptw_12_pmp_5_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_12_pmp_5_addr_0 = io_ptw_12_pmp_5_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_12_pmp_5_mask_0 = io_ptw_12_pmp_5_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_pmp_6_cfg_l_0 = io_ptw_12_pmp_6_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_12_pmp_6_cfg_a_0 = io_ptw_12_pmp_6_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_pmp_6_cfg_x_0 = io_ptw_12_pmp_6_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_pmp_6_cfg_w_0 = io_ptw_12_pmp_6_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_pmp_6_cfg_r_0 = io_ptw_12_pmp_6_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_12_pmp_6_addr_0 = io_ptw_12_pmp_6_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_12_pmp_6_mask_0 = io_ptw_12_pmp_6_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_pmp_7_cfg_l_0 = io_ptw_12_pmp_7_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_12_pmp_7_cfg_a_0 = io_ptw_12_pmp_7_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_pmp_7_cfg_x_0 = io_ptw_12_pmp_7_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_pmp_7_cfg_w_0 = io_ptw_12_pmp_7_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_pmp_7_cfg_r_0 = io_ptw_12_pmp_7_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_12_pmp_7_addr_0 = io_ptw_12_pmp_7_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_12_pmp_7_mask_0 = io_ptw_12_pmp_7_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_customCSRs_csrs_0_ren_0 = io_ptw_12_customCSRs_csrs_0_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_customCSRs_csrs_0_wen_0 = io_ptw_12_customCSRs_csrs_0_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_12_customCSRs_csrs_0_wdata_0 = io_ptw_12_customCSRs_csrs_0_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_12_customCSRs_csrs_0_value_0 = io_ptw_12_customCSRs_csrs_0_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_customCSRs_csrs_1_ren_0 = io_ptw_12_customCSRs_csrs_1_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_customCSRs_csrs_1_wen_0 = io_ptw_12_customCSRs_csrs_1_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_12_customCSRs_csrs_1_wdata_0 = io_ptw_12_customCSRs_csrs_1_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_12_customCSRs_csrs_1_value_0 = io_ptw_12_customCSRs_csrs_1_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_customCSRs_csrs_2_ren_0 = io_ptw_12_customCSRs_csrs_2_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_customCSRs_csrs_2_wen_0 = io_ptw_12_customCSRs_csrs_2_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_12_customCSRs_csrs_2_wdata_0 = io_ptw_12_customCSRs_csrs_2_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_12_customCSRs_csrs_2_value_0 = io_ptw_12_customCSRs_csrs_2_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_customCSRs_csrs_3_ren_0 = io_ptw_12_customCSRs_csrs_3_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_customCSRs_csrs_3_wen_0 = io_ptw_12_customCSRs_csrs_3_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_12_customCSRs_csrs_3_wdata_0 = io_ptw_12_customCSRs_csrs_3_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_12_customCSRs_csrs_3_value_0 = io_ptw_12_customCSRs_csrs_3_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_req_ready_0 = io_ptw_13_req_ready; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_resp_valid_0 = io_ptw_13_resp_valid; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_resp_bits_ae_ptw_0 = io_ptw_13_resp_bits_ae_ptw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_resp_bits_ae_final_0 = io_ptw_13_resp_bits_ae_final; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_resp_bits_pf_0 = io_ptw_13_resp_bits_pf; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_resp_bits_gf_0 = io_ptw_13_resp_bits_gf; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_resp_bits_hr_0 = io_ptw_13_resp_bits_hr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_resp_bits_hw_0 = io_ptw_13_resp_bits_hw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_resp_bits_hx_0 = io_ptw_13_resp_bits_hx; // @[ZstdCompressor.scala:95:7]
wire [9:0] io_ptw_13_resp_bits_pte_reserved_for_future_0 = io_ptw_13_resp_bits_pte_reserved_for_future; // @[ZstdCompressor.scala:95:7]
wire [43:0] io_ptw_13_resp_bits_pte_ppn_0 = io_ptw_13_resp_bits_pte_ppn; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_13_resp_bits_pte_reserved_for_software_0 = io_ptw_13_resp_bits_pte_reserved_for_software; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_resp_bits_pte_d_0 = io_ptw_13_resp_bits_pte_d; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_resp_bits_pte_a_0 = io_ptw_13_resp_bits_pte_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_resp_bits_pte_g_0 = io_ptw_13_resp_bits_pte_g; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_resp_bits_pte_u_0 = io_ptw_13_resp_bits_pte_u; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_resp_bits_pte_x_0 = io_ptw_13_resp_bits_pte_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_resp_bits_pte_w_0 = io_ptw_13_resp_bits_pte_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_resp_bits_pte_r_0 = io_ptw_13_resp_bits_pte_r; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_resp_bits_pte_v_0 = io_ptw_13_resp_bits_pte_v; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_13_resp_bits_level_0 = io_ptw_13_resp_bits_level; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_resp_bits_homogeneous_0 = io_ptw_13_resp_bits_homogeneous; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_resp_bits_gpa_valid_0 = io_ptw_13_resp_bits_gpa_valid; // @[ZstdCompressor.scala:95:7]
wire [38:0] io_ptw_13_resp_bits_gpa_bits_0 = io_ptw_13_resp_bits_gpa_bits; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_resp_bits_gpa_is_pte_0 = io_ptw_13_resp_bits_gpa_is_pte; // @[ZstdCompressor.scala:95:7]
wire [3:0] io_ptw_13_ptbr_mode_0 = io_ptw_13_ptbr_mode; // @[ZstdCompressor.scala:95:7]
wire [43:0] io_ptw_13_ptbr_ppn_0 = io_ptw_13_ptbr_ppn; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_status_debug_0 = io_ptw_13_status_debug; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_status_cease_0 = io_ptw_13_status_cease; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_status_wfi_0 = io_ptw_13_status_wfi; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_13_status_isa_0 = io_ptw_13_status_isa; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_13_status_dprv_0 = io_ptw_13_status_dprv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_status_dv_0 = io_ptw_13_status_dv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_13_status_prv_0 = io_ptw_13_status_prv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_status_v_0 = io_ptw_13_status_v; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_status_mpv_0 = io_ptw_13_status_mpv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_status_gva_0 = io_ptw_13_status_gva; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_status_tsr_0 = io_ptw_13_status_tsr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_status_tw_0 = io_ptw_13_status_tw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_status_tvm_0 = io_ptw_13_status_tvm; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_status_mxr_0 = io_ptw_13_status_mxr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_status_sum_0 = io_ptw_13_status_sum; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_status_mprv_0 = io_ptw_13_status_mprv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_13_status_fs_0 = io_ptw_13_status_fs; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_13_status_mpp_0 = io_ptw_13_status_mpp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_status_spp_0 = io_ptw_13_status_spp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_status_mpie_0 = io_ptw_13_status_mpie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_status_spie_0 = io_ptw_13_status_spie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_status_mie_0 = io_ptw_13_status_mie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_status_sie_0 = io_ptw_13_status_sie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_hstatus_spvp_0 = io_ptw_13_hstatus_spvp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_hstatus_spv_0 = io_ptw_13_hstatus_spv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_hstatus_gva_0 = io_ptw_13_hstatus_gva; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_gstatus_debug_0 = io_ptw_13_gstatus_debug; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_gstatus_cease_0 = io_ptw_13_gstatus_cease; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_gstatus_wfi_0 = io_ptw_13_gstatus_wfi; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_13_gstatus_isa_0 = io_ptw_13_gstatus_isa; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_13_gstatus_dprv_0 = io_ptw_13_gstatus_dprv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_gstatus_dv_0 = io_ptw_13_gstatus_dv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_13_gstatus_prv_0 = io_ptw_13_gstatus_prv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_gstatus_v_0 = io_ptw_13_gstatus_v; // @[ZstdCompressor.scala:95:7]
wire [22:0] io_ptw_13_gstatus_zero2_0 = io_ptw_13_gstatus_zero2; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_gstatus_mpv_0 = io_ptw_13_gstatus_mpv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_gstatus_gva_0 = io_ptw_13_gstatus_gva; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_gstatus_mbe_0 = io_ptw_13_gstatus_mbe; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_gstatus_sbe_0 = io_ptw_13_gstatus_sbe; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_13_gstatus_sxl_0 = io_ptw_13_gstatus_sxl; // @[ZstdCompressor.scala:95:7]
wire [7:0] io_ptw_13_gstatus_zero1_0 = io_ptw_13_gstatus_zero1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_gstatus_tsr_0 = io_ptw_13_gstatus_tsr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_gstatus_tw_0 = io_ptw_13_gstatus_tw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_gstatus_tvm_0 = io_ptw_13_gstatus_tvm; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_gstatus_mxr_0 = io_ptw_13_gstatus_mxr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_gstatus_sum_0 = io_ptw_13_gstatus_sum; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_gstatus_mprv_0 = io_ptw_13_gstatus_mprv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_13_gstatus_fs_0 = io_ptw_13_gstatus_fs; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_13_gstatus_mpp_0 = io_ptw_13_gstatus_mpp; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_13_gstatus_vs_0 = io_ptw_13_gstatus_vs; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_gstatus_spp_0 = io_ptw_13_gstatus_spp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_gstatus_mpie_0 = io_ptw_13_gstatus_mpie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_gstatus_ube_0 = io_ptw_13_gstatus_ube; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_gstatus_spie_0 = io_ptw_13_gstatus_spie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_gstatus_upie_0 = io_ptw_13_gstatus_upie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_gstatus_mie_0 = io_ptw_13_gstatus_mie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_gstatus_hie_0 = io_ptw_13_gstatus_hie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_gstatus_sie_0 = io_ptw_13_gstatus_sie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_gstatus_uie_0 = io_ptw_13_gstatus_uie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_pmp_0_cfg_l_0 = io_ptw_13_pmp_0_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_13_pmp_0_cfg_a_0 = io_ptw_13_pmp_0_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_pmp_0_cfg_x_0 = io_ptw_13_pmp_0_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_pmp_0_cfg_w_0 = io_ptw_13_pmp_0_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_pmp_0_cfg_r_0 = io_ptw_13_pmp_0_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_13_pmp_0_addr_0 = io_ptw_13_pmp_0_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_13_pmp_0_mask_0 = io_ptw_13_pmp_0_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_pmp_1_cfg_l_0 = io_ptw_13_pmp_1_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_13_pmp_1_cfg_a_0 = io_ptw_13_pmp_1_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_pmp_1_cfg_x_0 = io_ptw_13_pmp_1_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_pmp_1_cfg_w_0 = io_ptw_13_pmp_1_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_pmp_1_cfg_r_0 = io_ptw_13_pmp_1_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_13_pmp_1_addr_0 = io_ptw_13_pmp_1_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_13_pmp_1_mask_0 = io_ptw_13_pmp_1_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_pmp_2_cfg_l_0 = io_ptw_13_pmp_2_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_13_pmp_2_cfg_a_0 = io_ptw_13_pmp_2_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_pmp_2_cfg_x_0 = io_ptw_13_pmp_2_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_pmp_2_cfg_w_0 = io_ptw_13_pmp_2_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_pmp_2_cfg_r_0 = io_ptw_13_pmp_2_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_13_pmp_2_addr_0 = io_ptw_13_pmp_2_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_13_pmp_2_mask_0 = io_ptw_13_pmp_2_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_pmp_3_cfg_l_0 = io_ptw_13_pmp_3_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_13_pmp_3_cfg_a_0 = io_ptw_13_pmp_3_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_pmp_3_cfg_x_0 = io_ptw_13_pmp_3_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_pmp_3_cfg_w_0 = io_ptw_13_pmp_3_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_pmp_3_cfg_r_0 = io_ptw_13_pmp_3_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_13_pmp_3_addr_0 = io_ptw_13_pmp_3_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_13_pmp_3_mask_0 = io_ptw_13_pmp_3_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_pmp_4_cfg_l_0 = io_ptw_13_pmp_4_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_13_pmp_4_cfg_a_0 = io_ptw_13_pmp_4_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_pmp_4_cfg_x_0 = io_ptw_13_pmp_4_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_pmp_4_cfg_w_0 = io_ptw_13_pmp_4_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_pmp_4_cfg_r_0 = io_ptw_13_pmp_4_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_13_pmp_4_addr_0 = io_ptw_13_pmp_4_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_13_pmp_4_mask_0 = io_ptw_13_pmp_4_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_pmp_5_cfg_l_0 = io_ptw_13_pmp_5_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_13_pmp_5_cfg_a_0 = io_ptw_13_pmp_5_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_pmp_5_cfg_x_0 = io_ptw_13_pmp_5_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_pmp_5_cfg_w_0 = io_ptw_13_pmp_5_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_pmp_5_cfg_r_0 = io_ptw_13_pmp_5_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_13_pmp_5_addr_0 = io_ptw_13_pmp_5_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_13_pmp_5_mask_0 = io_ptw_13_pmp_5_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_pmp_6_cfg_l_0 = io_ptw_13_pmp_6_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_13_pmp_6_cfg_a_0 = io_ptw_13_pmp_6_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_pmp_6_cfg_x_0 = io_ptw_13_pmp_6_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_pmp_6_cfg_w_0 = io_ptw_13_pmp_6_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_pmp_6_cfg_r_0 = io_ptw_13_pmp_6_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_13_pmp_6_addr_0 = io_ptw_13_pmp_6_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_13_pmp_6_mask_0 = io_ptw_13_pmp_6_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_pmp_7_cfg_l_0 = io_ptw_13_pmp_7_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_13_pmp_7_cfg_a_0 = io_ptw_13_pmp_7_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_pmp_7_cfg_x_0 = io_ptw_13_pmp_7_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_pmp_7_cfg_w_0 = io_ptw_13_pmp_7_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_pmp_7_cfg_r_0 = io_ptw_13_pmp_7_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_13_pmp_7_addr_0 = io_ptw_13_pmp_7_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_13_pmp_7_mask_0 = io_ptw_13_pmp_7_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_customCSRs_csrs_0_ren_0 = io_ptw_13_customCSRs_csrs_0_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_customCSRs_csrs_0_wen_0 = io_ptw_13_customCSRs_csrs_0_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_13_customCSRs_csrs_0_wdata_0 = io_ptw_13_customCSRs_csrs_0_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_13_customCSRs_csrs_0_value_0 = io_ptw_13_customCSRs_csrs_0_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_customCSRs_csrs_1_ren_0 = io_ptw_13_customCSRs_csrs_1_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_customCSRs_csrs_1_wen_0 = io_ptw_13_customCSRs_csrs_1_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_13_customCSRs_csrs_1_wdata_0 = io_ptw_13_customCSRs_csrs_1_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_13_customCSRs_csrs_1_value_0 = io_ptw_13_customCSRs_csrs_1_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_customCSRs_csrs_2_ren_0 = io_ptw_13_customCSRs_csrs_2_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_customCSRs_csrs_2_wen_0 = io_ptw_13_customCSRs_csrs_2_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_13_customCSRs_csrs_2_wdata_0 = io_ptw_13_customCSRs_csrs_2_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_13_customCSRs_csrs_2_value_0 = io_ptw_13_customCSRs_csrs_2_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_customCSRs_csrs_3_ren_0 = io_ptw_13_customCSRs_csrs_3_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_customCSRs_csrs_3_wen_0 = io_ptw_13_customCSRs_csrs_3_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_13_customCSRs_csrs_3_wdata_0 = io_ptw_13_customCSRs_csrs_3_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_13_customCSRs_csrs_3_value_0 = io_ptw_13_customCSRs_csrs_3_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_req_ready_0 = io_ptw_14_req_ready; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_resp_valid_0 = io_ptw_14_resp_valid; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_resp_bits_ae_ptw_0 = io_ptw_14_resp_bits_ae_ptw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_resp_bits_ae_final_0 = io_ptw_14_resp_bits_ae_final; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_resp_bits_pf_0 = io_ptw_14_resp_bits_pf; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_resp_bits_gf_0 = io_ptw_14_resp_bits_gf; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_resp_bits_hr_0 = io_ptw_14_resp_bits_hr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_resp_bits_hw_0 = io_ptw_14_resp_bits_hw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_resp_bits_hx_0 = io_ptw_14_resp_bits_hx; // @[ZstdCompressor.scala:95:7]
wire [9:0] io_ptw_14_resp_bits_pte_reserved_for_future_0 = io_ptw_14_resp_bits_pte_reserved_for_future; // @[ZstdCompressor.scala:95:7]
wire [43:0] io_ptw_14_resp_bits_pte_ppn_0 = io_ptw_14_resp_bits_pte_ppn; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_14_resp_bits_pte_reserved_for_software_0 = io_ptw_14_resp_bits_pte_reserved_for_software; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_resp_bits_pte_d_0 = io_ptw_14_resp_bits_pte_d; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_resp_bits_pte_a_0 = io_ptw_14_resp_bits_pte_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_resp_bits_pte_g_0 = io_ptw_14_resp_bits_pte_g; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_resp_bits_pte_u_0 = io_ptw_14_resp_bits_pte_u; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_resp_bits_pte_x_0 = io_ptw_14_resp_bits_pte_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_resp_bits_pte_w_0 = io_ptw_14_resp_bits_pte_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_resp_bits_pte_r_0 = io_ptw_14_resp_bits_pte_r; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_resp_bits_pte_v_0 = io_ptw_14_resp_bits_pte_v; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_14_resp_bits_level_0 = io_ptw_14_resp_bits_level; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_resp_bits_homogeneous_0 = io_ptw_14_resp_bits_homogeneous; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_resp_bits_gpa_valid_0 = io_ptw_14_resp_bits_gpa_valid; // @[ZstdCompressor.scala:95:7]
wire [38:0] io_ptw_14_resp_bits_gpa_bits_0 = io_ptw_14_resp_bits_gpa_bits; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_resp_bits_gpa_is_pte_0 = io_ptw_14_resp_bits_gpa_is_pte; // @[ZstdCompressor.scala:95:7]
wire [3:0] io_ptw_14_ptbr_mode_0 = io_ptw_14_ptbr_mode; // @[ZstdCompressor.scala:95:7]
wire [43:0] io_ptw_14_ptbr_ppn_0 = io_ptw_14_ptbr_ppn; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_status_debug_0 = io_ptw_14_status_debug; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_status_cease_0 = io_ptw_14_status_cease; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_status_wfi_0 = io_ptw_14_status_wfi; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_14_status_isa_0 = io_ptw_14_status_isa; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_14_status_dprv_0 = io_ptw_14_status_dprv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_status_dv_0 = io_ptw_14_status_dv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_14_status_prv_0 = io_ptw_14_status_prv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_status_v_0 = io_ptw_14_status_v; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_status_mpv_0 = io_ptw_14_status_mpv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_status_gva_0 = io_ptw_14_status_gva; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_status_tsr_0 = io_ptw_14_status_tsr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_status_tw_0 = io_ptw_14_status_tw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_status_tvm_0 = io_ptw_14_status_tvm; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_status_mxr_0 = io_ptw_14_status_mxr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_status_sum_0 = io_ptw_14_status_sum; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_status_mprv_0 = io_ptw_14_status_mprv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_14_status_fs_0 = io_ptw_14_status_fs; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_14_status_mpp_0 = io_ptw_14_status_mpp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_status_spp_0 = io_ptw_14_status_spp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_status_mpie_0 = io_ptw_14_status_mpie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_status_spie_0 = io_ptw_14_status_spie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_status_mie_0 = io_ptw_14_status_mie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_status_sie_0 = io_ptw_14_status_sie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_hstatus_spvp_0 = io_ptw_14_hstatus_spvp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_hstatus_spv_0 = io_ptw_14_hstatus_spv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_hstatus_gva_0 = io_ptw_14_hstatus_gva; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_gstatus_debug_0 = io_ptw_14_gstatus_debug; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_gstatus_cease_0 = io_ptw_14_gstatus_cease; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_gstatus_wfi_0 = io_ptw_14_gstatus_wfi; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_14_gstatus_isa_0 = io_ptw_14_gstatus_isa; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_14_gstatus_dprv_0 = io_ptw_14_gstatus_dprv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_gstatus_dv_0 = io_ptw_14_gstatus_dv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_14_gstatus_prv_0 = io_ptw_14_gstatus_prv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_gstatus_v_0 = io_ptw_14_gstatus_v; // @[ZstdCompressor.scala:95:7]
wire [22:0] io_ptw_14_gstatus_zero2_0 = io_ptw_14_gstatus_zero2; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_gstatus_mpv_0 = io_ptw_14_gstatus_mpv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_gstatus_gva_0 = io_ptw_14_gstatus_gva; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_gstatus_mbe_0 = io_ptw_14_gstatus_mbe; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_gstatus_sbe_0 = io_ptw_14_gstatus_sbe; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_14_gstatus_sxl_0 = io_ptw_14_gstatus_sxl; // @[ZstdCompressor.scala:95:7]
wire [7:0] io_ptw_14_gstatus_zero1_0 = io_ptw_14_gstatus_zero1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_gstatus_tsr_0 = io_ptw_14_gstatus_tsr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_gstatus_tw_0 = io_ptw_14_gstatus_tw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_gstatus_tvm_0 = io_ptw_14_gstatus_tvm; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_gstatus_mxr_0 = io_ptw_14_gstatus_mxr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_gstatus_sum_0 = io_ptw_14_gstatus_sum; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_gstatus_mprv_0 = io_ptw_14_gstatus_mprv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_14_gstatus_fs_0 = io_ptw_14_gstatus_fs; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_14_gstatus_mpp_0 = io_ptw_14_gstatus_mpp; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_14_gstatus_vs_0 = io_ptw_14_gstatus_vs; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_gstatus_spp_0 = io_ptw_14_gstatus_spp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_gstatus_mpie_0 = io_ptw_14_gstatus_mpie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_gstatus_ube_0 = io_ptw_14_gstatus_ube; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_gstatus_spie_0 = io_ptw_14_gstatus_spie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_gstatus_upie_0 = io_ptw_14_gstatus_upie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_gstatus_mie_0 = io_ptw_14_gstatus_mie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_gstatus_hie_0 = io_ptw_14_gstatus_hie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_gstatus_sie_0 = io_ptw_14_gstatus_sie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_gstatus_uie_0 = io_ptw_14_gstatus_uie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_pmp_0_cfg_l_0 = io_ptw_14_pmp_0_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_14_pmp_0_cfg_a_0 = io_ptw_14_pmp_0_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_pmp_0_cfg_x_0 = io_ptw_14_pmp_0_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_pmp_0_cfg_w_0 = io_ptw_14_pmp_0_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_pmp_0_cfg_r_0 = io_ptw_14_pmp_0_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_14_pmp_0_addr_0 = io_ptw_14_pmp_0_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_14_pmp_0_mask_0 = io_ptw_14_pmp_0_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_pmp_1_cfg_l_0 = io_ptw_14_pmp_1_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_14_pmp_1_cfg_a_0 = io_ptw_14_pmp_1_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_pmp_1_cfg_x_0 = io_ptw_14_pmp_1_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_pmp_1_cfg_w_0 = io_ptw_14_pmp_1_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_pmp_1_cfg_r_0 = io_ptw_14_pmp_1_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_14_pmp_1_addr_0 = io_ptw_14_pmp_1_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_14_pmp_1_mask_0 = io_ptw_14_pmp_1_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_pmp_2_cfg_l_0 = io_ptw_14_pmp_2_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_14_pmp_2_cfg_a_0 = io_ptw_14_pmp_2_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_pmp_2_cfg_x_0 = io_ptw_14_pmp_2_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_pmp_2_cfg_w_0 = io_ptw_14_pmp_2_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_pmp_2_cfg_r_0 = io_ptw_14_pmp_2_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_14_pmp_2_addr_0 = io_ptw_14_pmp_2_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_14_pmp_2_mask_0 = io_ptw_14_pmp_2_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_pmp_3_cfg_l_0 = io_ptw_14_pmp_3_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_14_pmp_3_cfg_a_0 = io_ptw_14_pmp_3_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_pmp_3_cfg_x_0 = io_ptw_14_pmp_3_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_pmp_3_cfg_w_0 = io_ptw_14_pmp_3_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_pmp_3_cfg_r_0 = io_ptw_14_pmp_3_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_14_pmp_3_addr_0 = io_ptw_14_pmp_3_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_14_pmp_3_mask_0 = io_ptw_14_pmp_3_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_pmp_4_cfg_l_0 = io_ptw_14_pmp_4_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_14_pmp_4_cfg_a_0 = io_ptw_14_pmp_4_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_pmp_4_cfg_x_0 = io_ptw_14_pmp_4_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_pmp_4_cfg_w_0 = io_ptw_14_pmp_4_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_pmp_4_cfg_r_0 = io_ptw_14_pmp_4_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_14_pmp_4_addr_0 = io_ptw_14_pmp_4_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_14_pmp_4_mask_0 = io_ptw_14_pmp_4_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_pmp_5_cfg_l_0 = io_ptw_14_pmp_5_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_14_pmp_5_cfg_a_0 = io_ptw_14_pmp_5_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_pmp_5_cfg_x_0 = io_ptw_14_pmp_5_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_pmp_5_cfg_w_0 = io_ptw_14_pmp_5_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_pmp_5_cfg_r_0 = io_ptw_14_pmp_5_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_14_pmp_5_addr_0 = io_ptw_14_pmp_5_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_14_pmp_5_mask_0 = io_ptw_14_pmp_5_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_pmp_6_cfg_l_0 = io_ptw_14_pmp_6_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_14_pmp_6_cfg_a_0 = io_ptw_14_pmp_6_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_pmp_6_cfg_x_0 = io_ptw_14_pmp_6_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_pmp_6_cfg_w_0 = io_ptw_14_pmp_6_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_pmp_6_cfg_r_0 = io_ptw_14_pmp_6_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_14_pmp_6_addr_0 = io_ptw_14_pmp_6_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_14_pmp_6_mask_0 = io_ptw_14_pmp_6_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_pmp_7_cfg_l_0 = io_ptw_14_pmp_7_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_14_pmp_7_cfg_a_0 = io_ptw_14_pmp_7_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_pmp_7_cfg_x_0 = io_ptw_14_pmp_7_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_pmp_7_cfg_w_0 = io_ptw_14_pmp_7_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_pmp_7_cfg_r_0 = io_ptw_14_pmp_7_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_14_pmp_7_addr_0 = io_ptw_14_pmp_7_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_14_pmp_7_mask_0 = io_ptw_14_pmp_7_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_customCSRs_csrs_0_ren_0 = io_ptw_14_customCSRs_csrs_0_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_customCSRs_csrs_0_wen_0 = io_ptw_14_customCSRs_csrs_0_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_14_customCSRs_csrs_0_wdata_0 = io_ptw_14_customCSRs_csrs_0_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_14_customCSRs_csrs_0_value_0 = io_ptw_14_customCSRs_csrs_0_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_customCSRs_csrs_1_ren_0 = io_ptw_14_customCSRs_csrs_1_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_customCSRs_csrs_1_wen_0 = io_ptw_14_customCSRs_csrs_1_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_14_customCSRs_csrs_1_wdata_0 = io_ptw_14_customCSRs_csrs_1_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_14_customCSRs_csrs_1_value_0 = io_ptw_14_customCSRs_csrs_1_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_customCSRs_csrs_2_ren_0 = io_ptw_14_customCSRs_csrs_2_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_customCSRs_csrs_2_wen_0 = io_ptw_14_customCSRs_csrs_2_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_14_customCSRs_csrs_2_wdata_0 = io_ptw_14_customCSRs_csrs_2_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_14_customCSRs_csrs_2_value_0 = io_ptw_14_customCSRs_csrs_2_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_customCSRs_csrs_3_ren_0 = io_ptw_14_customCSRs_csrs_3_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_customCSRs_csrs_3_wen_0 = io_ptw_14_customCSRs_csrs_3_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_14_customCSRs_csrs_3_wdata_0 = io_ptw_14_customCSRs_csrs_3_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_14_customCSRs_csrs_3_value_0 = io_ptw_14_customCSRs_csrs_3_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_req_ready_0 = io_ptw_15_req_ready; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_resp_valid_0 = io_ptw_15_resp_valid; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_resp_bits_ae_ptw_0 = io_ptw_15_resp_bits_ae_ptw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_resp_bits_ae_final_0 = io_ptw_15_resp_bits_ae_final; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_resp_bits_pf_0 = io_ptw_15_resp_bits_pf; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_resp_bits_gf_0 = io_ptw_15_resp_bits_gf; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_resp_bits_hr_0 = io_ptw_15_resp_bits_hr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_resp_bits_hw_0 = io_ptw_15_resp_bits_hw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_resp_bits_hx_0 = io_ptw_15_resp_bits_hx; // @[ZstdCompressor.scala:95:7]
wire [9:0] io_ptw_15_resp_bits_pte_reserved_for_future_0 = io_ptw_15_resp_bits_pte_reserved_for_future; // @[ZstdCompressor.scala:95:7]
wire [43:0] io_ptw_15_resp_bits_pte_ppn_0 = io_ptw_15_resp_bits_pte_ppn; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_15_resp_bits_pte_reserved_for_software_0 = io_ptw_15_resp_bits_pte_reserved_for_software; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_resp_bits_pte_d_0 = io_ptw_15_resp_bits_pte_d; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_resp_bits_pte_a_0 = io_ptw_15_resp_bits_pte_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_resp_bits_pte_g_0 = io_ptw_15_resp_bits_pte_g; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_resp_bits_pte_u_0 = io_ptw_15_resp_bits_pte_u; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_resp_bits_pte_x_0 = io_ptw_15_resp_bits_pte_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_resp_bits_pte_w_0 = io_ptw_15_resp_bits_pte_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_resp_bits_pte_r_0 = io_ptw_15_resp_bits_pte_r; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_resp_bits_pte_v_0 = io_ptw_15_resp_bits_pte_v; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_15_resp_bits_level_0 = io_ptw_15_resp_bits_level; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_resp_bits_homogeneous_0 = io_ptw_15_resp_bits_homogeneous; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_resp_bits_gpa_valid_0 = io_ptw_15_resp_bits_gpa_valid; // @[ZstdCompressor.scala:95:7]
wire [38:0] io_ptw_15_resp_bits_gpa_bits_0 = io_ptw_15_resp_bits_gpa_bits; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_resp_bits_gpa_is_pte_0 = io_ptw_15_resp_bits_gpa_is_pte; // @[ZstdCompressor.scala:95:7]
wire [3:0] io_ptw_15_ptbr_mode_0 = io_ptw_15_ptbr_mode; // @[ZstdCompressor.scala:95:7]
wire [43:0] io_ptw_15_ptbr_ppn_0 = io_ptw_15_ptbr_ppn; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_status_debug_0 = io_ptw_15_status_debug; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_status_cease_0 = io_ptw_15_status_cease; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_status_wfi_0 = io_ptw_15_status_wfi; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_15_status_isa_0 = io_ptw_15_status_isa; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_15_status_dprv_0 = io_ptw_15_status_dprv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_status_dv_0 = io_ptw_15_status_dv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_15_status_prv_0 = io_ptw_15_status_prv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_status_v_0 = io_ptw_15_status_v; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_status_mpv_0 = io_ptw_15_status_mpv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_status_gva_0 = io_ptw_15_status_gva; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_status_tsr_0 = io_ptw_15_status_tsr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_status_tw_0 = io_ptw_15_status_tw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_status_tvm_0 = io_ptw_15_status_tvm; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_status_mxr_0 = io_ptw_15_status_mxr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_status_sum_0 = io_ptw_15_status_sum; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_status_mprv_0 = io_ptw_15_status_mprv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_15_status_fs_0 = io_ptw_15_status_fs; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_15_status_mpp_0 = io_ptw_15_status_mpp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_status_spp_0 = io_ptw_15_status_spp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_status_mpie_0 = io_ptw_15_status_mpie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_status_spie_0 = io_ptw_15_status_spie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_status_mie_0 = io_ptw_15_status_mie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_status_sie_0 = io_ptw_15_status_sie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_hstatus_spvp_0 = io_ptw_15_hstatus_spvp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_hstatus_spv_0 = io_ptw_15_hstatus_spv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_hstatus_gva_0 = io_ptw_15_hstatus_gva; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_gstatus_debug_0 = io_ptw_15_gstatus_debug; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_gstatus_cease_0 = io_ptw_15_gstatus_cease; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_gstatus_wfi_0 = io_ptw_15_gstatus_wfi; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_15_gstatus_isa_0 = io_ptw_15_gstatus_isa; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_15_gstatus_dprv_0 = io_ptw_15_gstatus_dprv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_gstatus_dv_0 = io_ptw_15_gstatus_dv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_15_gstatus_prv_0 = io_ptw_15_gstatus_prv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_gstatus_v_0 = io_ptw_15_gstatus_v; // @[ZstdCompressor.scala:95:7]
wire [22:0] io_ptw_15_gstatus_zero2_0 = io_ptw_15_gstatus_zero2; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_gstatus_mpv_0 = io_ptw_15_gstatus_mpv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_gstatus_gva_0 = io_ptw_15_gstatus_gva; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_gstatus_mbe_0 = io_ptw_15_gstatus_mbe; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_gstatus_sbe_0 = io_ptw_15_gstatus_sbe; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_15_gstatus_sxl_0 = io_ptw_15_gstatus_sxl; // @[ZstdCompressor.scala:95:7]
wire [7:0] io_ptw_15_gstatus_zero1_0 = io_ptw_15_gstatus_zero1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_gstatus_tsr_0 = io_ptw_15_gstatus_tsr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_gstatus_tw_0 = io_ptw_15_gstatus_tw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_gstatus_tvm_0 = io_ptw_15_gstatus_tvm; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_gstatus_mxr_0 = io_ptw_15_gstatus_mxr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_gstatus_sum_0 = io_ptw_15_gstatus_sum; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_gstatus_mprv_0 = io_ptw_15_gstatus_mprv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_15_gstatus_fs_0 = io_ptw_15_gstatus_fs; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_15_gstatus_mpp_0 = io_ptw_15_gstatus_mpp; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_15_gstatus_vs_0 = io_ptw_15_gstatus_vs; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_gstatus_spp_0 = io_ptw_15_gstatus_spp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_gstatus_mpie_0 = io_ptw_15_gstatus_mpie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_gstatus_ube_0 = io_ptw_15_gstatus_ube; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_gstatus_spie_0 = io_ptw_15_gstatus_spie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_gstatus_upie_0 = io_ptw_15_gstatus_upie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_gstatus_mie_0 = io_ptw_15_gstatus_mie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_gstatus_hie_0 = io_ptw_15_gstatus_hie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_gstatus_sie_0 = io_ptw_15_gstatus_sie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_gstatus_uie_0 = io_ptw_15_gstatus_uie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_pmp_0_cfg_l_0 = io_ptw_15_pmp_0_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_15_pmp_0_cfg_a_0 = io_ptw_15_pmp_0_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_pmp_0_cfg_x_0 = io_ptw_15_pmp_0_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_pmp_0_cfg_w_0 = io_ptw_15_pmp_0_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_pmp_0_cfg_r_0 = io_ptw_15_pmp_0_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_15_pmp_0_addr_0 = io_ptw_15_pmp_0_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_15_pmp_0_mask_0 = io_ptw_15_pmp_0_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_pmp_1_cfg_l_0 = io_ptw_15_pmp_1_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_15_pmp_1_cfg_a_0 = io_ptw_15_pmp_1_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_pmp_1_cfg_x_0 = io_ptw_15_pmp_1_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_pmp_1_cfg_w_0 = io_ptw_15_pmp_1_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_pmp_1_cfg_r_0 = io_ptw_15_pmp_1_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_15_pmp_1_addr_0 = io_ptw_15_pmp_1_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_15_pmp_1_mask_0 = io_ptw_15_pmp_1_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_pmp_2_cfg_l_0 = io_ptw_15_pmp_2_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_15_pmp_2_cfg_a_0 = io_ptw_15_pmp_2_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_pmp_2_cfg_x_0 = io_ptw_15_pmp_2_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_pmp_2_cfg_w_0 = io_ptw_15_pmp_2_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_pmp_2_cfg_r_0 = io_ptw_15_pmp_2_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_15_pmp_2_addr_0 = io_ptw_15_pmp_2_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_15_pmp_2_mask_0 = io_ptw_15_pmp_2_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_pmp_3_cfg_l_0 = io_ptw_15_pmp_3_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_15_pmp_3_cfg_a_0 = io_ptw_15_pmp_3_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_pmp_3_cfg_x_0 = io_ptw_15_pmp_3_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_pmp_3_cfg_w_0 = io_ptw_15_pmp_3_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_pmp_3_cfg_r_0 = io_ptw_15_pmp_3_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_15_pmp_3_addr_0 = io_ptw_15_pmp_3_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_15_pmp_3_mask_0 = io_ptw_15_pmp_3_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_pmp_4_cfg_l_0 = io_ptw_15_pmp_4_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_15_pmp_4_cfg_a_0 = io_ptw_15_pmp_4_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_pmp_4_cfg_x_0 = io_ptw_15_pmp_4_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_pmp_4_cfg_w_0 = io_ptw_15_pmp_4_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_pmp_4_cfg_r_0 = io_ptw_15_pmp_4_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_15_pmp_4_addr_0 = io_ptw_15_pmp_4_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_15_pmp_4_mask_0 = io_ptw_15_pmp_4_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_pmp_5_cfg_l_0 = io_ptw_15_pmp_5_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_15_pmp_5_cfg_a_0 = io_ptw_15_pmp_5_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_pmp_5_cfg_x_0 = io_ptw_15_pmp_5_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_pmp_5_cfg_w_0 = io_ptw_15_pmp_5_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_pmp_5_cfg_r_0 = io_ptw_15_pmp_5_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_15_pmp_5_addr_0 = io_ptw_15_pmp_5_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_15_pmp_5_mask_0 = io_ptw_15_pmp_5_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_pmp_6_cfg_l_0 = io_ptw_15_pmp_6_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_15_pmp_6_cfg_a_0 = io_ptw_15_pmp_6_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_pmp_6_cfg_x_0 = io_ptw_15_pmp_6_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_pmp_6_cfg_w_0 = io_ptw_15_pmp_6_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_pmp_6_cfg_r_0 = io_ptw_15_pmp_6_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_15_pmp_6_addr_0 = io_ptw_15_pmp_6_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_15_pmp_6_mask_0 = io_ptw_15_pmp_6_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_pmp_7_cfg_l_0 = io_ptw_15_pmp_7_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_15_pmp_7_cfg_a_0 = io_ptw_15_pmp_7_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_pmp_7_cfg_x_0 = io_ptw_15_pmp_7_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_pmp_7_cfg_w_0 = io_ptw_15_pmp_7_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_pmp_7_cfg_r_0 = io_ptw_15_pmp_7_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_15_pmp_7_addr_0 = io_ptw_15_pmp_7_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_15_pmp_7_mask_0 = io_ptw_15_pmp_7_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_customCSRs_csrs_0_ren_0 = io_ptw_15_customCSRs_csrs_0_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_customCSRs_csrs_0_wen_0 = io_ptw_15_customCSRs_csrs_0_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_15_customCSRs_csrs_0_wdata_0 = io_ptw_15_customCSRs_csrs_0_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_15_customCSRs_csrs_0_value_0 = io_ptw_15_customCSRs_csrs_0_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_customCSRs_csrs_1_ren_0 = io_ptw_15_customCSRs_csrs_1_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_customCSRs_csrs_1_wen_0 = io_ptw_15_customCSRs_csrs_1_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_15_customCSRs_csrs_1_wdata_0 = io_ptw_15_customCSRs_csrs_1_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_15_customCSRs_csrs_1_value_0 = io_ptw_15_customCSRs_csrs_1_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_customCSRs_csrs_2_ren_0 = io_ptw_15_customCSRs_csrs_2_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_customCSRs_csrs_2_wen_0 = io_ptw_15_customCSRs_csrs_2_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_15_customCSRs_csrs_2_wdata_0 = io_ptw_15_customCSRs_csrs_2_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_15_customCSRs_csrs_2_value_0 = io_ptw_15_customCSRs_csrs_2_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_customCSRs_csrs_3_ren_0 = io_ptw_15_customCSRs_csrs_3_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_customCSRs_csrs_3_wen_0 = io_ptw_15_customCSRs_csrs_3_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_15_customCSRs_csrs_3_wdata_0 = io_ptw_15_customCSRs_csrs_3_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_15_customCSRs_csrs_3_value_0 = io_ptw_15_customCSRs_csrs_3_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_req_ready_0 = io_ptw_16_req_ready; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_resp_valid_0 = io_ptw_16_resp_valid; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_resp_bits_ae_ptw_0 = io_ptw_16_resp_bits_ae_ptw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_resp_bits_ae_final_0 = io_ptw_16_resp_bits_ae_final; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_resp_bits_pf_0 = io_ptw_16_resp_bits_pf; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_resp_bits_gf_0 = io_ptw_16_resp_bits_gf; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_resp_bits_hr_0 = io_ptw_16_resp_bits_hr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_resp_bits_hw_0 = io_ptw_16_resp_bits_hw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_resp_bits_hx_0 = io_ptw_16_resp_bits_hx; // @[ZstdCompressor.scala:95:7]
wire [9:0] io_ptw_16_resp_bits_pte_reserved_for_future_0 = io_ptw_16_resp_bits_pte_reserved_for_future; // @[ZstdCompressor.scala:95:7]
wire [43:0] io_ptw_16_resp_bits_pte_ppn_0 = io_ptw_16_resp_bits_pte_ppn; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_16_resp_bits_pte_reserved_for_software_0 = io_ptw_16_resp_bits_pte_reserved_for_software; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_resp_bits_pte_d_0 = io_ptw_16_resp_bits_pte_d; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_resp_bits_pte_a_0 = io_ptw_16_resp_bits_pte_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_resp_bits_pte_g_0 = io_ptw_16_resp_bits_pte_g; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_resp_bits_pte_u_0 = io_ptw_16_resp_bits_pte_u; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_resp_bits_pte_x_0 = io_ptw_16_resp_bits_pte_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_resp_bits_pte_w_0 = io_ptw_16_resp_bits_pte_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_resp_bits_pte_r_0 = io_ptw_16_resp_bits_pte_r; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_resp_bits_pte_v_0 = io_ptw_16_resp_bits_pte_v; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_16_resp_bits_level_0 = io_ptw_16_resp_bits_level; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_resp_bits_homogeneous_0 = io_ptw_16_resp_bits_homogeneous; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_resp_bits_gpa_valid_0 = io_ptw_16_resp_bits_gpa_valid; // @[ZstdCompressor.scala:95:7]
wire [38:0] io_ptw_16_resp_bits_gpa_bits_0 = io_ptw_16_resp_bits_gpa_bits; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_resp_bits_gpa_is_pte_0 = io_ptw_16_resp_bits_gpa_is_pte; // @[ZstdCompressor.scala:95:7]
wire [3:0] io_ptw_16_ptbr_mode_0 = io_ptw_16_ptbr_mode; // @[ZstdCompressor.scala:95:7]
wire [43:0] io_ptw_16_ptbr_ppn_0 = io_ptw_16_ptbr_ppn; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_status_debug_0 = io_ptw_16_status_debug; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_status_cease_0 = io_ptw_16_status_cease; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_status_wfi_0 = io_ptw_16_status_wfi; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_16_status_isa_0 = io_ptw_16_status_isa; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_16_status_dprv_0 = io_ptw_16_status_dprv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_status_dv_0 = io_ptw_16_status_dv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_16_status_prv_0 = io_ptw_16_status_prv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_status_v_0 = io_ptw_16_status_v; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_status_mpv_0 = io_ptw_16_status_mpv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_status_gva_0 = io_ptw_16_status_gva; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_status_tsr_0 = io_ptw_16_status_tsr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_status_tw_0 = io_ptw_16_status_tw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_status_tvm_0 = io_ptw_16_status_tvm; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_status_mxr_0 = io_ptw_16_status_mxr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_status_sum_0 = io_ptw_16_status_sum; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_status_mprv_0 = io_ptw_16_status_mprv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_16_status_fs_0 = io_ptw_16_status_fs; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_16_status_mpp_0 = io_ptw_16_status_mpp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_status_spp_0 = io_ptw_16_status_spp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_status_mpie_0 = io_ptw_16_status_mpie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_status_spie_0 = io_ptw_16_status_spie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_status_mie_0 = io_ptw_16_status_mie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_status_sie_0 = io_ptw_16_status_sie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_hstatus_spvp_0 = io_ptw_16_hstatus_spvp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_hstatus_spv_0 = io_ptw_16_hstatus_spv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_hstatus_gva_0 = io_ptw_16_hstatus_gva; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_gstatus_debug_0 = io_ptw_16_gstatus_debug; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_gstatus_cease_0 = io_ptw_16_gstatus_cease; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_gstatus_wfi_0 = io_ptw_16_gstatus_wfi; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_16_gstatus_isa_0 = io_ptw_16_gstatus_isa; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_16_gstatus_dprv_0 = io_ptw_16_gstatus_dprv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_gstatus_dv_0 = io_ptw_16_gstatus_dv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_16_gstatus_prv_0 = io_ptw_16_gstatus_prv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_gstatus_v_0 = io_ptw_16_gstatus_v; // @[ZstdCompressor.scala:95:7]
wire [22:0] io_ptw_16_gstatus_zero2_0 = io_ptw_16_gstatus_zero2; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_gstatus_mpv_0 = io_ptw_16_gstatus_mpv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_gstatus_gva_0 = io_ptw_16_gstatus_gva; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_gstatus_mbe_0 = io_ptw_16_gstatus_mbe; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_gstatus_sbe_0 = io_ptw_16_gstatus_sbe; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_16_gstatus_sxl_0 = io_ptw_16_gstatus_sxl; // @[ZstdCompressor.scala:95:7]
wire [7:0] io_ptw_16_gstatus_zero1_0 = io_ptw_16_gstatus_zero1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_gstatus_tsr_0 = io_ptw_16_gstatus_tsr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_gstatus_tw_0 = io_ptw_16_gstatus_tw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_gstatus_tvm_0 = io_ptw_16_gstatus_tvm; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_gstatus_mxr_0 = io_ptw_16_gstatus_mxr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_gstatus_sum_0 = io_ptw_16_gstatus_sum; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_gstatus_mprv_0 = io_ptw_16_gstatus_mprv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_16_gstatus_fs_0 = io_ptw_16_gstatus_fs; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_16_gstatus_mpp_0 = io_ptw_16_gstatus_mpp; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_16_gstatus_vs_0 = io_ptw_16_gstatus_vs; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_gstatus_spp_0 = io_ptw_16_gstatus_spp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_gstatus_mpie_0 = io_ptw_16_gstatus_mpie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_gstatus_ube_0 = io_ptw_16_gstatus_ube; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_gstatus_spie_0 = io_ptw_16_gstatus_spie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_gstatus_upie_0 = io_ptw_16_gstatus_upie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_gstatus_mie_0 = io_ptw_16_gstatus_mie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_gstatus_hie_0 = io_ptw_16_gstatus_hie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_gstatus_sie_0 = io_ptw_16_gstatus_sie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_gstatus_uie_0 = io_ptw_16_gstatus_uie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_pmp_0_cfg_l_0 = io_ptw_16_pmp_0_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_16_pmp_0_cfg_a_0 = io_ptw_16_pmp_0_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_pmp_0_cfg_x_0 = io_ptw_16_pmp_0_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_pmp_0_cfg_w_0 = io_ptw_16_pmp_0_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_pmp_0_cfg_r_0 = io_ptw_16_pmp_0_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_16_pmp_0_addr_0 = io_ptw_16_pmp_0_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_16_pmp_0_mask_0 = io_ptw_16_pmp_0_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_pmp_1_cfg_l_0 = io_ptw_16_pmp_1_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_16_pmp_1_cfg_a_0 = io_ptw_16_pmp_1_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_pmp_1_cfg_x_0 = io_ptw_16_pmp_1_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_pmp_1_cfg_w_0 = io_ptw_16_pmp_1_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_pmp_1_cfg_r_0 = io_ptw_16_pmp_1_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_16_pmp_1_addr_0 = io_ptw_16_pmp_1_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_16_pmp_1_mask_0 = io_ptw_16_pmp_1_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_pmp_2_cfg_l_0 = io_ptw_16_pmp_2_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_16_pmp_2_cfg_a_0 = io_ptw_16_pmp_2_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_pmp_2_cfg_x_0 = io_ptw_16_pmp_2_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_pmp_2_cfg_w_0 = io_ptw_16_pmp_2_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_pmp_2_cfg_r_0 = io_ptw_16_pmp_2_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_16_pmp_2_addr_0 = io_ptw_16_pmp_2_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_16_pmp_2_mask_0 = io_ptw_16_pmp_2_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_pmp_3_cfg_l_0 = io_ptw_16_pmp_3_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_16_pmp_3_cfg_a_0 = io_ptw_16_pmp_3_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_pmp_3_cfg_x_0 = io_ptw_16_pmp_3_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_pmp_3_cfg_w_0 = io_ptw_16_pmp_3_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_pmp_3_cfg_r_0 = io_ptw_16_pmp_3_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_16_pmp_3_addr_0 = io_ptw_16_pmp_3_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_16_pmp_3_mask_0 = io_ptw_16_pmp_3_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_pmp_4_cfg_l_0 = io_ptw_16_pmp_4_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_16_pmp_4_cfg_a_0 = io_ptw_16_pmp_4_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_pmp_4_cfg_x_0 = io_ptw_16_pmp_4_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_pmp_4_cfg_w_0 = io_ptw_16_pmp_4_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_pmp_4_cfg_r_0 = io_ptw_16_pmp_4_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_16_pmp_4_addr_0 = io_ptw_16_pmp_4_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_16_pmp_4_mask_0 = io_ptw_16_pmp_4_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_pmp_5_cfg_l_0 = io_ptw_16_pmp_5_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_16_pmp_5_cfg_a_0 = io_ptw_16_pmp_5_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_pmp_5_cfg_x_0 = io_ptw_16_pmp_5_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_pmp_5_cfg_w_0 = io_ptw_16_pmp_5_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_pmp_5_cfg_r_0 = io_ptw_16_pmp_5_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_16_pmp_5_addr_0 = io_ptw_16_pmp_5_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_16_pmp_5_mask_0 = io_ptw_16_pmp_5_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_pmp_6_cfg_l_0 = io_ptw_16_pmp_6_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_16_pmp_6_cfg_a_0 = io_ptw_16_pmp_6_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_pmp_6_cfg_x_0 = io_ptw_16_pmp_6_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_pmp_6_cfg_w_0 = io_ptw_16_pmp_6_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_pmp_6_cfg_r_0 = io_ptw_16_pmp_6_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_16_pmp_6_addr_0 = io_ptw_16_pmp_6_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_16_pmp_6_mask_0 = io_ptw_16_pmp_6_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_pmp_7_cfg_l_0 = io_ptw_16_pmp_7_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_16_pmp_7_cfg_a_0 = io_ptw_16_pmp_7_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_pmp_7_cfg_x_0 = io_ptw_16_pmp_7_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_pmp_7_cfg_w_0 = io_ptw_16_pmp_7_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_pmp_7_cfg_r_0 = io_ptw_16_pmp_7_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_16_pmp_7_addr_0 = io_ptw_16_pmp_7_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_16_pmp_7_mask_0 = io_ptw_16_pmp_7_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_customCSRs_csrs_0_ren_0 = io_ptw_16_customCSRs_csrs_0_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_customCSRs_csrs_0_wen_0 = io_ptw_16_customCSRs_csrs_0_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_16_customCSRs_csrs_0_wdata_0 = io_ptw_16_customCSRs_csrs_0_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_16_customCSRs_csrs_0_value_0 = io_ptw_16_customCSRs_csrs_0_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_customCSRs_csrs_1_ren_0 = io_ptw_16_customCSRs_csrs_1_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_customCSRs_csrs_1_wen_0 = io_ptw_16_customCSRs_csrs_1_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_16_customCSRs_csrs_1_wdata_0 = io_ptw_16_customCSRs_csrs_1_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_16_customCSRs_csrs_1_value_0 = io_ptw_16_customCSRs_csrs_1_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_customCSRs_csrs_2_ren_0 = io_ptw_16_customCSRs_csrs_2_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_customCSRs_csrs_2_wen_0 = io_ptw_16_customCSRs_csrs_2_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_16_customCSRs_csrs_2_wdata_0 = io_ptw_16_customCSRs_csrs_2_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_16_customCSRs_csrs_2_value_0 = io_ptw_16_customCSRs_csrs_2_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_customCSRs_csrs_3_ren_0 = io_ptw_16_customCSRs_csrs_3_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_customCSRs_csrs_3_wen_0 = io_ptw_16_customCSRs_csrs_3_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_16_customCSRs_csrs_3_wdata_0 = io_ptw_16_customCSRs_csrs_3_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_16_customCSRs_csrs_3_value_0 = io_ptw_16_customCSRs_csrs_3_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_req_ready_0 = io_ptw_17_req_ready; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_resp_valid_0 = io_ptw_17_resp_valid; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_resp_bits_ae_ptw_0 = io_ptw_17_resp_bits_ae_ptw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_resp_bits_ae_final_0 = io_ptw_17_resp_bits_ae_final; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_resp_bits_pf_0 = io_ptw_17_resp_bits_pf; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_resp_bits_gf_0 = io_ptw_17_resp_bits_gf; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_resp_bits_hr_0 = io_ptw_17_resp_bits_hr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_resp_bits_hw_0 = io_ptw_17_resp_bits_hw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_resp_bits_hx_0 = io_ptw_17_resp_bits_hx; // @[ZstdCompressor.scala:95:7]
wire [9:0] io_ptw_17_resp_bits_pte_reserved_for_future_0 = io_ptw_17_resp_bits_pte_reserved_for_future; // @[ZstdCompressor.scala:95:7]
wire [43:0] io_ptw_17_resp_bits_pte_ppn_0 = io_ptw_17_resp_bits_pte_ppn; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_17_resp_bits_pte_reserved_for_software_0 = io_ptw_17_resp_bits_pte_reserved_for_software; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_resp_bits_pte_d_0 = io_ptw_17_resp_bits_pte_d; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_resp_bits_pte_a_0 = io_ptw_17_resp_bits_pte_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_resp_bits_pte_g_0 = io_ptw_17_resp_bits_pte_g; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_resp_bits_pte_u_0 = io_ptw_17_resp_bits_pte_u; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_resp_bits_pte_x_0 = io_ptw_17_resp_bits_pte_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_resp_bits_pte_w_0 = io_ptw_17_resp_bits_pte_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_resp_bits_pte_r_0 = io_ptw_17_resp_bits_pte_r; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_resp_bits_pte_v_0 = io_ptw_17_resp_bits_pte_v; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_17_resp_bits_level_0 = io_ptw_17_resp_bits_level; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_resp_bits_homogeneous_0 = io_ptw_17_resp_bits_homogeneous; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_resp_bits_gpa_valid_0 = io_ptw_17_resp_bits_gpa_valid; // @[ZstdCompressor.scala:95:7]
wire [38:0] io_ptw_17_resp_bits_gpa_bits_0 = io_ptw_17_resp_bits_gpa_bits; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_resp_bits_gpa_is_pte_0 = io_ptw_17_resp_bits_gpa_is_pte; // @[ZstdCompressor.scala:95:7]
wire [3:0] io_ptw_17_ptbr_mode_0 = io_ptw_17_ptbr_mode; // @[ZstdCompressor.scala:95:7]
wire [43:0] io_ptw_17_ptbr_ppn_0 = io_ptw_17_ptbr_ppn; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_status_debug_0 = io_ptw_17_status_debug; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_status_cease_0 = io_ptw_17_status_cease; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_status_wfi_0 = io_ptw_17_status_wfi; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_17_status_isa_0 = io_ptw_17_status_isa; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_17_status_dprv_0 = io_ptw_17_status_dprv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_status_dv_0 = io_ptw_17_status_dv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_17_status_prv_0 = io_ptw_17_status_prv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_status_v_0 = io_ptw_17_status_v; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_status_mpv_0 = io_ptw_17_status_mpv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_status_gva_0 = io_ptw_17_status_gva; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_status_tsr_0 = io_ptw_17_status_tsr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_status_tw_0 = io_ptw_17_status_tw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_status_tvm_0 = io_ptw_17_status_tvm; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_status_mxr_0 = io_ptw_17_status_mxr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_status_sum_0 = io_ptw_17_status_sum; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_status_mprv_0 = io_ptw_17_status_mprv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_17_status_fs_0 = io_ptw_17_status_fs; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_17_status_mpp_0 = io_ptw_17_status_mpp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_status_spp_0 = io_ptw_17_status_spp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_status_mpie_0 = io_ptw_17_status_mpie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_status_spie_0 = io_ptw_17_status_spie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_status_mie_0 = io_ptw_17_status_mie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_status_sie_0 = io_ptw_17_status_sie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_hstatus_spvp_0 = io_ptw_17_hstatus_spvp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_hstatus_spv_0 = io_ptw_17_hstatus_spv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_hstatus_gva_0 = io_ptw_17_hstatus_gva; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_gstatus_debug_0 = io_ptw_17_gstatus_debug; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_gstatus_cease_0 = io_ptw_17_gstatus_cease; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_gstatus_wfi_0 = io_ptw_17_gstatus_wfi; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_17_gstatus_isa_0 = io_ptw_17_gstatus_isa; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_17_gstatus_dprv_0 = io_ptw_17_gstatus_dprv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_gstatus_dv_0 = io_ptw_17_gstatus_dv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_17_gstatus_prv_0 = io_ptw_17_gstatus_prv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_gstatus_v_0 = io_ptw_17_gstatus_v; // @[ZstdCompressor.scala:95:7]
wire [22:0] io_ptw_17_gstatus_zero2_0 = io_ptw_17_gstatus_zero2; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_gstatus_mpv_0 = io_ptw_17_gstatus_mpv; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_gstatus_gva_0 = io_ptw_17_gstatus_gva; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_gstatus_mbe_0 = io_ptw_17_gstatus_mbe; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_gstatus_sbe_0 = io_ptw_17_gstatus_sbe; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_17_gstatus_sxl_0 = io_ptw_17_gstatus_sxl; // @[ZstdCompressor.scala:95:7]
wire [7:0] io_ptw_17_gstatus_zero1_0 = io_ptw_17_gstatus_zero1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_gstatus_tsr_0 = io_ptw_17_gstatus_tsr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_gstatus_tw_0 = io_ptw_17_gstatus_tw; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_gstatus_tvm_0 = io_ptw_17_gstatus_tvm; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_gstatus_mxr_0 = io_ptw_17_gstatus_mxr; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_gstatus_sum_0 = io_ptw_17_gstatus_sum; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_gstatus_mprv_0 = io_ptw_17_gstatus_mprv; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_17_gstatus_fs_0 = io_ptw_17_gstatus_fs; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_17_gstatus_mpp_0 = io_ptw_17_gstatus_mpp; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_17_gstatus_vs_0 = io_ptw_17_gstatus_vs; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_gstatus_spp_0 = io_ptw_17_gstatus_spp; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_gstatus_mpie_0 = io_ptw_17_gstatus_mpie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_gstatus_ube_0 = io_ptw_17_gstatus_ube; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_gstatus_spie_0 = io_ptw_17_gstatus_spie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_gstatus_upie_0 = io_ptw_17_gstatus_upie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_gstatus_mie_0 = io_ptw_17_gstatus_mie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_gstatus_hie_0 = io_ptw_17_gstatus_hie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_gstatus_sie_0 = io_ptw_17_gstatus_sie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_gstatus_uie_0 = io_ptw_17_gstatus_uie; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_pmp_0_cfg_l_0 = io_ptw_17_pmp_0_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_17_pmp_0_cfg_a_0 = io_ptw_17_pmp_0_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_pmp_0_cfg_x_0 = io_ptw_17_pmp_0_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_pmp_0_cfg_w_0 = io_ptw_17_pmp_0_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_pmp_0_cfg_r_0 = io_ptw_17_pmp_0_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_17_pmp_0_addr_0 = io_ptw_17_pmp_0_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_17_pmp_0_mask_0 = io_ptw_17_pmp_0_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_pmp_1_cfg_l_0 = io_ptw_17_pmp_1_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_17_pmp_1_cfg_a_0 = io_ptw_17_pmp_1_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_pmp_1_cfg_x_0 = io_ptw_17_pmp_1_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_pmp_1_cfg_w_0 = io_ptw_17_pmp_1_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_pmp_1_cfg_r_0 = io_ptw_17_pmp_1_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_17_pmp_1_addr_0 = io_ptw_17_pmp_1_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_17_pmp_1_mask_0 = io_ptw_17_pmp_1_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_pmp_2_cfg_l_0 = io_ptw_17_pmp_2_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_17_pmp_2_cfg_a_0 = io_ptw_17_pmp_2_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_pmp_2_cfg_x_0 = io_ptw_17_pmp_2_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_pmp_2_cfg_w_0 = io_ptw_17_pmp_2_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_pmp_2_cfg_r_0 = io_ptw_17_pmp_2_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_17_pmp_2_addr_0 = io_ptw_17_pmp_2_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_17_pmp_2_mask_0 = io_ptw_17_pmp_2_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_pmp_3_cfg_l_0 = io_ptw_17_pmp_3_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_17_pmp_3_cfg_a_0 = io_ptw_17_pmp_3_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_pmp_3_cfg_x_0 = io_ptw_17_pmp_3_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_pmp_3_cfg_w_0 = io_ptw_17_pmp_3_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_pmp_3_cfg_r_0 = io_ptw_17_pmp_3_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_17_pmp_3_addr_0 = io_ptw_17_pmp_3_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_17_pmp_3_mask_0 = io_ptw_17_pmp_3_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_pmp_4_cfg_l_0 = io_ptw_17_pmp_4_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_17_pmp_4_cfg_a_0 = io_ptw_17_pmp_4_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_pmp_4_cfg_x_0 = io_ptw_17_pmp_4_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_pmp_4_cfg_w_0 = io_ptw_17_pmp_4_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_pmp_4_cfg_r_0 = io_ptw_17_pmp_4_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_17_pmp_4_addr_0 = io_ptw_17_pmp_4_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_17_pmp_4_mask_0 = io_ptw_17_pmp_4_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_pmp_5_cfg_l_0 = io_ptw_17_pmp_5_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_17_pmp_5_cfg_a_0 = io_ptw_17_pmp_5_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_pmp_5_cfg_x_0 = io_ptw_17_pmp_5_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_pmp_5_cfg_w_0 = io_ptw_17_pmp_5_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_pmp_5_cfg_r_0 = io_ptw_17_pmp_5_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_17_pmp_5_addr_0 = io_ptw_17_pmp_5_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_17_pmp_5_mask_0 = io_ptw_17_pmp_5_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_pmp_6_cfg_l_0 = io_ptw_17_pmp_6_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_17_pmp_6_cfg_a_0 = io_ptw_17_pmp_6_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_pmp_6_cfg_x_0 = io_ptw_17_pmp_6_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_pmp_6_cfg_w_0 = io_ptw_17_pmp_6_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_pmp_6_cfg_r_0 = io_ptw_17_pmp_6_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_17_pmp_6_addr_0 = io_ptw_17_pmp_6_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_17_pmp_6_mask_0 = io_ptw_17_pmp_6_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_pmp_7_cfg_l_0 = io_ptw_17_pmp_7_cfg_l; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_17_pmp_7_cfg_a_0 = io_ptw_17_pmp_7_cfg_a; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_pmp_7_cfg_x_0 = io_ptw_17_pmp_7_cfg_x; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_pmp_7_cfg_w_0 = io_ptw_17_pmp_7_cfg_w; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_pmp_7_cfg_r_0 = io_ptw_17_pmp_7_cfg_r; // @[ZstdCompressor.scala:95:7]
wire [29:0] io_ptw_17_pmp_7_addr_0 = io_ptw_17_pmp_7_addr; // @[ZstdCompressor.scala:95:7]
wire [31:0] io_ptw_17_pmp_7_mask_0 = io_ptw_17_pmp_7_mask; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_customCSRs_csrs_0_ren_0 = io_ptw_17_customCSRs_csrs_0_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_customCSRs_csrs_0_wen_0 = io_ptw_17_customCSRs_csrs_0_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_17_customCSRs_csrs_0_wdata_0 = io_ptw_17_customCSRs_csrs_0_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_17_customCSRs_csrs_0_value_0 = io_ptw_17_customCSRs_csrs_0_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_customCSRs_csrs_1_ren_0 = io_ptw_17_customCSRs_csrs_1_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_customCSRs_csrs_1_wen_0 = io_ptw_17_customCSRs_csrs_1_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_17_customCSRs_csrs_1_wdata_0 = io_ptw_17_customCSRs_csrs_1_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_17_customCSRs_csrs_1_value_0 = io_ptw_17_customCSRs_csrs_1_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_customCSRs_csrs_2_ren_0 = io_ptw_17_customCSRs_csrs_2_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_customCSRs_csrs_2_wen_0 = io_ptw_17_customCSRs_csrs_2_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_17_customCSRs_csrs_2_wdata_0 = io_ptw_17_customCSRs_csrs_2_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_17_customCSRs_csrs_2_value_0 = io_ptw_17_customCSRs_csrs_2_value; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_customCSRs_csrs_3_ren_0 = io_ptw_17_customCSRs_csrs_3_ren; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_customCSRs_csrs_3_wen_0 = io_ptw_17_customCSRs_csrs_3_wen; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_17_customCSRs_csrs_3_wdata_0 = io_ptw_17_customCSRs_csrs_3_wdata; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_17_customCSRs_csrs_3_value_0 = io_ptw_17_customCSRs_csrs_3_value; // @[ZstdCompressor.scala:95:7]
wire [64:0] io_fpu_req_bits_in1 = 65'h0; // @[ZstdCompressor.scala:95:7]
wire [64:0] io_fpu_req_bits_in2 = 65'h0; // @[ZstdCompressor.scala:95:7]
wire [64:0] io_fpu_req_bits_in3 = 65'h0; // @[ZstdCompressor.scala:95:7]
wire [64:0] io_fpu_resp_bits_data = 65'h0; // @[ZstdCompressor.scala:95:7]
wire [2:0] io_fpu_req_bits_rm = 3'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_0_status_sxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_0_status_uxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_0_hstatus_vsxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_0_gstatus_uxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_1_status_sxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_1_status_uxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_1_hstatus_vsxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_1_gstatus_uxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_2_status_sxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_2_status_uxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_2_hstatus_vsxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_2_gstatus_uxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_3_status_sxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_3_status_uxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_3_hstatus_vsxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_3_gstatus_uxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_4_status_sxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_4_status_uxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_4_hstatus_vsxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_4_gstatus_uxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_5_status_sxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_5_status_uxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_5_hstatus_vsxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_5_gstatus_uxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_6_status_sxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_6_status_uxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_6_hstatus_vsxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_6_gstatus_uxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_7_status_sxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_7_status_uxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_7_hstatus_vsxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_7_gstatus_uxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_8_status_sxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_8_status_uxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_8_hstatus_vsxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_8_gstatus_uxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_9_status_sxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_9_status_uxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_9_hstatus_vsxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_9_gstatus_uxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_10_status_sxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_10_status_uxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_10_hstatus_vsxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_10_gstatus_uxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_11_status_sxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_11_status_uxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_11_hstatus_vsxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_11_gstatus_uxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_12_status_sxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_12_status_uxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_12_hstatus_vsxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_12_gstatus_uxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_13_status_sxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_13_status_uxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_13_hstatus_vsxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_13_gstatus_uxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_14_status_sxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_14_status_uxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_14_hstatus_vsxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_14_gstatus_uxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_15_status_sxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_15_status_uxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_15_hstatus_vsxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_15_gstatus_uxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_16_status_sxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_16_status_uxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_16_hstatus_vsxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_16_gstatus_uxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_17_status_sxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_17_status_uxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_17_hstatus_vsxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_17_gstatus_uxl = 2'h2; // @[LazyRoCC.scala:78:14]
wire [31:0] io_mem_s2_paddr = 32'h0; // @[LazyRoCC.scala:78:14]
wire [63:0] io_mem_req_bits_data = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_mem_s1_data_data = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_0_customCSRs_csrs_0_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_0_customCSRs_csrs_1_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_0_customCSRs_csrs_2_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_0_customCSRs_csrs_3_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_1_customCSRs_csrs_0_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_1_customCSRs_csrs_1_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_1_customCSRs_csrs_2_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_1_customCSRs_csrs_3_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_2_customCSRs_csrs_0_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_2_customCSRs_csrs_1_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_2_customCSRs_csrs_2_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_2_customCSRs_csrs_3_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_3_customCSRs_csrs_0_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_3_customCSRs_csrs_1_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_3_customCSRs_csrs_2_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_3_customCSRs_csrs_3_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_4_customCSRs_csrs_0_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_4_customCSRs_csrs_1_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_4_customCSRs_csrs_2_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_4_customCSRs_csrs_3_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_5_customCSRs_csrs_0_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_5_customCSRs_csrs_1_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_5_customCSRs_csrs_2_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_5_customCSRs_csrs_3_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_6_customCSRs_csrs_0_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_6_customCSRs_csrs_1_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_6_customCSRs_csrs_2_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_6_customCSRs_csrs_3_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_7_customCSRs_csrs_0_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_7_customCSRs_csrs_1_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_7_customCSRs_csrs_2_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_7_customCSRs_csrs_3_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_8_customCSRs_csrs_0_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_8_customCSRs_csrs_1_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_8_customCSRs_csrs_2_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_8_customCSRs_csrs_3_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_9_customCSRs_csrs_0_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_9_customCSRs_csrs_1_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_9_customCSRs_csrs_2_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_9_customCSRs_csrs_3_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_10_customCSRs_csrs_0_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_10_customCSRs_csrs_1_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_10_customCSRs_csrs_2_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_10_customCSRs_csrs_3_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_11_customCSRs_csrs_0_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_11_customCSRs_csrs_1_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_11_customCSRs_csrs_2_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_11_customCSRs_csrs_3_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_12_customCSRs_csrs_0_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_12_customCSRs_csrs_1_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_12_customCSRs_csrs_2_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_12_customCSRs_csrs_3_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_13_customCSRs_csrs_0_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_13_customCSRs_csrs_1_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_13_customCSRs_csrs_2_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_13_customCSRs_csrs_3_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_14_customCSRs_csrs_0_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_14_customCSRs_csrs_1_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_14_customCSRs_csrs_2_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_14_customCSRs_csrs_3_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_15_customCSRs_csrs_0_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_15_customCSRs_csrs_1_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_15_customCSRs_csrs_2_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_15_customCSRs_csrs_3_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_16_customCSRs_csrs_0_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_16_customCSRs_csrs_1_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_16_customCSRs_csrs_2_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_16_customCSRs_csrs_3_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_17_customCSRs_csrs_0_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_17_customCSRs_csrs_1_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_17_customCSRs_csrs_2_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_ptw_17_customCSRs_csrs_3_sdata = 64'h0; // @[ZstdCompressor.scala:95:7]
wire [39:0] io_mem_req_bits_addr = 40'h0; // @[ZstdCompressor.scala:95:7]
wire [39:0] io_mem_s2_gpa = 40'h0; // @[ZstdCompressor.scala:95:7]
wire [4:0] io_mem_req_bits_cmd = 5'h0; // @[ZstdCompressor.scala:95:7]
wire [4:0] io_ptw_0_hstatus_zero1 = 5'h0; // @[ZstdCompressor.scala:95:7]
wire [4:0] io_ptw_1_hstatus_zero1 = 5'h0; // @[ZstdCompressor.scala:95:7]
wire [4:0] io_ptw_2_hstatus_zero1 = 5'h0; // @[ZstdCompressor.scala:95:7]
wire [4:0] io_ptw_3_hstatus_zero1 = 5'h0; // @[ZstdCompressor.scala:95:7]
wire [4:0] io_ptw_4_hstatus_zero1 = 5'h0; // @[ZstdCompressor.scala:95:7]
wire [4:0] io_ptw_5_hstatus_zero1 = 5'h0; // @[ZstdCompressor.scala:95:7]
wire [4:0] io_ptw_6_hstatus_zero1 = 5'h0; // @[ZstdCompressor.scala:95:7]
wire [4:0] io_ptw_7_hstatus_zero1 = 5'h0; // @[ZstdCompressor.scala:95:7]
wire [4:0] io_ptw_8_hstatus_zero1 = 5'h0; // @[ZstdCompressor.scala:95:7]
wire [4:0] io_ptw_9_hstatus_zero1 = 5'h0; // @[ZstdCompressor.scala:95:7]
wire [4:0] io_ptw_10_hstatus_zero1 = 5'h0; // @[ZstdCompressor.scala:95:7]
wire [4:0] io_ptw_11_hstatus_zero1 = 5'h0; // @[ZstdCompressor.scala:95:7]
wire [4:0] io_ptw_12_hstatus_zero1 = 5'h0; // @[ZstdCompressor.scala:95:7]
wire [4:0] io_ptw_13_hstatus_zero1 = 5'h0; // @[ZstdCompressor.scala:95:7]
wire [4:0] io_ptw_14_hstatus_zero1 = 5'h0; // @[ZstdCompressor.scala:95:7]
wire [4:0] io_ptw_15_hstatus_zero1 = 5'h0; // @[ZstdCompressor.scala:95:7]
wire [4:0] io_ptw_16_hstatus_zero1 = 5'h0; // @[ZstdCompressor.scala:95:7]
wire [4:0] io_ptw_17_hstatus_zero1 = 5'h0; // @[ZstdCompressor.scala:95:7]
wire [4:0] io_fpu_resp_bits_exc = 5'h0; // @[ZstdCompressor.scala:95:7]
wire [5:0] io_ptw_0_hstatus_vgein = 6'h0; // @[LazyRoCC.scala:78:14]
wire [5:0] io_ptw_1_hstatus_vgein = 6'h0; // @[LazyRoCC.scala:78:14]
wire [5:0] io_ptw_2_hstatus_vgein = 6'h0; // @[LazyRoCC.scala:78:14]
wire [5:0] io_ptw_3_hstatus_vgein = 6'h0; // @[LazyRoCC.scala:78:14]
wire [5:0] io_ptw_4_hstatus_vgein = 6'h0; // @[LazyRoCC.scala:78:14]
wire [5:0] io_ptw_5_hstatus_vgein = 6'h0; // @[LazyRoCC.scala:78:14]
wire [5:0] io_ptw_6_hstatus_vgein = 6'h0; // @[LazyRoCC.scala:78:14]
wire [5:0] io_ptw_7_hstatus_vgein = 6'h0; // @[LazyRoCC.scala:78:14]
wire [5:0] io_ptw_8_hstatus_vgein = 6'h0; // @[LazyRoCC.scala:78:14]
wire [5:0] io_ptw_9_hstatus_vgein = 6'h0; // @[LazyRoCC.scala:78:14]
wire [5:0] io_ptw_10_hstatus_vgein = 6'h0; // @[LazyRoCC.scala:78:14]
wire [5:0] io_ptw_11_hstatus_vgein = 6'h0; // @[LazyRoCC.scala:78:14]
wire [5:0] io_ptw_12_hstatus_vgein = 6'h0; // @[LazyRoCC.scala:78:14]
wire [5:0] io_ptw_13_hstatus_vgein = 6'h0; // @[LazyRoCC.scala:78:14]
wire [5:0] io_ptw_14_hstatus_vgein = 6'h0; // @[LazyRoCC.scala:78:14]
wire [5:0] io_ptw_15_hstatus_vgein = 6'h0; // @[LazyRoCC.scala:78:14]
wire [5:0] io_ptw_16_hstatus_vgein = 6'h0; // @[LazyRoCC.scala:78:14]
wire [5:0] io_ptw_17_hstatus_vgein = 6'h0; // @[LazyRoCC.scala:78:14]
wire [8:0] io_ptw_0_hstatus_zero5 = 9'h0; // @[LazyRoCC.scala:78:14]
wire [8:0] io_ptw_1_hstatus_zero5 = 9'h0; // @[LazyRoCC.scala:78:14]
wire [8:0] io_ptw_2_hstatus_zero5 = 9'h0; // @[LazyRoCC.scala:78:14]
wire [8:0] io_ptw_3_hstatus_zero5 = 9'h0; // @[LazyRoCC.scala:78:14]
wire [8:0] io_ptw_4_hstatus_zero5 = 9'h0; // @[LazyRoCC.scala:78:14]
wire [8:0] io_ptw_5_hstatus_zero5 = 9'h0; // @[LazyRoCC.scala:78:14]
wire [8:0] io_ptw_6_hstatus_zero5 = 9'h0; // @[LazyRoCC.scala:78:14]
wire [8:0] io_ptw_7_hstatus_zero5 = 9'h0; // @[LazyRoCC.scala:78:14]
wire [8:0] io_ptw_8_hstatus_zero5 = 9'h0; // @[LazyRoCC.scala:78:14]
wire [8:0] io_ptw_9_hstatus_zero5 = 9'h0; // @[LazyRoCC.scala:78:14]
wire [8:0] io_ptw_10_hstatus_zero5 = 9'h0; // @[LazyRoCC.scala:78:14]
wire [8:0] io_ptw_11_hstatus_zero5 = 9'h0; // @[LazyRoCC.scala:78:14]
wire [8:0] io_ptw_12_hstatus_zero5 = 9'h0; // @[LazyRoCC.scala:78:14]
wire [8:0] io_ptw_13_hstatus_zero5 = 9'h0; // @[LazyRoCC.scala:78:14]
wire [8:0] io_ptw_14_hstatus_zero5 = 9'h0; // @[LazyRoCC.scala:78:14]
wire [8:0] io_ptw_15_hstatus_zero5 = 9'h0; // @[LazyRoCC.scala:78:14]
wire [8:0] io_ptw_16_hstatus_zero5 = 9'h0; // @[LazyRoCC.scala:78:14]
wire [8:0] io_ptw_17_hstatus_zero5 = 9'h0; // @[LazyRoCC.scala:78:14]
wire [29:0] io_ptw_0_hstatus_zero6 = 30'h0; // @[LazyRoCC.scala:78:14]
wire [29:0] io_ptw_1_hstatus_zero6 = 30'h0; // @[LazyRoCC.scala:78:14]
wire [29:0] io_ptw_2_hstatus_zero6 = 30'h0; // @[LazyRoCC.scala:78:14]
wire [29:0] io_ptw_3_hstatus_zero6 = 30'h0; // @[LazyRoCC.scala:78:14]
wire [29:0] io_ptw_4_hstatus_zero6 = 30'h0; // @[LazyRoCC.scala:78:14]
wire [29:0] io_ptw_5_hstatus_zero6 = 30'h0; // @[LazyRoCC.scala:78:14]
wire [29:0] io_ptw_6_hstatus_zero6 = 30'h0; // @[LazyRoCC.scala:78:14]
wire [29:0] io_ptw_7_hstatus_zero6 = 30'h0; // @[LazyRoCC.scala:78:14]
wire [29:0] io_ptw_8_hstatus_zero6 = 30'h0; // @[LazyRoCC.scala:78:14]
wire [29:0] io_ptw_9_hstatus_zero6 = 30'h0; // @[LazyRoCC.scala:78:14]
wire [29:0] io_ptw_10_hstatus_zero6 = 30'h0; // @[LazyRoCC.scala:78:14]
wire [29:0] io_ptw_11_hstatus_zero6 = 30'h0; // @[LazyRoCC.scala:78:14]
wire [29:0] io_ptw_12_hstatus_zero6 = 30'h0; // @[LazyRoCC.scala:78:14]
wire [29:0] io_ptw_13_hstatus_zero6 = 30'h0; // @[LazyRoCC.scala:78:14]
wire [29:0] io_ptw_14_hstatus_zero6 = 30'h0; // @[LazyRoCC.scala:78:14]
wire [29:0] io_ptw_15_hstatus_zero6 = 30'h0; // @[LazyRoCC.scala:78:14]
wire [29:0] io_ptw_16_hstatus_zero6 = 30'h0; // @[LazyRoCC.scala:78:14]
wire [29:0] io_ptw_17_hstatus_zero6 = 30'h0; // @[LazyRoCC.scala:78:14]
wire [1:0] io_mem_req_bits_size = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_mem_req_bits_dprv = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_0_status_vs = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_0_hstatus_zero3 = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_0_hstatus_zero2 = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_0_pmp_0_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_0_pmp_1_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_0_pmp_2_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_0_pmp_3_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_0_pmp_4_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_0_pmp_5_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_0_pmp_6_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_0_pmp_7_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_1_status_vs = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_1_hstatus_zero3 = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_1_hstatus_zero2 = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_1_pmp_0_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_1_pmp_1_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_1_pmp_2_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_1_pmp_3_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_1_pmp_4_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_1_pmp_5_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_1_pmp_6_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_1_pmp_7_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_2_status_vs = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_2_hstatus_zero3 = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_2_hstatus_zero2 = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_2_pmp_0_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_2_pmp_1_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_2_pmp_2_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_2_pmp_3_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_2_pmp_4_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_2_pmp_5_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_2_pmp_6_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_2_pmp_7_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_3_status_vs = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_3_hstatus_zero3 = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_3_hstatus_zero2 = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_3_pmp_0_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_3_pmp_1_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_3_pmp_2_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_3_pmp_3_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_3_pmp_4_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_3_pmp_5_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_3_pmp_6_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_3_pmp_7_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_4_status_vs = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_4_hstatus_zero3 = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_4_hstatus_zero2 = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_4_pmp_0_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_4_pmp_1_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_4_pmp_2_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_4_pmp_3_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_4_pmp_4_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_4_pmp_5_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_4_pmp_6_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_4_pmp_7_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_5_status_vs = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_5_hstatus_zero3 = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_5_hstatus_zero2 = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_5_pmp_0_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_5_pmp_1_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_5_pmp_2_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_5_pmp_3_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_5_pmp_4_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_5_pmp_5_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_5_pmp_6_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_5_pmp_7_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_6_status_vs = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_6_hstatus_zero3 = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_6_hstatus_zero2 = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_6_pmp_0_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_6_pmp_1_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_6_pmp_2_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_6_pmp_3_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_6_pmp_4_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_6_pmp_5_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_6_pmp_6_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_6_pmp_7_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_7_status_vs = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_7_hstatus_zero3 = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_7_hstatus_zero2 = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_7_pmp_0_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_7_pmp_1_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_7_pmp_2_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_7_pmp_3_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_7_pmp_4_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_7_pmp_5_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_7_pmp_6_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_7_pmp_7_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_8_status_vs = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_8_hstatus_zero3 = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_8_hstatus_zero2 = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_8_pmp_0_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_8_pmp_1_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_8_pmp_2_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_8_pmp_3_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_8_pmp_4_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_8_pmp_5_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_8_pmp_6_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_8_pmp_7_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_9_status_vs = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_9_hstatus_zero3 = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_9_hstatus_zero2 = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_9_pmp_0_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_9_pmp_1_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_9_pmp_2_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_9_pmp_3_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_9_pmp_4_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_9_pmp_5_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_9_pmp_6_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_9_pmp_7_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_10_status_vs = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_10_hstatus_zero3 = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_10_hstatus_zero2 = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_10_pmp_0_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_10_pmp_1_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_10_pmp_2_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_10_pmp_3_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_10_pmp_4_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_10_pmp_5_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_10_pmp_6_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_10_pmp_7_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_11_status_vs = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_11_hstatus_zero3 = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_11_hstatus_zero2 = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_11_pmp_0_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_11_pmp_1_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_11_pmp_2_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_11_pmp_3_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_11_pmp_4_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_11_pmp_5_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_11_pmp_6_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_11_pmp_7_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_12_status_vs = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_12_hstatus_zero3 = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_12_hstatus_zero2 = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_12_pmp_0_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_12_pmp_1_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_12_pmp_2_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_12_pmp_3_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_12_pmp_4_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_12_pmp_5_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_12_pmp_6_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_12_pmp_7_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_13_status_vs = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_13_hstatus_zero3 = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_13_hstatus_zero2 = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_13_pmp_0_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_13_pmp_1_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_13_pmp_2_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_13_pmp_3_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_13_pmp_4_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_13_pmp_5_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_13_pmp_6_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_13_pmp_7_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_14_status_vs = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_14_hstatus_zero3 = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_14_hstatus_zero2 = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_14_pmp_0_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_14_pmp_1_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_14_pmp_2_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_14_pmp_3_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_14_pmp_4_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_14_pmp_5_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_14_pmp_6_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_14_pmp_7_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_15_status_vs = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_15_hstatus_zero3 = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_15_hstatus_zero2 = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_15_pmp_0_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_15_pmp_1_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_15_pmp_2_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_15_pmp_3_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_15_pmp_4_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_15_pmp_5_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_15_pmp_6_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_15_pmp_7_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_16_status_vs = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_16_hstatus_zero3 = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_16_hstatus_zero2 = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_16_pmp_0_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_16_pmp_1_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_16_pmp_2_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_16_pmp_3_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_16_pmp_4_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_16_pmp_5_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_16_pmp_6_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_16_pmp_7_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_17_status_vs = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_17_hstatus_zero3 = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_17_hstatus_zero2 = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_17_pmp_0_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_17_pmp_1_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_17_pmp_2_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_17_pmp_3_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_17_pmp_4_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_17_pmp_5_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_17_pmp_6_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_17_pmp_7_cfg_res = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_fpu_req_bits_typeTagIn = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_fpu_req_bits_typeTagOut = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_fpu_req_bits_fmaCmd = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_fpu_req_bits_typ = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_fpu_req_bits_fmt = 2'h0; // @[ZstdCompressor.scala:95:7]
wire [1:0] io_ptw_0_status_xs = 2'h3; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_0_gstatus_xs = 2'h3; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_1_status_xs = 2'h3; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_1_gstatus_xs = 2'h3; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_2_status_xs = 2'h3; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_2_gstatus_xs = 2'h3; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_3_status_xs = 2'h3; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_3_gstatus_xs = 2'h3; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_4_status_xs = 2'h3; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_4_gstatus_xs = 2'h3; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_5_status_xs = 2'h3; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_5_gstatus_xs = 2'h3; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_6_status_xs = 2'h3; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_6_gstatus_xs = 2'h3; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_7_status_xs = 2'h3; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_7_gstatus_xs = 2'h3; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_8_status_xs = 2'h3; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_8_gstatus_xs = 2'h3; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_9_status_xs = 2'h3; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_9_gstatus_xs = 2'h3; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_10_status_xs = 2'h3; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_10_gstatus_xs = 2'h3; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_11_status_xs = 2'h3; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_11_gstatus_xs = 2'h3; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_12_status_xs = 2'h3; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_12_gstatus_xs = 2'h3; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_13_status_xs = 2'h3; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_13_gstatus_xs = 2'h3; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_14_status_xs = 2'h3; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_14_gstatus_xs = 2'h3; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_15_status_xs = 2'h3; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_15_gstatus_xs = 2'h3; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_16_status_xs = 2'h3; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_16_gstatus_xs = 2'h3; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_17_status_xs = 2'h3; // @[LazyRoCC.scala:78:14]
wire [1:0] io_ptw_17_gstatus_xs = 2'h3; // @[LazyRoCC.scala:78:14]
wire [7:0] io_mem_req_bits_tag = 8'h0; // @[ZstdCompressor.scala:95:7]
wire [7:0] io_mem_req_bits_mask = 8'h0; // @[ZstdCompressor.scala:95:7]
wire [7:0] io_mem_s1_data_mask = 8'h0; // @[ZstdCompressor.scala:95:7]
wire [7:0] io_ptw_0_status_zero1 = 8'h0; // @[ZstdCompressor.scala:95:7]
wire [7:0] io_ptw_1_status_zero1 = 8'h0; // @[ZstdCompressor.scala:95:7]
wire [7:0] io_ptw_2_status_zero1 = 8'h0; // @[ZstdCompressor.scala:95:7]
wire [7:0] io_ptw_3_status_zero1 = 8'h0; // @[ZstdCompressor.scala:95:7]
wire [7:0] io_ptw_4_status_zero1 = 8'h0; // @[ZstdCompressor.scala:95:7]
wire [7:0] io_ptw_5_status_zero1 = 8'h0; // @[ZstdCompressor.scala:95:7]
wire [7:0] io_ptw_6_status_zero1 = 8'h0; // @[ZstdCompressor.scala:95:7]
wire [7:0] io_ptw_7_status_zero1 = 8'h0; // @[ZstdCompressor.scala:95:7]
wire [7:0] io_ptw_8_status_zero1 = 8'h0; // @[ZstdCompressor.scala:95:7]
wire [7:0] io_ptw_9_status_zero1 = 8'h0; // @[ZstdCompressor.scala:95:7]
wire [7:0] io_ptw_10_status_zero1 = 8'h0; // @[ZstdCompressor.scala:95:7]
wire [7:0] io_ptw_11_status_zero1 = 8'h0; // @[ZstdCompressor.scala:95:7]
wire [7:0] io_ptw_12_status_zero1 = 8'h0; // @[ZstdCompressor.scala:95:7]
wire [7:0] io_ptw_13_status_zero1 = 8'h0; // @[ZstdCompressor.scala:95:7]
wire [7:0] io_ptw_14_status_zero1 = 8'h0; // @[ZstdCompressor.scala:95:7]
wire [7:0] io_ptw_15_status_zero1 = 8'h0; // @[ZstdCompressor.scala:95:7]
wire [7:0] io_ptw_16_status_zero1 = 8'h0; // @[ZstdCompressor.scala:95:7]
wire [7:0] io_ptw_17_status_zero1 = 8'h0; // @[ZstdCompressor.scala:95:7]
wire [22:0] io_ptw_0_status_zero2 = 23'h0; // @[LazyRoCC.scala:78:14]
wire [22:0] io_ptw_1_status_zero2 = 23'h0; // @[LazyRoCC.scala:78:14]
wire [22:0] io_ptw_2_status_zero2 = 23'h0; // @[LazyRoCC.scala:78:14]
wire [22:0] io_ptw_3_status_zero2 = 23'h0; // @[LazyRoCC.scala:78:14]
wire [22:0] io_ptw_4_status_zero2 = 23'h0; // @[LazyRoCC.scala:78:14]
wire [22:0] io_ptw_5_status_zero2 = 23'h0; // @[LazyRoCC.scala:78:14]
wire [22:0] io_ptw_6_status_zero2 = 23'h0; // @[LazyRoCC.scala:78:14]
wire [22:0] io_ptw_7_status_zero2 = 23'h0; // @[LazyRoCC.scala:78:14]
wire [22:0] io_ptw_8_status_zero2 = 23'h0; // @[LazyRoCC.scala:78:14]
wire [22:0] io_ptw_9_status_zero2 = 23'h0; // @[LazyRoCC.scala:78:14]
wire [22:0] io_ptw_10_status_zero2 = 23'h0; // @[LazyRoCC.scala:78:14]
wire [22:0] io_ptw_11_status_zero2 = 23'h0; // @[LazyRoCC.scala:78:14]
wire [22:0] io_ptw_12_status_zero2 = 23'h0; // @[LazyRoCC.scala:78:14]
wire [22:0] io_ptw_13_status_zero2 = 23'h0; // @[LazyRoCC.scala:78:14]
wire [22:0] io_ptw_14_status_zero2 = 23'h0; // @[LazyRoCC.scala:78:14]
wire [22:0] io_ptw_15_status_zero2 = 23'h0; // @[LazyRoCC.scala:78:14]
wire [22:0] io_ptw_16_status_zero2 = 23'h0; // @[LazyRoCC.scala:78:14]
wire [22:0] io_ptw_17_status_zero2 = 23'h0; // @[LazyRoCC.scala:78:14]
wire io_mem_keep_clock_enabled = 1'h1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_req_bits_valid = 1'h1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_status_sd = 1'h1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_gstatus_sd = 1'h1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_req_bits_valid = 1'h1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_status_sd = 1'h1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_gstatus_sd = 1'h1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_req_bits_valid = 1'h1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_status_sd = 1'h1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_gstatus_sd = 1'h1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_req_bits_valid = 1'h1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_status_sd = 1'h1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_gstatus_sd = 1'h1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_req_bits_valid = 1'h1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_status_sd = 1'h1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_gstatus_sd = 1'h1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_req_bits_valid = 1'h1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_status_sd = 1'h1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_gstatus_sd = 1'h1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_req_bits_valid = 1'h1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_status_sd = 1'h1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_gstatus_sd = 1'h1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_req_bits_valid = 1'h1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_status_sd = 1'h1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_gstatus_sd = 1'h1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_req_bits_valid = 1'h1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_status_sd = 1'h1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_gstatus_sd = 1'h1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_req_bits_valid = 1'h1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_status_sd = 1'h1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_gstatus_sd = 1'h1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_req_bits_valid = 1'h1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_status_sd = 1'h1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_gstatus_sd = 1'h1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_req_bits_valid = 1'h1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_status_sd = 1'h1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_gstatus_sd = 1'h1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_req_bits_valid = 1'h1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_status_sd = 1'h1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_gstatus_sd = 1'h1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_req_bits_valid = 1'h1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_status_sd = 1'h1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_gstatus_sd = 1'h1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_req_bits_valid = 1'h1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_status_sd = 1'h1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_gstatus_sd = 1'h1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_req_bits_valid = 1'h1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_status_sd = 1'h1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_gstatus_sd = 1'h1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_req_bits_valid = 1'h1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_status_sd = 1'h1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_gstatus_sd = 1'h1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_req_bits_valid = 1'h1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_status_sd = 1'h1; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_gstatus_sd = 1'h1; // @[ZstdCompressor.scala:95:7]
wire [43:0] io_ptw_0_hgatp_ppn = 44'h0; // @[LazyRoCC.scala:78:14]
wire [43:0] io_ptw_0_vsatp_ppn = 44'h0; // @[LazyRoCC.scala:78:14]
wire [43:0] io_ptw_1_hgatp_ppn = 44'h0; // @[LazyRoCC.scala:78:14]
wire [43:0] io_ptw_1_vsatp_ppn = 44'h0; // @[LazyRoCC.scala:78:14]
wire [43:0] io_ptw_2_hgatp_ppn = 44'h0; // @[LazyRoCC.scala:78:14]
wire [43:0] io_ptw_2_vsatp_ppn = 44'h0; // @[LazyRoCC.scala:78:14]
wire [43:0] io_ptw_3_hgatp_ppn = 44'h0; // @[LazyRoCC.scala:78:14]
wire [43:0] io_ptw_3_vsatp_ppn = 44'h0; // @[LazyRoCC.scala:78:14]
wire [43:0] io_ptw_4_hgatp_ppn = 44'h0; // @[LazyRoCC.scala:78:14]
wire [43:0] io_ptw_4_vsatp_ppn = 44'h0; // @[LazyRoCC.scala:78:14]
wire [43:0] io_ptw_5_hgatp_ppn = 44'h0; // @[LazyRoCC.scala:78:14]
wire [43:0] io_ptw_5_vsatp_ppn = 44'h0; // @[LazyRoCC.scala:78:14]
wire [43:0] io_ptw_6_hgatp_ppn = 44'h0; // @[LazyRoCC.scala:78:14]
wire [43:0] io_ptw_6_vsatp_ppn = 44'h0; // @[LazyRoCC.scala:78:14]
wire [43:0] io_ptw_7_hgatp_ppn = 44'h0; // @[LazyRoCC.scala:78:14]
wire [43:0] io_ptw_7_vsatp_ppn = 44'h0; // @[LazyRoCC.scala:78:14]
wire [43:0] io_ptw_8_hgatp_ppn = 44'h0; // @[LazyRoCC.scala:78:14]
wire [43:0] io_ptw_8_vsatp_ppn = 44'h0; // @[LazyRoCC.scala:78:14]
wire [43:0] io_ptw_9_hgatp_ppn = 44'h0; // @[LazyRoCC.scala:78:14]
wire [43:0] io_ptw_9_vsatp_ppn = 44'h0; // @[LazyRoCC.scala:78:14]
wire [43:0] io_ptw_10_hgatp_ppn = 44'h0; // @[LazyRoCC.scala:78:14]
wire [43:0] io_ptw_10_vsatp_ppn = 44'h0; // @[LazyRoCC.scala:78:14]
wire [43:0] io_ptw_11_hgatp_ppn = 44'h0; // @[LazyRoCC.scala:78:14]
wire [43:0] io_ptw_11_vsatp_ppn = 44'h0; // @[LazyRoCC.scala:78:14]
wire [43:0] io_ptw_12_hgatp_ppn = 44'h0; // @[LazyRoCC.scala:78:14]
wire [43:0] io_ptw_12_vsatp_ppn = 44'h0; // @[LazyRoCC.scala:78:14]
wire [43:0] io_ptw_13_hgatp_ppn = 44'h0; // @[LazyRoCC.scala:78:14]
wire [43:0] io_ptw_13_vsatp_ppn = 44'h0; // @[LazyRoCC.scala:78:14]
wire [43:0] io_ptw_14_hgatp_ppn = 44'h0; // @[LazyRoCC.scala:78:14]
wire [43:0] io_ptw_14_vsatp_ppn = 44'h0; // @[LazyRoCC.scala:78:14]
wire [43:0] io_ptw_15_hgatp_ppn = 44'h0; // @[LazyRoCC.scala:78:14]
wire [43:0] io_ptw_15_vsatp_ppn = 44'h0; // @[LazyRoCC.scala:78:14]
wire [43:0] io_ptw_16_hgatp_ppn = 44'h0; // @[LazyRoCC.scala:78:14]
wire [43:0] io_ptw_16_vsatp_ppn = 44'h0; // @[LazyRoCC.scala:78:14]
wire [43:0] io_ptw_17_hgatp_ppn = 44'h0; // @[LazyRoCC.scala:78:14]
wire [43:0] io_ptw_17_vsatp_ppn = 44'h0; // @[LazyRoCC.scala:78:14]
wire [3:0] io_ptw_0_hgatp_mode = 4'h0; // @[LazyRoCC.scala:78:14]
wire [3:0] io_ptw_0_vsatp_mode = 4'h0; // @[LazyRoCC.scala:78:14]
wire [3:0] io_ptw_1_hgatp_mode = 4'h0; // @[LazyRoCC.scala:78:14]
wire [3:0] io_ptw_1_vsatp_mode = 4'h0; // @[LazyRoCC.scala:78:14]
wire [3:0] io_ptw_2_hgatp_mode = 4'h0; // @[LazyRoCC.scala:78:14]
wire [3:0] io_ptw_2_vsatp_mode = 4'h0; // @[LazyRoCC.scala:78:14]
wire [3:0] io_ptw_3_hgatp_mode = 4'h0; // @[LazyRoCC.scala:78:14]
wire [3:0] io_ptw_3_vsatp_mode = 4'h0; // @[LazyRoCC.scala:78:14]
wire [3:0] io_ptw_4_hgatp_mode = 4'h0; // @[LazyRoCC.scala:78:14]
wire [3:0] io_ptw_4_vsatp_mode = 4'h0; // @[LazyRoCC.scala:78:14]
wire [3:0] io_ptw_5_hgatp_mode = 4'h0; // @[LazyRoCC.scala:78:14]
wire [3:0] io_ptw_5_vsatp_mode = 4'h0; // @[LazyRoCC.scala:78:14]
wire [3:0] io_ptw_6_hgatp_mode = 4'h0; // @[LazyRoCC.scala:78:14]
wire [3:0] io_ptw_6_vsatp_mode = 4'h0; // @[LazyRoCC.scala:78:14]
wire [3:0] io_ptw_7_hgatp_mode = 4'h0; // @[LazyRoCC.scala:78:14]
wire [3:0] io_ptw_7_vsatp_mode = 4'h0; // @[LazyRoCC.scala:78:14]
wire [3:0] io_ptw_8_hgatp_mode = 4'h0; // @[LazyRoCC.scala:78:14]
wire [3:0] io_ptw_8_vsatp_mode = 4'h0; // @[LazyRoCC.scala:78:14]
wire [3:0] io_ptw_9_hgatp_mode = 4'h0; // @[LazyRoCC.scala:78:14]
wire [3:0] io_ptw_9_vsatp_mode = 4'h0; // @[LazyRoCC.scala:78:14]
wire [3:0] io_ptw_10_hgatp_mode = 4'h0; // @[LazyRoCC.scala:78:14]
wire [3:0] io_ptw_10_vsatp_mode = 4'h0; // @[LazyRoCC.scala:78:14]
wire [3:0] io_ptw_11_hgatp_mode = 4'h0; // @[LazyRoCC.scala:78:14]
wire [3:0] io_ptw_11_vsatp_mode = 4'h0; // @[LazyRoCC.scala:78:14]
wire [3:0] io_ptw_12_hgatp_mode = 4'h0; // @[LazyRoCC.scala:78:14]
wire [3:0] io_ptw_12_vsatp_mode = 4'h0; // @[LazyRoCC.scala:78:14]
wire [3:0] io_ptw_13_hgatp_mode = 4'h0; // @[LazyRoCC.scala:78:14]
wire [3:0] io_ptw_13_vsatp_mode = 4'h0; // @[LazyRoCC.scala:78:14]
wire [3:0] io_ptw_14_hgatp_mode = 4'h0; // @[LazyRoCC.scala:78:14]
wire [3:0] io_ptw_14_vsatp_mode = 4'h0; // @[LazyRoCC.scala:78:14]
wire [3:0] io_ptw_15_hgatp_mode = 4'h0; // @[LazyRoCC.scala:78:14]
wire [3:0] io_ptw_15_vsatp_mode = 4'h0; // @[LazyRoCC.scala:78:14]
wire [3:0] io_ptw_16_hgatp_mode = 4'h0; // @[LazyRoCC.scala:78:14]
wire [3:0] io_ptw_16_vsatp_mode = 4'h0; // @[LazyRoCC.scala:78:14]
wire [3:0] io_ptw_17_hgatp_mode = 4'h0; // @[LazyRoCC.scala:78:14]
wire [3:0] io_ptw_17_vsatp_mode = 4'h0; // @[LazyRoCC.scala:78:14]
wire [15:0] io_ptw_0_ptbr_asid = 16'h0; // @[LazyRoCC.scala:78:14]
wire [15:0] io_ptw_0_hgatp_asid = 16'h0; // @[LazyRoCC.scala:78:14]
wire [15:0] io_ptw_0_vsatp_asid = 16'h0; // @[LazyRoCC.scala:78:14]
wire [15:0] io_ptw_1_ptbr_asid = 16'h0; // @[LazyRoCC.scala:78:14]
wire [15:0] io_ptw_1_hgatp_asid = 16'h0; // @[LazyRoCC.scala:78:14]
wire [15:0] io_ptw_1_vsatp_asid = 16'h0; // @[LazyRoCC.scala:78:14]
wire [15:0] io_ptw_2_ptbr_asid = 16'h0; // @[LazyRoCC.scala:78:14]
wire [15:0] io_ptw_2_hgatp_asid = 16'h0; // @[LazyRoCC.scala:78:14]
wire [15:0] io_ptw_2_vsatp_asid = 16'h0; // @[LazyRoCC.scala:78:14]
wire [15:0] io_ptw_3_ptbr_asid = 16'h0; // @[LazyRoCC.scala:78:14]
wire [15:0] io_ptw_3_hgatp_asid = 16'h0; // @[LazyRoCC.scala:78:14]
wire [15:0] io_ptw_3_vsatp_asid = 16'h0; // @[LazyRoCC.scala:78:14]
wire [15:0] io_ptw_4_ptbr_asid = 16'h0; // @[LazyRoCC.scala:78:14]
wire [15:0] io_ptw_4_hgatp_asid = 16'h0; // @[LazyRoCC.scala:78:14]
wire [15:0] io_ptw_4_vsatp_asid = 16'h0; // @[LazyRoCC.scala:78:14]
wire [15:0] io_ptw_5_ptbr_asid = 16'h0; // @[LazyRoCC.scala:78:14]
wire [15:0] io_ptw_5_hgatp_asid = 16'h0; // @[LazyRoCC.scala:78:14]
wire [15:0] io_ptw_5_vsatp_asid = 16'h0; // @[LazyRoCC.scala:78:14]
wire [15:0] io_ptw_6_ptbr_asid = 16'h0; // @[LazyRoCC.scala:78:14]
wire [15:0] io_ptw_6_hgatp_asid = 16'h0; // @[LazyRoCC.scala:78:14]
wire [15:0] io_ptw_6_vsatp_asid = 16'h0; // @[LazyRoCC.scala:78:14]
wire [15:0] io_ptw_7_ptbr_asid = 16'h0; // @[LazyRoCC.scala:78:14]
wire [15:0] io_ptw_7_hgatp_asid = 16'h0; // @[LazyRoCC.scala:78:14]
wire [15:0] io_ptw_7_vsatp_asid = 16'h0; // @[LazyRoCC.scala:78:14]
wire [15:0] io_ptw_8_ptbr_asid = 16'h0; // @[LazyRoCC.scala:78:14]
wire [15:0] io_ptw_8_hgatp_asid = 16'h0; // @[LazyRoCC.scala:78:14]
wire [15:0] io_ptw_8_vsatp_asid = 16'h0; // @[LazyRoCC.scala:78:14]
wire [15:0] io_ptw_9_ptbr_asid = 16'h0; // @[LazyRoCC.scala:78:14]
wire [15:0] io_ptw_9_hgatp_asid = 16'h0; // @[LazyRoCC.scala:78:14]
wire [15:0] io_ptw_9_vsatp_asid = 16'h0; // @[LazyRoCC.scala:78:14]
wire [15:0] io_ptw_10_ptbr_asid = 16'h0; // @[LazyRoCC.scala:78:14]
wire [15:0] io_ptw_10_hgatp_asid = 16'h0; // @[LazyRoCC.scala:78:14]
wire [15:0] io_ptw_10_vsatp_asid = 16'h0; // @[LazyRoCC.scala:78:14]
wire [15:0] io_ptw_11_ptbr_asid = 16'h0; // @[LazyRoCC.scala:78:14]
wire [15:0] io_ptw_11_hgatp_asid = 16'h0; // @[LazyRoCC.scala:78:14]
wire [15:0] io_ptw_11_vsatp_asid = 16'h0; // @[LazyRoCC.scala:78:14]
wire [15:0] io_ptw_12_ptbr_asid = 16'h0; // @[LazyRoCC.scala:78:14]
wire [15:0] io_ptw_12_hgatp_asid = 16'h0; // @[LazyRoCC.scala:78:14]
wire [15:0] io_ptw_12_vsatp_asid = 16'h0; // @[LazyRoCC.scala:78:14]
wire [15:0] io_ptw_13_ptbr_asid = 16'h0; // @[LazyRoCC.scala:78:14]
wire [15:0] io_ptw_13_hgatp_asid = 16'h0; // @[LazyRoCC.scala:78:14]
wire [15:0] io_ptw_13_vsatp_asid = 16'h0; // @[LazyRoCC.scala:78:14]
wire [15:0] io_ptw_14_ptbr_asid = 16'h0; // @[LazyRoCC.scala:78:14]
wire [15:0] io_ptw_14_hgatp_asid = 16'h0; // @[LazyRoCC.scala:78:14]
wire [15:0] io_ptw_14_vsatp_asid = 16'h0; // @[LazyRoCC.scala:78:14]
wire [15:0] io_ptw_15_ptbr_asid = 16'h0; // @[LazyRoCC.scala:78:14]
wire [15:0] io_ptw_15_hgatp_asid = 16'h0; // @[LazyRoCC.scala:78:14]
wire [15:0] io_ptw_15_vsatp_asid = 16'h0; // @[LazyRoCC.scala:78:14]
wire [15:0] io_ptw_16_ptbr_asid = 16'h0; // @[LazyRoCC.scala:78:14]
wire [15:0] io_ptw_16_hgatp_asid = 16'h0; // @[LazyRoCC.scala:78:14]
wire [15:0] io_ptw_16_vsatp_asid = 16'h0; // @[LazyRoCC.scala:78:14]
wire [15:0] io_ptw_17_ptbr_asid = 16'h0; // @[LazyRoCC.scala:78:14]
wire [15:0] io_ptw_17_hgatp_asid = 16'h0; // @[LazyRoCC.scala:78:14]
wire [15:0] io_ptw_17_vsatp_asid = 16'h0; // @[LazyRoCC.scala:78:14]
wire io_mem_req_valid = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_mem_req_bits_signed = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_mem_req_bits_dv = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_mem_req_bits_phys = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_mem_req_bits_no_resp = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_mem_req_bits_no_alloc = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_mem_req_bits_no_xcpt = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_mem_s1_kill = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_mem_s2_nack = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_mem_s2_nack_cause_raw = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_mem_s2_kill = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_mem_s2_uncached = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_mem_replay_next = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_mem_s2_xcpt_ma_ld = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_mem_s2_xcpt_ma_st = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_mem_s2_xcpt_pf_ld = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_mem_s2_xcpt_pf_st = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_mem_s2_xcpt_gf_ld = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_mem_s2_xcpt_gf_st = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_mem_s2_xcpt_ae_ld = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_mem_s2_xcpt_ae_st = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_mem_s2_gpa_is_pte = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_mem_ordered = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_mem_store_pending = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_mem_perf_acquire = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_mem_perf_release = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_mem_perf_grant = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_mem_perf_tlbMiss = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_mem_perf_blocked = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_mem_perf_canAcceptStoreThenLoad = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_mem_perf_canAcceptStoreThenRMW = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_mem_perf_canAcceptLoadThenLoad = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_mem_perf_storeBufferEmptyAfterLoad = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_mem_perf_storeBufferEmptyAfterStore = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_mem_clock_enabled = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_busy = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_interrupt = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_req_bits_bits_vstage1 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_req_bits_bits_stage2 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_resp_bits_fragmented_superpage = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_status_mbe = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_status_sbe = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_status_sd_rv32 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_status_ube = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_status_upie = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_status_hie = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_status_uie = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_hstatus_vtsr = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_hstatus_vtw = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_hstatus_vtvm = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_hstatus_hu = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_hstatus_vsbe = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_gstatus_sd_rv32 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_customCSRs_csrs_0_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_customCSRs_csrs_0_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_customCSRs_csrs_1_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_customCSRs_csrs_1_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_customCSRs_csrs_2_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_customCSRs_csrs_2_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_customCSRs_csrs_3_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_customCSRs_csrs_3_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_req_bits_bits_vstage1 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_req_bits_bits_stage2 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_resp_bits_fragmented_superpage = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_status_mbe = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_status_sbe = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_status_sd_rv32 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_status_ube = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_status_upie = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_status_hie = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_status_uie = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_hstatus_vtsr = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_hstatus_vtw = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_hstatus_vtvm = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_hstatus_hu = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_hstatus_vsbe = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_gstatus_sd_rv32 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_customCSRs_csrs_0_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_customCSRs_csrs_0_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_customCSRs_csrs_1_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_customCSRs_csrs_1_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_customCSRs_csrs_2_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_customCSRs_csrs_2_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_customCSRs_csrs_3_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_customCSRs_csrs_3_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_req_bits_bits_vstage1 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_req_bits_bits_stage2 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_resp_bits_fragmented_superpage = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_status_mbe = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_status_sbe = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_status_sd_rv32 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_status_ube = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_status_upie = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_status_hie = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_status_uie = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_hstatus_vtsr = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_hstatus_vtw = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_hstatus_vtvm = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_hstatus_hu = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_hstatus_vsbe = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_gstatus_sd_rv32 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_customCSRs_csrs_0_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_customCSRs_csrs_0_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_customCSRs_csrs_1_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_customCSRs_csrs_1_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_customCSRs_csrs_2_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_customCSRs_csrs_2_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_customCSRs_csrs_3_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_customCSRs_csrs_3_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_req_bits_bits_vstage1 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_req_bits_bits_stage2 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_resp_bits_fragmented_superpage = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_status_mbe = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_status_sbe = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_status_sd_rv32 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_status_ube = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_status_upie = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_status_hie = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_status_uie = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_hstatus_vtsr = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_hstatus_vtw = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_hstatus_vtvm = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_hstatus_hu = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_hstatus_vsbe = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_gstatus_sd_rv32 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_customCSRs_csrs_0_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_customCSRs_csrs_0_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_customCSRs_csrs_1_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_customCSRs_csrs_1_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_customCSRs_csrs_2_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_customCSRs_csrs_2_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_customCSRs_csrs_3_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_customCSRs_csrs_3_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_req_bits_bits_vstage1 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_req_bits_bits_stage2 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_resp_bits_fragmented_superpage = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_status_mbe = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_status_sbe = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_status_sd_rv32 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_status_ube = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_status_upie = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_status_hie = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_status_uie = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_hstatus_vtsr = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_hstatus_vtw = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_hstatus_vtvm = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_hstatus_hu = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_hstatus_vsbe = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_gstatus_sd_rv32 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_customCSRs_csrs_0_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_customCSRs_csrs_0_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_customCSRs_csrs_1_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_customCSRs_csrs_1_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_customCSRs_csrs_2_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_customCSRs_csrs_2_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_customCSRs_csrs_3_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_customCSRs_csrs_3_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_req_bits_bits_vstage1 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_req_bits_bits_stage2 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_resp_bits_fragmented_superpage = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_status_mbe = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_status_sbe = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_status_sd_rv32 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_status_ube = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_status_upie = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_status_hie = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_status_uie = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_hstatus_vtsr = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_hstatus_vtw = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_hstatus_vtvm = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_hstatus_hu = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_hstatus_vsbe = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_gstatus_sd_rv32 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_customCSRs_csrs_0_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_customCSRs_csrs_0_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_customCSRs_csrs_1_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_customCSRs_csrs_1_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_customCSRs_csrs_2_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_customCSRs_csrs_2_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_customCSRs_csrs_3_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_customCSRs_csrs_3_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_req_bits_bits_vstage1 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_req_bits_bits_stage2 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_resp_bits_fragmented_superpage = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_status_mbe = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_status_sbe = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_status_sd_rv32 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_status_ube = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_status_upie = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_status_hie = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_status_uie = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_hstatus_vtsr = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_hstatus_vtw = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_hstatus_vtvm = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_hstatus_hu = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_hstatus_vsbe = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_gstatus_sd_rv32 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_customCSRs_csrs_0_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_customCSRs_csrs_0_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_customCSRs_csrs_1_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_customCSRs_csrs_1_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_customCSRs_csrs_2_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_customCSRs_csrs_2_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_customCSRs_csrs_3_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_customCSRs_csrs_3_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_req_bits_bits_vstage1 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_req_bits_bits_stage2 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_resp_bits_fragmented_superpage = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_status_mbe = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_status_sbe = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_status_sd_rv32 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_status_ube = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_status_upie = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_status_hie = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_status_uie = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_hstatus_vtsr = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_hstatus_vtw = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_hstatus_vtvm = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_hstatus_hu = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_hstatus_vsbe = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_gstatus_sd_rv32 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_customCSRs_csrs_0_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_customCSRs_csrs_0_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_customCSRs_csrs_1_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_customCSRs_csrs_1_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_customCSRs_csrs_2_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_customCSRs_csrs_2_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_customCSRs_csrs_3_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_customCSRs_csrs_3_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_req_bits_bits_vstage1 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_req_bits_bits_stage2 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_resp_bits_fragmented_superpage = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_status_mbe = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_status_sbe = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_status_sd_rv32 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_status_ube = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_status_upie = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_status_hie = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_status_uie = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_hstatus_vtsr = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_hstatus_vtw = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_hstatus_vtvm = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_hstatus_hu = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_hstatus_vsbe = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_gstatus_sd_rv32 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_customCSRs_csrs_0_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_customCSRs_csrs_0_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_customCSRs_csrs_1_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_customCSRs_csrs_1_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_customCSRs_csrs_2_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_customCSRs_csrs_2_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_customCSRs_csrs_3_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_customCSRs_csrs_3_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_req_bits_bits_vstage1 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_req_bits_bits_stage2 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_resp_bits_fragmented_superpage = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_status_mbe = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_status_sbe = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_status_sd_rv32 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_status_ube = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_status_upie = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_status_hie = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_status_uie = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_hstatus_vtsr = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_hstatus_vtw = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_hstatus_vtvm = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_hstatus_hu = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_hstatus_vsbe = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_gstatus_sd_rv32 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_customCSRs_csrs_0_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_customCSRs_csrs_0_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_customCSRs_csrs_1_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_customCSRs_csrs_1_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_customCSRs_csrs_2_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_customCSRs_csrs_2_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_customCSRs_csrs_3_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_customCSRs_csrs_3_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_req_bits_bits_vstage1 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_req_bits_bits_stage2 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_resp_bits_fragmented_superpage = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_status_mbe = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_status_sbe = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_status_sd_rv32 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_status_ube = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_status_upie = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_status_hie = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_status_uie = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_hstatus_vtsr = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_hstatus_vtw = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_hstatus_vtvm = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_hstatus_hu = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_hstatus_vsbe = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_gstatus_sd_rv32 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_customCSRs_csrs_0_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_customCSRs_csrs_0_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_customCSRs_csrs_1_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_customCSRs_csrs_1_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_customCSRs_csrs_2_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_customCSRs_csrs_2_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_customCSRs_csrs_3_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_customCSRs_csrs_3_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_req_bits_bits_vstage1 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_req_bits_bits_stage2 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_resp_bits_fragmented_superpage = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_status_mbe = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_status_sbe = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_status_sd_rv32 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_status_ube = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_status_upie = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_status_hie = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_status_uie = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_hstatus_vtsr = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_hstatus_vtw = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_hstatus_vtvm = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_hstatus_hu = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_hstatus_vsbe = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_gstatus_sd_rv32 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_customCSRs_csrs_0_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_customCSRs_csrs_0_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_customCSRs_csrs_1_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_customCSRs_csrs_1_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_customCSRs_csrs_2_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_customCSRs_csrs_2_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_customCSRs_csrs_3_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_customCSRs_csrs_3_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_req_bits_bits_vstage1 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_req_bits_bits_stage2 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_resp_bits_fragmented_superpage = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_status_mbe = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_status_sbe = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_status_sd_rv32 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_status_ube = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_status_upie = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_status_hie = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_status_uie = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_hstatus_vtsr = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_hstatus_vtw = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_hstatus_vtvm = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_hstatus_hu = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_hstatus_vsbe = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_gstatus_sd_rv32 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_customCSRs_csrs_0_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_customCSRs_csrs_0_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_customCSRs_csrs_1_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_customCSRs_csrs_1_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_customCSRs_csrs_2_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_customCSRs_csrs_2_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_customCSRs_csrs_3_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_customCSRs_csrs_3_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_req_bits_bits_vstage1 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_req_bits_bits_stage2 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_resp_bits_fragmented_superpage = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_status_mbe = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_status_sbe = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_status_sd_rv32 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_status_ube = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_status_upie = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_status_hie = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_status_uie = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_hstatus_vtsr = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_hstatus_vtw = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_hstatus_vtvm = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_hstatus_hu = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_hstatus_vsbe = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_gstatus_sd_rv32 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_customCSRs_csrs_0_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_customCSRs_csrs_0_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_customCSRs_csrs_1_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_customCSRs_csrs_1_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_customCSRs_csrs_2_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_customCSRs_csrs_2_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_customCSRs_csrs_3_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_customCSRs_csrs_3_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_req_bits_bits_vstage1 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_req_bits_bits_stage2 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_resp_bits_fragmented_superpage = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_status_mbe = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_status_sbe = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_status_sd_rv32 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_status_ube = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_status_upie = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_status_hie = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_status_uie = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_hstatus_vtsr = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_hstatus_vtw = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_hstatus_vtvm = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_hstatus_hu = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_hstatus_vsbe = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_gstatus_sd_rv32 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_customCSRs_csrs_0_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_customCSRs_csrs_0_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_customCSRs_csrs_1_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_customCSRs_csrs_1_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_customCSRs_csrs_2_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_customCSRs_csrs_2_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_customCSRs_csrs_3_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_customCSRs_csrs_3_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_req_bits_bits_vstage1 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_req_bits_bits_stage2 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_resp_bits_fragmented_superpage = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_status_mbe = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_status_sbe = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_status_sd_rv32 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_status_ube = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_status_upie = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_status_hie = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_status_uie = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_hstatus_vtsr = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_hstatus_vtw = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_hstatus_vtvm = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_hstatus_hu = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_hstatus_vsbe = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_gstatus_sd_rv32 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_customCSRs_csrs_0_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_customCSRs_csrs_0_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_customCSRs_csrs_1_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_customCSRs_csrs_1_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_customCSRs_csrs_2_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_customCSRs_csrs_2_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_customCSRs_csrs_3_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_customCSRs_csrs_3_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_req_bits_bits_vstage1 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_req_bits_bits_stage2 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_resp_bits_fragmented_superpage = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_status_mbe = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_status_sbe = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_status_sd_rv32 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_status_ube = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_status_upie = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_status_hie = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_status_uie = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_hstatus_vtsr = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_hstatus_vtw = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_hstatus_vtvm = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_hstatus_hu = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_hstatus_vsbe = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_gstatus_sd_rv32 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_customCSRs_csrs_0_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_customCSRs_csrs_0_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_customCSRs_csrs_1_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_customCSRs_csrs_1_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_customCSRs_csrs_2_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_customCSRs_csrs_2_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_customCSRs_csrs_3_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_customCSRs_csrs_3_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_req_bits_bits_vstage1 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_req_bits_bits_stage2 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_resp_bits_fragmented_superpage = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_status_mbe = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_status_sbe = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_status_sd_rv32 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_status_ube = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_status_upie = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_status_hie = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_status_uie = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_hstatus_vtsr = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_hstatus_vtw = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_hstatus_vtvm = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_hstatus_hu = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_hstatus_vsbe = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_gstatus_sd_rv32 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_customCSRs_csrs_0_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_customCSRs_csrs_0_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_customCSRs_csrs_1_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_customCSRs_csrs_1_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_customCSRs_csrs_2_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_customCSRs_csrs_2_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_customCSRs_csrs_3_stall = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_customCSRs_csrs_3_set = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_fpu_req_ready = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_fpu_req_valid = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_fpu_req_bits_ldst = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_fpu_req_bits_wen = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_fpu_req_bits_ren1 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_fpu_req_bits_ren2 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_fpu_req_bits_ren3 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_fpu_req_bits_swap12 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_fpu_req_bits_swap23 = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_fpu_req_bits_fromint = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_fpu_req_bits_toint = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_fpu_req_bits_fastpipe = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_fpu_req_bits_fma = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_fpu_req_bits_div = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_fpu_req_bits_sqrt = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_fpu_req_bits_wflags = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_fpu_req_bits_vec = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_fpu_resp_ready = 1'h0; // @[ZstdCompressor.scala:95:7]
wire io_fpu_resp_valid = 1'h0; // @[ZstdCompressor.scala:95:7]
wire x1_tlNodeOut_16_a_ready = auto_tl_out_17_a_ready_0; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_16_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeOut_16_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeOut_16_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] x1_tlNodeOut_16_a_bits_size; // @[MixedNode.scala:542:17]
wire [4:0] x1_tlNodeOut_16_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] x1_tlNodeOut_16_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] x1_tlNodeOut_16_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] x1_tlNodeOut_16_a_bits_data; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_16_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_16_d_ready; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_16_d_valid = auto_tl_out_17_d_valid_0; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeOut_16_d_bits_opcode = auto_tl_out_17_d_bits_opcode_0; // @[MixedNode.scala:542:17]
wire [1:0] x1_tlNodeOut_16_d_bits_param = auto_tl_out_17_d_bits_param_0; // @[MixedNode.scala:542:17]
wire [3:0] x1_tlNodeOut_16_d_bits_size = auto_tl_out_17_d_bits_size_0; // @[MixedNode.scala:542:17]
wire [4:0] x1_tlNodeOut_16_d_bits_source = auto_tl_out_17_d_bits_source_0; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeOut_16_d_bits_sink = auto_tl_out_17_d_bits_sink_0; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_16_d_bits_denied = auto_tl_out_17_d_bits_denied_0; // @[MixedNode.scala:542:17]
wire [63:0] x1_tlNodeOut_16_d_bits_data = auto_tl_out_17_d_bits_data_0; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_16_d_bits_corrupt = auto_tl_out_17_d_bits_corrupt_0; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_15_a_ready = auto_tl_out_16_a_ready_0; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_15_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeOut_15_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeOut_15_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] x1_tlNodeOut_15_a_bits_size; // @[MixedNode.scala:542:17]
wire [4:0] x1_tlNodeOut_15_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] x1_tlNodeOut_15_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] x1_tlNodeOut_15_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] x1_tlNodeOut_15_a_bits_data; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_15_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_15_d_ready; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_15_d_valid = auto_tl_out_16_d_valid_0; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeOut_15_d_bits_opcode = auto_tl_out_16_d_bits_opcode_0; // @[MixedNode.scala:542:17]
wire [1:0] x1_tlNodeOut_15_d_bits_param = auto_tl_out_16_d_bits_param_0; // @[MixedNode.scala:542:17]
wire [3:0] x1_tlNodeOut_15_d_bits_size = auto_tl_out_16_d_bits_size_0; // @[MixedNode.scala:542:17]
wire [4:0] x1_tlNodeOut_15_d_bits_source = auto_tl_out_16_d_bits_source_0; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeOut_15_d_bits_sink = auto_tl_out_16_d_bits_sink_0; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_15_d_bits_denied = auto_tl_out_16_d_bits_denied_0; // @[MixedNode.scala:542:17]
wire [63:0] x1_tlNodeOut_15_d_bits_data = auto_tl_out_16_d_bits_data_0; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_15_d_bits_corrupt = auto_tl_out_16_d_bits_corrupt_0; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_14_a_ready = auto_tl_out_15_a_ready_0; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_14_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeOut_14_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeOut_14_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] x1_tlNodeOut_14_a_bits_size; // @[MixedNode.scala:542:17]
wire [4:0] x1_tlNodeOut_14_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] x1_tlNodeOut_14_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] x1_tlNodeOut_14_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] x1_tlNodeOut_14_a_bits_data; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_14_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_14_d_ready; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_14_d_valid = auto_tl_out_15_d_valid_0; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeOut_14_d_bits_opcode = auto_tl_out_15_d_bits_opcode_0; // @[MixedNode.scala:542:17]
wire [1:0] x1_tlNodeOut_14_d_bits_param = auto_tl_out_15_d_bits_param_0; // @[MixedNode.scala:542:17]
wire [3:0] x1_tlNodeOut_14_d_bits_size = auto_tl_out_15_d_bits_size_0; // @[MixedNode.scala:542:17]
wire [4:0] x1_tlNodeOut_14_d_bits_source = auto_tl_out_15_d_bits_source_0; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeOut_14_d_bits_sink = auto_tl_out_15_d_bits_sink_0; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_14_d_bits_denied = auto_tl_out_15_d_bits_denied_0; // @[MixedNode.scala:542:17]
wire [63:0] x1_tlNodeOut_14_d_bits_data = auto_tl_out_15_d_bits_data_0; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_14_d_bits_corrupt = auto_tl_out_15_d_bits_corrupt_0; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_13_a_ready = auto_tl_out_14_a_ready_0; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_13_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeOut_13_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeOut_13_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] x1_tlNodeOut_13_a_bits_size; // @[MixedNode.scala:542:17]
wire [4:0] x1_tlNodeOut_13_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] x1_tlNodeOut_13_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] x1_tlNodeOut_13_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] x1_tlNodeOut_13_a_bits_data; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_13_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_13_d_ready; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_13_d_valid = auto_tl_out_14_d_valid_0; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeOut_13_d_bits_opcode = auto_tl_out_14_d_bits_opcode_0; // @[MixedNode.scala:542:17]
wire [1:0] x1_tlNodeOut_13_d_bits_param = auto_tl_out_14_d_bits_param_0; // @[MixedNode.scala:542:17]
wire [3:0] x1_tlNodeOut_13_d_bits_size = auto_tl_out_14_d_bits_size_0; // @[MixedNode.scala:542:17]
wire [4:0] x1_tlNodeOut_13_d_bits_source = auto_tl_out_14_d_bits_source_0; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeOut_13_d_bits_sink = auto_tl_out_14_d_bits_sink_0; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_13_d_bits_denied = auto_tl_out_14_d_bits_denied_0; // @[MixedNode.scala:542:17]
wire [63:0] x1_tlNodeOut_13_d_bits_data = auto_tl_out_14_d_bits_data_0; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_13_d_bits_corrupt = auto_tl_out_14_d_bits_corrupt_0; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_12_a_ready = auto_tl_out_13_a_ready_0; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_12_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeOut_12_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeOut_12_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] x1_tlNodeOut_12_a_bits_size; // @[MixedNode.scala:542:17]
wire [4:0] x1_tlNodeOut_12_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] x1_tlNodeOut_12_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] x1_tlNodeOut_12_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] x1_tlNodeOut_12_a_bits_data; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_12_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_12_d_ready; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_12_d_valid = auto_tl_out_13_d_valid_0; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeOut_12_d_bits_opcode = auto_tl_out_13_d_bits_opcode_0; // @[MixedNode.scala:542:17]
wire [1:0] x1_tlNodeOut_12_d_bits_param = auto_tl_out_13_d_bits_param_0; // @[MixedNode.scala:542:17]
wire [3:0] x1_tlNodeOut_12_d_bits_size = auto_tl_out_13_d_bits_size_0; // @[MixedNode.scala:542:17]
wire [4:0] x1_tlNodeOut_12_d_bits_source = auto_tl_out_13_d_bits_source_0; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeOut_12_d_bits_sink = auto_tl_out_13_d_bits_sink_0; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_12_d_bits_denied = auto_tl_out_13_d_bits_denied_0; // @[MixedNode.scala:542:17]
wire [63:0] x1_tlNodeOut_12_d_bits_data = auto_tl_out_13_d_bits_data_0; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_12_d_bits_corrupt = auto_tl_out_13_d_bits_corrupt_0; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_11_a_ready = auto_tl_out_12_a_ready_0; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_11_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeOut_11_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeOut_11_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] x1_tlNodeOut_11_a_bits_size; // @[MixedNode.scala:542:17]
wire [4:0] x1_tlNodeOut_11_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] x1_tlNodeOut_11_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] x1_tlNodeOut_11_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] x1_tlNodeOut_11_a_bits_data; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_11_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_11_d_ready; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_11_d_valid = auto_tl_out_12_d_valid_0; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeOut_11_d_bits_opcode = auto_tl_out_12_d_bits_opcode_0; // @[MixedNode.scala:542:17]
wire [1:0] x1_tlNodeOut_11_d_bits_param = auto_tl_out_12_d_bits_param_0; // @[MixedNode.scala:542:17]
wire [3:0] x1_tlNodeOut_11_d_bits_size = auto_tl_out_12_d_bits_size_0; // @[MixedNode.scala:542:17]
wire [4:0] x1_tlNodeOut_11_d_bits_source = auto_tl_out_12_d_bits_source_0; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeOut_11_d_bits_sink = auto_tl_out_12_d_bits_sink_0; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_11_d_bits_denied = auto_tl_out_12_d_bits_denied_0; // @[MixedNode.scala:542:17]
wire [63:0] x1_tlNodeOut_11_d_bits_data = auto_tl_out_12_d_bits_data_0; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_11_d_bits_corrupt = auto_tl_out_12_d_bits_corrupt_0; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_10_a_ready = auto_tl_out_11_a_ready_0; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_10_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeOut_10_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeOut_10_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] x1_tlNodeOut_10_a_bits_size; // @[MixedNode.scala:542:17]
wire [4:0] x1_tlNodeOut_10_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] x1_tlNodeOut_10_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] x1_tlNodeOut_10_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] x1_tlNodeOut_10_a_bits_data; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_10_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_10_d_ready; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_10_d_valid = auto_tl_out_11_d_valid_0; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeOut_10_d_bits_opcode = auto_tl_out_11_d_bits_opcode_0; // @[MixedNode.scala:542:17]
wire [1:0] x1_tlNodeOut_10_d_bits_param = auto_tl_out_11_d_bits_param_0; // @[MixedNode.scala:542:17]
wire [3:0] x1_tlNodeOut_10_d_bits_size = auto_tl_out_11_d_bits_size_0; // @[MixedNode.scala:542:17]
wire [4:0] x1_tlNodeOut_10_d_bits_source = auto_tl_out_11_d_bits_source_0; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeOut_10_d_bits_sink = auto_tl_out_11_d_bits_sink_0; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_10_d_bits_denied = auto_tl_out_11_d_bits_denied_0; // @[MixedNode.scala:542:17]
wire [63:0] x1_tlNodeOut_10_d_bits_data = auto_tl_out_11_d_bits_data_0; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_10_d_bits_corrupt = auto_tl_out_11_d_bits_corrupt_0; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_9_a_ready = auto_tl_out_10_a_ready_0; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_9_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeOut_9_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeOut_9_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] x1_tlNodeOut_9_a_bits_size; // @[MixedNode.scala:542:17]
wire [4:0] x1_tlNodeOut_9_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] x1_tlNodeOut_9_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] x1_tlNodeOut_9_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] x1_tlNodeOut_9_a_bits_data; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_9_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_9_d_ready; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_9_d_valid = auto_tl_out_10_d_valid_0; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeOut_9_d_bits_opcode = auto_tl_out_10_d_bits_opcode_0; // @[MixedNode.scala:542:17]
wire [1:0] x1_tlNodeOut_9_d_bits_param = auto_tl_out_10_d_bits_param_0; // @[MixedNode.scala:542:17]
wire [3:0] x1_tlNodeOut_9_d_bits_size = auto_tl_out_10_d_bits_size_0; // @[MixedNode.scala:542:17]
wire [4:0] x1_tlNodeOut_9_d_bits_source = auto_tl_out_10_d_bits_source_0; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeOut_9_d_bits_sink = auto_tl_out_10_d_bits_sink_0; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_9_d_bits_denied = auto_tl_out_10_d_bits_denied_0; // @[MixedNode.scala:542:17]
wire [63:0] x1_tlNodeOut_9_d_bits_data = auto_tl_out_10_d_bits_data_0; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_9_d_bits_corrupt = auto_tl_out_10_d_bits_corrupt_0; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_8_a_ready = auto_tl_out_9_a_ready_0; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_8_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeOut_8_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeOut_8_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] x1_tlNodeOut_8_a_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] x1_tlNodeOut_8_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] x1_tlNodeOut_8_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] x1_tlNodeOut_8_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] x1_tlNodeOut_8_a_bits_data; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_8_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_8_d_ready; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_8_d_valid = auto_tl_out_9_d_valid_0; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeOut_8_d_bits_opcode = auto_tl_out_9_d_bits_opcode_0; // @[MixedNode.scala:542:17]
wire [1:0] x1_tlNodeOut_8_d_bits_param = auto_tl_out_9_d_bits_param_0; // @[MixedNode.scala:542:17]
wire [3:0] x1_tlNodeOut_8_d_bits_size = auto_tl_out_9_d_bits_size_0; // @[MixedNode.scala:542:17]
wire [1:0] x1_tlNodeOut_8_d_bits_source = auto_tl_out_9_d_bits_source_0; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeOut_8_d_bits_sink = auto_tl_out_9_d_bits_sink_0; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_8_d_bits_denied = auto_tl_out_9_d_bits_denied_0; // @[MixedNode.scala:542:17]
wire [63:0] x1_tlNodeOut_8_d_bits_data = auto_tl_out_9_d_bits_data_0; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_8_d_bits_corrupt = auto_tl_out_9_d_bits_corrupt_0; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_7_a_ready = auto_tl_out_8_a_ready_0; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_7_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeOut_7_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeOut_7_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] x1_tlNodeOut_7_a_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] x1_tlNodeOut_7_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] x1_tlNodeOut_7_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] x1_tlNodeOut_7_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] x1_tlNodeOut_7_a_bits_data; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_7_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_7_d_ready; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_7_d_valid = auto_tl_out_8_d_valid_0; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeOut_7_d_bits_opcode = auto_tl_out_8_d_bits_opcode_0; // @[MixedNode.scala:542:17]
wire [1:0] x1_tlNodeOut_7_d_bits_param = auto_tl_out_8_d_bits_param_0; // @[MixedNode.scala:542:17]
wire [3:0] x1_tlNodeOut_7_d_bits_size = auto_tl_out_8_d_bits_size_0; // @[MixedNode.scala:542:17]
wire [1:0] x1_tlNodeOut_7_d_bits_source = auto_tl_out_8_d_bits_source_0; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeOut_7_d_bits_sink = auto_tl_out_8_d_bits_sink_0; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_7_d_bits_denied = auto_tl_out_8_d_bits_denied_0; // @[MixedNode.scala:542:17]
wire [63:0] x1_tlNodeOut_7_d_bits_data = auto_tl_out_8_d_bits_data_0; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_7_d_bits_corrupt = auto_tl_out_8_d_bits_corrupt_0; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_6_a_ready = auto_tl_out_7_a_ready_0; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_6_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeOut_6_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeOut_6_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] x1_tlNodeOut_6_a_bits_size; // @[MixedNode.scala:542:17]
wire [4:0] x1_tlNodeOut_6_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] x1_tlNodeOut_6_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] x1_tlNodeOut_6_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] x1_tlNodeOut_6_a_bits_data; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_6_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_6_d_ready; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_6_d_valid = auto_tl_out_7_d_valid_0; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeOut_6_d_bits_opcode = auto_tl_out_7_d_bits_opcode_0; // @[MixedNode.scala:542:17]
wire [1:0] x1_tlNodeOut_6_d_bits_param = auto_tl_out_7_d_bits_param_0; // @[MixedNode.scala:542:17]
wire [3:0] x1_tlNodeOut_6_d_bits_size = auto_tl_out_7_d_bits_size_0; // @[MixedNode.scala:542:17]
wire [4:0] x1_tlNodeOut_6_d_bits_source = auto_tl_out_7_d_bits_source_0; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeOut_6_d_bits_sink = auto_tl_out_7_d_bits_sink_0; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_6_d_bits_denied = auto_tl_out_7_d_bits_denied_0; // @[MixedNode.scala:542:17]
wire [63:0] x1_tlNodeOut_6_d_bits_data = auto_tl_out_7_d_bits_data_0; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_6_d_bits_corrupt = auto_tl_out_7_d_bits_corrupt_0; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_5_a_ready = auto_tl_out_6_a_ready_0; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_5_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeOut_5_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeOut_5_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] x1_tlNodeOut_5_a_bits_size; // @[MixedNode.scala:542:17]
wire [4:0] x1_tlNodeOut_5_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] x1_tlNodeOut_5_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] x1_tlNodeOut_5_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] x1_tlNodeOut_5_a_bits_data; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_5_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_5_d_ready; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_5_d_valid = auto_tl_out_6_d_valid_0; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeOut_5_d_bits_opcode = auto_tl_out_6_d_bits_opcode_0; // @[MixedNode.scala:542:17]
wire [1:0] x1_tlNodeOut_5_d_bits_param = auto_tl_out_6_d_bits_param_0; // @[MixedNode.scala:542:17]
wire [3:0] x1_tlNodeOut_5_d_bits_size = auto_tl_out_6_d_bits_size_0; // @[MixedNode.scala:542:17]
wire [4:0] x1_tlNodeOut_5_d_bits_source = auto_tl_out_6_d_bits_source_0; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeOut_5_d_bits_sink = auto_tl_out_6_d_bits_sink_0; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_5_d_bits_denied = auto_tl_out_6_d_bits_denied_0; // @[MixedNode.scala:542:17]
wire [63:0] x1_tlNodeOut_5_d_bits_data = auto_tl_out_6_d_bits_data_0; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_5_d_bits_corrupt = auto_tl_out_6_d_bits_corrupt_0; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_4_a_ready = auto_tl_out_5_a_ready_0; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_4_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeOut_4_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeOut_4_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] x1_tlNodeOut_4_a_bits_size; // @[MixedNode.scala:542:17]
wire [4:0] x1_tlNodeOut_4_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] x1_tlNodeOut_4_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] x1_tlNodeOut_4_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] x1_tlNodeOut_4_a_bits_data; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_4_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_4_d_ready; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_4_d_valid = auto_tl_out_5_d_valid_0; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeOut_4_d_bits_opcode = auto_tl_out_5_d_bits_opcode_0; // @[MixedNode.scala:542:17]
wire [1:0] x1_tlNodeOut_4_d_bits_param = auto_tl_out_5_d_bits_param_0; // @[MixedNode.scala:542:17]
wire [3:0] x1_tlNodeOut_4_d_bits_size = auto_tl_out_5_d_bits_size_0; // @[MixedNode.scala:542:17]
wire [4:0] x1_tlNodeOut_4_d_bits_source = auto_tl_out_5_d_bits_source_0; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeOut_4_d_bits_sink = auto_tl_out_5_d_bits_sink_0; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_4_d_bits_denied = auto_tl_out_5_d_bits_denied_0; // @[MixedNode.scala:542:17]
wire [63:0] x1_tlNodeOut_4_d_bits_data = auto_tl_out_5_d_bits_data_0; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_4_d_bits_corrupt = auto_tl_out_5_d_bits_corrupt_0; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_3_a_ready = auto_tl_out_4_a_ready_0; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_3_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeOut_3_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeOut_3_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] x1_tlNodeOut_3_a_bits_size; // @[MixedNode.scala:542:17]
wire [4:0] x1_tlNodeOut_3_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] x1_tlNodeOut_3_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] x1_tlNodeOut_3_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] x1_tlNodeOut_3_a_bits_data; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_3_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_3_d_ready; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_3_d_valid = auto_tl_out_4_d_valid_0; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeOut_3_d_bits_opcode = auto_tl_out_4_d_bits_opcode_0; // @[MixedNode.scala:542:17]
wire [1:0] x1_tlNodeOut_3_d_bits_param = auto_tl_out_4_d_bits_param_0; // @[MixedNode.scala:542:17]
wire [3:0] x1_tlNodeOut_3_d_bits_size = auto_tl_out_4_d_bits_size_0; // @[MixedNode.scala:542:17]
wire [4:0] x1_tlNodeOut_3_d_bits_source = auto_tl_out_4_d_bits_source_0; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeOut_3_d_bits_sink = auto_tl_out_4_d_bits_sink_0; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_3_d_bits_denied = auto_tl_out_4_d_bits_denied_0; // @[MixedNode.scala:542:17]
wire [63:0] x1_tlNodeOut_3_d_bits_data = auto_tl_out_4_d_bits_data_0; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_3_d_bits_corrupt = auto_tl_out_4_d_bits_corrupt_0; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_2_a_ready = auto_tl_out_3_a_ready_0; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_2_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeOut_2_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeOut_2_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] x1_tlNodeOut_2_a_bits_size; // @[MixedNode.scala:542:17]
wire [4:0] x1_tlNodeOut_2_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] x1_tlNodeOut_2_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] x1_tlNodeOut_2_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] x1_tlNodeOut_2_a_bits_data; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_2_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_2_d_ready; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_2_d_valid = auto_tl_out_3_d_valid_0; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeOut_2_d_bits_opcode = auto_tl_out_3_d_bits_opcode_0; // @[MixedNode.scala:542:17]
wire [1:0] x1_tlNodeOut_2_d_bits_param = auto_tl_out_3_d_bits_param_0; // @[MixedNode.scala:542:17]
wire [3:0] x1_tlNodeOut_2_d_bits_size = auto_tl_out_3_d_bits_size_0; // @[MixedNode.scala:542:17]
wire [4:0] x1_tlNodeOut_2_d_bits_source = auto_tl_out_3_d_bits_source_0; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeOut_2_d_bits_sink = auto_tl_out_3_d_bits_sink_0; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_2_d_bits_denied = auto_tl_out_3_d_bits_denied_0; // @[MixedNode.scala:542:17]
wire [63:0] x1_tlNodeOut_2_d_bits_data = auto_tl_out_3_d_bits_data_0; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_2_d_bits_corrupt = auto_tl_out_3_d_bits_corrupt_0; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_1_a_ready = auto_tl_out_2_a_ready_0; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_1_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeOut_1_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeOut_1_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] x1_tlNodeOut_1_a_bits_size; // @[MixedNode.scala:542:17]
wire [4:0] x1_tlNodeOut_1_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] x1_tlNodeOut_1_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] x1_tlNodeOut_1_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] x1_tlNodeOut_1_a_bits_data; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_1_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_1_d_ready; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_1_d_valid = auto_tl_out_2_d_valid_0; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeOut_1_d_bits_opcode = auto_tl_out_2_d_bits_opcode_0; // @[MixedNode.scala:542:17]
wire [1:0] x1_tlNodeOut_1_d_bits_param = auto_tl_out_2_d_bits_param_0; // @[MixedNode.scala:542:17]
wire [3:0] x1_tlNodeOut_1_d_bits_size = auto_tl_out_2_d_bits_size_0; // @[MixedNode.scala:542:17]
wire [4:0] x1_tlNodeOut_1_d_bits_source = auto_tl_out_2_d_bits_source_0; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeOut_1_d_bits_sink = auto_tl_out_2_d_bits_sink_0; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_1_d_bits_denied = auto_tl_out_2_d_bits_denied_0; // @[MixedNode.scala:542:17]
wire [63:0] x1_tlNodeOut_1_d_bits_data = auto_tl_out_2_d_bits_data_0; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_1_d_bits_corrupt = auto_tl_out_2_d_bits_corrupt_0; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_a_ready = auto_tl_out_1_a_ready_0; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] x1_tlNodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] x1_tlNodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] x1_tlNodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] x1_tlNodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] x1_tlNodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_d_ready; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_d_valid = auto_tl_out_1_d_valid_0; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeOut_d_bits_opcode = auto_tl_out_1_d_bits_opcode_0; // @[MixedNode.scala:542:17]
wire [1:0] x1_tlNodeOut_d_bits_param = auto_tl_out_1_d_bits_param_0; // @[MixedNode.scala:542:17]
wire [3:0] x1_tlNodeOut_d_bits_size = auto_tl_out_1_d_bits_size_0; // @[MixedNode.scala:542:17]
wire [1:0] x1_tlNodeOut_d_bits_source = auto_tl_out_1_d_bits_source_0; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeOut_d_bits_sink = auto_tl_out_1_d_bits_sink_0; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_d_bits_denied = auto_tl_out_1_d_bits_denied_0; // @[MixedNode.scala:542:17]
wire [63:0] x1_tlNodeOut_d_bits_data = auto_tl_out_1_d_bits_data_0; // @[MixedNode.scala:542:17]
wire x1_tlNodeOut_d_bits_corrupt = auto_tl_out_1_d_bits_corrupt_0; // @[MixedNode.scala:542:17]
wire tlNodeOut_a_ready = auto_tl_out_0_a_ready_0; // @[MixedNode.scala:542:17]
wire tlNodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] tlNodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] tlNodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] tlNodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] tlNodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] tlNodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] tlNodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] tlNodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire tlNodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire tlNodeOut_d_ready; // @[MixedNode.scala:542:17]
wire tlNodeOut_d_valid = auto_tl_out_0_d_valid_0; // @[MixedNode.scala:542:17]
wire [2:0] tlNodeOut_d_bits_opcode = auto_tl_out_0_d_bits_opcode_0; // @[MixedNode.scala:542:17]
wire [1:0] tlNodeOut_d_bits_param = auto_tl_out_0_d_bits_param_0; // @[MixedNode.scala:542:17]
wire [3:0] tlNodeOut_d_bits_size = auto_tl_out_0_d_bits_size_0; // @[MixedNode.scala:542:17]
wire [1:0] tlNodeOut_d_bits_source = auto_tl_out_0_d_bits_source_0; // @[MixedNode.scala:542:17]
wire [2:0] tlNodeOut_d_bits_sink = auto_tl_out_0_d_bits_sink_0; // @[MixedNode.scala:542:17]
wire tlNodeOut_d_bits_denied = auto_tl_out_0_d_bits_denied_0; // @[MixedNode.scala:542:17]
wire [63:0] tlNodeOut_d_bits_data = auto_tl_out_0_d_bits_data_0; // @[MixedNode.scala:542:17]
wire tlNodeOut_d_bits_corrupt = auto_tl_out_0_d_bits_corrupt_0; // @[MixedNode.scala:542:17]
wire [2:0] auto_tl_out_17_a_bits_opcode_0; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_17_a_bits_param_0; // @[ZstdCompressor.scala:95:7]
wire [3:0] auto_tl_out_17_a_bits_size_0; // @[ZstdCompressor.scala:95:7]
wire [4:0] auto_tl_out_17_a_bits_source_0; // @[ZstdCompressor.scala:95:7]
wire [31:0] auto_tl_out_17_a_bits_address_0; // @[ZstdCompressor.scala:95:7]
wire [7:0] auto_tl_out_17_a_bits_mask_0; // @[ZstdCompressor.scala:95:7]
wire [63:0] auto_tl_out_17_a_bits_data_0; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_17_a_bits_corrupt_0; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_17_a_valid_0; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_17_d_ready_0; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_16_a_bits_opcode_0; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_16_a_bits_param_0; // @[ZstdCompressor.scala:95:7]
wire [3:0] auto_tl_out_16_a_bits_size_0; // @[ZstdCompressor.scala:95:7]
wire [4:0] auto_tl_out_16_a_bits_source_0; // @[ZstdCompressor.scala:95:7]
wire [31:0] auto_tl_out_16_a_bits_address_0; // @[ZstdCompressor.scala:95:7]
wire [7:0] auto_tl_out_16_a_bits_mask_0; // @[ZstdCompressor.scala:95:7]
wire [63:0] auto_tl_out_16_a_bits_data_0; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_16_a_bits_corrupt_0; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_16_a_valid_0; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_16_d_ready_0; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_15_a_bits_opcode_0; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_15_a_bits_param_0; // @[ZstdCompressor.scala:95:7]
wire [3:0] auto_tl_out_15_a_bits_size_0; // @[ZstdCompressor.scala:95:7]
wire [4:0] auto_tl_out_15_a_bits_source_0; // @[ZstdCompressor.scala:95:7]
wire [31:0] auto_tl_out_15_a_bits_address_0; // @[ZstdCompressor.scala:95:7]
wire [7:0] auto_tl_out_15_a_bits_mask_0; // @[ZstdCompressor.scala:95:7]
wire [63:0] auto_tl_out_15_a_bits_data_0; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_15_a_bits_corrupt_0; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_15_a_valid_0; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_15_d_ready_0; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_14_a_bits_opcode_0; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_14_a_bits_param_0; // @[ZstdCompressor.scala:95:7]
wire [3:0] auto_tl_out_14_a_bits_size_0; // @[ZstdCompressor.scala:95:7]
wire [4:0] auto_tl_out_14_a_bits_source_0; // @[ZstdCompressor.scala:95:7]
wire [31:0] auto_tl_out_14_a_bits_address_0; // @[ZstdCompressor.scala:95:7]
wire [7:0] auto_tl_out_14_a_bits_mask_0; // @[ZstdCompressor.scala:95:7]
wire [63:0] auto_tl_out_14_a_bits_data_0; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_14_a_bits_corrupt_0; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_14_a_valid_0; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_14_d_ready_0; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_13_a_bits_opcode_0; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_13_a_bits_param_0; // @[ZstdCompressor.scala:95:7]
wire [3:0] auto_tl_out_13_a_bits_size_0; // @[ZstdCompressor.scala:95:7]
wire [4:0] auto_tl_out_13_a_bits_source_0; // @[ZstdCompressor.scala:95:7]
wire [31:0] auto_tl_out_13_a_bits_address_0; // @[ZstdCompressor.scala:95:7]
wire [7:0] auto_tl_out_13_a_bits_mask_0; // @[ZstdCompressor.scala:95:7]
wire [63:0] auto_tl_out_13_a_bits_data_0; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_13_a_bits_corrupt_0; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_13_a_valid_0; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_13_d_ready_0; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_12_a_bits_opcode_0; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_12_a_bits_param_0; // @[ZstdCompressor.scala:95:7]
wire [3:0] auto_tl_out_12_a_bits_size_0; // @[ZstdCompressor.scala:95:7]
wire [4:0] auto_tl_out_12_a_bits_source_0; // @[ZstdCompressor.scala:95:7]
wire [31:0] auto_tl_out_12_a_bits_address_0; // @[ZstdCompressor.scala:95:7]
wire [7:0] auto_tl_out_12_a_bits_mask_0; // @[ZstdCompressor.scala:95:7]
wire [63:0] auto_tl_out_12_a_bits_data_0; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_12_a_bits_corrupt_0; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_12_a_valid_0; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_12_d_ready_0; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_11_a_bits_opcode_0; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_11_a_bits_param_0; // @[ZstdCompressor.scala:95:7]
wire [3:0] auto_tl_out_11_a_bits_size_0; // @[ZstdCompressor.scala:95:7]
wire [4:0] auto_tl_out_11_a_bits_source_0; // @[ZstdCompressor.scala:95:7]
wire [31:0] auto_tl_out_11_a_bits_address_0; // @[ZstdCompressor.scala:95:7]
wire [7:0] auto_tl_out_11_a_bits_mask_0; // @[ZstdCompressor.scala:95:7]
wire [63:0] auto_tl_out_11_a_bits_data_0; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_11_a_bits_corrupt_0; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_11_a_valid_0; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_11_d_ready_0; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_10_a_bits_opcode_0; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_10_a_bits_param_0; // @[ZstdCompressor.scala:95:7]
wire [3:0] auto_tl_out_10_a_bits_size_0; // @[ZstdCompressor.scala:95:7]
wire [4:0] auto_tl_out_10_a_bits_source_0; // @[ZstdCompressor.scala:95:7]
wire [31:0] auto_tl_out_10_a_bits_address_0; // @[ZstdCompressor.scala:95:7]
wire [7:0] auto_tl_out_10_a_bits_mask_0; // @[ZstdCompressor.scala:95:7]
wire [63:0] auto_tl_out_10_a_bits_data_0; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_10_a_bits_corrupt_0; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_10_a_valid_0; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_10_d_ready_0; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_9_a_bits_opcode_0; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_9_a_bits_param_0; // @[ZstdCompressor.scala:95:7]
wire [3:0] auto_tl_out_9_a_bits_size_0; // @[ZstdCompressor.scala:95:7]
wire [1:0] auto_tl_out_9_a_bits_source_0; // @[ZstdCompressor.scala:95:7]
wire [31:0] auto_tl_out_9_a_bits_address_0; // @[ZstdCompressor.scala:95:7]
wire [7:0] auto_tl_out_9_a_bits_mask_0; // @[ZstdCompressor.scala:95:7]
wire [63:0] auto_tl_out_9_a_bits_data_0; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_9_a_bits_corrupt_0; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_9_a_valid_0; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_9_d_ready_0; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_8_a_bits_opcode_0; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_8_a_bits_param_0; // @[ZstdCompressor.scala:95:7]
wire [3:0] auto_tl_out_8_a_bits_size_0; // @[ZstdCompressor.scala:95:7]
wire [1:0] auto_tl_out_8_a_bits_source_0; // @[ZstdCompressor.scala:95:7]
wire [31:0] auto_tl_out_8_a_bits_address_0; // @[ZstdCompressor.scala:95:7]
wire [7:0] auto_tl_out_8_a_bits_mask_0; // @[ZstdCompressor.scala:95:7]
wire [63:0] auto_tl_out_8_a_bits_data_0; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_8_a_bits_corrupt_0; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_8_a_valid_0; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_8_d_ready_0; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_7_a_bits_opcode_0; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_7_a_bits_param_0; // @[ZstdCompressor.scala:95:7]
wire [3:0] auto_tl_out_7_a_bits_size_0; // @[ZstdCompressor.scala:95:7]
wire [4:0] auto_tl_out_7_a_bits_source_0; // @[ZstdCompressor.scala:95:7]
wire [31:0] auto_tl_out_7_a_bits_address_0; // @[ZstdCompressor.scala:95:7]
wire [7:0] auto_tl_out_7_a_bits_mask_0; // @[ZstdCompressor.scala:95:7]
wire [63:0] auto_tl_out_7_a_bits_data_0; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_7_a_bits_corrupt_0; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_7_a_valid_0; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_7_d_ready_0; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_6_a_bits_opcode_0; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_6_a_bits_param_0; // @[ZstdCompressor.scala:95:7]
wire [3:0] auto_tl_out_6_a_bits_size_0; // @[ZstdCompressor.scala:95:7]
wire [4:0] auto_tl_out_6_a_bits_source_0; // @[ZstdCompressor.scala:95:7]
wire [31:0] auto_tl_out_6_a_bits_address_0; // @[ZstdCompressor.scala:95:7]
wire [7:0] auto_tl_out_6_a_bits_mask_0; // @[ZstdCompressor.scala:95:7]
wire [63:0] auto_tl_out_6_a_bits_data_0; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_6_a_bits_corrupt_0; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_6_a_valid_0; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_6_d_ready_0; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_5_a_bits_opcode_0; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_5_a_bits_param_0; // @[ZstdCompressor.scala:95:7]
wire [3:0] auto_tl_out_5_a_bits_size_0; // @[ZstdCompressor.scala:95:7]
wire [4:0] auto_tl_out_5_a_bits_source_0; // @[ZstdCompressor.scala:95:7]
wire [31:0] auto_tl_out_5_a_bits_address_0; // @[ZstdCompressor.scala:95:7]
wire [7:0] auto_tl_out_5_a_bits_mask_0; // @[ZstdCompressor.scala:95:7]
wire [63:0] auto_tl_out_5_a_bits_data_0; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_5_a_bits_corrupt_0; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_5_a_valid_0; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_5_d_ready_0; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_4_a_bits_opcode_0; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_4_a_bits_param_0; // @[ZstdCompressor.scala:95:7]
wire [3:0] auto_tl_out_4_a_bits_size_0; // @[ZstdCompressor.scala:95:7]
wire [4:0] auto_tl_out_4_a_bits_source_0; // @[ZstdCompressor.scala:95:7]
wire [31:0] auto_tl_out_4_a_bits_address_0; // @[ZstdCompressor.scala:95:7]
wire [7:0] auto_tl_out_4_a_bits_mask_0; // @[ZstdCompressor.scala:95:7]
wire [63:0] auto_tl_out_4_a_bits_data_0; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_4_a_bits_corrupt_0; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_4_a_valid_0; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_4_d_ready_0; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_3_a_bits_opcode_0; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_3_a_bits_param_0; // @[ZstdCompressor.scala:95:7]
wire [3:0] auto_tl_out_3_a_bits_size_0; // @[ZstdCompressor.scala:95:7]
wire [4:0] auto_tl_out_3_a_bits_source_0; // @[ZstdCompressor.scala:95:7]
wire [31:0] auto_tl_out_3_a_bits_address_0; // @[ZstdCompressor.scala:95:7]
wire [7:0] auto_tl_out_3_a_bits_mask_0; // @[ZstdCompressor.scala:95:7]
wire [63:0] auto_tl_out_3_a_bits_data_0; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_3_a_bits_corrupt_0; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_3_a_valid_0; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_3_d_ready_0; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_2_a_bits_opcode_0; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_2_a_bits_param_0; // @[ZstdCompressor.scala:95:7]
wire [3:0] auto_tl_out_2_a_bits_size_0; // @[ZstdCompressor.scala:95:7]
wire [4:0] auto_tl_out_2_a_bits_source_0; // @[ZstdCompressor.scala:95:7]
wire [31:0] auto_tl_out_2_a_bits_address_0; // @[ZstdCompressor.scala:95:7]
wire [7:0] auto_tl_out_2_a_bits_mask_0; // @[ZstdCompressor.scala:95:7]
wire [63:0] auto_tl_out_2_a_bits_data_0; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_2_a_bits_corrupt_0; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_2_a_valid_0; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_2_d_ready_0; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_1_a_bits_opcode_0; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_1_a_bits_param_0; // @[ZstdCompressor.scala:95:7]
wire [3:0] auto_tl_out_1_a_bits_size_0; // @[ZstdCompressor.scala:95:7]
wire [1:0] auto_tl_out_1_a_bits_source_0; // @[ZstdCompressor.scala:95:7]
wire [31:0] auto_tl_out_1_a_bits_address_0; // @[ZstdCompressor.scala:95:7]
wire [7:0] auto_tl_out_1_a_bits_mask_0; // @[ZstdCompressor.scala:95:7]
wire [63:0] auto_tl_out_1_a_bits_data_0; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_1_a_bits_corrupt_0; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_1_a_valid_0; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_1_d_ready_0; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_0_a_bits_opcode_0; // @[ZstdCompressor.scala:95:7]
wire [2:0] auto_tl_out_0_a_bits_param_0; // @[ZstdCompressor.scala:95:7]
wire [3:0] auto_tl_out_0_a_bits_size_0; // @[ZstdCompressor.scala:95:7]
wire [1:0] auto_tl_out_0_a_bits_source_0; // @[ZstdCompressor.scala:95:7]
wire [31:0] auto_tl_out_0_a_bits_address_0; // @[ZstdCompressor.scala:95:7]
wire [7:0] auto_tl_out_0_a_bits_mask_0; // @[ZstdCompressor.scala:95:7]
wire [63:0] auto_tl_out_0_a_bits_data_0; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_0_a_bits_corrupt_0; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_0_a_valid_0; // @[ZstdCompressor.scala:95:7]
wire auto_tl_out_0_d_ready_0; // @[ZstdCompressor.scala:95:7]
wire io_cmd_ready_0; // @[ZstdCompressor.scala:95:7]
wire [4:0] io_resp_bits_rd_0; // @[ZstdCompressor.scala:95:7]
wire [63:0] io_resp_bits_data_0; // @[ZstdCompressor.scala:95:7]
wire io_resp_valid_0; // @[ZstdCompressor.scala:95:7]
wire [26:0] io_ptw_0_req_bits_bits_addr_0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_req_bits_bits_need_gpa_0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_0_req_valid_0; // @[ZstdCompressor.scala:95:7]
wire [26:0] io_ptw_1_req_bits_bits_addr_0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_req_bits_bits_need_gpa_0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_1_req_valid_0; // @[ZstdCompressor.scala:95:7]
wire [26:0] io_ptw_2_req_bits_bits_addr_0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_req_bits_bits_need_gpa_0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_2_req_valid_0; // @[ZstdCompressor.scala:95:7]
wire [26:0] io_ptw_3_req_bits_bits_addr_0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_req_bits_bits_need_gpa_0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_3_req_valid_0; // @[ZstdCompressor.scala:95:7]
wire [26:0] io_ptw_4_req_bits_bits_addr_0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_req_bits_bits_need_gpa_0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_4_req_valid_0; // @[ZstdCompressor.scala:95:7]
wire [26:0] io_ptw_5_req_bits_bits_addr_0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_req_bits_bits_need_gpa_0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_5_req_valid_0; // @[ZstdCompressor.scala:95:7]
wire [26:0] io_ptw_6_req_bits_bits_addr_0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_req_bits_bits_need_gpa_0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_6_req_valid_0; // @[ZstdCompressor.scala:95:7]
wire [26:0] io_ptw_7_req_bits_bits_addr_0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_req_bits_bits_need_gpa_0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_7_req_valid_0; // @[ZstdCompressor.scala:95:7]
wire [26:0] io_ptw_8_req_bits_bits_addr_0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_req_bits_bits_need_gpa_0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_8_req_valid_0; // @[ZstdCompressor.scala:95:7]
wire [26:0] io_ptw_9_req_bits_bits_addr_0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_req_bits_bits_need_gpa_0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_9_req_valid_0; // @[ZstdCompressor.scala:95:7]
wire [26:0] io_ptw_10_req_bits_bits_addr_0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_req_bits_bits_need_gpa_0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_10_req_valid_0; // @[ZstdCompressor.scala:95:7]
wire [26:0] io_ptw_11_req_bits_bits_addr_0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_req_bits_bits_need_gpa_0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_11_req_valid_0; // @[ZstdCompressor.scala:95:7]
wire [26:0] io_ptw_12_req_bits_bits_addr_0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_req_bits_bits_need_gpa_0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_12_req_valid_0; // @[ZstdCompressor.scala:95:7]
wire [26:0] io_ptw_13_req_bits_bits_addr_0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_req_bits_bits_need_gpa_0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_13_req_valid_0; // @[ZstdCompressor.scala:95:7]
wire [26:0] io_ptw_14_req_bits_bits_addr_0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_req_bits_bits_need_gpa_0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_14_req_valid_0; // @[ZstdCompressor.scala:95:7]
wire [26:0] io_ptw_15_req_bits_bits_addr_0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_req_bits_bits_need_gpa_0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_15_req_valid_0; // @[ZstdCompressor.scala:95:7]
wire [26:0] io_ptw_16_req_bits_bits_addr_0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_req_bits_bits_need_gpa_0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_16_req_valid_0; // @[ZstdCompressor.scala:95:7]
wire [26:0] io_ptw_17_req_bits_bits_addr_0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_req_bits_bits_need_gpa_0; // @[ZstdCompressor.scala:95:7]
wire io_ptw_17_req_valid_0; // @[ZstdCompressor.scala:95:7]
wire tlNodeIn_a_ready = tlNodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire tlNodeIn_a_valid; // @[MixedNode.scala:551:17]
assign auto_tl_out_0_a_valid_0 = tlNodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] tlNodeIn_a_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_tl_out_0_a_bits_opcode_0 = tlNodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] tlNodeIn_a_bits_param; // @[MixedNode.scala:551:17]
assign auto_tl_out_0_a_bits_param_0 = tlNodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] tlNodeIn_a_bits_size; // @[MixedNode.scala:551:17]
assign auto_tl_out_0_a_bits_size_0 = tlNodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] tlNodeIn_a_bits_source; // @[MixedNode.scala:551:17]
assign auto_tl_out_0_a_bits_source_0 = tlNodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] tlNodeIn_a_bits_address; // @[MixedNode.scala:551:17]
assign auto_tl_out_0_a_bits_address_0 = tlNodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] tlNodeIn_a_bits_mask; // @[MixedNode.scala:551:17]
assign auto_tl_out_0_a_bits_mask_0 = tlNodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] tlNodeIn_a_bits_data; // @[MixedNode.scala:551:17]
assign auto_tl_out_0_a_bits_data_0 = tlNodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire tlNodeIn_a_bits_corrupt; // @[MixedNode.scala:551:17]
assign auto_tl_out_0_a_bits_corrupt_0 = tlNodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire tlNodeIn_d_ready; // @[MixedNode.scala:551:17]
assign auto_tl_out_0_d_ready_0 = tlNodeOut_d_ready; // @[MixedNode.scala:542:17]
wire tlNodeIn_d_valid = tlNodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] tlNodeIn_d_bits_opcode = tlNodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] tlNodeIn_d_bits_param = tlNodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] tlNodeIn_d_bits_size = tlNodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] tlNodeIn_d_bits_source = tlNodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] tlNodeIn_d_bits_sink = tlNodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire tlNodeIn_d_bits_denied = tlNodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] tlNodeIn_d_bits_data = tlNodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire tlNodeIn_d_bits_corrupt = tlNodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlNodeIn_a_ready = x1_tlNodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlNodeIn_a_valid; // @[MixedNode.scala:551:17]
assign auto_tl_out_1_a_valid_0 = x1_tlNodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeIn_a_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_tl_out_1_a_bits_opcode_0 = x1_tlNodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeIn_a_bits_param; // @[MixedNode.scala:551:17]
assign auto_tl_out_1_a_bits_param_0 = x1_tlNodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] x1_tlNodeIn_a_bits_size; // @[MixedNode.scala:551:17]
assign auto_tl_out_1_a_bits_size_0 = x1_tlNodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] x1_tlNodeIn_a_bits_source; // @[MixedNode.scala:551:17]
assign auto_tl_out_1_a_bits_source_0 = x1_tlNodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] x1_tlNodeIn_a_bits_address; // @[MixedNode.scala:551:17]
assign auto_tl_out_1_a_bits_address_0 = x1_tlNodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] x1_tlNodeIn_a_bits_mask; // @[MixedNode.scala:551:17]
assign auto_tl_out_1_a_bits_mask_0 = x1_tlNodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] x1_tlNodeIn_a_bits_data; // @[MixedNode.scala:551:17]
assign auto_tl_out_1_a_bits_data_0 = x1_tlNodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire x1_tlNodeIn_a_bits_corrupt; // @[MixedNode.scala:551:17]
assign auto_tl_out_1_a_bits_corrupt_0 = x1_tlNodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire x1_tlNodeIn_d_ready; // @[MixedNode.scala:551:17]
assign auto_tl_out_1_d_ready_0 = x1_tlNodeOut_d_ready; // @[MixedNode.scala:542:17]
wire x1_tlNodeIn_d_valid = x1_tlNodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] x1_tlNodeIn_d_bits_opcode = x1_tlNodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] x1_tlNodeIn_d_bits_param = x1_tlNodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] x1_tlNodeIn_d_bits_size = x1_tlNodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] x1_tlNodeIn_d_bits_source = x1_tlNodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] x1_tlNodeIn_d_bits_sink = x1_tlNodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlNodeIn_d_bits_denied = x1_tlNodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] x1_tlNodeIn_d_bits_data = x1_tlNodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlNodeIn_d_bits_corrupt = x1_tlNodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlNodeIn_1_a_ready = x1_tlNodeOut_1_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlNodeIn_1_a_valid; // @[MixedNode.scala:551:17]
assign auto_tl_out_2_a_valid_0 = x1_tlNodeOut_1_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeIn_1_a_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_tl_out_2_a_bits_opcode_0 = x1_tlNodeOut_1_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeIn_1_a_bits_param; // @[MixedNode.scala:551:17]
assign auto_tl_out_2_a_bits_param_0 = x1_tlNodeOut_1_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] x1_tlNodeIn_1_a_bits_size; // @[MixedNode.scala:551:17]
assign auto_tl_out_2_a_bits_size_0 = x1_tlNodeOut_1_a_bits_size; // @[MixedNode.scala:542:17]
wire [4:0] x1_tlNodeIn_1_a_bits_source; // @[MixedNode.scala:551:17]
assign auto_tl_out_2_a_bits_source_0 = x1_tlNodeOut_1_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] x1_tlNodeIn_1_a_bits_address; // @[MixedNode.scala:551:17]
assign auto_tl_out_2_a_bits_address_0 = x1_tlNodeOut_1_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] x1_tlNodeIn_1_a_bits_mask; // @[MixedNode.scala:551:17]
assign auto_tl_out_2_a_bits_mask_0 = x1_tlNodeOut_1_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] x1_tlNodeIn_1_a_bits_data; // @[MixedNode.scala:551:17]
assign auto_tl_out_2_a_bits_data_0 = x1_tlNodeOut_1_a_bits_data; // @[MixedNode.scala:542:17]
wire x1_tlNodeIn_1_a_bits_corrupt; // @[MixedNode.scala:551:17]
assign auto_tl_out_2_a_bits_corrupt_0 = x1_tlNodeOut_1_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire x1_tlNodeIn_1_d_ready; // @[MixedNode.scala:551:17]
assign auto_tl_out_2_d_ready_0 = x1_tlNodeOut_1_d_ready; // @[MixedNode.scala:542:17]
wire x1_tlNodeIn_1_d_valid = x1_tlNodeOut_1_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] x1_tlNodeIn_1_d_bits_opcode = x1_tlNodeOut_1_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] x1_tlNodeIn_1_d_bits_param = x1_tlNodeOut_1_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] x1_tlNodeIn_1_d_bits_size = x1_tlNodeOut_1_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [4:0] x1_tlNodeIn_1_d_bits_source = x1_tlNodeOut_1_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] x1_tlNodeIn_1_d_bits_sink = x1_tlNodeOut_1_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlNodeIn_1_d_bits_denied = x1_tlNodeOut_1_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] x1_tlNodeIn_1_d_bits_data = x1_tlNodeOut_1_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlNodeIn_1_d_bits_corrupt = x1_tlNodeOut_1_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlNodeIn_2_a_ready = x1_tlNodeOut_2_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlNodeIn_2_a_valid; // @[MixedNode.scala:551:17]
assign auto_tl_out_3_a_valid_0 = x1_tlNodeOut_2_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeIn_2_a_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_tl_out_3_a_bits_opcode_0 = x1_tlNodeOut_2_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeIn_2_a_bits_param; // @[MixedNode.scala:551:17]
assign auto_tl_out_3_a_bits_param_0 = x1_tlNodeOut_2_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] x1_tlNodeIn_2_a_bits_size; // @[MixedNode.scala:551:17]
assign auto_tl_out_3_a_bits_size_0 = x1_tlNodeOut_2_a_bits_size; // @[MixedNode.scala:542:17]
wire [4:0] x1_tlNodeIn_2_a_bits_source; // @[MixedNode.scala:551:17]
assign auto_tl_out_3_a_bits_source_0 = x1_tlNodeOut_2_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] x1_tlNodeIn_2_a_bits_address; // @[MixedNode.scala:551:17]
assign auto_tl_out_3_a_bits_address_0 = x1_tlNodeOut_2_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] x1_tlNodeIn_2_a_bits_mask; // @[MixedNode.scala:551:17]
assign auto_tl_out_3_a_bits_mask_0 = x1_tlNodeOut_2_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] x1_tlNodeIn_2_a_bits_data; // @[MixedNode.scala:551:17]
assign auto_tl_out_3_a_bits_data_0 = x1_tlNodeOut_2_a_bits_data; // @[MixedNode.scala:542:17]
wire x1_tlNodeIn_2_a_bits_corrupt; // @[MixedNode.scala:551:17]
assign auto_tl_out_3_a_bits_corrupt_0 = x1_tlNodeOut_2_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire x1_tlNodeIn_2_d_ready; // @[MixedNode.scala:551:17]
assign auto_tl_out_3_d_ready_0 = x1_tlNodeOut_2_d_ready; // @[MixedNode.scala:542:17]
wire x1_tlNodeIn_2_d_valid = x1_tlNodeOut_2_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] x1_tlNodeIn_2_d_bits_opcode = x1_tlNodeOut_2_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] x1_tlNodeIn_2_d_bits_param = x1_tlNodeOut_2_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] x1_tlNodeIn_2_d_bits_size = x1_tlNodeOut_2_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [4:0] x1_tlNodeIn_2_d_bits_source = x1_tlNodeOut_2_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] x1_tlNodeIn_2_d_bits_sink = x1_tlNodeOut_2_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlNodeIn_2_d_bits_denied = x1_tlNodeOut_2_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] x1_tlNodeIn_2_d_bits_data = x1_tlNodeOut_2_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlNodeIn_2_d_bits_corrupt = x1_tlNodeOut_2_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlNodeIn_3_a_ready = x1_tlNodeOut_3_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlNodeIn_3_a_valid; // @[MixedNode.scala:551:17]
assign auto_tl_out_4_a_valid_0 = x1_tlNodeOut_3_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeIn_3_a_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_tl_out_4_a_bits_opcode_0 = x1_tlNodeOut_3_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeIn_3_a_bits_param; // @[MixedNode.scala:551:17]
assign auto_tl_out_4_a_bits_param_0 = x1_tlNodeOut_3_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] x1_tlNodeIn_3_a_bits_size; // @[MixedNode.scala:551:17]
assign auto_tl_out_4_a_bits_size_0 = x1_tlNodeOut_3_a_bits_size; // @[MixedNode.scala:542:17]
wire [4:0] x1_tlNodeIn_3_a_bits_source; // @[MixedNode.scala:551:17]
assign auto_tl_out_4_a_bits_source_0 = x1_tlNodeOut_3_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] x1_tlNodeIn_3_a_bits_address; // @[MixedNode.scala:551:17]
assign auto_tl_out_4_a_bits_address_0 = x1_tlNodeOut_3_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] x1_tlNodeIn_3_a_bits_mask; // @[MixedNode.scala:551:17]
assign auto_tl_out_4_a_bits_mask_0 = x1_tlNodeOut_3_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] x1_tlNodeIn_3_a_bits_data; // @[MixedNode.scala:551:17]
assign auto_tl_out_4_a_bits_data_0 = x1_tlNodeOut_3_a_bits_data; // @[MixedNode.scala:542:17]
wire x1_tlNodeIn_3_a_bits_corrupt; // @[MixedNode.scala:551:17]
assign auto_tl_out_4_a_bits_corrupt_0 = x1_tlNodeOut_3_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire x1_tlNodeIn_3_d_ready; // @[MixedNode.scala:551:17]
assign auto_tl_out_4_d_ready_0 = x1_tlNodeOut_3_d_ready; // @[MixedNode.scala:542:17]
wire x1_tlNodeIn_3_d_valid = x1_tlNodeOut_3_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] x1_tlNodeIn_3_d_bits_opcode = x1_tlNodeOut_3_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] x1_tlNodeIn_3_d_bits_param = x1_tlNodeOut_3_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] x1_tlNodeIn_3_d_bits_size = x1_tlNodeOut_3_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [4:0] x1_tlNodeIn_3_d_bits_source = x1_tlNodeOut_3_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] x1_tlNodeIn_3_d_bits_sink = x1_tlNodeOut_3_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlNodeIn_3_d_bits_denied = x1_tlNodeOut_3_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] x1_tlNodeIn_3_d_bits_data = x1_tlNodeOut_3_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlNodeIn_3_d_bits_corrupt = x1_tlNodeOut_3_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlNodeIn_4_a_ready = x1_tlNodeOut_4_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlNodeIn_4_a_valid; // @[MixedNode.scala:551:17]
assign auto_tl_out_5_a_valid_0 = x1_tlNodeOut_4_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeIn_4_a_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_tl_out_5_a_bits_opcode_0 = x1_tlNodeOut_4_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeIn_4_a_bits_param; // @[MixedNode.scala:551:17]
assign auto_tl_out_5_a_bits_param_0 = x1_tlNodeOut_4_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] x1_tlNodeIn_4_a_bits_size; // @[MixedNode.scala:551:17]
assign auto_tl_out_5_a_bits_size_0 = x1_tlNodeOut_4_a_bits_size; // @[MixedNode.scala:542:17]
wire [4:0] x1_tlNodeIn_4_a_bits_source; // @[MixedNode.scala:551:17]
assign auto_tl_out_5_a_bits_source_0 = x1_tlNodeOut_4_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] x1_tlNodeIn_4_a_bits_address; // @[MixedNode.scala:551:17]
assign auto_tl_out_5_a_bits_address_0 = x1_tlNodeOut_4_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] x1_tlNodeIn_4_a_bits_mask; // @[MixedNode.scala:551:17]
assign auto_tl_out_5_a_bits_mask_0 = x1_tlNodeOut_4_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] x1_tlNodeIn_4_a_bits_data; // @[MixedNode.scala:551:17]
assign auto_tl_out_5_a_bits_data_0 = x1_tlNodeOut_4_a_bits_data; // @[MixedNode.scala:542:17]
wire x1_tlNodeIn_4_a_bits_corrupt; // @[MixedNode.scala:551:17]
assign auto_tl_out_5_a_bits_corrupt_0 = x1_tlNodeOut_4_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire x1_tlNodeIn_4_d_ready; // @[MixedNode.scala:551:17]
assign auto_tl_out_5_d_ready_0 = x1_tlNodeOut_4_d_ready; // @[MixedNode.scala:542:17]
wire x1_tlNodeIn_4_d_valid = x1_tlNodeOut_4_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] x1_tlNodeIn_4_d_bits_opcode = x1_tlNodeOut_4_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] x1_tlNodeIn_4_d_bits_param = x1_tlNodeOut_4_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] x1_tlNodeIn_4_d_bits_size = x1_tlNodeOut_4_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [4:0] x1_tlNodeIn_4_d_bits_source = x1_tlNodeOut_4_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] x1_tlNodeIn_4_d_bits_sink = x1_tlNodeOut_4_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlNodeIn_4_d_bits_denied = x1_tlNodeOut_4_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] x1_tlNodeIn_4_d_bits_data = x1_tlNodeOut_4_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlNodeIn_4_d_bits_corrupt = x1_tlNodeOut_4_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlNodeIn_5_a_ready = x1_tlNodeOut_5_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlNodeIn_5_a_valid; // @[MixedNode.scala:551:17]
assign auto_tl_out_6_a_valid_0 = x1_tlNodeOut_5_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeIn_5_a_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_tl_out_6_a_bits_opcode_0 = x1_tlNodeOut_5_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeIn_5_a_bits_param; // @[MixedNode.scala:551:17]
assign auto_tl_out_6_a_bits_param_0 = x1_tlNodeOut_5_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] x1_tlNodeIn_5_a_bits_size; // @[MixedNode.scala:551:17]
assign auto_tl_out_6_a_bits_size_0 = x1_tlNodeOut_5_a_bits_size; // @[MixedNode.scala:542:17]
wire [4:0] x1_tlNodeIn_5_a_bits_source; // @[MixedNode.scala:551:17]
assign auto_tl_out_6_a_bits_source_0 = x1_tlNodeOut_5_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] x1_tlNodeIn_5_a_bits_address; // @[MixedNode.scala:551:17]
assign auto_tl_out_6_a_bits_address_0 = x1_tlNodeOut_5_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] x1_tlNodeIn_5_a_bits_mask; // @[MixedNode.scala:551:17]
assign auto_tl_out_6_a_bits_mask_0 = x1_tlNodeOut_5_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] x1_tlNodeIn_5_a_bits_data; // @[MixedNode.scala:551:17]
assign auto_tl_out_6_a_bits_data_0 = x1_tlNodeOut_5_a_bits_data; // @[MixedNode.scala:542:17]
wire x1_tlNodeIn_5_a_bits_corrupt; // @[MixedNode.scala:551:17]
assign auto_tl_out_6_a_bits_corrupt_0 = x1_tlNodeOut_5_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire x1_tlNodeIn_5_d_ready; // @[MixedNode.scala:551:17]
assign auto_tl_out_6_d_ready_0 = x1_tlNodeOut_5_d_ready; // @[MixedNode.scala:542:17]
wire x1_tlNodeIn_5_d_valid = x1_tlNodeOut_5_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] x1_tlNodeIn_5_d_bits_opcode = x1_tlNodeOut_5_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] x1_tlNodeIn_5_d_bits_param = x1_tlNodeOut_5_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] x1_tlNodeIn_5_d_bits_size = x1_tlNodeOut_5_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [4:0] x1_tlNodeIn_5_d_bits_source = x1_tlNodeOut_5_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] x1_tlNodeIn_5_d_bits_sink = x1_tlNodeOut_5_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlNodeIn_5_d_bits_denied = x1_tlNodeOut_5_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] x1_tlNodeIn_5_d_bits_data = x1_tlNodeOut_5_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlNodeIn_5_d_bits_corrupt = x1_tlNodeOut_5_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlNodeIn_6_a_ready = x1_tlNodeOut_6_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlNodeIn_6_a_valid; // @[MixedNode.scala:551:17]
assign auto_tl_out_7_a_valid_0 = x1_tlNodeOut_6_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeIn_6_a_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_tl_out_7_a_bits_opcode_0 = x1_tlNodeOut_6_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeIn_6_a_bits_param; // @[MixedNode.scala:551:17]
assign auto_tl_out_7_a_bits_param_0 = x1_tlNodeOut_6_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] x1_tlNodeIn_6_a_bits_size; // @[MixedNode.scala:551:17]
assign auto_tl_out_7_a_bits_size_0 = x1_tlNodeOut_6_a_bits_size; // @[MixedNode.scala:542:17]
wire [4:0] x1_tlNodeIn_6_a_bits_source; // @[MixedNode.scala:551:17]
assign auto_tl_out_7_a_bits_source_0 = x1_tlNodeOut_6_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] x1_tlNodeIn_6_a_bits_address; // @[MixedNode.scala:551:17]
assign auto_tl_out_7_a_bits_address_0 = x1_tlNodeOut_6_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] x1_tlNodeIn_6_a_bits_mask; // @[MixedNode.scala:551:17]
assign auto_tl_out_7_a_bits_mask_0 = x1_tlNodeOut_6_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] x1_tlNodeIn_6_a_bits_data; // @[MixedNode.scala:551:17]
assign auto_tl_out_7_a_bits_data_0 = x1_tlNodeOut_6_a_bits_data; // @[MixedNode.scala:542:17]
wire x1_tlNodeIn_6_a_bits_corrupt; // @[MixedNode.scala:551:17]
assign auto_tl_out_7_a_bits_corrupt_0 = x1_tlNodeOut_6_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire x1_tlNodeIn_6_d_ready; // @[MixedNode.scala:551:17]
assign auto_tl_out_7_d_ready_0 = x1_tlNodeOut_6_d_ready; // @[MixedNode.scala:542:17]
wire x1_tlNodeIn_6_d_valid = x1_tlNodeOut_6_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] x1_tlNodeIn_6_d_bits_opcode = x1_tlNodeOut_6_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] x1_tlNodeIn_6_d_bits_param = x1_tlNodeOut_6_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] x1_tlNodeIn_6_d_bits_size = x1_tlNodeOut_6_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [4:0] x1_tlNodeIn_6_d_bits_source = x1_tlNodeOut_6_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] x1_tlNodeIn_6_d_bits_sink = x1_tlNodeOut_6_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlNodeIn_6_d_bits_denied = x1_tlNodeOut_6_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] x1_tlNodeIn_6_d_bits_data = x1_tlNodeOut_6_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlNodeIn_6_d_bits_corrupt = x1_tlNodeOut_6_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlNodeIn_7_a_ready = x1_tlNodeOut_7_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlNodeIn_7_a_valid; // @[MixedNode.scala:551:17]
assign auto_tl_out_8_a_valid_0 = x1_tlNodeOut_7_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeIn_7_a_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_tl_out_8_a_bits_opcode_0 = x1_tlNodeOut_7_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeIn_7_a_bits_param; // @[MixedNode.scala:551:17]
assign auto_tl_out_8_a_bits_param_0 = x1_tlNodeOut_7_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] x1_tlNodeIn_7_a_bits_size; // @[MixedNode.scala:551:17]
assign auto_tl_out_8_a_bits_size_0 = x1_tlNodeOut_7_a_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] x1_tlNodeIn_7_a_bits_source; // @[MixedNode.scala:551:17]
assign auto_tl_out_8_a_bits_source_0 = x1_tlNodeOut_7_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] x1_tlNodeIn_7_a_bits_address; // @[MixedNode.scala:551:17]
assign auto_tl_out_8_a_bits_address_0 = x1_tlNodeOut_7_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] x1_tlNodeIn_7_a_bits_mask; // @[MixedNode.scala:551:17]
assign auto_tl_out_8_a_bits_mask_0 = x1_tlNodeOut_7_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] x1_tlNodeIn_7_a_bits_data; // @[MixedNode.scala:551:17]
assign auto_tl_out_8_a_bits_data_0 = x1_tlNodeOut_7_a_bits_data; // @[MixedNode.scala:542:17]
wire x1_tlNodeIn_7_a_bits_corrupt; // @[MixedNode.scala:551:17]
assign auto_tl_out_8_a_bits_corrupt_0 = x1_tlNodeOut_7_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire x1_tlNodeIn_7_d_ready; // @[MixedNode.scala:551:17]
assign auto_tl_out_8_d_ready_0 = x1_tlNodeOut_7_d_ready; // @[MixedNode.scala:542:17]
wire x1_tlNodeIn_7_d_valid = x1_tlNodeOut_7_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] x1_tlNodeIn_7_d_bits_opcode = x1_tlNodeOut_7_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] x1_tlNodeIn_7_d_bits_param = x1_tlNodeOut_7_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] x1_tlNodeIn_7_d_bits_size = x1_tlNodeOut_7_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] x1_tlNodeIn_7_d_bits_source = x1_tlNodeOut_7_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] x1_tlNodeIn_7_d_bits_sink = x1_tlNodeOut_7_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlNodeIn_7_d_bits_denied = x1_tlNodeOut_7_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] x1_tlNodeIn_7_d_bits_data = x1_tlNodeOut_7_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlNodeIn_7_d_bits_corrupt = x1_tlNodeOut_7_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlNodeIn_8_a_ready = x1_tlNodeOut_8_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlNodeIn_8_a_valid; // @[MixedNode.scala:551:17]
assign auto_tl_out_9_a_valid_0 = x1_tlNodeOut_8_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeIn_8_a_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_tl_out_9_a_bits_opcode_0 = x1_tlNodeOut_8_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeIn_8_a_bits_param; // @[MixedNode.scala:551:17]
assign auto_tl_out_9_a_bits_param_0 = x1_tlNodeOut_8_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] x1_tlNodeIn_8_a_bits_size; // @[MixedNode.scala:551:17]
assign auto_tl_out_9_a_bits_size_0 = x1_tlNodeOut_8_a_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] x1_tlNodeIn_8_a_bits_source; // @[MixedNode.scala:551:17]
assign auto_tl_out_9_a_bits_source_0 = x1_tlNodeOut_8_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] x1_tlNodeIn_8_a_bits_address; // @[MixedNode.scala:551:17]
assign auto_tl_out_9_a_bits_address_0 = x1_tlNodeOut_8_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] x1_tlNodeIn_8_a_bits_mask; // @[MixedNode.scala:551:17]
assign auto_tl_out_9_a_bits_mask_0 = x1_tlNodeOut_8_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] x1_tlNodeIn_8_a_bits_data; // @[MixedNode.scala:551:17]
assign auto_tl_out_9_a_bits_data_0 = x1_tlNodeOut_8_a_bits_data; // @[MixedNode.scala:542:17]
wire x1_tlNodeIn_8_a_bits_corrupt; // @[MixedNode.scala:551:17]
assign auto_tl_out_9_a_bits_corrupt_0 = x1_tlNodeOut_8_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire x1_tlNodeIn_8_d_ready; // @[MixedNode.scala:551:17]
assign auto_tl_out_9_d_ready_0 = x1_tlNodeOut_8_d_ready; // @[MixedNode.scala:542:17]
wire x1_tlNodeIn_8_d_valid = x1_tlNodeOut_8_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] x1_tlNodeIn_8_d_bits_opcode = x1_tlNodeOut_8_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] x1_tlNodeIn_8_d_bits_param = x1_tlNodeOut_8_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] x1_tlNodeIn_8_d_bits_size = x1_tlNodeOut_8_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] x1_tlNodeIn_8_d_bits_source = x1_tlNodeOut_8_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] x1_tlNodeIn_8_d_bits_sink = x1_tlNodeOut_8_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlNodeIn_8_d_bits_denied = x1_tlNodeOut_8_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] x1_tlNodeIn_8_d_bits_data = x1_tlNodeOut_8_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlNodeIn_8_d_bits_corrupt = x1_tlNodeOut_8_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlNodeIn_9_a_ready = x1_tlNodeOut_9_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlNodeIn_9_a_valid; // @[MixedNode.scala:551:17]
assign auto_tl_out_10_a_valid_0 = x1_tlNodeOut_9_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeIn_9_a_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_tl_out_10_a_bits_opcode_0 = x1_tlNodeOut_9_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeIn_9_a_bits_param; // @[MixedNode.scala:551:17]
assign auto_tl_out_10_a_bits_param_0 = x1_tlNodeOut_9_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] x1_tlNodeIn_9_a_bits_size; // @[MixedNode.scala:551:17]
assign auto_tl_out_10_a_bits_size_0 = x1_tlNodeOut_9_a_bits_size; // @[MixedNode.scala:542:17]
wire [4:0] x1_tlNodeIn_9_a_bits_source; // @[MixedNode.scala:551:17]
assign auto_tl_out_10_a_bits_source_0 = x1_tlNodeOut_9_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] x1_tlNodeIn_9_a_bits_address; // @[MixedNode.scala:551:17]
assign auto_tl_out_10_a_bits_address_0 = x1_tlNodeOut_9_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] x1_tlNodeIn_9_a_bits_mask; // @[MixedNode.scala:551:17]
assign auto_tl_out_10_a_bits_mask_0 = x1_tlNodeOut_9_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] x1_tlNodeIn_9_a_bits_data; // @[MixedNode.scala:551:17]
assign auto_tl_out_10_a_bits_data_0 = x1_tlNodeOut_9_a_bits_data; // @[MixedNode.scala:542:17]
wire x1_tlNodeIn_9_a_bits_corrupt; // @[MixedNode.scala:551:17]
assign auto_tl_out_10_a_bits_corrupt_0 = x1_tlNodeOut_9_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire x1_tlNodeIn_9_d_ready; // @[MixedNode.scala:551:17]
assign auto_tl_out_10_d_ready_0 = x1_tlNodeOut_9_d_ready; // @[MixedNode.scala:542:17]
wire x1_tlNodeIn_9_d_valid = x1_tlNodeOut_9_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] x1_tlNodeIn_9_d_bits_opcode = x1_tlNodeOut_9_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] x1_tlNodeIn_9_d_bits_param = x1_tlNodeOut_9_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] x1_tlNodeIn_9_d_bits_size = x1_tlNodeOut_9_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [4:0] x1_tlNodeIn_9_d_bits_source = x1_tlNodeOut_9_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] x1_tlNodeIn_9_d_bits_sink = x1_tlNodeOut_9_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlNodeIn_9_d_bits_denied = x1_tlNodeOut_9_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] x1_tlNodeIn_9_d_bits_data = x1_tlNodeOut_9_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlNodeIn_9_d_bits_corrupt = x1_tlNodeOut_9_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlNodeIn_10_a_ready = x1_tlNodeOut_10_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlNodeIn_10_a_valid; // @[MixedNode.scala:551:17]
assign auto_tl_out_11_a_valid_0 = x1_tlNodeOut_10_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeIn_10_a_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_tl_out_11_a_bits_opcode_0 = x1_tlNodeOut_10_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeIn_10_a_bits_param; // @[MixedNode.scala:551:17]
assign auto_tl_out_11_a_bits_param_0 = x1_tlNodeOut_10_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] x1_tlNodeIn_10_a_bits_size; // @[MixedNode.scala:551:17]
assign auto_tl_out_11_a_bits_size_0 = x1_tlNodeOut_10_a_bits_size; // @[MixedNode.scala:542:17]
wire [4:0] x1_tlNodeIn_10_a_bits_source; // @[MixedNode.scala:551:17]
assign auto_tl_out_11_a_bits_source_0 = x1_tlNodeOut_10_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] x1_tlNodeIn_10_a_bits_address; // @[MixedNode.scala:551:17]
assign auto_tl_out_11_a_bits_address_0 = x1_tlNodeOut_10_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] x1_tlNodeIn_10_a_bits_mask; // @[MixedNode.scala:551:17]
assign auto_tl_out_11_a_bits_mask_0 = x1_tlNodeOut_10_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] x1_tlNodeIn_10_a_bits_data; // @[MixedNode.scala:551:17]
assign auto_tl_out_11_a_bits_data_0 = x1_tlNodeOut_10_a_bits_data; // @[MixedNode.scala:542:17]
wire x1_tlNodeIn_10_a_bits_corrupt; // @[MixedNode.scala:551:17]
assign auto_tl_out_11_a_bits_corrupt_0 = x1_tlNodeOut_10_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire x1_tlNodeIn_10_d_ready; // @[MixedNode.scala:551:17]
assign auto_tl_out_11_d_ready_0 = x1_tlNodeOut_10_d_ready; // @[MixedNode.scala:542:17]
wire x1_tlNodeIn_10_d_valid = x1_tlNodeOut_10_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] x1_tlNodeIn_10_d_bits_opcode = x1_tlNodeOut_10_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] x1_tlNodeIn_10_d_bits_param = x1_tlNodeOut_10_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] x1_tlNodeIn_10_d_bits_size = x1_tlNodeOut_10_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [4:0] x1_tlNodeIn_10_d_bits_source = x1_tlNodeOut_10_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] x1_tlNodeIn_10_d_bits_sink = x1_tlNodeOut_10_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlNodeIn_10_d_bits_denied = x1_tlNodeOut_10_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] x1_tlNodeIn_10_d_bits_data = x1_tlNodeOut_10_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlNodeIn_10_d_bits_corrupt = x1_tlNodeOut_10_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlNodeIn_11_a_ready = x1_tlNodeOut_11_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlNodeIn_11_a_valid; // @[MixedNode.scala:551:17]
assign auto_tl_out_12_a_valid_0 = x1_tlNodeOut_11_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeIn_11_a_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_tl_out_12_a_bits_opcode_0 = x1_tlNodeOut_11_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeIn_11_a_bits_param; // @[MixedNode.scala:551:17]
assign auto_tl_out_12_a_bits_param_0 = x1_tlNodeOut_11_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] x1_tlNodeIn_11_a_bits_size; // @[MixedNode.scala:551:17]
assign auto_tl_out_12_a_bits_size_0 = x1_tlNodeOut_11_a_bits_size; // @[MixedNode.scala:542:17]
wire [4:0] x1_tlNodeIn_11_a_bits_source; // @[MixedNode.scala:551:17]
assign auto_tl_out_12_a_bits_source_0 = x1_tlNodeOut_11_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] x1_tlNodeIn_11_a_bits_address; // @[MixedNode.scala:551:17]
assign auto_tl_out_12_a_bits_address_0 = x1_tlNodeOut_11_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] x1_tlNodeIn_11_a_bits_mask; // @[MixedNode.scala:551:17]
assign auto_tl_out_12_a_bits_mask_0 = x1_tlNodeOut_11_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] x1_tlNodeIn_11_a_bits_data; // @[MixedNode.scala:551:17]
assign auto_tl_out_12_a_bits_data_0 = x1_tlNodeOut_11_a_bits_data; // @[MixedNode.scala:542:17]
wire x1_tlNodeIn_11_a_bits_corrupt; // @[MixedNode.scala:551:17]
assign auto_tl_out_12_a_bits_corrupt_0 = x1_tlNodeOut_11_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire x1_tlNodeIn_11_d_ready; // @[MixedNode.scala:551:17]
assign auto_tl_out_12_d_ready_0 = x1_tlNodeOut_11_d_ready; // @[MixedNode.scala:542:17]
wire x1_tlNodeIn_11_d_valid = x1_tlNodeOut_11_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] x1_tlNodeIn_11_d_bits_opcode = x1_tlNodeOut_11_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] x1_tlNodeIn_11_d_bits_param = x1_tlNodeOut_11_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] x1_tlNodeIn_11_d_bits_size = x1_tlNodeOut_11_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [4:0] x1_tlNodeIn_11_d_bits_source = x1_tlNodeOut_11_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] x1_tlNodeIn_11_d_bits_sink = x1_tlNodeOut_11_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlNodeIn_11_d_bits_denied = x1_tlNodeOut_11_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] x1_tlNodeIn_11_d_bits_data = x1_tlNodeOut_11_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlNodeIn_11_d_bits_corrupt = x1_tlNodeOut_11_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlNodeIn_12_a_ready = x1_tlNodeOut_12_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlNodeIn_12_a_valid; // @[MixedNode.scala:551:17]
assign auto_tl_out_13_a_valid_0 = x1_tlNodeOut_12_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeIn_12_a_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_tl_out_13_a_bits_opcode_0 = x1_tlNodeOut_12_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeIn_12_a_bits_param; // @[MixedNode.scala:551:17]
assign auto_tl_out_13_a_bits_param_0 = x1_tlNodeOut_12_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] x1_tlNodeIn_12_a_bits_size; // @[MixedNode.scala:551:17]
assign auto_tl_out_13_a_bits_size_0 = x1_tlNodeOut_12_a_bits_size; // @[MixedNode.scala:542:17]
wire [4:0] x1_tlNodeIn_12_a_bits_source; // @[MixedNode.scala:551:17]
assign auto_tl_out_13_a_bits_source_0 = x1_tlNodeOut_12_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] x1_tlNodeIn_12_a_bits_address; // @[MixedNode.scala:551:17]
assign auto_tl_out_13_a_bits_address_0 = x1_tlNodeOut_12_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] x1_tlNodeIn_12_a_bits_mask; // @[MixedNode.scala:551:17]
assign auto_tl_out_13_a_bits_mask_0 = x1_tlNodeOut_12_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] x1_tlNodeIn_12_a_bits_data; // @[MixedNode.scala:551:17]
assign auto_tl_out_13_a_bits_data_0 = x1_tlNodeOut_12_a_bits_data; // @[MixedNode.scala:542:17]
wire x1_tlNodeIn_12_a_bits_corrupt; // @[MixedNode.scala:551:17]
assign auto_tl_out_13_a_bits_corrupt_0 = x1_tlNodeOut_12_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire x1_tlNodeIn_12_d_ready; // @[MixedNode.scala:551:17]
assign auto_tl_out_13_d_ready_0 = x1_tlNodeOut_12_d_ready; // @[MixedNode.scala:542:17]
wire x1_tlNodeIn_12_d_valid = x1_tlNodeOut_12_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] x1_tlNodeIn_12_d_bits_opcode = x1_tlNodeOut_12_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] x1_tlNodeIn_12_d_bits_param = x1_tlNodeOut_12_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] x1_tlNodeIn_12_d_bits_size = x1_tlNodeOut_12_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [4:0] x1_tlNodeIn_12_d_bits_source = x1_tlNodeOut_12_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] x1_tlNodeIn_12_d_bits_sink = x1_tlNodeOut_12_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlNodeIn_12_d_bits_denied = x1_tlNodeOut_12_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] x1_tlNodeIn_12_d_bits_data = x1_tlNodeOut_12_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlNodeIn_12_d_bits_corrupt = x1_tlNodeOut_12_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlNodeIn_13_a_ready = x1_tlNodeOut_13_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlNodeIn_13_a_valid; // @[MixedNode.scala:551:17]
assign auto_tl_out_14_a_valid_0 = x1_tlNodeOut_13_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeIn_13_a_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_tl_out_14_a_bits_opcode_0 = x1_tlNodeOut_13_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeIn_13_a_bits_param; // @[MixedNode.scala:551:17]
assign auto_tl_out_14_a_bits_param_0 = x1_tlNodeOut_13_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] x1_tlNodeIn_13_a_bits_size; // @[MixedNode.scala:551:17]
assign auto_tl_out_14_a_bits_size_0 = x1_tlNodeOut_13_a_bits_size; // @[MixedNode.scala:542:17]
wire [4:0] x1_tlNodeIn_13_a_bits_source; // @[MixedNode.scala:551:17]
assign auto_tl_out_14_a_bits_source_0 = x1_tlNodeOut_13_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] x1_tlNodeIn_13_a_bits_address; // @[MixedNode.scala:551:17]
assign auto_tl_out_14_a_bits_address_0 = x1_tlNodeOut_13_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] x1_tlNodeIn_13_a_bits_mask; // @[MixedNode.scala:551:17]
assign auto_tl_out_14_a_bits_mask_0 = x1_tlNodeOut_13_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] x1_tlNodeIn_13_a_bits_data; // @[MixedNode.scala:551:17]
assign auto_tl_out_14_a_bits_data_0 = x1_tlNodeOut_13_a_bits_data; // @[MixedNode.scala:542:17]
wire x1_tlNodeIn_13_a_bits_corrupt; // @[MixedNode.scala:551:17]
assign auto_tl_out_14_a_bits_corrupt_0 = x1_tlNodeOut_13_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire x1_tlNodeIn_13_d_ready; // @[MixedNode.scala:551:17]
assign auto_tl_out_14_d_ready_0 = x1_tlNodeOut_13_d_ready; // @[MixedNode.scala:542:17]
wire x1_tlNodeIn_13_d_valid = x1_tlNodeOut_13_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] x1_tlNodeIn_13_d_bits_opcode = x1_tlNodeOut_13_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] x1_tlNodeIn_13_d_bits_param = x1_tlNodeOut_13_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] x1_tlNodeIn_13_d_bits_size = x1_tlNodeOut_13_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [4:0] x1_tlNodeIn_13_d_bits_source = x1_tlNodeOut_13_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] x1_tlNodeIn_13_d_bits_sink = x1_tlNodeOut_13_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlNodeIn_13_d_bits_denied = x1_tlNodeOut_13_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] x1_tlNodeIn_13_d_bits_data = x1_tlNodeOut_13_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlNodeIn_13_d_bits_corrupt = x1_tlNodeOut_13_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlNodeIn_14_a_ready = x1_tlNodeOut_14_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlNodeIn_14_a_valid; // @[MixedNode.scala:551:17]
assign auto_tl_out_15_a_valid_0 = x1_tlNodeOut_14_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeIn_14_a_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_tl_out_15_a_bits_opcode_0 = x1_tlNodeOut_14_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeIn_14_a_bits_param; // @[MixedNode.scala:551:17]
assign auto_tl_out_15_a_bits_param_0 = x1_tlNodeOut_14_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] x1_tlNodeIn_14_a_bits_size; // @[MixedNode.scala:551:17]
assign auto_tl_out_15_a_bits_size_0 = x1_tlNodeOut_14_a_bits_size; // @[MixedNode.scala:542:17]
wire [4:0] x1_tlNodeIn_14_a_bits_source; // @[MixedNode.scala:551:17]
assign auto_tl_out_15_a_bits_source_0 = x1_tlNodeOut_14_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] x1_tlNodeIn_14_a_bits_address; // @[MixedNode.scala:551:17]
assign auto_tl_out_15_a_bits_address_0 = x1_tlNodeOut_14_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] x1_tlNodeIn_14_a_bits_mask; // @[MixedNode.scala:551:17]
assign auto_tl_out_15_a_bits_mask_0 = x1_tlNodeOut_14_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] x1_tlNodeIn_14_a_bits_data; // @[MixedNode.scala:551:17]
assign auto_tl_out_15_a_bits_data_0 = x1_tlNodeOut_14_a_bits_data; // @[MixedNode.scala:542:17]
wire x1_tlNodeIn_14_a_bits_corrupt; // @[MixedNode.scala:551:17]
assign auto_tl_out_15_a_bits_corrupt_0 = x1_tlNodeOut_14_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire x1_tlNodeIn_14_d_ready; // @[MixedNode.scala:551:17]
assign auto_tl_out_15_d_ready_0 = x1_tlNodeOut_14_d_ready; // @[MixedNode.scala:542:17]
wire x1_tlNodeIn_14_d_valid = x1_tlNodeOut_14_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] x1_tlNodeIn_14_d_bits_opcode = x1_tlNodeOut_14_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] x1_tlNodeIn_14_d_bits_param = x1_tlNodeOut_14_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] x1_tlNodeIn_14_d_bits_size = x1_tlNodeOut_14_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [4:0] x1_tlNodeIn_14_d_bits_source = x1_tlNodeOut_14_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] x1_tlNodeIn_14_d_bits_sink = x1_tlNodeOut_14_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlNodeIn_14_d_bits_denied = x1_tlNodeOut_14_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] x1_tlNodeIn_14_d_bits_data = x1_tlNodeOut_14_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlNodeIn_14_d_bits_corrupt = x1_tlNodeOut_14_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlNodeIn_15_a_ready = x1_tlNodeOut_15_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlNodeIn_15_a_valid; // @[MixedNode.scala:551:17]
assign auto_tl_out_16_a_valid_0 = x1_tlNodeOut_15_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeIn_15_a_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_tl_out_16_a_bits_opcode_0 = x1_tlNodeOut_15_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeIn_15_a_bits_param; // @[MixedNode.scala:551:17]
assign auto_tl_out_16_a_bits_param_0 = x1_tlNodeOut_15_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] x1_tlNodeIn_15_a_bits_size; // @[MixedNode.scala:551:17]
assign auto_tl_out_16_a_bits_size_0 = x1_tlNodeOut_15_a_bits_size; // @[MixedNode.scala:542:17]
wire [4:0] x1_tlNodeIn_15_a_bits_source; // @[MixedNode.scala:551:17]
assign auto_tl_out_16_a_bits_source_0 = x1_tlNodeOut_15_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] x1_tlNodeIn_15_a_bits_address; // @[MixedNode.scala:551:17]
assign auto_tl_out_16_a_bits_address_0 = x1_tlNodeOut_15_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] x1_tlNodeIn_15_a_bits_mask; // @[MixedNode.scala:551:17]
assign auto_tl_out_16_a_bits_mask_0 = x1_tlNodeOut_15_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] x1_tlNodeIn_15_a_bits_data; // @[MixedNode.scala:551:17]
assign auto_tl_out_16_a_bits_data_0 = x1_tlNodeOut_15_a_bits_data; // @[MixedNode.scala:542:17]
wire x1_tlNodeIn_15_a_bits_corrupt; // @[MixedNode.scala:551:17]
assign auto_tl_out_16_a_bits_corrupt_0 = x1_tlNodeOut_15_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire x1_tlNodeIn_15_d_ready; // @[MixedNode.scala:551:17]
assign auto_tl_out_16_d_ready_0 = x1_tlNodeOut_15_d_ready; // @[MixedNode.scala:542:17]
wire x1_tlNodeIn_15_d_valid = x1_tlNodeOut_15_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] x1_tlNodeIn_15_d_bits_opcode = x1_tlNodeOut_15_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] x1_tlNodeIn_15_d_bits_param = x1_tlNodeOut_15_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] x1_tlNodeIn_15_d_bits_size = x1_tlNodeOut_15_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [4:0] x1_tlNodeIn_15_d_bits_source = x1_tlNodeOut_15_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] x1_tlNodeIn_15_d_bits_sink = x1_tlNodeOut_15_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlNodeIn_15_d_bits_denied = x1_tlNodeOut_15_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] x1_tlNodeIn_15_d_bits_data = x1_tlNodeOut_15_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlNodeIn_15_d_bits_corrupt = x1_tlNodeOut_15_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlNodeIn_16_a_ready = x1_tlNodeOut_16_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlNodeIn_16_a_valid; // @[MixedNode.scala:551:17]
assign auto_tl_out_17_a_valid_0 = x1_tlNodeOut_16_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeIn_16_a_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_tl_out_17_a_bits_opcode_0 = x1_tlNodeOut_16_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlNodeIn_16_a_bits_param; // @[MixedNode.scala:551:17]
assign auto_tl_out_17_a_bits_param_0 = x1_tlNodeOut_16_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] x1_tlNodeIn_16_a_bits_size; // @[MixedNode.scala:551:17]
assign auto_tl_out_17_a_bits_size_0 = x1_tlNodeOut_16_a_bits_size; // @[MixedNode.scala:542:17]
wire [4:0] x1_tlNodeIn_16_a_bits_source; // @[MixedNode.scala:551:17]
assign auto_tl_out_17_a_bits_source_0 = x1_tlNodeOut_16_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] x1_tlNodeIn_16_a_bits_address; // @[MixedNode.scala:551:17]
assign auto_tl_out_17_a_bits_address_0 = x1_tlNodeOut_16_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] x1_tlNodeIn_16_a_bits_mask; // @[MixedNode.scala:551:17]
assign auto_tl_out_17_a_bits_mask_0 = x1_tlNodeOut_16_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] x1_tlNodeIn_16_a_bits_data; // @[MixedNode.scala:551:17]
assign auto_tl_out_17_a_bits_data_0 = x1_tlNodeOut_16_a_bits_data; // @[MixedNode.scala:542:17]
wire x1_tlNodeIn_16_a_bits_corrupt; // @[MixedNode.scala:551:17]
assign auto_tl_out_17_a_bits_corrupt_0 = x1_tlNodeOut_16_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire x1_tlNodeIn_16_d_ready; // @[MixedNode.scala:551:17]
assign auto_tl_out_17_d_ready_0 = x1_tlNodeOut_16_d_ready; // @[MixedNode.scala:542:17]
wire x1_tlNodeIn_16_d_valid = x1_tlNodeOut_16_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] x1_tlNodeIn_16_d_bits_opcode = x1_tlNodeOut_16_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] x1_tlNodeIn_16_d_bits_param = x1_tlNodeOut_16_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] x1_tlNodeIn_16_d_bits_size = x1_tlNodeOut_16_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [4:0] x1_tlNodeIn_16_d_bits_source = x1_tlNodeOut_16_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] x1_tlNodeIn_16_d_bits_sink = x1_tlNodeOut_16_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlNodeIn_16_d_bits_denied = x1_tlNodeOut_16_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] x1_tlNodeIn_16_d_bits_data = x1_tlNodeOut_16_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlNodeIn_16_d_bits_corrupt = x1_tlNodeOut_16_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign tlNodeOut_a_valid = tlNodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign tlNodeOut_a_bits_opcode = tlNodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign tlNodeOut_a_bits_param = tlNodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign tlNodeOut_a_bits_size = tlNodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign tlNodeOut_a_bits_source = tlNodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign tlNodeOut_a_bits_address = tlNodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign tlNodeOut_a_bits_mask = tlNodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign tlNodeOut_a_bits_data = tlNodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign tlNodeOut_a_bits_corrupt = tlNodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign tlNodeOut_d_ready = tlNodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_a_valid = x1_tlNodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_a_bits_opcode = x1_tlNodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_a_bits_param = x1_tlNodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_a_bits_size = x1_tlNodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_a_bits_source = x1_tlNodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_a_bits_address = x1_tlNodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_a_bits_mask = x1_tlNodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_a_bits_data = x1_tlNodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_a_bits_corrupt = x1_tlNodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_d_ready = x1_tlNodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_1_a_valid = x1_tlNodeIn_1_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_1_a_bits_opcode = x1_tlNodeIn_1_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_1_a_bits_param = x1_tlNodeIn_1_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_1_a_bits_size = x1_tlNodeIn_1_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_1_a_bits_source = x1_tlNodeIn_1_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_1_a_bits_address = x1_tlNodeIn_1_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_1_a_bits_mask = x1_tlNodeIn_1_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_1_a_bits_data = x1_tlNodeIn_1_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_1_a_bits_corrupt = x1_tlNodeIn_1_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_1_d_ready = x1_tlNodeIn_1_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_2_a_valid = x1_tlNodeIn_2_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_2_a_bits_opcode = x1_tlNodeIn_2_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_2_a_bits_param = x1_tlNodeIn_2_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_2_a_bits_size = x1_tlNodeIn_2_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_2_a_bits_source = x1_tlNodeIn_2_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_2_a_bits_address = x1_tlNodeIn_2_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_2_a_bits_mask = x1_tlNodeIn_2_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_2_a_bits_data = x1_tlNodeIn_2_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_2_a_bits_corrupt = x1_tlNodeIn_2_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_2_d_ready = x1_tlNodeIn_2_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_3_a_valid = x1_tlNodeIn_3_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_3_a_bits_opcode = x1_tlNodeIn_3_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_3_a_bits_param = x1_tlNodeIn_3_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_3_a_bits_size = x1_tlNodeIn_3_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_3_a_bits_source = x1_tlNodeIn_3_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_3_a_bits_address = x1_tlNodeIn_3_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_3_a_bits_mask = x1_tlNodeIn_3_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_3_a_bits_data = x1_tlNodeIn_3_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_3_a_bits_corrupt = x1_tlNodeIn_3_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_3_d_ready = x1_tlNodeIn_3_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_4_a_valid = x1_tlNodeIn_4_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_4_a_bits_opcode = x1_tlNodeIn_4_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_4_a_bits_param = x1_tlNodeIn_4_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_4_a_bits_size = x1_tlNodeIn_4_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_4_a_bits_source = x1_tlNodeIn_4_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_4_a_bits_address = x1_tlNodeIn_4_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_4_a_bits_mask = x1_tlNodeIn_4_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_4_a_bits_data = x1_tlNodeIn_4_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_4_a_bits_corrupt = x1_tlNodeIn_4_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_4_d_ready = x1_tlNodeIn_4_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_5_a_valid = x1_tlNodeIn_5_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_5_a_bits_opcode = x1_tlNodeIn_5_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_5_a_bits_param = x1_tlNodeIn_5_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_5_a_bits_size = x1_tlNodeIn_5_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_5_a_bits_source = x1_tlNodeIn_5_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_5_a_bits_address = x1_tlNodeIn_5_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_5_a_bits_mask = x1_tlNodeIn_5_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_5_a_bits_data = x1_tlNodeIn_5_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_5_a_bits_corrupt = x1_tlNodeIn_5_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_5_d_ready = x1_tlNodeIn_5_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_6_a_valid = x1_tlNodeIn_6_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_6_a_bits_opcode = x1_tlNodeIn_6_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_6_a_bits_param = x1_tlNodeIn_6_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_6_a_bits_size = x1_tlNodeIn_6_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_6_a_bits_source = x1_tlNodeIn_6_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_6_a_bits_address = x1_tlNodeIn_6_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_6_a_bits_mask = x1_tlNodeIn_6_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_6_a_bits_data = x1_tlNodeIn_6_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_6_a_bits_corrupt = x1_tlNodeIn_6_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_6_d_ready = x1_tlNodeIn_6_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_7_a_valid = x1_tlNodeIn_7_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_7_a_bits_opcode = x1_tlNodeIn_7_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_7_a_bits_param = x1_tlNodeIn_7_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_7_a_bits_size = x1_tlNodeIn_7_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_7_a_bits_source = x1_tlNodeIn_7_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_7_a_bits_address = x1_tlNodeIn_7_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_7_a_bits_mask = x1_tlNodeIn_7_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_7_a_bits_data = x1_tlNodeIn_7_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_7_a_bits_corrupt = x1_tlNodeIn_7_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_7_d_ready = x1_tlNodeIn_7_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_8_a_valid = x1_tlNodeIn_8_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_8_a_bits_opcode = x1_tlNodeIn_8_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_8_a_bits_param = x1_tlNodeIn_8_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_8_a_bits_size = x1_tlNodeIn_8_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_8_a_bits_source = x1_tlNodeIn_8_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_8_a_bits_address = x1_tlNodeIn_8_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_8_a_bits_mask = x1_tlNodeIn_8_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_8_a_bits_data = x1_tlNodeIn_8_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_8_a_bits_corrupt = x1_tlNodeIn_8_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_8_d_ready = x1_tlNodeIn_8_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_9_a_valid = x1_tlNodeIn_9_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_9_a_bits_opcode = x1_tlNodeIn_9_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_9_a_bits_param = x1_tlNodeIn_9_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_9_a_bits_size = x1_tlNodeIn_9_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_9_a_bits_source = x1_tlNodeIn_9_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_9_a_bits_address = x1_tlNodeIn_9_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_9_a_bits_mask = x1_tlNodeIn_9_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_9_a_bits_data = x1_tlNodeIn_9_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_9_a_bits_corrupt = x1_tlNodeIn_9_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_9_d_ready = x1_tlNodeIn_9_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_10_a_valid = x1_tlNodeIn_10_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_10_a_bits_opcode = x1_tlNodeIn_10_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_10_a_bits_param = x1_tlNodeIn_10_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_10_a_bits_size = x1_tlNodeIn_10_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_10_a_bits_source = x1_tlNodeIn_10_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_10_a_bits_address = x1_tlNodeIn_10_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_10_a_bits_mask = x1_tlNodeIn_10_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_10_a_bits_data = x1_tlNodeIn_10_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_10_a_bits_corrupt = x1_tlNodeIn_10_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_10_d_ready = x1_tlNodeIn_10_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_11_a_valid = x1_tlNodeIn_11_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_11_a_bits_opcode = x1_tlNodeIn_11_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_11_a_bits_param = x1_tlNodeIn_11_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_11_a_bits_size = x1_tlNodeIn_11_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_11_a_bits_source = x1_tlNodeIn_11_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_11_a_bits_address = x1_tlNodeIn_11_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_11_a_bits_mask = x1_tlNodeIn_11_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_11_a_bits_data = x1_tlNodeIn_11_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_11_a_bits_corrupt = x1_tlNodeIn_11_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_11_d_ready = x1_tlNodeIn_11_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_12_a_valid = x1_tlNodeIn_12_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_12_a_bits_opcode = x1_tlNodeIn_12_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_12_a_bits_param = x1_tlNodeIn_12_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_12_a_bits_size = x1_tlNodeIn_12_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_12_a_bits_source = x1_tlNodeIn_12_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_12_a_bits_address = x1_tlNodeIn_12_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_12_a_bits_mask = x1_tlNodeIn_12_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_12_a_bits_data = x1_tlNodeIn_12_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_12_a_bits_corrupt = x1_tlNodeIn_12_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_12_d_ready = x1_tlNodeIn_12_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_13_a_valid = x1_tlNodeIn_13_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_13_a_bits_opcode = x1_tlNodeIn_13_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_13_a_bits_param = x1_tlNodeIn_13_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_13_a_bits_size = x1_tlNodeIn_13_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_13_a_bits_source = x1_tlNodeIn_13_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_13_a_bits_address = x1_tlNodeIn_13_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_13_a_bits_mask = x1_tlNodeIn_13_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_13_a_bits_data = x1_tlNodeIn_13_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_13_a_bits_corrupt = x1_tlNodeIn_13_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_13_d_ready = x1_tlNodeIn_13_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_14_a_valid = x1_tlNodeIn_14_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_14_a_bits_opcode = x1_tlNodeIn_14_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_14_a_bits_param = x1_tlNodeIn_14_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_14_a_bits_size = x1_tlNodeIn_14_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_14_a_bits_source = x1_tlNodeIn_14_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_14_a_bits_address = x1_tlNodeIn_14_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_14_a_bits_mask = x1_tlNodeIn_14_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_14_a_bits_data = x1_tlNodeIn_14_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_14_a_bits_corrupt = x1_tlNodeIn_14_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_14_d_ready = x1_tlNodeIn_14_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_15_a_valid = x1_tlNodeIn_15_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_15_a_bits_opcode = x1_tlNodeIn_15_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_15_a_bits_param = x1_tlNodeIn_15_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_15_a_bits_size = x1_tlNodeIn_15_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_15_a_bits_source = x1_tlNodeIn_15_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_15_a_bits_address = x1_tlNodeIn_15_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_15_a_bits_mask = x1_tlNodeIn_15_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_15_a_bits_data = x1_tlNodeIn_15_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_15_a_bits_corrupt = x1_tlNodeIn_15_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_15_d_ready = x1_tlNodeIn_15_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_16_a_valid = x1_tlNodeIn_16_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_16_a_bits_opcode = x1_tlNodeIn_16_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_16_a_bits_param = x1_tlNodeIn_16_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_16_a_bits_size = x1_tlNodeIn_16_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_16_a_bits_source = x1_tlNodeIn_16_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_16_a_bits_address = x1_tlNodeIn_16_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_16_a_bits_mask = x1_tlNodeIn_16_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_16_a_bits_data = x1_tlNodeIn_16_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_16_a_bits_corrupt = x1_tlNodeIn_16_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlNodeOut_16_d_ready = x1_tlNodeIn_16_d_ready; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] _GEN = _cmd_router_io_HAS_INTERMEDIATE_CACHE ? 64'h0 : _cmd_router_io_LATENCY_INJECTION_CYCLES; // @[ZstdCompressor.scala:112:26, :185:63]
wire [63:0] _l2_mf_seqwriter_io_latency_inject_cycles_T; // @[ZstdCompressor.scala:185:63]
assign _l2_mf_seqwriter_io_latency_inject_cycles_T = _GEN; // @[ZstdCompressor.scala:185:63]
wire [63:0] _l2_mf_litwriter_io_latency_inject_cycles_T; // @[ZstdCompressor.scala:186:63]
assign _l2_mf_litwriter_io_latency_inject_cycles_T = _GEN; // @[ZstdCompressor.scala:185:63, :186:63]
wire [63:0] _l2_huf_lit_reader_io_latency_inject_cycles_T; // @[ZstdCompressor.scala:188:65]
assign _l2_huf_lit_reader_io_latency_inject_cycles_T = _GEN; // @[ZstdCompressor.scala:185:63, :188:65]
wire [63:0] _l2_huf_dic_reader_io_latency_inject_cycles_T; // @[ZstdCompressor.scala:189:65]
assign _l2_huf_dic_reader_io_latency_inject_cycles_T = _GEN; // @[ZstdCompressor.scala:185:63, :189:65]
wire [63:0] _l2_seq_reader_io_latency_inject_cycles_T; // @[ZstdCompressor.scala:195:61]
assign _l2_seq_reader_io_latency_inject_cycles_T = _GEN; // @[ZstdCompressor.scala:185:63, :195:61]
wire [63:0] _l2_seq_reader2_io_latency_inject_cycles_T; // @[ZstdCompressor.scala:196:62]
assign _l2_seq_reader2_io_latency_inject_cycles_T = _GEN; // @[ZstdCompressor.scala:185:63, :196:62]
wire [63:0] _l2_raw_block_reader_io_latency_inject_cycles_T; // @[ZstdCompressor.scala:199:67]
assign _l2_raw_block_reader_io_latency_inject_cycles_T = _GEN; // @[ZstdCompressor.scala:185:63, :199:67]
wire [63:0] _l2_raw_lit_reader_io_latency_inject_cycles_T; // @[ZstdCompressor.scala:202:65]
assign _l2_raw_lit_reader_io_latency_inject_cycles_T = _GEN; // @[ZstdCompressor.scala:185:63, :202:65]
L2MemHelperLatencyInjection l2_fhdr_writer ( // @[ZstdCompressor.scala:38:34]
.clock (clock),
.reset (reset),
.auto_master_out_a_ready (_widget_auto_anon_in_a_ready), // @[WidthWidget.scala:230:28]
.auto_master_out_a_valid (_l2_fhdr_writer_auto_master_out_a_valid),
.auto_master_out_a_bits_opcode (_l2_fhdr_writer_auto_master_out_a_bits_opcode),
.auto_master_out_a_bits_param (_l2_fhdr_writer_auto_master_out_a_bits_param),
.auto_master_out_a_bits_size (_l2_fhdr_writer_auto_master_out_a_bits_size),
.auto_master_out_a_bits_source (_l2_fhdr_writer_auto_master_out_a_bits_source),
.auto_master_out_a_bits_address (_l2_fhdr_writer_auto_master_out_a_bits_address),
.auto_master_out_a_bits_mask (_l2_fhdr_writer_auto_master_out_a_bits_mask),
.auto_master_out_a_bits_data (_l2_fhdr_writer_auto_master_out_a_bits_data),
.auto_master_out_a_bits_corrupt (_l2_fhdr_writer_auto_master_out_a_bits_corrupt),
.auto_master_out_d_ready (_l2_fhdr_writer_auto_master_out_d_ready),
.auto_master_out_d_valid (_widget_auto_anon_in_d_valid), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_opcode (_widget_auto_anon_in_d_bits_opcode), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_param (_widget_auto_anon_in_d_bits_param), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_size (_widget_auto_anon_in_d_bits_size), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_source (_widget_auto_anon_in_d_bits_source), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_sink (_widget_auto_anon_in_d_bits_sink), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_denied (_widget_auto_anon_in_d_bits_denied), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_data (_widget_auto_anon_in_d_bits_data), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_corrupt (_widget_auto_anon_in_d_bits_corrupt), // @[WidthWidget.scala:230:28]
.io_userif_req_ready (_l2_fhdr_writer_io_userif_req_ready),
.io_userif_req_valid (_controller_io_zstd_control_l2io_fhdr_l2userif_req_valid), // @[ZstdCompressor.scala:116:26]
.io_userif_req_bits_addr (_controller_io_zstd_control_l2io_fhdr_l2userif_req_bits_addr), // @[ZstdCompressor.scala:116:26]
.io_userif_req_bits_size (_controller_io_zstd_control_l2io_fhdr_l2userif_req_bits_size), // @[ZstdCompressor.scala:116:26]
.io_userif_req_bits_data (_controller_io_zstd_control_l2io_fhdr_l2userif_req_bits_data), // @[ZstdCompressor.scala:116:26]
.io_userif_resp_valid (_l2_fhdr_writer_io_userif_resp_valid),
.io_userif_resp_bits_data (_l2_fhdr_writer_io_userif_resp_bits_data),
.io_userif_no_memops_inflight (_l2_fhdr_writer_io_userif_no_memops_inflight),
.io_latency_inject_cycles (_cmd_router_io_LATENCY_INJECTION_CYCLES), // @[ZstdCompressor.scala:112:26]
.io_sfence (_cmd_router_io_sfence_out), // @[ZstdCompressor.scala:112:26]
.io_ptw_req_ready (io_ptw_0_req_ready_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_req_valid (io_ptw_0_req_valid_0),
.io_ptw_req_bits_bits_addr (io_ptw_0_req_bits_bits_addr_0),
.io_ptw_req_bits_bits_need_gpa (io_ptw_0_req_bits_bits_need_gpa_0),
.io_ptw_resp_valid (io_ptw_0_resp_valid_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_ae_ptw (io_ptw_0_resp_bits_ae_ptw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_ae_final (io_ptw_0_resp_bits_ae_final_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pf (io_ptw_0_resp_bits_pf_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gf (io_ptw_0_resp_bits_gf_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_hr (io_ptw_0_resp_bits_hr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_hw (io_ptw_0_resp_bits_hw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_hx (io_ptw_0_resp_bits_hx_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_reserved_for_future (io_ptw_0_resp_bits_pte_reserved_for_future_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_ppn (io_ptw_0_resp_bits_pte_ppn_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_reserved_for_software (io_ptw_0_resp_bits_pte_reserved_for_software_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_d (io_ptw_0_resp_bits_pte_d_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_a (io_ptw_0_resp_bits_pte_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_g (io_ptw_0_resp_bits_pte_g_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_u (io_ptw_0_resp_bits_pte_u_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_x (io_ptw_0_resp_bits_pte_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_w (io_ptw_0_resp_bits_pte_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_r (io_ptw_0_resp_bits_pte_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_v (io_ptw_0_resp_bits_pte_v_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_level (io_ptw_0_resp_bits_level_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_homogeneous (io_ptw_0_resp_bits_homogeneous_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gpa_valid (io_ptw_0_resp_bits_gpa_valid_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gpa_bits (io_ptw_0_resp_bits_gpa_bits_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gpa_is_pte (io_ptw_0_resp_bits_gpa_is_pte_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_ptbr_mode (io_ptw_0_ptbr_mode_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_ptbr_ppn (io_ptw_0_ptbr_ppn_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_debug (io_ptw_0_status_debug_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_cease (io_ptw_0_status_cease_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_wfi (io_ptw_0_status_wfi_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_isa (io_ptw_0_status_isa_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_dprv (io_ptw_0_status_dprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_dv (io_ptw_0_status_dv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_prv (io_ptw_0_status_prv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_v (io_ptw_0_status_v_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mpv (io_ptw_0_status_mpv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_gva (io_ptw_0_status_gva_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_tsr (io_ptw_0_status_tsr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_tw (io_ptw_0_status_tw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_tvm (io_ptw_0_status_tvm_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mxr (io_ptw_0_status_mxr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_sum (io_ptw_0_status_sum_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mprv (io_ptw_0_status_mprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_fs (io_ptw_0_status_fs_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mpp (io_ptw_0_status_mpp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_spp (io_ptw_0_status_spp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mpie (io_ptw_0_status_mpie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_spie (io_ptw_0_status_spie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mie (io_ptw_0_status_mie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_sie (io_ptw_0_status_sie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_hstatus_spvp (io_ptw_0_hstatus_spvp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_hstatus_spv (io_ptw_0_hstatus_spv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_hstatus_gva (io_ptw_0_hstatus_gva_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_debug (io_ptw_0_gstatus_debug_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_cease (io_ptw_0_gstatus_cease_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_wfi (io_ptw_0_gstatus_wfi_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_isa (io_ptw_0_gstatus_isa_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_dprv (io_ptw_0_gstatus_dprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_dv (io_ptw_0_gstatus_dv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_prv (io_ptw_0_gstatus_prv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_v (io_ptw_0_gstatus_v_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_zero2 (io_ptw_0_gstatus_zero2_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mpv (io_ptw_0_gstatus_mpv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_gva (io_ptw_0_gstatus_gva_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mbe (io_ptw_0_gstatus_mbe_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sbe (io_ptw_0_gstatus_sbe_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sxl (io_ptw_0_gstatus_sxl_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_zero1 (io_ptw_0_gstatus_zero1_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_tsr (io_ptw_0_gstatus_tsr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_tw (io_ptw_0_gstatus_tw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_tvm (io_ptw_0_gstatus_tvm_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mxr (io_ptw_0_gstatus_mxr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sum (io_ptw_0_gstatus_sum_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mprv (io_ptw_0_gstatus_mprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_fs (io_ptw_0_gstatus_fs_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mpp (io_ptw_0_gstatus_mpp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_vs (io_ptw_0_gstatus_vs_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_spp (io_ptw_0_gstatus_spp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mpie (io_ptw_0_gstatus_mpie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_ube (io_ptw_0_gstatus_ube_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_spie (io_ptw_0_gstatus_spie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_upie (io_ptw_0_gstatus_upie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mie (io_ptw_0_gstatus_mie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_hie (io_ptw_0_gstatus_hie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sie (io_ptw_0_gstatus_sie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_uie (io_ptw_0_gstatus_uie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_l (io_ptw_0_pmp_0_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_a (io_ptw_0_pmp_0_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_x (io_ptw_0_pmp_0_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_w (io_ptw_0_pmp_0_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_r (io_ptw_0_pmp_0_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_addr (io_ptw_0_pmp_0_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_mask (io_ptw_0_pmp_0_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_l (io_ptw_0_pmp_1_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_a (io_ptw_0_pmp_1_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_x (io_ptw_0_pmp_1_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_w (io_ptw_0_pmp_1_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_r (io_ptw_0_pmp_1_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_addr (io_ptw_0_pmp_1_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_mask (io_ptw_0_pmp_1_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_l (io_ptw_0_pmp_2_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_a (io_ptw_0_pmp_2_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_x (io_ptw_0_pmp_2_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_w (io_ptw_0_pmp_2_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_r (io_ptw_0_pmp_2_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_addr (io_ptw_0_pmp_2_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_mask (io_ptw_0_pmp_2_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_l (io_ptw_0_pmp_3_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_a (io_ptw_0_pmp_3_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_x (io_ptw_0_pmp_3_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_w (io_ptw_0_pmp_3_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_r (io_ptw_0_pmp_3_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_addr (io_ptw_0_pmp_3_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_mask (io_ptw_0_pmp_3_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_l (io_ptw_0_pmp_4_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_a (io_ptw_0_pmp_4_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_x (io_ptw_0_pmp_4_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_w (io_ptw_0_pmp_4_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_r (io_ptw_0_pmp_4_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_addr (io_ptw_0_pmp_4_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_mask (io_ptw_0_pmp_4_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_l (io_ptw_0_pmp_5_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_a (io_ptw_0_pmp_5_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_x (io_ptw_0_pmp_5_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_w (io_ptw_0_pmp_5_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_r (io_ptw_0_pmp_5_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_addr (io_ptw_0_pmp_5_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_mask (io_ptw_0_pmp_5_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_l (io_ptw_0_pmp_6_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_a (io_ptw_0_pmp_6_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_x (io_ptw_0_pmp_6_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_w (io_ptw_0_pmp_6_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_r (io_ptw_0_pmp_6_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_addr (io_ptw_0_pmp_6_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_mask (io_ptw_0_pmp_6_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_l (io_ptw_0_pmp_7_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_a (io_ptw_0_pmp_7_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_x (io_ptw_0_pmp_7_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_w (io_ptw_0_pmp_7_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_r (io_ptw_0_pmp_7_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_addr (io_ptw_0_pmp_7_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_mask (io_ptw_0_pmp_7_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_ren (io_ptw_0_customCSRs_csrs_0_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_wen (io_ptw_0_customCSRs_csrs_0_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_wdata (io_ptw_0_customCSRs_csrs_0_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_value (io_ptw_0_customCSRs_csrs_0_value_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_ren (io_ptw_0_customCSRs_csrs_1_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_wen (io_ptw_0_customCSRs_csrs_1_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_wdata (io_ptw_0_customCSRs_csrs_1_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_value (io_ptw_0_customCSRs_csrs_1_value_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_ren (io_ptw_0_customCSRs_csrs_2_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_wen (io_ptw_0_customCSRs_csrs_2_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_wdata (io_ptw_0_customCSRs_csrs_2_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_value (io_ptw_0_customCSRs_csrs_2_value_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_ren (io_ptw_0_customCSRs_csrs_3_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_wen (io_ptw_0_customCSRs_csrs_3_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_wdata (io_ptw_0_customCSRs_csrs_3_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_value (io_ptw_0_customCSRs_csrs_3_value_0), // @[ZstdCompressor.scala:95:7]
.io_status_valid (_cmd_router_io_dmem_status_out_valid), // @[ZstdCompressor.scala:112:26]
.io_status_bits_debug (_cmd_router_io_dmem_status_out_bits_status_debug), // @[ZstdCompressor.scala:112:26]
.io_status_bits_cease (_cmd_router_io_dmem_status_out_bits_status_cease), // @[ZstdCompressor.scala:112:26]
.io_status_bits_wfi (_cmd_router_io_dmem_status_out_bits_status_wfi), // @[ZstdCompressor.scala:112:26]
.io_status_bits_isa (_cmd_router_io_dmem_status_out_bits_status_isa), // @[ZstdCompressor.scala:112:26]
.io_status_bits_dprv (_cmd_router_io_dmem_status_out_bits_status_dprv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_dv (_cmd_router_io_dmem_status_out_bits_status_dv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_prv (_cmd_router_io_dmem_status_out_bits_status_prv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_v (_cmd_router_io_dmem_status_out_bits_status_v), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sd (_cmd_router_io_dmem_status_out_bits_status_sd), // @[ZstdCompressor.scala:112:26]
.io_status_bits_zero2 (_cmd_router_io_dmem_status_out_bits_status_zero2), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mpv (_cmd_router_io_dmem_status_out_bits_status_mpv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_gva (_cmd_router_io_dmem_status_out_bits_status_gva), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mbe (_cmd_router_io_dmem_status_out_bits_status_mbe), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sbe (_cmd_router_io_dmem_status_out_bits_status_sbe), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sxl (_cmd_router_io_dmem_status_out_bits_status_sxl), // @[ZstdCompressor.scala:112:26]
.io_status_bits_uxl (_cmd_router_io_dmem_status_out_bits_status_uxl), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sd_rv32 (_cmd_router_io_dmem_status_out_bits_status_sd_rv32), // @[ZstdCompressor.scala:112:26]
.io_status_bits_zero1 (_cmd_router_io_dmem_status_out_bits_status_zero1), // @[ZstdCompressor.scala:112:26]
.io_status_bits_tsr (_cmd_router_io_dmem_status_out_bits_status_tsr), // @[ZstdCompressor.scala:112:26]
.io_status_bits_tw (_cmd_router_io_dmem_status_out_bits_status_tw), // @[ZstdCompressor.scala:112:26]
.io_status_bits_tvm (_cmd_router_io_dmem_status_out_bits_status_tvm), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mxr (_cmd_router_io_dmem_status_out_bits_status_mxr), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sum (_cmd_router_io_dmem_status_out_bits_status_sum), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mprv (_cmd_router_io_dmem_status_out_bits_status_mprv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_xs (_cmd_router_io_dmem_status_out_bits_status_xs), // @[ZstdCompressor.scala:112:26]
.io_status_bits_fs (_cmd_router_io_dmem_status_out_bits_status_fs), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mpp (_cmd_router_io_dmem_status_out_bits_status_mpp), // @[ZstdCompressor.scala:112:26]
.io_status_bits_vs (_cmd_router_io_dmem_status_out_bits_status_vs), // @[ZstdCompressor.scala:112:26]
.io_status_bits_spp (_cmd_router_io_dmem_status_out_bits_status_spp), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mpie (_cmd_router_io_dmem_status_out_bits_status_mpie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_ube (_cmd_router_io_dmem_status_out_bits_status_ube), // @[ZstdCompressor.scala:112:26]
.io_status_bits_spie (_cmd_router_io_dmem_status_out_bits_status_spie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_upie (_cmd_router_io_dmem_status_out_bits_status_upie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mie (_cmd_router_io_dmem_status_out_bits_status_mie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_hie (_cmd_router_io_dmem_status_out_bits_status_hie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sie (_cmd_router_io_dmem_status_out_bits_status_sie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_uie (_cmd_router_io_dmem_status_out_bits_status_uie) // @[ZstdCompressor.scala:112:26]
); // @[ZstdCompressor.scala:38:34]
TLWidthWidget32 widget ( // @[WidthWidget.scala:230:28]
.clock (clock),
.reset (reset),
.auto_anon_in_a_ready (_widget_auto_anon_in_a_ready),
.auto_anon_in_a_valid (_l2_fhdr_writer_auto_master_out_a_valid), // @[ZstdCompressor.scala:38:34]
.auto_anon_in_a_bits_opcode (_l2_fhdr_writer_auto_master_out_a_bits_opcode), // @[ZstdCompressor.scala:38:34]
.auto_anon_in_a_bits_param (_l2_fhdr_writer_auto_master_out_a_bits_param), // @[ZstdCompressor.scala:38:34]
.auto_anon_in_a_bits_size (_l2_fhdr_writer_auto_master_out_a_bits_size), // @[ZstdCompressor.scala:38:34]
.auto_anon_in_a_bits_source (_l2_fhdr_writer_auto_master_out_a_bits_source), // @[ZstdCompressor.scala:38:34]
.auto_anon_in_a_bits_address (_l2_fhdr_writer_auto_master_out_a_bits_address), // @[ZstdCompressor.scala:38:34]
.auto_anon_in_a_bits_mask (_l2_fhdr_writer_auto_master_out_a_bits_mask), // @[ZstdCompressor.scala:38:34]
.auto_anon_in_a_bits_data (_l2_fhdr_writer_auto_master_out_a_bits_data), // @[ZstdCompressor.scala:38:34]
.auto_anon_in_a_bits_corrupt (_l2_fhdr_writer_auto_master_out_a_bits_corrupt), // @[ZstdCompressor.scala:38:34]
.auto_anon_in_d_ready (_l2_fhdr_writer_auto_master_out_d_ready), // @[ZstdCompressor.scala:38:34]
.auto_anon_in_d_valid (_widget_auto_anon_in_d_valid),
.auto_anon_in_d_bits_opcode (_widget_auto_anon_in_d_bits_opcode),
.auto_anon_in_d_bits_param (_widget_auto_anon_in_d_bits_param),
.auto_anon_in_d_bits_size (_widget_auto_anon_in_d_bits_size),
.auto_anon_in_d_bits_source (_widget_auto_anon_in_d_bits_source),
.auto_anon_in_d_bits_sink (_widget_auto_anon_in_d_bits_sink),
.auto_anon_in_d_bits_denied (_widget_auto_anon_in_d_bits_denied),
.auto_anon_in_d_bits_data (_widget_auto_anon_in_d_bits_data),
.auto_anon_in_d_bits_corrupt (_widget_auto_anon_in_d_bits_corrupt),
.auto_anon_out_a_ready (tlNodeIn_a_ready), // @[MixedNode.scala:551:17]
.auto_anon_out_a_valid (tlNodeIn_a_valid),
.auto_anon_out_a_bits_opcode (tlNodeIn_a_bits_opcode),
.auto_anon_out_a_bits_param (tlNodeIn_a_bits_param),
.auto_anon_out_a_bits_size (tlNodeIn_a_bits_size),
.auto_anon_out_a_bits_source (tlNodeIn_a_bits_source),
.auto_anon_out_a_bits_address (tlNodeIn_a_bits_address),
.auto_anon_out_a_bits_mask (tlNodeIn_a_bits_mask),
.auto_anon_out_a_bits_data (tlNodeIn_a_bits_data),
.auto_anon_out_a_bits_corrupt (tlNodeIn_a_bits_corrupt),
.auto_anon_out_d_ready (tlNodeIn_d_ready),
.auto_anon_out_d_valid (tlNodeIn_d_valid), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_opcode (tlNodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_param (tlNodeIn_d_bits_param), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_size (tlNodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_source (tlNodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_sink (tlNodeIn_d_bits_sink), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_denied (tlNodeIn_d_bits_denied), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_data (tlNodeIn_d_bits_data), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_corrupt (tlNodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[WidthWidget.scala:230:28]
L2MemHelperLatencyInjection_1 l2_bhdr_writer ( // @[ZstdCompressor.scala:42:34]
.clock (clock),
.reset (reset),
.auto_master_out_a_ready (_widget_1_auto_anon_in_a_ready), // @[WidthWidget.scala:230:28]
.auto_master_out_a_valid (_l2_bhdr_writer_auto_master_out_a_valid),
.auto_master_out_a_bits_opcode (_l2_bhdr_writer_auto_master_out_a_bits_opcode),
.auto_master_out_a_bits_param (_l2_bhdr_writer_auto_master_out_a_bits_param),
.auto_master_out_a_bits_size (_l2_bhdr_writer_auto_master_out_a_bits_size),
.auto_master_out_a_bits_source (_l2_bhdr_writer_auto_master_out_a_bits_source),
.auto_master_out_a_bits_address (_l2_bhdr_writer_auto_master_out_a_bits_address),
.auto_master_out_a_bits_mask (_l2_bhdr_writer_auto_master_out_a_bits_mask),
.auto_master_out_a_bits_data (_l2_bhdr_writer_auto_master_out_a_bits_data),
.auto_master_out_a_bits_corrupt (_l2_bhdr_writer_auto_master_out_a_bits_corrupt),
.auto_master_out_d_ready (_l2_bhdr_writer_auto_master_out_d_ready),
.auto_master_out_d_valid (_widget_1_auto_anon_in_d_valid), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_opcode (_widget_1_auto_anon_in_d_bits_opcode), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_param (_widget_1_auto_anon_in_d_bits_param), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_size (_widget_1_auto_anon_in_d_bits_size), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_source (_widget_1_auto_anon_in_d_bits_source), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_sink (_widget_1_auto_anon_in_d_bits_sink), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_denied (_widget_1_auto_anon_in_d_bits_denied), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_data (_widget_1_auto_anon_in_d_bits_data), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_corrupt (_widget_1_auto_anon_in_d_bits_corrupt), // @[WidthWidget.scala:230:28]
.io_userif_req_ready (_l2_bhdr_writer_io_userif_req_ready),
.io_userif_req_valid (_controller_io_zstd_control_l2io_bhdr_l2userif_req_valid), // @[ZstdCompressor.scala:116:26]
.io_userif_req_bits_addr (_controller_io_zstd_control_l2io_bhdr_l2userif_req_bits_addr), // @[ZstdCompressor.scala:116:26]
.io_userif_req_bits_size (_controller_io_zstd_control_l2io_bhdr_l2userif_req_bits_size), // @[ZstdCompressor.scala:116:26]
.io_userif_req_bits_data (_controller_io_zstd_control_l2io_bhdr_l2userif_req_bits_data), // @[ZstdCompressor.scala:116:26]
.io_userif_resp_valid (_l2_bhdr_writer_io_userif_resp_valid),
.io_userif_resp_bits_data (_l2_bhdr_writer_io_userif_resp_bits_data),
.io_userif_no_memops_inflight (_l2_bhdr_writer_io_userif_no_memops_inflight),
.io_latency_inject_cycles (_cmd_router_io_LATENCY_INJECTION_CYCLES), // @[ZstdCompressor.scala:112:26]
.io_sfence (_cmd_router_io_sfence_out), // @[ZstdCompressor.scala:112:26]
.io_ptw_req_ready (io_ptw_1_req_ready_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_req_valid (io_ptw_1_req_valid_0),
.io_ptw_req_bits_bits_addr (io_ptw_1_req_bits_bits_addr_0),
.io_ptw_req_bits_bits_need_gpa (io_ptw_1_req_bits_bits_need_gpa_0),
.io_ptw_resp_valid (io_ptw_1_resp_valid_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_ae_ptw (io_ptw_1_resp_bits_ae_ptw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_ae_final (io_ptw_1_resp_bits_ae_final_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pf (io_ptw_1_resp_bits_pf_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gf (io_ptw_1_resp_bits_gf_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_hr (io_ptw_1_resp_bits_hr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_hw (io_ptw_1_resp_bits_hw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_hx (io_ptw_1_resp_bits_hx_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_reserved_for_future (io_ptw_1_resp_bits_pte_reserved_for_future_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_ppn (io_ptw_1_resp_bits_pte_ppn_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_reserved_for_software (io_ptw_1_resp_bits_pte_reserved_for_software_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_d (io_ptw_1_resp_bits_pte_d_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_a (io_ptw_1_resp_bits_pte_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_g (io_ptw_1_resp_bits_pte_g_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_u (io_ptw_1_resp_bits_pte_u_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_x (io_ptw_1_resp_bits_pte_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_w (io_ptw_1_resp_bits_pte_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_r (io_ptw_1_resp_bits_pte_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_v (io_ptw_1_resp_bits_pte_v_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_level (io_ptw_1_resp_bits_level_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_homogeneous (io_ptw_1_resp_bits_homogeneous_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gpa_valid (io_ptw_1_resp_bits_gpa_valid_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gpa_bits (io_ptw_1_resp_bits_gpa_bits_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gpa_is_pte (io_ptw_1_resp_bits_gpa_is_pte_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_ptbr_mode (io_ptw_1_ptbr_mode_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_ptbr_ppn (io_ptw_1_ptbr_ppn_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_debug (io_ptw_1_status_debug_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_cease (io_ptw_1_status_cease_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_wfi (io_ptw_1_status_wfi_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_isa (io_ptw_1_status_isa_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_dprv (io_ptw_1_status_dprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_dv (io_ptw_1_status_dv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_prv (io_ptw_1_status_prv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_v (io_ptw_1_status_v_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mpv (io_ptw_1_status_mpv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_gva (io_ptw_1_status_gva_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_tsr (io_ptw_1_status_tsr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_tw (io_ptw_1_status_tw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_tvm (io_ptw_1_status_tvm_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mxr (io_ptw_1_status_mxr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_sum (io_ptw_1_status_sum_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mprv (io_ptw_1_status_mprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_fs (io_ptw_1_status_fs_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mpp (io_ptw_1_status_mpp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_spp (io_ptw_1_status_spp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mpie (io_ptw_1_status_mpie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_spie (io_ptw_1_status_spie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mie (io_ptw_1_status_mie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_sie (io_ptw_1_status_sie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_hstatus_spvp (io_ptw_1_hstatus_spvp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_hstatus_spv (io_ptw_1_hstatus_spv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_hstatus_gva (io_ptw_1_hstatus_gva_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_debug (io_ptw_1_gstatus_debug_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_cease (io_ptw_1_gstatus_cease_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_wfi (io_ptw_1_gstatus_wfi_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_isa (io_ptw_1_gstatus_isa_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_dprv (io_ptw_1_gstatus_dprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_dv (io_ptw_1_gstatus_dv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_prv (io_ptw_1_gstatus_prv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_v (io_ptw_1_gstatus_v_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_zero2 (io_ptw_1_gstatus_zero2_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mpv (io_ptw_1_gstatus_mpv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_gva (io_ptw_1_gstatus_gva_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mbe (io_ptw_1_gstatus_mbe_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sbe (io_ptw_1_gstatus_sbe_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sxl (io_ptw_1_gstatus_sxl_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_zero1 (io_ptw_1_gstatus_zero1_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_tsr (io_ptw_1_gstatus_tsr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_tw (io_ptw_1_gstatus_tw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_tvm (io_ptw_1_gstatus_tvm_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mxr (io_ptw_1_gstatus_mxr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sum (io_ptw_1_gstatus_sum_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mprv (io_ptw_1_gstatus_mprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_fs (io_ptw_1_gstatus_fs_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mpp (io_ptw_1_gstatus_mpp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_vs (io_ptw_1_gstatus_vs_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_spp (io_ptw_1_gstatus_spp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mpie (io_ptw_1_gstatus_mpie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_ube (io_ptw_1_gstatus_ube_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_spie (io_ptw_1_gstatus_spie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_upie (io_ptw_1_gstatus_upie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mie (io_ptw_1_gstatus_mie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_hie (io_ptw_1_gstatus_hie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sie (io_ptw_1_gstatus_sie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_uie (io_ptw_1_gstatus_uie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_l (io_ptw_1_pmp_0_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_a (io_ptw_1_pmp_0_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_x (io_ptw_1_pmp_0_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_w (io_ptw_1_pmp_0_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_r (io_ptw_1_pmp_0_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_addr (io_ptw_1_pmp_0_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_mask (io_ptw_1_pmp_0_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_l (io_ptw_1_pmp_1_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_a (io_ptw_1_pmp_1_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_x (io_ptw_1_pmp_1_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_w (io_ptw_1_pmp_1_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_r (io_ptw_1_pmp_1_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_addr (io_ptw_1_pmp_1_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_mask (io_ptw_1_pmp_1_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_l (io_ptw_1_pmp_2_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_a (io_ptw_1_pmp_2_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_x (io_ptw_1_pmp_2_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_w (io_ptw_1_pmp_2_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_r (io_ptw_1_pmp_2_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_addr (io_ptw_1_pmp_2_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_mask (io_ptw_1_pmp_2_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_l (io_ptw_1_pmp_3_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_a (io_ptw_1_pmp_3_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_x (io_ptw_1_pmp_3_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_w (io_ptw_1_pmp_3_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_r (io_ptw_1_pmp_3_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_addr (io_ptw_1_pmp_3_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_mask (io_ptw_1_pmp_3_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_l (io_ptw_1_pmp_4_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_a (io_ptw_1_pmp_4_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_x (io_ptw_1_pmp_4_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_w (io_ptw_1_pmp_4_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_r (io_ptw_1_pmp_4_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_addr (io_ptw_1_pmp_4_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_mask (io_ptw_1_pmp_4_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_l (io_ptw_1_pmp_5_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_a (io_ptw_1_pmp_5_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_x (io_ptw_1_pmp_5_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_w (io_ptw_1_pmp_5_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_r (io_ptw_1_pmp_5_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_addr (io_ptw_1_pmp_5_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_mask (io_ptw_1_pmp_5_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_l (io_ptw_1_pmp_6_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_a (io_ptw_1_pmp_6_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_x (io_ptw_1_pmp_6_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_w (io_ptw_1_pmp_6_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_r (io_ptw_1_pmp_6_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_addr (io_ptw_1_pmp_6_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_mask (io_ptw_1_pmp_6_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_l (io_ptw_1_pmp_7_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_a (io_ptw_1_pmp_7_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_x (io_ptw_1_pmp_7_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_w (io_ptw_1_pmp_7_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_r (io_ptw_1_pmp_7_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_addr (io_ptw_1_pmp_7_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_mask (io_ptw_1_pmp_7_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_ren (io_ptw_1_customCSRs_csrs_0_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_wen (io_ptw_1_customCSRs_csrs_0_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_wdata (io_ptw_1_customCSRs_csrs_0_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_value (io_ptw_1_customCSRs_csrs_0_value_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_ren (io_ptw_1_customCSRs_csrs_1_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_wen (io_ptw_1_customCSRs_csrs_1_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_wdata (io_ptw_1_customCSRs_csrs_1_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_value (io_ptw_1_customCSRs_csrs_1_value_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_ren (io_ptw_1_customCSRs_csrs_2_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_wen (io_ptw_1_customCSRs_csrs_2_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_wdata (io_ptw_1_customCSRs_csrs_2_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_value (io_ptw_1_customCSRs_csrs_2_value_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_ren (io_ptw_1_customCSRs_csrs_3_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_wen (io_ptw_1_customCSRs_csrs_3_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_wdata (io_ptw_1_customCSRs_csrs_3_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_value (io_ptw_1_customCSRs_csrs_3_value_0), // @[ZstdCompressor.scala:95:7]
.io_status_valid (_cmd_router_io_dmem_status_out_valid), // @[ZstdCompressor.scala:112:26]
.io_status_bits_debug (_cmd_router_io_dmem_status_out_bits_status_debug), // @[ZstdCompressor.scala:112:26]
.io_status_bits_cease (_cmd_router_io_dmem_status_out_bits_status_cease), // @[ZstdCompressor.scala:112:26]
.io_status_bits_wfi (_cmd_router_io_dmem_status_out_bits_status_wfi), // @[ZstdCompressor.scala:112:26]
.io_status_bits_isa (_cmd_router_io_dmem_status_out_bits_status_isa), // @[ZstdCompressor.scala:112:26]
.io_status_bits_dprv (_cmd_router_io_dmem_status_out_bits_status_dprv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_dv (_cmd_router_io_dmem_status_out_bits_status_dv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_prv (_cmd_router_io_dmem_status_out_bits_status_prv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_v (_cmd_router_io_dmem_status_out_bits_status_v), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sd (_cmd_router_io_dmem_status_out_bits_status_sd), // @[ZstdCompressor.scala:112:26]
.io_status_bits_zero2 (_cmd_router_io_dmem_status_out_bits_status_zero2), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mpv (_cmd_router_io_dmem_status_out_bits_status_mpv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_gva (_cmd_router_io_dmem_status_out_bits_status_gva), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mbe (_cmd_router_io_dmem_status_out_bits_status_mbe), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sbe (_cmd_router_io_dmem_status_out_bits_status_sbe), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sxl (_cmd_router_io_dmem_status_out_bits_status_sxl), // @[ZstdCompressor.scala:112:26]
.io_status_bits_uxl (_cmd_router_io_dmem_status_out_bits_status_uxl), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sd_rv32 (_cmd_router_io_dmem_status_out_bits_status_sd_rv32), // @[ZstdCompressor.scala:112:26]
.io_status_bits_zero1 (_cmd_router_io_dmem_status_out_bits_status_zero1), // @[ZstdCompressor.scala:112:26]
.io_status_bits_tsr (_cmd_router_io_dmem_status_out_bits_status_tsr), // @[ZstdCompressor.scala:112:26]
.io_status_bits_tw (_cmd_router_io_dmem_status_out_bits_status_tw), // @[ZstdCompressor.scala:112:26]
.io_status_bits_tvm (_cmd_router_io_dmem_status_out_bits_status_tvm), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mxr (_cmd_router_io_dmem_status_out_bits_status_mxr), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sum (_cmd_router_io_dmem_status_out_bits_status_sum), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mprv (_cmd_router_io_dmem_status_out_bits_status_mprv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_xs (_cmd_router_io_dmem_status_out_bits_status_xs), // @[ZstdCompressor.scala:112:26]
.io_status_bits_fs (_cmd_router_io_dmem_status_out_bits_status_fs), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mpp (_cmd_router_io_dmem_status_out_bits_status_mpp), // @[ZstdCompressor.scala:112:26]
.io_status_bits_vs (_cmd_router_io_dmem_status_out_bits_status_vs), // @[ZstdCompressor.scala:112:26]
.io_status_bits_spp (_cmd_router_io_dmem_status_out_bits_status_spp), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mpie (_cmd_router_io_dmem_status_out_bits_status_mpie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_ube (_cmd_router_io_dmem_status_out_bits_status_ube), // @[ZstdCompressor.scala:112:26]
.io_status_bits_spie (_cmd_router_io_dmem_status_out_bits_status_spie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_upie (_cmd_router_io_dmem_status_out_bits_status_upie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mie (_cmd_router_io_dmem_status_out_bits_status_mie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_hie (_cmd_router_io_dmem_status_out_bits_status_hie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sie (_cmd_router_io_dmem_status_out_bits_status_sie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_uie (_cmd_router_io_dmem_status_out_bits_status_uie) // @[ZstdCompressor.scala:112:26]
); // @[ZstdCompressor.scala:42:34]
TLWidthWidget32_1 widget_1 ( // @[WidthWidget.scala:230:28]
.clock (clock),
.reset (reset),
.auto_anon_in_a_ready (_widget_1_auto_anon_in_a_ready),
.auto_anon_in_a_valid (_l2_bhdr_writer_auto_master_out_a_valid), // @[ZstdCompressor.scala:42:34]
.auto_anon_in_a_bits_opcode (_l2_bhdr_writer_auto_master_out_a_bits_opcode), // @[ZstdCompressor.scala:42:34]
.auto_anon_in_a_bits_param (_l2_bhdr_writer_auto_master_out_a_bits_param), // @[ZstdCompressor.scala:42:34]
.auto_anon_in_a_bits_size (_l2_bhdr_writer_auto_master_out_a_bits_size), // @[ZstdCompressor.scala:42:34]
.auto_anon_in_a_bits_source (_l2_bhdr_writer_auto_master_out_a_bits_source), // @[ZstdCompressor.scala:42:34]
.auto_anon_in_a_bits_address (_l2_bhdr_writer_auto_master_out_a_bits_address), // @[ZstdCompressor.scala:42:34]
.auto_anon_in_a_bits_mask (_l2_bhdr_writer_auto_master_out_a_bits_mask), // @[ZstdCompressor.scala:42:34]
.auto_anon_in_a_bits_data (_l2_bhdr_writer_auto_master_out_a_bits_data), // @[ZstdCompressor.scala:42:34]
.auto_anon_in_a_bits_corrupt (_l2_bhdr_writer_auto_master_out_a_bits_corrupt), // @[ZstdCompressor.scala:42:34]
.auto_anon_in_d_ready (_l2_bhdr_writer_auto_master_out_d_ready), // @[ZstdCompressor.scala:42:34]
.auto_anon_in_d_valid (_widget_1_auto_anon_in_d_valid),
.auto_anon_in_d_bits_opcode (_widget_1_auto_anon_in_d_bits_opcode),
.auto_anon_in_d_bits_param (_widget_1_auto_anon_in_d_bits_param),
.auto_anon_in_d_bits_size (_widget_1_auto_anon_in_d_bits_size),
.auto_anon_in_d_bits_source (_widget_1_auto_anon_in_d_bits_source),
.auto_anon_in_d_bits_sink (_widget_1_auto_anon_in_d_bits_sink),
.auto_anon_in_d_bits_denied (_widget_1_auto_anon_in_d_bits_denied),
.auto_anon_in_d_bits_data (_widget_1_auto_anon_in_d_bits_data),
.auto_anon_in_d_bits_corrupt (_widget_1_auto_anon_in_d_bits_corrupt),
.auto_anon_out_a_ready (x1_tlNodeIn_a_ready), // @[MixedNode.scala:551:17]
.auto_anon_out_a_valid (x1_tlNodeIn_a_valid),
.auto_anon_out_a_bits_opcode (x1_tlNodeIn_a_bits_opcode),
.auto_anon_out_a_bits_param (x1_tlNodeIn_a_bits_param),
.auto_anon_out_a_bits_size (x1_tlNodeIn_a_bits_size),
.auto_anon_out_a_bits_source (x1_tlNodeIn_a_bits_source),
.auto_anon_out_a_bits_address (x1_tlNodeIn_a_bits_address),
.auto_anon_out_a_bits_mask (x1_tlNodeIn_a_bits_mask),
.auto_anon_out_a_bits_data (x1_tlNodeIn_a_bits_data),
.auto_anon_out_a_bits_corrupt (x1_tlNodeIn_a_bits_corrupt),
.auto_anon_out_d_ready (x1_tlNodeIn_d_ready),
.auto_anon_out_d_valid (x1_tlNodeIn_d_valid), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_opcode (x1_tlNodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_param (x1_tlNodeIn_d_bits_param), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_size (x1_tlNodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_source (x1_tlNodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_sink (x1_tlNodeIn_d_bits_sink), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_denied (x1_tlNodeIn_d_bits_denied), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_data (x1_tlNodeIn_d_bits_data), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_corrupt (x1_tlNodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[WidthWidget.scala:230:28]
L2MemHelperLatencyInjection_2 l2_mf_reader ( // @[ZstdCompressor.scala:46:32]
.clock (clock),
.reset (reset),
.auto_master_out_a_ready (_widget_2_auto_anon_in_a_ready), // @[WidthWidget.scala:230:28]
.auto_master_out_a_valid (_l2_mf_reader_auto_master_out_a_valid),
.auto_master_out_a_bits_opcode (_l2_mf_reader_auto_master_out_a_bits_opcode),
.auto_master_out_a_bits_param (_l2_mf_reader_auto_master_out_a_bits_param),
.auto_master_out_a_bits_size (_l2_mf_reader_auto_master_out_a_bits_size),
.auto_master_out_a_bits_source (_l2_mf_reader_auto_master_out_a_bits_source),
.auto_master_out_a_bits_address (_l2_mf_reader_auto_master_out_a_bits_address),
.auto_master_out_a_bits_mask (_l2_mf_reader_auto_master_out_a_bits_mask),
.auto_master_out_a_bits_data (_l2_mf_reader_auto_master_out_a_bits_data),
.auto_master_out_a_bits_corrupt (_l2_mf_reader_auto_master_out_a_bits_corrupt),
.auto_master_out_d_ready (_l2_mf_reader_auto_master_out_d_ready),
.auto_master_out_d_valid (_widget_2_auto_anon_in_d_valid), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_opcode (_widget_2_auto_anon_in_d_bits_opcode), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_param (_widget_2_auto_anon_in_d_bits_param), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_size (_widget_2_auto_anon_in_d_bits_size), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_source (_widget_2_auto_anon_in_d_bits_source), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_sink (_widget_2_auto_anon_in_d_bits_sink), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_denied (_widget_2_auto_anon_in_d_bits_denied), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_data (_widget_2_auto_anon_in_d_bits_data), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_corrupt (_widget_2_auto_anon_in_d_bits_corrupt), // @[WidthWidget.scala:230:28]
.io_userif_req_ready (_l2_mf_reader_io_userif_req_ready),
.io_userif_req_valid (_matchfinder_io_l2io_memloader_userif_req_valid), // @[ZstdCompressor.scala:129:27]
.io_userif_req_bits_addr (_matchfinder_io_l2io_memloader_userif_req_bits_addr), // @[ZstdCompressor.scala:129:27]
.io_userif_resp_ready (_matchfinder_io_l2io_memloader_userif_resp_ready), // @[ZstdCompressor.scala:129:27]
.io_userif_resp_valid (_l2_mf_reader_io_userif_resp_valid),
.io_userif_resp_bits_data (_l2_mf_reader_io_userif_resp_bits_data),
.io_userif_no_memops_inflight (_l2_mf_reader_io_userif_no_memops_inflight),
.io_latency_inject_cycles (_cmd_router_io_LATENCY_INJECTION_CYCLES), // @[ZstdCompressor.scala:112:26]
.io_sfence (_cmd_router_io_sfence_out), // @[ZstdCompressor.scala:112:26]
.io_ptw_req_ready (io_ptw_2_req_ready_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_req_valid (io_ptw_2_req_valid_0),
.io_ptw_req_bits_bits_addr (io_ptw_2_req_bits_bits_addr_0),
.io_ptw_req_bits_bits_need_gpa (io_ptw_2_req_bits_bits_need_gpa_0),
.io_ptw_resp_valid (io_ptw_2_resp_valid_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_ae_ptw (io_ptw_2_resp_bits_ae_ptw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_ae_final (io_ptw_2_resp_bits_ae_final_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pf (io_ptw_2_resp_bits_pf_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gf (io_ptw_2_resp_bits_gf_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_hr (io_ptw_2_resp_bits_hr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_hw (io_ptw_2_resp_bits_hw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_hx (io_ptw_2_resp_bits_hx_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_reserved_for_future (io_ptw_2_resp_bits_pte_reserved_for_future_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_ppn (io_ptw_2_resp_bits_pte_ppn_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_reserved_for_software (io_ptw_2_resp_bits_pte_reserved_for_software_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_d (io_ptw_2_resp_bits_pte_d_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_a (io_ptw_2_resp_bits_pte_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_g (io_ptw_2_resp_bits_pte_g_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_u (io_ptw_2_resp_bits_pte_u_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_x (io_ptw_2_resp_bits_pte_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_w (io_ptw_2_resp_bits_pte_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_r (io_ptw_2_resp_bits_pte_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_v (io_ptw_2_resp_bits_pte_v_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_level (io_ptw_2_resp_bits_level_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_homogeneous (io_ptw_2_resp_bits_homogeneous_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gpa_valid (io_ptw_2_resp_bits_gpa_valid_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gpa_bits (io_ptw_2_resp_bits_gpa_bits_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gpa_is_pte (io_ptw_2_resp_bits_gpa_is_pte_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_ptbr_mode (io_ptw_2_ptbr_mode_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_ptbr_ppn (io_ptw_2_ptbr_ppn_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_debug (io_ptw_2_status_debug_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_cease (io_ptw_2_status_cease_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_wfi (io_ptw_2_status_wfi_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_isa (io_ptw_2_status_isa_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_dprv (io_ptw_2_status_dprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_dv (io_ptw_2_status_dv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_prv (io_ptw_2_status_prv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_v (io_ptw_2_status_v_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mpv (io_ptw_2_status_mpv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_gva (io_ptw_2_status_gva_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_tsr (io_ptw_2_status_tsr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_tw (io_ptw_2_status_tw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_tvm (io_ptw_2_status_tvm_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mxr (io_ptw_2_status_mxr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_sum (io_ptw_2_status_sum_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mprv (io_ptw_2_status_mprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_fs (io_ptw_2_status_fs_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mpp (io_ptw_2_status_mpp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_spp (io_ptw_2_status_spp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mpie (io_ptw_2_status_mpie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_spie (io_ptw_2_status_spie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mie (io_ptw_2_status_mie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_sie (io_ptw_2_status_sie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_hstatus_spvp (io_ptw_2_hstatus_spvp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_hstatus_spv (io_ptw_2_hstatus_spv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_hstatus_gva (io_ptw_2_hstatus_gva_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_debug (io_ptw_2_gstatus_debug_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_cease (io_ptw_2_gstatus_cease_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_wfi (io_ptw_2_gstatus_wfi_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_isa (io_ptw_2_gstatus_isa_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_dprv (io_ptw_2_gstatus_dprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_dv (io_ptw_2_gstatus_dv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_prv (io_ptw_2_gstatus_prv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_v (io_ptw_2_gstatus_v_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_zero2 (io_ptw_2_gstatus_zero2_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mpv (io_ptw_2_gstatus_mpv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_gva (io_ptw_2_gstatus_gva_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mbe (io_ptw_2_gstatus_mbe_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sbe (io_ptw_2_gstatus_sbe_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sxl (io_ptw_2_gstatus_sxl_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_zero1 (io_ptw_2_gstatus_zero1_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_tsr (io_ptw_2_gstatus_tsr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_tw (io_ptw_2_gstatus_tw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_tvm (io_ptw_2_gstatus_tvm_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mxr (io_ptw_2_gstatus_mxr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sum (io_ptw_2_gstatus_sum_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mprv (io_ptw_2_gstatus_mprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_fs (io_ptw_2_gstatus_fs_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mpp (io_ptw_2_gstatus_mpp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_vs (io_ptw_2_gstatus_vs_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_spp (io_ptw_2_gstatus_spp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mpie (io_ptw_2_gstatus_mpie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_ube (io_ptw_2_gstatus_ube_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_spie (io_ptw_2_gstatus_spie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_upie (io_ptw_2_gstatus_upie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mie (io_ptw_2_gstatus_mie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_hie (io_ptw_2_gstatus_hie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sie (io_ptw_2_gstatus_sie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_uie (io_ptw_2_gstatus_uie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_l (io_ptw_2_pmp_0_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_a (io_ptw_2_pmp_0_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_x (io_ptw_2_pmp_0_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_w (io_ptw_2_pmp_0_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_r (io_ptw_2_pmp_0_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_addr (io_ptw_2_pmp_0_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_mask (io_ptw_2_pmp_0_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_l (io_ptw_2_pmp_1_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_a (io_ptw_2_pmp_1_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_x (io_ptw_2_pmp_1_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_w (io_ptw_2_pmp_1_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_r (io_ptw_2_pmp_1_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_addr (io_ptw_2_pmp_1_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_mask (io_ptw_2_pmp_1_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_l (io_ptw_2_pmp_2_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_a (io_ptw_2_pmp_2_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_x (io_ptw_2_pmp_2_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_w (io_ptw_2_pmp_2_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_r (io_ptw_2_pmp_2_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_addr (io_ptw_2_pmp_2_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_mask (io_ptw_2_pmp_2_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_l (io_ptw_2_pmp_3_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_a (io_ptw_2_pmp_3_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_x (io_ptw_2_pmp_3_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_w (io_ptw_2_pmp_3_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_r (io_ptw_2_pmp_3_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_addr (io_ptw_2_pmp_3_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_mask (io_ptw_2_pmp_3_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_l (io_ptw_2_pmp_4_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_a (io_ptw_2_pmp_4_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_x (io_ptw_2_pmp_4_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_w (io_ptw_2_pmp_4_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_r (io_ptw_2_pmp_4_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_addr (io_ptw_2_pmp_4_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_mask (io_ptw_2_pmp_4_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_l (io_ptw_2_pmp_5_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_a (io_ptw_2_pmp_5_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_x (io_ptw_2_pmp_5_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_w (io_ptw_2_pmp_5_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_r (io_ptw_2_pmp_5_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_addr (io_ptw_2_pmp_5_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_mask (io_ptw_2_pmp_5_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_l (io_ptw_2_pmp_6_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_a (io_ptw_2_pmp_6_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_x (io_ptw_2_pmp_6_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_w (io_ptw_2_pmp_6_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_r (io_ptw_2_pmp_6_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_addr (io_ptw_2_pmp_6_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_mask (io_ptw_2_pmp_6_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_l (io_ptw_2_pmp_7_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_a (io_ptw_2_pmp_7_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_x (io_ptw_2_pmp_7_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_w (io_ptw_2_pmp_7_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_r (io_ptw_2_pmp_7_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_addr (io_ptw_2_pmp_7_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_mask (io_ptw_2_pmp_7_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_ren (io_ptw_2_customCSRs_csrs_0_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_wen (io_ptw_2_customCSRs_csrs_0_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_wdata (io_ptw_2_customCSRs_csrs_0_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_value (io_ptw_2_customCSRs_csrs_0_value_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_ren (io_ptw_2_customCSRs_csrs_1_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_wen (io_ptw_2_customCSRs_csrs_1_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_wdata (io_ptw_2_customCSRs_csrs_1_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_value (io_ptw_2_customCSRs_csrs_1_value_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_ren (io_ptw_2_customCSRs_csrs_2_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_wen (io_ptw_2_customCSRs_csrs_2_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_wdata (io_ptw_2_customCSRs_csrs_2_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_value (io_ptw_2_customCSRs_csrs_2_value_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_ren (io_ptw_2_customCSRs_csrs_3_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_wen (io_ptw_2_customCSRs_csrs_3_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_wdata (io_ptw_2_customCSRs_csrs_3_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_value (io_ptw_2_customCSRs_csrs_3_value_0), // @[ZstdCompressor.scala:95:7]
.io_status_valid (_cmd_router_io_dmem_status_out_valid), // @[ZstdCompressor.scala:112:26]
.io_status_bits_debug (_cmd_router_io_dmem_status_out_bits_status_debug), // @[ZstdCompressor.scala:112:26]
.io_status_bits_cease (_cmd_router_io_dmem_status_out_bits_status_cease), // @[ZstdCompressor.scala:112:26]
.io_status_bits_wfi (_cmd_router_io_dmem_status_out_bits_status_wfi), // @[ZstdCompressor.scala:112:26]
.io_status_bits_isa (_cmd_router_io_dmem_status_out_bits_status_isa), // @[ZstdCompressor.scala:112:26]
.io_status_bits_dprv (_cmd_router_io_dmem_status_out_bits_status_dprv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_dv (_cmd_router_io_dmem_status_out_bits_status_dv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_prv (_cmd_router_io_dmem_status_out_bits_status_prv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_v (_cmd_router_io_dmem_status_out_bits_status_v), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sd (_cmd_router_io_dmem_status_out_bits_status_sd), // @[ZstdCompressor.scala:112:26]
.io_status_bits_zero2 (_cmd_router_io_dmem_status_out_bits_status_zero2), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mpv (_cmd_router_io_dmem_status_out_bits_status_mpv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_gva (_cmd_router_io_dmem_status_out_bits_status_gva), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mbe (_cmd_router_io_dmem_status_out_bits_status_mbe), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sbe (_cmd_router_io_dmem_status_out_bits_status_sbe), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sxl (_cmd_router_io_dmem_status_out_bits_status_sxl), // @[ZstdCompressor.scala:112:26]
.io_status_bits_uxl (_cmd_router_io_dmem_status_out_bits_status_uxl), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sd_rv32 (_cmd_router_io_dmem_status_out_bits_status_sd_rv32), // @[ZstdCompressor.scala:112:26]
.io_status_bits_zero1 (_cmd_router_io_dmem_status_out_bits_status_zero1), // @[ZstdCompressor.scala:112:26]
.io_status_bits_tsr (_cmd_router_io_dmem_status_out_bits_status_tsr), // @[ZstdCompressor.scala:112:26]
.io_status_bits_tw (_cmd_router_io_dmem_status_out_bits_status_tw), // @[ZstdCompressor.scala:112:26]
.io_status_bits_tvm (_cmd_router_io_dmem_status_out_bits_status_tvm), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mxr (_cmd_router_io_dmem_status_out_bits_status_mxr), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sum (_cmd_router_io_dmem_status_out_bits_status_sum), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mprv (_cmd_router_io_dmem_status_out_bits_status_mprv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_xs (_cmd_router_io_dmem_status_out_bits_status_xs), // @[ZstdCompressor.scala:112:26]
.io_status_bits_fs (_cmd_router_io_dmem_status_out_bits_status_fs), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mpp (_cmd_router_io_dmem_status_out_bits_status_mpp), // @[ZstdCompressor.scala:112:26]
.io_status_bits_vs (_cmd_router_io_dmem_status_out_bits_status_vs), // @[ZstdCompressor.scala:112:26]
.io_status_bits_spp (_cmd_router_io_dmem_status_out_bits_status_spp), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mpie (_cmd_router_io_dmem_status_out_bits_status_mpie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_ube (_cmd_router_io_dmem_status_out_bits_status_ube), // @[ZstdCompressor.scala:112:26]
.io_status_bits_spie (_cmd_router_io_dmem_status_out_bits_status_spie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_upie (_cmd_router_io_dmem_status_out_bits_status_upie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mie (_cmd_router_io_dmem_status_out_bits_status_mie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_hie (_cmd_router_io_dmem_status_out_bits_status_hie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sie (_cmd_router_io_dmem_status_out_bits_status_sie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_uie (_cmd_router_io_dmem_status_out_bits_status_uie) // @[ZstdCompressor.scala:112:26]
); // @[ZstdCompressor.scala:46:32]
TLWidthWidget32_2 widget_2 ( // @[WidthWidget.scala:230:28]
.clock (clock),
.reset (reset),
.auto_anon_in_a_ready (_widget_2_auto_anon_in_a_ready),
.auto_anon_in_a_valid (_l2_mf_reader_auto_master_out_a_valid), // @[ZstdCompressor.scala:46:32]
.auto_anon_in_a_bits_opcode (_l2_mf_reader_auto_master_out_a_bits_opcode), // @[ZstdCompressor.scala:46:32]
.auto_anon_in_a_bits_param (_l2_mf_reader_auto_master_out_a_bits_param), // @[ZstdCompressor.scala:46:32]
.auto_anon_in_a_bits_size (_l2_mf_reader_auto_master_out_a_bits_size), // @[ZstdCompressor.scala:46:32]
.auto_anon_in_a_bits_source (_l2_mf_reader_auto_master_out_a_bits_source), // @[ZstdCompressor.scala:46:32]
.auto_anon_in_a_bits_address (_l2_mf_reader_auto_master_out_a_bits_address), // @[ZstdCompressor.scala:46:32]
.auto_anon_in_a_bits_mask (_l2_mf_reader_auto_master_out_a_bits_mask), // @[ZstdCompressor.scala:46:32]
.auto_anon_in_a_bits_data (_l2_mf_reader_auto_master_out_a_bits_data), // @[ZstdCompressor.scala:46:32]
.auto_anon_in_a_bits_corrupt (_l2_mf_reader_auto_master_out_a_bits_corrupt), // @[ZstdCompressor.scala:46:32]
.auto_anon_in_d_ready (_l2_mf_reader_auto_master_out_d_ready), // @[ZstdCompressor.scala:46:32]
.auto_anon_in_d_valid (_widget_2_auto_anon_in_d_valid),
.auto_anon_in_d_bits_opcode (_widget_2_auto_anon_in_d_bits_opcode),
.auto_anon_in_d_bits_param (_widget_2_auto_anon_in_d_bits_param),
.auto_anon_in_d_bits_size (_widget_2_auto_anon_in_d_bits_size),
.auto_anon_in_d_bits_source (_widget_2_auto_anon_in_d_bits_source),
.auto_anon_in_d_bits_sink (_widget_2_auto_anon_in_d_bits_sink),
.auto_anon_in_d_bits_denied (_widget_2_auto_anon_in_d_bits_denied),
.auto_anon_in_d_bits_data (_widget_2_auto_anon_in_d_bits_data),
.auto_anon_in_d_bits_corrupt (_widget_2_auto_anon_in_d_bits_corrupt),
.auto_anon_out_a_ready (x1_tlNodeIn_1_a_ready), // @[MixedNode.scala:551:17]
.auto_anon_out_a_valid (x1_tlNodeIn_1_a_valid),
.auto_anon_out_a_bits_opcode (x1_tlNodeIn_1_a_bits_opcode),
.auto_anon_out_a_bits_param (x1_tlNodeIn_1_a_bits_param),
.auto_anon_out_a_bits_size (x1_tlNodeIn_1_a_bits_size),
.auto_anon_out_a_bits_source (x1_tlNodeIn_1_a_bits_source),
.auto_anon_out_a_bits_address (x1_tlNodeIn_1_a_bits_address),
.auto_anon_out_a_bits_mask (x1_tlNodeIn_1_a_bits_mask),
.auto_anon_out_a_bits_data (x1_tlNodeIn_1_a_bits_data),
.auto_anon_out_a_bits_corrupt (x1_tlNodeIn_1_a_bits_corrupt),
.auto_anon_out_d_ready (x1_tlNodeIn_1_d_ready),
.auto_anon_out_d_valid (x1_tlNodeIn_1_d_valid), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_opcode (x1_tlNodeIn_1_d_bits_opcode), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_param (x1_tlNodeIn_1_d_bits_param), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_size (x1_tlNodeIn_1_d_bits_size), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_source (x1_tlNodeIn_1_d_bits_source), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_sink (x1_tlNodeIn_1_d_bits_sink), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_denied (x1_tlNodeIn_1_d_bits_denied), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_data (x1_tlNodeIn_1_d_bits_data), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_corrupt (x1_tlNodeIn_1_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[WidthWidget.scala:230:28]
L2MemHelperLatencyInjection_3 l2_mf_seqwriter ( // @[ZstdCompressor.scala:49:35]
.clock (clock),
.reset (reset),
.auto_master_out_a_ready (_widget_3_auto_anon_in_a_ready), // @[WidthWidget.scala:230:28]
.auto_master_out_a_valid (_l2_mf_seqwriter_auto_master_out_a_valid),
.auto_master_out_a_bits_opcode (_l2_mf_seqwriter_auto_master_out_a_bits_opcode),
.auto_master_out_a_bits_param (_l2_mf_seqwriter_auto_master_out_a_bits_param),
.auto_master_out_a_bits_size (_l2_mf_seqwriter_auto_master_out_a_bits_size),
.auto_master_out_a_bits_source (_l2_mf_seqwriter_auto_master_out_a_bits_source),
.auto_master_out_a_bits_address (_l2_mf_seqwriter_auto_master_out_a_bits_address),
.auto_master_out_a_bits_mask (_l2_mf_seqwriter_auto_master_out_a_bits_mask),
.auto_master_out_a_bits_data (_l2_mf_seqwriter_auto_master_out_a_bits_data),
.auto_master_out_a_bits_corrupt (_l2_mf_seqwriter_auto_master_out_a_bits_corrupt),
.auto_master_out_d_ready (_l2_mf_seqwriter_auto_master_out_d_ready),
.auto_master_out_d_valid (_widget_3_auto_anon_in_d_valid), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_opcode (_widget_3_auto_anon_in_d_bits_opcode), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_param (_widget_3_auto_anon_in_d_bits_param), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_size (_widget_3_auto_anon_in_d_bits_size), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_source (_widget_3_auto_anon_in_d_bits_source), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_sink (_widget_3_auto_anon_in_d_bits_sink), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_denied (_widget_3_auto_anon_in_d_bits_denied), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_data (_widget_3_auto_anon_in_d_bits_data), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_corrupt (_widget_3_auto_anon_in_d_bits_corrupt), // @[WidthWidget.scala:230:28]
.io_userif_req_ready (_l2_mf_seqwriter_io_userif_req_ready),
.io_userif_req_valid (_matchfinder_io_l2io_seq_memwriter_userif_req_valid), // @[ZstdCompressor.scala:129:27]
.io_userif_req_bits_addr (_matchfinder_io_l2io_seq_memwriter_userif_req_bits_addr), // @[ZstdCompressor.scala:129:27]
.io_userif_req_bits_size (_matchfinder_io_l2io_seq_memwriter_userif_req_bits_size), // @[ZstdCompressor.scala:129:27]
.io_userif_req_bits_data (_matchfinder_io_l2io_seq_memwriter_userif_req_bits_data), // @[ZstdCompressor.scala:129:27]
.io_userif_resp_valid (_l2_mf_seqwriter_io_userif_resp_valid),
.io_userif_resp_bits_data (_l2_mf_seqwriter_io_userif_resp_bits_data),
.io_userif_no_memops_inflight (_l2_mf_seqwriter_io_userif_no_memops_inflight),
.io_latency_inject_cycles (_l2_mf_seqwriter_io_latency_inject_cycles_T), // @[ZstdCompressor.scala:185:63]
.io_sfence (_cmd_router_io_sfence_out), // @[ZstdCompressor.scala:112:26]
.io_ptw_req_ready (io_ptw_3_req_ready_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_req_valid (io_ptw_3_req_valid_0),
.io_ptw_req_bits_bits_addr (io_ptw_3_req_bits_bits_addr_0),
.io_ptw_req_bits_bits_need_gpa (io_ptw_3_req_bits_bits_need_gpa_0),
.io_ptw_resp_valid (io_ptw_3_resp_valid_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_ae_ptw (io_ptw_3_resp_bits_ae_ptw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_ae_final (io_ptw_3_resp_bits_ae_final_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pf (io_ptw_3_resp_bits_pf_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gf (io_ptw_3_resp_bits_gf_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_hr (io_ptw_3_resp_bits_hr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_hw (io_ptw_3_resp_bits_hw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_hx (io_ptw_3_resp_bits_hx_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_reserved_for_future (io_ptw_3_resp_bits_pte_reserved_for_future_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_ppn (io_ptw_3_resp_bits_pte_ppn_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_reserved_for_software (io_ptw_3_resp_bits_pte_reserved_for_software_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_d (io_ptw_3_resp_bits_pte_d_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_a (io_ptw_3_resp_bits_pte_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_g (io_ptw_3_resp_bits_pte_g_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_u (io_ptw_3_resp_bits_pte_u_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_x (io_ptw_3_resp_bits_pte_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_w (io_ptw_3_resp_bits_pte_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_r (io_ptw_3_resp_bits_pte_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_v (io_ptw_3_resp_bits_pte_v_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_level (io_ptw_3_resp_bits_level_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_homogeneous (io_ptw_3_resp_bits_homogeneous_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gpa_valid (io_ptw_3_resp_bits_gpa_valid_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gpa_bits (io_ptw_3_resp_bits_gpa_bits_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gpa_is_pte (io_ptw_3_resp_bits_gpa_is_pte_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_ptbr_mode (io_ptw_3_ptbr_mode_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_ptbr_ppn (io_ptw_3_ptbr_ppn_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_debug (io_ptw_3_status_debug_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_cease (io_ptw_3_status_cease_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_wfi (io_ptw_3_status_wfi_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_isa (io_ptw_3_status_isa_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_dprv (io_ptw_3_status_dprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_dv (io_ptw_3_status_dv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_prv (io_ptw_3_status_prv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_v (io_ptw_3_status_v_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mpv (io_ptw_3_status_mpv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_gva (io_ptw_3_status_gva_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_tsr (io_ptw_3_status_tsr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_tw (io_ptw_3_status_tw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_tvm (io_ptw_3_status_tvm_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mxr (io_ptw_3_status_mxr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_sum (io_ptw_3_status_sum_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mprv (io_ptw_3_status_mprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_fs (io_ptw_3_status_fs_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mpp (io_ptw_3_status_mpp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_spp (io_ptw_3_status_spp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mpie (io_ptw_3_status_mpie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_spie (io_ptw_3_status_spie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mie (io_ptw_3_status_mie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_sie (io_ptw_3_status_sie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_hstatus_spvp (io_ptw_3_hstatus_spvp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_hstatus_spv (io_ptw_3_hstatus_spv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_hstatus_gva (io_ptw_3_hstatus_gva_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_debug (io_ptw_3_gstatus_debug_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_cease (io_ptw_3_gstatus_cease_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_wfi (io_ptw_3_gstatus_wfi_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_isa (io_ptw_3_gstatus_isa_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_dprv (io_ptw_3_gstatus_dprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_dv (io_ptw_3_gstatus_dv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_prv (io_ptw_3_gstatus_prv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_v (io_ptw_3_gstatus_v_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_zero2 (io_ptw_3_gstatus_zero2_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mpv (io_ptw_3_gstatus_mpv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_gva (io_ptw_3_gstatus_gva_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mbe (io_ptw_3_gstatus_mbe_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sbe (io_ptw_3_gstatus_sbe_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sxl (io_ptw_3_gstatus_sxl_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_zero1 (io_ptw_3_gstatus_zero1_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_tsr (io_ptw_3_gstatus_tsr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_tw (io_ptw_3_gstatus_tw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_tvm (io_ptw_3_gstatus_tvm_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mxr (io_ptw_3_gstatus_mxr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sum (io_ptw_3_gstatus_sum_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mprv (io_ptw_3_gstatus_mprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_fs (io_ptw_3_gstatus_fs_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mpp (io_ptw_3_gstatus_mpp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_vs (io_ptw_3_gstatus_vs_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_spp (io_ptw_3_gstatus_spp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mpie (io_ptw_3_gstatus_mpie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_ube (io_ptw_3_gstatus_ube_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_spie (io_ptw_3_gstatus_spie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_upie (io_ptw_3_gstatus_upie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mie (io_ptw_3_gstatus_mie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_hie (io_ptw_3_gstatus_hie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sie (io_ptw_3_gstatus_sie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_uie (io_ptw_3_gstatus_uie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_l (io_ptw_3_pmp_0_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_a (io_ptw_3_pmp_0_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_x (io_ptw_3_pmp_0_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_w (io_ptw_3_pmp_0_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_r (io_ptw_3_pmp_0_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_addr (io_ptw_3_pmp_0_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_mask (io_ptw_3_pmp_0_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_l (io_ptw_3_pmp_1_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_a (io_ptw_3_pmp_1_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_x (io_ptw_3_pmp_1_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_w (io_ptw_3_pmp_1_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_r (io_ptw_3_pmp_1_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_addr (io_ptw_3_pmp_1_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_mask (io_ptw_3_pmp_1_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_l (io_ptw_3_pmp_2_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_a (io_ptw_3_pmp_2_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_x (io_ptw_3_pmp_2_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_w (io_ptw_3_pmp_2_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_r (io_ptw_3_pmp_2_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_addr (io_ptw_3_pmp_2_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_mask (io_ptw_3_pmp_2_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_l (io_ptw_3_pmp_3_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_a (io_ptw_3_pmp_3_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_x (io_ptw_3_pmp_3_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_w (io_ptw_3_pmp_3_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_r (io_ptw_3_pmp_3_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_addr (io_ptw_3_pmp_3_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_mask (io_ptw_3_pmp_3_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_l (io_ptw_3_pmp_4_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_a (io_ptw_3_pmp_4_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_x (io_ptw_3_pmp_4_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_w (io_ptw_3_pmp_4_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_r (io_ptw_3_pmp_4_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_addr (io_ptw_3_pmp_4_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_mask (io_ptw_3_pmp_4_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_l (io_ptw_3_pmp_5_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_a (io_ptw_3_pmp_5_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_x (io_ptw_3_pmp_5_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_w (io_ptw_3_pmp_5_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_r (io_ptw_3_pmp_5_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_addr (io_ptw_3_pmp_5_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_mask (io_ptw_3_pmp_5_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_l (io_ptw_3_pmp_6_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_a (io_ptw_3_pmp_6_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_x (io_ptw_3_pmp_6_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_w (io_ptw_3_pmp_6_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_r (io_ptw_3_pmp_6_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_addr (io_ptw_3_pmp_6_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_mask (io_ptw_3_pmp_6_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_l (io_ptw_3_pmp_7_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_a (io_ptw_3_pmp_7_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_x (io_ptw_3_pmp_7_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_w (io_ptw_3_pmp_7_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_r (io_ptw_3_pmp_7_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_addr (io_ptw_3_pmp_7_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_mask (io_ptw_3_pmp_7_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_ren (io_ptw_3_customCSRs_csrs_0_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_wen (io_ptw_3_customCSRs_csrs_0_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_wdata (io_ptw_3_customCSRs_csrs_0_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_value (io_ptw_3_customCSRs_csrs_0_value_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_ren (io_ptw_3_customCSRs_csrs_1_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_wen (io_ptw_3_customCSRs_csrs_1_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_wdata (io_ptw_3_customCSRs_csrs_1_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_value (io_ptw_3_customCSRs_csrs_1_value_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_ren (io_ptw_3_customCSRs_csrs_2_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_wen (io_ptw_3_customCSRs_csrs_2_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_wdata (io_ptw_3_customCSRs_csrs_2_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_value (io_ptw_3_customCSRs_csrs_2_value_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_ren (io_ptw_3_customCSRs_csrs_3_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_wen (io_ptw_3_customCSRs_csrs_3_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_wdata (io_ptw_3_customCSRs_csrs_3_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_value (io_ptw_3_customCSRs_csrs_3_value_0), // @[ZstdCompressor.scala:95:7]
.io_status_valid (_cmd_router_io_dmem_status_out_valid), // @[ZstdCompressor.scala:112:26]
.io_status_bits_debug (_cmd_router_io_dmem_status_out_bits_status_debug), // @[ZstdCompressor.scala:112:26]
.io_status_bits_cease (_cmd_router_io_dmem_status_out_bits_status_cease), // @[ZstdCompressor.scala:112:26]
.io_status_bits_wfi (_cmd_router_io_dmem_status_out_bits_status_wfi), // @[ZstdCompressor.scala:112:26]
.io_status_bits_isa (_cmd_router_io_dmem_status_out_bits_status_isa), // @[ZstdCompressor.scala:112:26]
.io_status_bits_dprv (_cmd_router_io_dmem_status_out_bits_status_dprv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_dv (_cmd_router_io_dmem_status_out_bits_status_dv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_prv (_cmd_router_io_dmem_status_out_bits_status_prv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_v (_cmd_router_io_dmem_status_out_bits_status_v), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sd (_cmd_router_io_dmem_status_out_bits_status_sd), // @[ZstdCompressor.scala:112:26]
.io_status_bits_zero2 (_cmd_router_io_dmem_status_out_bits_status_zero2), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mpv (_cmd_router_io_dmem_status_out_bits_status_mpv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_gva (_cmd_router_io_dmem_status_out_bits_status_gva), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mbe (_cmd_router_io_dmem_status_out_bits_status_mbe), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sbe (_cmd_router_io_dmem_status_out_bits_status_sbe), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sxl (_cmd_router_io_dmem_status_out_bits_status_sxl), // @[ZstdCompressor.scala:112:26]
.io_status_bits_uxl (_cmd_router_io_dmem_status_out_bits_status_uxl), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sd_rv32 (_cmd_router_io_dmem_status_out_bits_status_sd_rv32), // @[ZstdCompressor.scala:112:26]
.io_status_bits_zero1 (_cmd_router_io_dmem_status_out_bits_status_zero1), // @[ZstdCompressor.scala:112:26]
.io_status_bits_tsr (_cmd_router_io_dmem_status_out_bits_status_tsr), // @[ZstdCompressor.scala:112:26]
.io_status_bits_tw (_cmd_router_io_dmem_status_out_bits_status_tw), // @[ZstdCompressor.scala:112:26]
.io_status_bits_tvm (_cmd_router_io_dmem_status_out_bits_status_tvm), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mxr (_cmd_router_io_dmem_status_out_bits_status_mxr), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sum (_cmd_router_io_dmem_status_out_bits_status_sum), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mprv (_cmd_router_io_dmem_status_out_bits_status_mprv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_xs (_cmd_router_io_dmem_status_out_bits_status_xs), // @[ZstdCompressor.scala:112:26]
.io_status_bits_fs (_cmd_router_io_dmem_status_out_bits_status_fs), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mpp (_cmd_router_io_dmem_status_out_bits_status_mpp), // @[ZstdCompressor.scala:112:26]
.io_status_bits_vs (_cmd_router_io_dmem_status_out_bits_status_vs), // @[ZstdCompressor.scala:112:26]
.io_status_bits_spp (_cmd_router_io_dmem_status_out_bits_status_spp), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mpie (_cmd_router_io_dmem_status_out_bits_status_mpie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_ube (_cmd_router_io_dmem_status_out_bits_status_ube), // @[ZstdCompressor.scala:112:26]
.io_status_bits_spie (_cmd_router_io_dmem_status_out_bits_status_spie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_upie (_cmd_router_io_dmem_status_out_bits_status_upie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mie (_cmd_router_io_dmem_status_out_bits_status_mie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_hie (_cmd_router_io_dmem_status_out_bits_status_hie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sie (_cmd_router_io_dmem_status_out_bits_status_sie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_uie (_cmd_router_io_dmem_status_out_bits_status_uie) // @[ZstdCompressor.scala:112:26]
); // @[ZstdCompressor.scala:49:35]
TLWidthWidget32_3 widget_3 ( // @[WidthWidget.scala:230:28]
.clock (clock),
.reset (reset),
.auto_anon_in_a_ready (_widget_3_auto_anon_in_a_ready),
.auto_anon_in_a_valid (_l2_mf_seqwriter_auto_master_out_a_valid), // @[ZstdCompressor.scala:49:35]
.auto_anon_in_a_bits_opcode (_l2_mf_seqwriter_auto_master_out_a_bits_opcode), // @[ZstdCompressor.scala:49:35]
.auto_anon_in_a_bits_param (_l2_mf_seqwriter_auto_master_out_a_bits_param), // @[ZstdCompressor.scala:49:35]
.auto_anon_in_a_bits_size (_l2_mf_seqwriter_auto_master_out_a_bits_size), // @[ZstdCompressor.scala:49:35]
.auto_anon_in_a_bits_source (_l2_mf_seqwriter_auto_master_out_a_bits_source), // @[ZstdCompressor.scala:49:35]
.auto_anon_in_a_bits_address (_l2_mf_seqwriter_auto_master_out_a_bits_address), // @[ZstdCompressor.scala:49:35]
.auto_anon_in_a_bits_mask (_l2_mf_seqwriter_auto_master_out_a_bits_mask), // @[ZstdCompressor.scala:49:35]
.auto_anon_in_a_bits_data (_l2_mf_seqwriter_auto_master_out_a_bits_data), // @[ZstdCompressor.scala:49:35]
.auto_anon_in_a_bits_corrupt (_l2_mf_seqwriter_auto_master_out_a_bits_corrupt), // @[ZstdCompressor.scala:49:35]
.auto_anon_in_d_ready (_l2_mf_seqwriter_auto_master_out_d_ready), // @[ZstdCompressor.scala:49:35]
.auto_anon_in_d_valid (_widget_3_auto_anon_in_d_valid),
.auto_anon_in_d_bits_opcode (_widget_3_auto_anon_in_d_bits_opcode),
.auto_anon_in_d_bits_param (_widget_3_auto_anon_in_d_bits_param),
.auto_anon_in_d_bits_size (_widget_3_auto_anon_in_d_bits_size),
.auto_anon_in_d_bits_source (_widget_3_auto_anon_in_d_bits_source),
.auto_anon_in_d_bits_sink (_widget_3_auto_anon_in_d_bits_sink),
.auto_anon_in_d_bits_denied (_widget_3_auto_anon_in_d_bits_denied),
.auto_anon_in_d_bits_data (_widget_3_auto_anon_in_d_bits_data),
.auto_anon_in_d_bits_corrupt (_widget_3_auto_anon_in_d_bits_corrupt),
.auto_anon_out_a_ready (x1_tlNodeIn_2_a_ready), // @[MixedNode.scala:551:17]
.auto_anon_out_a_valid (x1_tlNodeIn_2_a_valid),
.auto_anon_out_a_bits_opcode (x1_tlNodeIn_2_a_bits_opcode),
.auto_anon_out_a_bits_param (x1_tlNodeIn_2_a_bits_param),
.auto_anon_out_a_bits_size (x1_tlNodeIn_2_a_bits_size),
.auto_anon_out_a_bits_source (x1_tlNodeIn_2_a_bits_source),
.auto_anon_out_a_bits_address (x1_tlNodeIn_2_a_bits_address),
.auto_anon_out_a_bits_mask (x1_tlNodeIn_2_a_bits_mask),
.auto_anon_out_a_bits_data (x1_tlNodeIn_2_a_bits_data),
.auto_anon_out_a_bits_corrupt (x1_tlNodeIn_2_a_bits_corrupt),
.auto_anon_out_d_ready (x1_tlNodeIn_2_d_ready),
.auto_anon_out_d_valid (x1_tlNodeIn_2_d_valid), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_opcode (x1_tlNodeIn_2_d_bits_opcode), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_param (x1_tlNodeIn_2_d_bits_param), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_size (x1_tlNodeIn_2_d_bits_size), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_source (x1_tlNodeIn_2_d_bits_source), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_sink (x1_tlNodeIn_2_d_bits_sink), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_denied (x1_tlNodeIn_2_d_bits_denied), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_data (x1_tlNodeIn_2_d_bits_data), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_corrupt (x1_tlNodeIn_2_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[WidthWidget.scala:230:28]
L2MemHelperLatencyInjection_4 l2_mf_litwriter ( // @[ZstdCompressor.scala:52:35]
.clock (clock),
.reset (reset),
.auto_master_out_a_ready (_widget_4_auto_anon_in_a_ready), // @[WidthWidget.scala:230:28]
.auto_master_out_a_valid (_l2_mf_litwriter_auto_master_out_a_valid),
.auto_master_out_a_bits_opcode (_l2_mf_litwriter_auto_master_out_a_bits_opcode),
.auto_master_out_a_bits_param (_l2_mf_litwriter_auto_master_out_a_bits_param),
.auto_master_out_a_bits_size (_l2_mf_litwriter_auto_master_out_a_bits_size),
.auto_master_out_a_bits_source (_l2_mf_litwriter_auto_master_out_a_bits_source),
.auto_master_out_a_bits_address (_l2_mf_litwriter_auto_master_out_a_bits_address),
.auto_master_out_a_bits_mask (_l2_mf_litwriter_auto_master_out_a_bits_mask),
.auto_master_out_a_bits_data (_l2_mf_litwriter_auto_master_out_a_bits_data),
.auto_master_out_a_bits_corrupt (_l2_mf_litwriter_auto_master_out_a_bits_corrupt),
.auto_master_out_d_ready (_l2_mf_litwriter_auto_master_out_d_ready),
.auto_master_out_d_valid (_widget_4_auto_anon_in_d_valid), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_opcode (_widget_4_auto_anon_in_d_bits_opcode), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_param (_widget_4_auto_anon_in_d_bits_param), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_size (_widget_4_auto_anon_in_d_bits_size), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_source (_widget_4_auto_anon_in_d_bits_source), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_sink (_widget_4_auto_anon_in_d_bits_sink), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_denied (_widget_4_auto_anon_in_d_bits_denied), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_data (_widget_4_auto_anon_in_d_bits_data), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_corrupt (_widget_4_auto_anon_in_d_bits_corrupt), // @[WidthWidget.scala:230:28]
.io_userif_req_ready (_l2_mf_litwriter_io_userif_req_ready),
.io_userif_req_valid (_matchfinder_io_l2io_lit_memwriter_userif_req_valid), // @[ZstdCompressor.scala:129:27]
.io_userif_req_bits_addr (_matchfinder_io_l2io_lit_memwriter_userif_req_bits_addr), // @[ZstdCompressor.scala:129:27]
.io_userif_req_bits_size (_matchfinder_io_l2io_lit_memwriter_userif_req_bits_size), // @[ZstdCompressor.scala:129:27]
.io_userif_req_bits_data (_matchfinder_io_l2io_lit_memwriter_userif_req_bits_data), // @[ZstdCompressor.scala:129:27]
.io_userif_resp_valid (_l2_mf_litwriter_io_userif_resp_valid),
.io_userif_resp_bits_data (_l2_mf_litwriter_io_userif_resp_bits_data),
.io_userif_no_memops_inflight (_l2_mf_litwriter_io_userif_no_memops_inflight),
.io_latency_inject_cycles (_l2_mf_litwriter_io_latency_inject_cycles_T), // @[ZstdCompressor.scala:186:63]
.io_sfence (_cmd_router_io_sfence_out), // @[ZstdCompressor.scala:112:26]
.io_ptw_req_ready (io_ptw_4_req_ready_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_req_valid (io_ptw_4_req_valid_0),
.io_ptw_req_bits_bits_addr (io_ptw_4_req_bits_bits_addr_0),
.io_ptw_req_bits_bits_need_gpa (io_ptw_4_req_bits_bits_need_gpa_0),
.io_ptw_resp_valid (io_ptw_4_resp_valid_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_ae_ptw (io_ptw_4_resp_bits_ae_ptw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_ae_final (io_ptw_4_resp_bits_ae_final_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pf (io_ptw_4_resp_bits_pf_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gf (io_ptw_4_resp_bits_gf_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_hr (io_ptw_4_resp_bits_hr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_hw (io_ptw_4_resp_bits_hw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_hx (io_ptw_4_resp_bits_hx_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_reserved_for_future (io_ptw_4_resp_bits_pte_reserved_for_future_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_ppn (io_ptw_4_resp_bits_pte_ppn_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_reserved_for_software (io_ptw_4_resp_bits_pte_reserved_for_software_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_d (io_ptw_4_resp_bits_pte_d_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_a (io_ptw_4_resp_bits_pte_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_g (io_ptw_4_resp_bits_pte_g_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_u (io_ptw_4_resp_bits_pte_u_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_x (io_ptw_4_resp_bits_pte_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_w (io_ptw_4_resp_bits_pte_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_r (io_ptw_4_resp_bits_pte_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_v (io_ptw_4_resp_bits_pte_v_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_level (io_ptw_4_resp_bits_level_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_homogeneous (io_ptw_4_resp_bits_homogeneous_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gpa_valid (io_ptw_4_resp_bits_gpa_valid_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gpa_bits (io_ptw_4_resp_bits_gpa_bits_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gpa_is_pte (io_ptw_4_resp_bits_gpa_is_pte_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_ptbr_mode (io_ptw_4_ptbr_mode_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_ptbr_ppn (io_ptw_4_ptbr_ppn_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_debug (io_ptw_4_status_debug_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_cease (io_ptw_4_status_cease_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_wfi (io_ptw_4_status_wfi_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_isa (io_ptw_4_status_isa_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_dprv (io_ptw_4_status_dprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_dv (io_ptw_4_status_dv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_prv (io_ptw_4_status_prv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_v (io_ptw_4_status_v_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mpv (io_ptw_4_status_mpv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_gva (io_ptw_4_status_gva_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_tsr (io_ptw_4_status_tsr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_tw (io_ptw_4_status_tw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_tvm (io_ptw_4_status_tvm_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mxr (io_ptw_4_status_mxr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_sum (io_ptw_4_status_sum_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mprv (io_ptw_4_status_mprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_fs (io_ptw_4_status_fs_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mpp (io_ptw_4_status_mpp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_spp (io_ptw_4_status_spp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mpie (io_ptw_4_status_mpie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_spie (io_ptw_4_status_spie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mie (io_ptw_4_status_mie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_sie (io_ptw_4_status_sie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_hstatus_spvp (io_ptw_4_hstatus_spvp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_hstatus_spv (io_ptw_4_hstatus_spv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_hstatus_gva (io_ptw_4_hstatus_gva_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_debug (io_ptw_4_gstatus_debug_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_cease (io_ptw_4_gstatus_cease_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_wfi (io_ptw_4_gstatus_wfi_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_isa (io_ptw_4_gstatus_isa_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_dprv (io_ptw_4_gstatus_dprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_dv (io_ptw_4_gstatus_dv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_prv (io_ptw_4_gstatus_prv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_v (io_ptw_4_gstatus_v_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_zero2 (io_ptw_4_gstatus_zero2_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mpv (io_ptw_4_gstatus_mpv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_gva (io_ptw_4_gstatus_gva_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mbe (io_ptw_4_gstatus_mbe_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sbe (io_ptw_4_gstatus_sbe_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sxl (io_ptw_4_gstatus_sxl_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_zero1 (io_ptw_4_gstatus_zero1_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_tsr (io_ptw_4_gstatus_tsr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_tw (io_ptw_4_gstatus_tw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_tvm (io_ptw_4_gstatus_tvm_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mxr (io_ptw_4_gstatus_mxr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sum (io_ptw_4_gstatus_sum_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mprv (io_ptw_4_gstatus_mprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_fs (io_ptw_4_gstatus_fs_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mpp (io_ptw_4_gstatus_mpp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_vs (io_ptw_4_gstatus_vs_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_spp (io_ptw_4_gstatus_spp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mpie (io_ptw_4_gstatus_mpie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_ube (io_ptw_4_gstatus_ube_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_spie (io_ptw_4_gstatus_spie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_upie (io_ptw_4_gstatus_upie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mie (io_ptw_4_gstatus_mie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_hie (io_ptw_4_gstatus_hie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sie (io_ptw_4_gstatus_sie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_uie (io_ptw_4_gstatus_uie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_l (io_ptw_4_pmp_0_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_a (io_ptw_4_pmp_0_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_x (io_ptw_4_pmp_0_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_w (io_ptw_4_pmp_0_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_r (io_ptw_4_pmp_0_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_addr (io_ptw_4_pmp_0_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_mask (io_ptw_4_pmp_0_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_l (io_ptw_4_pmp_1_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_a (io_ptw_4_pmp_1_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_x (io_ptw_4_pmp_1_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_w (io_ptw_4_pmp_1_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_r (io_ptw_4_pmp_1_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_addr (io_ptw_4_pmp_1_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_mask (io_ptw_4_pmp_1_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_l (io_ptw_4_pmp_2_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_a (io_ptw_4_pmp_2_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_x (io_ptw_4_pmp_2_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_w (io_ptw_4_pmp_2_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_r (io_ptw_4_pmp_2_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_addr (io_ptw_4_pmp_2_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_mask (io_ptw_4_pmp_2_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_l (io_ptw_4_pmp_3_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_a (io_ptw_4_pmp_3_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_x (io_ptw_4_pmp_3_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_w (io_ptw_4_pmp_3_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_r (io_ptw_4_pmp_3_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_addr (io_ptw_4_pmp_3_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_mask (io_ptw_4_pmp_3_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_l (io_ptw_4_pmp_4_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_a (io_ptw_4_pmp_4_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_x (io_ptw_4_pmp_4_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_w (io_ptw_4_pmp_4_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_r (io_ptw_4_pmp_4_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_addr (io_ptw_4_pmp_4_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_mask (io_ptw_4_pmp_4_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_l (io_ptw_4_pmp_5_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_a (io_ptw_4_pmp_5_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_x (io_ptw_4_pmp_5_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_w (io_ptw_4_pmp_5_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_r (io_ptw_4_pmp_5_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_addr (io_ptw_4_pmp_5_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_mask (io_ptw_4_pmp_5_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_l (io_ptw_4_pmp_6_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_a (io_ptw_4_pmp_6_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_x (io_ptw_4_pmp_6_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_w (io_ptw_4_pmp_6_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_r (io_ptw_4_pmp_6_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_addr (io_ptw_4_pmp_6_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_mask (io_ptw_4_pmp_6_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_l (io_ptw_4_pmp_7_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_a (io_ptw_4_pmp_7_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_x (io_ptw_4_pmp_7_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_w (io_ptw_4_pmp_7_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_r (io_ptw_4_pmp_7_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_addr (io_ptw_4_pmp_7_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_mask (io_ptw_4_pmp_7_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_ren (io_ptw_4_customCSRs_csrs_0_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_wen (io_ptw_4_customCSRs_csrs_0_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_wdata (io_ptw_4_customCSRs_csrs_0_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_value (io_ptw_4_customCSRs_csrs_0_value_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_ren (io_ptw_4_customCSRs_csrs_1_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_wen (io_ptw_4_customCSRs_csrs_1_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_wdata (io_ptw_4_customCSRs_csrs_1_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_value (io_ptw_4_customCSRs_csrs_1_value_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_ren (io_ptw_4_customCSRs_csrs_2_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_wen (io_ptw_4_customCSRs_csrs_2_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_wdata (io_ptw_4_customCSRs_csrs_2_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_value (io_ptw_4_customCSRs_csrs_2_value_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_ren (io_ptw_4_customCSRs_csrs_3_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_wen (io_ptw_4_customCSRs_csrs_3_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_wdata (io_ptw_4_customCSRs_csrs_3_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_value (io_ptw_4_customCSRs_csrs_3_value_0), // @[ZstdCompressor.scala:95:7]
.io_status_valid (_cmd_router_io_dmem_status_out_valid), // @[ZstdCompressor.scala:112:26]
.io_status_bits_debug (_cmd_router_io_dmem_status_out_bits_status_debug), // @[ZstdCompressor.scala:112:26]
.io_status_bits_cease (_cmd_router_io_dmem_status_out_bits_status_cease), // @[ZstdCompressor.scala:112:26]
.io_status_bits_wfi (_cmd_router_io_dmem_status_out_bits_status_wfi), // @[ZstdCompressor.scala:112:26]
.io_status_bits_isa (_cmd_router_io_dmem_status_out_bits_status_isa), // @[ZstdCompressor.scala:112:26]
.io_status_bits_dprv (_cmd_router_io_dmem_status_out_bits_status_dprv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_dv (_cmd_router_io_dmem_status_out_bits_status_dv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_prv (_cmd_router_io_dmem_status_out_bits_status_prv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_v (_cmd_router_io_dmem_status_out_bits_status_v), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sd (_cmd_router_io_dmem_status_out_bits_status_sd), // @[ZstdCompressor.scala:112:26]
.io_status_bits_zero2 (_cmd_router_io_dmem_status_out_bits_status_zero2), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mpv (_cmd_router_io_dmem_status_out_bits_status_mpv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_gva (_cmd_router_io_dmem_status_out_bits_status_gva), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mbe (_cmd_router_io_dmem_status_out_bits_status_mbe), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sbe (_cmd_router_io_dmem_status_out_bits_status_sbe), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sxl (_cmd_router_io_dmem_status_out_bits_status_sxl), // @[ZstdCompressor.scala:112:26]
.io_status_bits_uxl (_cmd_router_io_dmem_status_out_bits_status_uxl), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sd_rv32 (_cmd_router_io_dmem_status_out_bits_status_sd_rv32), // @[ZstdCompressor.scala:112:26]
.io_status_bits_zero1 (_cmd_router_io_dmem_status_out_bits_status_zero1), // @[ZstdCompressor.scala:112:26]
.io_status_bits_tsr (_cmd_router_io_dmem_status_out_bits_status_tsr), // @[ZstdCompressor.scala:112:26]
.io_status_bits_tw (_cmd_router_io_dmem_status_out_bits_status_tw), // @[ZstdCompressor.scala:112:26]
.io_status_bits_tvm (_cmd_router_io_dmem_status_out_bits_status_tvm), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mxr (_cmd_router_io_dmem_status_out_bits_status_mxr), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sum (_cmd_router_io_dmem_status_out_bits_status_sum), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mprv (_cmd_router_io_dmem_status_out_bits_status_mprv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_xs (_cmd_router_io_dmem_status_out_bits_status_xs), // @[ZstdCompressor.scala:112:26]
.io_status_bits_fs (_cmd_router_io_dmem_status_out_bits_status_fs), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mpp (_cmd_router_io_dmem_status_out_bits_status_mpp), // @[ZstdCompressor.scala:112:26]
.io_status_bits_vs (_cmd_router_io_dmem_status_out_bits_status_vs), // @[ZstdCompressor.scala:112:26]
.io_status_bits_spp (_cmd_router_io_dmem_status_out_bits_status_spp), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mpie (_cmd_router_io_dmem_status_out_bits_status_mpie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_ube (_cmd_router_io_dmem_status_out_bits_status_ube), // @[ZstdCompressor.scala:112:26]
.io_status_bits_spie (_cmd_router_io_dmem_status_out_bits_status_spie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_upie (_cmd_router_io_dmem_status_out_bits_status_upie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mie (_cmd_router_io_dmem_status_out_bits_status_mie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_hie (_cmd_router_io_dmem_status_out_bits_status_hie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sie (_cmd_router_io_dmem_status_out_bits_status_sie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_uie (_cmd_router_io_dmem_status_out_bits_status_uie) // @[ZstdCompressor.scala:112:26]
); // @[ZstdCompressor.scala:52:35]
TLWidthWidget32_4 widget_4 ( // @[WidthWidget.scala:230:28]
.clock (clock),
.reset (reset),
.auto_anon_in_a_ready (_widget_4_auto_anon_in_a_ready),
.auto_anon_in_a_valid (_l2_mf_litwriter_auto_master_out_a_valid), // @[ZstdCompressor.scala:52:35]
.auto_anon_in_a_bits_opcode (_l2_mf_litwriter_auto_master_out_a_bits_opcode), // @[ZstdCompressor.scala:52:35]
.auto_anon_in_a_bits_param (_l2_mf_litwriter_auto_master_out_a_bits_param), // @[ZstdCompressor.scala:52:35]
.auto_anon_in_a_bits_size (_l2_mf_litwriter_auto_master_out_a_bits_size), // @[ZstdCompressor.scala:52:35]
.auto_anon_in_a_bits_source (_l2_mf_litwriter_auto_master_out_a_bits_source), // @[ZstdCompressor.scala:52:35]
.auto_anon_in_a_bits_address (_l2_mf_litwriter_auto_master_out_a_bits_address), // @[ZstdCompressor.scala:52:35]
.auto_anon_in_a_bits_mask (_l2_mf_litwriter_auto_master_out_a_bits_mask), // @[ZstdCompressor.scala:52:35]
.auto_anon_in_a_bits_data (_l2_mf_litwriter_auto_master_out_a_bits_data), // @[ZstdCompressor.scala:52:35]
.auto_anon_in_a_bits_corrupt (_l2_mf_litwriter_auto_master_out_a_bits_corrupt), // @[ZstdCompressor.scala:52:35]
.auto_anon_in_d_ready (_l2_mf_litwriter_auto_master_out_d_ready), // @[ZstdCompressor.scala:52:35]
.auto_anon_in_d_valid (_widget_4_auto_anon_in_d_valid),
.auto_anon_in_d_bits_opcode (_widget_4_auto_anon_in_d_bits_opcode),
.auto_anon_in_d_bits_param (_widget_4_auto_anon_in_d_bits_param),
.auto_anon_in_d_bits_size (_widget_4_auto_anon_in_d_bits_size),
.auto_anon_in_d_bits_source (_widget_4_auto_anon_in_d_bits_source),
.auto_anon_in_d_bits_sink (_widget_4_auto_anon_in_d_bits_sink),
.auto_anon_in_d_bits_denied (_widget_4_auto_anon_in_d_bits_denied),
.auto_anon_in_d_bits_data (_widget_4_auto_anon_in_d_bits_data),
.auto_anon_in_d_bits_corrupt (_widget_4_auto_anon_in_d_bits_corrupt),
.auto_anon_out_a_ready (x1_tlNodeIn_3_a_ready), // @[MixedNode.scala:551:17]
.auto_anon_out_a_valid (x1_tlNodeIn_3_a_valid),
.auto_anon_out_a_bits_opcode (x1_tlNodeIn_3_a_bits_opcode),
.auto_anon_out_a_bits_param (x1_tlNodeIn_3_a_bits_param),
.auto_anon_out_a_bits_size (x1_tlNodeIn_3_a_bits_size),
.auto_anon_out_a_bits_source (x1_tlNodeIn_3_a_bits_source),
.auto_anon_out_a_bits_address (x1_tlNodeIn_3_a_bits_address),
.auto_anon_out_a_bits_mask (x1_tlNodeIn_3_a_bits_mask),
.auto_anon_out_a_bits_data (x1_tlNodeIn_3_a_bits_data),
.auto_anon_out_a_bits_corrupt (x1_tlNodeIn_3_a_bits_corrupt),
.auto_anon_out_d_ready (x1_tlNodeIn_3_d_ready),
.auto_anon_out_d_valid (x1_tlNodeIn_3_d_valid), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_opcode (x1_tlNodeIn_3_d_bits_opcode), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_param (x1_tlNodeIn_3_d_bits_param), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_size (x1_tlNodeIn_3_d_bits_size), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_source (x1_tlNodeIn_3_d_bits_source), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_sink (x1_tlNodeIn_3_d_bits_sink), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_denied (x1_tlNodeIn_3_d_bits_denied), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_data (x1_tlNodeIn_3_d_bits_data), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_corrupt (x1_tlNodeIn_3_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[WidthWidget.scala:230:28]
L2MemHelperLatencyInjection_5 l2_huf_lit_reader ( // @[ZstdCompressor.scala:55:37]
.clock (clock),
.reset (reset),
.auto_master_out_a_ready (_widget_5_auto_anon_in_a_ready), // @[WidthWidget.scala:230:28]
.auto_master_out_a_valid (_l2_huf_lit_reader_auto_master_out_a_valid),
.auto_master_out_a_bits_opcode (_l2_huf_lit_reader_auto_master_out_a_bits_opcode),
.auto_master_out_a_bits_param (_l2_huf_lit_reader_auto_master_out_a_bits_param),
.auto_master_out_a_bits_size (_l2_huf_lit_reader_auto_master_out_a_bits_size),
.auto_master_out_a_bits_source (_l2_huf_lit_reader_auto_master_out_a_bits_source),
.auto_master_out_a_bits_address (_l2_huf_lit_reader_auto_master_out_a_bits_address),
.auto_master_out_a_bits_mask (_l2_huf_lit_reader_auto_master_out_a_bits_mask),
.auto_master_out_a_bits_data (_l2_huf_lit_reader_auto_master_out_a_bits_data),
.auto_master_out_a_bits_corrupt (_l2_huf_lit_reader_auto_master_out_a_bits_corrupt),
.auto_master_out_d_ready (_l2_huf_lit_reader_auto_master_out_d_ready),
.auto_master_out_d_valid (_widget_5_auto_anon_in_d_valid), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_opcode (_widget_5_auto_anon_in_d_bits_opcode), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_param (_widget_5_auto_anon_in_d_bits_param), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_size (_widget_5_auto_anon_in_d_bits_size), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_source (_widget_5_auto_anon_in_d_bits_source), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_sink (_widget_5_auto_anon_in_d_bits_sink), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_denied (_widget_5_auto_anon_in_d_bits_denied), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_data (_widget_5_auto_anon_in_d_bits_data), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_corrupt (_widget_5_auto_anon_in_d_bits_corrupt), // @[WidthWidget.scala:230:28]
.io_userif_req_ready (_l2_huf_lit_reader_io_userif_req_ready),
.io_userif_req_valid (_lit_compressor_io_l2if_lit_reader_req_valid), // @[ZstdCompressor.scala:140:30]
.io_userif_req_bits_addr (_lit_compressor_io_l2if_lit_reader_req_bits_addr), // @[ZstdCompressor.scala:140:30]
.io_userif_req_bits_size (_lit_compressor_io_l2if_lit_reader_req_bits_size), // @[ZstdCompressor.scala:140:30]
.io_userif_req_bits_data (_lit_compressor_io_l2if_lit_reader_req_bits_data), // @[ZstdCompressor.scala:140:30]
.io_userif_req_bits_cmd (_lit_compressor_io_l2if_lit_reader_req_bits_cmd), // @[ZstdCompressor.scala:140:30]
.io_userif_resp_ready (_lit_compressor_io_l2if_lit_reader_resp_ready), // @[ZstdCompressor.scala:140:30]
.io_userif_resp_valid (_l2_huf_lit_reader_io_userif_resp_valid),
.io_userif_resp_bits_data (_l2_huf_lit_reader_io_userif_resp_bits_data),
.io_userif_no_memops_inflight (_l2_huf_lit_reader_io_userif_no_memops_inflight),
.io_latency_inject_cycles (_l2_huf_lit_reader_io_latency_inject_cycles_T), // @[ZstdCompressor.scala:188:65]
.io_sfence (_cmd_router_io_sfence_out), // @[ZstdCompressor.scala:112:26]
.io_ptw_req_ready (io_ptw_5_req_ready_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_req_valid (io_ptw_5_req_valid_0),
.io_ptw_req_bits_bits_addr (io_ptw_5_req_bits_bits_addr_0),
.io_ptw_req_bits_bits_need_gpa (io_ptw_5_req_bits_bits_need_gpa_0),
.io_ptw_resp_valid (io_ptw_5_resp_valid_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_ae_ptw (io_ptw_5_resp_bits_ae_ptw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_ae_final (io_ptw_5_resp_bits_ae_final_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pf (io_ptw_5_resp_bits_pf_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gf (io_ptw_5_resp_bits_gf_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_hr (io_ptw_5_resp_bits_hr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_hw (io_ptw_5_resp_bits_hw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_hx (io_ptw_5_resp_bits_hx_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_reserved_for_future (io_ptw_5_resp_bits_pte_reserved_for_future_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_ppn (io_ptw_5_resp_bits_pte_ppn_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_reserved_for_software (io_ptw_5_resp_bits_pte_reserved_for_software_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_d (io_ptw_5_resp_bits_pte_d_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_a (io_ptw_5_resp_bits_pte_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_g (io_ptw_5_resp_bits_pte_g_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_u (io_ptw_5_resp_bits_pte_u_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_x (io_ptw_5_resp_bits_pte_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_w (io_ptw_5_resp_bits_pte_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_r (io_ptw_5_resp_bits_pte_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_v (io_ptw_5_resp_bits_pte_v_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_level (io_ptw_5_resp_bits_level_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_homogeneous (io_ptw_5_resp_bits_homogeneous_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gpa_valid (io_ptw_5_resp_bits_gpa_valid_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gpa_bits (io_ptw_5_resp_bits_gpa_bits_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gpa_is_pte (io_ptw_5_resp_bits_gpa_is_pte_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_ptbr_mode (io_ptw_5_ptbr_mode_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_ptbr_ppn (io_ptw_5_ptbr_ppn_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_debug (io_ptw_5_status_debug_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_cease (io_ptw_5_status_cease_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_wfi (io_ptw_5_status_wfi_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_isa (io_ptw_5_status_isa_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_dprv (io_ptw_5_status_dprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_dv (io_ptw_5_status_dv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_prv (io_ptw_5_status_prv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_v (io_ptw_5_status_v_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mpv (io_ptw_5_status_mpv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_gva (io_ptw_5_status_gva_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_tsr (io_ptw_5_status_tsr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_tw (io_ptw_5_status_tw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_tvm (io_ptw_5_status_tvm_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mxr (io_ptw_5_status_mxr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_sum (io_ptw_5_status_sum_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mprv (io_ptw_5_status_mprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_fs (io_ptw_5_status_fs_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mpp (io_ptw_5_status_mpp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_spp (io_ptw_5_status_spp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mpie (io_ptw_5_status_mpie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_spie (io_ptw_5_status_spie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mie (io_ptw_5_status_mie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_sie (io_ptw_5_status_sie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_hstatus_spvp (io_ptw_5_hstatus_spvp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_hstatus_spv (io_ptw_5_hstatus_spv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_hstatus_gva (io_ptw_5_hstatus_gva_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_debug (io_ptw_5_gstatus_debug_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_cease (io_ptw_5_gstatus_cease_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_wfi (io_ptw_5_gstatus_wfi_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_isa (io_ptw_5_gstatus_isa_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_dprv (io_ptw_5_gstatus_dprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_dv (io_ptw_5_gstatus_dv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_prv (io_ptw_5_gstatus_prv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_v (io_ptw_5_gstatus_v_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_zero2 (io_ptw_5_gstatus_zero2_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mpv (io_ptw_5_gstatus_mpv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_gva (io_ptw_5_gstatus_gva_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mbe (io_ptw_5_gstatus_mbe_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sbe (io_ptw_5_gstatus_sbe_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sxl (io_ptw_5_gstatus_sxl_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_zero1 (io_ptw_5_gstatus_zero1_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_tsr (io_ptw_5_gstatus_tsr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_tw (io_ptw_5_gstatus_tw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_tvm (io_ptw_5_gstatus_tvm_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mxr (io_ptw_5_gstatus_mxr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sum (io_ptw_5_gstatus_sum_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mprv (io_ptw_5_gstatus_mprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_fs (io_ptw_5_gstatus_fs_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mpp (io_ptw_5_gstatus_mpp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_vs (io_ptw_5_gstatus_vs_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_spp (io_ptw_5_gstatus_spp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mpie (io_ptw_5_gstatus_mpie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_ube (io_ptw_5_gstatus_ube_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_spie (io_ptw_5_gstatus_spie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_upie (io_ptw_5_gstatus_upie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mie (io_ptw_5_gstatus_mie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_hie (io_ptw_5_gstatus_hie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sie (io_ptw_5_gstatus_sie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_uie (io_ptw_5_gstatus_uie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_l (io_ptw_5_pmp_0_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_a (io_ptw_5_pmp_0_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_x (io_ptw_5_pmp_0_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_w (io_ptw_5_pmp_0_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_r (io_ptw_5_pmp_0_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_addr (io_ptw_5_pmp_0_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_mask (io_ptw_5_pmp_0_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_l (io_ptw_5_pmp_1_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_a (io_ptw_5_pmp_1_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_x (io_ptw_5_pmp_1_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_w (io_ptw_5_pmp_1_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_r (io_ptw_5_pmp_1_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_addr (io_ptw_5_pmp_1_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_mask (io_ptw_5_pmp_1_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_l (io_ptw_5_pmp_2_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_a (io_ptw_5_pmp_2_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_x (io_ptw_5_pmp_2_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_w (io_ptw_5_pmp_2_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_r (io_ptw_5_pmp_2_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_addr (io_ptw_5_pmp_2_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_mask (io_ptw_5_pmp_2_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_l (io_ptw_5_pmp_3_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_a (io_ptw_5_pmp_3_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_x (io_ptw_5_pmp_3_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_w (io_ptw_5_pmp_3_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_r (io_ptw_5_pmp_3_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_addr (io_ptw_5_pmp_3_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_mask (io_ptw_5_pmp_3_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_l (io_ptw_5_pmp_4_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_a (io_ptw_5_pmp_4_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_x (io_ptw_5_pmp_4_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_w (io_ptw_5_pmp_4_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_r (io_ptw_5_pmp_4_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_addr (io_ptw_5_pmp_4_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_mask (io_ptw_5_pmp_4_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_l (io_ptw_5_pmp_5_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_a (io_ptw_5_pmp_5_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_x (io_ptw_5_pmp_5_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_w (io_ptw_5_pmp_5_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_r (io_ptw_5_pmp_5_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_addr (io_ptw_5_pmp_5_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_mask (io_ptw_5_pmp_5_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_l (io_ptw_5_pmp_6_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_a (io_ptw_5_pmp_6_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_x (io_ptw_5_pmp_6_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_w (io_ptw_5_pmp_6_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_r (io_ptw_5_pmp_6_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_addr (io_ptw_5_pmp_6_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_mask (io_ptw_5_pmp_6_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_l (io_ptw_5_pmp_7_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_a (io_ptw_5_pmp_7_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_x (io_ptw_5_pmp_7_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_w (io_ptw_5_pmp_7_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_r (io_ptw_5_pmp_7_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_addr (io_ptw_5_pmp_7_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_mask (io_ptw_5_pmp_7_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_ren (io_ptw_5_customCSRs_csrs_0_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_wen (io_ptw_5_customCSRs_csrs_0_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_wdata (io_ptw_5_customCSRs_csrs_0_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_value (io_ptw_5_customCSRs_csrs_0_value_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_ren (io_ptw_5_customCSRs_csrs_1_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_wen (io_ptw_5_customCSRs_csrs_1_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_wdata (io_ptw_5_customCSRs_csrs_1_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_value (io_ptw_5_customCSRs_csrs_1_value_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_ren (io_ptw_5_customCSRs_csrs_2_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_wen (io_ptw_5_customCSRs_csrs_2_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_wdata (io_ptw_5_customCSRs_csrs_2_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_value (io_ptw_5_customCSRs_csrs_2_value_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_ren (io_ptw_5_customCSRs_csrs_3_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_wen (io_ptw_5_customCSRs_csrs_3_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_wdata (io_ptw_5_customCSRs_csrs_3_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_value (io_ptw_5_customCSRs_csrs_3_value_0), // @[ZstdCompressor.scala:95:7]
.io_status_valid (_cmd_router_io_dmem_status_out_valid), // @[ZstdCompressor.scala:112:26]
.io_status_bits_debug (_cmd_router_io_dmem_status_out_bits_status_debug), // @[ZstdCompressor.scala:112:26]
.io_status_bits_cease (_cmd_router_io_dmem_status_out_bits_status_cease), // @[ZstdCompressor.scala:112:26]
.io_status_bits_wfi (_cmd_router_io_dmem_status_out_bits_status_wfi), // @[ZstdCompressor.scala:112:26]
.io_status_bits_isa (_cmd_router_io_dmem_status_out_bits_status_isa), // @[ZstdCompressor.scala:112:26]
.io_status_bits_dprv (_cmd_router_io_dmem_status_out_bits_status_dprv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_dv (_cmd_router_io_dmem_status_out_bits_status_dv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_prv (_cmd_router_io_dmem_status_out_bits_status_prv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_v (_cmd_router_io_dmem_status_out_bits_status_v), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sd (_cmd_router_io_dmem_status_out_bits_status_sd), // @[ZstdCompressor.scala:112:26]
.io_status_bits_zero2 (_cmd_router_io_dmem_status_out_bits_status_zero2), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mpv (_cmd_router_io_dmem_status_out_bits_status_mpv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_gva (_cmd_router_io_dmem_status_out_bits_status_gva), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mbe (_cmd_router_io_dmem_status_out_bits_status_mbe), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sbe (_cmd_router_io_dmem_status_out_bits_status_sbe), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sxl (_cmd_router_io_dmem_status_out_bits_status_sxl), // @[ZstdCompressor.scala:112:26]
.io_status_bits_uxl (_cmd_router_io_dmem_status_out_bits_status_uxl), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sd_rv32 (_cmd_router_io_dmem_status_out_bits_status_sd_rv32), // @[ZstdCompressor.scala:112:26]
.io_status_bits_zero1 (_cmd_router_io_dmem_status_out_bits_status_zero1), // @[ZstdCompressor.scala:112:26]
.io_status_bits_tsr (_cmd_router_io_dmem_status_out_bits_status_tsr), // @[ZstdCompressor.scala:112:26]
.io_status_bits_tw (_cmd_router_io_dmem_status_out_bits_status_tw), // @[ZstdCompressor.scala:112:26]
.io_status_bits_tvm (_cmd_router_io_dmem_status_out_bits_status_tvm), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mxr (_cmd_router_io_dmem_status_out_bits_status_mxr), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sum (_cmd_router_io_dmem_status_out_bits_status_sum), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mprv (_cmd_router_io_dmem_status_out_bits_status_mprv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_xs (_cmd_router_io_dmem_status_out_bits_status_xs), // @[ZstdCompressor.scala:112:26]
.io_status_bits_fs (_cmd_router_io_dmem_status_out_bits_status_fs), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mpp (_cmd_router_io_dmem_status_out_bits_status_mpp), // @[ZstdCompressor.scala:112:26]
.io_status_bits_vs (_cmd_router_io_dmem_status_out_bits_status_vs), // @[ZstdCompressor.scala:112:26]
.io_status_bits_spp (_cmd_router_io_dmem_status_out_bits_status_spp), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mpie (_cmd_router_io_dmem_status_out_bits_status_mpie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_ube (_cmd_router_io_dmem_status_out_bits_status_ube), // @[ZstdCompressor.scala:112:26]
.io_status_bits_spie (_cmd_router_io_dmem_status_out_bits_status_spie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_upie (_cmd_router_io_dmem_status_out_bits_status_upie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mie (_cmd_router_io_dmem_status_out_bits_status_mie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_hie (_cmd_router_io_dmem_status_out_bits_status_hie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sie (_cmd_router_io_dmem_status_out_bits_status_sie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_uie (_cmd_router_io_dmem_status_out_bits_status_uie) // @[ZstdCompressor.scala:112:26]
); // @[ZstdCompressor.scala:55:37]
TLWidthWidget32_5 widget_5 ( // @[WidthWidget.scala:230:28]
.clock (clock),
.reset (reset),
.auto_anon_in_a_ready (_widget_5_auto_anon_in_a_ready),
.auto_anon_in_a_valid (_l2_huf_lit_reader_auto_master_out_a_valid), // @[ZstdCompressor.scala:55:37]
.auto_anon_in_a_bits_opcode (_l2_huf_lit_reader_auto_master_out_a_bits_opcode), // @[ZstdCompressor.scala:55:37]
.auto_anon_in_a_bits_param (_l2_huf_lit_reader_auto_master_out_a_bits_param), // @[ZstdCompressor.scala:55:37]
.auto_anon_in_a_bits_size (_l2_huf_lit_reader_auto_master_out_a_bits_size), // @[ZstdCompressor.scala:55:37]
.auto_anon_in_a_bits_source (_l2_huf_lit_reader_auto_master_out_a_bits_source), // @[ZstdCompressor.scala:55:37]
.auto_anon_in_a_bits_address (_l2_huf_lit_reader_auto_master_out_a_bits_address), // @[ZstdCompressor.scala:55:37]
.auto_anon_in_a_bits_mask (_l2_huf_lit_reader_auto_master_out_a_bits_mask), // @[ZstdCompressor.scala:55:37]
.auto_anon_in_a_bits_data (_l2_huf_lit_reader_auto_master_out_a_bits_data), // @[ZstdCompressor.scala:55:37]
.auto_anon_in_a_bits_corrupt (_l2_huf_lit_reader_auto_master_out_a_bits_corrupt), // @[ZstdCompressor.scala:55:37]
.auto_anon_in_d_ready (_l2_huf_lit_reader_auto_master_out_d_ready), // @[ZstdCompressor.scala:55:37]
.auto_anon_in_d_valid (_widget_5_auto_anon_in_d_valid),
.auto_anon_in_d_bits_opcode (_widget_5_auto_anon_in_d_bits_opcode),
.auto_anon_in_d_bits_param (_widget_5_auto_anon_in_d_bits_param),
.auto_anon_in_d_bits_size (_widget_5_auto_anon_in_d_bits_size),
.auto_anon_in_d_bits_source (_widget_5_auto_anon_in_d_bits_source),
.auto_anon_in_d_bits_sink (_widget_5_auto_anon_in_d_bits_sink),
.auto_anon_in_d_bits_denied (_widget_5_auto_anon_in_d_bits_denied),
.auto_anon_in_d_bits_data (_widget_5_auto_anon_in_d_bits_data),
.auto_anon_in_d_bits_corrupt (_widget_5_auto_anon_in_d_bits_corrupt),
.auto_anon_out_a_ready (x1_tlNodeIn_4_a_ready), // @[MixedNode.scala:551:17]
.auto_anon_out_a_valid (x1_tlNodeIn_4_a_valid),
.auto_anon_out_a_bits_opcode (x1_tlNodeIn_4_a_bits_opcode),
.auto_anon_out_a_bits_param (x1_tlNodeIn_4_a_bits_param),
.auto_anon_out_a_bits_size (x1_tlNodeIn_4_a_bits_size),
.auto_anon_out_a_bits_source (x1_tlNodeIn_4_a_bits_source),
.auto_anon_out_a_bits_address (x1_tlNodeIn_4_a_bits_address),
.auto_anon_out_a_bits_mask (x1_tlNodeIn_4_a_bits_mask),
.auto_anon_out_a_bits_data (x1_tlNodeIn_4_a_bits_data),
.auto_anon_out_a_bits_corrupt (x1_tlNodeIn_4_a_bits_corrupt),
.auto_anon_out_d_ready (x1_tlNodeIn_4_d_ready),
.auto_anon_out_d_valid (x1_tlNodeIn_4_d_valid), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_opcode (x1_tlNodeIn_4_d_bits_opcode), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_param (x1_tlNodeIn_4_d_bits_param), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_size (x1_tlNodeIn_4_d_bits_size), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_source (x1_tlNodeIn_4_d_bits_source), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_sink (x1_tlNodeIn_4_d_bits_sink), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_denied (x1_tlNodeIn_4_d_bits_denied), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_data (x1_tlNodeIn_4_d_bits_data), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_corrupt (x1_tlNodeIn_4_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[WidthWidget.scala:230:28]
L2MemHelperLatencyInjection_6 l2_huf_dic_reader ( // @[ZstdCompressor.scala:58:37]
.clock (clock),
.reset (reset),
.auto_master_out_a_ready (_widget_6_auto_anon_in_a_ready), // @[WidthWidget.scala:230:28]
.auto_master_out_a_valid (_l2_huf_dic_reader_auto_master_out_a_valid),
.auto_master_out_a_bits_opcode (_l2_huf_dic_reader_auto_master_out_a_bits_opcode),
.auto_master_out_a_bits_param (_l2_huf_dic_reader_auto_master_out_a_bits_param),
.auto_master_out_a_bits_size (_l2_huf_dic_reader_auto_master_out_a_bits_size),
.auto_master_out_a_bits_source (_l2_huf_dic_reader_auto_master_out_a_bits_source),
.auto_master_out_a_bits_address (_l2_huf_dic_reader_auto_master_out_a_bits_address),
.auto_master_out_a_bits_mask (_l2_huf_dic_reader_auto_master_out_a_bits_mask),
.auto_master_out_a_bits_data (_l2_huf_dic_reader_auto_master_out_a_bits_data),
.auto_master_out_a_bits_corrupt (_l2_huf_dic_reader_auto_master_out_a_bits_corrupt),
.auto_master_out_d_ready (_l2_huf_dic_reader_auto_master_out_d_ready),
.auto_master_out_d_valid (_widget_6_auto_anon_in_d_valid), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_opcode (_widget_6_auto_anon_in_d_bits_opcode), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_param (_widget_6_auto_anon_in_d_bits_param), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_size (_widget_6_auto_anon_in_d_bits_size), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_source (_widget_6_auto_anon_in_d_bits_source), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_sink (_widget_6_auto_anon_in_d_bits_sink), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_denied (_widget_6_auto_anon_in_d_bits_denied), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_data (_widget_6_auto_anon_in_d_bits_data), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_corrupt (_widget_6_auto_anon_in_d_bits_corrupt), // @[WidthWidget.scala:230:28]
.io_userif_req_ready (_l2_huf_dic_reader_io_userif_req_ready),
.io_userif_req_valid (_lit_compressor_io_l2if_dic_reader_req_valid), // @[ZstdCompressor.scala:140:30]
.io_userif_req_bits_addr (_lit_compressor_io_l2if_dic_reader_req_bits_addr), // @[ZstdCompressor.scala:140:30]
.io_userif_req_bits_size (_lit_compressor_io_l2if_dic_reader_req_bits_size), // @[ZstdCompressor.scala:140:30]
.io_userif_req_bits_data (_lit_compressor_io_l2if_dic_reader_req_bits_data), // @[ZstdCompressor.scala:140:30]
.io_userif_req_bits_cmd (_lit_compressor_io_l2if_dic_reader_req_bits_cmd), // @[ZstdCompressor.scala:140:30]
.io_userif_resp_ready (_lit_compressor_io_l2if_dic_reader_resp_ready), // @[ZstdCompressor.scala:140:30]
.io_userif_resp_valid (_l2_huf_dic_reader_io_userif_resp_valid),
.io_userif_resp_bits_data (_l2_huf_dic_reader_io_userif_resp_bits_data),
.io_userif_no_memops_inflight (_l2_huf_dic_reader_io_userif_no_memops_inflight),
.io_latency_inject_cycles (_l2_huf_dic_reader_io_latency_inject_cycles_T), // @[ZstdCompressor.scala:189:65]
.io_sfence (_cmd_router_io_sfence_out), // @[ZstdCompressor.scala:112:26]
.io_ptw_req_ready (io_ptw_6_req_ready_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_req_valid (io_ptw_6_req_valid_0),
.io_ptw_req_bits_bits_addr (io_ptw_6_req_bits_bits_addr_0),
.io_ptw_req_bits_bits_need_gpa (io_ptw_6_req_bits_bits_need_gpa_0),
.io_ptw_resp_valid (io_ptw_6_resp_valid_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_ae_ptw (io_ptw_6_resp_bits_ae_ptw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_ae_final (io_ptw_6_resp_bits_ae_final_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pf (io_ptw_6_resp_bits_pf_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gf (io_ptw_6_resp_bits_gf_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_hr (io_ptw_6_resp_bits_hr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_hw (io_ptw_6_resp_bits_hw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_hx (io_ptw_6_resp_bits_hx_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_reserved_for_future (io_ptw_6_resp_bits_pte_reserved_for_future_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_ppn (io_ptw_6_resp_bits_pte_ppn_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_reserved_for_software (io_ptw_6_resp_bits_pte_reserved_for_software_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_d (io_ptw_6_resp_bits_pte_d_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_a (io_ptw_6_resp_bits_pte_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_g (io_ptw_6_resp_bits_pte_g_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_u (io_ptw_6_resp_bits_pte_u_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_x (io_ptw_6_resp_bits_pte_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_w (io_ptw_6_resp_bits_pte_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_r (io_ptw_6_resp_bits_pte_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_v (io_ptw_6_resp_bits_pte_v_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_level (io_ptw_6_resp_bits_level_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_homogeneous (io_ptw_6_resp_bits_homogeneous_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gpa_valid (io_ptw_6_resp_bits_gpa_valid_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gpa_bits (io_ptw_6_resp_bits_gpa_bits_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gpa_is_pte (io_ptw_6_resp_bits_gpa_is_pte_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_ptbr_mode (io_ptw_6_ptbr_mode_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_ptbr_ppn (io_ptw_6_ptbr_ppn_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_debug (io_ptw_6_status_debug_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_cease (io_ptw_6_status_cease_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_wfi (io_ptw_6_status_wfi_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_isa (io_ptw_6_status_isa_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_dprv (io_ptw_6_status_dprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_dv (io_ptw_6_status_dv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_prv (io_ptw_6_status_prv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_v (io_ptw_6_status_v_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mpv (io_ptw_6_status_mpv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_gva (io_ptw_6_status_gva_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_tsr (io_ptw_6_status_tsr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_tw (io_ptw_6_status_tw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_tvm (io_ptw_6_status_tvm_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mxr (io_ptw_6_status_mxr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_sum (io_ptw_6_status_sum_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mprv (io_ptw_6_status_mprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_fs (io_ptw_6_status_fs_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mpp (io_ptw_6_status_mpp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_spp (io_ptw_6_status_spp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mpie (io_ptw_6_status_mpie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_spie (io_ptw_6_status_spie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mie (io_ptw_6_status_mie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_sie (io_ptw_6_status_sie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_hstatus_spvp (io_ptw_6_hstatus_spvp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_hstatus_spv (io_ptw_6_hstatus_spv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_hstatus_gva (io_ptw_6_hstatus_gva_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_debug (io_ptw_6_gstatus_debug_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_cease (io_ptw_6_gstatus_cease_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_wfi (io_ptw_6_gstatus_wfi_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_isa (io_ptw_6_gstatus_isa_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_dprv (io_ptw_6_gstatus_dprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_dv (io_ptw_6_gstatus_dv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_prv (io_ptw_6_gstatus_prv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_v (io_ptw_6_gstatus_v_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_zero2 (io_ptw_6_gstatus_zero2_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mpv (io_ptw_6_gstatus_mpv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_gva (io_ptw_6_gstatus_gva_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mbe (io_ptw_6_gstatus_mbe_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sbe (io_ptw_6_gstatus_sbe_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sxl (io_ptw_6_gstatus_sxl_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_zero1 (io_ptw_6_gstatus_zero1_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_tsr (io_ptw_6_gstatus_tsr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_tw (io_ptw_6_gstatus_tw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_tvm (io_ptw_6_gstatus_tvm_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mxr (io_ptw_6_gstatus_mxr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sum (io_ptw_6_gstatus_sum_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mprv (io_ptw_6_gstatus_mprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_fs (io_ptw_6_gstatus_fs_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mpp (io_ptw_6_gstatus_mpp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_vs (io_ptw_6_gstatus_vs_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_spp (io_ptw_6_gstatus_spp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mpie (io_ptw_6_gstatus_mpie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_ube (io_ptw_6_gstatus_ube_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_spie (io_ptw_6_gstatus_spie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_upie (io_ptw_6_gstatus_upie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mie (io_ptw_6_gstatus_mie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_hie (io_ptw_6_gstatus_hie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sie (io_ptw_6_gstatus_sie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_uie (io_ptw_6_gstatus_uie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_l (io_ptw_6_pmp_0_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_a (io_ptw_6_pmp_0_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_x (io_ptw_6_pmp_0_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_w (io_ptw_6_pmp_0_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_r (io_ptw_6_pmp_0_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_addr (io_ptw_6_pmp_0_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_mask (io_ptw_6_pmp_0_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_l (io_ptw_6_pmp_1_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_a (io_ptw_6_pmp_1_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_x (io_ptw_6_pmp_1_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_w (io_ptw_6_pmp_1_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_r (io_ptw_6_pmp_1_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_addr (io_ptw_6_pmp_1_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_mask (io_ptw_6_pmp_1_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_l (io_ptw_6_pmp_2_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_a (io_ptw_6_pmp_2_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_x (io_ptw_6_pmp_2_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_w (io_ptw_6_pmp_2_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_r (io_ptw_6_pmp_2_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_addr (io_ptw_6_pmp_2_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_mask (io_ptw_6_pmp_2_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_l (io_ptw_6_pmp_3_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_a (io_ptw_6_pmp_3_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_x (io_ptw_6_pmp_3_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_w (io_ptw_6_pmp_3_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_r (io_ptw_6_pmp_3_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_addr (io_ptw_6_pmp_3_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_mask (io_ptw_6_pmp_3_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_l (io_ptw_6_pmp_4_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_a (io_ptw_6_pmp_4_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_x (io_ptw_6_pmp_4_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_w (io_ptw_6_pmp_4_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_r (io_ptw_6_pmp_4_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_addr (io_ptw_6_pmp_4_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_mask (io_ptw_6_pmp_4_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_l (io_ptw_6_pmp_5_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_a (io_ptw_6_pmp_5_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_x (io_ptw_6_pmp_5_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_w (io_ptw_6_pmp_5_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_r (io_ptw_6_pmp_5_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_addr (io_ptw_6_pmp_5_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_mask (io_ptw_6_pmp_5_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_l (io_ptw_6_pmp_6_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_a (io_ptw_6_pmp_6_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_x (io_ptw_6_pmp_6_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_w (io_ptw_6_pmp_6_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_r (io_ptw_6_pmp_6_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_addr (io_ptw_6_pmp_6_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_mask (io_ptw_6_pmp_6_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_l (io_ptw_6_pmp_7_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_a (io_ptw_6_pmp_7_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_x (io_ptw_6_pmp_7_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_w (io_ptw_6_pmp_7_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_r (io_ptw_6_pmp_7_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_addr (io_ptw_6_pmp_7_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_mask (io_ptw_6_pmp_7_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_ren (io_ptw_6_customCSRs_csrs_0_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_wen (io_ptw_6_customCSRs_csrs_0_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_wdata (io_ptw_6_customCSRs_csrs_0_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_value (io_ptw_6_customCSRs_csrs_0_value_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_ren (io_ptw_6_customCSRs_csrs_1_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_wen (io_ptw_6_customCSRs_csrs_1_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_wdata (io_ptw_6_customCSRs_csrs_1_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_value (io_ptw_6_customCSRs_csrs_1_value_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_ren (io_ptw_6_customCSRs_csrs_2_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_wen (io_ptw_6_customCSRs_csrs_2_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_wdata (io_ptw_6_customCSRs_csrs_2_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_value (io_ptw_6_customCSRs_csrs_2_value_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_ren (io_ptw_6_customCSRs_csrs_3_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_wen (io_ptw_6_customCSRs_csrs_3_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_wdata (io_ptw_6_customCSRs_csrs_3_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_value (io_ptw_6_customCSRs_csrs_3_value_0), // @[ZstdCompressor.scala:95:7]
.io_status_valid (_cmd_router_io_dmem_status_out_valid), // @[ZstdCompressor.scala:112:26]
.io_status_bits_debug (_cmd_router_io_dmem_status_out_bits_status_debug), // @[ZstdCompressor.scala:112:26]
.io_status_bits_cease (_cmd_router_io_dmem_status_out_bits_status_cease), // @[ZstdCompressor.scala:112:26]
.io_status_bits_wfi (_cmd_router_io_dmem_status_out_bits_status_wfi), // @[ZstdCompressor.scala:112:26]
.io_status_bits_isa (_cmd_router_io_dmem_status_out_bits_status_isa), // @[ZstdCompressor.scala:112:26]
.io_status_bits_dprv (_cmd_router_io_dmem_status_out_bits_status_dprv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_dv (_cmd_router_io_dmem_status_out_bits_status_dv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_prv (_cmd_router_io_dmem_status_out_bits_status_prv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_v (_cmd_router_io_dmem_status_out_bits_status_v), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sd (_cmd_router_io_dmem_status_out_bits_status_sd), // @[ZstdCompressor.scala:112:26]
.io_status_bits_zero2 (_cmd_router_io_dmem_status_out_bits_status_zero2), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mpv (_cmd_router_io_dmem_status_out_bits_status_mpv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_gva (_cmd_router_io_dmem_status_out_bits_status_gva), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mbe (_cmd_router_io_dmem_status_out_bits_status_mbe), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sbe (_cmd_router_io_dmem_status_out_bits_status_sbe), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sxl (_cmd_router_io_dmem_status_out_bits_status_sxl), // @[ZstdCompressor.scala:112:26]
.io_status_bits_uxl (_cmd_router_io_dmem_status_out_bits_status_uxl), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sd_rv32 (_cmd_router_io_dmem_status_out_bits_status_sd_rv32), // @[ZstdCompressor.scala:112:26]
.io_status_bits_zero1 (_cmd_router_io_dmem_status_out_bits_status_zero1), // @[ZstdCompressor.scala:112:26]
.io_status_bits_tsr (_cmd_router_io_dmem_status_out_bits_status_tsr), // @[ZstdCompressor.scala:112:26]
.io_status_bits_tw (_cmd_router_io_dmem_status_out_bits_status_tw), // @[ZstdCompressor.scala:112:26]
.io_status_bits_tvm (_cmd_router_io_dmem_status_out_bits_status_tvm), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mxr (_cmd_router_io_dmem_status_out_bits_status_mxr), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sum (_cmd_router_io_dmem_status_out_bits_status_sum), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mprv (_cmd_router_io_dmem_status_out_bits_status_mprv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_xs (_cmd_router_io_dmem_status_out_bits_status_xs), // @[ZstdCompressor.scala:112:26]
.io_status_bits_fs (_cmd_router_io_dmem_status_out_bits_status_fs), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mpp (_cmd_router_io_dmem_status_out_bits_status_mpp), // @[ZstdCompressor.scala:112:26]
.io_status_bits_vs (_cmd_router_io_dmem_status_out_bits_status_vs), // @[ZstdCompressor.scala:112:26]
.io_status_bits_spp (_cmd_router_io_dmem_status_out_bits_status_spp), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mpie (_cmd_router_io_dmem_status_out_bits_status_mpie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_ube (_cmd_router_io_dmem_status_out_bits_status_ube), // @[ZstdCompressor.scala:112:26]
.io_status_bits_spie (_cmd_router_io_dmem_status_out_bits_status_spie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_upie (_cmd_router_io_dmem_status_out_bits_status_upie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mie (_cmd_router_io_dmem_status_out_bits_status_mie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_hie (_cmd_router_io_dmem_status_out_bits_status_hie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sie (_cmd_router_io_dmem_status_out_bits_status_sie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_uie (_cmd_router_io_dmem_status_out_bits_status_uie) // @[ZstdCompressor.scala:112:26]
); // @[ZstdCompressor.scala:58:37]
TLWidthWidget32_6 widget_6 ( // @[WidthWidget.scala:230:28]
.clock (clock),
.reset (reset),
.auto_anon_in_a_ready (_widget_6_auto_anon_in_a_ready),
.auto_anon_in_a_valid (_l2_huf_dic_reader_auto_master_out_a_valid), // @[ZstdCompressor.scala:58:37]
.auto_anon_in_a_bits_opcode (_l2_huf_dic_reader_auto_master_out_a_bits_opcode), // @[ZstdCompressor.scala:58:37]
.auto_anon_in_a_bits_param (_l2_huf_dic_reader_auto_master_out_a_bits_param), // @[ZstdCompressor.scala:58:37]
.auto_anon_in_a_bits_size (_l2_huf_dic_reader_auto_master_out_a_bits_size), // @[ZstdCompressor.scala:58:37]
.auto_anon_in_a_bits_source (_l2_huf_dic_reader_auto_master_out_a_bits_source), // @[ZstdCompressor.scala:58:37]
.auto_anon_in_a_bits_address (_l2_huf_dic_reader_auto_master_out_a_bits_address), // @[ZstdCompressor.scala:58:37]
.auto_anon_in_a_bits_mask (_l2_huf_dic_reader_auto_master_out_a_bits_mask), // @[ZstdCompressor.scala:58:37]
.auto_anon_in_a_bits_data (_l2_huf_dic_reader_auto_master_out_a_bits_data), // @[ZstdCompressor.scala:58:37]
.auto_anon_in_a_bits_corrupt (_l2_huf_dic_reader_auto_master_out_a_bits_corrupt), // @[ZstdCompressor.scala:58:37]
.auto_anon_in_d_ready (_l2_huf_dic_reader_auto_master_out_d_ready), // @[ZstdCompressor.scala:58:37]
.auto_anon_in_d_valid (_widget_6_auto_anon_in_d_valid),
.auto_anon_in_d_bits_opcode (_widget_6_auto_anon_in_d_bits_opcode),
.auto_anon_in_d_bits_param (_widget_6_auto_anon_in_d_bits_param),
.auto_anon_in_d_bits_size (_widget_6_auto_anon_in_d_bits_size),
.auto_anon_in_d_bits_source (_widget_6_auto_anon_in_d_bits_source),
.auto_anon_in_d_bits_sink (_widget_6_auto_anon_in_d_bits_sink),
.auto_anon_in_d_bits_denied (_widget_6_auto_anon_in_d_bits_denied),
.auto_anon_in_d_bits_data (_widget_6_auto_anon_in_d_bits_data),
.auto_anon_in_d_bits_corrupt (_widget_6_auto_anon_in_d_bits_corrupt),
.auto_anon_out_a_ready (x1_tlNodeIn_5_a_ready), // @[MixedNode.scala:551:17]
.auto_anon_out_a_valid (x1_tlNodeIn_5_a_valid),
.auto_anon_out_a_bits_opcode (x1_tlNodeIn_5_a_bits_opcode),
.auto_anon_out_a_bits_param (x1_tlNodeIn_5_a_bits_param),
.auto_anon_out_a_bits_size (x1_tlNodeIn_5_a_bits_size),
.auto_anon_out_a_bits_source (x1_tlNodeIn_5_a_bits_source),
.auto_anon_out_a_bits_address (x1_tlNodeIn_5_a_bits_address),
.auto_anon_out_a_bits_mask (x1_tlNodeIn_5_a_bits_mask),
.auto_anon_out_a_bits_data (x1_tlNodeIn_5_a_bits_data),
.auto_anon_out_a_bits_corrupt (x1_tlNodeIn_5_a_bits_corrupt),
.auto_anon_out_d_ready (x1_tlNodeIn_5_d_ready),
.auto_anon_out_d_valid (x1_tlNodeIn_5_d_valid), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_opcode (x1_tlNodeIn_5_d_bits_opcode), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_param (x1_tlNodeIn_5_d_bits_param), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_size (x1_tlNodeIn_5_d_bits_size), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_source (x1_tlNodeIn_5_d_bits_source), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_sink (x1_tlNodeIn_5_d_bits_sink), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_denied (x1_tlNodeIn_5_d_bits_denied), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_data (x1_tlNodeIn_5_d_bits_data), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_corrupt (x1_tlNodeIn_5_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[WidthWidget.scala:230:28]
L2MemHelperLatencyInjection_7 l2_huf_dic_writer ( // @[ZstdCompressor.scala:61:37]
.clock (clock),
.reset (reset),
.auto_master_out_a_ready (_widget_7_auto_anon_in_a_ready), // @[WidthWidget.scala:230:28]
.auto_master_out_a_valid (_l2_huf_dic_writer_auto_master_out_a_valid),
.auto_master_out_a_bits_opcode (_l2_huf_dic_writer_auto_master_out_a_bits_opcode),
.auto_master_out_a_bits_param (_l2_huf_dic_writer_auto_master_out_a_bits_param),
.auto_master_out_a_bits_size (_l2_huf_dic_writer_auto_master_out_a_bits_size),
.auto_master_out_a_bits_source (_l2_huf_dic_writer_auto_master_out_a_bits_source),
.auto_master_out_a_bits_address (_l2_huf_dic_writer_auto_master_out_a_bits_address),
.auto_master_out_a_bits_mask (_l2_huf_dic_writer_auto_master_out_a_bits_mask),
.auto_master_out_a_bits_data (_l2_huf_dic_writer_auto_master_out_a_bits_data),
.auto_master_out_a_bits_corrupt (_l2_huf_dic_writer_auto_master_out_a_bits_corrupt),
.auto_master_out_d_ready (_l2_huf_dic_writer_auto_master_out_d_ready),
.auto_master_out_d_valid (_widget_7_auto_anon_in_d_valid), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_opcode (_widget_7_auto_anon_in_d_bits_opcode), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_param (_widget_7_auto_anon_in_d_bits_param), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_size (_widget_7_auto_anon_in_d_bits_size), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_source (_widget_7_auto_anon_in_d_bits_source), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_sink (_widget_7_auto_anon_in_d_bits_sink), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_denied (_widget_7_auto_anon_in_d_bits_denied), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_data (_widget_7_auto_anon_in_d_bits_data), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_corrupt (_widget_7_auto_anon_in_d_bits_corrupt), // @[WidthWidget.scala:230:28]
.io_userif_req_ready (_l2_huf_dic_writer_io_userif_req_ready),
.io_userif_req_valid (_lit_compressor_io_l2if_dic_writer_req_valid), // @[ZstdCompressor.scala:140:30]
.io_userif_req_bits_addr (_lit_compressor_io_l2if_dic_writer_req_bits_addr), // @[ZstdCompressor.scala:140:30]
.io_userif_req_bits_size (_lit_compressor_io_l2if_dic_writer_req_bits_size), // @[ZstdCompressor.scala:140:30]
.io_userif_req_bits_data (_lit_compressor_io_l2if_dic_writer_req_bits_data), // @[ZstdCompressor.scala:140:30]
.io_userif_req_bits_cmd (_lit_compressor_io_l2if_dic_writer_req_bits_cmd), // @[ZstdCompressor.scala:140:30]
.io_userif_resp_ready (_lit_compressor_io_l2if_dic_writer_resp_ready), // @[ZstdCompressor.scala:140:30]
.io_userif_resp_valid (_l2_huf_dic_writer_io_userif_resp_valid),
.io_userif_resp_bits_data (_l2_huf_dic_writer_io_userif_resp_bits_data),
.io_userif_no_memops_inflight (_l2_huf_dic_writer_io_userif_no_memops_inflight),
.io_latency_inject_cycles (_cmd_router_io_LATENCY_INJECTION_CYCLES), // @[ZstdCompressor.scala:112:26]
.io_sfence (_cmd_router_io_sfence_out), // @[ZstdCompressor.scala:112:26]
.io_ptw_req_ready (io_ptw_7_req_ready_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_req_valid (io_ptw_7_req_valid_0),
.io_ptw_req_bits_bits_addr (io_ptw_7_req_bits_bits_addr_0),
.io_ptw_req_bits_bits_need_gpa (io_ptw_7_req_bits_bits_need_gpa_0),
.io_ptw_resp_valid (io_ptw_7_resp_valid_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_ae_ptw (io_ptw_7_resp_bits_ae_ptw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_ae_final (io_ptw_7_resp_bits_ae_final_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pf (io_ptw_7_resp_bits_pf_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gf (io_ptw_7_resp_bits_gf_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_hr (io_ptw_7_resp_bits_hr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_hw (io_ptw_7_resp_bits_hw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_hx (io_ptw_7_resp_bits_hx_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_reserved_for_future (io_ptw_7_resp_bits_pte_reserved_for_future_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_ppn (io_ptw_7_resp_bits_pte_ppn_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_reserved_for_software (io_ptw_7_resp_bits_pte_reserved_for_software_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_d (io_ptw_7_resp_bits_pte_d_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_a (io_ptw_7_resp_bits_pte_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_g (io_ptw_7_resp_bits_pte_g_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_u (io_ptw_7_resp_bits_pte_u_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_x (io_ptw_7_resp_bits_pte_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_w (io_ptw_7_resp_bits_pte_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_r (io_ptw_7_resp_bits_pte_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_v (io_ptw_7_resp_bits_pte_v_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_level (io_ptw_7_resp_bits_level_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_homogeneous (io_ptw_7_resp_bits_homogeneous_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gpa_valid (io_ptw_7_resp_bits_gpa_valid_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gpa_bits (io_ptw_7_resp_bits_gpa_bits_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gpa_is_pte (io_ptw_7_resp_bits_gpa_is_pte_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_ptbr_mode (io_ptw_7_ptbr_mode_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_ptbr_ppn (io_ptw_7_ptbr_ppn_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_debug (io_ptw_7_status_debug_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_cease (io_ptw_7_status_cease_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_wfi (io_ptw_7_status_wfi_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_isa (io_ptw_7_status_isa_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_dprv (io_ptw_7_status_dprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_dv (io_ptw_7_status_dv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_prv (io_ptw_7_status_prv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_v (io_ptw_7_status_v_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mpv (io_ptw_7_status_mpv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_gva (io_ptw_7_status_gva_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_tsr (io_ptw_7_status_tsr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_tw (io_ptw_7_status_tw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_tvm (io_ptw_7_status_tvm_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mxr (io_ptw_7_status_mxr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_sum (io_ptw_7_status_sum_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mprv (io_ptw_7_status_mprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_fs (io_ptw_7_status_fs_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mpp (io_ptw_7_status_mpp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_spp (io_ptw_7_status_spp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mpie (io_ptw_7_status_mpie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_spie (io_ptw_7_status_spie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mie (io_ptw_7_status_mie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_sie (io_ptw_7_status_sie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_hstatus_spvp (io_ptw_7_hstatus_spvp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_hstatus_spv (io_ptw_7_hstatus_spv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_hstatus_gva (io_ptw_7_hstatus_gva_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_debug (io_ptw_7_gstatus_debug_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_cease (io_ptw_7_gstatus_cease_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_wfi (io_ptw_7_gstatus_wfi_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_isa (io_ptw_7_gstatus_isa_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_dprv (io_ptw_7_gstatus_dprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_dv (io_ptw_7_gstatus_dv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_prv (io_ptw_7_gstatus_prv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_v (io_ptw_7_gstatus_v_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_zero2 (io_ptw_7_gstatus_zero2_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mpv (io_ptw_7_gstatus_mpv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_gva (io_ptw_7_gstatus_gva_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mbe (io_ptw_7_gstatus_mbe_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sbe (io_ptw_7_gstatus_sbe_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sxl (io_ptw_7_gstatus_sxl_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_zero1 (io_ptw_7_gstatus_zero1_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_tsr (io_ptw_7_gstatus_tsr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_tw (io_ptw_7_gstatus_tw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_tvm (io_ptw_7_gstatus_tvm_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mxr (io_ptw_7_gstatus_mxr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sum (io_ptw_7_gstatus_sum_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mprv (io_ptw_7_gstatus_mprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_fs (io_ptw_7_gstatus_fs_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mpp (io_ptw_7_gstatus_mpp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_vs (io_ptw_7_gstatus_vs_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_spp (io_ptw_7_gstatus_spp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mpie (io_ptw_7_gstatus_mpie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_ube (io_ptw_7_gstatus_ube_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_spie (io_ptw_7_gstatus_spie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_upie (io_ptw_7_gstatus_upie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mie (io_ptw_7_gstatus_mie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_hie (io_ptw_7_gstatus_hie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sie (io_ptw_7_gstatus_sie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_uie (io_ptw_7_gstatus_uie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_l (io_ptw_7_pmp_0_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_a (io_ptw_7_pmp_0_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_x (io_ptw_7_pmp_0_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_w (io_ptw_7_pmp_0_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_r (io_ptw_7_pmp_0_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_addr (io_ptw_7_pmp_0_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_mask (io_ptw_7_pmp_0_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_l (io_ptw_7_pmp_1_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_a (io_ptw_7_pmp_1_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_x (io_ptw_7_pmp_1_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_w (io_ptw_7_pmp_1_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_r (io_ptw_7_pmp_1_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_addr (io_ptw_7_pmp_1_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_mask (io_ptw_7_pmp_1_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_l (io_ptw_7_pmp_2_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_a (io_ptw_7_pmp_2_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_x (io_ptw_7_pmp_2_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_w (io_ptw_7_pmp_2_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_r (io_ptw_7_pmp_2_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_addr (io_ptw_7_pmp_2_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_mask (io_ptw_7_pmp_2_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_l (io_ptw_7_pmp_3_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_a (io_ptw_7_pmp_3_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_x (io_ptw_7_pmp_3_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_w (io_ptw_7_pmp_3_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_r (io_ptw_7_pmp_3_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_addr (io_ptw_7_pmp_3_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_mask (io_ptw_7_pmp_3_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_l (io_ptw_7_pmp_4_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_a (io_ptw_7_pmp_4_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_x (io_ptw_7_pmp_4_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_w (io_ptw_7_pmp_4_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_r (io_ptw_7_pmp_4_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_addr (io_ptw_7_pmp_4_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_mask (io_ptw_7_pmp_4_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_l (io_ptw_7_pmp_5_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_a (io_ptw_7_pmp_5_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_x (io_ptw_7_pmp_5_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_w (io_ptw_7_pmp_5_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_r (io_ptw_7_pmp_5_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_addr (io_ptw_7_pmp_5_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_mask (io_ptw_7_pmp_5_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_l (io_ptw_7_pmp_6_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_a (io_ptw_7_pmp_6_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_x (io_ptw_7_pmp_6_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_w (io_ptw_7_pmp_6_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_r (io_ptw_7_pmp_6_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_addr (io_ptw_7_pmp_6_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_mask (io_ptw_7_pmp_6_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_l (io_ptw_7_pmp_7_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_a (io_ptw_7_pmp_7_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_x (io_ptw_7_pmp_7_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_w (io_ptw_7_pmp_7_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_r (io_ptw_7_pmp_7_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_addr (io_ptw_7_pmp_7_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_mask (io_ptw_7_pmp_7_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_ren (io_ptw_7_customCSRs_csrs_0_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_wen (io_ptw_7_customCSRs_csrs_0_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_wdata (io_ptw_7_customCSRs_csrs_0_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_value (io_ptw_7_customCSRs_csrs_0_value_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_ren (io_ptw_7_customCSRs_csrs_1_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_wen (io_ptw_7_customCSRs_csrs_1_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_wdata (io_ptw_7_customCSRs_csrs_1_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_value (io_ptw_7_customCSRs_csrs_1_value_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_ren (io_ptw_7_customCSRs_csrs_2_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_wen (io_ptw_7_customCSRs_csrs_2_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_wdata (io_ptw_7_customCSRs_csrs_2_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_value (io_ptw_7_customCSRs_csrs_2_value_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_ren (io_ptw_7_customCSRs_csrs_3_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_wen (io_ptw_7_customCSRs_csrs_3_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_wdata (io_ptw_7_customCSRs_csrs_3_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_value (io_ptw_7_customCSRs_csrs_3_value_0), // @[ZstdCompressor.scala:95:7]
.io_status_valid (_cmd_router_io_dmem_status_out_valid), // @[ZstdCompressor.scala:112:26]
.io_status_bits_debug (_cmd_router_io_dmem_status_out_bits_status_debug), // @[ZstdCompressor.scala:112:26]
.io_status_bits_cease (_cmd_router_io_dmem_status_out_bits_status_cease), // @[ZstdCompressor.scala:112:26]
.io_status_bits_wfi (_cmd_router_io_dmem_status_out_bits_status_wfi), // @[ZstdCompressor.scala:112:26]
.io_status_bits_isa (_cmd_router_io_dmem_status_out_bits_status_isa), // @[ZstdCompressor.scala:112:26]
.io_status_bits_dprv (_cmd_router_io_dmem_status_out_bits_status_dprv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_dv (_cmd_router_io_dmem_status_out_bits_status_dv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_prv (_cmd_router_io_dmem_status_out_bits_status_prv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_v (_cmd_router_io_dmem_status_out_bits_status_v), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sd (_cmd_router_io_dmem_status_out_bits_status_sd), // @[ZstdCompressor.scala:112:26]
.io_status_bits_zero2 (_cmd_router_io_dmem_status_out_bits_status_zero2), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mpv (_cmd_router_io_dmem_status_out_bits_status_mpv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_gva (_cmd_router_io_dmem_status_out_bits_status_gva), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mbe (_cmd_router_io_dmem_status_out_bits_status_mbe), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sbe (_cmd_router_io_dmem_status_out_bits_status_sbe), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sxl (_cmd_router_io_dmem_status_out_bits_status_sxl), // @[ZstdCompressor.scala:112:26]
.io_status_bits_uxl (_cmd_router_io_dmem_status_out_bits_status_uxl), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sd_rv32 (_cmd_router_io_dmem_status_out_bits_status_sd_rv32), // @[ZstdCompressor.scala:112:26]
.io_status_bits_zero1 (_cmd_router_io_dmem_status_out_bits_status_zero1), // @[ZstdCompressor.scala:112:26]
.io_status_bits_tsr (_cmd_router_io_dmem_status_out_bits_status_tsr), // @[ZstdCompressor.scala:112:26]
.io_status_bits_tw (_cmd_router_io_dmem_status_out_bits_status_tw), // @[ZstdCompressor.scala:112:26]
.io_status_bits_tvm (_cmd_router_io_dmem_status_out_bits_status_tvm), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mxr (_cmd_router_io_dmem_status_out_bits_status_mxr), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sum (_cmd_router_io_dmem_status_out_bits_status_sum), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mprv (_cmd_router_io_dmem_status_out_bits_status_mprv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_xs (_cmd_router_io_dmem_status_out_bits_status_xs), // @[ZstdCompressor.scala:112:26]
.io_status_bits_fs (_cmd_router_io_dmem_status_out_bits_status_fs), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mpp (_cmd_router_io_dmem_status_out_bits_status_mpp), // @[ZstdCompressor.scala:112:26]
.io_status_bits_vs (_cmd_router_io_dmem_status_out_bits_status_vs), // @[ZstdCompressor.scala:112:26]
.io_status_bits_spp (_cmd_router_io_dmem_status_out_bits_status_spp), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mpie (_cmd_router_io_dmem_status_out_bits_status_mpie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_ube (_cmd_router_io_dmem_status_out_bits_status_ube), // @[ZstdCompressor.scala:112:26]
.io_status_bits_spie (_cmd_router_io_dmem_status_out_bits_status_spie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_upie (_cmd_router_io_dmem_status_out_bits_status_upie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mie (_cmd_router_io_dmem_status_out_bits_status_mie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_hie (_cmd_router_io_dmem_status_out_bits_status_hie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sie (_cmd_router_io_dmem_status_out_bits_status_sie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_uie (_cmd_router_io_dmem_status_out_bits_status_uie) // @[ZstdCompressor.scala:112:26]
); // @[ZstdCompressor.scala:61:37]
TLWidthWidget32_7 widget_7 ( // @[WidthWidget.scala:230:28]
.clock (clock),
.reset (reset),
.auto_anon_in_a_ready (_widget_7_auto_anon_in_a_ready),
.auto_anon_in_a_valid (_l2_huf_dic_writer_auto_master_out_a_valid), // @[ZstdCompressor.scala:61:37]
.auto_anon_in_a_bits_opcode (_l2_huf_dic_writer_auto_master_out_a_bits_opcode), // @[ZstdCompressor.scala:61:37]
.auto_anon_in_a_bits_param (_l2_huf_dic_writer_auto_master_out_a_bits_param), // @[ZstdCompressor.scala:61:37]
.auto_anon_in_a_bits_size (_l2_huf_dic_writer_auto_master_out_a_bits_size), // @[ZstdCompressor.scala:61:37]
.auto_anon_in_a_bits_source (_l2_huf_dic_writer_auto_master_out_a_bits_source), // @[ZstdCompressor.scala:61:37]
.auto_anon_in_a_bits_address (_l2_huf_dic_writer_auto_master_out_a_bits_address), // @[ZstdCompressor.scala:61:37]
.auto_anon_in_a_bits_mask (_l2_huf_dic_writer_auto_master_out_a_bits_mask), // @[ZstdCompressor.scala:61:37]
.auto_anon_in_a_bits_data (_l2_huf_dic_writer_auto_master_out_a_bits_data), // @[ZstdCompressor.scala:61:37]
.auto_anon_in_a_bits_corrupt (_l2_huf_dic_writer_auto_master_out_a_bits_corrupt), // @[ZstdCompressor.scala:61:37]
.auto_anon_in_d_ready (_l2_huf_dic_writer_auto_master_out_d_ready), // @[ZstdCompressor.scala:61:37]
.auto_anon_in_d_valid (_widget_7_auto_anon_in_d_valid),
.auto_anon_in_d_bits_opcode (_widget_7_auto_anon_in_d_bits_opcode),
.auto_anon_in_d_bits_param (_widget_7_auto_anon_in_d_bits_param),
.auto_anon_in_d_bits_size (_widget_7_auto_anon_in_d_bits_size),
.auto_anon_in_d_bits_source (_widget_7_auto_anon_in_d_bits_source),
.auto_anon_in_d_bits_sink (_widget_7_auto_anon_in_d_bits_sink),
.auto_anon_in_d_bits_denied (_widget_7_auto_anon_in_d_bits_denied),
.auto_anon_in_d_bits_data (_widget_7_auto_anon_in_d_bits_data),
.auto_anon_in_d_bits_corrupt (_widget_7_auto_anon_in_d_bits_corrupt),
.auto_anon_out_a_ready (x1_tlNodeIn_6_a_ready), // @[MixedNode.scala:551:17]
.auto_anon_out_a_valid (x1_tlNodeIn_6_a_valid),
.auto_anon_out_a_bits_opcode (x1_tlNodeIn_6_a_bits_opcode),
.auto_anon_out_a_bits_param (x1_tlNodeIn_6_a_bits_param),
.auto_anon_out_a_bits_size (x1_tlNodeIn_6_a_bits_size),
.auto_anon_out_a_bits_source (x1_tlNodeIn_6_a_bits_source),
.auto_anon_out_a_bits_address (x1_tlNodeIn_6_a_bits_address),
.auto_anon_out_a_bits_mask (x1_tlNodeIn_6_a_bits_mask),
.auto_anon_out_a_bits_data (x1_tlNodeIn_6_a_bits_data),
.auto_anon_out_a_bits_corrupt (x1_tlNodeIn_6_a_bits_corrupt),
.auto_anon_out_d_ready (x1_tlNodeIn_6_d_ready),
.auto_anon_out_d_valid (x1_tlNodeIn_6_d_valid), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_opcode (x1_tlNodeIn_6_d_bits_opcode), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_param (x1_tlNodeIn_6_d_bits_param), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_size (x1_tlNodeIn_6_d_bits_size), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_source (x1_tlNodeIn_6_d_bits_source), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_sink (x1_tlNodeIn_6_d_bits_sink), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_denied (x1_tlNodeIn_6_d_bits_denied), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_data (x1_tlNodeIn_6_d_bits_data), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_corrupt (x1_tlNodeIn_6_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[WidthWidget.scala:230:28]
L2MemHelperLatencyInjection_8 l2_huf_hdr_writer ( // @[ZstdCompressor.scala:64:37]
.clock (clock),
.reset (reset),
.auto_master_out_a_ready (_widget_8_auto_anon_in_a_ready), // @[WidthWidget.scala:230:28]
.auto_master_out_a_valid (_l2_huf_hdr_writer_auto_master_out_a_valid),
.auto_master_out_a_bits_opcode (_l2_huf_hdr_writer_auto_master_out_a_bits_opcode),
.auto_master_out_a_bits_param (_l2_huf_hdr_writer_auto_master_out_a_bits_param),
.auto_master_out_a_bits_size (_l2_huf_hdr_writer_auto_master_out_a_bits_size),
.auto_master_out_a_bits_source (_l2_huf_hdr_writer_auto_master_out_a_bits_source),
.auto_master_out_a_bits_address (_l2_huf_hdr_writer_auto_master_out_a_bits_address),
.auto_master_out_a_bits_mask (_l2_huf_hdr_writer_auto_master_out_a_bits_mask),
.auto_master_out_a_bits_data (_l2_huf_hdr_writer_auto_master_out_a_bits_data),
.auto_master_out_a_bits_corrupt (_l2_huf_hdr_writer_auto_master_out_a_bits_corrupt),
.auto_master_out_d_ready (_l2_huf_hdr_writer_auto_master_out_d_ready),
.auto_master_out_d_valid (_widget_8_auto_anon_in_d_valid), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_opcode (_widget_8_auto_anon_in_d_bits_opcode), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_param (_widget_8_auto_anon_in_d_bits_param), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_size (_widget_8_auto_anon_in_d_bits_size), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_source (_widget_8_auto_anon_in_d_bits_source), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_sink (_widget_8_auto_anon_in_d_bits_sink), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_denied (_widget_8_auto_anon_in_d_bits_denied), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_data (_widget_8_auto_anon_in_d_bits_data), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_corrupt (_widget_8_auto_anon_in_d_bits_corrupt), // @[WidthWidget.scala:230:28]
.io_userif_req_ready (_l2_huf_hdr_writer_io_userif_req_ready),
.io_userif_req_valid (_lit_compressor_io_l2if_hdr_writer_req_valid), // @[ZstdCompressor.scala:140:30]
.io_userif_req_bits_addr (_lit_compressor_io_l2if_hdr_writer_req_bits_addr), // @[ZstdCompressor.scala:140:30]
.io_userif_req_bits_size (_lit_compressor_io_l2if_hdr_writer_req_bits_size), // @[ZstdCompressor.scala:140:30]
.io_userif_req_bits_data (_lit_compressor_io_l2if_hdr_writer_req_bits_data), // @[ZstdCompressor.scala:140:30]
.io_userif_req_bits_cmd (_lit_compressor_io_l2if_hdr_writer_req_bits_cmd), // @[ZstdCompressor.scala:140:30]
.io_userif_resp_ready (_lit_compressor_io_l2if_hdr_writer_resp_ready), // @[ZstdCompressor.scala:140:30]
.io_userif_resp_valid (_l2_huf_hdr_writer_io_userif_resp_valid),
.io_userif_resp_bits_data (_l2_huf_hdr_writer_io_userif_resp_bits_data),
.io_userif_no_memops_inflight (_l2_huf_hdr_writer_io_userif_no_memops_inflight),
.io_latency_inject_cycles (_cmd_router_io_LATENCY_INJECTION_CYCLES), // @[ZstdCompressor.scala:112:26]
.io_sfence (_cmd_router_io_sfence_out), // @[ZstdCompressor.scala:112:26]
.io_ptw_req_ready (io_ptw_8_req_ready_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_req_valid (io_ptw_8_req_valid_0),
.io_ptw_req_bits_bits_addr (io_ptw_8_req_bits_bits_addr_0),
.io_ptw_req_bits_bits_need_gpa (io_ptw_8_req_bits_bits_need_gpa_0),
.io_ptw_resp_valid (io_ptw_8_resp_valid_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_ae_ptw (io_ptw_8_resp_bits_ae_ptw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_ae_final (io_ptw_8_resp_bits_ae_final_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pf (io_ptw_8_resp_bits_pf_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gf (io_ptw_8_resp_bits_gf_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_hr (io_ptw_8_resp_bits_hr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_hw (io_ptw_8_resp_bits_hw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_hx (io_ptw_8_resp_bits_hx_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_reserved_for_future (io_ptw_8_resp_bits_pte_reserved_for_future_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_ppn (io_ptw_8_resp_bits_pte_ppn_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_reserved_for_software (io_ptw_8_resp_bits_pte_reserved_for_software_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_d (io_ptw_8_resp_bits_pte_d_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_a (io_ptw_8_resp_bits_pte_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_g (io_ptw_8_resp_bits_pte_g_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_u (io_ptw_8_resp_bits_pte_u_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_x (io_ptw_8_resp_bits_pte_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_w (io_ptw_8_resp_bits_pte_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_r (io_ptw_8_resp_bits_pte_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_v (io_ptw_8_resp_bits_pte_v_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_level (io_ptw_8_resp_bits_level_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_homogeneous (io_ptw_8_resp_bits_homogeneous_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gpa_valid (io_ptw_8_resp_bits_gpa_valid_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gpa_bits (io_ptw_8_resp_bits_gpa_bits_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gpa_is_pte (io_ptw_8_resp_bits_gpa_is_pte_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_ptbr_mode (io_ptw_8_ptbr_mode_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_ptbr_ppn (io_ptw_8_ptbr_ppn_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_debug (io_ptw_8_status_debug_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_cease (io_ptw_8_status_cease_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_wfi (io_ptw_8_status_wfi_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_isa (io_ptw_8_status_isa_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_dprv (io_ptw_8_status_dprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_dv (io_ptw_8_status_dv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_prv (io_ptw_8_status_prv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_v (io_ptw_8_status_v_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mpv (io_ptw_8_status_mpv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_gva (io_ptw_8_status_gva_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_tsr (io_ptw_8_status_tsr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_tw (io_ptw_8_status_tw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_tvm (io_ptw_8_status_tvm_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mxr (io_ptw_8_status_mxr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_sum (io_ptw_8_status_sum_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mprv (io_ptw_8_status_mprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_fs (io_ptw_8_status_fs_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mpp (io_ptw_8_status_mpp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_spp (io_ptw_8_status_spp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mpie (io_ptw_8_status_mpie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_spie (io_ptw_8_status_spie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mie (io_ptw_8_status_mie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_sie (io_ptw_8_status_sie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_hstatus_spvp (io_ptw_8_hstatus_spvp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_hstatus_spv (io_ptw_8_hstatus_spv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_hstatus_gva (io_ptw_8_hstatus_gva_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_debug (io_ptw_8_gstatus_debug_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_cease (io_ptw_8_gstatus_cease_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_wfi (io_ptw_8_gstatus_wfi_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_isa (io_ptw_8_gstatus_isa_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_dprv (io_ptw_8_gstatus_dprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_dv (io_ptw_8_gstatus_dv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_prv (io_ptw_8_gstatus_prv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_v (io_ptw_8_gstatus_v_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_zero2 (io_ptw_8_gstatus_zero2_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mpv (io_ptw_8_gstatus_mpv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_gva (io_ptw_8_gstatus_gva_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mbe (io_ptw_8_gstatus_mbe_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sbe (io_ptw_8_gstatus_sbe_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sxl (io_ptw_8_gstatus_sxl_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_zero1 (io_ptw_8_gstatus_zero1_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_tsr (io_ptw_8_gstatus_tsr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_tw (io_ptw_8_gstatus_tw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_tvm (io_ptw_8_gstatus_tvm_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mxr (io_ptw_8_gstatus_mxr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sum (io_ptw_8_gstatus_sum_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mprv (io_ptw_8_gstatus_mprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_fs (io_ptw_8_gstatus_fs_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mpp (io_ptw_8_gstatus_mpp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_vs (io_ptw_8_gstatus_vs_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_spp (io_ptw_8_gstatus_spp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mpie (io_ptw_8_gstatus_mpie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_ube (io_ptw_8_gstatus_ube_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_spie (io_ptw_8_gstatus_spie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_upie (io_ptw_8_gstatus_upie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mie (io_ptw_8_gstatus_mie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_hie (io_ptw_8_gstatus_hie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sie (io_ptw_8_gstatus_sie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_uie (io_ptw_8_gstatus_uie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_l (io_ptw_8_pmp_0_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_a (io_ptw_8_pmp_0_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_x (io_ptw_8_pmp_0_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_w (io_ptw_8_pmp_0_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_r (io_ptw_8_pmp_0_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_addr (io_ptw_8_pmp_0_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_mask (io_ptw_8_pmp_0_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_l (io_ptw_8_pmp_1_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_a (io_ptw_8_pmp_1_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_x (io_ptw_8_pmp_1_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_w (io_ptw_8_pmp_1_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_r (io_ptw_8_pmp_1_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_addr (io_ptw_8_pmp_1_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_mask (io_ptw_8_pmp_1_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_l (io_ptw_8_pmp_2_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_a (io_ptw_8_pmp_2_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_x (io_ptw_8_pmp_2_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_w (io_ptw_8_pmp_2_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_r (io_ptw_8_pmp_2_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_addr (io_ptw_8_pmp_2_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_mask (io_ptw_8_pmp_2_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_l (io_ptw_8_pmp_3_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_a (io_ptw_8_pmp_3_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_x (io_ptw_8_pmp_3_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_w (io_ptw_8_pmp_3_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_r (io_ptw_8_pmp_3_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_addr (io_ptw_8_pmp_3_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_mask (io_ptw_8_pmp_3_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_l (io_ptw_8_pmp_4_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_a (io_ptw_8_pmp_4_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_x (io_ptw_8_pmp_4_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_w (io_ptw_8_pmp_4_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_r (io_ptw_8_pmp_4_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_addr (io_ptw_8_pmp_4_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_mask (io_ptw_8_pmp_4_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_l (io_ptw_8_pmp_5_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_a (io_ptw_8_pmp_5_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_x (io_ptw_8_pmp_5_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_w (io_ptw_8_pmp_5_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_r (io_ptw_8_pmp_5_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_addr (io_ptw_8_pmp_5_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_mask (io_ptw_8_pmp_5_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_l (io_ptw_8_pmp_6_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_a (io_ptw_8_pmp_6_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_x (io_ptw_8_pmp_6_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_w (io_ptw_8_pmp_6_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_r (io_ptw_8_pmp_6_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_addr (io_ptw_8_pmp_6_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_mask (io_ptw_8_pmp_6_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_l (io_ptw_8_pmp_7_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_a (io_ptw_8_pmp_7_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_x (io_ptw_8_pmp_7_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_w (io_ptw_8_pmp_7_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_r (io_ptw_8_pmp_7_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_addr (io_ptw_8_pmp_7_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_mask (io_ptw_8_pmp_7_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_ren (io_ptw_8_customCSRs_csrs_0_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_wen (io_ptw_8_customCSRs_csrs_0_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_wdata (io_ptw_8_customCSRs_csrs_0_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_value (io_ptw_8_customCSRs_csrs_0_value_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_ren (io_ptw_8_customCSRs_csrs_1_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_wen (io_ptw_8_customCSRs_csrs_1_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_wdata (io_ptw_8_customCSRs_csrs_1_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_value (io_ptw_8_customCSRs_csrs_1_value_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_ren (io_ptw_8_customCSRs_csrs_2_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_wen (io_ptw_8_customCSRs_csrs_2_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_wdata (io_ptw_8_customCSRs_csrs_2_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_value (io_ptw_8_customCSRs_csrs_2_value_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_ren (io_ptw_8_customCSRs_csrs_3_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_wen (io_ptw_8_customCSRs_csrs_3_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_wdata (io_ptw_8_customCSRs_csrs_3_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_value (io_ptw_8_customCSRs_csrs_3_value_0), // @[ZstdCompressor.scala:95:7]
.io_status_valid (_cmd_router_io_dmem_status_out_valid), // @[ZstdCompressor.scala:112:26]
.io_status_bits_debug (_cmd_router_io_dmem_status_out_bits_status_debug), // @[ZstdCompressor.scala:112:26]
.io_status_bits_cease (_cmd_router_io_dmem_status_out_bits_status_cease), // @[ZstdCompressor.scala:112:26]
.io_status_bits_wfi (_cmd_router_io_dmem_status_out_bits_status_wfi), // @[ZstdCompressor.scala:112:26]
.io_status_bits_isa (_cmd_router_io_dmem_status_out_bits_status_isa), // @[ZstdCompressor.scala:112:26]
.io_status_bits_dprv (_cmd_router_io_dmem_status_out_bits_status_dprv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_dv (_cmd_router_io_dmem_status_out_bits_status_dv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_prv (_cmd_router_io_dmem_status_out_bits_status_prv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_v (_cmd_router_io_dmem_status_out_bits_status_v), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sd (_cmd_router_io_dmem_status_out_bits_status_sd), // @[ZstdCompressor.scala:112:26]
.io_status_bits_zero2 (_cmd_router_io_dmem_status_out_bits_status_zero2), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mpv (_cmd_router_io_dmem_status_out_bits_status_mpv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_gva (_cmd_router_io_dmem_status_out_bits_status_gva), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mbe (_cmd_router_io_dmem_status_out_bits_status_mbe), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sbe (_cmd_router_io_dmem_status_out_bits_status_sbe), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sxl (_cmd_router_io_dmem_status_out_bits_status_sxl), // @[ZstdCompressor.scala:112:26]
.io_status_bits_uxl (_cmd_router_io_dmem_status_out_bits_status_uxl), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sd_rv32 (_cmd_router_io_dmem_status_out_bits_status_sd_rv32), // @[ZstdCompressor.scala:112:26]
.io_status_bits_zero1 (_cmd_router_io_dmem_status_out_bits_status_zero1), // @[ZstdCompressor.scala:112:26]
.io_status_bits_tsr (_cmd_router_io_dmem_status_out_bits_status_tsr), // @[ZstdCompressor.scala:112:26]
.io_status_bits_tw (_cmd_router_io_dmem_status_out_bits_status_tw), // @[ZstdCompressor.scala:112:26]
.io_status_bits_tvm (_cmd_router_io_dmem_status_out_bits_status_tvm), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mxr (_cmd_router_io_dmem_status_out_bits_status_mxr), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sum (_cmd_router_io_dmem_status_out_bits_status_sum), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mprv (_cmd_router_io_dmem_status_out_bits_status_mprv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_xs (_cmd_router_io_dmem_status_out_bits_status_xs), // @[ZstdCompressor.scala:112:26]
.io_status_bits_fs (_cmd_router_io_dmem_status_out_bits_status_fs), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mpp (_cmd_router_io_dmem_status_out_bits_status_mpp), // @[ZstdCompressor.scala:112:26]
.io_status_bits_vs (_cmd_router_io_dmem_status_out_bits_status_vs), // @[ZstdCompressor.scala:112:26]
.io_status_bits_spp (_cmd_router_io_dmem_status_out_bits_status_spp), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mpie (_cmd_router_io_dmem_status_out_bits_status_mpie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_ube (_cmd_router_io_dmem_status_out_bits_status_ube), // @[ZstdCompressor.scala:112:26]
.io_status_bits_spie (_cmd_router_io_dmem_status_out_bits_status_spie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_upie (_cmd_router_io_dmem_status_out_bits_status_upie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mie (_cmd_router_io_dmem_status_out_bits_status_mie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_hie (_cmd_router_io_dmem_status_out_bits_status_hie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sie (_cmd_router_io_dmem_status_out_bits_status_sie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_uie (_cmd_router_io_dmem_status_out_bits_status_uie) // @[ZstdCompressor.scala:112:26]
); // @[ZstdCompressor.scala:64:37]
TLWidthWidget32_8 widget_8 ( // @[WidthWidget.scala:230:28]
.clock (clock),
.reset (reset),
.auto_anon_in_a_ready (_widget_8_auto_anon_in_a_ready),
.auto_anon_in_a_valid (_l2_huf_hdr_writer_auto_master_out_a_valid), // @[ZstdCompressor.scala:64:37]
.auto_anon_in_a_bits_opcode (_l2_huf_hdr_writer_auto_master_out_a_bits_opcode), // @[ZstdCompressor.scala:64:37]
.auto_anon_in_a_bits_param (_l2_huf_hdr_writer_auto_master_out_a_bits_param), // @[ZstdCompressor.scala:64:37]
.auto_anon_in_a_bits_size (_l2_huf_hdr_writer_auto_master_out_a_bits_size), // @[ZstdCompressor.scala:64:37]
.auto_anon_in_a_bits_source (_l2_huf_hdr_writer_auto_master_out_a_bits_source), // @[ZstdCompressor.scala:64:37]
.auto_anon_in_a_bits_address (_l2_huf_hdr_writer_auto_master_out_a_bits_address), // @[ZstdCompressor.scala:64:37]
.auto_anon_in_a_bits_mask (_l2_huf_hdr_writer_auto_master_out_a_bits_mask), // @[ZstdCompressor.scala:64:37]
.auto_anon_in_a_bits_data (_l2_huf_hdr_writer_auto_master_out_a_bits_data), // @[ZstdCompressor.scala:64:37]
.auto_anon_in_a_bits_corrupt (_l2_huf_hdr_writer_auto_master_out_a_bits_corrupt), // @[ZstdCompressor.scala:64:37]
.auto_anon_in_d_ready (_l2_huf_hdr_writer_auto_master_out_d_ready), // @[ZstdCompressor.scala:64:37]
.auto_anon_in_d_valid (_widget_8_auto_anon_in_d_valid),
.auto_anon_in_d_bits_opcode (_widget_8_auto_anon_in_d_bits_opcode),
.auto_anon_in_d_bits_param (_widget_8_auto_anon_in_d_bits_param),
.auto_anon_in_d_bits_size (_widget_8_auto_anon_in_d_bits_size),
.auto_anon_in_d_bits_source (_widget_8_auto_anon_in_d_bits_source),
.auto_anon_in_d_bits_sink (_widget_8_auto_anon_in_d_bits_sink),
.auto_anon_in_d_bits_denied (_widget_8_auto_anon_in_d_bits_denied),
.auto_anon_in_d_bits_data (_widget_8_auto_anon_in_d_bits_data),
.auto_anon_in_d_bits_corrupt (_widget_8_auto_anon_in_d_bits_corrupt),
.auto_anon_out_a_ready (x1_tlNodeIn_7_a_ready), // @[MixedNode.scala:551:17]
.auto_anon_out_a_valid (x1_tlNodeIn_7_a_valid),
.auto_anon_out_a_bits_opcode (x1_tlNodeIn_7_a_bits_opcode),
.auto_anon_out_a_bits_param (x1_tlNodeIn_7_a_bits_param),
.auto_anon_out_a_bits_size (x1_tlNodeIn_7_a_bits_size),
.auto_anon_out_a_bits_source (x1_tlNodeIn_7_a_bits_source),
.auto_anon_out_a_bits_address (x1_tlNodeIn_7_a_bits_address),
.auto_anon_out_a_bits_mask (x1_tlNodeIn_7_a_bits_mask),
.auto_anon_out_a_bits_data (x1_tlNodeIn_7_a_bits_data),
.auto_anon_out_a_bits_corrupt (x1_tlNodeIn_7_a_bits_corrupt),
.auto_anon_out_d_ready (x1_tlNodeIn_7_d_ready),
.auto_anon_out_d_valid (x1_tlNodeIn_7_d_valid), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_opcode (x1_tlNodeIn_7_d_bits_opcode), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_param (x1_tlNodeIn_7_d_bits_param), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_size (x1_tlNodeIn_7_d_bits_size), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_source (x1_tlNodeIn_7_d_bits_source), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_sink (x1_tlNodeIn_7_d_bits_sink), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_denied (x1_tlNodeIn_7_d_bits_denied), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_data (x1_tlNodeIn_7_d_bits_data), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_corrupt (x1_tlNodeIn_7_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[WidthWidget.scala:230:28]
L2MemHelperLatencyInjection_9 l2_huf_jt_writer ( // @[ZstdCompressor.scala:67:36]
.clock (clock),
.reset (reset),
.auto_master_out_a_ready (_widget_9_auto_anon_in_a_ready), // @[WidthWidget.scala:230:28]
.auto_master_out_a_valid (_l2_huf_jt_writer_auto_master_out_a_valid),
.auto_master_out_a_bits_opcode (_l2_huf_jt_writer_auto_master_out_a_bits_opcode),
.auto_master_out_a_bits_param (_l2_huf_jt_writer_auto_master_out_a_bits_param),
.auto_master_out_a_bits_size (_l2_huf_jt_writer_auto_master_out_a_bits_size),
.auto_master_out_a_bits_source (_l2_huf_jt_writer_auto_master_out_a_bits_source),
.auto_master_out_a_bits_address (_l2_huf_jt_writer_auto_master_out_a_bits_address),
.auto_master_out_a_bits_mask (_l2_huf_jt_writer_auto_master_out_a_bits_mask),
.auto_master_out_a_bits_data (_l2_huf_jt_writer_auto_master_out_a_bits_data),
.auto_master_out_a_bits_corrupt (_l2_huf_jt_writer_auto_master_out_a_bits_corrupt),
.auto_master_out_d_ready (_l2_huf_jt_writer_auto_master_out_d_ready),
.auto_master_out_d_valid (_widget_9_auto_anon_in_d_valid), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_opcode (_widget_9_auto_anon_in_d_bits_opcode), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_param (_widget_9_auto_anon_in_d_bits_param), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_size (_widget_9_auto_anon_in_d_bits_size), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_source (_widget_9_auto_anon_in_d_bits_source), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_sink (_widget_9_auto_anon_in_d_bits_sink), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_denied (_widget_9_auto_anon_in_d_bits_denied), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_data (_widget_9_auto_anon_in_d_bits_data), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_corrupt (_widget_9_auto_anon_in_d_bits_corrupt), // @[WidthWidget.scala:230:28]
.io_userif_req_ready (_l2_huf_jt_writer_io_userif_req_ready),
.io_userif_req_valid (_lit_compressor_io_l2if_jt_writer_req_valid), // @[ZstdCompressor.scala:140:30]
.io_userif_req_bits_addr (_lit_compressor_io_l2if_jt_writer_req_bits_addr), // @[ZstdCompressor.scala:140:30]
.io_userif_req_bits_size (_lit_compressor_io_l2if_jt_writer_req_bits_size), // @[ZstdCompressor.scala:140:30]
.io_userif_req_bits_data (_lit_compressor_io_l2if_jt_writer_req_bits_data), // @[ZstdCompressor.scala:140:30]
.io_userif_req_bits_cmd (_lit_compressor_io_l2if_jt_writer_req_bits_cmd), // @[ZstdCompressor.scala:140:30]
.io_userif_resp_ready (_lit_compressor_io_l2if_jt_writer_resp_ready), // @[ZstdCompressor.scala:140:30]
.io_userif_resp_valid (_l2_huf_jt_writer_io_userif_resp_valid),
.io_userif_resp_bits_data (_l2_huf_jt_writer_io_userif_resp_bits_data),
.io_userif_no_memops_inflight (_l2_huf_jt_writer_io_userif_no_memops_inflight),
.io_latency_inject_cycles (_cmd_router_io_LATENCY_INJECTION_CYCLES), // @[ZstdCompressor.scala:112:26]
.io_sfence (_cmd_router_io_sfence_out), // @[ZstdCompressor.scala:112:26]
.io_ptw_req_ready (io_ptw_9_req_ready_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_req_valid (io_ptw_9_req_valid_0),
.io_ptw_req_bits_bits_addr (io_ptw_9_req_bits_bits_addr_0),
.io_ptw_req_bits_bits_need_gpa (io_ptw_9_req_bits_bits_need_gpa_0),
.io_ptw_resp_valid (io_ptw_9_resp_valid_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_ae_ptw (io_ptw_9_resp_bits_ae_ptw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_ae_final (io_ptw_9_resp_bits_ae_final_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pf (io_ptw_9_resp_bits_pf_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gf (io_ptw_9_resp_bits_gf_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_hr (io_ptw_9_resp_bits_hr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_hw (io_ptw_9_resp_bits_hw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_hx (io_ptw_9_resp_bits_hx_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_reserved_for_future (io_ptw_9_resp_bits_pte_reserved_for_future_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_ppn (io_ptw_9_resp_bits_pte_ppn_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_reserved_for_software (io_ptw_9_resp_bits_pte_reserved_for_software_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_d (io_ptw_9_resp_bits_pte_d_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_a (io_ptw_9_resp_bits_pte_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_g (io_ptw_9_resp_bits_pte_g_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_u (io_ptw_9_resp_bits_pte_u_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_x (io_ptw_9_resp_bits_pte_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_w (io_ptw_9_resp_bits_pte_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_r (io_ptw_9_resp_bits_pte_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_v (io_ptw_9_resp_bits_pte_v_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_level (io_ptw_9_resp_bits_level_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_homogeneous (io_ptw_9_resp_bits_homogeneous_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gpa_valid (io_ptw_9_resp_bits_gpa_valid_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gpa_bits (io_ptw_9_resp_bits_gpa_bits_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gpa_is_pte (io_ptw_9_resp_bits_gpa_is_pte_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_ptbr_mode (io_ptw_9_ptbr_mode_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_ptbr_ppn (io_ptw_9_ptbr_ppn_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_debug (io_ptw_9_status_debug_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_cease (io_ptw_9_status_cease_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_wfi (io_ptw_9_status_wfi_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_isa (io_ptw_9_status_isa_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_dprv (io_ptw_9_status_dprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_dv (io_ptw_9_status_dv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_prv (io_ptw_9_status_prv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_v (io_ptw_9_status_v_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mpv (io_ptw_9_status_mpv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_gva (io_ptw_9_status_gva_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_tsr (io_ptw_9_status_tsr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_tw (io_ptw_9_status_tw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_tvm (io_ptw_9_status_tvm_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mxr (io_ptw_9_status_mxr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_sum (io_ptw_9_status_sum_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mprv (io_ptw_9_status_mprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_fs (io_ptw_9_status_fs_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mpp (io_ptw_9_status_mpp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_spp (io_ptw_9_status_spp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mpie (io_ptw_9_status_mpie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_spie (io_ptw_9_status_spie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mie (io_ptw_9_status_mie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_sie (io_ptw_9_status_sie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_hstatus_spvp (io_ptw_9_hstatus_spvp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_hstatus_spv (io_ptw_9_hstatus_spv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_hstatus_gva (io_ptw_9_hstatus_gva_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_debug (io_ptw_9_gstatus_debug_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_cease (io_ptw_9_gstatus_cease_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_wfi (io_ptw_9_gstatus_wfi_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_isa (io_ptw_9_gstatus_isa_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_dprv (io_ptw_9_gstatus_dprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_dv (io_ptw_9_gstatus_dv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_prv (io_ptw_9_gstatus_prv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_v (io_ptw_9_gstatus_v_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_zero2 (io_ptw_9_gstatus_zero2_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mpv (io_ptw_9_gstatus_mpv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_gva (io_ptw_9_gstatus_gva_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mbe (io_ptw_9_gstatus_mbe_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sbe (io_ptw_9_gstatus_sbe_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sxl (io_ptw_9_gstatus_sxl_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_zero1 (io_ptw_9_gstatus_zero1_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_tsr (io_ptw_9_gstatus_tsr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_tw (io_ptw_9_gstatus_tw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_tvm (io_ptw_9_gstatus_tvm_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mxr (io_ptw_9_gstatus_mxr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sum (io_ptw_9_gstatus_sum_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mprv (io_ptw_9_gstatus_mprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_fs (io_ptw_9_gstatus_fs_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mpp (io_ptw_9_gstatus_mpp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_vs (io_ptw_9_gstatus_vs_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_spp (io_ptw_9_gstatus_spp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mpie (io_ptw_9_gstatus_mpie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_ube (io_ptw_9_gstatus_ube_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_spie (io_ptw_9_gstatus_spie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_upie (io_ptw_9_gstatus_upie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mie (io_ptw_9_gstatus_mie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_hie (io_ptw_9_gstatus_hie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sie (io_ptw_9_gstatus_sie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_uie (io_ptw_9_gstatus_uie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_l (io_ptw_9_pmp_0_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_a (io_ptw_9_pmp_0_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_x (io_ptw_9_pmp_0_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_w (io_ptw_9_pmp_0_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_r (io_ptw_9_pmp_0_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_addr (io_ptw_9_pmp_0_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_mask (io_ptw_9_pmp_0_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_l (io_ptw_9_pmp_1_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_a (io_ptw_9_pmp_1_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_x (io_ptw_9_pmp_1_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_w (io_ptw_9_pmp_1_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_r (io_ptw_9_pmp_1_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_addr (io_ptw_9_pmp_1_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_mask (io_ptw_9_pmp_1_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_l (io_ptw_9_pmp_2_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_a (io_ptw_9_pmp_2_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_x (io_ptw_9_pmp_2_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_w (io_ptw_9_pmp_2_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_r (io_ptw_9_pmp_2_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_addr (io_ptw_9_pmp_2_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_mask (io_ptw_9_pmp_2_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_l (io_ptw_9_pmp_3_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_a (io_ptw_9_pmp_3_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_x (io_ptw_9_pmp_3_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_w (io_ptw_9_pmp_3_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_r (io_ptw_9_pmp_3_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_addr (io_ptw_9_pmp_3_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_mask (io_ptw_9_pmp_3_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_l (io_ptw_9_pmp_4_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_a (io_ptw_9_pmp_4_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_x (io_ptw_9_pmp_4_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_w (io_ptw_9_pmp_4_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_r (io_ptw_9_pmp_4_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_addr (io_ptw_9_pmp_4_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_mask (io_ptw_9_pmp_4_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_l (io_ptw_9_pmp_5_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_a (io_ptw_9_pmp_5_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_x (io_ptw_9_pmp_5_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_w (io_ptw_9_pmp_5_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_r (io_ptw_9_pmp_5_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_addr (io_ptw_9_pmp_5_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_mask (io_ptw_9_pmp_5_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_l (io_ptw_9_pmp_6_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_a (io_ptw_9_pmp_6_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_x (io_ptw_9_pmp_6_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_w (io_ptw_9_pmp_6_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_r (io_ptw_9_pmp_6_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_addr (io_ptw_9_pmp_6_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_mask (io_ptw_9_pmp_6_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_l (io_ptw_9_pmp_7_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_a (io_ptw_9_pmp_7_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_x (io_ptw_9_pmp_7_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_w (io_ptw_9_pmp_7_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_r (io_ptw_9_pmp_7_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_addr (io_ptw_9_pmp_7_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_mask (io_ptw_9_pmp_7_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_ren (io_ptw_9_customCSRs_csrs_0_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_wen (io_ptw_9_customCSRs_csrs_0_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_wdata (io_ptw_9_customCSRs_csrs_0_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_value (io_ptw_9_customCSRs_csrs_0_value_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_ren (io_ptw_9_customCSRs_csrs_1_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_wen (io_ptw_9_customCSRs_csrs_1_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_wdata (io_ptw_9_customCSRs_csrs_1_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_value (io_ptw_9_customCSRs_csrs_1_value_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_ren (io_ptw_9_customCSRs_csrs_2_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_wen (io_ptw_9_customCSRs_csrs_2_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_wdata (io_ptw_9_customCSRs_csrs_2_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_value (io_ptw_9_customCSRs_csrs_2_value_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_ren (io_ptw_9_customCSRs_csrs_3_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_wen (io_ptw_9_customCSRs_csrs_3_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_wdata (io_ptw_9_customCSRs_csrs_3_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_value (io_ptw_9_customCSRs_csrs_3_value_0), // @[ZstdCompressor.scala:95:7]
.io_status_valid (_cmd_router_io_dmem_status_out_valid), // @[ZstdCompressor.scala:112:26]
.io_status_bits_debug (_cmd_router_io_dmem_status_out_bits_status_debug), // @[ZstdCompressor.scala:112:26]
.io_status_bits_cease (_cmd_router_io_dmem_status_out_bits_status_cease), // @[ZstdCompressor.scala:112:26]
.io_status_bits_wfi (_cmd_router_io_dmem_status_out_bits_status_wfi), // @[ZstdCompressor.scala:112:26]
.io_status_bits_isa (_cmd_router_io_dmem_status_out_bits_status_isa), // @[ZstdCompressor.scala:112:26]
.io_status_bits_dprv (_cmd_router_io_dmem_status_out_bits_status_dprv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_dv (_cmd_router_io_dmem_status_out_bits_status_dv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_prv (_cmd_router_io_dmem_status_out_bits_status_prv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_v (_cmd_router_io_dmem_status_out_bits_status_v), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sd (_cmd_router_io_dmem_status_out_bits_status_sd), // @[ZstdCompressor.scala:112:26]
.io_status_bits_zero2 (_cmd_router_io_dmem_status_out_bits_status_zero2), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mpv (_cmd_router_io_dmem_status_out_bits_status_mpv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_gva (_cmd_router_io_dmem_status_out_bits_status_gva), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mbe (_cmd_router_io_dmem_status_out_bits_status_mbe), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sbe (_cmd_router_io_dmem_status_out_bits_status_sbe), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sxl (_cmd_router_io_dmem_status_out_bits_status_sxl), // @[ZstdCompressor.scala:112:26]
.io_status_bits_uxl (_cmd_router_io_dmem_status_out_bits_status_uxl), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sd_rv32 (_cmd_router_io_dmem_status_out_bits_status_sd_rv32), // @[ZstdCompressor.scala:112:26]
.io_status_bits_zero1 (_cmd_router_io_dmem_status_out_bits_status_zero1), // @[ZstdCompressor.scala:112:26]
.io_status_bits_tsr (_cmd_router_io_dmem_status_out_bits_status_tsr), // @[ZstdCompressor.scala:112:26]
.io_status_bits_tw (_cmd_router_io_dmem_status_out_bits_status_tw), // @[ZstdCompressor.scala:112:26]
.io_status_bits_tvm (_cmd_router_io_dmem_status_out_bits_status_tvm), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mxr (_cmd_router_io_dmem_status_out_bits_status_mxr), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sum (_cmd_router_io_dmem_status_out_bits_status_sum), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mprv (_cmd_router_io_dmem_status_out_bits_status_mprv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_xs (_cmd_router_io_dmem_status_out_bits_status_xs), // @[ZstdCompressor.scala:112:26]
.io_status_bits_fs (_cmd_router_io_dmem_status_out_bits_status_fs), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mpp (_cmd_router_io_dmem_status_out_bits_status_mpp), // @[ZstdCompressor.scala:112:26]
.io_status_bits_vs (_cmd_router_io_dmem_status_out_bits_status_vs), // @[ZstdCompressor.scala:112:26]
.io_status_bits_spp (_cmd_router_io_dmem_status_out_bits_status_spp), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mpie (_cmd_router_io_dmem_status_out_bits_status_mpie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_ube (_cmd_router_io_dmem_status_out_bits_status_ube), // @[ZstdCompressor.scala:112:26]
.io_status_bits_spie (_cmd_router_io_dmem_status_out_bits_status_spie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_upie (_cmd_router_io_dmem_status_out_bits_status_upie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mie (_cmd_router_io_dmem_status_out_bits_status_mie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_hie (_cmd_router_io_dmem_status_out_bits_status_hie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sie (_cmd_router_io_dmem_status_out_bits_status_sie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_uie (_cmd_router_io_dmem_status_out_bits_status_uie) // @[ZstdCompressor.scala:112:26]
); // @[ZstdCompressor.scala:67:36]
TLWidthWidget32_9 widget_9 ( // @[WidthWidget.scala:230:28]
.clock (clock),
.reset (reset),
.auto_anon_in_a_ready (_widget_9_auto_anon_in_a_ready),
.auto_anon_in_a_valid (_l2_huf_jt_writer_auto_master_out_a_valid), // @[ZstdCompressor.scala:67:36]
.auto_anon_in_a_bits_opcode (_l2_huf_jt_writer_auto_master_out_a_bits_opcode), // @[ZstdCompressor.scala:67:36]
.auto_anon_in_a_bits_param (_l2_huf_jt_writer_auto_master_out_a_bits_param), // @[ZstdCompressor.scala:67:36]
.auto_anon_in_a_bits_size (_l2_huf_jt_writer_auto_master_out_a_bits_size), // @[ZstdCompressor.scala:67:36]
.auto_anon_in_a_bits_source (_l2_huf_jt_writer_auto_master_out_a_bits_source), // @[ZstdCompressor.scala:67:36]
.auto_anon_in_a_bits_address (_l2_huf_jt_writer_auto_master_out_a_bits_address), // @[ZstdCompressor.scala:67:36]
.auto_anon_in_a_bits_mask (_l2_huf_jt_writer_auto_master_out_a_bits_mask), // @[ZstdCompressor.scala:67:36]
.auto_anon_in_a_bits_data (_l2_huf_jt_writer_auto_master_out_a_bits_data), // @[ZstdCompressor.scala:67:36]
.auto_anon_in_a_bits_corrupt (_l2_huf_jt_writer_auto_master_out_a_bits_corrupt), // @[ZstdCompressor.scala:67:36]
.auto_anon_in_d_ready (_l2_huf_jt_writer_auto_master_out_d_ready), // @[ZstdCompressor.scala:67:36]
.auto_anon_in_d_valid (_widget_9_auto_anon_in_d_valid),
.auto_anon_in_d_bits_opcode (_widget_9_auto_anon_in_d_bits_opcode),
.auto_anon_in_d_bits_param (_widget_9_auto_anon_in_d_bits_param),
.auto_anon_in_d_bits_size (_widget_9_auto_anon_in_d_bits_size),
.auto_anon_in_d_bits_source (_widget_9_auto_anon_in_d_bits_source),
.auto_anon_in_d_bits_sink (_widget_9_auto_anon_in_d_bits_sink),
.auto_anon_in_d_bits_denied (_widget_9_auto_anon_in_d_bits_denied),
.auto_anon_in_d_bits_data (_widget_9_auto_anon_in_d_bits_data),
.auto_anon_in_d_bits_corrupt (_widget_9_auto_anon_in_d_bits_corrupt),
.auto_anon_out_a_ready (x1_tlNodeIn_8_a_ready), // @[MixedNode.scala:551:17]
.auto_anon_out_a_valid (x1_tlNodeIn_8_a_valid),
.auto_anon_out_a_bits_opcode (x1_tlNodeIn_8_a_bits_opcode),
.auto_anon_out_a_bits_param (x1_tlNodeIn_8_a_bits_param),
.auto_anon_out_a_bits_size (x1_tlNodeIn_8_a_bits_size),
.auto_anon_out_a_bits_source (x1_tlNodeIn_8_a_bits_source),
.auto_anon_out_a_bits_address (x1_tlNodeIn_8_a_bits_address),
.auto_anon_out_a_bits_mask (x1_tlNodeIn_8_a_bits_mask),
.auto_anon_out_a_bits_data (x1_tlNodeIn_8_a_bits_data),
.auto_anon_out_a_bits_corrupt (x1_tlNodeIn_8_a_bits_corrupt),
.auto_anon_out_d_ready (x1_tlNodeIn_8_d_ready),
.auto_anon_out_d_valid (x1_tlNodeIn_8_d_valid), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_opcode (x1_tlNodeIn_8_d_bits_opcode), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_param (x1_tlNodeIn_8_d_bits_param), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_size (x1_tlNodeIn_8_d_bits_size), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_source (x1_tlNodeIn_8_d_bits_source), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_sink (x1_tlNodeIn_8_d_bits_sink), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_denied (x1_tlNodeIn_8_d_bits_denied), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_data (x1_tlNodeIn_8_d_bits_data), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_corrupt (x1_tlNodeIn_8_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[WidthWidget.scala:230:28]
L2MemHelperLatencyInjection_10 l2_huf_lit_writer ( // @[ZstdCompressor.scala:70:37]
.clock (clock),
.reset (reset),
.auto_master_out_a_ready (_widget_10_auto_anon_in_a_ready), // @[WidthWidget.scala:230:28]
.auto_master_out_a_valid (_l2_huf_lit_writer_auto_master_out_a_valid),
.auto_master_out_a_bits_opcode (_l2_huf_lit_writer_auto_master_out_a_bits_opcode),
.auto_master_out_a_bits_param (_l2_huf_lit_writer_auto_master_out_a_bits_param),
.auto_master_out_a_bits_size (_l2_huf_lit_writer_auto_master_out_a_bits_size),
.auto_master_out_a_bits_source (_l2_huf_lit_writer_auto_master_out_a_bits_source),
.auto_master_out_a_bits_address (_l2_huf_lit_writer_auto_master_out_a_bits_address),
.auto_master_out_a_bits_mask (_l2_huf_lit_writer_auto_master_out_a_bits_mask),
.auto_master_out_a_bits_data (_l2_huf_lit_writer_auto_master_out_a_bits_data),
.auto_master_out_a_bits_corrupt (_l2_huf_lit_writer_auto_master_out_a_bits_corrupt),
.auto_master_out_d_ready (_l2_huf_lit_writer_auto_master_out_d_ready),
.auto_master_out_d_valid (_widget_10_auto_anon_in_d_valid), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_opcode (_widget_10_auto_anon_in_d_bits_opcode), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_param (_widget_10_auto_anon_in_d_bits_param), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_size (_widget_10_auto_anon_in_d_bits_size), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_source (_widget_10_auto_anon_in_d_bits_source), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_sink (_widget_10_auto_anon_in_d_bits_sink), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_denied (_widget_10_auto_anon_in_d_bits_denied), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_data (_widget_10_auto_anon_in_d_bits_data), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_corrupt (_widget_10_auto_anon_in_d_bits_corrupt), // @[WidthWidget.scala:230:28]
.io_userif_req_ready (_l2_huf_lit_writer_io_userif_req_ready),
.io_userif_req_valid (_lit_compressor_io_l2if_lit_writer_req_valid), // @[ZstdCompressor.scala:140:30]
.io_userif_req_bits_addr (_lit_compressor_io_l2if_lit_writer_req_bits_addr), // @[ZstdCompressor.scala:140:30]
.io_userif_req_bits_size (_lit_compressor_io_l2if_lit_writer_req_bits_size), // @[ZstdCompressor.scala:140:30]
.io_userif_req_bits_data (_lit_compressor_io_l2if_lit_writer_req_bits_data), // @[ZstdCompressor.scala:140:30]
.io_userif_req_bits_cmd (_lit_compressor_io_l2if_lit_writer_req_bits_cmd), // @[ZstdCompressor.scala:140:30]
.io_userif_resp_ready (_lit_compressor_io_l2if_lit_writer_resp_ready), // @[ZstdCompressor.scala:140:30]
.io_userif_resp_valid (_l2_huf_lit_writer_io_userif_resp_valid),
.io_userif_resp_bits_data (_l2_huf_lit_writer_io_userif_resp_bits_data),
.io_userif_no_memops_inflight (_l2_huf_lit_writer_io_userif_no_memops_inflight),
.io_latency_inject_cycles (_cmd_router_io_LATENCY_INJECTION_CYCLES), // @[ZstdCompressor.scala:112:26]
.io_sfence (_cmd_router_io_sfence_out), // @[ZstdCompressor.scala:112:26]
.io_ptw_req_ready (io_ptw_10_req_ready_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_req_valid (io_ptw_10_req_valid_0),
.io_ptw_req_bits_bits_addr (io_ptw_10_req_bits_bits_addr_0),
.io_ptw_req_bits_bits_need_gpa (io_ptw_10_req_bits_bits_need_gpa_0),
.io_ptw_resp_valid (io_ptw_10_resp_valid_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_ae_ptw (io_ptw_10_resp_bits_ae_ptw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_ae_final (io_ptw_10_resp_bits_ae_final_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pf (io_ptw_10_resp_bits_pf_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gf (io_ptw_10_resp_bits_gf_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_hr (io_ptw_10_resp_bits_hr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_hw (io_ptw_10_resp_bits_hw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_hx (io_ptw_10_resp_bits_hx_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_reserved_for_future (io_ptw_10_resp_bits_pte_reserved_for_future_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_ppn (io_ptw_10_resp_bits_pte_ppn_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_reserved_for_software (io_ptw_10_resp_bits_pte_reserved_for_software_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_d (io_ptw_10_resp_bits_pte_d_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_a (io_ptw_10_resp_bits_pte_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_g (io_ptw_10_resp_bits_pte_g_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_u (io_ptw_10_resp_bits_pte_u_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_x (io_ptw_10_resp_bits_pte_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_w (io_ptw_10_resp_bits_pte_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_r (io_ptw_10_resp_bits_pte_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_v (io_ptw_10_resp_bits_pte_v_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_level (io_ptw_10_resp_bits_level_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_homogeneous (io_ptw_10_resp_bits_homogeneous_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gpa_valid (io_ptw_10_resp_bits_gpa_valid_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gpa_bits (io_ptw_10_resp_bits_gpa_bits_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gpa_is_pte (io_ptw_10_resp_bits_gpa_is_pte_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_ptbr_mode (io_ptw_10_ptbr_mode_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_ptbr_ppn (io_ptw_10_ptbr_ppn_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_debug (io_ptw_10_status_debug_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_cease (io_ptw_10_status_cease_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_wfi (io_ptw_10_status_wfi_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_isa (io_ptw_10_status_isa_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_dprv (io_ptw_10_status_dprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_dv (io_ptw_10_status_dv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_prv (io_ptw_10_status_prv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_v (io_ptw_10_status_v_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mpv (io_ptw_10_status_mpv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_gva (io_ptw_10_status_gva_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_tsr (io_ptw_10_status_tsr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_tw (io_ptw_10_status_tw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_tvm (io_ptw_10_status_tvm_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mxr (io_ptw_10_status_mxr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_sum (io_ptw_10_status_sum_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mprv (io_ptw_10_status_mprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_fs (io_ptw_10_status_fs_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mpp (io_ptw_10_status_mpp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_spp (io_ptw_10_status_spp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mpie (io_ptw_10_status_mpie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_spie (io_ptw_10_status_spie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mie (io_ptw_10_status_mie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_sie (io_ptw_10_status_sie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_hstatus_spvp (io_ptw_10_hstatus_spvp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_hstatus_spv (io_ptw_10_hstatus_spv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_hstatus_gva (io_ptw_10_hstatus_gva_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_debug (io_ptw_10_gstatus_debug_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_cease (io_ptw_10_gstatus_cease_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_wfi (io_ptw_10_gstatus_wfi_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_isa (io_ptw_10_gstatus_isa_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_dprv (io_ptw_10_gstatus_dprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_dv (io_ptw_10_gstatus_dv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_prv (io_ptw_10_gstatus_prv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_v (io_ptw_10_gstatus_v_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_zero2 (io_ptw_10_gstatus_zero2_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mpv (io_ptw_10_gstatus_mpv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_gva (io_ptw_10_gstatus_gva_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mbe (io_ptw_10_gstatus_mbe_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sbe (io_ptw_10_gstatus_sbe_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sxl (io_ptw_10_gstatus_sxl_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_zero1 (io_ptw_10_gstatus_zero1_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_tsr (io_ptw_10_gstatus_tsr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_tw (io_ptw_10_gstatus_tw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_tvm (io_ptw_10_gstatus_tvm_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mxr (io_ptw_10_gstatus_mxr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sum (io_ptw_10_gstatus_sum_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mprv (io_ptw_10_gstatus_mprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_fs (io_ptw_10_gstatus_fs_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mpp (io_ptw_10_gstatus_mpp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_vs (io_ptw_10_gstatus_vs_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_spp (io_ptw_10_gstatus_spp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mpie (io_ptw_10_gstatus_mpie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_ube (io_ptw_10_gstatus_ube_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_spie (io_ptw_10_gstatus_spie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_upie (io_ptw_10_gstatus_upie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mie (io_ptw_10_gstatus_mie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_hie (io_ptw_10_gstatus_hie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sie (io_ptw_10_gstatus_sie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_uie (io_ptw_10_gstatus_uie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_l (io_ptw_10_pmp_0_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_a (io_ptw_10_pmp_0_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_x (io_ptw_10_pmp_0_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_w (io_ptw_10_pmp_0_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_r (io_ptw_10_pmp_0_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_addr (io_ptw_10_pmp_0_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_mask (io_ptw_10_pmp_0_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_l (io_ptw_10_pmp_1_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_a (io_ptw_10_pmp_1_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_x (io_ptw_10_pmp_1_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_w (io_ptw_10_pmp_1_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_r (io_ptw_10_pmp_1_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_addr (io_ptw_10_pmp_1_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_mask (io_ptw_10_pmp_1_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_l (io_ptw_10_pmp_2_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_a (io_ptw_10_pmp_2_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_x (io_ptw_10_pmp_2_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_w (io_ptw_10_pmp_2_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_r (io_ptw_10_pmp_2_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_addr (io_ptw_10_pmp_2_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_mask (io_ptw_10_pmp_2_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_l (io_ptw_10_pmp_3_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_a (io_ptw_10_pmp_3_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_x (io_ptw_10_pmp_3_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_w (io_ptw_10_pmp_3_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_r (io_ptw_10_pmp_3_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_addr (io_ptw_10_pmp_3_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_mask (io_ptw_10_pmp_3_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_l (io_ptw_10_pmp_4_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_a (io_ptw_10_pmp_4_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_x (io_ptw_10_pmp_4_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_w (io_ptw_10_pmp_4_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_r (io_ptw_10_pmp_4_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_addr (io_ptw_10_pmp_4_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_mask (io_ptw_10_pmp_4_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_l (io_ptw_10_pmp_5_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_a (io_ptw_10_pmp_5_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_x (io_ptw_10_pmp_5_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_w (io_ptw_10_pmp_5_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_r (io_ptw_10_pmp_5_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_addr (io_ptw_10_pmp_5_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_mask (io_ptw_10_pmp_5_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_l (io_ptw_10_pmp_6_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_a (io_ptw_10_pmp_6_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_x (io_ptw_10_pmp_6_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_w (io_ptw_10_pmp_6_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_r (io_ptw_10_pmp_6_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_addr (io_ptw_10_pmp_6_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_mask (io_ptw_10_pmp_6_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_l (io_ptw_10_pmp_7_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_a (io_ptw_10_pmp_7_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_x (io_ptw_10_pmp_7_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_w (io_ptw_10_pmp_7_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_r (io_ptw_10_pmp_7_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_addr (io_ptw_10_pmp_7_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_mask (io_ptw_10_pmp_7_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_ren (io_ptw_10_customCSRs_csrs_0_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_wen (io_ptw_10_customCSRs_csrs_0_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_wdata (io_ptw_10_customCSRs_csrs_0_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_value (io_ptw_10_customCSRs_csrs_0_value_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_ren (io_ptw_10_customCSRs_csrs_1_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_wen (io_ptw_10_customCSRs_csrs_1_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_wdata (io_ptw_10_customCSRs_csrs_1_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_value (io_ptw_10_customCSRs_csrs_1_value_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_ren (io_ptw_10_customCSRs_csrs_2_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_wen (io_ptw_10_customCSRs_csrs_2_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_wdata (io_ptw_10_customCSRs_csrs_2_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_value (io_ptw_10_customCSRs_csrs_2_value_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_ren (io_ptw_10_customCSRs_csrs_3_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_wen (io_ptw_10_customCSRs_csrs_3_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_wdata (io_ptw_10_customCSRs_csrs_3_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_value (io_ptw_10_customCSRs_csrs_3_value_0), // @[ZstdCompressor.scala:95:7]
.io_status_valid (_cmd_router_io_dmem_status_out_valid), // @[ZstdCompressor.scala:112:26]
.io_status_bits_debug (_cmd_router_io_dmem_status_out_bits_status_debug), // @[ZstdCompressor.scala:112:26]
.io_status_bits_cease (_cmd_router_io_dmem_status_out_bits_status_cease), // @[ZstdCompressor.scala:112:26]
.io_status_bits_wfi (_cmd_router_io_dmem_status_out_bits_status_wfi), // @[ZstdCompressor.scala:112:26]
.io_status_bits_isa (_cmd_router_io_dmem_status_out_bits_status_isa), // @[ZstdCompressor.scala:112:26]
.io_status_bits_dprv (_cmd_router_io_dmem_status_out_bits_status_dprv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_dv (_cmd_router_io_dmem_status_out_bits_status_dv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_prv (_cmd_router_io_dmem_status_out_bits_status_prv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_v (_cmd_router_io_dmem_status_out_bits_status_v), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sd (_cmd_router_io_dmem_status_out_bits_status_sd), // @[ZstdCompressor.scala:112:26]
.io_status_bits_zero2 (_cmd_router_io_dmem_status_out_bits_status_zero2), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mpv (_cmd_router_io_dmem_status_out_bits_status_mpv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_gva (_cmd_router_io_dmem_status_out_bits_status_gva), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mbe (_cmd_router_io_dmem_status_out_bits_status_mbe), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sbe (_cmd_router_io_dmem_status_out_bits_status_sbe), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sxl (_cmd_router_io_dmem_status_out_bits_status_sxl), // @[ZstdCompressor.scala:112:26]
.io_status_bits_uxl (_cmd_router_io_dmem_status_out_bits_status_uxl), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sd_rv32 (_cmd_router_io_dmem_status_out_bits_status_sd_rv32), // @[ZstdCompressor.scala:112:26]
.io_status_bits_zero1 (_cmd_router_io_dmem_status_out_bits_status_zero1), // @[ZstdCompressor.scala:112:26]
.io_status_bits_tsr (_cmd_router_io_dmem_status_out_bits_status_tsr), // @[ZstdCompressor.scala:112:26]
.io_status_bits_tw (_cmd_router_io_dmem_status_out_bits_status_tw), // @[ZstdCompressor.scala:112:26]
.io_status_bits_tvm (_cmd_router_io_dmem_status_out_bits_status_tvm), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mxr (_cmd_router_io_dmem_status_out_bits_status_mxr), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sum (_cmd_router_io_dmem_status_out_bits_status_sum), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mprv (_cmd_router_io_dmem_status_out_bits_status_mprv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_xs (_cmd_router_io_dmem_status_out_bits_status_xs), // @[ZstdCompressor.scala:112:26]
.io_status_bits_fs (_cmd_router_io_dmem_status_out_bits_status_fs), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mpp (_cmd_router_io_dmem_status_out_bits_status_mpp), // @[ZstdCompressor.scala:112:26]
.io_status_bits_vs (_cmd_router_io_dmem_status_out_bits_status_vs), // @[ZstdCompressor.scala:112:26]
.io_status_bits_spp (_cmd_router_io_dmem_status_out_bits_status_spp), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mpie (_cmd_router_io_dmem_status_out_bits_status_mpie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_ube (_cmd_router_io_dmem_status_out_bits_status_ube), // @[ZstdCompressor.scala:112:26]
.io_status_bits_spie (_cmd_router_io_dmem_status_out_bits_status_spie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_upie (_cmd_router_io_dmem_status_out_bits_status_upie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mie (_cmd_router_io_dmem_status_out_bits_status_mie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_hie (_cmd_router_io_dmem_status_out_bits_status_hie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sie (_cmd_router_io_dmem_status_out_bits_status_sie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_uie (_cmd_router_io_dmem_status_out_bits_status_uie) // @[ZstdCompressor.scala:112:26]
); // @[ZstdCompressor.scala:70:37]
TLWidthWidget32_10 widget_10 ( // @[WidthWidget.scala:230:28]
.clock (clock),
.reset (reset),
.auto_anon_in_a_ready (_widget_10_auto_anon_in_a_ready),
.auto_anon_in_a_valid (_l2_huf_lit_writer_auto_master_out_a_valid), // @[ZstdCompressor.scala:70:37]
.auto_anon_in_a_bits_opcode (_l2_huf_lit_writer_auto_master_out_a_bits_opcode), // @[ZstdCompressor.scala:70:37]
.auto_anon_in_a_bits_param (_l2_huf_lit_writer_auto_master_out_a_bits_param), // @[ZstdCompressor.scala:70:37]
.auto_anon_in_a_bits_size (_l2_huf_lit_writer_auto_master_out_a_bits_size), // @[ZstdCompressor.scala:70:37]
.auto_anon_in_a_bits_source (_l2_huf_lit_writer_auto_master_out_a_bits_source), // @[ZstdCompressor.scala:70:37]
.auto_anon_in_a_bits_address (_l2_huf_lit_writer_auto_master_out_a_bits_address), // @[ZstdCompressor.scala:70:37]
.auto_anon_in_a_bits_mask (_l2_huf_lit_writer_auto_master_out_a_bits_mask), // @[ZstdCompressor.scala:70:37]
.auto_anon_in_a_bits_data (_l2_huf_lit_writer_auto_master_out_a_bits_data), // @[ZstdCompressor.scala:70:37]
.auto_anon_in_a_bits_corrupt (_l2_huf_lit_writer_auto_master_out_a_bits_corrupt), // @[ZstdCompressor.scala:70:37]
.auto_anon_in_d_ready (_l2_huf_lit_writer_auto_master_out_d_ready), // @[ZstdCompressor.scala:70:37]
.auto_anon_in_d_valid (_widget_10_auto_anon_in_d_valid),
.auto_anon_in_d_bits_opcode (_widget_10_auto_anon_in_d_bits_opcode),
.auto_anon_in_d_bits_param (_widget_10_auto_anon_in_d_bits_param),
.auto_anon_in_d_bits_size (_widget_10_auto_anon_in_d_bits_size),
.auto_anon_in_d_bits_source (_widget_10_auto_anon_in_d_bits_source),
.auto_anon_in_d_bits_sink (_widget_10_auto_anon_in_d_bits_sink),
.auto_anon_in_d_bits_denied (_widget_10_auto_anon_in_d_bits_denied),
.auto_anon_in_d_bits_data (_widget_10_auto_anon_in_d_bits_data),
.auto_anon_in_d_bits_corrupt (_widget_10_auto_anon_in_d_bits_corrupt),
.auto_anon_out_a_ready (x1_tlNodeIn_9_a_ready), // @[MixedNode.scala:551:17]
.auto_anon_out_a_valid (x1_tlNodeIn_9_a_valid),
.auto_anon_out_a_bits_opcode (x1_tlNodeIn_9_a_bits_opcode),
.auto_anon_out_a_bits_param (x1_tlNodeIn_9_a_bits_param),
.auto_anon_out_a_bits_size (x1_tlNodeIn_9_a_bits_size),
.auto_anon_out_a_bits_source (x1_tlNodeIn_9_a_bits_source),
.auto_anon_out_a_bits_address (x1_tlNodeIn_9_a_bits_address),
.auto_anon_out_a_bits_mask (x1_tlNodeIn_9_a_bits_mask),
.auto_anon_out_a_bits_data (x1_tlNodeIn_9_a_bits_data),
.auto_anon_out_a_bits_corrupt (x1_tlNodeIn_9_a_bits_corrupt),
.auto_anon_out_d_ready (x1_tlNodeIn_9_d_ready),
.auto_anon_out_d_valid (x1_tlNodeIn_9_d_valid), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_opcode (x1_tlNodeIn_9_d_bits_opcode), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_param (x1_tlNodeIn_9_d_bits_param), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_size (x1_tlNodeIn_9_d_bits_size), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_source (x1_tlNodeIn_9_d_bits_source), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_sink (x1_tlNodeIn_9_d_bits_sink), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_denied (x1_tlNodeIn_9_d_bits_denied), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_data (x1_tlNodeIn_9_d_bits_data), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_corrupt (x1_tlNodeIn_9_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[WidthWidget.scala:230:28]
L2MemHelperLatencyInjection_11 l2_seq_reader ( // @[ZstdCompressor.scala:73:33]
.clock (clock),
.reset (reset),
.auto_master_out_a_ready (_widget_11_auto_anon_in_a_ready), // @[WidthWidget.scala:230:28]
.auto_master_out_a_valid (_l2_seq_reader_auto_master_out_a_valid),
.auto_master_out_a_bits_opcode (_l2_seq_reader_auto_master_out_a_bits_opcode),
.auto_master_out_a_bits_param (_l2_seq_reader_auto_master_out_a_bits_param),
.auto_master_out_a_bits_size (_l2_seq_reader_auto_master_out_a_bits_size),
.auto_master_out_a_bits_source (_l2_seq_reader_auto_master_out_a_bits_source),
.auto_master_out_a_bits_address (_l2_seq_reader_auto_master_out_a_bits_address),
.auto_master_out_a_bits_mask (_l2_seq_reader_auto_master_out_a_bits_mask),
.auto_master_out_a_bits_data (_l2_seq_reader_auto_master_out_a_bits_data),
.auto_master_out_a_bits_corrupt (_l2_seq_reader_auto_master_out_a_bits_corrupt),
.auto_master_out_d_ready (_l2_seq_reader_auto_master_out_d_ready),
.auto_master_out_d_valid (_widget_11_auto_anon_in_d_valid), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_opcode (_widget_11_auto_anon_in_d_bits_opcode), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_param (_widget_11_auto_anon_in_d_bits_param), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_size (_widget_11_auto_anon_in_d_bits_size), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_source (_widget_11_auto_anon_in_d_bits_source), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_sink (_widget_11_auto_anon_in_d_bits_sink), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_denied (_widget_11_auto_anon_in_d_bits_denied), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_data (_widget_11_auto_anon_in_d_bits_data), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_corrupt (_widget_11_auto_anon_in_d_bits_corrupt), // @[WidthWidget.scala:230:28]
.io_userif_req_ready (_l2_seq_reader_io_userif_req_ready),
.io_userif_req_valid (_seq_compressor_io_l2if_seq_reader_req_valid), // @[ZstdCompressor.scala:168:30]
.io_userif_req_bits_addr (_seq_compressor_io_l2if_seq_reader_req_bits_addr), // @[ZstdCompressor.scala:168:30]
.io_userif_req_bits_size (_seq_compressor_io_l2if_seq_reader_req_bits_size), // @[ZstdCompressor.scala:168:30]
.io_userif_req_bits_data (_seq_compressor_io_l2if_seq_reader_req_bits_data), // @[ZstdCompressor.scala:168:30]
.io_userif_req_bits_cmd (_seq_compressor_io_l2if_seq_reader_req_bits_cmd), // @[ZstdCompressor.scala:168:30]
.io_userif_resp_ready (_seq_compressor_io_l2if_seq_reader_resp_ready), // @[ZstdCompressor.scala:168:30]
.io_userif_resp_valid (_l2_seq_reader_io_userif_resp_valid),
.io_userif_resp_bits_data (_l2_seq_reader_io_userif_resp_bits_data),
.io_userif_no_memops_inflight (_l2_seq_reader_io_userif_no_memops_inflight),
.io_latency_inject_cycles (_l2_seq_reader_io_latency_inject_cycles_T), // @[ZstdCompressor.scala:195:61]
.io_sfence (_cmd_router_io_sfence_out), // @[ZstdCompressor.scala:112:26]
.io_ptw_req_ready (io_ptw_11_req_ready_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_req_valid (io_ptw_11_req_valid_0),
.io_ptw_req_bits_bits_addr (io_ptw_11_req_bits_bits_addr_0),
.io_ptw_req_bits_bits_need_gpa (io_ptw_11_req_bits_bits_need_gpa_0),
.io_ptw_resp_valid (io_ptw_11_resp_valid_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_ae_ptw (io_ptw_11_resp_bits_ae_ptw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_ae_final (io_ptw_11_resp_bits_ae_final_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pf (io_ptw_11_resp_bits_pf_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gf (io_ptw_11_resp_bits_gf_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_hr (io_ptw_11_resp_bits_hr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_hw (io_ptw_11_resp_bits_hw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_hx (io_ptw_11_resp_bits_hx_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_reserved_for_future (io_ptw_11_resp_bits_pte_reserved_for_future_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_ppn (io_ptw_11_resp_bits_pte_ppn_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_reserved_for_software (io_ptw_11_resp_bits_pte_reserved_for_software_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_d (io_ptw_11_resp_bits_pte_d_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_a (io_ptw_11_resp_bits_pte_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_g (io_ptw_11_resp_bits_pte_g_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_u (io_ptw_11_resp_bits_pte_u_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_x (io_ptw_11_resp_bits_pte_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_w (io_ptw_11_resp_bits_pte_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_r (io_ptw_11_resp_bits_pte_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_v (io_ptw_11_resp_bits_pte_v_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_level (io_ptw_11_resp_bits_level_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_homogeneous (io_ptw_11_resp_bits_homogeneous_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gpa_valid (io_ptw_11_resp_bits_gpa_valid_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gpa_bits (io_ptw_11_resp_bits_gpa_bits_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gpa_is_pte (io_ptw_11_resp_bits_gpa_is_pte_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_ptbr_mode (io_ptw_11_ptbr_mode_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_ptbr_ppn (io_ptw_11_ptbr_ppn_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_debug (io_ptw_11_status_debug_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_cease (io_ptw_11_status_cease_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_wfi (io_ptw_11_status_wfi_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_isa (io_ptw_11_status_isa_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_dprv (io_ptw_11_status_dprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_dv (io_ptw_11_status_dv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_prv (io_ptw_11_status_prv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_v (io_ptw_11_status_v_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mpv (io_ptw_11_status_mpv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_gva (io_ptw_11_status_gva_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_tsr (io_ptw_11_status_tsr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_tw (io_ptw_11_status_tw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_tvm (io_ptw_11_status_tvm_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mxr (io_ptw_11_status_mxr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_sum (io_ptw_11_status_sum_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mprv (io_ptw_11_status_mprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_fs (io_ptw_11_status_fs_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mpp (io_ptw_11_status_mpp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_spp (io_ptw_11_status_spp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mpie (io_ptw_11_status_mpie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_spie (io_ptw_11_status_spie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mie (io_ptw_11_status_mie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_sie (io_ptw_11_status_sie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_hstatus_spvp (io_ptw_11_hstatus_spvp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_hstatus_spv (io_ptw_11_hstatus_spv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_hstatus_gva (io_ptw_11_hstatus_gva_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_debug (io_ptw_11_gstatus_debug_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_cease (io_ptw_11_gstatus_cease_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_wfi (io_ptw_11_gstatus_wfi_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_isa (io_ptw_11_gstatus_isa_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_dprv (io_ptw_11_gstatus_dprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_dv (io_ptw_11_gstatus_dv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_prv (io_ptw_11_gstatus_prv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_v (io_ptw_11_gstatus_v_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_zero2 (io_ptw_11_gstatus_zero2_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mpv (io_ptw_11_gstatus_mpv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_gva (io_ptw_11_gstatus_gva_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mbe (io_ptw_11_gstatus_mbe_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sbe (io_ptw_11_gstatus_sbe_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sxl (io_ptw_11_gstatus_sxl_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_zero1 (io_ptw_11_gstatus_zero1_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_tsr (io_ptw_11_gstatus_tsr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_tw (io_ptw_11_gstatus_tw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_tvm (io_ptw_11_gstatus_tvm_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mxr (io_ptw_11_gstatus_mxr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sum (io_ptw_11_gstatus_sum_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mprv (io_ptw_11_gstatus_mprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_fs (io_ptw_11_gstatus_fs_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mpp (io_ptw_11_gstatus_mpp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_vs (io_ptw_11_gstatus_vs_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_spp (io_ptw_11_gstatus_spp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mpie (io_ptw_11_gstatus_mpie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_ube (io_ptw_11_gstatus_ube_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_spie (io_ptw_11_gstatus_spie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_upie (io_ptw_11_gstatus_upie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mie (io_ptw_11_gstatus_mie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_hie (io_ptw_11_gstatus_hie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sie (io_ptw_11_gstatus_sie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_uie (io_ptw_11_gstatus_uie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_l (io_ptw_11_pmp_0_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_a (io_ptw_11_pmp_0_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_x (io_ptw_11_pmp_0_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_w (io_ptw_11_pmp_0_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_r (io_ptw_11_pmp_0_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_addr (io_ptw_11_pmp_0_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_mask (io_ptw_11_pmp_0_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_l (io_ptw_11_pmp_1_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_a (io_ptw_11_pmp_1_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_x (io_ptw_11_pmp_1_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_w (io_ptw_11_pmp_1_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_r (io_ptw_11_pmp_1_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_addr (io_ptw_11_pmp_1_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_mask (io_ptw_11_pmp_1_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_l (io_ptw_11_pmp_2_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_a (io_ptw_11_pmp_2_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_x (io_ptw_11_pmp_2_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_w (io_ptw_11_pmp_2_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_r (io_ptw_11_pmp_2_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_addr (io_ptw_11_pmp_2_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_mask (io_ptw_11_pmp_2_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_l (io_ptw_11_pmp_3_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_a (io_ptw_11_pmp_3_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_x (io_ptw_11_pmp_3_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_w (io_ptw_11_pmp_3_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_r (io_ptw_11_pmp_3_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_addr (io_ptw_11_pmp_3_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_mask (io_ptw_11_pmp_3_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_l (io_ptw_11_pmp_4_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_a (io_ptw_11_pmp_4_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_x (io_ptw_11_pmp_4_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_w (io_ptw_11_pmp_4_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_r (io_ptw_11_pmp_4_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_addr (io_ptw_11_pmp_4_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_mask (io_ptw_11_pmp_4_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_l (io_ptw_11_pmp_5_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_a (io_ptw_11_pmp_5_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_x (io_ptw_11_pmp_5_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_w (io_ptw_11_pmp_5_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_r (io_ptw_11_pmp_5_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_addr (io_ptw_11_pmp_5_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_mask (io_ptw_11_pmp_5_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_l (io_ptw_11_pmp_6_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_a (io_ptw_11_pmp_6_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_x (io_ptw_11_pmp_6_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_w (io_ptw_11_pmp_6_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_r (io_ptw_11_pmp_6_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_addr (io_ptw_11_pmp_6_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_mask (io_ptw_11_pmp_6_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_l (io_ptw_11_pmp_7_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_a (io_ptw_11_pmp_7_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_x (io_ptw_11_pmp_7_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_w (io_ptw_11_pmp_7_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_r (io_ptw_11_pmp_7_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_addr (io_ptw_11_pmp_7_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_mask (io_ptw_11_pmp_7_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_ren (io_ptw_11_customCSRs_csrs_0_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_wen (io_ptw_11_customCSRs_csrs_0_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_wdata (io_ptw_11_customCSRs_csrs_0_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_value (io_ptw_11_customCSRs_csrs_0_value_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_ren (io_ptw_11_customCSRs_csrs_1_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_wen (io_ptw_11_customCSRs_csrs_1_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_wdata (io_ptw_11_customCSRs_csrs_1_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_value (io_ptw_11_customCSRs_csrs_1_value_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_ren (io_ptw_11_customCSRs_csrs_2_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_wen (io_ptw_11_customCSRs_csrs_2_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_wdata (io_ptw_11_customCSRs_csrs_2_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_value (io_ptw_11_customCSRs_csrs_2_value_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_ren (io_ptw_11_customCSRs_csrs_3_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_wen (io_ptw_11_customCSRs_csrs_3_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_wdata (io_ptw_11_customCSRs_csrs_3_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_value (io_ptw_11_customCSRs_csrs_3_value_0), // @[ZstdCompressor.scala:95:7]
.io_status_valid (_cmd_router_io_dmem_status_out_valid), // @[ZstdCompressor.scala:112:26]
.io_status_bits_debug (_cmd_router_io_dmem_status_out_bits_status_debug), // @[ZstdCompressor.scala:112:26]
.io_status_bits_cease (_cmd_router_io_dmem_status_out_bits_status_cease), // @[ZstdCompressor.scala:112:26]
.io_status_bits_wfi (_cmd_router_io_dmem_status_out_bits_status_wfi), // @[ZstdCompressor.scala:112:26]
.io_status_bits_isa (_cmd_router_io_dmem_status_out_bits_status_isa), // @[ZstdCompressor.scala:112:26]
.io_status_bits_dprv (_cmd_router_io_dmem_status_out_bits_status_dprv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_dv (_cmd_router_io_dmem_status_out_bits_status_dv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_prv (_cmd_router_io_dmem_status_out_bits_status_prv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_v (_cmd_router_io_dmem_status_out_bits_status_v), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sd (_cmd_router_io_dmem_status_out_bits_status_sd), // @[ZstdCompressor.scala:112:26]
.io_status_bits_zero2 (_cmd_router_io_dmem_status_out_bits_status_zero2), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mpv (_cmd_router_io_dmem_status_out_bits_status_mpv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_gva (_cmd_router_io_dmem_status_out_bits_status_gva), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mbe (_cmd_router_io_dmem_status_out_bits_status_mbe), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sbe (_cmd_router_io_dmem_status_out_bits_status_sbe), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sxl (_cmd_router_io_dmem_status_out_bits_status_sxl), // @[ZstdCompressor.scala:112:26]
.io_status_bits_uxl (_cmd_router_io_dmem_status_out_bits_status_uxl), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sd_rv32 (_cmd_router_io_dmem_status_out_bits_status_sd_rv32), // @[ZstdCompressor.scala:112:26]
.io_status_bits_zero1 (_cmd_router_io_dmem_status_out_bits_status_zero1), // @[ZstdCompressor.scala:112:26]
.io_status_bits_tsr (_cmd_router_io_dmem_status_out_bits_status_tsr), // @[ZstdCompressor.scala:112:26]
.io_status_bits_tw (_cmd_router_io_dmem_status_out_bits_status_tw), // @[ZstdCompressor.scala:112:26]
.io_status_bits_tvm (_cmd_router_io_dmem_status_out_bits_status_tvm), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mxr (_cmd_router_io_dmem_status_out_bits_status_mxr), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sum (_cmd_router_io_dmem_status_out_bits_status_sum), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mprv (_cmd_router_io_dmem_status_out_bits_status_mprv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_xs (_cmd_router_io_dmem_status_out_bits_status_xs), // @[ZstdCompressor.scala:112:26]
.io_status_bits_fs (_cmd_router_io_dmem_status_out_bits_status_fs), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mpp (_cmd_router_io_dmem_status_out_bits_status_mpp), // @[ZstdCompressor.scala:112:26]
.io_status_bits_vs (_cmd_router_io_dmem_status_out_bits_status_vs), // @[ZstdCompressor.scala:112:26]
.io_status_bits_spp (_cmd_router_io_dmem_status_out_bits_status_spp), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mpie (_cmd_router_io_dmem_status_out_bits_status_mpie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_ube (_cmd_router_io_dmem_status_out_bits_status_ube), // @[ZstdCompressor.scala:112:26]
.io_status_bits_spie (_cmd_router_io_dmem_status_out_bits_status_spie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_upie (_cmd_router_io_dmem_status_out_bits_status_upie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mie (_cmd_router_io_dmem_status_out_bits_status_mie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_hie (_cmd_router_io_dmem_status_out_bits_status_hie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sie (_cmd_router_io_dmem_status_out_bits_status_sie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_uie (_cmd_router_io_dmem_status_out_bits_status_uie) // @[ZstdCompressor.scala:112:26]
); // @[ZstdCompressor.scala:73:33]
TLWidthWidget32_11 widget_11 ( // @[WidthWidget.scala:230:28]
.clock (clock),
.reset (reset),
.auto_anon_in_a_ready (_widget_11_auto_anon_in_a_ready),
.auto_anon_in_a_valid (_l2_seq_reader_auto_master_out_a_valid), // @[ZstdCompressor.scala:73:33]
.auto_anon_in_a_bits_opcode (_l2_seq_reader_auto_master_out_a_bits_opcode), // @[ZstdCompressor.scala:73:33]
.auto_anon_in_a_bits_param (_l2_seq_reader_auto_master_out_a_bits_param), // @[ZstdCompressor.scala:73:33]
.auto_anon_in_a_bits_size (_l2_seq_reader_auto_master_out_a_bits_size), // @[ZstdCompressor.scala:73:33]
.auto_anon_in_a_bits_source (_l2_seq_reader_auto_master_out_a_bits_source), // @[ZstdCompressor.scala:73:33]
.auto_anon_in_a_bits_address (_l2_seq_reader_auto_master_out_a_bits_address), // @[ZstdCompressor.scala:73:33]
.auto_anon_in_a_bits_mask (_l2_seq_reader_auto_master_out_a_bits_mask), // @[ZstdCompressor.scala:73:33]
.auto_anon_in_a_bits_data (_l2_seq_reader_auto_master_out_a_bits_data), // @[ZstdCompressor.scala:73:33]
.auto_anon_in_a_bits_corrupt (_l2_seq_reader_auto_master_out_a_bits_corrupt), // @[ZstdCompressor.scala:73:33]
.auto_anon_in_d_ready (_l2_seq_reader_auto_master_out_d_ready), // @[ZstdCompressor.scala:73:33]
.auto_anon_in_d_valid (_widget_11_auto_anon_in_d_valid),
.auto_anon_in_d_bits_opcode (_widget_11_auto_anon_in_d_bits_opcode),
.auto_anon_in_d_bits_param (_widget_11_auto_anon_in_d_bits_param),
.auto_anon_in_d_bits_size (_widget_11_auto_anon_in_d_bits_size),
.auto_anon_in_d_bits_source (_widget_11_auto_anon_in_d_bits_source),
.auto_anon_in_d_bits_sink (_widget_11_auto_anon_in_d_bits_sink),
.auto_anon_in_d_bits_denied (_widget_11_auto_anon_in_d_bits_denied),
.auto_anon_in_d_bits_data (_widget_11_auto_anon_in_d_bits_data),
.auto_anon_in_d_bits_corrupt (_widget_11_auto_anon_in_d_bits_corrupt),
.auto_anon_out_a_ready (x1_tlNodeIn_10_a_ready), // @[MixedNode.scala:551:17]
.auto_anon_out_a_valid (x1_tlNodeIn_10_a_valid),
.auto_anon_out_a_bits_opcode (x1_tlNodeIn_10_a_bits_opcode),
.auto_anon_out_a_bits_param (x1_tlNodeIn_10_a_bits_param),
.auto_anon_out_a_bits_size (x1_tlNodeIn_10_a_bits_size),
.auto_anon_out_a_bits_source (x1_tlNodeIn_10_a_bits_source),
.auto_anon_out_a_bits_address (x1_tlNodeIn_10_a_bits_address),
.auto_anon_out_a_bits_mask (x1_tlNodeIn_10_a_bits_mask),
.auto_anon_out_a_bits_data (x1_tlNodeIn_10_a_bits_data),
.auto_anon_out_a_bits_corrupt (x1_tlNodeIn_10_a_bits_corrupt),
.auto_anon_out_d_ready (x1_tlNodeIn_10_d_ready),
.auto_anon_out_d_valid (x1_tlNodeIn_10_d_valid), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_opcode (x1_tlNodeIn_10_d_bits_opcode), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_param (x1_tlNodeIn_10_d_bits_param), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_size (x1_tlNodeIn_10_d_bits_size), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_source (x1_tlNodeIn_10_d_bits_source), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_sink (x1_tlNodeIn_10_d_bits_sink), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_denied (x1_tlNodeIn_10_d_bits_denied), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_data (x1_tlNodeIn_10_d_bits_data), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_corrupt (x1_tlNodeIn_10_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[WidthWidget.scala:230:28]
L2MemHelperLatencyInjection_12 l2_seq_reader2 ( // @[ZstdCompressor.scala:76:34]
.clock (clock),
.reset (reset),
.auto_master_out_a_ready (_widget_12_auto_anon_in_a_ready), // @[WidthWidget.scala:230:28]
.auto_master_out_a_valid (_l2_seq_reader2_auto_master_out_a_valid),
.auto_master_out_a_bits_opcode (_l2_seq_reader2_auto_master_out_a_bits_opcode),
.auto_master_out_a_bits_param (_l2_seq_reader2_auto_master_out_a_bits_param),
.auto_master_out_a_bits_size (_l2_seq_reader2_auto_master_out_a_bits_size),
.auto_master_out_a_bits_source (_l2_seq_reader2_auto_master_out_a_bits_source),
.auto_master_out_a_bits_address (_l2_seq_reader2_auto_master_out_a_bits_address),
.auto_master_out_a_bits_mask (_l2_seq_reader2_auto_master_out_a_bits_mask),
.auto_master_out_a_bits_data (_l2_seq_reader2_auto_master_out_a_bits_data),
.auto_master_out_a_bits_corrupt (_l2_seq_reader2_auto_master_out_a_bits_corrupt),
.auto_master_out_d_ready (_l2_seq_reader2_auto_master_out_d_ready),
.auto_master_out_d_valid (_widget_12_auto_anon_in_d_valid), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_opcode (_widget_12_auto_anon_in_d_bits_opcode), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_param (_widget_12_auto_anon_in_d_bits_param), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_size (_widget_12_auto_anon_in_d_bits_size), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_source (_widget_12_auto_anon_in_d_bits_source), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_sink (_widget_12_auto_anon_in_d_bits_sink), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_denied (_widget_12_auto_anon_in_d_bits_denied), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_data (_widget_12_auto_anon_in_d_bits_data), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_corrupt (_widget_12_auto_anon_in_d_bits_corrupt), // @[WidthWidget.scala:230:28]
.io_userif_req_ready (_l2_seq_reader2_io_userif_req_ready),
.io_userif_req_valid (_seq_compressor_io_l2if_seq_reader2_req_valid), // @[ZstdCompressor.scala:168:30]
.io_userif_req_bits_addr (_seq_compressor_io_l2if_seq_reader2_req_bits_addr), // @[ZstdCompressor.scala:168:30]
.io_userif_req_bits_size (_seq_compressor_io_l2if_seq_reader2_req_bits_size), // @[ZstdCompressor.scala:168:30]
.io_userif_req_bits_data (_seq_compressor_io_l2if_seq_reader2_req_bits_data), // @[ZstdCompressor.scala:168:30]
.io_userif_req_bits_cmd (_seq_compressor_io_l2if_seq_reader2_req_bits_cmd), // @[ZstdCompressor.scala:168:30]
.io_userif_resp_ready (_seq_compressor_io_l2if_seq_reader2_resp_ready), // @[ZstdCompressor.scala:168:30]
.io_userif_resp_valid (_l2_seq_reader2_io_userif_resp_valid),
.io_userif_resp_bits_data (_l2_seq_reader2_io_userif_resp_bits_data),
.io_userif_no_memops_inflight (_l2_seq_reader2_io_userif_no_memops_inflight),
.io_latency_inject_cycles (_l2_seq_reader2_io_latency_inject_cycles_T), // @[ZstdCompressor.scala:196:62]
.io_sfence (_cmd_router_io_sfence_out), // @[ZstdCompressor.scala:112:26]
.io_ptw_req_ready (io_ptw_12_req_ready_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_req_valid (io_ptw_12_req_valid_0),
.io_ptw_req_bits_bits_addr (io_ptw_12_req_bits_bits_addr_0),
.io_ptw_req_bits_bits_need_gpa (io_ptw_12_req_bits_bits_need_gpa_0),
.io_ptw_resp_valid (io_ptw_12_resp_valid_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_ae_ptw (io_ptw_12_resp_bits_ae_ptw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_ae_final (io_ptw_12_resp_bits_ae_final_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pf (io_ptw_12_resp_bits_pf_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gf (io_ptw_12_resp_bits_gf_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_hr (io_ptw_12_resp_bits_hr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_hw (io_ptw_12_resp_bits_hw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_hx (io_ptw_12_resp_bits_hx_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_reserved_for_future (io_ptw_12_resp_bits_pte_reserved_for_future_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_ppn (io_ptw_12_resp_bits_pte_ppn_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_reserved_for_software (io_ptw_12_resp_bits_pte_reserved_for_software_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_d (io_ptw_12_resp_bits_pte_d_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_a (io_ptw_12_resp_bits_pte_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_g (io_ptw_12_resp_bits_pte_g_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_u (io_ptw_12_resp_bits_pte_u_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_x (io_ptw_12_resp_bits_pte_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_w (io_ptw_12_resp_bits_pte_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_r (io_ptw_12_resp_bits_pte_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_v (io_ptw_12_resp_bits_pte_v_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_level (io_ptw_12_resp_bits_level_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_homogeneous (io_ptw_12_resp_bits_homogeneous_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gpa_valid (io_ptw_12_resp_bits_gpa_valid_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gpa_bits (io_ptw_12_resp_bits_gpa_bits_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gpa_is_pte (io_ptw_12_resp_bits_gpa_is_pte_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_ptbr_mode (io_ptw_12_ptbr_mode_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_ptbr_ppn (io_ptw_12_ptbr_ppn_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_debug (io_ptw_12_status_debug_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_cease (io_ptw_12_status_cease_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_wfi (io_ptw_12_status_wfi_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_isa (io_ptw_12_status_isa_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_dprv (io_ptw_12_status_dprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_dv (io_ptw_12_status_dv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_prv (io_ptw_12_status_prv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_v (io_ptw_12_status_v_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mpv (io_ptw_12_status_mpv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_gva (io_ptw_12_status_gva_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_tsr (io_ptw_12_status_tsr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_tw (io_ptw_12_status_tw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_tvm (io_ptw_12_status_tvm_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mxr (io_ptw_12_status_mxr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_sum (io_ptw_12_status_sum_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mprv (io_ptw_12_status_mprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_fs (io_ptw_12_status_fs_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mpp (io_ptw_12_status_mpp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_spp (io_ptw_12_status_spp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mpie (io_ptw_12_status_mpie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_spie (io_ptw_12_status_spie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mie (io_ptw_12_status_mie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_sie (io_ptw_12_status_sie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_hstatus_spvp (io_ptw_12_hstatus_spvp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_hstatus_spv (io_ptw_12_hstatus_spv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_hstatus_gva (io_ptw_12_hstatus_gva_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_debug (io_ptw_12_gstatus_debug_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_cease (io_ptw_12_gstatus_cease_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_wfi (io_ptw_12_gstatus_wfi_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_isa (io_ptw_12_gstatus_isa_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_dprv (io_ptw_12_gstatus_dprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_dv (io_ptw_12_gstatus_dv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_prv (io_ptw_12_gstatus_prv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_v (io_ptw_12_gstatus_v_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_zero2 (io_ptw_12_gstatus_zero2_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mpv (io_ptw_12_gstatus_mpv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_gva (io_ptw_12_gstatus_gva_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mbe (io_ptw_12_gstatus_mbe_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sbe (io_ptw_12_gstatus_sbe_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sxl (io_ptw_12_gstatus_sxl_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_zero1 (io_ptw_12_gstatus_zero1_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_tsr (io_ptw_12_gstatus_tsr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_tw (io_ptw_12_gstatus_tw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_tvm (io_ptw_12_gstatus_tvm_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mxr (io_ptw_12_gstatus_mxr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sum (io_ptw_12_gstatus_sum_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mprv (io_ptw_12_gstatus_mprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_fs (io_ptw_12_gstatus_fs_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mpp (io_ptw_12_gstatus_mpp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_vs (io_ptw_12_gstatus_vs_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_spp (io_ptw_12_gstatus_spp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mpie (io_ptw_12_gstatus_mpie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_ube (io_ptw_12_gstatus_ube_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_spie (io_ptw_12_gstatus_spie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_upie (io_ptw_12_gstatus_upie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mie (io_ptw_12_gstatus_mie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_hie (io_ptw_12_gstatus_hie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sie (io_ptw_12_gstatus_sie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_uie (io_ptw_12_gstatus_uie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_l (io_ptw_12_pmp_0_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_a (io_ptw_12_pmp_0_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_x (io_ptw_12_pmp_0_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_w (io_ptw_12_pmp_0_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_r (io_ptw_12_pmp_0_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_addr (io_ptw_12_pmp_0_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_mask (io_ptw_12_pmp_0_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_l (io_ptw_12_pmp_1_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_a (io_ptw_12_pmp_1_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_x (io_ptw_12_pmp_1_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_w (io_ptw_12_pmp_1_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_r (io_ptw_12_pmp_1_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_addr (io_ptw_12_pmp_1_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_mask (io_ptw_12_pmp_1_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_l (io_ptw_12_pmp_2_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_a (io_ptw_12_pmp_2_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_x (io_ptw_12_pmp_2_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_w (io_ptw_12_pmp_2_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_r (io_ptw_12_pmp_2_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_addr (io_ptw_12_pmp_2_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_mask (io_ptw_12_pmp_2_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_l (io_ptw_12_pmp_3_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_a (io_ptw_12_pmp_3_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_x (io_ptw_12_pmp_3_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_w (io_ptw_12_pmp_3_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_r (io_ptw_12_pmp_3_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_addr (io_ptw_12_pmp_3_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_mask (io_ptw_12_pmp_3_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_l (io_ptw_12_pmp_4_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_a (io_ptw_12_pmp_4_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_x (io_ptw_12_pmp_4_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_w (io_ptw_12_pmp_4_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_r (io_ptw_12_pmp_4_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_addr (io_ptw_12_pmp_4_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_mask (io_ptw_12_pmp_4_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_l (io_ptw_12_pmp_5_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_a (io_ptw_12_pmp_5_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_x (io_ptw_12_pmp_5_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_w (io_ptw_12_pmp_5_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_r (io_ptw_12_pmp_5_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_addr (io_ptw_12_pmp_5_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_mask (io_ptw_12_pmp_5_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_l (io_ptw_12_pmp_6_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_a (io_ptw_12_pmp_6_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_x (io_ptw_12_pmp_6_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_w (io_ptw_12_pmp_6_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_r (io_ptw_12_pmp_6_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_addr (io_ptw_12_pmp_6_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_mask (io_ptw_12_pmp_6_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_l (io_ptw_12_pmp_7_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_a (io_ptw_12_pmp_7_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_x (io_ptw_12_pmp_7_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_w (io_ptw_12_pmp_7_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_r (io_ptw_12_pmp_7_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_addr (io_ptw_12_pmp_7_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_mask (io_ptw_12_pmp_7_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_ren (io_ptw_12_customCSRs_csrs_0_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_wen (io_ptw_12_customCSRs_csrs_0_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_wdata (io_ptw_12_customCSRs_csrs_0_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_value (io_ptw_12_customCSRs_csrs_0_value_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_ren (io_ptw_12_customCSRs_csrs_1_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_wen (io_ptw_12_customCSRs_csrs_1_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_wdata (io_ptw_12_customCSRs_csrs_1_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_value (io_ptw_12_customCSRs_csrs_1_value_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_ren (io_ptw_12_customCSRs_csrs_2_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_wen (io_ptw_12_customCSRs_csrs_2_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_wdata (io_ptw_12_customCSRs_csrs_2_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_value (io_ptw_12_customCSRs_csrs_2_value_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_ren (io_ptw_12_customCSRs_csrs_3_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_wen (io_ptw_12_customCSRs_csrs_3_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_wdata (io_ptw_12_customCSRs_csrs_3_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_value (io_ptw_12_customCSRs_csrs_3_value_0), // @[ZstdCompressor.scala:95:7]
.io_status_valid (_cmd_router_io_dmem_status_out_valid), // @[ZstdCompressor.scala:112:26]
.io_status_bits_debug (_cmd_router_io_dmem_status_out_bits_status_debug), // @[ZstdCompressor.scala:112:26]
.io_status_bits_cease (_cmd_router_io_dmem_status_out_bits_status_cease), // @[ZstdCompressor.scala:112:26]
.io_status_bits_wfi (_cmd_router_io_dmem_status_out_bits_status_wfi), // @[ZstdCompressor.scala:112:26]
.io_status_bits_isa (_cmd_router_io_dmem_status_out_bits_status_isa), // @[ZstdCompressor.scala:112:26]
.io_status_bits_dprv (_cmd_router_io_dmem_status_out_bits_status_dprv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_dv (_cmd_router_io_dmem_status_out_bits_status_dv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_prv (_cmd_router_io_dmem_status_out_bits_status_prv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_v (_cmd_router_io_dmem_status_out_bits_status_v), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sd (_cmd_router_io_dmem_status_out_bits_status_sd), // @[ZstdCompressor.scala:112:26]
.io_status_bits_zero2 (_cmd_router_io_dmem_status_out_bits_status_zero2), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mpv (_cmd_router_io_dmem_status_out_bits_status_mpv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_gva (_cmd_router_io_dmem_status_out_bits_status_gva), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mbe (_cmd_router_io_dmem_status_out_bits_status_mbe), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sbe (_cmd_router_io_dmem_status_out_bits_status_sbe), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sxl (_cmd_router_io_dmem_status_out_bits_status_sxl), // @[ZstdCompressor.scala:112:26]
.io_status_bits_uxl (_cmd_router_io_dmem_status_out_bits_status_uxl), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sd_rv32 (_cmd_router_io_dmem_status_out_bits_status_sd_rv32), // @[ZstdCompressor.scala:112:26]
.io_status_bits_zero1 (_cmd_router_io_dmem_status_out_bits_status_zero1), // @[ZstdCompressor.scala:112:26]
.io_status_bits_tsr (_cmd_router_io_dmem_status_out_bits_status_tsr), // @[ZstdCompressor.scala:112:26]
.io_status_bits_tw (_cmd_router_io_dmem_status_out_bits_status_tw), // @[ZstdCompressor.scala:112:26]
.io_status_bits_tvm (_cmd_router_io_dmem_status_out_bits_status_tvm), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mxr (_cmd_router_io_dmem_status_out_bits_status_mxr), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sum (_cmd_router_io_dmem_status_out_bits_status_sum), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mprv (_cmd_router_io_dmem_status_out_bits_status_mprv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_xs (_cmd_router_io_dmem_status_out_bits_status_xs), // @[ZstdCompressor.scala:112:26]
.io_status_bits_fs (_cmd_router_io_dmem_status_out_bits_status_fs), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mpp (_cmd_router_io_dmem_status_out_bits_status_mpp), // @[ZstdCompressor.scala:112:26]
.io_status_bits_vs (_cmd_router_io_dmem_status_out_bits_status_vs), // @[ZstdCompressor.scala:112:26]
.io_status_bits_spp (_cmd_router_io_dmem_status_out_bits_status_spp), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mpie (_cmd_router_io_dmem_status_out_bits_status_mpie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_ube (_cmd_router_io_dmem_status_out_bits_status_ube), // @[ZstdCompressor.scala:112:26]
.io_status_bits_spie (_cmd_router_io_dmem_status_out_bits_status_spie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_upie (_cmd_router_io_dmem_status_out_bits_status_upie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mie (_cmd_router_io_dmem_status_out_bits_status_mie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_hie (_cmd_router_io_dmem_status_out_bits_status_hie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sie (_cmd_router_io_dmem_status_out_bits_status_sie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_uie (_cmd_router_io_dmem_status_out_bits_status_uie) // @[ZstdCompressor.scala:112:26]
); // @[ZstdCompressor.scala:76:34]
TLWidthWidget32_12 widget_12 ( // @[WidthWidget.scala:230:28]
.clock (clock),
.reset (reset),
.auto_anon_in_a_ready (_widget_12_auto_anon_in_a_ready),
.auto_anon_in_a_valid (_l2_seq_reader2_auto_master_out_a_valid), // @[ZstdCompressor.scala:76:34]
.auto_anon_in_a_bits_opcode (_l2_seq_reader2_auto_master_out_a_bits_opcode), // @[ZstdCompressor.scala:76:34]
.auto_anon_in_a_bits_param (_l2_seq_reader2_auto_master_out_a_bits_param), // @[ZstdCompressor.scala:76:34]
.auto_anon_in_a_bits_size (_l2_seq_reader2_auto_master_out_a_bits_size), // @[ZstdCompressor.scala:76:34]
.auto_anon_in_a_bits_source (_l2_seq_reader2_auto_master_out_a_bits_source), // @[ZstdCompressor.scala:76:34]
.auto_anon_in_a_bits_address (_l2_seq_reader2_auto_master_out_a_bits_address), // @[ZstdCompressor.scala:76:34]
.auto_anon_in_a_bits_mask (_l2_seq_reader2_auto_master_out_a_bits_mask), // @[ZstdCompressor.scala:76:34]
.auto_anon_in_a_bits_data (_l2_seq_reader2_auto_master_out_a_bits_data), // @[ZstdCompressor.scala:76:34]
.auto_anon_in_a_bits_corrupt (_l2_seq_reader2_auto_master_out_a_bits_corrupt), // @[ZstdCompressor.scala:76:34]
.auto_anon_in_d_ready (_l2_seq_reader2_auto_master_out_d_ready), // @[ZstdCompressor.scala:76:34]
.auto_anon_in_d_valid (_widget_12_auto_anon_in_d_valid),
.auto_anon_in_d_bits_opcode (_widget_12_auto_anon_in_d_bits_opcode),
.auto_anon_in_d_bits_param (_widget_12_auto_anon_in_d_bits_param),
.auto_anon_in_d_bits_size (_widget_12_auto_anon_in_d_bits_size),
.auto_anon_in_d_bits_source (_widget_12_auto_anon_in_d_bits_source),
.auto_anon_in_d_bits_sink (_widget_12_auto_anon_in_d_bits_sink),
.auto_anon_in_d_bits_denied (_widget_12_auto_anon_in_d_bits_denied),
.auto_anon_in_d_bits_data (_widget_12_auto_anon_in_d_bits_data),
.auto_anon_in_d_bits_corrupt (_widget_12_auto_anon_in_d_bits_corrupt),
.auto_anon_out_a_ready (x1_tlNodeIn_11_a_ready), // @[MixedNode.scala:551:17]
.auto_anon_out_a_valid (x1_tlNodeIn_11_a_valid),
.auto_anon_out_a_bits_opcode (x1_tlNodeIn_11_a_bits_opcode),
.auto_anon_out_a_bits_param (x1_tlNodeIn_11_a_bits_param),
.auto_anon_out_a_bits_size (x1_tlNodeIn_11_a_bits_size),
.auto_anon_out_a_bits_source (x1_tlNodeIn_11_a_bits_source),
.auto_anon_out_a_bits_address (x1_tlNodeIn_11_a_bits_address),
.auto_anon_out_a_bits_mask (x1_tlNodeIn_11_a_bits_mask),
.auto_anon_out_a_bits_data (x1_tlNodeIn_11_a_bits_data),
.auto_anon_out_a_bits_corrupt (x1_tlNodeIn_11_a_bits_corrupt),
.auto_anon_out_d_ready (x1_tlNodeIn_11_d_ready),
.auto_anon_out_d_valid (x1_tlNodeIn_11_d_valid), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_opcode (x1_tlNodeIn_11_d_bits_opcode), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_param (x1_tlNodeIn_11_d_bits_param), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_size (x1_tlNodeIn_11_d_bits_size), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_source (x1_tlNodeIn_11_d_bits_source), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_sink (x1_tlNodeIn_11_d_bits_sink), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_denied (x1_tlNodeIn_11_d_bits_denied), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_data (x1_tlNodeIn_11_d_bits_data), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_corrupt (x1_tlNodeIn_11_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[WidthWidget.scala:230:28]
L2MemHelperLatencyInjection_13 l2_seq_writer ( // @[ZstdCompressor.scala:79:33]
.clock (clock),
.reset (reset),
.auto_master_out_a_ready (_widget_13_auto_anon_in_a_ready), // @[WidthWidget.scala:230:28]
.auto_master_out_a_valid (_l2_seq_writer_auto_master_out_a_valid),
.auto_master_out_a_bits_opcode (_l2_seq_writer_auto_master_out_a_bits_opcode),
.auto_master_out_a_bits_param (_l2_seq_writer_auto_master_out_a_bits_param),
.auto_master_out_a_bits_size (_l2_seq_writer_auto_master_out_a_bits_size),
.auto_master_out_a_bits_source (_l2_seq_writer_auto_master_out_a_bits_source),
.auto_master_out_a_bits_address (_l2_seq_writer_auto_master_out_a_bits_address),
.auto_master_out_a_bits_mask (_l2_seq_writer_auto_master_out_a_bits_mask),
.auto_master_out_a_bits_data (_l2_seq_writer_auto_master_out_a_bits_data),
.auto_master_out_a_bits_corrupt (_l2_seq_writer_auto_master_out_a_bits_corrupt),
.auto_master_out_d_ready (_l2_seq_writer_auto_master_out_d_ready),
.auto_master_out_d_valid (_widget_13_auto_anon_in_d_valid), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_opcode (_widget_13_auto_anon_in_d_bits_opcode), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_param (_widget_13_auto_anon_in_d_bits_param), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_size (_widget_13_auto_anon_in_d_bits_size), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_source (_widget_13_auto_anon_in_d_bits_source), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_sink (_widget_13_auto_anon_in_d_bits_sink), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_denied (_widget_13_auto_anon_in_d_bits_denied), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_data (_widget_13_auto_anon_in_d_bits_data), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_corrupt (_widget_13_auto_anon_in_d_bits_corrupt), // @[WidthWidget.scala:230:28]
.io_userif_req_ready (_l2_seq_writer_io_userif_req_ready),
.io_userif_req_valid (_seq_compressor_io_l2if_seq_writer_req_valid), // @[ZstdCompressor.scala:168:30]
.io_userif_req_bits_addr (_seq_compressor_io_l2if_seq_writer_req_bits_addr), // @[ZstdCompressor.scala:168:30]
.io_userif_req_bits_size (_seq_compressor_io_l2if_seq_writer_req_bits_size), // @[ZstdCompressor.scala:168:30]
.io_userif_req_bits_data (_seq_compressor_io_l2if_seq_writer_req_bits_data), // @[ZstdCompressor.scala:168:30]
.io_userif_req_bits_cmd (_seq_compressor_io_l2if_seq_writer_req_bits_cmd), // @[ZstdCompressor.scala:168:30]
.io_userif_resp_ready (_seq_compressor_io_l2if_seq_writer_resp_ready), // @[ZstdCompressor.scala:168:30]
.io_userif_resp_valid (_l2_seq_writer_io_userif_resp_valid),
.io_userif_resp_bits_data (_l2_seq_writer_io_userif_resp_bits_data),
.io_userif_no_memops_inflight (_l2_seq_writer_io_userif_no_memops_inflight),
.io_latency_inject_cycles (_cmd_router_io_LATENCY_INJECTION_CYCLES), // @[ZstdCompressor.scala:112:26]
.io_sfence (_cmd_router_io_sfence_out), // @[ZstdCompressor.scala:112:26]
.io_ptw_req_ready (io_ptw_13_req_ready_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_req_valid (io_ptw_13_req_valid_0),
.io_ptw_req_bits_bits_addr (io_ptw_13_req_bits_bits_addr_0),
.io_ptw_req_bits_bits_need_gpa (io_ptw_13_req_bits_bits_need_gpa_0),
.io_ptw_resp_valid (io_ptw_13_resp_valid_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_ae_ptw (io_ptw_13_resp_bits_ae_ptw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_ae_final (io_ptw_13_resp_bits_ae_final_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pf (io_ptw_13_resp_bits_pf_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gf (io_ptw_13_resp_bits_gf_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_hr (io_ptw_13_resp_bits_hr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_hw (io_ptw_13_resp_bits_hw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_hx (io_ptw_13_resp_bits_hx_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_reserved_for_future (io_ptw_13_resp_bits_pte_reserved_for_future_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_ppn (io_ptw_13_resp_bits_pte_ppn_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_reserved_for_software (io_ptw_13_resp_bits_pte_reserved_for_software_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_d (io_ptw_13_resp_bits_pte_d_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_a (io_ptw_13_resp_bits_pte_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_g (io_ptw_13_resp_bits_pte_g_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_u (io_ptw_13_resp_bits_pte_u_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_x (io_ptw_13_resp_bits_pte_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_w (io_ptw_13_resp_bits_pte_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_r (io_ptw_13_resp_bits_pte_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_v (io_ptw_13_resp_bits_pte_v_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_level (io_ptw_13_resp_bits_level_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_homogeneous (io_ptw_13_resp_bits_homogeneous_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gpa_valid (io_ptw_13_resp_bits_gpa_valid_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gpa_bits (io_ptw_13_resp_bits_gpa_bits_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gpa_is_pte (io_ptw_13_resp_bits_gpa_is_pte_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_ptbr_mode (io_ptw_13_ptbr_mode_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_ptbr_ppn (io_ptw_13_ptbr_ppn_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_debug (io_ptw_13_status_debug_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_cease (io_ptw_13_status_cease_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_wfi (io_ptw_13_status_wfi_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_isa (io_ptw_13_status_isa_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_dprv (io_ptw_13_status_dprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_dv (io_ptw_13_status_dv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_prv (io_ptw_13_status_prv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_v (io_ptw_13_status_v_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mpv (io_ptw_13_status_mpv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_gva (io_ptw_13_status_gva_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_tsr (io_ptw_13_status_tsr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_tw (io_ptw_13_status_tw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_tvm (io_ptw_13_status_tvm_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mxr (io_ptw_13_status_mxr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_sum (io_ptw_13_status_sum_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mprv (io_ptw_13_status_mprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_fs (io_ptw_13_status_fs_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mpp (io_ptw_13_status_mpp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_spp (io_ptw_13_status_spp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mpie (io_ptw_13_status_mpie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_spie (io_ptw_13_status_spie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mie (io_ptw_13_status_mie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_sie (io_ptw_13_status_sie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_hstatus_spvp (io_ptw_13_hstatus_spvp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_hstatus_spv (io_ptw_13_hstatus_spv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_hstatus_gva (io_ptw_13_hstatus_gva_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_debug (io_ptw_13_gstatus_debug_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_cease (io_ptw_13_gstatus_cease_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_wfi (io_ptw_13_gstatus_wfi_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_isa (io_ptw_13_gstatus_isa_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_dprv (io_ptw_13_gstatus_dprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_dv (io_ptw_13_gstatus_dv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_prv (io_ptw_13_gstatus_prv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_v (io_ptw_13_gstatus_v_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_zero2 (io_ptw_13_gstatus_zero2_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mpv (io_ptw_13_gstatus_mpv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_gva (io_ptw_13_gstatus_gva_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mbe (io_ptw_13_gstatus_mbe_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sbe (io_ptw_13_gstatus_sbe_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sxl (io_ptw_13_gstatus_sxl_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_zero1 (io_ptw_13_gstatus_zero1_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_tsr (io_ptw_13_gstatus_tsr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_tw (io_ptw_13_gstatus_tw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_tvm (io_ptw_13_gstatus_tvm_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mxr (io_ptw_13_gstatus_mxr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sum (io_ptw_13_gstatus_sum_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mprv (io_ptw_13_gstatus_mprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_fs (io_ptw_13_gstatus_fs_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mpp (io_ptw_13_gstatus_mpp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_vs (io_ptw_13_gstatus_vs_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_spp (io_ptw_13_gstatus_spp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mpie (io_ptw_13_gstatus_mpie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_ube (io_ptw_13_gstatus_ube_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_spie (io_ptw_13_gstatus_spie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_upie (io_ptw_13_gstatus_upie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mie (io_ptw_13_gstatus_mie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_hie (io_ptw_13_gstatus_hie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sie (io_ptw_13_gstatus_sie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_uie (io_ptw_13_gstatus_uie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_l (io_ptw_13_pmp_0_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_a (io_ptw_13_pmp_0_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_x (io_ptw_13_pmp_0_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_w (io_ptw_13_pmp_0_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_r (io_ptw_13_pmp_0_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_addr (io_ptw_13_pmp_0_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_mask (io_ptw_13_pmp_0_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_l (io_ptw_13_pmp_1_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_a (io_ptw_13_pmp_1_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_x (io_ptw_13_pmp_1_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_w (io_ptw_13_pmp_1_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_r (io_ptw_13_pmp_1_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_addr (io_ptw_13_pmp_1_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_mask (io_ptw_13_pmp_1_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_l (io_ptw_13_pmp_2_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_a (io_ptw_13_pmp_2_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_x (io_ptw_13_pmp_2_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_w (io_ptw_13_pmp_2_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_r (io_ptw_13_pmp_2_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_addr (io_ptw_13_pmp_2_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_mask (io_ptw_13_pmp_2_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_l (io_ptw_13_pmp_3_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_a (io_ptw_13_pmp_3_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_x (io_ptw_13_pmp_3_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_w (io_ptw_13_pmp_3_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_r (io_ptw_13_pmp_3_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_addr (io_ptw_13_pmp_3_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_mask (io_ptw_13_pmp_3_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_l (io_ptw_13_pmp_4_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_a (io_ptw_13_pmp_4_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_x (io_ptw_13_pmp_4_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_w (io_ptw_13_pmp_4_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_r (io_ptw_13_pmp_4_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_addr (io_ptw_13_pmp_4_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_mask (io_ptw_13_pmp_4_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_l (io_ptw_13_pmp_5_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_a (io_ptw_13_pmp_5_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_x (io_ptw_13_pmp_5_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_w (io_ptw_13_pmp_5_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_r (io_ptw_13_pmp_5_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_addr (io_ptw_13_pmp_5_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_mask (io_ptw_13_pmp_5_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_l (io_ptw_13_pmp_6_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_a (io_ptw_13_pmp_6_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_x (io_ptw_13_pmp_6_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_w (io_ptw_13_pmp_6_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_r (io_ptw_13_pmp_6_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_addr (io_ptw_13_pmp_6_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_mask (io_ptw_13_pmp_6_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_l (io_ptw_13_pmp_7_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_a (io_ptw_13_pmp_7_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_x (io_ptw_13_pmp_7_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_w (io_ptw_13_pmp_7_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_r (io_ptw_13_pmp_7_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_addr (io_ptw_13_pmp_7_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_mask (io_ptw_13_pmp_7_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_ren (io_ptw_13_customCSRs_csrs_0_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_wen (io_ptw_13_customCSRs_csrs_0_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_wdata (io_ptw_13_customCSRs_csrs_0_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_value (io_ptw_13_customCSRs_csrs_0_value_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_ren (io_ptw_13_customCSRs_csrs_1_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_wen (io_ptw_13_customCSRs_csrs_1_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_wdata (io_ptw_13_customCSRs_csrs_1_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_value (io_ptw_13_customCSRs_csrs_1_value_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_ren (io_ptw_13_customCSRs_csrs_2_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_wen (io_ptw_13_customCSRs_csrs_2_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_wdata (io_ptw_13_customCSRs_csrs_2_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_value (io_ptw_13_customCSRs_csrs_2_value_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_ren (io_ptw_13_customCSRs_csrs_3_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_wen (io_ptw_13_customCSRs_csrs_3_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_wdata (io_ptw_13_customCSRs_csrs_3_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_value (io_ptw_13_customCSRs_csrs_3_value_0), // @[ZstdCompressor.scala:95:7]
.io_status_valid (_cmd_router_io_dmem_status_out_valid), // @[ZstdCompressor.scala:112:26]
.io_status_bits_debug (_cmd_router_io_dmem_status_out_bits_status_debug), // @[ZstdCompressor.scala:112:26]
.io_status_bits_cease (_cmd_router_io_dmem_status_out_bits_status_cease), // @[ZstdCompressor.scala:112:26]
.io_status_bits_wfi (_cmd_router_io_dmem_status_out_bits_status_wfi), // @[ZstdCompressor.scala:112:26]
.io_status_bits_isa (_cmd_router_io_dmem_status_out_bits_status_isa), // @[ZstdCompressor.scala:112:26]
.io_status_bits_dprv (_cmd_router_io_dmem_status_out_bits_status_dprv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_dv (_cmd_router_io_dmem_status_out_bits_status_dv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_prv (_cmd_router_io_dmem_status_out_bits_status_prv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_v (_cmd_router_io_dmem_status_out_bits_status_v), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sd (_cmd_router_io_dmem_status_out_bits_status_sd), // @[ZstdCompressor.scala:112:26]
.io_status_bits_zero2 (_cmd_router_io_dmem_status_out_bits_status_zero2), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mpv (_cmd_router_io_dmem_status_out_bits_status_mpv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_gva (_cmd_router_io_dmem_status_out_bits_status_gva), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mbe (_cmd_router_io_dmem_status_out_bits_status_mbe), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sbe (_cmd_router_io_dmem_status_out_bits_status_sbe), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sxl (_cmd_router_io_dmem_status_out_bits_status_sxl), // @[ZstdCompressor.scala:112:26]
.io_status_bits_uxl (_cmd_router_io_dmem_status_out_bits_status_uxl), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sd_rv32 (_cmd_router_io_dmem_status_out_bits_status_sd_rv32), // @[ZstdCompressor.scala:112:26]
.io_status_bits_zero1 (_cmd_router_io_dmem_status_out_bits_status_zero1), // @[ZstdCompressor.scala:112:26]
.io_status_bits_tsr (_cmd_router_io_dmem_status_out_bits_status_tsr), // @[ZstdCompressor.scala:112:26]
.io_status_bits_tw (_cmd_router_io_dmem_status_out_bits_status_tw), // @[ZstdCompressor.scala:112:26]
.io_status_bits_tvm (_cmd_router_io_dmem_status_out_bits_status_tvm), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mxr (_cmd_router_io_dmem_status_out_bits_status_mxr), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sum (_cmd_router_io_dmem_status_out_bits_status_sum), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mprv (_cmd_router_io_dmem_status_out_bits_status_mprv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_xs (_cmd_router_io_dmem_status_out_bits_status_xs), // @[ZstdCompressor.scala:112:26]
.io_status_bits_fs (_cmd_router_io_dmem_status_out_bits_status_fs), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mpp (_cmd_router_io_dmem_status_out_bits_status_mpp), // @[ZstdCompressor.scala:112:26]
.io_status_bits_vs (_cmd_router_io_dmem_status_out_bits_status_vs), // @[ZstdCompressor.scala:112:26]
.io_status_bits_spp (_cmd_router_io_dmem_status_out_bits_status_spp), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mpie (_cmd_router_io_dmem_status_out_bits_status_mpie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_ube (_cmd_router_io_dmem_status_out_bits_status_ube), // @[ZstdCompressor.scala:112:26]
.io_status_bits_spie (_cmd_router_io_dmem_status_out_bits_status_spie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_upie (_cmd_router_io_dmem_status_out_bits_status_upie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mie (_cmd_router_io_dmem_status_out_bits_status_mie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_hie (_cmd_router_io_dmem_status_out_bits_status_hie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sie (_cmd_router_io_dmem_status_out_bits_status_sie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_uie (_cmd_router_io_dmem_status_out_bits_status_uie) // @[ZstdCompressor.scala:112:26]
); // @[ZstdCompressor.scala:79:33]
TLWidthWidget32_13 widget_13 ( // @[WidthWidget.scala:230:28]
.clock (clock),
.reset (reset),
.auto_anon_in_a_ready (_widget_13_auto_anon_in_a_ready),
.auto_anon_in_a_valid (_l2_seq_writer_auto_master_out_a_valid), // @[ZstdCompressor.scala:79:33]
.auto_anon_in_a_bits_opcode (_l2_seq_writer_auto_master_out_a_bits_opcode), // @[ZstdCompressor.scala:79:33]
.auto_anon_in_a_bits_param (_l2_seq_writer_auto_master_out_a_bits_param), // @[ZstdCompressor.scala:79:33]
.auto_anon_in_a_bits_size (_l2_seq_writer_auto_master_out_a_bits_size), // @[ZstdCompressor.scala:79:33]
.auto_anon_in_a_bits_source (_l2_seq_writer_auto_master_out_a_bits_source), // @[ZstdCompressor.scala:79:33]
.auto_anon_in_a_bits_address (_l2_seq_writer_auto_master_out_a_bits_address), // @[ZstdCompressor.scala:79:33]
.auto_anon_in_a_bits_mask (_l2_seq_writer_auto_master_out_a_bits_mask), // @[ZstdCompressor.scala:79:33]
.auto_anon_in_a_bits_data (_l2_seq_writer_auto_master_out_a_bits_data), // @[ZstdCompressor.scala:79:33]
.auto_anon_in_a_bits_corrupt (_l2_seq_writer_auto_master_out_a_bits_corrupt), // @[ZstdCompressor.scala:79:33]
.auto_anon_in_d_ready (_l2_seq_writer_auto_master_out_d_ready), // @[ZstdCompressor.scala:79:33]
.auto_anon_in_d_valid (_widget_13_auto_anon_in_d_valid),
.auto_anon_in_d_bits_opcode (_widget_13_auto_anon_in_d_bits_opcode),
.auto_anon_in_d_bits_param (_widget_13_auto_anon_in_d_bits_param),
.auto_anon_in_d_bits_size (_widget_13_auto_anon_in_d_bits_size),
.auto_anon_in_d_bits_source (_widget_13_auto_anon_in_d_bits_source),
.auto_anon_in_d_bits_sink (_widget_13_auto_anon_in_d_bits_sink),
.auto_anon_in_d_bits_denied (_widget_13_auto_anon_in_d_bits_denied),
.auto_anon_in_d_bits_data (_widget_13_auto_anon_in_d_bits_data),
.auto_anon_in_d_bits_corrupt (_widget_13_auto_anon_in_d_bits_corrupt),
.auto_anon_out_a_ready (x1_tlNodeIn_12_a_ready), // @[MixedNode.scala:551:17]
.auto_anon_out_a_valid (x1_tlNodeIn_12_a_valid),
.auto_anon_out_a_bits_opcode (x1_tlNodeIn_12_a_bits_opcode),
.auto_anon_out_a_bits_param (x1_tlNodeIn_12_a_bits_param),
.auto_anon_out_a_bits_size (x1_tlNodeIn_12_a_bits_size),
.auto_anon_out_a_bits_source (x1_tlNodeIn_12_a_bits_source),
.auto_anon_out_a_bits_address (x1_tlNodeIn_12_a_bits_address),
.auto_anon_out_a_bits_mask (x1_tlNodeIn_12_a_bits_mask),
.auto_anon_out_a_bits_data (x1_tlNodeIn_12_a_bits_data),
.auto_anon_out_a_bits_corrupt (x1_tlNodeIn_12_a_bits_corrupt),
.auto_anon_out_d_ready (x1_tlNodeIn_12_d_ready),
.auto_anon_out_d_valid (x1_tlNodeIn_12_d_valid), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_opcode (x1_tlNodeIn_12_d_bits_opcode), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_param (x1_tlNodeIn_12_d_bits_param), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_size (x1_tlNodeIn_12_d_bits_size), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_source (x1_tlNodeIn_12_d_bits_source), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_sink (x1_tlNodeIn_12_d_bits_sink), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_denied (x1_tlNodeIn_12_d_bits_denied), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_data (x1_tlNodeIn_12_d_bits_data), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_corrupt (x1_tlNodeIn_12_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[WidthWidget.scala:230:28]
L2MemHelperLatencyInjection_14 l2_raw_block_reader ( // @[ZstdCompressor.scala:82:39]
.clock (clock),
.reset (reset),
.auto_master_out_a_ready (_widget_14_auto_anon_in_a_ready), // @[WidthWidget.scala:230:28]
.auto_master_out_a_valid (_l2_raw_block_reader_auto_master_out_a_valid),
.auto_master_out_a_bits_opcode (_l2_raw_block_reader_auto_master_out_a_bits_opcode),
.auto_master_out_a_bits_param (_l2_raw_block_reader_auto_master_out_a_bits_param),
.auto_master_out_a_bits_size (_l2_raw_block_reader_auto_master_out_a_bits_size),
.auto_master_out_a_bits_source (_l2_raw_block_reader_auto_master_out_a_bits_source),
.auto_master_out_a_bits_address (_l2_raw_block_reader_auto_master_out_a_bits_address),
.auto_master_out_a_bits_mask (_l2_raw_block_reader_auto_master_out_a_bits_mask),
.auto_master_out_a_bits_data (_l2_raw_block_reader_auto_master_out_a_bits_data),
.auto_master_out_a_bits_corrupt (_l2_raw_block_reader_auto_master_out_a_bits_corrupt),
.auto_master_out_d_ready (_l2_raw_block_reader_auto_master_out_d_ready),
.auto_master_out_d_valid (_widget_14_auto_anon_in_d_valid), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_opcode (_widget_14_auto_anon_in_d_bits_opcode), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_param (_widget_14_auto_anon_in_d_bits_param), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_size (_widget_14_auto_anon_in_d_bits_size), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_source (_widget_14_auto_anon_in_d_bits_source), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_sink (_widget_14_auto_anon_in_d_bits_sink), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_denied (_widget_14_auto_anon_in_d_bits_denied), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_data (_widget_14_auto_anon_in_d_bits_data), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_corrupt (_widget_14_auto_anon_in_d_bits_corrupt), // @[WidthWidget.scala:230:28]
.io_userif_req_ready (_l2_raw_block_reader_io_userif_req_ready),
.io_userif_req_valid (_raw_block_encoder_io_l2if_reader_req_valid), // @[ZstdCompressor.scala:161:33]
.io_userif_req_bits_addr (_raw_block_encoder_io_l2if_reader_req_bits_addr), // @[ZstdCompressor.scala:161:33]
.io_userif_resp_ready (_raw_block_encoder_io_l2if_reader_resp_ready), // @[ZstdCompressor.scala:161:33]
.io_userif_resp_valid (_l2_raw_block_reader_io_userif_resp_valid),
.io_userif_resp_bits_data (_l2_raw_block_reader_io_userif_resp_bits_data),
.io_userif_no_memops_inflight (_l2_raw_block_reader_io_userif_no_memops_inflight),
.io_latency_inject_cycles (_l2_raw_block_reader_io_latency_inject_cycles_T), // @[ZstdCompressor.scala:199:67]
.io_sfence (_cmd_router_io_sfence_out), // @[ZstdCompressor.scala:112:26]
.io_ptw_req_ready (io_ptw_14_req_ready_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_req_valid (io_ptw_14_req_valid_0),
.io_ptw_req_bits_bits_addr (io_ptw_14_req_bits_bits_addr_0),
.io_ptw_req_bits_bits_need_gpa (io_ptw_14_req_bits_bits_need_gpa_0),
.io_ptw_resp_valid (io_ptw_14_resp_valid_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_ae_ptw (io_ptw_14_resp_bits_ae_ptw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_ae_final (io_ptw_14_resp_bits_ae_final_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pf (io_ptw_14_resp_bits_pf_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gf (io_ptw_14_resp_bits_gf_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_hr (io_ptw_14_resp_bits_hr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_hw (io_ptw_14_resp_bits_hw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_hx (io_ptw_14_resp_bits_hx_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_reserved_for_future (io_ptw_14_resp_bits_pte_reserved_for_future_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_ppn (io_ptw_14_resp_bits_pte_ppn_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_reserved_for_software (io_ptw_14_resp_bits_pte_reserved_for_software_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_d (io_ptw_14_resp_bits_pte_d_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_a (io_ptw_14_resp_bits_pte_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_g (io_ptw_14_resp_bits_pte_g_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_u (io_ptw_14_resp_bits_pte_u_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_x (io_ptw_14_resp_bits_pte_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_w (io_ptw_14_resp_bits_pte_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_r (io_ptw_14_resp_bits_pte_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_v (io_ptw_14_resp_bits_pte_v_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_level (io_ptw_14_resp_bits_level_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_homogeneous (io_ptw_14_resp_bits_homogeneous_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gpa_valid (io_ptw_14_resp_bits_gpa_valid_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gpa_bits (io_ptw_14_resp_bits_gpa_bits_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gpa_is_pte (io_ptw_14_resp_bits_gpa_is_pte_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_ptbr_mode (io_ptw_14_ptbr_mode_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_ptbr_ppn (io_ptw_14_ptbr_ppn_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_debug (io_ptw_14_status_debug_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_cease (io_ptw_14_status_cease_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_wfi (io_ptw_14_status_wfi_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_isa (io_ptw_14_status_isa_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_dprv (io_ptw_14_status_dprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_dv (io_ptw_14_status_dv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_prv (io_ptw_14_status_prv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_v (io_ptw_14_status_v_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mpv (io_ptw_14_status_mpv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_gva (io_ptw_14_status_gva_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_tsr (io_ptw_14_status_tsr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_tw (io_ptw_14_status_tw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_tvm (io_ptw_14_status_tvm_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mxr (io_ptw_14_status_mxr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_sum (io_ptw_14_status_sum_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mprv (io_ptw_14_status_mprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_fs (io_ptw_14_status_fs_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mpp (io_ptw_14_status_mpp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_spp (io_ptw_14_status_spp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mpie (io_ptw_14_status_mpie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_spie (io_ptw_14_status_spie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mie (io_ptw_14_status_mie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_sie (io_ptw_14_status_sie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_hstatus_spvp (io_ptw_14_hstatus_spvp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_hstatus_spv (io_ptw_14_hstatus_spv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_hstatus_gva (io_ptw_14_hstatus_gva_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_debug (io_ptw_14_gstatus_debug_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_cease (io_ptw_14_gstatus_cease_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_wfi (io_ptw_14_gstatus_wfi_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_isa (io_ptw_14_gstatus_isa_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_dprv (io_ptw_14_gstatus_dprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_dv (io_ptw_14_gstatus_dv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_prv (io_ptw_14_gstatus_prv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_v (io_ptw_14_gstatus_v_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_zero2 (io_ptw_14_gstatus_zero2_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mpv (io_ptw_14_gstatus_mpv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_gva (io_ptw_14_gstatus_gva_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mbe (io_ptw_14_gstatus_mbe_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sbe (io_ptw_14_gstatus_sbe_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sxl (io_ptw_14_gstatus_sxl_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_zero1 (io_ptw_14_gstatus_zero1_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_tsr (io_ptw_14_gstatus_tsr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_tw (io_ptw_14_gstatus_tw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_tvm (io_ptw_14_gstatus_tvm_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mxr (io_ptw_14_gstatus_mxr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sum (io_ptw_14_gstatus_sum_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mprv (io_ptw_14_gstatus_mprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_fs (io_ptw_14_gstatus_fs_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mpp (io_ptw_14_gstatus_mpp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_vs (io_ptw_14_gstatus_vs_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_spp (io_ptw_14_gstatus_spp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mpie (io_ptw_14_gstatus_mpie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_ube (io_ptw_14_gstatus_ube_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_spie (io_ptw_14_gstatus_spie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_upie (io_ptw_14_gstatus_upie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mie (io_ptw_14_gstatus_mie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_hie (io_ptw_14_gstatus_hie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sie (io_ptw_14_gstatus_sie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_uie (io_ptw_14_gstatus_uie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_l (io_ptw_14_pmp_0_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_a (io_ptw_14_pmp_0_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_x (io_ptw_14_pmp_0_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_w (io_ptw_14_pmp_0_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_r (io_ptw_14_pmp_0_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_addr (io_ptw_14_pmp_0_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_mask (io_ptw_14_pmp_0_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_l (io_ptw_14_pmp_1_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_a (io_ptw_14_pmp_1_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_x (io_ptw_14_pmp_1_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_w (io_ptw_14_pmp_1_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_r (io_ptw_14_pmp_1_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_addr (io_ptw_14_pmp_1_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_mask (io_ptw_14_pmp_1_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_l (io_ptw_14_pmp_2_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_a (io_ptw_14_pmp_2_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_x (io_ptw_14_pmp_2_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_w (io_ptw_14_pmp_2_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_r (io_ptw_14_pmp_2_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_addr (io_ptw_14_pmp_2_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_mask (io_ptw_14_pmp_2_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_l (io_ptw_14_pmp_3_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_a (io_ptw_14_pmp_3_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_x (io_ptw_14_pmp_3_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_w (io_ptw_14_pmp_3_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_r (io_ptw_14_pmp_3_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_addr (io_ptw_14_pmp_3_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_mask (io_ptw_14_pmp_3_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_l (io_ptw_14_pmp_4_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_a (io_ptw_14_pmp_4_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_x (io_ptw_14_pmp_4_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_w (io_ptw_14_pmp_4_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_r (io_ptw_14_pmp_4_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_addr (io_ptw_14_pmp_4_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_mask (io_ptw_14_pmp_4_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_l (io_ptw_14_pmp_5_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_a (io_ptw_14_pmp_5_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_x (io_ptw_14_pmp_5_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_w (io_ptw_14_pmp_5_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_r (io_ptw_14_pmp_5_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_addr (io_ptw_14_pmp_5_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_mask (io_ptw_14_pmp_5_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_l (io_ptw_14_pmp_6_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_a (io_ptw_14_pmp_6_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_x (io_ptw_14_pmp_6_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_w (io_ptw_14_pmp_6_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_r (io_ptw_14_pmp_6_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_addr (io_ptw_14_pmp_6_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_mask (io_ptw_14_pmp_6_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_l (io_ptw_14_pmp_7_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_a (io_ptw_14_pmp_7_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_x (io_ptw_14_pmp_7_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_w (io_ptw_14_pmp_7_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_r (io_ptw_14_pmp_7_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_addr (io_ptw_14_pmp_7_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_mask (io_ptw_14_pmp_7_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_ren (io_ptw_14_customCSRs_csrs_0_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_wen (io_ptw_14_customCSRs_csrs_0_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_wdata (io_ptw_14_customCSRs_csrs_0_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_value (io_ptw_14_customCSRs_csrs_0_value_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_ren (io_ptw_14_customCSRs_csrs_1_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_wen (io_ptw_14_customCSRs_csrs_1_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_wdata (io_ptw_14_customCSRs_csrs_1_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_value (io_ptw_14_customCSRs_csrs_1_value_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_ren (io_ptw_14_customCSRs_csrs_2_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_wen (io_ptw_14_customCSRs_csrs_2_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_wdata (io_ptw_14_customCSRs_csrs_2_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_value (io_ptw_14_customCSRs_csrs_2_value_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_ren (io_ptw_14_customCSRs_csrs_3_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_wen (io_ptw_14_customCSRs_csrs_3_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_wdata (io_ptw_14_customCSRs_csrs_3_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_value (io_ptw_14_customCSRs_csrs_3_value_0), // @[ZstdCompressor.scala:95:7]
.io_status_valid (_cmd_router_io_dmem_status_out_valid), // @[ZstdCompressor.scala:112:26]
.io_status_bits_debug (_cmd_router_io_dmem_status_out_bits_status_debug), // @[ZstdCompressor.scala:112:26]
.io_status_bits_cease (_cmd_router_io_dmem_status_out_bits_status_cease), // @[ZstdCompressor.scala:112:26]
.io_status_bits_wfi (_cmd_router_io_dmem_status_out_bits_status_wfi), // @[ZstdCompressor.scala:112:26]
.io_status_bits_isa (_cmd_router_io_dmem_status_out_bits_status_isa), // @[ZstdCompressor.scala:112:26]
.io_status_bits_dprv (_cmd_router_io_dmem_status_out_bits_status_dprv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_dv (_cmd_router_io_dmem_status_out_bits_status_dv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_prv (_cmd_router_io_dmem_status_out_bits_status_prv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_v (_cmd_router_io_dmem_status_out_bits_status_v), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sd (_cmd_router_io_dmem_status_out_bits_status_sd), // @[ZstdCompressor.scala:112:26]
.io_status_bits_zero2 (_cmd_router_io_dmem_status_out_bits_status_zero2), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mpv (_cmd_router_io_dmem_status_out_bits_status_mpv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_gva (_cmd_router_io_dmem_status_out_bits_status_gva), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mbe (_cmd_router_io_dmem_status_out_bits_status_mbe), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sbe (_cmd_router_io_dmem_status_out_bits_status_sbe), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sxl (_cmd_router_io_dmem_status_out_bits_status_sxl), // @[ZstdCompressor.scala:112:26]
.io_status_bits_uxl (_cmd_router_io_dmem_status_out_bits_status_uxl), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sd_rv32 (_cmd_router_io_dmem_status_out_bits_status_sd_rv32), // @[ZstdCompressor.scala:112:26]
.io_status_bits_zero1 (_cmd_router_io_dmem_status_out_bits_status_zero1), // @[ZstdCompressor.scala:112:26]
.io_status_bits_tsr (_cmd_router_io_dmem_status_out_bits_status_tsr), // @[ZstdCompressor.scala:112:26]
.io_status_bits_tw (_cmd_router_io_dmem_status_out_bits_status_tw), // @[ZstdCompressor.scala:112:26]
.io_status_bits_tvm (_cmd_router_io_dmem_status_out_bits_status_tvm), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mxr (_cmd_router_io_dmem_status_out_bits_status_mxr), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sum (_cmd_router_io_dmem_status_out_bits_status_sum), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mprv (_cmd_router_io_dmem_status_out_bits_status_mprv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_xs (_cmd_router_io_dmem_status_out_bits_status_xs), // @[ZstdCompressor.scala:112:26]
.io_status_bits_fs (_cmd_router_io_dmem_status_out_bits_status_fs), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mpp (_cmd_router_io_dmem_status_out_bits_status_mpp), // @[ZstdCompressor.scala:112:26]
.io_status_bits_vs (_cmd_router_io_dmem_status_out_bits_status_vs), // @[ZstdCompressor.scala:112:26]
.io_status_bits_spp (_cmd_router_io_dmem_status_out_bits_status_spp), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mpie (_cmd_router_io_dmem_status_out_bits_status_mpie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_ube (_cmd_router_io_dmem_status_out_bits_status_ube), // @[ZstdCompressor.scala:112:26]
.io_status_bits_spie (_cmd_router_io_dmem_status_out_bits_status_spie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_upie (_cmd_router_io_dmem_status_out_bits_status_upie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mie (_cmd_router_io_dmem_status_out_bits_status_mie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_hie (_cmd_router_io_dmem_status_out_bits_status_hie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sie (_cmd_router_io_dmem_status_out_bits_status_sie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_uie (_cmd_router_io_dmem_status_out_bits_status_uie) // @[ZstdCompressor.scala:112:26]
); // @[ZstdCompressor.scala:82:39]
TLWidthWidget32_14 widget_14 ( // @[WidthWidget.scala:230:28]
.clock (clock),
.reset (reset),
.auto_anon_in_a_ready (_widget_14_auto_anon_in_a_ready),
.auto_anon_in_a_valid (_l2_raw_block_reader_auto_master_out_a_valid), // @[ZstdCompressor.scala:82:39]
.auto_anon_in_a_bits_opcode (_l2_raw_block_reader_auto_master_out_a_bits_opcode), // @[ZstdCompressor.scala:82:39]
.auto_anon_in_a_bits_param (_l2_raw_block_reader_auto_master_out_a_bits_param), // @[ZstdCompressor.scala:82:39]
.auto_anon_in_a_bits_size (_l2_raw_block_reader_auto_master_out_a_bits_size), // @[ZstdCompressor.scala:82:39]
.auto_anon_in_a_bits_source (_l2_raw_block_reader_auto_master_out_a_bits_source), // @[ZstdCompressor.scala:82:39]
.auto_anon_in_a_bits_address (_l2_raw_block_reader_auto_master_out_a_bits_address), // @[ZstdCompressor.scala:82:39]
.auto_anon_in_a_bits_mask (_l2_raw_block_reader_auto_master_out_a_bits_mask), // @[ZstdCompressor.scala:82:39]
.auto_anon_in_a_bits_data (_l2_raw_block_reader_auto_master_out_a_bits_data), // @[ZstdCompressor.scala:82:39]
.auto_anon_in_a_bits_corrupt (_l2_raw_block_reader_auto_master_out_a_bits_corrupt), // @[ZstdCompressor.scala:82:39]
.auto_anon_in_d_ready (_l2_raw_block_reader_auto_master_out_d_ready), // @[ZstdCompressor.scala:82:39]
.auto_anon_in_d_valid (_widget_14_auto_anon_in_d_valid),
.auto_anon_in_d_bits_opcode (_widget_14_auto_anon_in_d_bits_opcode),
.auto_anon_in_d_bits_param (_widget_14_auto_anon_in_d_bits_param),
.auto_anon_in_d_bits_size (_widget_14_auto_anon_in_d_bits_size),
.auto_anon_in_d_bits_source (_widget_14_auto_anon_in_d_bits_source),
.auto_anon_in_d_bits_sink (_widget_14_auto_anon_in_d_bits_sink),
.auto_anon_in_d_bits_denied (_widget_14_auto_anon_in_d_bits_denied),
.auto_anon_in_d_bits_data (_widget_14_auto_anon_in_d_bits_data),
.auto_anon_in_d_bits_corrupt (_widget_14_auto_anon_in_d_bits_corrupt),
.auto_anon_out_a_ready (x1_tlNodeIn_13_a_ready), // @[MixedNode.scala:551:17]
.auto_anon_out_a_valid (x1_tlNodeIn_13_a_valid),
.auto_anon_out_a_bits_opcode (x1_tlNodeIn_13_a_bits_opcode),
.auto_anon_out_a_bits_param (x1_tlNodeIn_13_a_bits_param),
.auto_anon_out_a_bits_size (x1_tlNodeIn_13_a_bits_size),
.auto_anon_out_a_bits_source (x1_tlNodeIn_13_a_bits_source),
.auto_anon_out_a_bits_address (x1_tlNodeIn_13_a_bits_address),
.auto_anon_out_a_bits_mask (x1_tlNodeIn_13_a_bits_mask),
.auto_anon_out_a_bits_data (x1_tlNodeIn_13_a_bits_data),
.auto_anon_out_a_bits_corrupt (x1_tlNodeIn_13_a_bits_corrupt),
.auto_anon_out_d_ready (x1_tlNodeIn_13_d_ready),
.auto_anon_out_d_valid (x1_tlNodeIn_13_d_valid), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_opcode (x1_tlNodeIn_13_d_bits_opcode), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_param (x1_tlNodeIn_13_d_bits_param), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_size (x1_tlNodeIn_13_d_bits_size), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_source (x1_tlNodeIn_13_d_bits_source), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_sink (x1_tlNodeIn_13_d_bits_sink), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_denied (x1_tlNodeIn_13_d_bits_denied), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_data (x1_tlNodeIn_13_d_bits_data), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_corrupt (x1_tlNodeIn_13_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[WidthWidget.scala:230:28]
L2MemHelperLatencyInjection_15 l2_raw_block_writer ( // @[ZstdCompressor.scala:85:39]
.clock (clock),
.reset (reset),
.auto_master_out_a_ready (_widget_15_auto_anon_in_a_ready), // @[WidthWidget.scala:230:28]
.auto_master_out_a_valid (_l2_raw_block_writer_auto_master_out_a_valid),
.auto_master_out_a_bits_opcode (_l2_raw_block_writer_auto_master_out_a_bits_opcode),
.auto_master_out_a_bits_param (_l2_raw_block_writer_auto_master_out_a_bits_param),
.auto_master_out_a_bits_size (_l2_raw_block_writer_auto_master_out_a_bits_size),
.auto_master_out_a_bits_source (_l2_raw_block_writer_auto_master_out_a_bits_source),
.auto_master_out_a_bits_address (_l2_raw_block_writer_auto_master_out_a_bits_address),
.auto_master_out_a_bits_mask (_l2_raw_block_writer_auto_master_out_a_bits_mask),
.auto_master_out_a_bits_data (_l2_raw_block_writer_auto_master_out_a_bits_data),
.auto_master_out_a_bits_corrupt (_l2_raw_block_writer_auto_master_out_a_bits_corrupt),
.auto_master_out_d_ready (_l2_raw_block_writer_auto_master_out_d_ready),
.auto_master_out_d_valid (_widget_15_auto_anon_in_d_valid), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_opcode (_widget_15_auto_anon_in_d_bits_opcode), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_param (_widget_15_auto_anon_in_d_bits_param), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_size (_widget_15_auto_anon_in_d_bits_size), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_source (_widget_15_auto_anon_in_d_bits_source), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_sink (_widget_15_auto_anon_in_d_bits_sink), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_denied (_widget_15_auto_anon_in_d_bits_denied), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_data (_widget_15_auto_anon_in_d_bits_data), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_corrupt (_widget_15_auto_anon_in_d_bits_corrupt), // @[WidthWidget.scala:230:28]
.io_userif_req_ready (_l2_raw_block_writer_io_userif_req_ready),
.io_userif_req_valid (_raw_block_encoder_io_l2if_writer_req_valid), // @[ZstdCompressor.scala:161:33]
.io_userif_req_bits_addr (_raw_block_encoder_io_l2if_writer_req_bits_addr), // @[ZstdCompressor.scala:161:33]
.io_userif_req_bits_size (_raw_block_encoder_io_l2if_writer_req_bits_size), // @[ZstdCompressor.scala:161:33]
.io_userif_req_bits_data (_raw_block_encoder_io_l2if_writer_req_bits_data), // @[ZstdCompressor.scala:161:33]
.io_userif_resp_valid (_l2_raw_block_writer_io_userif_resp_valid),
.io_userif_resp_bits_data (_l2_raw_block_writer_io_userif_resp_bits_data),
.io_userif_no_memops_inflight (_l2_raw_block_writer_io_userif_no_memops_inflight),
.io_latency_inject_cycles (_cmd_router_io_LATENCY_INJECTION_CYCLES), // @[ZstdCompressor.scala:112:26]
.io_sfence (_cmd_router_io_sfence_out), // @[ZstdCompressor.scala:112:26]
.io_ptw_req_ready (io_ptw_15_req_ready_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_req_valid (io_ptw_15_req_valid_0),
.io_ptw_req_bits_bits_addr (io_ptw_15_req_bits_bits_addr_0),
.io_ptw_req_bits_bits_need_gpa (io_ptw_15_req_bits_bits_need_gpa_0),
.io_ptw_resp_valid (io_ptw_15_resp_valid_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_ae_ptw (io_ptw_15_resp_bits_ae_ptw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_ae_final (io_ptw_15_resp_bits_ae_final_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pf (io_ptw_15_resp_bits_pf_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gf (io_ptw_15_resp_bits_gf_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_hr (io_ptw_15_resp_bits_hr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_hw (io_ptw_15_resp_bits_hw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_hx (io_ptw_15_resp_bits_hx_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_reserved_for_future (io_ptw_15_resp_bits_pte_reserved_for_future_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_ppn (io_ptw_15_resp_bits_pte_ppn_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_reserved_for_software (io_ptw_15_resp_bits_pte_reserved_for_software_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_d (io_ptw_15_resp_bits_pte_d_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_a (io_ptw_15_resp_bits_pte_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_g (io_ptw_15_resp_bits_pte_g_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_u (io_ptw_15_resp_bits_pte_u_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_x (io_ptw_15_resp_bits_pte_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_w (io_ptw_15_resp_bits_pte_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_r (io_ptw_15_resp_bits_pte_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_v (io_ptw_15_resp_bits_pte_v_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_level (io_ptw_15_resp_bits_level_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_homogeneous (io_ptw_15_resp_bits_homogeneous_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gpa_valid (io_ptw_15_resp_bits_gpa_valid_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gpa_bits (io_ptw_15_resp_bits_gpa_bits_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gpa_is_pte (io_ptw_15_resp_bits_gpa_is_pte_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_ptbr_mode (io_ptw_15_ptbr_mode_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_ptbr_ppn (io_ptw_15_ptbr_ppn_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_debug (io_ptw_15_status_debug_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_cease (io_ptw_15_status_cease_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_wfi (io_ptw_15_status_wfi_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_isa (io_ptw_15_status_isa_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_dprv (io_ptw_15_status_dprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_dv (io_ptw_15_status_dv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_prv (io_ptw_15_status_prv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_v (io_ptw_15_status_v_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mpv (io_ptw_15_status_mpv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_gva (io_ptw_15_status_gva_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_tsr (io_ptw_15_status_tsr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_tw (io_ptw_15_status_tw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_tvm (io_ptw_15_status_tvm_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mxr (io_ptw_15_status_mxr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_sum (io_ptw_15_status_sum_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mprv (io_ptw_15_status_mprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_fs (io_ptw_15_status_fs_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mpp (io_ptw_15_status_mpp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_spp (io_ptw_15_status_spp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mpie (io_ptw_15_status_mpie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_spie (io_ptw_15_status_spie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mie (io_ptw_15_status_mie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_sie (io_ptw_15_status_sie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_hstatus_spvp (io_ptw_15_hstatus_spvp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_hstatus_spv (io_ptw_15_hstatus_spv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_hstatus_gva (io_ptw_15_hstatus_gva_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_debug (io_ptw_15_gstatus_debug_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_cease (io_ptw_15_gstatus_cease_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_wfi (io_ptw_15_gstatus_wfi_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_isa (io_ptw_15_gstatus_isa_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_dprv (io_ptw_15_gstatus_dprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_dv (io_ptw_15_gstatus_dv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_prv (io_ptw_15_gstatus_prv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_v (io_ptw_15_gstatus_v_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_zero2 (io_ptw_15_gstatus_zero2_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mpv (io_ptw_15_gstatus_mpv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_gva (io_ptw_15_gstatus_gva_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mbe (io_ptw_15_gstatus_mbe_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sbe (io_ptw_15_gstatus_sbe_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sxl (io_ptw_15_gstatus_sxl_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_zero1 (io_ptw_15_gstatus_zero1_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_tsr (io_ptw_15_gstatus_tsr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_tw (io_ptw_15_gstatus_tw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_tvm (io_ptw_15_gstatus_tvm_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mxr (io_ptw_15_gstatus_mxr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sum (io_ptw_15_gstatus_sum_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mprv (io_ptw_15_gstatus_mprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_fs (io_ptw_15_gstatus_fs_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mpp (io_ptw_15_gstatus_mpp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_vs (io_ptw_15_gstatus_vs_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_spp (io_ptw_15_gstatus_spp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mpie (io_ptw_15_gstatus_mpie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_ube (io_ptw_15_gstatus_ube_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_spie (io_ptw_15_gstatus_spie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_upie (io_ptw_15_gstatus_upie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mie (io_ptw_15_gstatus_mie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_hie (io_ptw_15_gstatus_hie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sie (io_ptw_15_gstatus_sie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_uie (io_ptw_15_gstatus_uie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_l (io_ptw_15_pmp_0_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_a (io_ptw_15_pmp_0_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_x (io_ptw_15_pmp_0_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_w (io_ptw_15_pmp_0_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_r (io_ptw_15_pmp_0_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_addr (io_ptw_15_pmp_0_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_mask (io_ptw_15_pmp_0_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_l (io_ptw_15_pmp_1_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_a (io_ptw_15_pmp_1_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_x (io_ptw_15_pmp_1_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_w (io_ptw_15_pmp_1_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_r (io_ptw_15_pmp_1_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_addr (io_ptw_15_pmp_1_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_mask (io_ptw_15_pmp_1_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_l (io_ptw_15_pmp_2_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_a (io_ptw_15_pmp_2_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_x (io_ptw_15_pmp_2_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_w (io_ptw_15_pmp_2_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_r (io_ptw_15_pmp_2_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_addr (io_ptw_15_pmp_2_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_mask (io_ptw_15_pmp_2_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_l (io_ptw_15_pmp_3_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_a (io_ptw_15_pmp_3_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_x (io_ptw_15_pmp_3_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_w (io_ptw_15_pmp_3_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_r (io_ptw_15_pmp_3_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_addr (io_ptw_15_pmp_3_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_mask (io_ptw_15_pmp_3_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_l (io_ptw_15_pmp_4_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_a (io_ptw_15_pmp_4_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_x (io_ptw_15_pmp_4_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_w (io_ptw_15_pmp_4_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_r (io_ptw_15_pmp_4_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_addr (io_ptw_15_pmp_4_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_mask (io_ptw_15_pmp_4_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_l (io_ptw_15_pmp_5_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_a (io_ptw_15_pmp_5_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_x (io_ptw_15_pmp_5_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_w (io_ptw_15_pmp_5_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_r (io_ptw_15_pmp_5_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_addr (io_ptw_15_pmp_5_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_mask (io_ptw_15_pmp_5_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_l (io_ptw_15_pmp_6_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_a (io_ptw_15_pmp_6_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_x (io_ptw_15_pmp_6_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_w (io_ptw_15_pmp_6_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_r (io_ptw_15_pmp_6_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_addr (io_ptw_15_pmp_6_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_mask (io_ptw_15_pmp_6_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_l (io_ptw_15_pmp_7_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_a (io_ptw_15_pmp_7_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_x (io_ptw_15_pmp_7_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_w (io_ptw_15_pmp_7_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_r (io_ptw_15_pmp_7_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_addr (io_ptw_15_pmp_7_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_mask (io_ptw_15_pmp_7_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_ren (io_ptw_15_customCSRs_csrs_0_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_wen (io_ptw_15_customCSRs_csrs_0_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_wdata (io_ptw_15_customCSRs_csrs_0_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_value (io_ptw_15_customCSRs_csrs_0_value_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_ren (io_ptw_15_customCSRs_csrs_1_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_wen (io_ptw_15_customCSRs_csrs_1_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_wdata (io_ptw_15_customCSRs_csrs_1_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_value (io_ptw_15_customCSRs_csrs_1_value_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_ren (io_ptw_15_customCSRs_csrs_2_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_wen (io_ptw_15_customCSRs_csrs_2_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_wdata (io_ptw_15_customCSRs_csrs_2_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_value (io_ptw_15_customCSRs_csrs_2_value_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_ren (io_ptw_15_customCSRs_csrs_3_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_wen (io_ptw_15_customCSRs_csrs_3_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_wdata (io_ptw_15_customCSRs_csrs_3_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_value (io_ptw_15_customCSRs_csrs_3_value_0), // @[ZstdCompressor.scala:95:7]
.io_status_valid (_cmd_router_io_dmem_status_out_valid), // @[ZstdCompressor.scala:112:26]
.io_status_bits_debug (_cmd_router_io_dmem_status_out_bits_status_debug), // @[ZstdCompressor.scala:112:26]
.io_status_bits_cease (_cmd_router_io_dmem_status_out_bits_status_cease), // @[ZstdCompressor.scala:112:26]
.io_status_bits_wfi (_cmd_router_io_dmem_status_out_bits_status_wfi), // @[ZstdCompressor.scala:112:26]
.io_status_bits_isa (_cmd_router_io_dmem_status_out_bits_status_isa), // @[ZstdCompressor.scala:112:26]
.io_status_bits_dprv (_cmd_router_io_dmem_status_out_bits_status_dprv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_dv (_cmd_router_io_dmem_status_out_bits_status_dv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_prv (_cmd_router_io_dmem_status_out_bits_status_prv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_v (_cmd_router_io_dmem_status_out_bits_status_v), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sd (_cmd_router_io_dmem_status_out_bits_status_sd), // @[ZstdCompressor.scala:112:26]
.io_status_bits_zero2 (_cmd_router_io_dmem_status_out_bits_status_zero2), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mpv (_cmd_router_io_dmem_status_out_bits_status_mpv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_gva (_cmd_router_io_dmem_status_out_bits_status_gva), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mbe (_cmd_router_io_dmem_status_out_bits_status_mbe), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sbe (_cmd_router_io_dmem_status_out_bits_status_sbe), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sxl (_cmd_router_io_dmem_status_out_bits_status_sxl), // @[ZstdCompressor.scala:112:26]
.io_status_bits_uxl (_cmd_router_io_dmem_status_out_bits_status_uxl), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sd_rv32 (_cmd_router_io_dmem_status_out_bits_status_sd_rv32), // @[ZstdCompressor.scala:112:26]
.io_status_bits_zero1 (_cmd_router_io_dmem_status_out_bits_status_zero1), // @[ZstdCompressor.scala:112:26]
.io_status_bits_tsr (_cmd_router_io_dmem_status_out_bits_status_tsr), // @[ZstdCompressor.scala:112:26]
.io_status_bits_tw (_cmd_router_io_dmem_status_out_bits_status_tw), // @[ZstdCompressor.scala:112:26]
.io_status_bits_tvm (_cmd_router_io_dmem_status_out_bits_status_tvm), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mxr (_cmd_router_io_dmem_status_out_bits_status_mxr), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sum (_cmd_router_io_dmem_status_out_bits_status_sum), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mprv (_cmd_router_io_dmem_status_out_bits_status_mprv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_xs (_cmd_router_io_dmem_status_out_bits_status_xs), // @[ZstdCompressor.scala:112:26]
.io_status_bits_fs (_cmd_router_io_dmem_status_out_bits_status_fs), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mpp (_cmd_router_io_dmem_status_out_bits_status_mpp), // @[ZstdCompressor.scala:112:26]
.io_status_bits_vs (_cmd_router_io_dmem_status_out_bits_status_vs), // @[ZstdCompressor.scala:112:26]
.io_status_bits_spp (_cmd_router_io_dmem_status_out_bits_status_spp), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mpie (_cmd_router_io_dmem_status_out_bits_status_mpie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_ube (_cmd_router_io_dmem_status_out_bits_status_ube), // @[ZstdCompressor.scala:112:26]
.io_status_bits_spie (_cmd_router_io_dmem_status_out_bits_status_spie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_upie (_cmd_router_io_dmem_status_out_bits_status_upie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mie (_cmd_router_io_dmem_status_out_bits_status_mie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_hie (_cmd_router_io_dmem_status_out_bits_status_hie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sie (_cmd_router_io_dmem_status_out_bits_status_sie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_uie (_cmd_router_io_dmem_status_out_bits_status_uie) // @[ZstdCompressor.scala:112:26]
); // @[ZstdCompressor.scala:85:39]
TLWidthWidget32_15 widget_15 ( // @[WidthWidget.scala:230:28]
.clock (clock),
.reset (reset),
.auto_anon_in_a_ready (_widget_15_auto_anon_in_a_ready),
.auto_anon_in_a_valid (_l2_raw_block_writer_auto_master_out_a_valid), // @[ZstdCompressor.scala:85:39]
.auto_anon_in_a_bits_opcode (_l2_raw_block_writer_auto_master_out_a_bits_opcode), // @[ZstdCompressor.scala:85:39]
.auto_anon_in_a_bits_param (_l2_raw_block_writer_auto_master_out_a_bits_param), // @[ZstdCompressor.scala:85:39]
.auto_anon_in_a_bits_size (_l2_raw_block_writer_auto_master_out_a_bits_size), // @[ZstdCompressor.scala:85:39]
.auto_anon_in_a_bits_source (_l2_raw_block_writer_auto_master_out_a_bits_source), // @[ZstdCompressor.scala:85:39]
.auto_anon_in_a_bits_address (_l2_raw_block_writer_auto_master_out_a_bits_address), // @[ZstdCompressor.scala:85:39]
.auto_anon_in_a_bits_mask (_l2_raw_block_writer_auto_master_out_a_bits_mask), // @[ZstdCompressor.scala:85:39]
.auto_anon_in_a_bits_data (_l2_raw_block_writer_auto_master_out_a_bits_data), // @[ZstdCompressor.scala:85:39]
.auto_anon_in_a_bits_corrupt (_l2_raw_block_writer_auto_master_out_a_bits_corrupt), // @[ZstdCompressor.scala:85:39]
.auto_anon_in_d_ready (_l2_raw_block_writer_auto_master_out_d_ready), // @[ZstdCompressor.scala:85:39]
.auto_anon_in_d_valid (_widget_15_auto_anon_in_d_valid),
.auto_anon_in_d_bits_opcode (_widget_15_auto_anon_in_d_bits_opcode),
.auto_anon_in_d_bits_param (_widget_15_auto_anon_in_d_bits_param),
.auto_anon_in_d_bits_size (_widget_15_auto_anon_in_d_bits_size),
.auto_anon_in_d_bits_source (_widget_15_auto_anon_in_d_bits_source),
.auto_anon_in_d_bits_sink (_widget_15_auto_anon_in_d_bits_sink),
.auto_anon_in_d_bits_denied (_widget_15_auto_anon_in_d_bits_denied),
.auto_anon_in_d_bits_data (_widget_15_auto_anon_in_d_bits_data),
.auto_anon_in_d_bits_corrupt (_widget_15_auto_anon_in_d_bits_corrupt),
.auto_anon_out_a_ready (x1_tlNodeIn_14_a_ready), // @[MixedNode.scala:551:17]
.auto_anon_out_a_valid (x1_tlNodeIn_14_a_valid),
.auto_anon_out_a_bits_opcode (x1_tlNodeIn_14_a_bits_opcode),
.auto_anon_out_a_bits_param (x1_tlNodeIn_14_a_bits_param),
.auto_anon_out_a_bits_size (x1_tlNodeIn_14_a_bits_size),
.auto_anon_out_a_bits_source (x1_tlNodeIn_14_a_bits_source),
.auto_anon_out_a_bits_address (x1_tlNodeIn_14_a_bits_address),
.auto_anon_out_a_bits_mask (x1_tlNodeIn_14_a_bits_mask),
.auto_anon_out_a_bits_data (x1_tlNodeIn_14_a_bits_data),
.auto_anon_out_a_bits_corrupt (x1_tlNodeIn_14_a_bits_corrupt),
.auto_anon_out_d_ready (x1_tlNodeIn_14_d_ready),
.auto_anon_out_d_valid (x1_tlNodeIn_14_d_valid), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_opcode (x1_tlNodeIn_14_d_bits_opcode), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_param (x1_tlNodeIn_14_d_bits_param), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_size (x1_tlNodeIn_14_d_bits_size), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_source (x1_tlNodeIn_14_d_bits_source), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_sink (x1_tlNodeIn_14_d_bits_sink), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_denied (x1_tlNodeIn_14_d_bits_denied), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_data (x1_tlNodeIn_14_d_bits_data), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_corrupt (x1_tlNodeIn_14_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[WidthWidget.scala:230:28]
L2MemHelperLatencyInjection_16 l2_raw_lit_reader ( // @[ZstdCompressor.scala:88:37]
.clock (clock),
.reset (reset),
.auto_master_out_a_ready (_widget_16_auto_anon_in_a_ready), // @[WidthWidget.scala:230:28]
.auto_master_out_a_valid (_l2_raw_lit_reader_auto_master_out_a_valid),
.auto_master_out_a_bits_opcode (_l2_raw_lit_reader_auto_master_out_a_bits_opcode),
.auto_master_out_a_bits_param (_l2_raw_lit_reader_auto_master_out_a_bits_param),
.auto_master_out_a_bits_size (_l2_raw_lit_reader_auto_master_out_a_bits_size),
.auto_master_out_a_bits_source (_l2_raw_lit_reader_auto_master_out_a_bits_source),
.auto_master_out_a_bits_address (_l2_raw_lit_reader_auto_master_out_a_bits_address),
.auto_master_out_a_bits_mask (_l2_raw_lit_reader_auto_master_out_a_bits_mask),
.auto_master_out_a_bits_data (_l2_raw_lit_reader_auto_master_out_a_bits_data),
.auto_master_out_a_bits_corrupt (_l2_raw_lit_reader_auto_master_out_a_bits_corrupt),
.auto_master_out_d_ready (_l2_raw_lit_reader_auto_master_out_d_ready),
.auto_master_out_d_valid (_widget_16_auto_anon_in_d_valid), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_opcode (_widget_16_auto_anon_in_d_bits_opcode), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_param (_widget_16_auto_anon_in_d_bits_param), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_size (_widget_16_auto_anon_in_d_bits_size), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_source (_widget_16_auto_anon_in_d_bits_source), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_sink (_widget_16_auto_anon_in_d_bits_sink), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_denied (_widget_16_auto_anon_in_d_bits_denied), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_data (_widget_16_auto_anon_in_d_bits_data), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_corrupt (_widget_16_auto_anon_in_d_bits_corrupt), // @[WidthWidget.scala:230:28]
.io_userif_req_ready (_l2_raw_lit_reader_io_userif_req_ready),
.io_userif_req_valid (_raw_lit_encoder_io_l2io_read_req_valid), // @[ZstdCompressor.scala:154:31]
.io_userif_req_bits_addr (_raw_lit_encoder_io_l2io_read_req_bits_addr), // @[ZstdCompressor.scala:154:31]
.io_userif_resp_ready (_raw_lit_encoder_io_l2io_read_resp_ready), // @[ZstdCompressor.scala:154:31]
.io_userif_resp_valid (_l2_raw_lit_reader_io_userif_resp_valid),
.io_userif_resp_bits_data (_l2_raw_lit_reader_io_userif_resp_bits_data),
.io_userif_no_memops_inflight (_l2_raw_lit_reader_io_userif_no_memops_inflight),
.io_latency_inject_cycles (_l2_raw_lit_reader_io_latency_inject_cycles_T), // @[ZstdCompressor.scala:202:65]
.io_sfence (_cmd_router_io_sfence_out), // @[ZstdCompressor.scala:112:26]
.io_ptw_req_ready (io_ptw_16_req_ready_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_req_valid (io_ptw_16_req_valid_0),
.io_ptw_req_bits_bits_addr (io_ptw_16_req_bits_bits_addr_0),
.io_ptw_req_bits_bits_need_gpa (io_ptw_16_req_bits_bits_need_gpa_0),
.io_ptw_resp_valid (io_ptw_16_resp_valid_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_ae_ptw (io_ptw_16_resp_bits_ae_ptw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_ae_final (io_ptw_16_resp_bits_ae_final_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pf (io_ptw_16_resp_bits_pf_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gf (io_ptw_16_resp_bits_gf_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_hr (io_ptw_16_resp_bits_hr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_hw (io_ptw_16_resp_bits_hw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_hx (io_ptw_16_resp_bits_hx_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_reserved_for_future (io_ptw_16_resp_bits_pte_reserved_for_future_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_ppn (io_ptw_16_resp_bits_pte_ppn_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_reserved_for_software (io_ptw_16_resp_bits_pte_reserved_for_software_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_d (io_ptw_16_resp_bits_pte_d_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_a (io_ptw_16_resp_bits_pte_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_g (io_ptw_16_resp_bits_pte_g_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_u (io_ptw_16_resp_bits_pte_u_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_x (io_ptw_16_resp_bits_pte_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_w (io_ptw_16_resp_bits_pte_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_r (io_ptw_16_resp_bits_pte_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_v (io_ptw_16_resp_bits_pte_v_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_level (io_ptw_16_resp_bits_level_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_homogeneous (io_ptw_16_resp_bits_homogeneous_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gpa_valid (io_ptw_16_resp_bits_gpa_valid_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gpa_bits (io_ptw_16_resp_bits_gpa_bits_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gpa_is_pte (io_ptw_16_resp_bits_gpa_is_pte_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_ptbr_mode (io_ptw_16_ptbr_mode_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_ptbr_ppn (io_ptw_16_ptbr_ppn_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_debug (io_ptw_16_status_debug_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_cease (io_ptw_16_status_cease_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_wfi (io_ptw_16_status_wfi_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_isa (io_ptw_16_status_isa_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_dprv (io_ptw_16_status_dprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_dv (io_ptw_16_status_dv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_prv (io_ptw_16_status_prv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_v (io_ptw_16_status_v_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mpv (io_ptw_16_status_mpv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_gva (io_ptw_16_status_gva_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_tsr (io_ptw_16_status_tsr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_tw (io_ptw_16_status_tw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_tvm (io_ptw_16_status_tvm_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mxr (io_ptw_16_status_mxr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_sum (io_ptw_16_status_sum_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mprv (io_ptw_16_status_mprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_fs (io_ptw_16_status_fs_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mpp (io_ptw_16_status_mpp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_spp (io_ptw_16_status_spp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mpie (io_ptw_16_status_mpie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_spie (io_ptw_16_status_spie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mie (io_ptw_16_status_mie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_sie (io_ptw_16_status_sie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_hstatus_spvp (io_ptw_16_hstatus_spvp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_hstatus_spv (io_ptw_16_hstatus_spv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_hstatus_gva (io_ptw_16_hstatus_gva_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_debug (io_ptw_16_gstatus_debug_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_cease (io_ptw_16_gstatus_cease_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_wfi (io_ptw_16_gstatus_wfi_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_isa (io_ptw_16_gstatus_isa_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_dprv (io_ptw_16_gstatus_dprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_dv (io_ptw_16_gstatus_dv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_prv (io_ptw_16_gstatus_prv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_v (io_ptw_16_gstatus_v_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_zero2 (io_ptw_16_gstatus_zero2_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mpv (io_ptw_16_gstatus_mpv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_gva (io_ptw_16_gstatus_gva_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mbe (io_ptw_16_gstatus_mbe_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sbe (io_ptw_16_gstatus_sbe_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sxl (io_ptw_16_gstatus_sxl_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_zero1 (io_ptw_16_gstatus_zero1_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_tsr (io_ptw_16_gstatus_tsr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_tw (io_ptw_16_gstatus_tw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_tvm (io_ptw_16_gstatus_tvm_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mxr (io_ptw_16_gstatus_mxr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sum (io_ptw_16_gstatus_sum_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mprv (io_ptw_16_gstatus_mprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_fs (io_ptw_16_gstatus_fs_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mpp (io_ptw_16_gstatus_mpp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_vs (io_ptw_16_gstatus_vs_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_spp (io_ptw_16_gstatus_spp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mpie (io_ptw_16_gstatus_mpie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_ube (io_ptw_16_gstatus_ube_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_spie (io_ptw_16_gstatus_spie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_upie (io_ptw_16_gstatus_upie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mie (io_ptw_16_gstatus_mie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_hie (io_ptw_16_gstatus_hie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sie (io_ptw_16_gstatus_sie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_uie (io_ptw_16_gstatus_uie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_l (io_ptw_16_pmp_0_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_a (io_ptw_16_pmp_0_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_x (io_ptw_16_pmp_0_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_w (io_ptw_16_pmp_0_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_r (io_ptw_16_pmp_0_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_addr (io_ptw_16_pmp_0_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_mask (io_ptw_16_pmp_0_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_l (io_ptw_16_pmp_1_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_a (io_ptw_16_pmp_1_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_x (io_ptw_16_pmp_1_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_w (io_ptw_16_pmp_1_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_r (io_ptw_16_pmp_1_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_addr (io_ptw_16_pmp_1_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_mask (io_ptw_16_pmp_1_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_l (io_ptw_16_pmp_2_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_a (io_ptw_16_pmp_2_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_x (io_ptw_16_pmp_2_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_w (io_ptw_16_pmp_2_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_r (io_ptw_16_pmp_2_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_addr (io_ptw_16_pmp_2_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_mask (io_ptw_16_pmp_2_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_l (io_ptw_16_pmp_3_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_a (io_ptw_16_pmp_3_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_x (io_ptw_16_pmp_3_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_w (io_ptw_16_pmp_3_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_r (io_ptw_16_pmp_3_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_addr (io_ptw_16_pmp_3_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_mask (io_ptw_16_pmp_3_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_l (io_ptw_16_pmp_4_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_a (io_ptw_16_pmp_4_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_x (io_ptw_16_pmp_4_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_w (io_ptw_16_pmp_4_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_r (io_ptw_16_pmp_4_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_addr (io_ptw_16_pmp_4_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_mask (io_ptw_16_pmp_4_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_l (io_ptw_16_pmp_5_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_a (io_ptw_16_pmp_5_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_x (io_ptw_16_pmp_5_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_w (io_ptw_16_pmp_5_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_r (io_ptw_16_pmp_5_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_addr (io_ptw_16_pmp_5_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_mask (io_ptw_16_pmp_5_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_l (io_ptw_16_pmp_6_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_a (io_ptw_16_pmp_6_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_x (io_ptw_16_pmp_6_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_w (io_ptw_16_pmp_6_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_r (io_ptw_16_pmp_6_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_addr (io_ptw_16_pmp_6_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_mask (io_ptw_16_pmp_6_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_l (io_ptw_16_pmp_7_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_a (io_ptw_16_pmp_7_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_x (io_ptw_16_pmp_7_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_w (io_ptw_16_pmp_7_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_r (io_ptw_16_pmp_7_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_addr (io_ptw_16_pmp_7_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_mask (io_ptw_16_pmp_7_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_ren (io_ptw_16_customCSRs_csrs_0_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_wen (io_ptw_16_customCSRs_csrs_0_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_wdata (io_ptw_16_customCSRs_csrs_0_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_value (io_ptw_16_customCSRs_csrs_0_value_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_ren (io_ptw_16_customCSRs_csrs_1_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_wen (io_ptw_16_customCSRs_csrs_1_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_wdata (io_ptw_16_customCSRs_csrs_1_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_value (io_ptw_16_customCSRs_csrs_1_value_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_ren (io_ptw_16_customCSRs_csrs_2_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_wen (io_ptw_16_customCSRs_csrs_2_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_wdata (io_ptw_16_customCSRs_csrs_2_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_value (io_ptw_16_customCSRs_csrs_2_value_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_ren (io_ptw_16_customCSRs_csrs_3_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_wen (io_ptw_16_customCSRs_csrs_3_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_wdata (io_ptw_16_customCSRs_csrs_3_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_value (io_ptw_16_customCSRs_csrs_3_value_0), // @[ZstdCompressor.scala:95:7]
.io_status_valid (_cmd_router_io_dmem_status_out_valid), // @[ZstdCompressor.scala:112:26]
.io_status_bits_debug (_cmd_router_io_dmem_status_out_bits_status_debug), // @[ZstdCompressor.scala:112:26]
.io_status_bits_cease (_cmd_router_io_dmem_status_out_bits_status_cease), // @[ZstdCompressor.scala:112:26]
.io_status_bits_wfi (_cmd_router_io_dmem_status_out_bits_status_wfi), // @[ZstdCompressor.scala:112:26]
.io_status_bits_isa (_cmd_router_io_dmem_status_out_bits_status_isa), // @[ZstdCompressor.scala:112:26]
.io_status_bits_dprv (_cmd_router_io_dmem_status_out_bits_status_dprv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_dv (_cmd_router_io_dmem_status_out_bits_status_dv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_prv (_cmd_router_io_dmem_status_out_bits_status_prv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_v (_cmd_router_io_dmem_status_out_bits_status_v), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sd (_cmd_router_io_dmem_status_out_bits_status_sd), // @[ZstdCompressor.scala:112:26]
.io_status_bits_zero2 (_cmd_router_io_dmem_status_out_bits_status_zero2), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mpv (_cmd_router_io_dmem_status_out_bits_status_mpv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_gva (_cmd_router_io_dmem_status_out_bits_status_gva), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mbe (_cmd_router_io_dmem_status_out_bits_status_mbe), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sbe (_cmd_router_io_dmem_status_out_bits_status_sbe), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sxl (_cmd_router_io_dmem_status_out_bits_status_sxl), // @[ZstdCompressor.scala:112:26]
.io_status_bits_uxl (_cmd_router_io_dmem_status_out_bits_status_uxl), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sd_rv32 (_cmd_router_io_dmem_status_out_bits_status_sd_rv32), // @[ZstdCompressor.scala:112:26]
.io_status_bits_zero1 (_cmd_router_io_dmem_status_out_bits_status_zero1), // @[ZstdCompressor.scala:112:26]
.io_status_bits_tsr (_cmd_router_io_dmem_status_out_bits_status_tsr), // @[ZstdCompressor.scala:112:26]
.io_status_bits_tw (_cmd_router_io_dmem_status_out_bits_status_tw), // @[ZstdCompressor.scala:112:26]
.io_status_bits_tvm (_cmd_router_io_dmem_status_out_bits_status_tvm), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mxr (_cmd_router_io_dmem_status_out_bits_status_mxr), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sum (_cmd_router_io_dmem_status_out_bits_status_sum), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mprv (_cmd_router_io_dmem_status_out_bits_status_mprv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_xs (_cmd_router_io_dmem_status_out_bits_status_xs), // @[ZstdCompressor.scala:112:26]
.io_status_bits_fs (_cmd_router_io_dmem_status_out_bits_status_fs), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mpp (_cmd_router_io_dmem_status_out_bits_status_mpp), // @[ZstdCompressor.scala:112:26]
.io_status_bits_vs (_cmd_router_io_dmem_status_out_bits_status_vs), // @[ZstdCompressor.scala:112:26]
.io_status_bits_spp (_cmd_router_io_dmem_status_out_bits_status_spp), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mpie (_cmd_router_io_dmem_status_out_bits_status_mpie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_ube (_cmd_router_io_dmem_status_out_bits_status_ube), // @[ZstdCompressor.scala:112:26]
.io_status_bits_spie (_cmd_router_io_dmem_status_out_bits_status_spie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_upie (_cmd_router_io_dmem_status_out_bits_status_upie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mie (_cmd_router_io_dmem_status_out_bits_status_mie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_hie (_cmd_router_io_dmem_status_out_bits_status_hie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sie (_cmd_router_io_dmem_status_out_bits_status_sie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_uie (_cmd_router_io_dmem_status_out_bits_status_uie) // @[ZstdCompressor.scala:112:26]
); // @[ZstdCompressor.scala:88:37]
TLWidthWidget32_16 widget_16 ( // @[WidthWidget.scala:230:28]
.clock (clock),
.reset (reset),
.auto_anon_in_a_ready (_widget_16_auto_anon_in_a_ready),
.auto_anon_in_a_valid (_l2_raw_lit_reader_auto_master_out_a_valid), // @[ZstdCompressor.scala:88:37]
.auto_anon_in_a_bits_opcode (_l2_raw_lit_reader_auto_master_out_a_bits_opcode), // @[ZstdCompressor.scala:88:37]
.auto_anon_in_a_bits_param (_l2_raw_lit_reader_auto_master_out_a_bits_param), // @[ZstdCompressor.scala:88:37]
.auto_anon_in_a_bits_size (_l2_raw_lit_reader_auto_master_out_a_bits_size), // @[ZstdCompressor.scala:88:37]
.auto_anon_in_a_bits_source (_l2_raw_lit_reader_auto_master_out_a_bits_source), // @[ZstdCompressor.scala:88:37]
.auto_anon_in_a_bits_address (_l2_raw_lit_reader_auto_master_out_a_bits_address), // @[ZstdCompressor.scala:88:37]
.auto_anon_in_a_bits_mask (_l2_raw_lit_reader_auto_master_out_a_bits_mask), // @[ZstdCompressor.scala:88:37]
.auto_anon_in_a_bits_data (_l2_raw_lit_reader_auto_master_out_a_bits_data), // @[ZstdCompressor.scala:88:37]
.auto_anon_in_a_bits_corrupt (_l2_raw_lit_reader_auto_master_out_a_bits_corrupt), // @[ZstdCompressor.scala:88:37]
.auto_anon_in_d_ready (_l2_raw_lit_reader_auto_master_out_d_ready), // @[ZstdCompressor.scala:88:37]
.auto_anon_in_d_valid (_widget_16_auto_anon_in_d_valid),
.auto_anon_in_d_bits_opcode (_widget_16_auto_anon_in_d_bits_opcode),
.auto_anon_in_d_bits_param (_widget_16_auto_anon_in_d_bits_param),
.auto_anon_in_d_bits_size (_widget_16_auto_anon_in_d_bits_size),
.auto_anon_in_d_bits_source (_widget_16_auto_anon_in_d_bits_source),
.auto_anon_in_d_bits_sink (_widget_16_auto_anon_in_d_bits_sink),
.auto_anon_in_d_bits_denied (_widget_16_auto_anon_in_d_bits_denied),
.auto_anon_in_d_bits_data (_widget_16_auto_anon_in_d_bits_data),
.auto_anon_in_d_bits_corrupt (_widget_16_auto_anon_in_d_bits_corrupt),
.auto_anon_out_a_ready (x1_tlNodeIn_15_a_ready), // @[MixedNode.scala:551:17]
.auto_anon_out_a_valid (x1_tlNodeIn_15_a_valid),
.auto_anon_out_a_bits_opcode (x1_tlNodeIn_15_a_bits_opcode),
.auto_anon_out_a_bits_param (x1_tlNodeIn_15_a_bits_param),
.auto_anon_out_a_bits_size (x1_tlNodeIn_15_a_bits_size),
.auto_anon_out_a_bits_source (x1_tlNodeIn_15_a_bits_source),
.auto_anon_out_a_bits_address (x1_tlNodeIn_15_a_bits_address),
.auto_anon_out_a_bits_mask (x1_tlNodeIn_15_a_bits_mask),
.auto_anon_out_a_bits_data (x1_tlNodeIn_15_a_bits_data),
.auto_anon_out_a_bits_corrupt (x1_tlNodeIn_15_a_bits_corrupt),
.auto_anon_out_d_ready (x1_tlNodeIn_15_d_ready),
.auto_anon_out_d_valid (x1_tlNodeIn_15_d_valid), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_opcode (x1_tlNodeIn_15_d_bits_opcode), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_param (x1_tlNodeIn_15_d_bits_param), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_size (x1_tlNodeIn_15_d_bits_size), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_source (x1_tlNodeIn_15_d_bits_source), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_sink (x1_tlNodeIn_15_d_bits_sink), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_denied (x1_tlNodeIn_15_d_bits_denied), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_data (x1_tlNodeIn_15_d_bits_data), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_corrupt (x1_tlNodeIn_15_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[WidthWidget.scala:230:28]
L2MemHelperLatencyInjection_17 l2_raw_lit_writer ( // @[ZstdCompressor.scala:91:37]
.clock (clock),
.reset (reset),
.auto_master_out_a_ready (_widget_17_auto_anon_in_a_ready), // @[WidthWidget.scala:230:28]
.auto_master_out_a_valid (_l2_raw_lit_writer_auto_master_out_a_valid),
.auto_master_out_a_bits_opcode (_l2_raw_lit_writer_auto_master_out_a_bits_opcode),
.auto_master_out_a_bits_param (_l2_raw_lit_writer_auto_master_out_a_bits_param),
.auto_master_out_a_bits_size (_l2_raw_lit_writer_auto_master_out_a_bits_size),
.auto_master_out_a_bits_source (_l2_raw_lit_writer_auto_master_out_a_bits_source),
.auto_master_out_a_bits_address (_l2_raw_lit_writer_auto_master_out_a_bits_address),
.auto_master_out_a_bits_mask (_l2_raw_lit_writer_auto_master_out_a_bits_mask),
.auto_master_out_a_bits_data (_l2_raw_lit_writer_auto_master_out_a_bits_data),
.auto_master_out_a_bits_corrupt (_l2_raw_lit_writer_auto_master_out_a_bits_corrupt),
.auto_master_out_d_ready (_l2_raw_lit_writer_auto_master_out_d_ready),
.auto_master_out_d_valid (_widget_17_auto_anon_in_d_valid), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_opcode (_widget_17_auto_anon_in_d_bits_opcode), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_param (_widget_17_auto_anon_in_d_bits_param), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_size (_widget_17_auto_anon_in_d_bits_size), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_source (_widget_17_auto_anon_in_d_bits_source), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_sink (_widget_17_auto_anon_in_d_bits_sink), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_denied (_widget_17_auto_anon_in_d_bits_denied), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_data (_widget_17_auto_anon_in_d_bits_data), // @[WidthWidget.scala:230:28]
.auto_master_out_d_bits_corrupt (_widget_17_auto_anon_in_d_bits_corrupt), // @[WidthWidget.scala:230:28]
.io_userif_req_ready (_l2_raw_lit_writer_io_userif_req_ready),
.io_userif_req_valid (_raw_lit_encoder_io_l2io_write_req_valid), // @[ZstdCompressor.scala:154:31]
.io_userif_req_bits_addr (_raw_lit_encoder_io_l2io_write_req_bits_addr), // @[ZstdCompressor.scala:154:31]
.io_userif_req_bits_size (_raw_lit_encoder_io_l2io_write_req_bits_size), // @[ZstdCompressor.scala:154:31]
.io_userif_req_bits_data (_raw_lit_encoder_io_l2io_write_req_bits_data), // @[ZstdCompressor.scala:154:31]
.io_userif_resp_valid (_l2_raw_lit_writer_io_userif_resp_valid),
.io_userif_resp_bits_data (_l2_raw_lit_writer_io_userif_resp_bits_data),
.io_userif_no_memops_inflight (_l2_raw_lit_writer_io_userif_no_memops_inflight),
.io_latency_inject_cycles (_cmd_router_io_LATENCY_INJECTION_CYCLES), // @[ZstdCompressor.scala:112:26]
.io_sfence (_cmd_router_io_sfence_out), // @[ZstdCompressor.scala:112:26]
.io_ptw_req_ready (io_ptw_17_req_ready_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_req_valid (io_ptw_17_req_valid_0),
.io_ptw_req_bits_bits_addr (io_ptw_17_req_bits_bits_addr_0),
.io_ptw_req_bits_bits_need_gpa (io_ptw_17_req_bits_bits_need_gpa_0),
.io_ptw_resp_valid (io_ptw_17_resp_valid_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_ae_ptw (io_ptw_17_resp_bits_ae_ptw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_ae_final (io_ptw_17_resp_bits_ae_final_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pf (io_ptw_17_resp_bits_pf_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gf (io_ptw_17_resp_bits_gf_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_hr (io_ptw_17_resp_bits_hr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_hw (io_ptw_17_resp_bits_hw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_hx (io_ptw_17_resp_bits_hx_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_reserved_for_future (io_ptw_17_resp_bits_pte_reserved_for_future_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_ppn (io_ptw_17_resp_bits_pte_ppn_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_reserved_for_software (io_ptw_17_resp_bits_pte_reserved_for_software_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_d (io_ptw_17_resp_bits_pte_d_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_a (io_ptw_17_resp_bits_pte_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_g (io_ptw_17_resp_bits_pte_g_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_u (io_ptw_17_resp_bits_pte_u_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_x (io_ptw_17_resp_bits_pte_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_w (io_ptw_17_resp_bits_pte_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_r (io_ptw_17_resp_bits_pte_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_pte_v (io_ptw_17_resp_bits_pte_v_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_level (io_ptw_17_resp_bits_level_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_homogeneous (io_ptw_17_resp_bits_homogeneous_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gpa_valid (io_ptw_17_resp_bits_gpa_valid_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gpa_bits (io_ptw_17_resp_bits_gpa_bits_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_resp_bits_gpa_is_pte (io_ptw_17_resp_bits_gpa_is_pte_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_ptbr_mode (io_ptw_17_ptbr_mode_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_ptbr_ppn (io_ptw_17_ptbr_ppn_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_debug (io_ptw_17_status_debug_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_cease (io_ptw_17_status_cease_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_wfi (io_ptw_17_status_wfi_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_isa (io_ptw_17_status_isa_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_dprv (io_ptw_17_status_dprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_dv (io_ptw_17_status_dv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_prv (io_ptw_17_status_prv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_v (io_ptw_17_status_v_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mpv (io_ptw_17_status_mpv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_gva (io_ptw_17_status_gva_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_tsr (io_ptw_17_status_tsr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_tw (io_ptw_17_status_tw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_tvm (io_ptw_17_status_tvm_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mxr (io_ptw_17_status_mxr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_sum (io_ptw_17_status_sum_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mprv (io_ptw_17_status_mprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_fs (io_ptw_17_status_fs_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mpp (io_ptw_17_status_mpp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_spp (io_ptw_17_status_spp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mpie (io_ptw_17_status_mpie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_spie (io_ptw_17_status_spie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_mie (io_ptw_17_status_mie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_status_sie (io_ptw_17_status_sie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_hstatus_spvp (io_ptw_17_hstatus_spvp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_hstatus_spv (io_ptw_17_hstatus_spv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_hstatus_gva (io_ptw_17_hstatus_gva_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_debug (io_ptw_17_gstatus_debug_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_cease (io_ptw_17_gstatus_cease_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_wfi (io_ptw_17_gstatus_wfi_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_isa (io_ptw_17_gstatus_isa_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_dprv (io_ptw_17_gstatus_dprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_dv (io_ptw_17_gstatus_dv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_prv (io_ptw_17_gstatus_prv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_v (io_ptw_17_gstatus_v_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_zero2 (io_ptw_17_gstatus_zero2_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mpv (io_ptw_17_gstatus_mpv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_gva (io_ptw_17_gstatus_gva_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mbe (io_ptw_17_gstatus_mbe_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sbe (io_ptw_17_gstatus_sbe_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sxl (io_ptw_17_gstatus_sxl_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_zero1 (io_ptw_17_gstatus_zero1_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_tsr (io_ptw_17_gstatus_tsr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_tw (io_ptw_17_gstatus_tw_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_tvm (io_ptw_17_gstatus_tvm_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mxr (io_ptw_17_gstatus_mxr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sum (io_ptw_17_gstatus_sum_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mprv (io_ptw_17_gstatus_mprv_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_fs (io_ptw_17_gstatus_fs_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mpp (io_ptw_17_gstatus_mpp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_vs (io_ptw_17_gstatus_vs_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_spp (io_ptw_17_gstatus_spp_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mpie (io_ptw_17_gstatus_mpie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_ube (io_ptw_17_gstatus_ube_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_spie (io_ptw_17_gstatus_spie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_upie (io_ptw_17_gstatus_upie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_mie (io_ptw_17_gstatus_mie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_hie (io_ptw_17_gstatus_hie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_sie (io_ptw_17_gstatus_sie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_gstatus_uie (io_ptw_17_gstatus_uie_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_l (io_ptw_17_pmp_0_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_a (io_ptw_17_pmp_0_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_x (io_ptw_17_pmp_0_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_w (io_ptw_17_pmp_0_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_cfg_r (io_ptw_17_pmp_0_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_addr (io_ptw_17_pmp_0_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_0_mask (io_ptw_17_pmp_0_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_l (io_ptw_17_pmp_1_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_a (io_ptw_17_pmp_1_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_x (io_ptw_17_pmp_1_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_w (io_ptw_17_pmp_1_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_cfg_r (io_ptw_17_pmp_1_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_addr (io_ptw_17_pmp_1_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_1_mask (io_ptw_17_pmp_1_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_l (io_ptw_17_pmp_2_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_a (io_ptw_17_pmp_2_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_x (io_ptw_17_pmp_2_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_w (io_ptw_17_pmp_2_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_cfg_r (io_ptw_17_pmp_2_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_addr (io_ptw_17_pmp_2_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_2_mask (io_ptw_17_pmp_2_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_l (io_ptw_17_pmp_3_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_a (io_ptw_17_pmp_3_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_x (io_ptw_17_pmp_3_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_w (io_ptw_17_pmp_3_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_cfg_r (io_ptw_17_pmp_3_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_addr (io_ptw_17_pmp_3_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_3_mask (io_ptw_17_pmp_3_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_l (io_ptw_17_pmp_4_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_a (io_ptw_17_pmp_4_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_x (io_ptw_17_pmp_4_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_w (io_ptw_17_pmp_4_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_cfg_r (io_ptw_17_pmp_4_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_addr (io_ptw_17_pmp_4_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_4_mask (io_ptw_17_pmp_4_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_l (io_ptw_17_pmp_5_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_a (io_ptw_17_pmp_5_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_x (io_ptw_17_pmp_5_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_w (io_ptw_17_pmp_5_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_cfg_r (io_ptw_17_pmp_5_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_addr (io_ptw_17_pmp_5_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_5_mask (io_ptw_17_pmp_5_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_l (io_ptw_17_pmp_6_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_a (io_ptw_17_pmp_6_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_x (io_ptw_17_pmp_6_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_w (io_ptw_17_pmp_6_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_cfg_r (io_ptw_17_pmp_6_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_addr (io_ptw_17_pmp_6_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_6_mask (io_ptw_17_pmp_6_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_l (io_ptw_17_pmp_7_cfg_l_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_a (io_ptw_17_pmp_7_cfg_a_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_x (io_ptw_17_pmp_7_cfg_x_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_w (io_ptw_17_pmp_7_cfg_w_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_cfg_r (io_ptw_17_pmp_7_cfg_r_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_addr (io_ptw_17_pmp_7_addr_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_pmp_7_mask (io_ptw_17_pmp_7_mask_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_ren (io_ptw_17_customCSRs_csrs_0_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_wen (io_ptw_17_customCSRs_csrs_0_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_wdata (io_ptw_17_customCSRs_csrs_0_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_0_value (io_ptw_17_customCSRs_csrs_0_value_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_ren (io_ptw_17_customCSRs_csrs_1_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_wen (io_ptw_17_customCSRs_csrs_1_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_wdata (io_ptw_17_customCSRs_csrs_1_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_1_value (io_ptw_17_customCSRs_csrs_1_value_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_ren (io_ptw_17_customCSRs_csrs_2_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_wen (io_ptw_17_customCSRs_csrs_2_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_wdata (io_ptw_17_customCSRs_csrs_2_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_2_value (io_ptw_17_customCSRs_csrs_2_value_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_ren (io_ptw_17_customCSRs_csrs_3_ren_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_wen (io_ptw_17_customCSRs_csrs_3_wen_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_wdata (io_ptw_17_customCSRs_csrs_3_wdata_0), // @[ZstdCompressor.scala:95:7]
.io_ptw_customCSRs_csrs_3_value (io_ptw_17_customCSRs_csrs_3_value_0), // @[ZstdCompressor.scala:95:7]
.io_status_valid (_cmd_router_io_dmem_status_out_valid), // @[ZstdCompressor.scala:112:26]
.io_status_bits_debug (_cmd_router_io_dmem_status_out_bits_status_debug), // @[ZstdCompressor.scala:112:26]
.io_status_bits_cease (_cmd_router_io_dmem_status_out_bits_status_cease), // @[ZstdCompressor.scala:112:26]
.io_status_bits_wfi (_cmd_router_io_dmem_status_out_bits_status_wfi), // @[ZstdCompressor.scala:112:26]
.io_status_bits_isa (_cmd_router_io_dmem_status_out_bits_status_isa), // @[ZstdCompressor.scala:112:26]
.io_status_bits_dprv (_cmd_router_io_dmem_status_out_bits_status_dprv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_dv (_cmd_router_io_dmem_status_out_bits_status_dv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_prv (_cmd_router_io_dmem_status_out_bits_status_prv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_v (_cmd_router_io_dmem_status_out_bits_status_v), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sd (_cmd_router_io_dmem_status_out_bits_status_sd), // @[ZstdCompressor.scala:112:26]
.io_status_bits_zero2 (_cmd_router_io_dmem_status_out_bits_status_zero2), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mpv (_cmd_router_io_dmem_status_out_bits_status_mpv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_gva (_cmd_router_io_dmem_status_out_bits_status_gva), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mbe (_cmd_router_io_dmem_status_out_bits_status_mbe), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sbe (_cmd_router_io_dmem_status_out_bits_status_sbe), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sxl (_cmd_router_io_dmem_status_out_bits_status_sxl), // @[ZstdCompressor.scala:112:26]
.io_status_bits_uxl (_cmd_router_io_dmem_status_out_bits_status_uxl), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sd_rv32 (_cmd_router_io_dmem_status_out_bits_status_sd_rv32), // @[ZstdCompressor.scala:112:26]
.io_status_bits_zero1 (_cmd_router_io_dmem_status_out_bits_status_zero1), // @[ZstdCompressor.scala:112:26]
.io_status_bits_tsr (_cmd_router_io_dmem_status_out_bits_status_tsr), // @[ZstdCompressor.scala:112:26]
.io_status_bits_tw (_cmd_router_io_dmem_status_out_bits_status_tw), // @[ZstdCompressor.scala:112:26]
.io_status_bits_tvm (_cmd_router_io_dmem_status_out_bits_status_tvm), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mxr (_cmd_router_io_dmem_status_out_bits_status_mxr), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sum (_cmd_router_io_dmem_status_out_bits_status_sum), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mprv (_cmd_router_io_dmem_status_out_bits_status_mprv), // @[ZstdCompressor.scala:112:26]
.io_status_bits_xs (_cmd_router_io_dmem_status_out_bits_status_xs), // @[ZstdCompressor.scala:112:26]
.io_status_bits_fs (_cmd_router_io_dmem_status_out_bits_status_fs), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mpp (_cmd_router_io_dmem_status_out_bits_status_mpp), // @[ZstdCompressor.scala:112:26]
.io_status_bits_vs (_cmd_router_io_dmem_status_out_bits_status_vs), // @[ZstdCompressor.scala:112:26]
.io_status_bits_spp (_cmd_router_io_dmem_status_out_bits_status_spp), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mpie (_cmd_router_io_dmem_status_out_bits_status_mpie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_ube (_cmd_router_io_dmem_status_out_bits_status_ube), // @[ZstdCompressor.scala:112:26]
.io_status_bits_spie (_cmd_router_io_dmem_status_out_bits_status_spie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_upie (_cmd_router_io_dmem_status_out_bits_status_upie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_mie (_cmd_router_io_dmem_status_out_bits_status_mie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_hie (_cmd_router_io_dmem_status_out_bits_status_hie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_sie (_cmd_router_io_dmem_status_out_bits_status_sie), // @[ZstdCompressor.scala:112:26]
.io_status_bits_uie (_cmd_router_io_dmem_status_out_bits_status_uie) // @[ZstdCompressor.scala:112:26]
); // @[ZstdCompressor.scala:91:37]
TLWidthWidget32_17 widget_17 ( // @[WidthWidget.scala:230:28]
.clock (clock),
.reset (reset),
.auto_anon_in_a_ready (_widget_17_auto_anon_in_a_ready),
.auto_anon_in_a_valid (_l2_raw_lit_writer_auto_master_out_a_valid), // @[ZstdCompressor.scala:91:37]
.auto_anon_in_a_bits_opcode (_l2_raw_lit_writer_auto_master_out_a_bits_opcode), // @[ZstdCompressor.scala:91:37]
.auto_anon_in_a_bits_param (_l2_raw_lit_writer_auto_master_out_a_bits_param), // @[ZstdCompressor.scala:91:37]
.auto_anon_in_a_bits_size (_l2_raw_lit_writer_auto_master_out_a_bits_size), // @[ZstdCompressor.scala:91:37]
.auto_anon_in_a_bits_source (_l2_raw_lit_writer_auto_master_out_a_bits_source), // @[ZstdCompressor.scala:91:37]
.auto_anon_in_a_bits_address (_l2_raw_lit_writer_auto_master_out_a_bits_address), // @[ZstdCompressor.scala:91:37]
.auto_anon_in_a_bits_mask (_l2_raw_lit_writer_auto_master_out_a_bits_mask), // @[ZstdCompressor.scala:91:37]
.auto_anon_in_a_bits_data (_l2_raw_lit_writer_auto_master_out_a_bits_data), // @[ZstdCompressor.scala:91:37]
.auto_anon_in_a_bits_corrupt (_l2_raw_lit_writer_auto_master_out_a_bits_corrupt), // @[ZstdCompressor.scala:91:37]
.auto_anon_in_d_ready (_l2_raw_lit_writer_auto_master_out_d_ready), // @[ZstdCompressor.scala:91:37]
.auto_anon_in_d_valid (_widget_17_auto_anon_in_d_valid),
.auto_anon_in_d_bits_opcode (_widget_17_auto_anon_in_d_bits_opcode),
.auto_anon_in_d_bits_param (_widget_17_auto_anon_in_d_bits_param),
.auto_anon_in_d_bits_size (_widget_17_auto_anon_in_d_bits_size),
.auto_anon_in_d_bits_source (_widget_17_auto_anon_in_d_bits_source),
.auto_anon_in_d_bits_sink (_widget_17_auto_anon_in_d_bits_sink),
.auto_anon_in_d_bits_denied (_widget_17_auto_anon_in_d_bits_denied),
.auto_anon_in_d_bits_data (_widget_17_auto_anon_in_d_bits_data),
.auto_anon_in_d_bits_corrupt (_widget_17_auto_anon_in_d_bits_corrupt),
.auto_anon_out_a_ready (x1_tlNodeIn_16_a_ready), // @[MixedNode.scala:551:17]
.auto_anon_out_a_valid (x1_tlNodeIn_16_a_valid),
.auto_anon_out_a_bits_opcode (x1_tlNodeIn_16_a_bits_opcode),
.auto_anon_out_a_bits_param (x1_tlNodeIn_16_a_bits_param),
.auto_anon_out_a_bits_size (x1_tlNodeIn_16_a_bits_size),
.auto_anon_out_a_bits_source (x1_tlNodeIn_16_a_bits_source),
.auto_anon_out_a_bits_address (x1_tlNodeIn_16_a_bits_address),
.auto_anon_out_a_bits_mask (x1_tlNodeIn_16_a_bits_mask),
.auto_anon_out_a_bits_data (x1_tlNodeIn_16_a_bits_data),
.auto_anon_out_a_bits_corrupt (x1_tlNodeIn_16_a_bits_corrupt),
.auto_anon_out_d_ready (x1_tlNodeIn_16_d_ready),
.auto_anon_out_d_valid (x1_tlNodeIn_16_d_valid), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_opcode (x1_tlNodeIn_16_d_bits_opcode), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_param (x1_tlNodeIn_16_d_bits_param), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_size (x1_tlNodeIn_16_d_bits_size), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_source (x1_tlNodeIn_16_d_bits_source), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_sink (x1_tlNodeIn_16_d_bits_sink), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_denied (x1_tlNodeIn_16_d_bits_denied), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_data (x1_tlNodeIn_16_d_bits_data), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_corrupt (x1_tlNodeIn_16_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[WidthWidget.scala:230:28]
ZstdCompressorCommandRouter cmd_router ( // @[ZstdCompressor.scala:112:26]
.clock (clock),
.reset (reset),
.io_rocc_in_ready (io_cmd_ready_0),
.io_rocc_in_valid (io_cmd_valid_0), // @[ZstdCompressor.scala:95:7]
.io_rocc_in_bits_inst_funct (io_cmd_bits_inst_funct_0), // @[ZstdCompressor.scala:95:7]
.io_rocc_in_bits_inst_rs2 (io_cmd_bits_inst_rs2_0), // @[ZstdCompressor.scala:95:7]
.io_rocc_in_bits_inst_rs1 (io_cmd_bits_inst_rs1_0), // @[ZstdCompressor.scala:95:7]
.io_rocc_in_bits_inst_xd (io_cmd_bits_inst_xd_0), // @[ZstdCompressor.scala:95:7]
.io_rocc_in_bits_inst_xs1 (io_cmd_bits_inst_xs1_0), // @[ZstdCompressor.scala:95:7]
.io_rocc_in_bits_inst_xs2 (io_cmd_bits_inst_xs2_0), // @[ZstdCompressor.scala:95:7]
.io_rocc_in_bits_inst_rd (io_cmd_bits_inst_rd_0), // @[ZstdCompressor.scala:95:7]
.io_rocc_in_bits_inst_opcode (io_cmd_bits_inst_opcode_0), // @[ZstdCompressor.scala:95:7]
.io_rocc_in_bits_rs1 (io_cmd_bits_rs1_0), // @[ZstdCompressor.scala:95:7]
.io_rocc_in_bits_rs2 (io_cmd_bits_rs2_0), // @[ZstdCompressor.scala:95:7]
.io_rocc_in_bits_status_debug (io_cmd_bits_status_debug_0), // @[ZstdCompressor.scala:95:7]
.io_rocc_in_bits_status_cease (io_cmd_bits_status_cease_0), // @[ZstdCompressor.scala:95:7]
.io_rocc_in_bits_status_wfi (io_cmd_bits_status_wfi_0), // @[ZstdCompressor.scala:95:7]
.io_rocc_in_bits_status_isa (io_cmd_bits_status_isa_0), // @[ZstdCompressor.scala:95:7]
.io_rocc_in_bits_status_dprv (io_cmd_bits_status_dprv_0), // @[ZstdCompressor.scala:95:7]
.io_rocc_in_bits_status_dv (io_cmd_bits_status_dv_0), // @[ZstdCompressor.scala:95:7]
.io_rocc_in_bits_status_prv (io_cmd_bits_status_prv_0), // @[ZstdCompressor.scala:95:7]
.io_rocc_in_bits_status_v (io_cmd_bits_status_v_0), // @[ZstdCompressor.scala:95:7]
.io_rocc_in_bits_status_sd (io_cmd_bits_status_sd_0), // @[ZstdCompressor.scala:95:7]
.io_rocc_in_bits_status_zero2 (io_cmd_bits_status_zero2_0), // @[ZstdCompressor.scala:95:7]
.io_rocc_in_bits_status_mpv (io_cmd_bits_status_mpv_0), // @[ZstdCompressor.scala:95:7]
.io_rocc_in_bits_status_gva (io_cmd_bits_status_gva_0), // @[ZstdCompressor.scala:95:7]
.io_rocc_in_bits_status_mbe (io_cmd_bits_status_mbe_0), // @[ZstdCompressor.scala:95:7]
.io_rocc_in_bits_status_sbe (io_cmd_bits_status_sbe_0), // @[ZstdCompressor.scala:95:7]
.io_rocc_in_bits_status_sxl (io_cmd_bits_status_sxl_0), // @[ZstdCompressor.scala:95:7]
.io_rocc_in_bits_status_uxl (io_cmd_bits_status_uxl_0), // @[ZstdCompressor.scala:95:7]
.io_rocc_in_bits_status_sd_rv32 (io_cmd_bits_status_sd_rv32_0), // @[ZstdCompressor.scala:95:7]
.io_rocc_in_bits_status_zero1 (io_cmd_bits_status_zero1_0), // @[ZstdCompressor.scala:95:7]
.io_rocc_in_bits_status_tsr (io_cmd_bits_status_tsr_0), // @[ZstdCompressor.scala:95:7]
.io_rocc_in_bits_status_tw (io_cmd_bits_status_tw_0), // @[ZstdCompressor.scala:95:7]
.io_rocc_in_bits_status_tvm (io_cmd_bits_status_tvm_0), // @[ZstdCompressor.scala:95:7]
.io_rocc_in_bits_status_mxr (io_cmd_bits_status_mxr_0), // @[ZstdCompressor.scala:95:7]
.io_rocc_in_bits_status_sum (io_cmd_bits_status_sum_0), // @[ZstdCompressor.scala:95:7]
.io_rocc_in_bits_status_mprv (io_cmd_bits_status_mprv_0), // @[ZstdCompressor.scala:95:7]
.io_rocc_in_bits_status_xs (io_cmd_bits_status_xs_0), // @[ZstdCompressor.scala:95:7]
.io_rocc_in_bits_status_fs (io_cmd_bits_status_fs_0), // @[ZstdCompressor.scala:95:7]
.io_rocc_in_bits_status_mpp (io_cmd_bits_status_mpp_0), // @[ZstdCompressor.scala:95:7]
.io_rocc_in_bits_status_vs (io_cmd_bits_status_vs_0), // @[ZstdCompressor.scala:95:7]
.io_rocc_in_bits_status_spp (io_cmd_bits_status_spp_0), // @[ZstdCompressor.scala:95:7]
.io_rocc_in_bits_status_mpie (io_cmd_bits_status_mpie_0), // @[ZstdCompressor.scala:95:7]
.io_rocc_in_bits_status_ube (io_cmd_bits_status_ube_0), // @[ZstdCompressor.scala:95:7]
.io_rocc_in_bits_status_spie (io_cmd_bits_status_spie_0), // @[ZstdCompressor.scala:95:7]
.io_rocc_in_bits_status_upie (io_cmd_bits_status_upie_0), // @[ZstdCompressor.scala:95:7]
.io_rocc_in_bits_status_mie (io_cmd_bits_status_mie_0), // @[ZstdCompressor.scala:95:7]
.io_rocc_in_bits_status_hie (io_cmd_bits_status_hie_0), // @[ZstdCompressor.scala:95:7]
.io_rocc_in_bits_status_sie (io_cmd_bits_status_sie_0), // @[ZstdCompressor.scala:95:7]
.io_rocc_in_bits_status_uie (io_cmd_bits_status_uie_0), // @[ZstdCompressor.scala:95:7]
.io_rocc_out_ready (io_resp_ready_0), // @[ZstdCompressor.scala:95:7]
.io_rocc_out_valid (io_resp_valid_0),
.io_rocc_out_bits_rd (io_resp_bits_rd_0),
.io_rocc_out_bits_data (io_resp_bits_data_0),
.io_dmem_status_out_valid (_cmd_router_io_dmem_status_out_valid),
.io_dmem_status_out_bits_status_debug (_cmd_router_io_dmem_status_out_bits_status_debug),
.io_dmem_status_out_bits_status_cease (_cmd_router_io_dmem_status_out_bits_status_cease),
.io_dmem_status_out_bits_status_wfi (_cmd_router_io_dmem_status_out_bits_status_wfi),
.io_dmem_status_out_bits_status_isa (_cmd_router_io_dmem_status_out_bits_status_isa),
.io_dmem_status_out_bits_status_dprv (_cmd_router_io_dmem_status_out_bits_status_dprv),
.io_dmem_status_out_bits_status_dv (_cmd_router_io_dmem_status_out_bits_status_dv),
.io_dmem_status_out_bits_status_prv (_cmd_router_io_dmem_status_out_bits_status_prv),
.io_dmem_status_out_bits_status_v (_cmd_router_io_dmem_status_out_bits_status_v),
.io_dmem_status_out_bits_status_sd (_cmd_router_io_dmem_status_out_bits_status_sd),
.io_dmem_status_out_bits_status_zero2 (_cmd_router_io_dmem_status_out_bits_status_zero2),
.io_dmem_status_out_bits_status_mpv (_cmd_router_io_dmem_status_out_bits_status_mpv),
.io_dmem_status_out_bits_status_gva (_cmd_router_io_dmem_status_out_bits_status_gva),
.io_dmem_status_out_bits_status_mbe (_cmd_router_io_dmem_status_out_bits_status_mbe),
.io_dmem_status_out_bits_status_sbe (_cmd_router_io_dmem_status_out_bits_status_sbe),
.io_dmem_status_out_bits_status_sxl (_cmd_router_io_dmem_status_out_bits_status_sxl),
.io_dmem_status_out_bits_status_uxl (_cmd_router_io_dmem_status_out_bits_status_uxl),
.io_dmem_status_out_bits_status_sd_rv32 (_cmd_router_io_dmem_status_out_bits_status_sd_rv32),
.io_dmem_status_out_bits_status_zero1 (_cmd_router_io_dmem_status_out_bits_status_zero1),
.io_dmem_status_out_bits_status_tsr (_cmd_router_io_dmem_status_out_bits_status_tsr),
.io_dmem_status_out_bits_status_tw (_cmd_router_io_dmem_status_out_bits_status_tw),
.io_dmem_status_out_bits_status_tvm (_cmd_router_io_dmem_status_out_bits_status_tvm),
.io_dmem_status_out_bits_status_mxr (_cmd_router_io_dmem_status_out_bits_status_mxr),
.io_dmem_status_out_bits_status_sum (_cmd_router_io_dmem_status_out_bits_status_sum),
.io_dmem_status_out_bits_status_mprv (_cmd_router_io_dmem_status_out_bits_status_mprv),
.io_dmem_status_out_bits_status_xs (_cmd_router_io_dmem_status_out_bits_status_xs),
.io_dmem_status_out_bits_status_fs (_cmd_router_io_dmem_status_out_bits_status_fs),
.io_dmem_status_out_bits_status_mpp (_cmd_router_io_dmem_status_out_bits_status_mpp),
.io_dmem_status_out_bits_status_vs (_cmd_router_io_dmem_status_out_bits_status_vs),
.io_dmem_status_out_bits_status_spp (_cmd_router_io_dmem_status_out_bits_status_spp),
.io_dmem_status_out_bits_status_mpie (_cmd_router_io_dmem_status_out_bits_status_mpie),
.io_dmem_status_out_bits_status_ube (_cmd_router_io_dmem_status_out_bits_status_ube),
.io_dmem_status_out_bits_status_spie (_cmd_router_io_dmem_status_out_bits_status_spie),
.io_dmem_status_out_bits_status_upie (_cmd_router_io_dmem_status_out_bits_status_upie),
.io_dmem_status_out_bits_status_mie (_cmd_router_io_dmem_status_out_bits_status_mie),
.io_dmem_status_out_bits_status_hie (_cmd_router_io_dmem_status_out_bits_status_hie),
.io_dmem_status_out_bits_status_sie (_cmd_router_io_dmem_status_out_bits_status_sie),
.io_dmem_status_out_bits_status_uie (_cmd_router_io_dmem_status_out_bits_status_uie),
.io_sfence_out (_cmd_router_io_sfence_out),
.io_ALGORITHM (_cmd_router_io_ALGORITHM),
.io_src_info_ready (_controller_io_src_info_ready), // @[ZstdCompressor.scala:116:26]
.io_src_info_valid (_cmd_router_io_src_info_valid),
.io_src_info_bits_ip (_cmd_router_io_src_info_bits_ip),
.io_src_info_bits_isize (_cmd_router_io_src_info_bits_isize),
.io_dst_info_ready (_controller_io_dst_info_ready), // @[ZstdCompressor.scala:116:26]
.io_dst_info_valid (_cmd_router_io_dst_info_valid),
.io_dst_info_bits_op (_cmd_router_io_dst_info_bits_op),
.io_dst_info_bits_cmpflag (_cmd_router_io_dst_info_bits_cmpflag),
.io_buff_info_lit_ready (_controller_io_buff_info_lit_ready), // @[ZstdCompressor.scala:116:26]
.io_buff_info_lit_valid (_cmd_router_io_buff_info_lit_valid),
.io_buff_info_lit_bits_ip (_cmd_router_io_buff_info_lit_bits_ip),
.io_buff_info_lit_bits_isize (_cmd_router_io_buff_info_lit_bits_isize),
.io_buff_info_seq_ready (_controller_io_buff_info_seq_ready), // @[ZstdCompressor.scala:116:26]
.io_buff_info_seq_valid (_cmd_router_io_buff_info_seq_valid),
.io_buff_info_seq_bits_ip (_cmd_router_io_buff_info_seq_bits_ip),
.io_buff_info_seq_bits_isize (_cmd_router_io_buff_info_seq_bits_isize),
.io_clevel_info_ready (_controller_io_clevel_info_ready), // @[ZstdCompressor.scala:116:26]
.io_clevel_info_valid (_cmd_router_io_clevel_info_valid),
.io_clevel_info_bits (_cmd_router_io_clevel_info_bits),
.io_SNAPPY_MAX_OFFSET_ALLOWED (_cmd_router_io_SNAPPY_MAX_OFFSET_ALLOWED),
.io_SNAPPY_RUNTIME_HT_NUM_ENTRIES_LOG2 (_cmd_router_io_SNAPPY_RUNTIME_HT_NUM_ENTRIES_LOG2),
.io_LATENCY_INJECTION_CYCLES (_cmd_router_io_LATENCY_INJECTION_CYCLES),
.io_HAS_INTERMEDIATE_CACHE (_cmd_router_io_HAS_INTERMEDIATE_CACHE),
.io_zstd_finished_cnt_ready (_cmd_router_io_zstd_finished_cnt_ready),
.io_zstd_finished_cnt_valid (_controller_io_zstd_finished_cnt_valid), // @[ZstdCompressor.scala:116:26]
.io_zstd_finished_cnt_bits (_controller_io_zstd_finished_cnt_bits), // @[ZstdCompressor.scala:116:26]
.io_snappy_finished_cnt_ready (_cmd_router_io_snappy_finished_cnt_ready),
.io_snappy_finished_cnt_valid (_controller_io_snappy_finished_cnt_valid), // @[ZstdCompressor.scala:116:26]
.io_snappy_finished_cnt_bits (_controller_io_snappy_finished_cnt_bits) // @[ZstdCompressor.scala:116:26]
); // @[ZstdCompressor.scala:112:26]
CompressorController controller ( // @[ZstdCompressor.scala:116:26]
.clock (clock),
.reset (reset),
.io_ALGORITHM (_cmd_router_io_ALGORITHM), // @[ZstdCompressor.scala:112:26]
.io_SNAPPY_MAX_OFFSET_ALLOWED (_cmd_router_io_SNAPPY_MAX_OFFSET_ALLOWED), // @[ZstdCompressor.scala:112:26]
.io_SNAPPY_RUNTIME_HT_NUM_ENTRIES_LOG2 (_cmd_router_io_SNAPPY_RUNTIME_HT_NUM_ENTRIES_LOG2), // @[ZstdCompressor.scala:112:26]
.io_src_info_ready (_controller_io_src_info_ready),
.io_src_info_valid (_cmd_router_io_src_info_valid), // @[ZstdCompressor.scala:112:26]
.io_src_info_bits_ip (_cmd_router_io_src_info_bits_ip), // @[ZstdCompressor.scala:112:26]
.io_src_info_bits_isize (_cmd_router_io_src_info_bits_isize), // @[ZstdCompressor.scala:112:26]
.io_dst_info_ready (_controller_io_dst_info_ready),
.io_dst_info_valid (_cmd_router_io_dst_info_valid), // @[ZstdCompressor.scala:112:26]
.io_dst_info_bits_op (_cmd_router_io_dst_info_bits_op), // @[ZstdCompressor.scala:112:26]
.io_dst_info_bits_cmpflag (_cmd_router_io_dst_info_bits_cmpflag), // @[ZstdCompressor.scala:112:26]
.io_buff_info_lit_ready (_controller_io_buff_info_lit_ready),
.io_buff_info_lit_valid (_cmd_router_io_buff_info_lit_valid), // @[ZstdCompressor.scala:112:26]
.io_buff_info_lit_bits_ip (_cmd_router_io_buff_info_lit_bits_ip), // @[ZstdCompressor.scala:112:26]
.io_buff_info_lit_bits_isize (_cmd_router_io_buff_info_lit_bits_isize), // @[ZstdCompressor.scala:112:26]
.io_buff_info_seq_ready (_controller_io_buff_info_seq_ready),
.io_buff_info_seq_valid (_cmd_router_io_buff_info_seq_valid), // @[ZstdCompressor.scala:112:26]
.io_buff_info_seq_bits_ip (_cmd_router_io_buff_info_seq_bits_ip), // @[ZstdCompressor.scala:112:26]
.io_buff_info_seq_bits_isize (_cmd_router_io_buff_info_seq_bits_isize), // @[ZstdCompressor.scala:112:26]
.io_clevel_info_ready (_controller_io_clevel_info_ready),
.io_clevel_info_valid (_cmd_router_io_clevel_info_valid), // @[ZstdCompressor.scala:112:26]
.io_clevel_info_bits (_cmd_router_io_clevel_info_bits), // @[ZstdCompressor.scala:112:26]
.io_zstd_control_l2io_fhdr_l2userif_req_ready (_l2_fhdr_writer_io_userif_req_ready), // @[ZstdCompressor.scala:38:34]
.io_zstd_control_l2io_fhdr_l2userif_req_valid (_controller_io_zstd_control_l2io_fhdr_l2userif_req_valid),
.io_zstd_control_l2io_fhdr_l2userif_req_bits_addr (_controller_io_zstd_control_l2io_fhdr_l2userif_req_bits_addr),
.io_zstd_control_l2io_fhdr_l2userif_req_bits_size (_controller_io_zstd_control_l2io_fhdr_l2userif_req_bits_size),
.io_zstd_control_l2io_fhdr_l2userif_req_bits_data (_controller_io_zstd_control_l2io_fhdr_l2userif_req_bits_data),
.io_zstd_control_l2io_fhdr_l2userif_resp_valid (_l2_fhdr_writer_io_userif_resp_valid), // @[ZstdCompressor.scala:38:34]
.io_zstd_control_l2io_fhdr_l2userif_resp_bits_data (_l2_fhdr_writer_io_userif_resp_bits_data), // @[ZstdCompressor.scala:38:34]
.io_zstd_control_l2io_fhdr_l2userif_no_memops_inflight (_l2_fhdr_writer_io_userif_no_memops_inflight), // @[ZstdCompressor.scala:38:34]
.io_zstd_control_l2io_bhdr_l2userif_req_ready (_l2_bhdr_writer_io_userif_req_ready), // @[ZstdCompressor.scala:42:34]
.io_zstd_control_l2io_bhdr_l2userif_req_valid (_controller_io_zstd_control_l2io_bhdr_l2userif_req_valid),
.io_zstd_control_l2io_bhdr_l2userif_req_bits_addr (_controller_io_zstd_control_l2io_bhdr_l2userif_req_bits_addr),
.io_zstd_control_l2io_bhdr_l2userif_req_bits_size (_controller_io_zstd_control_l2io_bhdr_l2userif_req_bits_size),
.io_zstd_control_l2io_bhdr_l2userif_req_bits_data (_controller_io_zstd_control_l2io_bhdr_l2userif_req_bits_data),
.io_zstd_control_l2io_bhdr_l2userif_resp_valid (_l2_bhdr_writer_io_userif_resp_valid), // @[ZstdCompressor.scala:42:34]
.io_zstd_control_l2io_bhdr_l2userif_resp_bits_data (_l2_bhdr_writer_io_userif_resp_bits_data), // @[ZstdCompressor.scala:42:34]
.io_zstd_control_l2io_bhdr_l2userif_no_memops_inflight (_l2_bhdr_writer_io_userif_no_memops_inflight), // @[ZstdCompressor.scala:42:34]
.io_zstd_control_litcpy_src_ready (_lit_compressor_io_src_info_ready), // @[ZstdCompressor.scala:140:30]
.io_zstd_control_litcpy_src_valid (_controller_io_zstd_control_litcpy_src_valid),
.io_zstd_control_litcpy_src_bits_ip (_controller_io_zstd_control_litcpy_src_bits_ip),
.io_zstd_control_litcpy_src_bits_isize (_controller_io_zstd_control_litcpy_src_bits_isize),
.io_zstd_control_litcpy_src2_ready (_lit_compressor_io_src_info2_ready), // @[ZstdCompressor.scala:140:30]
.io_zstd_control_litcpy_src2_valid (_controller_io_zstd_control_litcpy_src2_valid),
.io_zstd_control_litcpy_src2_bits_ip (_controller_io_zstd_control_litcpy_src2_bits_ip),
.io_zstd_control_litcpy_src2_bits_isize (_controller_io_zstd_control_litcpy_src2_bits_isize),
.io_zstd_control_litcpy_dst_ready (_lit_compressor_io_dst_info_ready), // @[ZstdCompressor.scala:140:30]
.io_zstd_control_litcpy_dst_valid (_controller_io_zstd_control_litcpy_dst_valid),
.io_zstd_control_litcpy_dst_bits_op (_controller_io_zstd_control_litcpy_dst_bits_op),
.io_zstd_control_litcpy_dst_bits_cmpflag (_controller_io_zstd_control_litcpy_dst_bits_cmpflag),
.io_zstd_control_litcpy_dst_bits_cmpval (_controller_io_zstd_control_litcpy_dst_bits_cmpval),
.io_zstd_control_litbytes_written_ready (_controller_io_zstd_control_litbytes_written_ready),
.io_zstd_control_litbytes_written_valid (_lit_compressor_io_bytes_written_valid), // @[ZstdCompressor.scala:140:30]
.io_zstd_control_litbytes_written_bits (_lit_compressor_io_bytes_written_bits), // @[ZstdCompressor.scala:140:30]
.io_zstd_control_raw_lit_src_ready (_raw_lit_encoder_io_src_info_ready), // @[ZstdCompressor.scala:154:31]
.io_zstd_control_raw_lit_src_valid (_controller_io_zstd_control_raw_lit_src_valid),
.io_zstd_control_raw_lit_src_bits_ip (_controller_io_zstd_control_raw_lit_src_bits_ip),
.io_zstd_control_raw_lit_src_bits_isize (_controller_io_zstd_control_raw_lit_src_bits_isize),
.io_zstd_control_raw_lit_dst_ready (_raw_lit_encoder_io_dst_info_ready), // @[ZstdCompressor.scala:154:31]
.io_zstd_control_raw_lit_dst_valid (_controller_io_zstd_control_raw_lit_dst_valid),
.io_zstd_control_raw_lit_dst_bits_op (_controller_io_zstd_control_raw_lit_dst_bits_op),
.io_zstd_control_raw_lit_dst_bits_cmpflag (_controller_io_zstd_control_raw_lit_dst_bits_cmpflag),
.io_zstd_control_raw_lit_dst_bits_cmpval (_controller_io_zstd_control_raw_lit_dst_bits_cmpval),
.io_zstd_control_raw_litbytes_written_ready (_controller_io_zstd_control_raw_litbytes_written_ready),
.io_zstd_control_raw_litbytes_written_valid (_raw_lit_encoder_io_bytes_written_valid), // @[ZstdCompressor.scala:154:31]
.io_zstd_control_raw_litbytes_written_bits (_raw_lit_encoder_io_bytes_written_bits), // @[ZstdCompressor.scala:154:31]
.io_zstd_control_raw_block_src_ready (_raw_block_encoder_io_src_info_ready), // @[ZstdCompressor.scala:161:33]
.io_zstd_control_raw_block_src_valid (_controller_io_zstd_control_raw_block_src_valid),
.io_zstd_control_raw_block_src_bits_ip (_controller_io_zstd_control_raw_block_src_bits_ip),
.io_zstd_control_raw_block_src_bits_isize (_controller_io_zstd_control_raw_block_src_bits_isize),
.io_zstd_control_raw_block_dst_ready (_raw_block_encoder_io_dst_info_ready), // @[ZstdCompressor.scala:161:33]
.io_zstd_control_raw_block_dst_valid (_controller_io_zstd_control_raw_block_dst_valid),
.io_zstd_control_raw_block_dst_bits_op (_controller_io_zstd_control_raw_block_dst_bits_op),
.io_zstd_control_raw_block_dst_bits_cmpflag (_controller_io_zstd_control_raw_block_dst_bits_cmpflag),
.io_zstd_control_raw_block_dst_bits_cmpval (_controller_io_zstd_control_raw_block_dst_bits_cmpval),
.io_zstd_control_raw_blockbytes_written_ready (_controller_io_zstd_control_raw_blockbytes_written_ready),
.io_zstd_control_raw_blockbytes_written_valid (_raw_block_encoder_io_bytes_written_valid), // @[ZstdCompressor.scala:161:33]
.io_zstd_control_raw_blockbytes_written_bits (_raw_block_encoder_io_bytes_written_bits), // @[ZstdCompressor.scala:161:33]
.io_zstd_control_seqcpy_src_ready (_seq_compressor_io_src_info_ready), // @[ZstdCompressor.scala:168:30]
.io_zstd_control_seqcpy_src_valid (_controller_io_zstd_control_seqcpy_src_valid),
.io_zstd_control_seqcpy_src_bits_ip (_controller_io_zstd_control_seqcpy_src_bits_ip),
.io_zstd_control_seqcpy_src_bits_isize (_controller_io_zstd_control_seqcpy_src_bits_isize),
.io_zstd_control_seqcpy_dst_ready (_seq_compressor_io_dst_info_ready), // @[ZstdCompressor.scala:168:30]
.io_zstd_control_seqcpy_dst_valid (_controller_io_zstd_control_seqcpy_dst_valid),
.io_zstd_control_seqcpy_dst_bits_op (_controller_io_zstd_control_seqcpy_dst_bits_op),
.io_zstd_control_seqcpy_dst_bits_cmpflag (_controller_io_zstd_control_seqcpy_dst_bits_cmpflag),
.io_zstd_control_seqcpy_dst_bits_cmpval (_controller_io_zstd_control_seqcpy_dst_bits_cmpval),
.io_zstd_control_seqbytes_written_ready (_controller_io_zstd_control_seqbytes_written_ready),
.io_zstd_control_seqbytes_written_valid (_seq_compressor_io_bytes_written_valid), // @[ZstdCompressor.scala:168:30]
.io_zstd_control_seqbytes_written_bits (_seq_compressor_io_bytes_written_bits), // @[ZstdCompressor.scala:168:30]
.io_shared_control_mf_src_compress_src_info_ready (_matchfinder_io_src_compress_src_info_ready), // @[ZstdCompressor.scala:129:27]
.io_shared_control_mf_src_compress_src_info_valid (_controller_io_shared_control_mf_src_compress_src_info_valid),
.io_shared_control_mf_src_compress_src_info_bits_ip (_controller_io_shared_control_mf_src_compress_src_info_bits_ip),
.io_shared_control_mf_src_compress_src_info_bits_isize (_controller_io_shared_control_mf_src_compress_src_info_bits_isize),
.io_shared_control_mf_src_compress_src_info2_ready (_matchfinder_io_src_compress_src_info2_ready), // @[ZstdCompressor.scala:129:27]
.io_shared_control_mf_src_compress_src_info2_valid (_controller_io_shared_control_mf_src_compress_src_info2_valid),
.io_shared_control_mf_src_compress_src_info2_bits_ip (_controller_io_shared_control_mf_src_compress_src_info2_bits_ip),
.io_shared_control_mf_src_compress_src_info2_bits_isize (_controller_io_shared_control_mf_src_compress_src_info2_bits_isize),
.io_shared_control_mf_dst_lit_dst_info_ready (_matchfinder_io_dst_lit_dst_info_ready), // @[ZstdCompressor.scala:129:27]
.io_shared_control_mf_dst_lit_dst_info_valid (_controller_io_shared_control_mf_dst_lit_dst_info_valid),
.io_shared_control_mf_dst_lit_dst_info_bits_op (_controller_io_shared_control_mf_dst_lit_dst_info_bits_op),
.io_shared_control_mf_dst_lit_dst_info_bits_cmpflag (_controller_io_shared_control_mf_dst_lit_dst_info_bits_cmpflag),
.io_shared_control_mf_dst_seq_dst_info_ready (_matchfinder_io_dst_seq_dst_info_ready), // @[ZstdCompressor.scala:129:27]
.io_shared_control_mf_dst_seq_dst_info_valid (_controller_io_shared_control_mf_dst_seq_dst_info_valid),
.io_shared_control_mf_dst_seq_dst_info_bits_op (_controller_io_shared_control_mf_dst_seq_dst_info_bits_op),
.io_shared_control_mf_dst_seq_dst_info_bits_cmpflag (_controller_io_shared_control_mf_dst_seq_dst_info_bits_cmpflag),
.io_shared_control_mf_buff_consumed_lit_consumed_bytes_ready (_controller_io_shared_control_mf_buff_consumed_lit_consumed_bytes_ready),
.io_shared_control_mf_buff_consumed_lit_consumed_bytes_valid (_matchfinder_io_buff_consumed_lit_consumed_bytes_valid), // @[ZstdCompressor.scala:129:27]
.io_shared_control_mf_buff_consumed_lit_consumed_bytes_bits (_matchfinder_io_buff_consumed_lit_consumed_bytes_bits), // @[ZstdCompressor.scala:129:27]
.io_shared_control_mf_buff_consumed_seq_consumed_bytes_ready (_controller_io_shared_control_mf_buff_consumed_seq_consumed_bytes_ready),
.io_shared_control_mf_buff_consumed_seq_consumed_bytes_valid (_matchfinder_io_buff_consumed_seq_consumed_bytes_valid), // @[ZstdCompressor.scala:129:27]
.io_shared_control_mf_buff_consumed_seq_consumed_bytes_bits (_matchfinder_io_buff_consumed_seq_consumed_bytes_bits), // @[ZstdCompressor.scala:129:27]
.io_zstd_finished_cnt_ready (_cmd_router_io_zstd_finished_cnt_ready), // @[ZstdCompressor.scala:112:26]
.io_zstd_finished_cnt_valid (_controller_io_zstd_finished_cnt_valid),
.io_zstd_finished_cnt_bits (_controller_io_zstd_finished_cnt_bits),
.io_snappy_finished_cnt_ready (_cmd_router_io_snappy_finished_cnt_ready), // @[ZstdCompressor.scala:112:26]
.io_snappy_finished_cnt_valid (_controller_io_snappy_finished_cnt_valid),
.io_snappy_finished_cnt_bits (_controller_io_snappy_finished_cnt_bits)
); // @[ZstdCompressor.scala:116:26]
ZstdMatchFinder matchfinder ( // @[ZstdCompressor.scala:129:27]
.clock (clock),
.reset (reset),
.io_l2io_memloader_userif_req_ready (_l2_mf_reader_io_userif_req_ready), // @[ZstdCompressor.scala:46:32]
.io_l2io_memloader_userif_req_valid (_matchfinder_io_l2io_memloader_userif_req_valid),
.io_l2io_memloader_userif_req_bits_addr (_matchfinder_io_l2io_memloader_userif_req_bits_addr),
.io_l2io_memloader_userif_resp_ready (_matchfinder_io_l2io_memloader_userif_resp_ready),
.io_l2io_memloader_userif_resp_valid (_l2_mf_reader_io_userif_resp_valid), // @[ZstdCompressor.scala:46:32]
.io_l2io_memloader_userif_resp_bits_data (_l2_mf_reader_io_userif_resp_bits_data), // @[ZstdCompressor.scala:46:32]
.io_l2io_memloader_userif_no_memops_inflight (_l2_mf_reader_io_userif_no_memops_inflight), // @[ZstdCompressor.scala:46:32]
.io_l2io_lit_memwriter_userif_req_ready (_l2_mf_litwriter_io_userif_req_ready), // @[ZstdCompressor.scala:52:35]
.io_l2io_lit_memwriter_userif_req_valid (_matchfinder_io_l2io_lit_memwriter_userif_req_valid),
.io_l2io_lit_memwriter_userif_req_bits_addr (_matchfinder_io_l2io_lit_memwriter_userif_req_bits_addr),
.io_l2io_lit_memwriter_userif_req_bits_size (_matchfinder_io_l2io_lit_memwriter_userif_req_bits_size),
.io_l2io_lit_memwriter_userif_req_bits_data (_matchfinder_io_l2io_lit_memwriter_userif_req_bits_data),
.io_l2io_lit_memwriter_userif_resp_valid (_l2_mf_litwriter_io_userif_resp_valid), // @[ZstdCompressor.scala:52:35]
.io_l2io_lit_memwriter_userif_resp_bits_data (_l2_mf_litwriter_io_userif_resp_bits_data), // @[ZstdCompressor.scala:52:35]
.io_l2io_lit_memwriter_userif_no_memops_inflight (_l2_mf_litwriter_io_userif_no_memops_inflight), // @[ZstdCompressor.scala:52:35]
.io_l2io_seq_memwriter_userif_req_ready (_l2_mf_seqwriter_io_userif_req_ready), // @[ZstdCompressor.scala:49:35]
.io_l2io_seq_memwriter_userif_req_valid (_matchfinder_io_l2io_seq_memwriter_userif_req_valid),
.io_l2io_seq_memwriter_userif_req_bits_addr (_matchfinder_io_l2io_seq_memwriter_userif_req_bits_addr),
.io_l2io_seq_memwriter_userif_req_bits_size (_matchfinder_io_l2io_seq_memwriter_userif_req_bits_size),
.io_l2io_seq_memwriter_userif_req_bits_data (_matchfinder_io_l2io_seq_memwriter_userif_req_bits_data),
.io_l2io_seq_memwriter_userif_resp_valid (_l2_mf_seqwriter_io_userif_resp_valid), // @[ZstdCompressor.scala:49:35]
.io_l2io_seq_memwriter_userif_resp_bits_data (_l2_mf_seqwriter_io_userif_resp_bits_data), // @[ZstdCompressor.scala:49:35]
.io_l2io_seq_memwriter_userif_no_memops_inflight (_l2_mf_seqwriter_io_userif_no_memops_inflight), // @[ZstdCompressor.scala:49:35]
.io_src_compress_src_info_ready (_matchfinder_io_src_compress_src_info_ready),
.io_src_compress_src_info_valid (_controller_io_shared_control_mf_src_compress_src_info_valid), // @[ZstdCompressor.scala:116:26]
.io_src_compress_src_info_bits_ip (_controller_io_shared_control_mf_src_compress_src_info_bits_ip), // @[ZstdCompressor.scala:116:26]
.io_src_compress_src_info_bits_isize (_controller_io_shared_control_mf_src_compress_src_info_bits_isize), // @[ZstdCompressor.scala:116:26]
.io_src_compress_src_info2_ready (_matchfinder_io_src_compress_src_info2_ready),
.io_src_compress_src_info2_valid (_controller_io_shared_control_mf_src_compress_src_info2_valid), // @[ZstdCompressor.scala:116:26]
.io_src_compress_src_info2_bits_ip (_controller_io_shared_control_mf_src_compress_src_info2_bits_ip), // @[ZstdCompressor.scala:116:26]
.io_src_compress_src_info2_bits_isize (_controller_io_shared_control_mf_src_compress_src_info2_bits_isize), // @[ZstdCompressor.scala:116:26]
.io_dst_lit_dst_info_ready (_matchfinder_io_dst_lit_dst_info_ready),
.io_dst_lit_dst_info_valid (_controller_io_shared_control_mf_dst_lit_dst_info_valid), // @[ZstdCompressor.scala:116:26]
.io_dst_lit_dst_info_bits_op (_controller_io_shared_control_mf_dst_lit_dst_info_bits_op), // @[ZstdCompressor.scala:116:26]
.io_dst_lit_dst_info_bits_cmpflag (_controller_io_shared_control_mf_dst_lit_dst_info_bits_cmpflag), // @[ZstdCompressor.scala:116:26]
.io_dst_seq_dst_info_ready (_matchfinder_io_dst_seq_dst_info_ready),
.io_dst_seq_dst_info_valid (_controller_io_shared_control_mf_dst_seq_dst_info_valid), // @[ZstdCompressor.scala:116:26]
.io_dst_seq_dst_info_bits_op (_controller_io_shared_control_mf_dst_seq_dst_info_bits_op), // @[ZstdCompressor.scala:116:26]
.io_dst_seq_dst_info_bits_cmpflag (_controller_io_shared_control_mf_dst_seq_dst_info_bits_cmpflag), // @[ZstdCompressor.scala:116:26]
.io_buff_consumed_lit_consumed_bytes_ready (_controller_io_shared_control_mf_buff_consumed_lit_consumed_bytes_ready), // @[ZstdCompressor.scala:116:26]
.io_buff_consumed_lit_consumed_bytes_valid (_matchfinder_io_buff_consumed_lit_consumed_bytes_valid),
.io_buff_consumed_lit_consumed_bytes_bits (_matchfinder_io_buff_consumed_lit_consumed_bytes_bits),
.io_buff_consumed_seq_consumed_bytes_ready (_controller_io_shared_control_mf_buff_consumed_seq_consumed_bytes_ready), // @[ZstdCompressor.scala:116:26]
.io_buff_consumed_seq_consumed_bytes_valid (_matchfinder_io_buff_consumed_seq_consumed_bytes_valid),
.io_buff_consumed_seq_consumed_bytes_bits (_matchfinder_io_buff_consumed_seq_consumed_bytes_bits),
.io_MAX_OFFSET_ALLOWED (_cmd_router_io_SNAPPY_MAX_OFFSET_ALLOWED), // @[ZstdCompressor.scala:112:26]
.io_RUNTIME_HT_NUM_ENTRIES_LOG2 (_cmd_router_io_SNAPPY_RUNTIME_HT_NUM_ENTRIES_LOG2), // @[ZstdCompressor.scala:112:26]
.io_ALGORITHM (_cmd_router_io_ALGORITHM) // @[ZstdCompressor.scala:112:26]
); // @[ZstdCompressor.scala:129:27]
ZstdLiteralEncoder lit_compressor ( // @[ZstdCompressor.scala:140:30]
.clock (clock),
.reset (reset),
.io_src_info_ready (_lit_compressor_io_src_info_ready),
.io_src_info_valid (_controller_io_zstd_control_litcpy_src_valid), // @[ZstdCompressor.scala:116:26]
.io_src_info_bits_ip (_controller_io_zstd_control_litcpy_src_bits_ip), // @[ZstdCompressor.scala:116:26]
.io_src_info_bits_isize (_controller_io_zstd_control_litcpy_src_bits_isize), // @[ZstdCompressor.scala:116:26]
.io_src_info2_ready (_lit_compressor_io_src_info2_ready),
.io_src_info2_valid (_controller_io_zstd_control_litcpy_src2_valid), // @[ZstdCompressor.scala:116:26]
.io_src_info2_bits_ip (_controller_io_zstd_control_litcpy_src2_bits_ip), // @[ZstdCompressor.scala:116:26]
.io_src_info2_bits_isize (_controller_io_zstd_control_litcpy_src2_bits_isize), // @[ZstdCompressor.scala:116:26]
.io_dst_info_ready (_lit_compressor_io_dst_info_ready),
.io_dst_info_valid (_controller_io_zstd_control_litcpy_dst_valid), // @[ZstdCompressor.scala:116:26]
.io_dst_info_bits_op (_controller_io_zstd_control_litcpy_dst_bits_op), // @[ZstdCompressor.scala:116:26]
.io_dst_info_bits_cmpflag (_controller_io_zstd_control_litcpy_dst_bits_cmpflag), // @[ZstdCompressor.scala:116:26]
.io_dst_info_bits_cmpval (_controller_io_zstd_control_litcpy_dst_bits_cmpval), // @[ZstdCompressor.scala:116:26]
.io_bytes_written_ready (_controller_io_zstd_control_litbytes_written_ready), // @[ZstdCompressor.scala:116:26]
.io_bytes_written_valid (_lit_compressor_io_bytes_written_valid),
.io_bytes_written_bits (_lit_compressor_io_bytes_written_bits),
.io_l2if_lit_reader_req_ready (_l2_huf_lit_reader_io_userif_req_ready), // @[ZstdCompressor.scala:55:37]
.io_l2if_lit_reader_req_valid (_lit_compressor_io_l2if_lit_reader_req_valid),
.io_l2if_lit_reader_req_bits_addr (_lit_compressor_io_l2if_lit_reader_req_bits_addr),
.io_l2if_lit_reader_req_bits_size (_lit_compressor_io_l2if_lit_reader_req_bits_size),
.io_l2if_lit_reader_req_bits_data (_lit_compressor_io_l2if_lit_reader_req_bits_data),
.io_l2if_lit_reader_req_bits_cmd (_lit_compressor_io_l2if_lit_reader_req_bits_cmd),
.io_l2if_lit_reader_resp_ready (_lit_compressor_io_l2if_lit_reader_resp_ready),
.io_l2if_lit_reader_resp_valid (_l2_huf_lit_reader_io_userif_resp_valid), // @[ZstdCompressor.scala:55:37]
.io_l2if_lit_reader_resp_bits_data (_l2_huf_lit_reader_io_userif_resp_bits_data), // @[ZstdCompressor.scala:55:37]
.io_l2if_lit_reader_no_memops_inflight (_l2_huf_lit_reader_io_userif_no_memops_inflight), // @[ZstdCompressor.scala:55:37]
.io_l2if_dic_reader_req_ready (_l2_huf_dic_reader_io_userif_req_ready), // @[ZstdCompressor.scala:58:37]
.io_l2if_dic_reader_req_valid (_lit_compressor_io_l2if_dic_reader_req_valid),
.io_l2if_dic_reader_req_bits_addr (_lit_compressor_io_l2if_dic_reader_req_bits_addr),
.io_l2if_dic_reader_req_bits_size (_lit_compressor_io_l2if_dic_reader_req_bits_size),
.io_l2if_dic_reader_req_bits_data (_lit_compressor_io_l2if_dic_reader_req_bits_data),
.io_l2if_dic_reader_req_bits_cmd (_lit_compressor_io_l2if_dic_reader_req_bits_cmd),
.io_l2if_dic_reader_resp_ready (_lit_compressor_io_l2if_dic_reader_resp_ready),
.io_l2if_dic_reader_resp_valid (_l2_huf_dic_reader_io_userif_resp_valid), // @[ZstdCompressor.scala:58:37]
.io_l2if_dic_reader_resp_bits_data (_l2_huf_dic_reader_io_userif_resp_bits_data), // @[ZstdCompressor.scala:58:37]
.io_l2if_dic_reader_no_memops_inflight (_l2_huf_dic_reader_io_userif_no_memops_inflight), // @[ZstdCompressor.scala:58:37]
.io_l2if_dic_writer_req_ready (_l2_huf_dic_writer_io_userif_req_ready), // @[ZstdCompressor.scala:61:37]
.io_l2if_dic_writer_req_valid (_lit_compressor_io_l2if_dic_writer_req_valid),
.io_l2if_dic_writer_req_bits_addr (_lit_compressor_io_l2if_dic_writer_req_bits_addr),
.io_l2if_dic_writer_req_bits_size (_lit_compressor_io_l2if_dic_writer_req_bits_size),
.io_l2if_dic_writer_req_bits_data (_lit_compressor_io_l2if_dic_writer_req_bits_data),
.io_l2if_dic_writer_req_bits_cmd (_lit_compressor_io_l2if_dic_writer_req_bits_cmd),
.io_l2if_dic_writer_resp_ready (_lit_compressor_io_l2if_dic_writer_resp_ready),
.io_l2if_dic_writer_resp_valid (_l2_huf_dic_writer_io_userif_resp_valid), // @[ZstdCompressor.scala:61:37]
.io_l2if_dic_writer_resp_bits_data (_l2_huf_dic_writer_io_userif_resp_bits_data), // @[ZstdCompressor.scala:61:37]
.io_l2if_dic_writer_no_memops_inflight (_l2_huf_dic_writer_io_userif_no_memops_inflight), // @[ZstdCompressor.scala:61:37]
.io_l2if_hdr_writer_req_ready (_l2_huf_hdr_writer_io_userif_req_ready), // @[ZstdCompressor.scala:64:37]
.io_l2if_hdr_writer_req_valid (_lit_compressor_io_l2if_hdr_writer_req_valid),
.io_l2if_hdr_writer_req_bits_addr (_lit_compressor_io_l2if_hdr_writer_req_bits_addr),
.io_l2if_hdr_writer_req_bits_size (_lit_compressor_io_l2if_hdr_writer_req_bits_size),
.io_l2if_hdr_writer_req_bits_data (_lit_compressor_io_l2if_hdr_writer_req_bits_data),
.io_l2if_hdr_writer_req_bits_cmd (_lit_compressor_io_l2if_hdr_writer_req_bits_cmd),
.io_l2if_hdr_writer_resp_ready (_lit_compressor_io_l2if_hdr_writer_resp_ready),
.io_l2if_hdr_writer_resp_valid (_l2_huf_hdr_writer_io_userif_resp_valid), // @[ZstdCompressor.scala:64:37]
.io_l2if_hdr_writer_resp_bits_data (_l2_huf_hdr_writer_io_userif_resp_bits_data), // @[ZstdCompressor.scala:64:37]
.io_l2if_hdr_writer_no_memops_inflight (_l2_huf_hdr_writer_io_userif_no_memops_inflight), // @[ZstdCompressor.scala:64:37]
.io_l2if_jt_writer_req_ready (_l2_huf_jt_writer_io_userif_req_ready), // @[ZstdCompressor.scala:67:36]
.io_l2if_jt_writer_req_valid (_lit_compressor_io_l2if_jt_writer_req_valid),
.io_l2if_jt_writer_req_bits_addr (_lit_compressor_io_l2if_jt_writer_req_bits_addr),
.io_l2if_jt_writer_req_bits_size (_lit_compressor_io_l2if_jt_writer_req_bits_size),
.io_l2if_jt_writer_req_bits_data (_lit_compressor_io_l2if_jt_writer_req_bits_data),
.io_l2if_jt_writer_req_bits_cmd (_lit_compressor_io_l2if_jt_writer_req_bits_cmd),
.io_l2if_jt_writer_resp_ready (_lit_compressor_io_l2if_jt_writer_resp_ready),
.io_l2if_jt_writer_resp_valid (_l2_huf_jt_writer_io_userif_resp_valid), // @[ZstdCompressor.scala:67:36]
.io_l2if_jt_writer_resp_bits_data (_l2_huf_jt_writer_io_userif_resp_bits_data), // @[ZstdCompressor.scala:67:36]
.io_l2if_jt_writer_no_memops_inflight (_l2_huf_jt_writer_io_userif_no_memops_inflight), // @[ZstdCompressor.scala:67:36]
.io_l2if_lit_writer_req_ready (_l2_huf_lit_writer_io_userif_req_ready), // @[ZstdCompressor.scala:70:37]
.io_l2if_lit_writer_req_valid (_lit_compressor_io_l2if_lit_writer_req_valid),
.io_l2if_lit_writer_req_bits_addr (_lit_compressor_io_l2if_lit_writer_req_bits_addr),
.io_l2if_lit_writer_req_bits_size (_lit_compressor_io_l2if_lit_writer_req_bits_size),
.io_l2if_lit_writer_req_bits_data (_lit_compressor_io_l2if_lit_writer_req_bits_data),
.io_l2if_lit_writer_req_bits_cmd (_lit_compressor_io_l2if_lit_writer_req_bits_cmd),
.io_l2if_lit_writer_resp_ready (_lit_compressor_io_l2if_lit_writer_resp_ready),
.io_l2if_lit_writer_resp_valid (_l2_huf_lit_writer_io_userif_resp_valid), // @[ZstdCompressor.scala:70:37]
.io_l2if_lit_writer_resp_bits_data (_l2_huf_lit_writer_io_userif_resp_bits_data), // @[ZstdCompressor.scala:70:37]
.io_l2if_lit_writer_no_memops_inflight (_l2_huf_lit_writer_io_userif_no_memops_inflight), // @[ZstdCompressor.scala:70:37]
.io_busy (/* unused */)
); // @[ZstdCompressor.scala:140:30]
ZstdRawLiteralEncoder raw_lit_encoder ( // @[ZstdCompressor.scala:154:31]
.clock (clock),
.reset (reset),
.io_l2io_read_req_ready (_l2_raw_lit_reader_io_userif_req_ready), // @[ZstdCompressor.scala:88:37]
.io_l2io_read_req_valid (_raw_lit_encoder_io_l2io_read_req_valid),
.io_l2io_read_req_bits_addr (_raw_lit_encoder_io_l2io_read_req_bits_addr),
.io_l2io_read_resp_ready (_raw_lit_encoder_io_l2io_read_resp_ready),
.io_l2io_read_resp_valid (_l2_raw_lit_reader_io_userif_resp_valid), // @[ZstdCompressor.scala:88:37]
.io_l2io_read_resp_bits_data (_l2_raw_lit_reader_io_userif_resp_bits_data), // @[ZstdCompressor.scala:88:37]
.io_l2io_read_no_memops_inflight (_l2_raw_lit_reader_io_userif_no_memops_inflight), // @[ZstdCompressor.scala:88:37]
.io_src_info_ready (_raw_lit_encoder_io_src_info_ready),
.io_src_info_valid (_controller_io_zstd_control_raw_lit_src_valid), // @[ZstdCompressor.scala:116:26]
.io_src_info_bits_ip (_controller_io_zstd_control_raw_lit_src_bits_ip), // @[ZstdCompressor.scala:116:26]
.io_src_info_bits_isize (_controller_io_zstd_control_raw_lit_src_bits_isize), // @[ZstdCompressor.scala:116:26]
.io_dst_info_ready (_raw_lit_encoder_io_dst_info_ready),
.io_dst_info_valid (_controller_io_zstd_control_raw_lit_dst_valid), // @[ZstdCompressor.scala:116:26]
.io_dst_info_bits_op (_controller_io_zstd_control_raw_lit_dst_bits_op), // @[ZstdCompressor.scala:116:26]
.io_dst_info_bits_cmpflag (_controller_io_zstd_control_raw_lit_dst_bits_cmpflag), // @[ZstdCompressor.scala:116:26]
.io_dst_info_bits_cmpval (_controller_io_zstd_control_raw_lit_dst_bits_cmpval), // @[ZstdCompressor.scala:116:26]
.io_l2io_write_req_ready (_l2_raw_lit_writer_io_userif_req_ready), // @[ZstdCompressor.scala:91:37]
.io_l2io_write_req_valid (_raw_lit_encoder_io_l2io_write_req_valid),
.io_l2io_write_req_bits_addr (_raw_lit_encoder_io_l2io_write_req_bits_addr),
.io_l2io_write_req_bits_size (_raw_lit_encoder_io_l2io_write_req_bits_size),
.io_l2io_write_req_bits_data (_raw_lit_encoder_io_l2io_write_req_bits_data),
.io_l2io_write_resp_valid (_l2_raw_lit_writer_io_userif_resp_valid), // @[ZstdCompressor.scala:91:37]
.io_l2io_write_resp_bits_data (_l2_raw_lit_writer_io_userif_resp_bits_data), // @[ZstdCompressor.scala:91:37]
.io_l2io_write_no_memops_inflight (_l2_raw_lit_writer_io_userif_no_memops_inflight), // @[ZstdCompressor.scala:91:37]
.io_bytes_written_ready (_controller_io_zstd_control_raw_litbytes_written_ready), // @[ZstdCompressor.scala:116:26]
.io_bytes_written_valid (_raw_lit_encoder_io_bytes_written_valid),
.io_bytes_written_bits (_raw_lit_encoder_io_bytes_written_bits)
); // @[ZstdCompressor.scala:154:31]
ZstdRawBlockMemcopy raw_block_encoder ( // @[ZstdCompressor.scala:161:33]
.clock (clock),
.reset (reset),
.io_src_info_ready (_raw_block_encoder_io_src_info_ready),
.io_src_info_valid (_controller_io_zstd_control_raw_block_src_valid), // @[ZstdCompressor.scala:116:26]
.io_src_info_bits_ip (_controller_io_zstd_control_raw_block_src_bits_ip), // @[ZstdCompressor.scala:116:26]
.io_src_info_bits_isize (_controller_io_zstd_control_raw_block_src_bits_isize), // @[ZstdCompressor.scala:116:26]
.io_dst_info_ready (_raw_block_encoder_io_dst_info_ready),
.io_dst_info_valid (_controller_io_zstd_control_raw_block_dst_valid), // @[ZstdCompressor.scala:116:26]
.io_dst_info_bits_op (_controller_io_zstd_control_raw_block_dst_bits_op), // @[ZstdCompressor.scala:116:26]
.io_dst_info_bits_cmpflag (_controller_io_zstd_control_raw_block_dst_bits_cmpflag), // @[ZstdCompressor.scala:116:26]
.io_dst_info_bits_cmpval (_controller_io_zstd_control_raw_block_dst_bits_cmpval), // @[ZstdCompressor.scala:116:26]
.io_bytes_written_ready (_controller_io_zstd_control_raw_blockbytes_written_ready), // @[ZstdCompressor.scala:116:26]
.io_bytes_written_valid (_raw_block_encoder_io_bytes_written_valid),
.io_bytes_written_bits (_raw_block_encoder_io_bytes_written_bits),
.io_l2if_reader_req_ready (_l2_raw_block_reader_io_userif_req_ready), // @[ZstdCompressor.scala:82:39]
.io_l2if_reader_req_valid (_raw_block_encoder_io_l2if_reader_req_valid),
.io_l2if_reader_req_bits_addr (_raw_block_encoder_io_l2if_reader_req_bits_addr),
.io_l2if_reader_resp_ready (_raw_block_encoder_io_l2if_reader_resp_ready),
.io_l2if_reader_resp_valid (_l2_raw_block_reader_io_userif_resp_valid), // @[ZstdCompressor.scala:82:39]
.io_l2if_reader_resp_bits_data (_l2_raw_block_reader_io_userif_resp_bits_data), // @[ZstdCompressor.scala:82:39]
.io_l2if_reader_no_memops_inflight (_l2_raw_block_reader_io_userif_no_memops_inflight), // @[ZstdCompressor.scala:82:39]
.io_l2if_writer_req_ready (_l2_raw_block_writer_io_userif_req_ready), // @[ZstdCompressor.scala:85:39]
.io_l2if_writer_req_valid (_raw_block_encoder_io_l2if_writer_req_valid),
.io_l2if_writer_req_bits_addr (_raw_block_encoder_io_l2if_writer_req_bits_addr),
.io_l2if_writer_req_bits_size (_raw_block_encoder_io_l2if_writer_req_bits_size),
.io_l2if_writer_req_bits_data (_raw_block_encoder_io_l2if_writer_req_bits_data),
.io_l2if_writer_resp_valid (_l2_raw_block_writer_io_userif_resp_valid), // @[ZstdCompressor.scala:85:39]
.io_l2if_writer_resp_bits_data (_l2_raw_block_writer_io_userif_resp_bits_data), // @[ZstdCompressor.scala:85:39]
.io_l2if_writer_no_memops_inflight (_l2_raw_block_writer_io_userif_no_memops_inflight) // @[ZstdCompressor.scala:85:39]
); // @[ZstdCompressor.scala:161:33]
ZstdSequenceEncoder seq_compressor ( // @[ZstdCompressor.scala:168:30]
.clock (clock),
.reset (reset),
.io_src_info_ready (_seq_compressor_io_src_info_ready),
.io_src_info_valid (_controller_io_zstd_control_seqcpy_src_valid), // @[ZstdCompressor.scala:116:26]
.io_src_info_bits_ip (_controller_io_zstd_control_seqcpy_src_bits_ip), // @[ZstdCompressor.scala:116:26]
.io_src_info_bits_isize (_controller_io_zstd_control_seqcpy_src_bits_isize), // @[ZstdCompressor.scala:116:26]
.io_dst_info_ready (_seq_compressor_io_dst_info_ready),
.io_dst_info_valid (_controller_io_zstd_control_seqcpy_dst_valid), // @[ZstdCompressor.scala:116:26]
.io_dst_info_bits_op (_controller_io_zstd_control_seqcpy_dst_bits_op), // @[ZstdCompressor.scala:116:26]
.io_dst_info_bits_cmpflag (_controller_io_zstd_control_seqcpy_dst_bits_cmpflag), // @[ZstdCompressor.scala:116:26]
.io_dst_info_bits_cmpval (_controller_io_zstd_control_seqcpy_dst_bits_cmpval), // @[ZstdCompressor.scala:116:26]
.io_bytes_written_ready (_controller_io_zstd_control_seqbytes_written_ready), // @[ZstdCompressor.scala:116:26]
.io_bytes_written_valid (_seq_compressor_io_bytes_written_valid),
.io_bytes_written_bits (_seq_compressor_io_bytes_written_bits),
.io_l2if_seq_reader_req_ready (_l2_seq_reader_io_userif_req_ready), // @[ZstdCompressor.scala:73:33]
.io_l2if_seq_reader_req_valid (_seq_compressor_io_l2if_seq_reader_req_valid),
.io_l2if_seq_reader_req_bits_addr (_seq_compressor_io_l2if_seq_reader_req_bits_addr),
.io_l2if_seq_reader_req_bits_size (_seq_compressor_io_l2if_seq_reader_req_bits_size),
.io_l2if_seq_reader_req_bits_data (_seq_compressor_io_l2if_seq_reader_req_bits_data),
.io_l2if_seq_reader_req_bits_cmd (_seq_compressor_io_l2if_seq_reader_req_bits_cmd),
.io_l2if_seq_reader_resp_ready (_seq_compressor_io_l2if_seq_reader_resp_ready),
.io_l2if_seq_reader_resp_valid (_l2_seq_reader_io_userif_resp_valid), // @[ZstdCompressor.scala:73:33]
.io_l2if_seq_reader_resp_bits_data (_l2_seq_reader_io_userif_resp_bits_data), // @[ZstdCompressor.scala:73:33]
.io_l2if_seq_reader_no_memops_inflight (_l2_seq_reader_io_userif_no_memops_inflight), // @[ZstdCompressor.scala:73:33]
.io_l2if_seq_reader2_req_ready (_l2_seq_reader2_io_userif_req_ready), // @[ZstdCompressor.scala:76:34]
.io_l2if_seq_reader2_req_valid (_seq_compressor_io_l2if_seq_reader2_req_valid),
.io_l2if_seq_reader2_req_bits_addr (_seq_compressor_io_l2if_seq_reader2_req_bits_addr),
.io_l2if_seq_reader2_req_bits_size (_seq_compressor_io_l2if_seq_reader2_req_bits_size),
.io_l2if_seq_reader2_req_bits_data (_seq_compressor_io_l2if_seq_reader2_req_bits_data),
.io_l2if_seq_reader2_req_bits_cmd (_seq_compressor_io_l2if_seq_reader2_req_bits_cmd),
.io_l2if_seq_reader2_resp_ready (_seq_compressor_io_l2if_seq_reader2_resp_ready),
.io_l2if_seq_reader2_resp_valid (_l2_seq_reader2_io_userif_resp_valid), // @[ZstdCompressor.scala:76:34]
.io_l2if_seq_reader2_resp_bits_data (_l2_seq_reader2_io_userif_resp_bits_data), // @[ZstdCompressor.scala:76:34]
.io_l2if_seq_reader2_no_memops_inflight (_l2_seq_reader2_io_userif_no_memops_inflight), // @[ZstdCompressor.scala:76:34]
.io_l2if_seq_writer_req_ready (_l2_seq_writer_io_userif_req_ready), // @[ZstdCompressor.scala:79:33]
.io_l2if_seq_writer_req_valid (_seq_compressor_io_l2if_seq_writer_req_valid),
.io_l2if_seq_writer_req_bits_addr (_seq_compressor_io_l2if_seq_writer_req_bits_addr),
.io_l2if_seq_writer_req_bits_size (_seq_compressor_io_l2if_seq_writer_req_bits_size),
.io_l2if_seq_writer_req_bits_data (_seq_compressor_io_l2if_seq_writer_req_bits_data),
.io_l2if_seq_writer_req_bits_cmd (_seq_compressor_io_l2if_seq_writer_req_bits_cmd),
.io_l2if_seq_writer_resp_ready (_seq_compressor_io_l2if_seq_writer_resp_ready),
.io_l2if_seq_writer_resp_valid (_l2_seq_writer_io_userif_resp_valid), // @[ZstdCompressor.scala:79:33]
.io_l2if_seq_writer_resp_bits_data (_l2_seq_writer_io_userif_resp_bits_data), // @[ZstdCompressor.scala:79:33]
.io_l2if_seq_writer_no_memops_inflight (_l2_seq_writer_io_userif_no_memops_inflight), // @[ZstdCompressor.scala:79:33]
.io_busy (/* unused */)
); // @[ZstdCompressor.scala:168:30]
assign auto_tl_out_17_a_valid = auto_tl_out_17_a_valid_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_17_a_bits_opcode = auto_tl_out_17_a_bits_opcode_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_17_a_bits_param = auto_tl_out_17_a_bits_param_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_17_a_bits_size = auto_tl_out_17_a_bits_size_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_17_a_bits_source = auto_tl_out_17_a_bits_source_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_17_a_bits_address = auto_tl_out_17_a_bits_address_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_17_a_bits_mask = auto_tl_out_17_a_bits_mask_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_17_a_bits_data = auto_tl_out_17_a_bits_data_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_17_a_bits_corrupt = auto_tl_out_17_a_bits_corrupt_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_17_d_ready = auto_tl_out_17_d_ready_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_16_a_valid = auto_tl_out_16_a_valid_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_16_a_bits_opcode = auto_tl_out_16_a_bits_opcode_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_16_a_bits_param = auto_tl_out_16_a_bits_param_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_16_a_bits_size = auto_tl_out_16_a_bits_size_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_16_a_bits_source = auto_tl_out_16_a_bits_source_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_16_a_bits_address = auto_tl_out_16_a_bits_address_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_16_a_bits_mask = auto_tl_out_16_a_bits_mask_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_16_a_bits_data = auto_tl_out_16_a_bits_data_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_16_a_bits_corrupt = auto_tl_out_16_a_bits_corrupt_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_16_d_ready = auto_tl_out_16_d_ready_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_15_a_valid = auto_tl_out_15_a_valid_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_15_a_bits_opcode = auto_tl_out_15_a_bits_opcode_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_15_a_bits_param = auto_tl_out_15_a_bits_param_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_15_a_bits_size = auto_tl_out_15_a_bits_size_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_15_a_bits_source = auto_tl_out_15_a_bits_source_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_15_a_bits_address = auto_tl_out_15_a_bits_address_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_15_a_bits_mask = auto_tl_out_15_a_bits_mask_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_15_a_bits_data = auto_tl_out_15_a_bits_data_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_15_a_bits_corrupt = auto_tl_out_15_a_bits_corrupt_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_15_d_ready = auto_tl_out_15_d_ready_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_14_a_valid = auto_tl_out_14_a_valid_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_14_a_bits_opcode = auto_tl_out_14_a_bits_opcode_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_14_a_bits_param = auto_tl_out_14_a_bits_param_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_14_a_bits_size = auto_tl_out_14_a_bits_size_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_14_a_bits_source = auto_tl_out_14_a_bits_source_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_14_a_bits_address = auto_tl_out_14_a_bits_address_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_14_a_bits_mask = auto_tl_out_14_a_bits_mask_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_14_a_bits_data = auto_tl_out_14_a_bits_data_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_14_a_bits_corrupt = auto_tl_out_14_a_bits_corrupt_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_14_d_ready = auto_tl_out_14_d_ready_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_13_a_valid = auto_tl_out_13_a_valid_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_13_a_bits_opcode = auto_tl_out_13_a_bits_opcode_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_13_a_bits_param = auto_tl_out_13_a_bits_param_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_13_a_bits_size = auto_tl_out_13_a_bits_size_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_13_a_bits_source = auto_tl_out_13_a_bits_source_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_13_a_bits_address = auto_tl_out_13_a_bits_address_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_13_a_bits_mask = auto_tl_out_13_a_bits_mask_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_13_a_bits_data = auto_tl_out_13_a_bits_data_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_13_a_bits_corrupt = auto_tl_out_13_a_bits_corrupt_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_13_d_ready = auto_tl_out_13_d_ready_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_12_a_valid = auto_tl_out_12_a_valid_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_12_a_bits_opcode = auto_tl_out_12_a_bits_opcode_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_12_a_bits_param = auto_tl_out_12_a_bits_param_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_12_a_bits_size = auto_tl_out_12_a_bits_size_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_12_a_bits_source = auto_tl_out_12_a_bits_source_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_12_a_bits_address = auto_tl_out_12_a_bits_address_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_12_a_bits_mask = auto_tl_out_12_a_bits_mask_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_12_a_bits_data = auto_tl_out_12_a_bits_data_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_12_a_bits_corrupt = auto_tl_out_12_a_bits_corrupt_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_12_d_ready = auto_tl_out_12_d_ready_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_11_a_valid = auto_tl_out_11_a_valid_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_11_a_bits_opcode = auto_tl_out_11_a_bits_opcode_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_11_a_bits_param = auto_tl_out_11_a_bits_param_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_11_a_bits_size = auto_tl_out_11_a_bits_size_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_11_a_bits_source = auto_tl_out_11_a_bits_source_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_11_a_bits_address = auto_tl_out_11_a_bits_address_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_11_a_bits_mask = auto_tl_out_11_a_bits_mask_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_11_a_bits_data = auto_tl_out_11_a_bits_data_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_11_a_bits_corrupt = auto_tl_out_11_a_bits_corrupt_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_11_d_ready = auto_tl_out_11_d_ready_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_10_a_valid = auto_tl_out_10_a_valid_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_10_a_bits_opcode = auto_tl_out_10_a_bits_opcode_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_10_a_bits_param = auto_tl_out_10_a_bits_param_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_10_a_bits_size = auto_tl_out_10_a_bits_size_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_10_a_bits_source = auto_tl_out_10_a_bits_source_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_10_a_bits_address = auto_tl_out_10_a_bits_address_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_10_a_bits_mask = auto_tl_out_10_a_bits_mask_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_10_a_bits_data = auto_tl_out_10_a_bits_data_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_10_a_bits_corrupt = auto_tl_out_10_a_bits_corrupt_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_10_d_ready = auto_tl_out_10_d_ready_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_9_a_valid = auto_tl_out_9_a_valid_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_9_a_bits_opcode = auto_tl_out_9_a_bits_opcode_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_9_a_bits_param = auto_tl_out_9_a_bits_param_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_9_a_bits_size = auto_tl_out_9_a_bits_size_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_9_a_bits_source = auto_tl_out_9_a_bits_source_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_9_a_bits_address = auto_tl_out_9_a_bits_address_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_9_a_bits_mask = auto_tl_out_9_a_bits_mask_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_9_a_bits_data = auto_tl_out_9_a_bits_data_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_9_a_bits_corrupt = auto_tl_out_9_a_bits_corrupt_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_9_d_ready = auto_tl_out_9_d_ready_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_8_a_valid = auto_tl_out_8_a_valid_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_8_a_bits_opcode = auto_tl_out_8_a_bits_opcode_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_8_a_bits_param = auto_tl_out_8_a_bits_param_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_8_a_bits_size = auto_tl_out_8_a_bits_size_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_8_a_bits_source = auto_tl_out_8_a_bits_source_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_8_a_bits_address = auto_tl_out_8_a_bits_address_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_8_a_bits_mask = auto_tl_out_8_a_bits_mask_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_8_a_bits_data = auto_tl_out_8_a_bits_data_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_8_a_bits_corrupt = auto_tl_out_8_a_bits_corrupt_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_8_d_ready = auto_tl_out_8_d_ready_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_7_a_valid = auto_tl_out_7_a_valid_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_7_a_bits_opcode = auto_tl_out_7_a_bits_opcode_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_7_a_bits_param = auto_tl_out_7_a_bits_param_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_7_a_bits_size = auto_tl_out_7_a_bits_size_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_7_a_bits_source = auto_tl_out_7_a_bits_source_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_7_a_bits_address = auto_tl_out_7_a_bits_address_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_7_a_bits_mask = auto_tl_out_7_a_bits_mask_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_7_a_bits_data = auto_tl_out_7_a_bits_data_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_7_a_bits_corrupt = auto_tl_out_7_a_bits_corrupt_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_7_d_ready = auto_tl_out_7_d_ready_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_6_a_valid = auto_tl_out_6_a_valid_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_6_a_bits_opcode = auto_tl_out_6_a_bits_opcode_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_6_a_bits_param = auto_tl_out_6_a_bits_param_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_6_a_bits_size = auto_tl_out_6_a_bits_size_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_6_a_bits_source = auto_tl_out_6_a_bits_source_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_6_a_bits_address = auto_tl_out_6_a_bits_address_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_6_a_bits_mask = auto_tl_out_6_a_bits_mask_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_6_a_bits_data = auto_tl_out_6_a_bits_data_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_6_a_bits_corrupt = auto_tl_out_6_a_bits_corrupt_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_6_d_ready = auto_tl_out_6_d_ready_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_5_a_valid = auto_tl_out_5_a_valid_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_5_a_bits_opcode = auto_tl_out_5_a_bits_opcode_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_5_a_bits_param = auto_tl_out_5_a_bits_param_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_5_a_bits_size = auto_tl_out_5_a_bits_size_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_5_a_bits_source = auto_tl_out_5_a_bits_source_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_5_a_bits_address = auto_tl_out_5_a_bits_address_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_5_a_bits_mask = auto_tl_out_5_a_bits_mask_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_5_a_bits_data = auto_tl_out_5_a_bits_data_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_5_a_bits_corrupt = auto_tl_out_5_a_bits_corrupt_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_5_d_ready = auto_tl_out_5_d_ready_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_4_a_valid = auto_tl_out_4_a_valid_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_4_a_bits_opcode = auto_tl_out_4_a_bits_opcode_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_4_a_bits_param = auto_tl_out_4_a_bits_param_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_4_a_bits_size = auto_tl_out_4_a_bits_size_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_4_a_bits_source = auto_tl_out_4_a_bits_source_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_4_a_bits_address = auto_tl_out_4_a_bits_address_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_4_a_bits_mask = auto_tl_out_4_a_bits_mask_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_4_a_bits_data = auto_tl_out_4_a_bits_data_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_4_a_bits_corrupt = auto_tl_out_4_a_bits_corrupt_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_4_d_ready = auto_tl_out_4_d_ready_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_3_a_valid = auto_tl_out_3_a_valid_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_3_a_bits_opcode = auto_tl_out_3_a_bits_opcode_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_3_a_bits_param = auto_tl_out_3_a_bits_param_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_3_a_bits_size = auto_tl_out_3_a_bits_size_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_3_a_bits_source = auto_tl_out_3_a_bits_source_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_3_a_bits_address = auto_tl_out_3_a_bits_address_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_3_a_bits_mask = auto_tl_out_3_a_bits_mask_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_3_a_bits_data = auto_tl_out_3_a_bits_data_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_3_a_bits_corrupt = auto_tl_out_3_a_bits_corrupt_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_3_d_ready = auto_tl_out_3_d_ready_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_2_a_valid = auto_tl_out_2_a_valid_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_2_a_bits_opcode = auto_tl_out_2_a_bits_opcode_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_2_a_bits_param = auto_tl_out_2_a_bits_param_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_2_a_bits_size = auto_tl_out_2_a_bits_size_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_2_a_bits_source = auto_tl_out_2_a_bits_source_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_2_a_bits_address = auto_tl_out_2_a_bits_address_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_2_a_bits_mask = auto_tl_out_2_a_bits_mask_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_2_a_bits_data = auto_tl_out_2_a_bits_data_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_2_a_bits_corrupt = auto_tl_out_2_a_bits_corrupt_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_2_d_ready = auto_tl_out_2_d_ready_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_1_a_valid = auto_tl_out_1_a_valid_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_1_a_bits_opcode = auto_tl_out_1_a_bits_opcode_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_1_a_bits_param = auto_tl_out_1_a_bits_param_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_1_a_bits_size = auto_tl_out_1_a_bits_size_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_1_a_bits_source = auto_tl_out_1_a_bits_source_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_1_a_bits_address = auto_tl_out_1_a_bits_address_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_1_a_bits_mask = auto_tl_out_1_a_bits_mask_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_1_a_bits_data = auto_tl_out_1_a_bits_data_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_1_a_bits_corrupt = auto_tl_out_1_a_bits_corrupt_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_1_d_ready = auto_tl_out_1_d_ready_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_0_a_valid = auto_tl_out_0_a_valid_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_0_a_bits_opcode = auto_tl_out_0_a_bits_opcode_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_0_a_bits_param = auto_tl_out_0_a_bits_param_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_0_a_bits_size = auto_tl_out_0_a_bits_size_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_0_a_bits_source = auto_tl_out_0_a_bits_source_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_0_a_bits_address = auto_tl_out_0_a_bits_address_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_0_a_bits_mask = auto_tl_out_0_a_bits_mask_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_0_a_bits_data = auto_tl_out_0_a_bits_data_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_0_a_bits_corrupt = auto_tl_out_0_a_bits_corrupt_0; // @[ZstdCompressor.scala:95:7]
assign auto_tl_out_0_d_ready = auto_tl_out_0_d_ready_0; // @[ZstdCompressor.scala:95:7]
assign io_cmd_ready = io_cmd_ready_0; // @[ZstdCompressor.scala:95:7]
assign io_resp_valid = io_resp_valid_0; // @[ZstdCompressor.scala:95:7]
assign io_resp_bits_rd = io_resp_bits_rd_0; // @[ZstdCompressor.scala:95:7]
assign io_resp_bits_data = io_resp_bits_data_0; // @[ZstdCompressor.scala:95:7]
assign io_ptw_0_req_valid = io_ptw_0_req_valid_0; // @[ZstdCompressor.scala:95:7]
assign io_ptw_0_req_bits_bits_addr = io_ptw_0_req_bits_bits_addr_0; // @[ZstdCompressor.scala:95:7]
assign io_ptw_0_req_bits_bits_need_gpa = io_ptw_0_req_bits_bits_need_gpa_0; // @[ZstdCompressor.scala:95:7]
assign io_ptw_1_req_valid = io_ptw_1_req_valid_0; // @[ZstdCompressor.scala:95:7]
assign io_ptw_1_req_bits_bits_addr = io_ptw_1_req_bits_bits_addr_0; // @[ZstdCompressor.scala:95:7]
assign io_ptw_1_req_bits_bits_need_gpa = io_ptw_1_req_bits_bits_need_gpa_0; // @[ZstdCompressor.scala:95:7]
assign io_ptw_2_req_valid = io_ptw_2_req_valid_0; // @[ZstdCompressor.scala:95:7]
assign io_ptw_2_req_bits_bits_addr = io_ptw_2_req_bits_bits_addr_0; // @[ZstdCompressor.scala:95:7]
assign io_ptw_2_req_bits_bits_need_gpa = io_ptw_2_req_bits_bits_need_gpa_0; // @[ZstdCompressor.scala:95:7]
assign io_ptw_3_req_valid = io_ptw_3_req_valid_0; // @[ZstdCompressor.scala:95:7]
assign io_ptw_3_req_bits_bits_addr = io_ptw_3_req_bits_bits_addr_0; // @[ZstdCompressor.scala:95:7]
assign io_ptw_3_req_bits_bits_need_gpa = io_ptw_3_req_bits_bits_need_gpa_0; // @[ZstdCompressor.scala:95:7]
assign io_ptw_4_req_valid = io_ptw_4_req_valid_0; // @[ZstdCompressor.scala:95:7]
assign io_ptw_4_req_bits_bits_addr = io_ptw_4_req_bits_bits_addr_0; // @[ZstdCompressor.scala:95:7]
assign io_ptw_4_req_bits_bits_need_gpa = io_ptw_4_req_bits_bits_need_gpa_0; // @[ZstdCompressor.scala:95:7]
assign io_ptw_5_req_valid = io_ptw_5_req_valid_0; // @[ZstdCompressor.scala:95:7]
assign io_ptw_5_req_bits_bits_addr = io_ptw_5_req_bits_bits_addr_0; // @[ZstdCompressor.scala:95:7]
assign io_ptw_5_req_bits_bits_need_gpa = io_ptw_5_req_bits_bits_need_gpa_0; // @[ZstdCompressor.scala:95:7]
assign io_ptw_6_req_valid = io_ptw_6_req_valid_0; // @[ZstdCompressor.scala:95:7]
assign io_ptw_6_req_bits_bits_addr = io_ptw_6_req_bits_bits_addr_0; // @[ZstdCompressor.scala:95:7]
assign io_ptw_6_req_bits_bits_need_gpa = io_ptw_6_req_bits_bits_need_gpa_0; // @[ZstdCompressor.scala:95:7]
assign io_ptw_7_req_valid = io_ptw_7_req_valid_0; // @[ZstdCompressor.scala:95:7]
assign io_ptw_7_req_bits_bits_addr = io_ptw_7_req_bits_bits_addr_0; // @[ZstdCompressor.scala:95:7]
assign io_ptw_7_req_bits_bits_need_gpa = io_ptw_7_req_bits_bits_need_gpa_0; // @[ZstdCompressor.scala:95:7]
assign io_ptw_8_req_valid = io_ptw_8_req_valid_0; // @[ZstdCompressor.scala:95:7]
assign io_ptw_8_req_bits_bits_addr = io_ptw_8_req_bits_bits_addr_0; // @[ZstdCompressor.scala:95:7]
assign io_ptw_8_req_bits_bits_need_gpa = io_ptw_8_req_bits_bits_need_gpa_0; // @[ZstdCompressor.scala:95:7]
assign io_ptw_9_req_valid = io_ptw_9_req_valid_0; // @[ZstdCompressor.scala:95:7]
assign io_ptw_9_req_bits_bits_addr = io_ptw_9_req_bits_bits_addr_0; // @[ZstdCompressor.scala:95:7]
assign io_ptw_9_req_bits_bits_need_gpa = io_ptw_9_req_bits_bits_need_gpa_0; // @[ZstdCompressor.scala:95:7]
assign io_ptw_10_req_valid = io_ptw_10_req_valid_0; // @[ZstdCompressor.scala:95:7]
assign io_ptw_10_req_bits_bits_addr = io_ptw_10_req_bits_bits_addr_0; // @[ZstdCompressor.scala:95:7]
assign io_ptw_10_req_bits_bits_need_gpa = io_ptw_10_req_bits_bits_need_gpa_0; // @[ZstdCompressor.scala:95:7]
assign io_ptw_11_req_valid = io_ptw_11_req_valid_0; // @[ZstdCompressor.scala:95:7]
assign io_ptw_11_req_bits_bits_addr = io_ptw_11_req_bits_bits_addr_0; // @[ZstdCompressor.scala:95:7]
assign io_ptw_11_req_bits_bits_need_gpa = io_ptw_11_req_bits_bits_need_gpa_0; // @[ZstdCompressor.scala:95:7]
assign io_ptw_12_req_valid = io_ptw_12_req_valid_0; // @[ZstdCompressor.scala:95:7]
assign io_ptw_12_req_bits_bits_addr = io_ptw_12_req_bits_bits_addr_0; // @[ZstdCompressor.scala:95:7]
assign io_ptw_12_req_bits_bits_need_gpa = io_ptw_12_req_bits_bits_need_gpa_0; // @[ZstdCompressor.scala:95:7]
assign io_ptw_13_req_valid = io_ptw_13_req_valid_0; // @[ZstdCompressor.scala:95:7]
assign io_ptw_13_req_bits_bits_addr = io_ptw_13_req_bits_bits_addr_0; // @[ZstdCompressor.scala:95:7]
assign io_ptw_13_req_bits_bits_need_gpa = io_ptw_13_req_bits_bits_need_gpa_0; // @[ZstdCompressor.scala:95:7]
assign io_ptw_14_req_valid = io_ptw_14_req_valid_0; // @[ZstdCompressor.scala:95:7]
assign io_ptw_14_req_bits_bits_addr = io_ptw_14_req_bits_bits_addr_0; // @[ZstdCompressor.scala:95:7]
assign io_ptw_14_req_bits_bits_need_gpa = io_ptw_14_req_bits_bits_need_gpa_0; // @[ZstdCompressor.scala:95:7]
assign io_ptw_15_req_valid = io_ptw_15_req_valid_0; // @[ZstdCompressor.scala:95:7]
assign io_ptw_15_req_bits_bits_addr = io_ptw_15_req_bits_bits_addr_0; // @[ZstdCompressor.scala:95:7]
assign io_ptw_15_req_bits_bits_need_gpa = io_ptw_15_req_bits_bits_need_gpa_0; // @[ZstdCompressor.scala:95:7]
assign io_ptw_16_req_valid = io_ptw_16_req_valid_0; // @[ZstdCompressor.scala:95:7]
assign io_ptw_16_req_bits_bits_addr = io_ptw_16_req_bits_bits_addr_0; // @[ZstdCompressor.scala:95:7]
assign io_ptw_16_req_bits_bits_need_gpa = io_ptw_16_req_bits_bits_need_gpa_0; // @[ZstdCompressor.scala:95:7]
assign io_ptw_17_req_valid = io_ptw_17_req_valid_0; // @[ZstdCompressor.scala:95:7]
assign io_ptw_17_req_bits_bits_addr = io_ptw_17_req_bits_bits_addr_0; // @[ZstdCompressor.scala:95:7]
assign io_ptw_17_req_bits_bits_need_gpa = io_ptw_17_req_bits_bits_need_gpa_0; // @[ZstdCompressor.scala:95:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_108 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>}
node _io_out_d_T = mul(io.in_a, io.in_b)
node _io_out_d_T_1 = add(_io_out_d_T, io.in_c)
node _io_out_d_T_2 = tail(_io_out_d_T_1, 1)
node _io_out_d_T_3 = asSInt(_io_out_d_T_2)
connect io.out_d, _io_out_d_T_3 | module MacUnit_108( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [31:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7]
wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54]
wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TileResetSetter :
input clock : Clock
input reset : Reset
output auto : { flip clock_in : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}}, clock_out : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}}, flip tl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<9>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
wire tlNodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<9>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate tlNodeIn.d.bits.corrupt
invalidate tlNodeIn.d.bits.data
invalidate tlNodeIn.d.bits.denied
invalidate tlNodeIn.d.bits.sink
invalidate tlNodeIn.d.bits.source
invalidate tlNodeIn.d.bits.size
invalidate tlNodeIn.d.bits.param
invalidate tlNodeIn.d.bits.opcode
invalidate tlNodeIn.d.valid
invalidate tlNodeIn.d.ready
invalidate tlNodeIn.a.bits.corrupt
invalidate tlNodeIn.a.bits.data
invalidate tlNodeIn.a.bits.mask
invalidate tlNodeIn.a.bits.address
invalidate tlNodeIn.a.bits.source
invalidate tlNodeIn.a.bits.size
invalidate tlNodeIn.a.bits.param
invalidate tlNodeIn.a.bits.opcode
invalidate tlNodeIn.a.valid
invalidate tlNodeIn.a.ready
inst monitor of TLMonitor_22
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, tlNodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, tlNodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, tlNodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, tlNodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, tlNodeIn.d.bits.source
connect monitor.io.in.d.bits.size, tlNodeIn.d.bits.size
connect monitor.io.in.d.bits.param, tlNodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, tlNodeIn.d.bits.opcode
connect monitor.io.in.d.valid, tlNodeIn.d.valid
connect monitor.io.in.d.ready, tlNodeIn.d.ready
connect monitor.io.in.a.bits.corrupt, tlNodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, tlNodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, tlNodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, tlNodeIn.a.bits.address
connect monitor.io.in.a.bits.source, tlNodeIn.a.bits.source
connect monitor.io.in.a.bits.size, tlNodeIn.a.bits.size
connect monitor.io.in.a.bits.param, tlNodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, tlNodeIn.a.bits.opcode
connect monitor.io.in.a.valid, tlNodeIn.a.valid
connect monitor.io.in.a.ready, tlNodeIn.a.ready
wire clockNodeOut : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}}
invalidate clockNodeOut.member.allClocks_uncore.reset
invalidate clockNodeOut.member.allClocks_uncore.clock
wire clockNodeIn : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}}
invalidate clockNodeIn.member.allClocks_uncore.reset
invalidate clockNodeIn.member.allClocks_uncore.clock
connect clockNodeOut, clockNodeIn
connect tlNodeIn, auto.tl_in
connect auto.clock_out, clockNodeOut
connect clockNodeIn, auto.clock_in
wire tile_async_resets : Reset[2]
node _tile_async_resets_0_T = asAsyncReset(UInt<1>(0h1))
connect tile_async_resets[0], _tile_async_resets_0_T
inst r_tile_resets_0 of AsyncResetRegVec_w1_i0_10
connect r_tile_resets_0.clock, clock
connect r_tile_resets_0.reset, tile_async_resets[0]
node _tile_async_resets_1_T = asAsyncReset(UInt<1>(0h1))
connect tile_async_resets[1], _tile_async_resets_1_T
inst r_tile_resets_1 of AsyncResetRegVec_w1_i0_11
connect r_tile_resets_1.clock, clock
connect r_tile_resets_1.reset, tile_async_resets[1]
wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<9>, size : UInt<2>}}}}
node _in_bits_read_T = eq(tlNodeIn.a.bits.opcode, UInt<3>(0h4))
connect in.bits.read, _in_bits_read_T
node _in_bits_index_T = shr(tlNodeIn.a.bits.address, 3)
connect in.bits.index, _in_bits_index_T
connect in.bits.data, tlNodeIn.a.bits.data
connect in.bits.mask, tlNodeIn.a.bits.mask
connect in.bits.extra.tlrr_extra.source, tlNodeIn.a.bits.source
connect in.bits.extra.tlrr_extra.size, tlNodeIn.a.bits.size
wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tlrr_extra : { source : UInt<9>, size : UInt<2>}}}}
wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<9>, size : UInt<2>}}}}
connect out_front.bits, in.bits
node out_maskMatch = not(UInt<9>(0h0))
node out_findex = and(out_front.bits.index, out_maskMatch)
node out_bindex = and(out_front.bits.index, out_maskMatch)
node _out_T = eq(out_findex, UInt<9>(0h0))
node _out_T_1 = eq(out_bindex, UInt<9>(0h0))
wire out_rivalid : UInt<1>[2]
wire out_wivalid : UInt<1>[2]
wire out_roready : UInt<1>[2]
wire out_woready : UInt<1>[2]
node _out_frontMask_T = bits(out_front.bits.mask, 0, 0)
node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1)
node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2)
node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3)
node _out_frontMask_T_4 = bits(out_front.bits.mask, 4, 4)
node _out_frontMask_T_5 = bits(out_front.bits.mask, 5, 5)
node _out_frontMask_T_6 = bits(out_front.bits.mask, 6, 6)
node _out_frontMask_T_7 = bits(out_front.bits.mask, 7, 7)
node _out_frontMask_T_8 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_9 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_10 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_11 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_12 = mux(_out_frontMask_T_4, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_13 = mux(_out_frontMask_T_5, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_14 = mux(_out_frontMask_T_6, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_15 = mux(_out_frontMask_T_7, UInt<8>(0hff), UInt<8>(0h0))
node out_frontMask_lo_lo = cat(_out_frontMask_T_9, _out_frontMask_T_8)
node out_frontMask_lo_hi = cat(_out_frontMask_T_11, _out_frontMask_T_10)
node out_frontMask_lo = cat(out_frontMask_lo_hi, out_frontMask_lo_lo)
node out_frontMask_hi_lo = cat(_out_frontMask_T_13, _out_frontMask_T_12)
node out_frontMask_hi_hi = cat(_out_frontMask_T_15, _out_frontMask_T_14)
node out_frontMask_hi = cat(out_frontMask_hi_hi, out_frontMask_hi_lo)
node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo)
node _out_backMask_T = bits(out_front.bits.mask, 0, 0)
node _out_backMask_T_1 = bits(out_front.bits.mask, 1, 1)
node _out_backMask_T_2 = bits(out_front.bits.mask, 2, 2)
node _out_backMask_T_3 = bits(out_front.bits.mask, 3, 3)
node _out_backMask_T_4 = bits(out_front.bits.mask, 4, 4)
node _out_backMask_T_5 = bits(out_front.bits.mask, 5, 5)
node _out_backMask_T_6 = bits(out_front.bits.mask, 6, 6)
node _out_backMask_T_7 = bits(out_front.bits.mask, 7, 7)
node _out_backMask_T_8 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_9 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_10 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_11 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_12 = mux(_out_backMask_T_4, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_13 = mux(_out_backMask_T_5, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_14 = mux(_out_backMask_T_6, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_15 = mux(_out_backMask_T_7, UInt<8>(0hff), UInt<8>(0h0))
node out_backMask_lo_lo = cat(_out_backMask_T_9, _out_backMask_T_8)
node out_backMask_lo_hi = cat(_out_backMask_T_11, _out_backMask_T_10)
node out_backMask_lo = cat(out_backMask_lo_hi, out_backMask_lo_lo)
node out_backMask_hi_lo = cat(_out_backMask_T_13, _out_backMask_T_12)
node out_backMask_hi_hi = cat(_out_backMask_T_15, _out_backMask_T_14)
node out_backMask_hi = cat(out_backMask_hi_hi, out_backMask_hi_lo)
node out_backMask = cat(out_backMask_hi, out_backMask_lo)
node _out_rimask_T = bits(out_frontMask, 0, 0)
node out_rimask = orr(_out_rimask_T)
node _out_wimask_T = bits(out_frontMask, 0, 0)
node out_wimask = andr(_out_wimask_T)
node _out_romask_T = bits(out_backMask, 0, 0)
node out_romask = orr(_out_romask_T)
node _out_womask_T = bits(out_backMask, 0, 0)
node out_womask = andr(_out_womask_T)
node out_f_rivalid = and(out_rivalid[0], out_rimask)
node out_f_roready = and(out_roready[0], out_romask)
node out_f_wivalid = and(out_wivalid[0], out_wimask)
node out_f_woready = and(out_woready[0], out_womask)
node _out_T_2 = bits(out_front.bits.data, 0, 0)
connect r_tile_resets_0.io.en, out_f_woready
connect r_tile_resets_0.io.d, _out_T_2
node _out_T_3 = eq(out_rimask, UInt<1>(0h0))
node _out_T_4 = eq(out_wimask, UInt<1>(0h0))
node _out_T_5 = eq(out_romask, UInt<1>(0h0))
node _out_T_6 = eq(out_womask, UInt<1>(0h0))
node _out_T_7 = or(r_tile_resets_0.io.q, UInt<1>(0h0))
node _out_T_8 = bits(_out_T_7, 0, 0)
node _out_rimask_T_1 = bits(out_frontMask, 32, 32)
node out_rimask_1 = orr(_out_rimask_T_1)
node _out_wimask_T_1 = bits(out_frontMask, 32, 32)
node out_wimask_1 = andr(_out_wimask_T_1)
node _out_romask_T_1 = bits(out_backMask, 32, 32)
node out_romask_1 = orr(_out_romask_T_1)
node _out_womask_T_1 = bits(out_backMask, 32, 32)
node out_womask_1 = andr(_out_womask_T_1)
node out_f_rivalid_1 = and(out_rivalid[1], out_rimask_1)
node out_f_roready_1 = and(out_roready[1], out_romask_1)
node out_f_wivalid_1 = and(out_wivalid[1], out_wimask_1)
node out_f_woready_1 = and(out_woready[1], out_womask_1)
node _out_T_9 = bits(out_front.bits.data, 32, 32)
connect r_tile_resets_1.io.en, out_f_woready_1
connect r_tile_resets_1.io.d, _out_T_9
node _out_T_10 = eq(out_rimask_1, UInt<1>(0h0))
node _out_T_11 = eq(out_wimask_1, UInt<1>(0h0))
node _out_T_12 = eq(out_romask_1, UInt<1>(0h0))
node _out_T_13 = eq(out_womask_1, UInt<1>(0h0))
node _out_prepend_T = or(_out_T_8, UInt<32>(0h0))
node out_prepend = cat(r_tile_resets_1.io.q, _out_prepend_T)
node _out_T_14 = or(out_prepend, UInt<33>(0h0))
node _out_T_15 = bits(_out_T_14, 32, 0)
node _out_frontSel_T = dshl(UInt<1>(0h1), UInt<1>(0h0))
node out_frontSel_0 = bits(_out_frontSel_T, 0, 0)
node out_frontSel_1 = bits(_out_frontSel_T, 1, 1)
node _out_backSel_T = dshl(UInt<1>(0h1), UInt<1>(0h0))
node out_backSel_0 = bits(_out_backSel_T, 0, 0)
node out_backSel_1 = bits(_out_backSel_T, 1, 1)
node _out_rifireMux_T = and(in.valid, out_front.ready)
node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read)
wire out_rifireMux_out : UInt<1>
node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0)
node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T)
connect out_rifireMux_out, UInt<1>(0h1)
connect out_rivalid[1], _out_rifireMux_T_3
connect out_rivalid[0], _out_rifireMux_T_3
node _out_rifireMux_T_4 = eq(_out_T, UInt<1>(0h0))
node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4)
node _out_rifireMux_T_6 = geq(UInt<1>(0h0), UInt<1>(0h1))
wire _out_rifireMux_WIRE : UInt<1>[1]
connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5
node out_rifireMux = mux(_out_rifireMux_T_6, UInt<1>(0h1), _out_rifireMux_WIRE[0])
node _out_wifireMux_T = and(in.valid, out_front.ready)
node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0))
node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1)
wire out_wifireMux_out : UInt<1>
node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0)
node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T)
connect out_wifireMux_out, UInt<1>(0h1)
connect out_wivalid[1], _out_wifireMux_T_4
connect out_wivalid[0], _out_wifireMux_T_4
node _out_wifireMux_T_5 = eq(_out_T, UInt<1>(0h0))
node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5)
node _out_wifireMux_T_7 = geq(UInt<1>(0h0), UInt<1>(0h1))
wire _out_wifireMux_WIRE : UInt<1>[1]
connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6
node out_wifireMux = mux(_out_wifireMux_T_7, UInt<1>(0h1), _out_wifireMux_WIRE[0])
node _out_rofireMux_T = and(out_front.valid, out.ready)
node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_front.bits.read)
wire out_rofireMux_out : UInt<1>
node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0)
node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_1)
connect out_rofireMux_out, UInt<1>(0h1)
connect out_roready[1], _out_rofireMux_T_3
connect out_roready[0], _out_rofireMux_T_3
node _out_rofireMux_T_4 = eq(_out_T_1, UInt<1>(0h0))
node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4)
node _out_rofireMux_T_6 = geq(UInt<1>(0h0), UInt<1>(0h1))
wire _out_rofireMux_WIRE : UInt<1>[1]
connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5
node out_rofireMux = mux(_out_rofireMux_T_6, UInt<1>(0h1), _out_rofireMux_WIRE[0])
node _out_wofireMux_T = and(out_front.valid, out.ready)
node _out_wofireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0))
node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1)
wire out_wofireMux_out : UInt<1>
node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0)
node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_1)
connect out_wofireMux_out, UInt<1>(0h1)
connect out_woready[1], _out_wofireMux_T_4
connect out_woready[0], _out_wofireMux_T_4
node _out_wofireMux_T_5 = eq(_out_T_1, UInt<1>(0h0))
node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5)
node _out_wofireMux_T_7 = geq(UInt<1>(0h0), UInt<1>(0h1))
wire _out_wofireMux_WIRE : UInt<1>[1]
connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6
node out_wofireMux = mux(_out_wofireMux_T_7, UInt<1>(0h1), _out_wofireMux_WIRE[0])
node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux)
node out_oready = mux(out_front.bits.read, out_rofireMux, out_wofireMux)
node _out_in_ready_T = and(out_front.ready, out_iready)
connect in.ready, _out_in_ready_T
node _out_front_valid_T = and(in.valid, out_iready)
connect out_front.valid, _out_front_valid_T
node _out_front_ready_T = and(out.ready, out_oready)
connect out_front.ready, _out_front_ready_T
node _out_out_valid_T = and(out_front.valid, out_oready)
connect out.valid, _out_out_valid_T
connect out.bits.read, out_front.bits.read
node _out_out_bits_data_T = geq(UInt<1>(0h0), UInt<1>(0h1))
wire _out_out_bits_data_WIRE : UInt<1>[1]
connect _out_out_bits_data_WIRE[0], _out_T_1
node _out_out_bits_data_T_1 = mux(_out_out_bits_data_T, UInt<1>(0h1), _out_out_bits_data_WIRE[0])
node _out_out_bits_data_T_2 = geq(UInt<1>(0h0), UInt<1>(0h1))
wire _out_out_bits_data_WIRE_1 : UInt<33>[1]
connect _out_out_bits_data_WIRE_1[0], _out_T_15
node _out_out_bits_data_T_3 = mux(_out_out_bits_data_T_2, UInt<1>(0h0), _out_out_bits_data_WIRE_1[0])
node _out_out_bits_data_T_4 = mux(_out_out_bits_data_T_1, _out_out_bits_data_T_3, UInt<1>(0h0))
connect out.bits.data, _out_out_bits_data_T_4
connect out.bits.extra, out_front.bits.extra
connect in.valid, tlNodeIn.a.valid
connect tlNodeIn.a.ready, in.ready
connect tlNodeIn.d.valid, out.valid
connect out.ready, tlNodeIn.d.ready
wire tlNodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<9>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
connect tlNodeIn_d_bits_d.opcode, UInt<1>(0h0)
connect tlNodeIn_d_bits_d.param, UInt<1>(0h0)
connect tlNodeIn_d_bits_d.size, out.bits.extra.tlrr_extra.size
connect tlNodeIn_d_bits_d.source, out.bits.extra.tlrr_extra.source
connect tlNodeIn_d_bits_d.sink, UInt<1>(0h0)
connect tlNodeIn_d_bits_d.denied, UInt<1>(0h0)
invalidate tlNodeIn_d_bits_d.data
connect tlNodeIn_d_bits_d.corrupt, UInt<1>(0h0)
connect tlNodeIn.d.bits.corrupt, tlNodeIn_d_bits_d.corrupt
connect tlNodeIn.d.bits.data, tlNodeIn_d_bits_d.data
connect tlNodeIn.d.bits.denied, tlNodeIn_d_bits_d.denied
connect tlNodeIn.d.bits.sink, tlNodeIn_d_bits_d.sink
connect tlNodeIn.d.bits.source, tlNodeIn_d_bits_d.source
connect tlNodeIn.d.bits.size, tlNodeIn_d_bits_d.size
connect tlNodeIn.d.bits.param, tlNodeIn_d_bits_d.param
connect tlNodeIn.d.bits.opcode, tlNodeIn_d_bits_d.opcode
connect tlNodeIn.d.bits.data, out.bits.data
node _tlNodeIn_d_bits_opcode_T = mux(out.bits.read, UInt<1>(0h1), UInt<1>(0h0))
connect tlNodeIn.d.bits.opcode, _tlNodeIn_d_bits_opcode_T
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<9>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<21>(0h0)
connect _WIRE.bits.source, UInt<9>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<9>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
connect _WIRE_1.valid, UInt<1>(0h0)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<21>(0h0)
connect _WIRE_2.bits.source, UInt<9>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<9>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.ready, UInt<1>(0h1)
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1)
connect clockNodeOut.member.allClocks_uncore.clock, clockNodeIn.member.allClocks_uncore.clock
connect clockNodeOut.member.allClocks_uncore.reset, clockNodeIn.member.allClocks_uncore.reset
extmodule plusarg_reader_46 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_47 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TileResetSetter( // @[TileResetSetter.scala:26:25]
input clock, // @[TileResetSetter.scala:26:25]
input reset, // @[TileResetSetter.scala:26:25]
input auto_clock_in_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25]
output auto_clock_out_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25]
output auto_clock_out_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25]
output auto_tl_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [8:0] auto_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [20:0] auto_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_tl_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_tl_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [8:0] auto_tl_in_d_bits_source // @[LazyModuleImp.scala:107:25]
);
wire out_front_valid; // @[RegisterRouter.scala:87:24]
wire out_front_ready; // @[RegisterRouter.scala:87:24]
wire out_bits_read; // @[RegisterRouter.scala:87:24]
wire [8:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24]
wire [8:0] in_bits_index; // @[RegisterRouter.scala:73:18]
wire in_bits_read; // @[RegisterRouter.scala:73:18]
wire auto_clock_in_member_allClocks_uncore_clock_0 = auto_clock_in_member_allClocks_uncore_clock; // @[TileResetSetter.scala:26:25]
wire auto_clock_in_member_allClocks_uncore_reset_0 = auto_clock_in_member_allClocks_uncore_reset; // @[TileResetSetter.scala:26:25]
wire auto_tl_in_a_valid_0 = auto_tl_in_a_valid; // @[TileResetSetter.scala:26:25]
wire [2:0] auto_tl_in_a_bits_opcode_0 = auto_tl_in_a_bits_opcode; // @[TileResetSetter.scala:26:25]
wire [2:0] auto_tl_in_a_bits_param_0 = auto_tl_in_a_bits_param; // @[TileResetSetter.scala:26:25]
wire [1:0] auto_tl_in_a_bits_size_0 = auto_tl_in_a_bits_size; // @[TileResetSetter.scala:26:25]
wire [8:0] auto_tl_in_a_bits_source_0 = auto_tl_in_a_bits_source; // @[TileResetSetter.scala:26:25]
wire [20:0] auto_tl_in_a_bits_address_0 = auto_tl_in_a_bits_address; // @[TileResetSetter.scala:26:25]
wire [7:0] auto_tl_in_a_bits_mask_0 = auto_tl_in_a_bits_mask; // @[TileResetSetter.scala:26:25]
wire [63:0] auto_tl_in_a_bits_data_0 = auto_tl_in_a_bits_data; // @[TileResetSetter.scala:26:25]
wire auto_tl_in_a_bits_corrupt_0 = auto_tl_in_a_bits_corrupt; // @[TileResetSetter.scala:26:25]
wire auto_tl_in_d_ready_0 = auto_tl_in_d_ready; // @[TileResetSetter.scala:26:25]
wire [1:0] _out_frontSel_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _out_backSel_T = 2'h1; // @[OneHot.scala:58:35]
wire [8:0] out_maskMatch = 9'h1FF; // @[RegisterRouter.scala:87:24]
wire tile_async_resets_0 = 1'h1; // @[TileResetSetter.scala:29:33]
wire tile_async_resets_1 = 1'h1; // @[TileResetSetter.scala:29:33]
wire _tile_async_resets_0_T = 1'h1; // @[TileResetSetter.scala:31:38]
wire _tile_async_resets_1_T = 1'h1; // @[TileResetSetter.scala:31:38]
wire out_frontSel_0 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_backSel_0 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_wofireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_oready = 1'h1; // @[RegisterRouter.scala:87:24]
wire [2:0] tlNodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17]
wire [1:0] auto_tl_in_d_bits_param = 2'h0; // @[TileResetSetter.scala:26:25]
wire [1:0] tlNodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] tlNodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17]
wire [31:0] _out_prepend_T = 32'h0; // @[RegisterRouter.scala:87:24]
wire [32:0] out_prepend = 33'h0; // @[MuxLiteral.scala:49:{10,48}]
wire [32:0] _out_T_14 = 33'h0; // @[MuxLiteral.scala:49:{10,48}]
wire [32:0] _out_T_15 = 33'h0; // @[MuxLiteral.scala:49:{10,48}]
wire [32:0] _out_out_bits_data_WIRE_1_0 = 33'h0; // @[MuxLiteral.scala:49:{10,48}]
wire [32:0] _out_out_bits_data_T_3 = 33'h0; // @[MuxLiteral.scala:49:{10,48}]
wire [32:0] _out_out_bits_data_T_4 = 33'h0; // @[MuxLiteral.scala:49:{10,48}]
wire auto_tl_in_d_bits_sink = 1'h0; // @[TileResetSetter.scala:26:25]
wire auto_tl_in_d_bits_denied = 1'h0; // @[TileResetSetter.scala:26:25]
wire auto_tl_in_d_bits_corrupt = 1'h0; // @[TileResetSetter.scala:26:25]
wire tlNodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17]
wire tlNodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17]
wire tlNodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire _out_T_7 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_8 = 1'h0; // @[RegisterRouter.scala:87:24]
wire out_frontSel_1 = 1'h0; // @[RegisterRouter.scala:87:24]
wire out_backSel_1 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_6 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_wifireMux_T_7 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_rofireMux_T_6 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_wofireMux_T_7 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17]
wire tlNodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17]
wire tlNodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17]
wire tlNodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17]
wire [63:0] auto_tl_in_d_bits_data = 64'h0; // @[TileResetSetter.scala:26:25]
wire [63:0] tlNodeIn_d_bits_data = 64'h0; // @[MixedNode.scala:551:17]
wire [63:0] out_bits_data = 64'h0; // @[RegisterRouter.scala:87:24]
wire [63:0] tlNodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17]
wire clockNodeIn_member_allClocks_uncore_clock = auto_clock_in_member_allClocks_uncore_clock_0; // @[MixedNode.scala:551:17]
wire clockNodeOut_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17]
wire clockNodeIn_member_allClocks_uncore_reset = auto_clock_in_member_allClocks_uncore_reset_0; // @[MixedNode.scala:551:17]
wire clockNodeOut_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17]
wire tlNodeIn_a_ready; // @[MixedNode.scala:551:17]
wire tlNodeIn_a_valid = auto_tl_in_a_valid_0; // @[MixedNode.scala:551:17]
wire [2:0] tlNodeIn_a_bits_opcode = auto_tl_in_a_bits_opcode_0; // @[MixedNode.scala:551:17]
wire [2:0] tlNodeIn_a_bits_param = auto_tl_in_a_bits_param_0; // @[MixedNode.scala:551:17]
wire [1:0] tlNodeIn_a_bits_size = auto_tl_in_a_bits_size_0; // @[MixedNode.scala:551:17]
wire [8:0] tlNodeIn_a_bits_source = auto_tl_in_a_bits_source_0; // @[MixedNode.scala:551:17]
wire [20:0] tlNodeIn_a_bits_address = auto_tl_in_a_bits_address_0; // @[MixedNode.scala:551:17]
wire [7:0] tlNodeIn_a_bits_mask = auto_tl_in_a_bits_mask_0; // @[MixedNode.scala:551:17]
wire [63:0] tlNodeIn_a_bits_data = auto_tl_in_a_bits_data_0; // @[MixedNode.scala:551:17]
wire tlNodeIn_a_bits_corrupt = auto_tl_in_a_bits_corrupt_0; // @[MixedNode.scala:551:17]
wire tlNodeIn_d_ready = auto_tl_in_d_ready_0; // @[MixedNode.scala:551:17]
wire tlNodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] tlNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] tlNodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [8:0] tlNodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire auto_clock_out_member_allClocks_uncore_clock_0; // @[TileResetSetter.scala:26:25]
wire auto_clock_out_member_allClocks_uncore_reset_0; // @[TileResetSetter.scala:26:25]
wire auto_tl_in_a_ready_0; // @[TileResetSetter.scala:26:25]
wire [2:0] auto_tl_in_d_bits_opcode_0; // @[TileResetSetter.scala:26:25]
wire [1:0] auto_tl_in_d_bits_size_0; // @[TileResetSetter.scala:26:25]
wire [8:0] auto_tl_in_d_bits_source_0; // @[TileResetSetter.scala:26:25]
wire auto_tl_in_d_valid_0; // @[TileResetSetter.scala:26:25]
wire in_ready; // @[RegisterRouter.scala:73:18]
assign auto_tl_in_a_ready_0 = tlNodeIn_a_ready; // @[MixedNode.scala:551:17]
wire in_valid = tlNodeIn_a_valid; // @[RegisterRouter.scala:73:18]
wire [1:0] in_bits_extra_tlrr_extra_size = tlNodeIn_a_bits_size; // @[RegisterRouter.scala:73:18]
wire [8:0] in_bits_extra_tlrr_extra_source = tlNodeIn_a_bits_source; // @[RegisterRouter.scala:73:18]
wire [7:0] in_bits_mask = tlNodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18]
wire [63:0] in_bits_data = tlNodeIn_a_bits_data; // @[RegisterRouter.scala:73:18]
wire out_ready = tlNodeIn_d_ready; // @[RegisterRouter.scala:87:24]
wire out_valid; // @[RegisterRouter.scala:87:24]
assign auto_tl_in_d_valid_0 = tlNodeIn_d_valid; // @[MixedNode.scala:551:17]
assign auto_tl_in_d_bits_opcode_0 = tlNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] tlNodeIn_d_bits_d_size; // @[Edges.scala:792:17]
assign auto_tl_in_d_bits_size_0 = tlNodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [8:0] tlNodeIn_d_bits_d_source; // @[Edges.scala:792:17]
assign auto_tl_in_d_bits_source_0 = tlNodeIn_d_bits_source; // @[MixedNode.scala:551:17]
assign auto_clock_out_member_allClocks_uncore_clock_0 = clockNodeOut_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17]
assign auto_clock_out_member_allClocks_uncore_reset_0 = clockNodeOut_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17]
assign clockNodeOut_member_allClocks_uncore_clock = clockNodeIn_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17, :551:17]
assign clockNodeOut_member_allClocks_uncore_reset = clockNodeIn_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17, :551:17]
wire _out_in_ready_T; // @[RegisterRouter.scala:87:24]
assign tlNodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18]
wire _in_bits_read_T; // @[RegisterRouter.scala:74:36]
wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24]
wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24]
wire [8:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24]
wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24]
wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24]
wire [8:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24]
wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24]
assign _in_bits_read_T = tlNodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36]
assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36]
wire [17:0] _in_bits_index_T = tlNodeIn_a_bits_address[20:3]; // @[Edges.scala:192:34]
assign in_bits_index = _in_bits_index_T[8:0]; // @[RegisterRouter.scala:73:18, :75:19]
wire _out_front_ready_T = out_ready; // @[RegisterRouter.scala:87:24]
wire _out_out_valid_T; // @[RegisterRouter.scala:87:24]
assign tlNodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24]
wire _tlNodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25]
assign tlNodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24]
wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24]
assign tlNodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24]
assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24]
assign _out_out_valid_T = out_front_valid; // @[RegisterRouter.scala:87:24]
assign out_bits_read = out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire [8:0] out_findex = out_front_bits_index; // @[RegisterRouter.scala:87:24]
wire [8:0] out_bindex = out_front_bits_index; // @[RegisterRouter.scala:87:24]
assign out_bits_extra_tlrr_extra_source = out_front_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24]
assign out_bits_extra_tlrr_extra_size = out_front_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24]
wire _out_T = out_findex == 9'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_1 = out_bindex == 9'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
wire _out_out_bits_data_WIRE_0 = _out_T_1; // @[MuxLiteral.scala:49:48]
wire out_rivalid_0; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
wire out_wivalid_0; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
wire out_roready_0; // @[RegisterRouter.scala:87:24]
wire out_roready_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
wire out_woready_0; // @[RegisterRouter.scala:87:24]
wire out_woready_1; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24]
wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24]
wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24]
wire out_rimask = _out_rimask_T; // @[RegisterRouter.scala:87:24]
wire out_wimask = _out_wimask_T; // @[RegisterRouter.scala:87:24]
wire _out_romask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24]
wire out_romask = _out_romask_T; // @[RegisterRouter.scala:87:24]
wire out_womask = _out_womask_T; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24]
wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24]
wire out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24]
wire _out_T_2 = out_front_bits_data[0]; // @[RegisterRouter.scala:87:24]
wire _out_T_3 = ~out_rimask; // @[RegisterRouter.scala:87:24]
wire _out_T_4 = ~out_wimask; // @[RegisterRouter.scala:87:24]
wire _out_T_5 = ~out_romask; // @[RegisterRouter.scala:87:24]
wire _out_T_6 = ~out_womask; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_1 = out_frontMask[32]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_1 = out_frontMask[32]; // @[RegisterRouter.scala:87:24]
wire out_rimask_1 = _out_rimask_T_1; // @[RegisterRouter.scala:87:24]
wire out_wimask_1 = _out_wimask_T_1; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_1 = out_backMask[32]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_1 = out_backMask[32]; // @[RegisterRouter.scala:87:24]
wire out_romask_1 = _out_romask_T_1; // @[RegisterRouter.scala:87:24]
wire out_womask_1 = _out_womask_T_1; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1 = out_rivalid_1 & out_rimask_1; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1 = out_roready_1 & out_romask_1; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1 = out_wivalid_1 & out_wimask_1; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1 = out_woready_1 & out_womask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_9 = out_front_bits_data[32]; // @[RegisterRouter.scala:87:24]
wire _out_T_10 = ~out_rimask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_11 = ~out_wimask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_12 = ~out_romask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_13 = ~out_womask_1; // @[RegisterRouter.scala:87:24]
wire _GEN = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24]
wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T = _GEN; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T = _GEN; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_2 = _out_rifireMux_T_1; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T; // @[RegisterRouter.scala:87:24]
assign out_rivalid_0 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_4 = ~_out_T; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_3 = _out_wifireMux_T_2; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T; // @[RegisterRouter.scala:87:24]
assign out_wivalid_0 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_5 = ~_out_T; // @[RegisterRouter.scala:87:24]
wire _GEN_0 = out_front_valid & out_ready; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T = _GEN_0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T = _GEN_0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1 = _out_rofireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_2 = _out_rofireMux_T_1; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_1; // @[RegisterRouter.scala:87:24]
assign out_roready_0 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_1 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_4 = ~_out_T_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_3 = _out_wofireMux_T_2; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_1; // @[RegisterRouter.scala:87:24]
assign out_woready_0 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_woready_1 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_5 = ~_out_T_1; // @[RegisterRouter.scala:87:24]
assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24]
assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24]
assign out_front_ready = _out_front_ready_T; // @[RegisterRouter.scala:87:24]
assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24]
wire _out_out_bits_data_T_1 = _out_out_bits_data_WIRE_0; // @[MuxLiteral.scala:49:{10,48}]
assign tlNodeIn_d_bits_size = tlNodeIn_d_bits_d_size; // @[Edges.scala:792:17]
assign tlNodeIn_d_bits_source = tlNodeIn_d_bits_d_source; // @[Edges.scala:792:17]
assign tlNodeIn_d_bits_opcode = {2'h0, _tlNodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}]
TLMonitor_22 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (tlNodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (tlNodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (tlNodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (tlNodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (tlNodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (tlNodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (tlNodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (tlNodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (tlNodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (tlNodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (tlNodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (tlNodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (tlNodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (tlNodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (tlNodeIn_d_bits_source) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
AsyncResetRegVec_w1_i0_10 r_tile_resets_0 ( // @[TileResetSetter.scala:33:15]
.clock (clock),
.io_d (_out_T_2), // @[RegisterRouter.scala:87:24]
.io_en (out_f_woready) // @[RegisterRouter.scala:87:24]
); // @[TileResetSetter.scala:33:15]
AsyncResetRegVec_w1_i0_11 r_tile_resets_1 ( // @[TileResetSetter.scala:33:15]
.clock (clock),
.io_d (_out_T_9), // @[RegisterRouter.scala:87:24]
.io_en (out_f_woready_1) // @[RegisterRouter.scala:87:24]
); // @[TileResetSetter.scala:33:15]
assign auto_clock_out_member_allClocks_uncore_clock = auto_clock_out_member_allClocks_uncore_clock_0; // @[TileResetSetter.scala:26:25]
assign auto_clock_out_member_allClocks_uncore_reset = auto_clock_out_member_allClocks_uncore_reset_0; // @[TileResetSetter.scala:26:25]
assign auto_tl_in_a_ready = auto_tl_in_a_ready_0; // @[TileResetSetter.scala:26:25]
assign auto_tl_in_d_valid = auto_tl_in_d_valid_0; // @[TileResetSetter.scala:26:25]
assign auto_tl_in_d_bits_opcode = auto_tl_in_d_bits_opcode_0; // @[TileResetSetter.scala:26:25]
assign auto_tl_in_d_bits_size = auto_tl_in_d_bits_size_0; // @[TileResetSetter.scala:26:25]
assign auto_tl_in_d_bits_source = auto_tl_in_d_bits_source_0; // @[TileResetSetter.scala:26:25]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie6_is32_oe8_os24_12 :
output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<8>, sig : UInt<33>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0))
node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1))
node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2))
node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3))
node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4))
node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6))
node _roundMagUp_T = and(roundingMode_min, io.in.sign)
node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0))
node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1)
node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2)
node _sAdjustedExp_T = add(io.in.sExp, asSInt(UInt<9>(0hc0)))
node _sAdjustedExp_T_1 = bits(_sAdjustedExp_T, 8, 0)
node sAdjustedExp = cvt(_sAdjustedExp_T_1)
node _adjustedSig_T = bits(io.in.sig, 32, 7)
node _adjustedSig_T_1 = bits(io.in.sig, 6, 0)
node _adjustedSig_T_2 = orr(_adjustedSig_T_1)
node adjustedSig = cat(_adjustedSig_T, _adjustedSig_T_2)
wire common_expOut : UInt<9>
wire common_fractOut : UInt<23>
wire common_overflow : UInt<1>
wire common_totalUnderflow : UInt<1>
wire common_underflow : UInt<1>
wire common_inexact : UInt<1>
node _roundMask_T = cat(UInt<24>(0h0), UInt<1>(0h0))
node roundMask = cat(_roundMask_T, UInt<2>(0h3))
node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask)
node shiftedRoundMask = shr(_shiftedRoundMask_T, 1)
node _roundPosMask_T = not(shiftedRoundMask)
node roundPosMask = and(_roundPosMask_T, roundMask)
node _roundPosBit_T = and(adjustedSig, roundPosMask)
node roundPosBit = orr(_roundPosBit_T)
node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask)
node anyRoundExtra = orr(_anyRoundExtra_T)
node anyRound = or(roundPosBit, anyRoundExtra)
node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit)
node _roundIncr_T_2 = and(roundMagUp, anyRound)
node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2)
node _roundedSig_T = or(adjustedSig, roundMask)
node _roundedSig_T_1 = shr(_roundedSig_T, 2)
node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1))
node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit)
node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0))
node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4)
node _roundedSig_T_6 = shr(roundMask, 1)
node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<26>(0h0))
node _roundedSig_T_8 = not(_roundedSig_T_7)
node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8)
node _roundedSig_T_10 = not(roundMask)
node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10)
node _roundedSig_T_12 = shr(_roundedSig_T_11, 2)
node _roundedSig_T_13 = and(roundingMode_odd, anyRound)
node _roundedSig_T_14 = shr(roundPosMask, 1)
node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0))
node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15)
node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16)
node _sRoundedExp_T = shr(roundedSig, 24)
node _sRoundedExp_T_1 = cvt(_sRoundedExp_T)
node sRoundedExp = add(sAdjustedExp, _sRoundedExp_T_1)
node _common_expOut_T = bits(sRoundedExp, 8, 0)
connect common_expOut, _common_expOut_T
node _common_fractOut_T = bits(roundedSig, 23, 1)
node _common_fractOut_T_1 = bits(roundedSig, 22, 0)
node _common_fractOut_T_2 = mux(UInt<1>(0h0), _common_fractOut_T, _common_fractOut_T_1)
connect common_fractOut, _common_fractOut_T_2
connect common_overflow, UInt<1>(0h0)
connect common_totalUnderflow, UInt<1>(0h0)
node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2)
node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1)
node unboundedRange_roundPosBit = mux(UInt<1>(0h0), _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1)
node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2)
node _unboundedRange_anyRound_T_1 = and(UInt<1>(0h0), _unboundedRange_anyRound_T)
node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0)
node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2)
node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3)
node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit)
node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound)
node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2)
node _roundCarry_T = bits(roundedSig, 25, 25)
node _roundCarry_T_1 = bits(roundedSig, 24, 24)
node roundCarry = mux(UInt<1>(0h0), _roundCarry_T, _roundCarry_T_1)
connect common_underflow, UInt<1>(0h0)
node _common_inexact_T = or(common_totalUnderflow, anyRound)
connect common_inexact, _common_inexact_T
node isNaNOut = or(io.invalidExc, io.in.isNaN)
node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf)
node _commonCase_T = eq(isNaNOut, UInt<1>(0h0))
node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0))
node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1)
node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0))
node commonCase = and(_commonCase_T_2, _commonCase_T_3)
node overflow = and(commonCase, common_overflow)
node underflow = and(commonCase, common_underflow)
node _inexact_T = and(commonCase, common_inexact)
node inexact = or(overflow, _inexact_T)
node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp)
node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow)
node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd)
node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1)
node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0))
node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T)
node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp)
node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T)
node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign)
node _expOut_T = or(io.in.isZero, common_totalUnderflow)
node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0))
node _expOut_T_2 = not(_expOut_T_1)
node _expOut_T_3 = and(common_expOut, _expOut_T_2)
node _expOut_T_4 = not(UInt<9>(0h6b))
node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0))
node _expOut_T_6 = not(_expOut_T_5)
node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6)
node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0))
node _expOut_T_9 = not(_expOut_T_8)
node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9)
node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0))
node _expOut_T_12 = not(_expOut_T_11)
node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12)
node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0))
node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14)
node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0))
node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16)
node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0))
node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18)
node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0))
node expOut = or(_expOut_T_19, _expOut_T_20)
node _fractOut_T = or(isNaNOut, io.in.isZero)
node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow)
node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0))
node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut)
node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0))
node fractOut = or(_fractOut_T_3, _fractOut_T_4)
node _io_out_T = cat(signOut, expOut)
node _io_out_T_1 = cat(_io_out_T, fractOut)
connect io.out, _io_out_T_1
node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc)
node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow)
node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact)
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RoundAnyRawFNToRecFN_ie6_is32_oe8_os24_12( // @[RoundAnyRawFNToRecFN.scala:48:5]
input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [7:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [32:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16]
);
wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [7:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [32:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [24:0] _roundMask_T = 25'h0; // @[RoundAnyRawFNToRecFN.scala:153:36]
wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19]
wire [26:0] roundMask = 27'h3; // @[RoundAnyRawFNToRecFN.scala:153:55]
wire [27:0] _shiftedRoundMask_T = 28'h3; // @[RoundAnyRawFNToRecFN.scala:162:41]
wire [26:0] shiftedRoundMask = 27'h1; // @[RoundAnyRawFNToRecFN.scala:162:53]
wire [26:0] _roundPosMask_T = 27'h7FFFFFE; // @[RoundAnyRawFNToRecFN.scala:163:28]
wire [26:0] roundPosMask = 27'h2; // @[RoundAnyRawFNToRecFN.scala:163:46]
wire [26:0] _roundedSig_T_10 = 27'h7FFFFFC; // @[RoundAnyRawFNToRecFN.scala:180:32]
wire [25:0] _roundedSig_T_6 = 26'h1; // @[RoundAnyRawFNToRecFN.scala:177:35, :181:67]
wire [25:0] _roundedSig_T_14 = 26'h1; // @[RoundAnyRawFNToRecFN.scala:177:35, :181:67]
wire [25:0] _roundedSig_T_15 = 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:24]
wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14, :265:14]
wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14, :265:14]
wire [8:0] _expOut_T_12 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14, :265:14]
wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:257:18]
wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:261:18]
wire [8:0] _expOut_T_11 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:265:18]
wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:269:16]
wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:273:16]
wire [8:0] _expOut_T_18 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:277:16]
wire [8:0] _expOut_T_20 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:278:16]
wire [22:0] _fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:281:16, :284:13]
wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:281:16, :284:13]
wire [1:0] _io_exceptionFlags_T = 2'h0; // @[RoundAnyRawFNToRecFN.scala:288:23]
wire [3:0] _io_exceptionFlags_T_2 = 4'h0; // @[RoundAnyRawFNToRecFN.scala:288:53]
wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:90:53]
wire _roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:169:38]
wire _unboundedRange_roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:207:38]
wire _commonCase_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:237:22]
wire _commonCase_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:237:36]
wire _commonCase_T_2 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:237:33]
wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:32]
wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:60]
wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41]
wire [2:0] _io_exceptionFlags_T_1 = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41]
wire io_invalidExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isNaN = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isInf = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53]
wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53]
wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53]
wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53]
wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53]
wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27]
wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63]
wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42]
wire common_overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:124:37]
wire common_totalUnderflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:125:37]
wire common_underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:126:37]
wire _roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:171:29]
wire _roundedSig_T_13 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:181:42]
wire _unboundedRange_anyRound_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:205:30]
wire _unboundedRange_roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:209:29]
wire isNaNOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:235:34]
wire notNaN_isSpecialInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:236:49]
wire overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:238:32]
wire underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:239:32]
wire _pegMinNonzeroMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:20]
wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60]
wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45]
wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42]
wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39]
wire _notNaN_isInfOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:45]
wire notNaN_isInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:32]
wire _expOut_T = io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :253:32]
wire _fractOut_T = io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :280:22]
wire signOut = io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :250:22]
wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33]
wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66]
wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66]
wire [9:0] _sAdjustedExp_T = {{2{io_in_sExp_0[7]}}, io_in_sExp_0} + 10'hC0; // @[RoundAnyRawFNToRecFN.scala:48:5, :104:25]
wire [8:0] _sAdjustedExp_T_1 = _sAdjustedExp_T[8:0]; // @[RoundAnyRawFNToRecFN.scala:104:25, :106:14]
wire [9:0] sAdjustedExp = {1'h0, _sAdjustedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:106:{14,31}]
wire [25:0] _adjustedSig_T = io_in_sig_0[32:7]; // @[RoundAnyRawFNToRecFN.scala:48:5, :116:23]
wire [6:0] _adjustedSig_T_1 = io_in_sig_0[6:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :117:26]
wire _adjustedSig_T_2 = |_adjustedSig_T_1; // @[RoundAnyRawFNToRecFN.scala:117:{26,60}]
wire [26:0] adjustedSig = {_adjustedSig_T, _adjustedSig_T_2}; // @[RoundAnyRawFNToRecFN.scala:116:{23,66}, :117:60]
wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37]
wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31]
wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16]
wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31]
wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49]
wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37]
wire [26:0] _roundPosBit_T = adjustedSig & 27'h2; // @[RoundAnyRawFNToRecFN.scala:116:66, :163:46, :164:40]
wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}]
wire _roundIncr_T_1 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:67]
wire _roundedSig_T_3 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :175:49]
wire [26:0] _anyRoundExtra_T = adjustedSig & 27'h1; // @[RoundAnyRawFNToRecFN.scala:116:66, :162:53, :165:42]
wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}]
wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36]
assign _common_inexact_T = anyRound; // @[RoundAnyRawFNToRecFN.scala:166:36, :230:49]
wire roundIncr = _roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31]
wire [26:0] _roundedSig_T = adjustedSig | 27'h3; // @[RoundAnyRawFNToRecFN.scala:116:66, :153:55, :174:32]
wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}]
wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}, :177:35, :181:67]
wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30]
wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30]
wire [25:0] _roundedSig_T_7 = {25'h0, _roundedSig_T_5}; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}]
wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}]
wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21]
wire [26:0] _roundedSig_T_11 = adjustedSig & 27'h7FFFFFC; // @[RoundAnyRawFNToRecFN.scala:116:66, :180:{30,32}]
wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}]
wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12}; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}]
wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47]
wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54]
wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}]
wire [10:0] sRoundedExp = {sAdjustedExp[9], sAdjustedExp} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:106:31, :185:{40,76}]
assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37]
assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37]
wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27]
wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27]
assign _common_fractOut_T_2 = _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:189:16, :191:27]
assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16]
wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:116:66, :203:45]
wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:116:66, :203:45, :205:44]
wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:116:66, :203:61]
wire unboundedRange_roundPosBit = _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:203:{16,61}]
wire _unboundedRange_roundIncr_T_1 = unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:67]
wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:116:66, :205:63]
wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}]
wire unboundedRange_anyRound = _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{49,70}]
wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46]
wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27]
wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27]
wire roundCarry = _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:211:16, :213:27]
assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49]
wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64]
wire commonCase = _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{61,64}]
wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43]
wire inexact = _inexact_T; // @[RoundAnyRawFNToRecFN.scala:240:{28,43}]
wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}]
wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}]
wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14]
wire [8:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17]
wire [8:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17]
wire [8:0] _expOut_T_13 = _expOut_T_10; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17]
wire [8:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18]
wire [8:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15]
wire [8:0] _expOut_T_19 = _expOut_T_17; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15]
wire [8:0] expOut = _expOut_T_19; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73]
wire _fractOut_T_1 = _fractOut_T; // @[RoundAnyRawFNToRecFN.scala:280:{22,38}]
wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? 23'h0 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16, :284:13]
wire [22:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11]
wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23]
assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}]
assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33]
assign _io_exceptionFlags_T_3 = {4'h0, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}]
assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66]
assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLFragmenter_1 :
input clock : Clock
input reset : Reset
output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<13>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}}
wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}
invalidate anonIn.d.bits.corrupt
invalidate anonIn.d.bits.data
invalidate anonIn.d.bits.denied
invalidate anonIn.d.bits.sink
invalidate anonIn.d.bits.source
invalidate anonIn.d.bits.size
invalidate anonIn.d.bits.param
invalidate anonIn.d.bits.opcode
invalidate anonIn.d.valid
invalidate anonIn.d.ready
invalidate anonIn.a.bits.corrupt
invalidate anonIn.a.bits.data
invalidate anonIn.a.bits.mask
invalidate anonIn.a.bits.address
invalidate anonIn.a.bits.source
invalidate anonIn.a.bits.size
invalidate anonIn.a.bits.param
invalidate anonIn.a.bits.opcode
invalidate anonIn.a.valid
invalidate anonIn.a.ready
wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<13>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}
invalidate anonOut.d.bits.corrupt
invalidate anonOut.d.bits.data
invalidate anonOut.d.bits.denied
invalidate anonOut.d.bits.sink
invalidate anonOut.d.bits.source
invalidate anonOut.d.bits.size
invalidate anonOut.d.bits.param
invalidate anonOut.d.bits.opcode
invalidate anonOut.d.valid
invalidate anonOut.d.ready
invalidate anonOut.a.bits.corrupt
invalidate anonOut.a.bits.data
invalidate anonOut.a.bits.mask
invalidate anonOut.a.bits.address
invalidate anonOut.a.bits.source
invalidate anonOut.a.bits.size
invalidate anonOut.a.bits.param
invalidate anonOut.a.bits.opcode
invalidate anonOut.a.valid
invalidate anonOut.a.ready
connect auto.anon_out, anonOut
connect anonIn, auto.anon_in
regreset acknum : UInt<4>, clock, reset, UInt<4>(0h0)
reg dOrig : UInt, clock
regreset dToggle : UInt<1>, clock, reset, UInt<1>(0h0)
node dFragnum = bits(anonOut.d.bits.source, 3, 0)
node dFirst = eq(acknum, UInt<1>(0h0))
node dLast = eq(dFragnum, UInt<1>(0h0))
node dsizeOH_shiftAmount = bits(anonOut.d.bits.size, 1, 0)
node _dsizeOH_T = dshl(UInt<1>(0h1), dsizeOH_shiftAmount)
node dsizeOH = bits(_dsizeOH_T, 2, 0)
node _dsizeOH1_T = dshl(UInt<2>(0h3), anonOut.d.bits.size)
node _dsizeOH1_T_1 = bits(_dsizeOH1_T, 1, 0)
node dsizeOH1 = not(_dsizeOH1_T_1)
node dHasData = bits(anonOut.d.bits.opcode, 0, 0)
node acknum_fragment = shl(dFragnum, 0)
node acknum_size = shr(dsizeOH1, 2)
node _T = eq(anonOut.d.valid, UInt<1>(0h0))
node _T_1 = and(acknum_fragment, acknum_size)
node _T_2 = eq(_T_1, UInt<1>(0h0))
node _T_3 = or(_T, _T_2)
node _T_4 = asUInt(reset)
node _T_5 = eq(_T_4, UInt<1>(0h0))
when _T_5 :
node _T_6 = eq(_T_3, UInt<1>(0h0))
when _T_6 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:214 assert (!out.d.valid || (acknum_fragment & acknum_size) === 0.U)\n") : printf
assert(clock, _T_3, UInt<1>(0h1), "") : assert
node _dFirst_acknum_T = mux(dHasData, acknum_size, UInt<1>(0h0))
node dFirst_acknum = or(acknum_fragment, _dFirst_acknum_T)
node _ack_decrement_T = shr(dsizeOH, 2)
node ack_decrement = mux(dHasData, UInt<1>(0h1), _ack_decrement_T)
node _dFirst_size_T = shl(dFragnum, 2)
node _dFirst_size_T_1 = or(_dFirst_size_T, dsizeOH1)
node _dFirst_size_T_2 = shl(_dFirst_size_T_1, 1)
node _dFirst_size_T_3 = or(_dFirst_size_T_2, UInt<1>(0h1))
node _dFirst_size_T_4 = cat(UInt<1>(0h0), _dFirst_size_T_1)
node _dFirst_size_T_5 = not(_dFirst_size_T_4)
node _dFirst_size_T_6 = and(_dFirst_size_T_3, _dFirst_size_T_5)
node dFirst_size_hi = bits(_dFirst_size_T_6, 6, 4)
node dFirst_size_lo = bits(_dFirst_size_T_6, 3, 0)
node _dFirst_size_T_7 = orr(dFirst_size_hi)
node _dFirst_size_T_8 = or(dFirst_size_hi, dFirst_size_lo)
node dFirst_size_hi_1 = bits(_dFirst_size_T_8, 3, 2)
node dFirst_size_lo_1 = bits(_dFirst_size_T_8, 1, 0)
node _dFirst_size_T_9 = orr(dFirst_size_hi_1)
node _dFirst_size_T_10 = or(dFirst_size_hi_1, dFirst_size_lo_1)
node _dFirst_size_T_11 = bits(_dFirst_size_T_10, 1, 1)
node _dFirst_size_T_12 = cat(_dFirst_size_T_9, _dFirst_size_T_11)
node dFirst_size = cat(_dFirst_size_T_7, _dFirst_size_T_12)
node _T_7 = and(anonOut.d.ready, anonOut.d.valid)
when _T_7 :
node _acknum_T = sub(acknum, ack_decrement)
node _acknum_T_1 = tail(_acknum_T, 1)
node _acknum_T_2 = mux(dFirst, dFirst_acknum, _acknum_T_1)
connect acknum, _acknum_T_2
when dFirst :
connect dOrig, dFirst_size
node _dToggle_T = bits(anonOut.d.bits.source, 4, 4)
connect dToggle, _dToggle_T
node doEarlyAck = bits(anonOut.d.bits.source, 5, 5)
node _drop_T = eq(dHasData, UInt<1>(0h0))
node _drop_T_1 = mux(doEarlyAck, dFirst, dLast)
node _drop_T_2 = eq(_drop_T_1, UInt<1>(0h0))
node drop = and(_drop_T, _drop_T_2)
node _anonOut_d_ready_T = or(anonIn.d.ready, drop)
connect anonOut.d.ready, _anonOut_d_ready_T
node _anonIn_d_valid_T = eq(drop, UInt<1>(0h0))
node _anonIn_d_valid_T_1 = and(anonOut.d.valid, _anonIn_d_valid_T)
connect anonIn.d.valid, _anonIn_d_valid_T_1
connect anonIn.d.bits.corrupt, anonOut.d.bits.corrupt
connect anonIn.d.bits.data, anonOut.d.bits.data
connect anonIn.d.bits.denied, anonOut.d.bits.denied
connect anonIn.d.bits.sink, anonOut.d.bits.sink
connect anonIn.d.bits.source, anonOut.d.bits.source
connect anonIn.d.bits.size, anonOut.d.bits.size
connect anonIn.d.bits.param, anonOut.d.bits.param
connect anonIn.d.bits.opcode, anonOut.d.bits.opcode
node _anonIn_d_bits_source_T = shr(anonOut.d.bits.source, 6)
connect anonIn.d.bits.source, _anonIn_d_bits_source_T
node _anonIn_d_bits_size_T = mux(dFirst, dFirst_size, dOrig)
connect anonIn.d.bits.size, _anonIn_d_bits_size_T
inst repeater of Repeater_TLBundleA_a32d32s7k1z3u
connect repeater.clock, clock
connect repeater.reset, reset
connect repeater.io.enq, anonIn.a
node _find_T = xor(repeater.io.deq.bits.address, UInt<1>(0h0))
node _find_T_1 = cvt(_find_T)
node _find_T_2 = and(_find_T_1, asSInt(UInt<1>(0h0)))
node _find_T_3 = asSInt(_find_T_2)
node _find_T_4 = eq(_find_T_3, asSInt(UInt<1>(0h0)))
wire find : UInt<1>[1]
connect find[0], _find_T_4
node _limit_T = eq(UInt<1>(0h0), repeater.io.deq.bits.opcode)
node _limit_T_1 = mux(_limit_T, UInt<2>(0h2), UInt<2>(0h2))
node _limit_T_2 = eq(UInt<1>(0h1), repeater.io.deq.bits.opcode)
node _limit_T_3 = mux(_limit_T_2, UInt<2>(0h2), _limit_T_1)
node _limit_T_4 = eq(UInt<2>(0h2), repeater.io.deq.bits.opcode)
node _limit_T_5 = mux(_limit_T_4, UInt<2>(0h2), _limit_T_3)
node _limit_T_6 = eq(UInt<2>(0h3), repeater.io.deq.bits.opcode)
node _limit_T_7 = mux(_limit_T_6, UInt<2>(0h2), _limit_T_5)
node _limit_T_8 = eq(UInt<3>(0h4), repeater.io.deq.bits.opcode)
node _limit_T_9 = mux(_limit_T_8, UInt<2>(0h2), _limit_T_7)
node _limit_T_10 = eq(UInt<3>(0h5), repeater.io.deq.bits.opcode)
node limit = mux(_limit_T_10, UInt<2>(0h2), _limit_T_9)
node _aFrag_T = gt(repeater.io.deq.bits.size, limit)
node aFrag = mux(_aFrag_T, limit, repeater.io.deq.bits.size)
node _aOrigOH1_T = dshl(UInt<6>(0h3f), repeater.io.deq.bits.size)
node _aOrigOH1_T_1 = bits(_aOrigOH1_T, 5, 0)
node aOrigOH1 = not(_aOrigOH1_T_1)
node _aFragOH1_T = dshl(UInt<2>(0h3), aFrag)
node _aFragOH1_T_1 = bits(_aFragOH1_T, 1, 0)
node aFragOH1 = not(_aFragOH1_T_1)
node _aHasData_opdata_T = bits(repeater.io.deq.bits.opcode, 2, 2)
node aHasData = eq(_aHasData_opdata_T, UInt<1>(0h0))
node aMask = mux(aHasData, UInt<1>(0h0), aFragOH1)
regreset gennum : UInt<4>, clock, reset, UInt<4>(0h0)
node aFirst = eq(gennum, UInt<1>(0h0))
node _old_gennum1_T = shr(aOrigOH1, 2)
node _old_gennum1_T_1 = sub(gennum, UInt<1>(0h1))
node _old_gennum1_T_2 = tail(_old_gennum1_T_1, 1)
node old_gennum1 = mux(aFirst, _old_gennum1_T, _old_gennum1_T_2)
node _new_gennum_T = not(old_gennum1)
node _new_gennum_T_1 = shr(aMask, 2)
node _new_gennum_T_2 = or(_new_gennum_T, _new_gennum_T_1)
node new_gennum = not(_new_gennum_T_2)
node _aFragnum_T = shr(old_gennum1, 0)
node _aFragnum_T_1 = not(_aFragnum_T)
node _aFragnum_T_2 = shr(aFragOH1, 2)
node _aFragnum_T_3 = or(_aFragnum_T_1, _aFragnum_T_2)
node aFragnum = not(_aFragnum_T_3)
node aLast = eq(aFragnum, UInt<1>(0h0))
reg aToggle_r : UInt<1>, clock
when aFirst :
connect aToggle_r, dToggle
node _aToggle_T = mux(aFirst, dToggle, aToggle_r)
node aToggle = eq(_aToggle_T, UInt<1>(0h0))
node aFull = eq(repeater.io.deq.bits.opcode, UInt<1>(0h0))
node _T_8 = and(anonOut.a.ready, anonOut.a.valid)
when _T_8 :
connect gennum, new_gennum
node _repeater_io_repeat_T = eq(aHasData, UInt<1>(0h0))
node _repeater_io_repeat_T_1 = neq(aFragnum, UInt<1>(0h0))
node _repeater_io_repeat_T_2 = and(_repeater_io_repeat_T, _repeater_io_repeat_T_1)
connect repeater.io.repeat, _repeater_io_repeat_T_2
connect anonOut.a.bits, repeater.io.deq.bits
connect anonOut.a.valid, repeater.io.deq.valid
connect repeater.io.deq.ready, anonOut.a.ready
node _anonOut_a_bits_address_T = shl(old_gennum1, 2)
node _anonOut_a_bits_address_T_1 = not(aOrigOH1)
node _anonOut_a_bits_address_T_2 = or(_anonOut_a_bits_address_T, _anonOut_a_bits_address_T_1)
node _anonOut_a_bits_address_T_3 = or(_anonOut_a_bits_address_T_2, aFragOH1)
node _anonOut_a_bits_address_T_4 = or(_anonOut_a_bits_address_T_3, UInt<2>(0h3))
node _anonOut_a_bits_address_T_5 = not(_anonOut_a_bits_address_T_4)
node _anonOut_a_bits_address_T_6 = or(repeater.io.deq.bits.address, _anonOut_a_bits_address_T_5)
connect anonOut.a.bits.address, _anonOut_a_bits_address_T_6
node anonOut_a_bits_source_lo = cat(aToggle, aFragnum)
node anonOut_a_bits_source_hi = cat(repeater.io.deq.bits.source, aFull)
node _anonOut_a_bits_source_T = cat(anonOut_a_bits_source_hi, anonOut_a_bits_source_lo)
connect anonOut.a.bits.source, _anonOut_a_bits_source_T
connect anonOut.a.bits.size, aFrag
node _T_9 = eq(repeater.io.full, UInt<1>(0h0))
node _T_10 = eq(aHasData, UInt<1>(0h0))
node _T_11 = or(_T_9, _T_10)
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:321 assert (!repeater.io.full || !aHasData)\n") : printf_1
assert(clock, _T_11, UInt<1>(0h1), "") : assert_1
connect anonOut.a.bits.data, anonIn.a.bits.data
node _T_15 = eq(repeater.io.full, UInt<1>(0h0))
node _T_16 = eq(repeater.io.deq.bits.mask, UInt<4>(0hf))
node _T_17 = or(_T_15, _T_16)
node _T_18 = asUInt(reset)
node _T_19 = eq(_T_18, UInt<1>(0h0))
when _T_19 :
node _T_20 = eq(_T_17, UInt<1>(0h0))
when _T_20 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:324 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n") : printf_2
assert(clock, _T_17, UInt<1>(0h1), "") : assert_2
node _anonOut_a_bits_mask_T = mux(repeater.io.full, UInt<4>(0hf), anonIn.a.bits.mask)
connect anonOut.a.bits.mask, _anonOut_a_bits_mask_T
wire anonOut_a_bits_user_out : { }
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<32>(0h0)
connect _WIRE.bits.mask, UInt<4>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<7>(0h0)
connect _WIRE.bits.size, UInt<3>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
connect _WIRE_1.valid, UInt<1>(0h0)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<32>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<7>(0h0)
connect _WIRE_2.bits.size, UInt<3>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.ready, UInt<1>(0h1)
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<13>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<32>(0h0)
connect _WIRE_6.bits.mask, UInt<4>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<13>(0h0)
connect _WIRE_6.bits.size, UInt<2>(0h0)
connect _WIRE_6.bits.param, UInt<2>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<13>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
connect _WIRE_7.ready, UInt<1>(0h1)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<32>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<13>(0h0)
connect _WIRE_8.bits.size, UInt<2>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
connect _WIRE_9.valid, UInt<1>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_10.bits.sink, UInt<1>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
connect _WIRE_11.valid, UInt<1>(0h0) | module TLFragmenter_1( // @[Fragmenter.scala:92:9]
input clock, // @[Fragmenter.scala:92:9]
input reset, // @[Fragmenter.scala:92:9]
output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [12:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [12:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_out_d_bits_data // @[LazyModuleImp.scala:107:25]
);
wire _repeater_io_full; // @[Fragmenter.scala:274:30]
wire [2:0] _repeater_io_deq_bits_opcode; // @[Fragmenter.scala:274:30]
wire [2:0] _repeater_io_deq_bits_size; // @[Fragmenter.scala:274:30]
wire [6:0] _repeater_io_deq_bits_source; // @[Fragmenter.scala:274:30]
wire [31:0] _repeater_io_deq_bits_address; // @[Fragmenter.scala:274:30]
wire [3:0] _repeater_io_deq_bits_mask; // @[Fragmenter.scala:274:30]
wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[Fragmenter.scala:92:9]
wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[Fragmenter.scala:92:9]
wire [2:0] auto_anon_in_a_bits_param_0 = auto_anon_in_a_bits_param; // @[Fragmenter.scala:92:9]
wire [2:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[Fragmenter.scala:92:9]
wire [6:0] auto_anon_in_a_bits_source_0 = auto_anon_in_a_bits_source; // @[Fragmenter.scala:92:9]
wire [31:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[Fragmenter.scala:92:9]
wire [3:0] auto_anon_in_a_bits_mask_0 = auto_anon_in_a_bits_mask; // @[Fragmenter.scala:92:9]
wire [31:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[Fragmenter.scala:92:9]
wire auto_anon_in_a_bits_corrupt_0 = auto_anon_in_a_bits_corrupt; // @[Fragmenter.scala:92:9]
wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[Fragmenter.scala:92:9]
wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[Fragmenter.scala:92:9]
wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[Fragmenter.scala:92:9]
wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[Fragmenter.scala:92:9]
wire [1:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[Fragmenter.scala:92:9]
wire [12:0] auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source; // @[Fragmenter.scala:92:9]
wire [31:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[Fragmenter.scala:92:9]
wire [1:0] auto_anon_in_d_bits_param = 2'h0; // @[Fragmenter.scala:92:9]
wire [1:0] auto_anon_out_d_bits_param = 2'h0; // @[Fragmenter.scala:92:9]
wire [1:0] anonIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] anonOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17]
wire auto_anon_in_d_bits_sink = 1'h0; // @[Fragmenter.scala:92:9]
wire auto_anon_in_d_bits_denied = 1'h0; // @[Fragmenter.scala:92:9]
wire auto_anon_in_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:92:9]
wire auto_anon_out_d_bits_sink = 1'h0; // @[Fragmenter.scala:92:9]
wire auto_anon_out_d_bits_denied = 1'h0; // @[Fragmenter.scala:92:9]
wire auto_anon_out_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:92:9]
wire anonIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire anonOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17]
wire anonOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17]
wire anonOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire acknum_size = 1'h0; // @[Fragmenter.scala:213:36]
wire _dFirst_acknum_T = 1'h0; // @[Fragmenter.scala:215:50]
wire _new_gennum_T_1 = 1'h0; // @[Fragmenter.scala:306:50]
wire _aFragnum_T_2 = 1'h0; // @[Fragmenter.scala:307:84]
wire [1:0] _limit_T_1 = 2'h2; // @[Fragmenter.scala:288:49]
wire [1:0] _limit_T_3 = 2'h2; // @[Fragmenter.scala:288:49]
wire [1:0] _limit_T_5 = 2'h2; // @[Fragmenter.scala:288:49]
wire [1:0] _limit_T_7 = 2'h2; // @[Fragmenter.scala:288:49]
wire [1:0] _limit_T_9 = 2'h2; // @[Fragmenter.scala:288:49]
wire [1:0] limit = 2'h2; // @[Fragmenter.scala:288:49]
wire _find_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire find_0 = 1'h1; // @[Parameters.scala:616:12]
wire [32:0] _find_T_2 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _find_T_3 = 33'h0; // @[Parameters.scala:137:46]
wire anonIn_a_ready; // @[MixedNode.scala:551:17]
wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[Fragmenter.scala:92:9]
wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[Fragmenter.scala:92:9]
wire [2:0] anonIn_a_bits_param = auto_anon_in_a_bits_param_0; // @[Fragmenter.scala:92:9]
wire [2:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[Fragmenter.scala:92:9]
wire [6:0] anonIn_a_bits_source = auto_anon_in_a_bits_source_0; // @[Fragmenter.scala:92:9]
wire [31:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[Fragmenter.scala:92:9]
wire [3:0] anonIn_a_bits_mask = auto_anon_in_a_bits_mask_0; // @[Fragmenter.scala:92:9]
wire [31:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[Fragmenter.scala:92:9]
wire anonIn_a_bits_corrupt = auto_anon_in_a_bits_corrupt_0; // @[Fragmenter.scala:92:9]
wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[Fragmenter.scala:92:9]
wire anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [6:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [31:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17]
wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[Fragmenter.scala:92:9]
wire anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [1:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [12:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [3:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [31:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire anonOut_d_ready; // @[MixedNode.scala:542:17]
wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[Fragmenter.scala:92:9]
wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[Fragmenter.scala:92:9]
wire [1:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[Fragmenter.scala:92:9]
wire [12:0] anonOut_d_bits_source = auto_anon_out_d_bits_source_0; // @[Fragmenter.scala:92:9]
wire [31:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[Fragmenter.scala:92:9]
wire auto_anon_in_a_ready_0; // @[Fragmenter.scala:92:9]
wire [2:0] auto_anon_in_d_bits_opcode_0; // @[Fragmenter.scala:92:9]
wire [2:0] auto_anon_in_d_bits_size_0; // @[Fragmenter.scala:92:9]
wire [6:0] auto_anon_in_d_bits_source_0; // @[Fragmenter.scala:92:9]
wire [31:0] auto_anon_in_d_bits_data_0; // @[Fragmenter.scala:92:9]
wire auto_anon_in_d_valid_0; // @[Fragmenter.scala:92:9]
wire [2:0] auto_anon_out_a_bits_opcode_0; // @[Fragmenter.scala:92:9]
wire [2:0] auto_anon_out_a_bits_param_0; // @[Fragmenter.scala:92:9]
wire [1:0] auto_anon_out_a_bits_size_0; // @[Fragmenter.scala:92:9]
wire [12:0] auto_anon_out_a_bits_source_0; // @[Fragmenter.scala:92:9]
wire [31:0] auto_anon_out_a_bits_address_0; // @[Fragmenter.scala:92:9]
wire [3:0] auto_anon_out_a_bits_mask_0; // @[Fragmenter.scala:92:9]
wire [31:0] auto_anon_out_a_bits_data_0; // @[Fragmenter.scala:92:9]
wire auto_anon_out_a_bits_corrupt_0; // @[Fragmenter.scala:92:9]
wire auto_anon_out_a_valid_0; // @[Fragmenter.scala:92:9]
wire auto_anon_out_d_ready_0; // @[Fragmenter.scala:92:9]
assign auto_anon_in_a_ready_0 = anonIn_a_ready; // @[Fragmenter.scala:92:9]
assign anonOut_a_bits_data = anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire _anonIn_d_valid_T_1; // @[Fragmenter.scala:236:36]
assign auto_anon_in_d_valid_0 = anonIn_d_valid; // @[Fragmenter.scala:92:9]
assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[Fragmenter.scala:92:9]
wire [2:0] _anonIn_d_bits_size_T; // @[Fragmenter.scala:239:32]
assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size; // @[Fragmenter.scala:92:9]
wire [6:0] _anonIn_d_bits_source_T; // @[Fragmenter.scala:238:47]
assign auto_anon_in_d_bits_source_0 = anonIn_d_bits_source; // @[Fragmenter.scala:92:9]
assign auto_anon_in_d_bits_data_0 = anonIn_d_bits_data; // @[Fragmenter.scala:92:9]
assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[Fragmenter.scala:92:9]
assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[Fragmenter.scala:92:9]
assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param; // @[Fragmenter.scala:92:9]
assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[Fragmenter.scala:92:9]
wire [12:0] _anonOut_a_bits_source_T; // @[Fragmenter.scala:317:33]
assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[Fragmenter.scala:92:9]
wire [31:0] _anonOut_a_bits_address_T_6; // @[Fragmenter.scala:316:49]
assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[Fragmenter.scala:92:9]
wire [3:0] _anonOut_a_bits_mask_T; // @[Fragmenter.scala:325:31]
assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[Fragmenter.scala:92:9]
assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[Fragmenter.scala:92:9]
assign auto_anon_out_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[Fragmenter.scala:92:9]
wire _anonOut_d_ready_T; // @[Fragmenter.scala:235:35]
assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[Fragmenter.scala:92:9]
assign anonIn_d_bits_opcode = anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] dsizeOH_shiftAmount = anonOut_d_bits_size; // @[OneHot.scala:64:49]
assign anonIn_d_bits_data = anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
reg [3:0] acknum; // @[Fragmenter.scala:201:29]
reg [2:0] dOrig; // @[Fragmenter.scala:202:24]
reg dToggle; // @[Fragmenter.scala:203:30]
wire [3:0] dFragnum = anonOut_d_bits_source[3:0]; // @[Fragmenter.scala:204:41]
wire [3:0] acknum_fragment = dFragnum; // @[Fragmenter.scala:204:41, :212:40]
wire dFirst = acknum == 4'h0; // @[Fragmenter.scala:201:29, :205:29]
wire dLast = dFragnum == 4'h0; // @[Fragmenter.scala:204:41, :206:30]
wire [3:0] _dsizeOH_T = 4'h1 << dsizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] dsizeOH = _dsizeOH_T[2:0]; // @[OneHot.scala:65:{12,27}]
wire [4:0] _dsizeOH1_T = 5'h3 << anonOut_d_bits_size; // @[package.scala:243:71]
wire [1:0] _dsizeOH1_T_1 = _dsizeOH1_T[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] dsizeOH1 = ~_dsizeOH1_T_1; // @[package.scala:243:{46,76}]
wire dHasData = anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36]
wire [3:0] dFirst_acknum = acknum_fragment; // @[Fragmenter.scala:212:40, :215:45]
wire _ack_decrement_T = dsizeOH[2]; // @[OneHot.scala:65:27]
wire ack_decrement = dHasData | _ack_decrement_T; // @[Fragmenter.scala:216:{32,56}]
wire [5:0] _dFirst_size_T = {dFragnum, 2'h0}; // @[Fragmenter.scala:204:41, :218:47]
wire [5:0] _dFirst_size_T_1 = {_dFirst_size_T[5:2], _dFirst_size_T[1:0] | dsizeOH1}; // @[package.scala:243:46]
wire [6:0] _dFirst_size_T_2 = {_dFirst_size_T_1, 1'h0}; // @[package.scala:241:35]
wire [6:0] _dFirst_size_T_3 = {_dFirst_size_T_2[6:1], 1'h1}; // @[package.scala:241:{35,40}]
wire [6:0] _dFirst_size_T_4 = {1'h0, _dFirst_size_T_1}; // @[package.scala:241:53]
wire [6:0] _dFirst_size_T_5 = ~_dFirst_size_T_4; // @[package.scala:241:{49,53}]
wire [6:0] _dFirst_size_T_6 = _dFirst_size_T_3 & _dFirst_size_T_5; // @[package.scala:241:{40,47,49}]
wire [2:0] dFirst_size_hi = _dFirst_size_T_6[6:4]; // @[OneHot.scala:30:18]
wire [3:0] dFirst_size_lo = _dFirst_size_T_6[3:0]; // @[OneHot.scala:31:18]
wire _dFirst_size_T_7 = |dFirst_size_hi; // @[OneHot.scala:30:18, :32:14]
wire [3:0] _dFirst_size_T_8 = {1'h0, dFirst_size_hi} | dFirst_size_lo; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] dFirst_size_hi_1 = _dFirst_size_T_8[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] dFirst_size_lo_1 = _dFirst_size_T_8[1:0]; // @[OneHot.scala:31:18, :32:28]
wire _dFirst_size_T_9 = |dFirst_size_hi_1; // @[OneHot.scala:30:18, :32:14]
wire [1:0] _dFirst_size_T_10 = dFirst_size_hi_1 | dFirst_size_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28]
wire _dFirst_size_T_11 = _dFirst_size_T_10[1]; // @[OneHot.scala:32:28]
wire [1:0] _dFirst_size_T_12 = {_dFirst_size_T_9, _dFirst_size_T_11}; // @[OneHot.scala:32:{10,14}]
wire [2:0] dFirst_size = {_dFirst_size_T_7, _dFirst_size_T_12}; // @[OneHot.scala:32:{10,14}]
wire [4:0] _acknum_T = {1'h0, acknum} - {4'h0, ack_decrement}; // @[Fragmenter.scala:201:29, :216:32, :221:55]
wire [3:0] _acknum_T_1 = _acknum_T[3:0]; // @[Fragmenter.scala:221:55]
wire [3:0] _acknum_T_2 = dFirst ? dFirst_acknum : _acknum_T_1; // @[Fragmenter.scala:205:29, :215:45, :221:{24,55}]
wire _dToggle_T = anonOut_d_bits_source[4]; // @[Fragmenter.scala:224:41]
wire doEarlyAck = anonOut_d_bits_source[5]; // @[Fragmenter.scala:231:54]
wire _drop_T = ~dHasData; // @[Fragmenter.scala:234:20]
wire _drop_T_1 = doEarlyAck ? dFirst : dLast; // @[Fragmenter.scala:205:29, :206:30, :231:54, :234:37]
wire _drop_T_2 = ~_drop_T_1; // @[Fragmenter.scala:234:{33,37}]
wire drop = _drop_T & _drop_T_2; // @[Fragmenter.scala:234:{20,30,33}]
assign _anonOut_d_ready_T = anonIn_d_ready | drop; // @[Fragmenter.scala:234:30, :235:35]
assign anonOut_d_ready = _anonOut_d_ready_T; // @[Fragmenter.scala:235:35]
wire _anonIn_d_valid_T = ~drop; // @[Fragmenter.scala:234:30, :236:39]
assign _anonIn_d_valid_T_1 = anonOut_d_valid & _anonIn_d_valid_T; // @[Fragmenter.scala:236:{36,39}]
assign anonIn_d_valid = _anonIn_d_valid_T_1; // @[Fragmenter.scala:236:36]
assign _anonIn_d_bits_source_T = anonOut_d_bits_source[12:6]; // @[Fragmenter.scala:238:47]
assign anonIn_d_bits_source = _anonIn_d_bits_source_T; // @[Fragmenter.scala:238:47]
assign _anonIn_d_bits_size_T = dFirst ? dFirst_size : dOrig; // @[OneHot.scala:32:10]
assign anonIn_d_bits_size = _anonIn_d_bits_size_T; // @[Fragmenter.scala:239:32]
wire [31:0] _find_T; // @[Parameters.scala:137:31]
wire [32:0] _find_T_1 = {1'h0, _find_T}; // @[Parameters.scala:137:{31,41}]
wire _GEN = _repeater_io_deq_bits_opcode == 3'h0; // @[Fragmenter.scala:274:30, :288:49]
wire _limit_T; // @[Fragmenter.scala:288:49]
assign _limit_T = _GEN; // @[Fragmenter.scala:288:49]
wire aFull; // @[Fragmenter.scala:310:78]
assign aFull = _GEN; // @[Fragmenter.scala:288:49, :310:78]
wire _limit_T_2 = _repeater_io_deq_bits_opcode == 3'h1; // @[Fragmenter.scala:274:30, :288:49]
wire _limit_T_4 = _repeater_io_deq_bits_opcode == 3'h2; // @[Fragmenter.scala:274:30, :288:49]
wire _limit_T_6 = _repeater_io_deq_bits_opcode == 3'h3; // @[Fragmenter.scala:274:30, :288:49]
wire _limit_T_8 = _repeater_io_deq_bits_opcode == 3'h4; // @[Fragmenter.scala:274:30, :288:49]
wire _limit_T_10 = _repeater_io_deq_bits_opcode == 3'h5; // @[Fragmenter.scala:274:30, :288:49]
wire _aFrag_T = _repeater_io_deq_bits_size > 3'h2; // @[Fragmenter.scala:274:30, :297:31]
wire [2:0] aFrag = _aFrag_T ? 3'h2 : _repeater_io_deq_bits_size; // @[Fragmenter.scala:274:30, :297:{24,31}]
wire [12:0] _aOrigOH1_T = 13'h3F << _repeater_io_deq_bits_size; // @[package.scala:243:71]
wire [5:0] _aOrigOH1_T_1 = _aOrigOH1_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] aOrigOH1 = ~_aOrigOH1_T_1; // @[package.scala:243:{46,76}]
wire [8:0] _aFragOH1_T = 9'h3 << aFrag; // @[package.scala:243:71]
wire [1:0] _aFragOH1_T_1 = _aFragOH1_T[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] aFragOH1 = ~_aFragOH1_T_1; // @[package.scala:243:{46,76}]
wire _aHasData_opdata_T = _repeater_io_deq_bits_opcode[2]; // @[Fragmenter.scala:274:30]
wire aHasData = ~_aHasData_opdata_T; // @[Edges.scala:92:{28,37}]
wire [1:0] aMask = aHasData ? 2'h0 : aFragOH1; // @[package.scala:243:46]
reg [3:0] gennum; // @[Fragmenter.scala:303:29]
wire aFirst = gennum == 4'h0; // @[Fragmenter.scala:303:29, :304:29]
wire [3:0] _old_gennum1_T = aOrigOH1[5:2]; // @[package.scala:243:46]
wire [4:0] _old_gennum1_T_1 = {1'h0, gennum} - 5'h1; // @[Fragmenter.scala:303:29, :305:79]
wire [3:0] _old_gennum1_T_2 = _old_gennum1_T_1[3:0]; // @[Fragmenter.scala:305:79]
wire [3:0] old_gennum1 = aFirst ? _old_gennum1_T : _old_gennum1_T_2; // @[Fragmenter.scala:304:29, :305:{30,48,79}]
wire [3:0] _aFragnum_T = old_gennum1; // @[Fragmenter.scala:305:30, :307:40]
wire [3:0] _new_gennum_T = ~old_gennum1; // @[Fragmenter.scala:305:30, :306:28]
wire [3:0] _new_gennum_T_2 = _new_gennum_T; // @[Fragmenter.scala:306:{28,41}]
wire [3:0] new_gennum = ~_new_gennum_T_2; // @[Fragmenter.scala:306:{26,41}]
wire [3:0] _aFragnum_T_1 = ~_aFragnum_T; // @[Fragmenter.scala:307:{26,40}]
wire [3:0] _aFragnum_T_3 = _aFragnum_T_1; // @[Fragmenter.scala:307:{26,72}]
wire [3:0] aFragnum = ~_aFragnum_T_3; // @[Fragmenter.scala:307:{24,72}]
wire aLast = ~(|aFragnum); // @[Fragmenter.scala:307:24, :308:30]
reg aToggle_r; // @[Fragmenter.scala:309:54]
wire _aToggle_T = aFirst ? dToggle : aToggle_r; // @[Fragmenter.scala:203:30, :304:29, :309:{27,54}]
wire aToggle = ~_aToggle_T; // @[Fragmenter.scala:309:{23,27}]
wire _repeater_io_repeat_T = ~aHasData; // @[Fragmenter.scala:314:31]
wire _repeater_io_repeat_T_1 = |aFragnum; // @[Fragmenter.scala:307:24, :308:30, :314:53]
wire _repeater_io_repeat_T_2 = _repeater_io_repeat_T & _repeater_io_repeat_T_1; // @[Fragmenter.scala:314:{31,41,53}]
wire [5:0] _anonOut_a_bits_address_T = {old_gennum1, 2'h0}; // @[Fragmenter.scala:305:30, :316:65]
wire [5:0] _anonOut_a_bits_address_T_1 = ~aOrigOH1; // @[package.scala:243:46]
wire [5:0] _anonOut_a_bits_address_T_2 = _anonOut_a_bits_address_T | _anonOut_a_bits_address_T_1; // @[Fragmenter.scala:316:{65,88,90}]
wire [5:0] _anonOut_a_bits_address_T_3 = {_anonOut_a_bits_address_T_2[5:2], _anonOut_a_bits_address_T_2[1:0] | aFragOH1}; // @[package.scala:243:46]
wire [5:0] _anonOut_a_bits_address_T_4 = {_anonOut_a_bits_address_T_3[5:2], 2'h3}; // @[Fragmenter.scala:316:{100,111}]
wire [5:0] _anonOut_a_bits_address_T_5 = ~_anonOut_a_bits_address_T_4; // @[Fragmenter.scala:316:{51,111}]
assign _anonOut_a_bits_address_T_6 = {_repeater_io_deq_bits_address[31:6], _repeater_io_deq_bits_address[5:0] | _anonOut_a_bits_address_T_5}; // @[Fragmenter.scala:274:30, :316:{49,51}]
assign anonOut_a_bits_address = _anonOut_a_bits_address_T_6; // @[Fragmenter.scala:316:49]
wire [4:0] anonOut_a_bits_source_lo = {aToggle, aFragnum}; // @[Fragmenter.scala:307:24, :309:23, :317:33]
wire [7:0] anonOut_a_bits_source_hi = {_repeater_io_deq_bits_source, aFull}; // @[Fragmenter.scala:274:30, :310:78, :317:33]
assign _anonOut_a_bits_source_T = {anonOut_a_bits_source_hi, anonOut_a_bits_source_lo}; // @[Fragmenter.scala:317:33]
assign anonOut_a_bits_source = _anonOut_a_bits_source_T; // @[Fragmenter.scala:317:33]
assign anonOut_a_bits_size = aFrag[1:0]; // @[Fragmenter.scala:297:24, :318:25] |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_54 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 3, 0)
node _source_ok_T = shr(io.in.a.bits.source, 4)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<4>(0h9))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T_5
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits = bits(_uncommonBits_T, 3, 0)
node _T_4 = shr(io.in.a.bits.source, 4)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<4>(0h9))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_16, UInt<1>(0h1), "") : assert_1
node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_20 :
node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_23 = and(_T_21, _T_22)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 3, 0)
node _T_24 = shr(io.in.a.bits.source, 4)
node _T_25 = eq(_T_24, UInt<1>(0h0))
node _T_26 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_27 = and(_T_25, _T_26)
node _T_28 = leq(uncommonBits_1, UInt<4>(0h9))
node _T_29 = and(_T_27, _T_28)
node _T_30 = and(_T_23, _T_29)
node _T_31 = or(UInt<1>(0h0), _T_30)
node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_33 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_34 = cvt(_T_33)
node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000)))
node _T_36 = asSInt(_T_35)
node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0)))
node _T_38 = and(_T_32, _T_37)
node _T_39 = or(UInt<1>(0h0), _T_38)
node _T_40 = and(_T_31, _T_39)
node _T_41 = asUInt(reset)
node _T_42 = eq(_T_41, UInt<1>(0h0))
when _T_42 :
node _T_43 = eq(_T_40, UInt<1>(0h0))
when _T_43 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_40, UInt<1>(0h1), "") : assert_2
node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_46 = and(_T_44, _T_45)
node _T_47 = or(UInt<1>(0h0), _T_46)
node _T_48 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_49 = cvt(_T_48)
node _T_50 = and(_T_49, asSInt(UInt<17>(0h10000)))
node _T_51 = asSInt(_T_50)
node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0)))
node _T_53 = and(_T_47, _T_52)
node _T_54 = or(UInt<1>(0h0), _T_53)
node _T_55 = and(UInt<1>(0h0), _T_54)
node _T_56 = asUInt(reset)
node _T_57 = eq(_T_56, UInt<1>(0h0))
when _T_57 :
node _T_58 = eq(_T_55, UInt<1>(0h0))
when _T_58 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_55, UInt<1>(0h1), "") : assert_3
node _T_59 = asUInt(reset)
node _T_60 = eq(_T_59, UInt<1>(0h0))
when _T_60 :
node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_61 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_63 = asUInt(reset)
node _T_64 = eq(_T_63, UInt<1>(0h0))
when _T_64 :
node _T_65 = eq(_T_62, UInt<1>(0h0))
when _T_65 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_62, UInt<1>(0h1), "") : assert_5
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(is_aligned, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_70 = asUInt(reset)
node _T_71 = eq(_T_70, UInt<1>(0h0))
when _T_71 :
node _T_72 = eq(_T_69, UInt<1>(0h0))
when _T_72 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_69, UInt<1>(0h1), "") : assert_7
node _T_73 = not(io.in.a.bits.mask)
node _T_74 = eq(_T_73, UInt<1>(0h0))
node _T_75 = asUInt(reset)
node _T_76 = eq(_T_75, UInt<1>(0h0))
when _T_76 :
node _T_77 = eq(_T_74, UInt<1>(0h0))
when _T_77 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_74, UInt<1>(0h1), "") : assert_8
node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_79 = asUInt(reset)
node _T_80 = eq(_T_79, UInt<1>(0h0))
when _T_80 :
node _T_81 = eq(_T_78, UInt<1>(0h0))
when _T_81 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_78, UInt<1>(0h1), "") : assert_9
node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_82 :
node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_85 = and(_T_83, _T_84)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 3, 0)
node _T_86 = shr(io.in.a.bits.source, 4)
node _T_87 = eq(_T_86, UInt<1>(0h0))
node _T_88 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_89 = and(_T_87, _T_88)
node _T_90 = leq(uncommonBits_2, UInt<4>(0h9))
node _T_91 = and(_T_89, _T_90)
node _T_92 = and(_T_85, _T_91)
node _T_93 = or(UInt<1>(0h0), _T_92)
node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_95 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_96 = cvt(_T_95)
node _T_97 = and(_T_96, asSInt(UInt<17>(0h10000)))
node _T_98 = asSInt(_T_97)
node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = and(_T_94, _T_99)
node _T_101 = or(UInt<1>(0h0), _T_100)
node _T_102 = and(_T_93, _T_101)
node _T_103 = asUInt(reset)
node _T_104 = eq(_T_103, UInt<1>(0h0))
when _T_104 :
node _T_105 = eq(_T_102, UInt<1>(0h0))
when _T_105 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_102, UInt<1>(0h1), "") : assert_10
node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_108 = and(_T_106, _T_107)
node _T_109 = or(UInt<1>(0h0), _T_108)
node _T_110 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_111 = cvt(_T_110)
node _T_112 = and(_T_111, asSInt(UInt<17>(0h10000)))
node _T_113 = asSInt(_T_112)
node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0)))
node _T_115 = and(_T_109, _T_114)
node _T_116 = or(UInt<1>(0h0), _T_115)
node _T_117 = and(UInt<1>(0h0), _T_116)
node _T_118 = asUInt(reset)
node _T_119 = eq(_T_118, UInt<1>(0h0))
when _T_119 :
node _T_120 = eq(_T_117, UInt<1>(0h0))
when _T_120 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_117, UInt<1>(0h1), "") : assert_11
node _T_121 = asUInt(reset)
node _T_122 = eq(_T_121, UInt<1>(0h0))
when _T_122 :
node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_125 = asUInt(reset)
node _T_126 = eq(_T_125, UInt<1>(0h0))
when _T_126 :
node _T_127 = eq(_T_124, UInt<1>(0h0))
when _T_127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_124, UInt<1>(0h1), "") : assert_13
node _T_128 = asUInt(reset)
node _T_129 = eq(_T_128, UInt<1>(0h0))
when _T_129 :
node _T_130 = eq(is_aligned, UInt<1>(0h0))
when _T_130 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_132 = asUInt(reset)
node _T_133 = eq(_T_132, UInt<1>(0h0))
when _T_133 :
node _T_134 = eq(_T_131, UInt<1>(0h0))
when _T_134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_131, UInt<1>(0h1), "") : assert_15
node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_136 = asUInt(reset)
node _T_137 = eq(_T_136, UInt<1>(0h0))
when _T_137 :
node _T_138 = eq(_T_135, UInt<1>(0h0))
when _T_138 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_135, UInt<1>(0h1), "") : assert_16
node _T_139 = not(io.in.a.bits.mask)
node _T_140 = eq(_T_139, UInt<1>(0h0))
node _T_141 = asUInt(reset)
node _T_142 = eq(_T_141, UInt<1>(0h0))
when _T_142 :
node _T_143 = eq(_T_140, UInt<1>(0h0))
when _T_143 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_140, UInt<1>(0h1), "") : assert_17
node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_145 = asUInt(reset)
node _T_146 = eq(_T_145, UInt<1>(0h0))
when _T_146 :
node _T_147 = eq(_T_144, UInt<1>(0h0))
when _T_147 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_144, UInt<1>(0h1), "") : assert_18
node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_148 :
node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_151 = and(_T_149, _T_150)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 3, 0)
node _T_152 = shr(io.in.a.bits.source, 4)
node _T_153 = eq(_T_152, UInt<1>(0h0))
node _T_154 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_155 = and(_T_153, _T_154)
node _T_156 = leq(uncommonBits_3, UInt<4>(0h9))
node _T_157 = and(_T_155, _T_156)
node _T_158 = and(_T_151, _T_157)
node _T_159 = or(UInt<1>(0h0), _T_158)
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(_T_159, UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_159, UInt<1>(0h1), "") : assert_19
node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_164 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_165 = and(_T_163, _T_164)
node _T_166 = or(UInt<1>(0h0), _T_165)
node _T_167 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_168 = cvt(_T_167)
node _T_169 = and(_T_168, asSInt(UInt<17>(0h10000)))
node _T_170 = asSInt(_T_169)
node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0)))
node _T_172 = and(_T_166, _T_171)
node _T_173 = or(UInt<1>(0h0), _T_172)
node _T_174 = asUInt(reset)
node _T_175 = eq(_T_174, UInt<1>(0h0))
when _T_175 :
node _T_176 = eq(_T_173, UInt<1>(0h0))
when _T_176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_173, UInt<1>(0h1), "") : assert_20
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_180 = asUInt(reset)
node _T_181 = eq(_T_180, UInt<1>(0h0))
when _T_181 :
node _T_182 = eq(is_aligned, UInt<1>(0h0))
when _T_182 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_183, UInt<1>(0h1), "") : assert_23
node _T_187 = eq(io.in.a.bits.mask, mask)
node _T_188 = asUInt(reset)
node _T_189 = eq(_T_188, UInt<1>(0h0))
when _T_189 :
node _T_190 = eq(_T_187, UInt<1>(0h0))
when _T_190 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_187, UInt<1>(0h1), "") : assert_24
node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_192 = asUInt(reset)
node _T_193 = eq(_T_192, UInt<1>(0h0))
when _T_193 :
node _T_194 = eq(_T_191, UInt<1>(0h0))
when _T_194 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_191, UInt<1>(0h1), "") : assert_25
node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_195 :
node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_198 = and(_T_196, _T_197)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 3, 0)
node _T_199 = shr(io.in.a.bits.source, 4)
node _T_200 = eq(_T_199, UInt<1>(0h0))
node _T_201 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_202 = and(_T_200, _T_201)
node _T_203 = leq(uncommonBits_4, UInt<4>(0h9))
node _T_204 = and(_T_202, _T_203)
node _T_205 = and(_T_198, _T_204)
node _T_206 = or(UInt<1>(0h0), _T_205)
node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_208 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_209 = and(_T_207, _T_208)
node _T_210 = or(UInt<1>(0h0), _T_209)
node _T_211 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_212 = cvt(_T_211)
node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000)))
node _T_214 = asSInt(_T_213)
node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0)))
node _T_216 = and(_T_210, _T_215)
node _T_217 = or(UInt<1>(0h0), _T_216)
node _T_218 = and(_T_206, _T_217)
node _T_219 = asUInt(reset)
node _T_220 = eq(_T_219, UInt<1>(0h0))
when _T_220 :
node _T_221 = eq(_T_218, UInt<1>(0h0))
when _T_221 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_218, UInt<1>(0h1), "") : assert_26
node _T_222 = asUInt(reset)
node _T_223 = eq(_T_222, UInt<1>(0h0))
when _T_223 :
node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_225 = asUInt(reset)
node _T_226 = eq(_T_225, UInt<1>(0h0))
when _T_226 :
node _T_227 = eq(is_aligned, UInt<1>(0h0))
when _T_227 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_229 = asUInt(reset)
node _T_230 = eq(_T_229, UInt<1>(0h0))
when _T_230 :
node _T_231 = eq(_T_228, UInt<1>(0h0))
when _T_231 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_228, UInt<1>(0h1), "") : assert_29
node _T_232 = eq(io.in.a.bits.mask, mask)
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_232, UInt<1>(0h1), "") : assert_30
node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_236 :
node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_239 = and(_T_237, _T_238)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 3, 0)
node _T_240 = shr(io.in.a.bits.source, 4)
node _T_241 = eq(_T_240, UInt<1>(0h0))
node _T_242 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_243 = and(_T_241, _T_242)
node _T_244 = leq(uncommonBits_5, UInt<4>(0h9))
node _T_245 = and(_T_243, _T_244)
node _T_246 = and(_T_239, _T_245)
node _T_247 = or(UInt<1>(0h0), _T_246)
node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_249 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_250 = and(_T_248, _T_249)
node _T_251 = or(UInt<1>(0h0), _T_250)
node _T_252 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_253 = cvt(_T_252)
node _T_254 = and(_T_253, asSInt(UInt<17>(0h10000)))
node _T_255 = asSInt(_T_254)
node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0)))
node _T_257 = and(_T_251, _T_256)
node _T_258 = or(UInt<1>(0h0), _T_257)
node _T_259 = and(_T_247, _T_258)
node _T_260 = asUInt(reset)
node _T_261 = eq(_T_260, UInt<1>(0h0))
when _T_261 :
node _T_262 = eq(_T_259, UInt<1>(0h0))
when _T_262 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_259, UInt<1>(0h1), "") : assert_31
node _T_263 = asUInt(reset)
node _T_264 = eq(_T_263, UInt<1>(0h0))
when _T_264 :
node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_265 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_266 = asUInt(reset)
node _T_267 = eq(_T_266, UInt<1>(0h0))
when _T_267 :
node _T_268 = eq(is_aligned, UInt<1>(0h0))
when _T_268 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_270 = asUInt(reset)
node _T_271 = eq(_T_270, UInt<1>(0h0))
when _T_271 :
node _T_272 = eq(_T_269, UInt<1>(0h0))
when _T_272 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_269, UInt<1>(0h1), "") : assert_34
node _T_273 = not(mask)
node _T_274 = and(io.in.a.bits.mask, _T_273)
node _T_275 = eq(_T_274, UInt<1>(0h0))
node _T_276 = asUInt(reset)
node _T_277 = eq(_T_276, UInt<1>(0h0))
when _T_277 :
node _T_278 = eq(_T_275, UInt<1>(0h0))
when _T_278 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_275, UInt<1>(0h1), "") : assert_35
node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_279 :
node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_282 = and(_T_280, _T_281)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 3, 0)
node _T_283 = shr(io.in.a.bits.source, 4)
node _T_284 = eq(_T_283, UInt<1>(0h0))
node _T_285 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_286 = and(_T_284, _T_285)
node _T_287 = leq(uncommonBits_6, UInt<4>(0h9))
node _T_288 = and(_T_286, _T_287)
node _T_289 = and(_T_282, _T_288)
node _T_290 = or(UInt<1>(0h0), _T_289)
node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_292 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_293 = cvt(_T_292)
node _T_294 = and(_T_293, asSInt(UInt<17>(0h10000)))
node _T_295 = asSInt(_T_294)
node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0)))
node _T_297 = and(_T_291, _T_296)
node _T_298 = or(UInt<1>(0h0), _T_297)
node _T_299 = and(_T_290, _T_298)
node _T_300 = asUInt(reset)
node _T_301 = eq(_T_300, UInt<1>(0h0))
when _T_301 :
node _T_302 = eq(_T_299, UInt<1>(0h0))
when _T_302 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_299, UInt<1>(0h1), "") : assert_36
node _T_303 = asUInt(reset)
node _T_304 = eq(_T_303, UInt<1>(0h0))
when _T_304 :
node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_305 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_306 = asUInt(reset)
node _T_307 = eq(_T_306, UInt<1>(0h0))
when _T_307 :
node _T_308 = eq(is_aligned, UInt<1>(0h0))
when _T_308 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_310 = asUInt(reset)
node _T_311 = eq(_T_310, UInt<1>(0h0))
when _T_311 :
node _T_312 = eq(_T_309, UInt<1>(0h0))
when _T_312 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_309, UInt<1>(0h1), "") : assert_39
node _T_313 = eq(io.in.a.bits.mask, mask)
node _T_314 = asUInt(reset)
node _T_315 = eq(_T_314, UInt<1>(0h0))
when _T_315 :
node _T_316 = eq(_T_313, UInt<1>(0h0))
when _T_316 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_313, UInt<1>(0h1), "") : assert_40
node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_317 :
node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_320 = and(_T_318, _T_319)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 3, 0)
node _T_321 = shr(io.in.a.bits.source, 4)
node _T_322 = eq(_T_321, UInt<1>(0h0))
node _T_323 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_324 = and(_T_322, _T_323)
node _T_325 = leq(uncommonBits_7, UInt<4>(0h9))
node _T_326 = and(_T_324, _T_325)
node _T_327 = and(_T_320, _T_326)
node _T_328 = or(UInt<1>(0h0), _T_327)
node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_330 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_331 = cvt(_T_330)
node _T_332 = and(_T_331, asSInt(UInt<17>(0h10000)))
node _T_333 = asSInt(_T_332)
node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0)))
node _T_335 = and(_T_329, _T_334)
node _T_336 = or(UInt<1>(0h0), _T_335)
node _T_337 = and(_T_328, _T_336)
node _T_338 = asUInt(reset)
node _T_339 = eq(_T_338, UInt<1>(0h0))
when _T_339 :
node _T_340 = eq(_T_337, UInt<1>(0h0))
when _T_340 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_337, UInt<1>(0h1), "") : assert_41
node _T_341 = asUInt(reset)
node _T_342 = eq(_T_341, UInt<1>(0h0))
when _T_342 :
node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_343 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_344 = asUInt(reset)
node _T_345 = eq(_T_344, UInt<1>(0h0))
when _T_345 :
node _T_346 = eq(is_aligned, UInt<1>(0h0))
when _T_346 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_348 = asUInt(reset)
node _T_349 = eq(_T_348, UInt<1>(0h0))
when _T_349 :
node _T_350 = eq(_T_347, UInt<1>(0h0))
when _T_350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_347, UInt<1>(0h1), "") : assert_44
node _T_351 = eq(io.in.a.bits.mask, mask)
node _T_352 = asUInt(reset)
node _T_353 = eq(_T_352, UInt<1>(0h0))
when _T_353 :
node _T_354 = eq(_T_351, UInt<1>(0h0))
when _T_354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_351, UInt<1>(0h1), "") : assert_45
node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_355 :
node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_358 = and(_T_356, _T_357)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 3, 0)
node _T_359 = shr(io.in.a.bits.source, 4)
node _T_360 = eq(_T_359, UInt<1>(0h0))
node _T_361 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_362 = and(_T_360, _T_361)
node _T_363 = leq(uncommonBits_8, UInt<4>(0h9))
node _T_364 = and(_T_362, _T_363)
node _T_365 = and(_T_358, _T_364)
node _T_366 = or(UInt<1>(0h0), _T_365)
node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_368 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_369 = cvt(_T_368)
node _T_370 = and(_T_369, asSInt(UInt<17>(0h10000)))
node _T_371 = asSInt(_T_370)
node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0)))
node _T_373 = and(_T_367, _T_372)
node _T_374 = or(UInt<1>(0h0), _T_373)
node _T_375 = and(_T_366, _T_374)
node _T_376 = asUInt(reset)
node _T_377 = eq(_T_376, UInt<1>(0h0))
when _T_377 :
node _T_378 = eq(_T_375, UInt<1>(0h0))
when _T_378 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_375, UInt<1>(0h1), "") : assert_46
node _T_379 = asUInt(reset)
node _T_380 = eq(_T_379, UInt<1>(0h0))
when _T_380 :
node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_381 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_382 = asUInt(reset)
node _T_383 = eq(_T_382, UInt<1>(0h0))
when _T_383 :
node _T_384 = eq(is_aligned, UInt<1>(0h0))
when _T_384 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_386 = asUInt(reset)
node _T_387 = eq(_T_386, UInt<1>(0h0))
when _T_387 :
node _T_388 = eq(_T_385, UInt<1>(0h0))
when _T_388 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_385, UInt<1>(0h1), "") : assert_49
node _T_389 = eq(io.in.a.bits.mask, mask)
node _T_390 = asUInt(reset)
node _T_391 = eq(_T_390, UInt<1>(0h0))
when _T_391 :
node _T_392 = eq(_T_389, UInt<1>(0h0))
when _T_392 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_389, UInt<1>(0h1), "") : assert_50
node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_394 = asUInt(reset)
node _T_395 = eq(_T_394, UInt<1>(0h0))
when _T_395 :
node _T_396 = eq(_T_393, UInt<1>(0h0))
when _T_396 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_393, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(_T_397, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_397, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 3, 0)
node _source_ok_T_6 = shr(io.in.d.bits.source, 4)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<4>(0h9))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_11
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_401 :
node _T_402 = asUInt(reset)
node _T_403 = eq(_T_402, UInt<1>(0h0))
when _T_403 :
node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_404 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_406 = asUInt(reset)
node _T_407 = eq(_T_406, UInt<1>(0h0))
when _T_407 :
node _T_408 = eq(_T_405, UInt<1>(0h0))
when _T_408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_405, UInt<1>(0h1), "") : assert_54
node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_410 = asUInt(reset)
node _T_411 = eq(_T_410, UInt<1>(0h0))
when _T_411 :
node _T_412 = eq(_T_409, UInt<1>(0h0))
when _T_412 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_409, UInt<1>(0h1), "") : assert_55
node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_414 = asUInt(reset)
node _T_415 = eq(_T_414, UInt<1>(0h0))
when _T_415 :
node _T_416 = eq(_T_413, UInt<1>(0h0))
when _T_416 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_413, UInt<1>(0h1), "") : assert_56
node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_418 = asUInt(reset)
node _T_419 = eq(_T_418, UInt<1>(0h0))
when _T_419 :
node _T_420 = eq(_T_417, UInt<1>(0h0))
when _T_420 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_417, UInt<1>(0h1), "") : assert_57
node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_421 :
node _T_422 = asUInt(reset)
node _T_423 = eq(_T_422, UInt<1>(0h0))
when _T_423 :
node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_424 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_425 = asUInt(reset)
node _T_426 = eq(_T_425, UInt<1>(0h0))
when _T_426 :
node _T_427 = eq(sink_ok, UInt<1>(0h0))
when _T_427 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_429 = asUInt(reset)
node _T_430 = eq(_T_429, UInt<1>(0h0))
when _T_430 :
node _T_431 = eq(_T_428, UInt<1>(0h0))
when _T_431 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_428, UInt<1>(0h1), "") : assert_60
node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_433 = asUInt(reset)
node _T_434 = eq(_T_433, UInt<1>(0h0))
when _T_434 :
node _T_435 = eq(_T_432, UInt<1>(0h0))
when _T_435 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_432, UInt<1>(0h1), "") : assert_61
node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_437 = asUInt(reset)
node _T_438 = eq(_T_437, UInt<1>(0h0))
when _T_438 :
node _T_439 = eq(_T_436, UInt<1>(0h0))
when _T_439 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_436, UInt<1>(0h1), "") : assert_62
node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_441 = asUInt(reset)
node _T_442 = eq(_T_441, UInt<1>(0h0))
when _T_442 :
node _T_443 = eq(_T_440, UInt<1>(0h0))
when _T_443 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_440, UInt<1>(0h1), "") : assert_63
node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_445 = or(UInt<1>(0h0), _T_444)
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_445, UInt<1>(0h1), "") : assert_64
node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_449 :
node _T_450 = asUInt(reset)
node _T_451 = eq(_T_450, UInt<1>(0h0))
when _T_451 :
node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_452 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(sink_ok, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_457 = asUInt(reset)
node _T_458 = eq(_T_457, UInt<1>(0h0))
when _T_458 :
node _T_459 = eq(_T_456, UInt<1>(0h0))
when _T_459 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_456, UInt<1>(0h1), "") : assert_67
node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_461 = asUInt(reset)
node _T_462 = eq(_T_461, UInt<1>(0h0))
when _T_462 :
node _T_463 = eq(_T_460, UInt<1>(0h0))
when _T_463 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_460, UInt<1>(0h1), "") : assert_68
node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_465 = asUInt(reset)
node _T_466 = eq(_T_465, UInt<1>(0h0))
when _T_466 :
node _T_467 = eq(_T_464, UInt<1>(0h0))
when _T_467 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_464, UInt<1>(0h1), "") : assert_69
node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_469 = or(_T_468, io.in.d.bits.corrupt)
node _T_470 = asUInt(reset)
node _T_471 = eq(_T_470, UInt<1>(0h0))
when _T_471 :
node _T_472 = eq(_T_469, UInt<1>(0h0))
when _T_472 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_469, UInt<1>(0h1), "") : assert_70
node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_474 = or(UInt<1>(0h0), _T_473)
node _T_475 = asUInt(reset)
node _T_476 = eq(_T_475, UInt<1>(0h0))
when _T_476 :
node _T_477 = eq(_T_474, UInt<1>(0h0))
when _T_477 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_474, UInt<1>(0h1), "") : assert_71
node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_478 :
node _T_479 = asUInt(reset)
node _T_480 = eq(_T_479, UInt<1>(0h0))
when _T_480 :
node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_481 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_483 = asUInt(reset)
node _T_484 = eq(_T_483, UInt<1>(0h0))
when _T_484 :
node _T_485 = eq(_T_482, UInt<1>(0h0))
when _T_485 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_482, UInt<1>(0h1), "") : assert_73
node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_487 = asUInt(reset)
node _T_488 = eq(_T_487, UInt<1>(0h0))
when _T_488 :
node _T_489 = eq(_T_486, UInt<1>(0h0))
when _T_489 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_486, UInt<1>(0h1), "") : assert_74
node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_491 = or(UInt<1>(0h0), _T_490)
node _T_492 = asUInt(reset)
node _T_493 = eq(_T_492, UInt<1>(0h0))
when _T_493 :
node _T_494 = eq(_T_491, UInt<1>(0h0))
when _T_494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_491, UInt<1>(0h1), "") : assert_75
node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_495 :
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_500 = asUInt(reset)
node _T_501 = eq(_T_500, UInt<1>(0h0))
when _T_501 :
node _T_502 = eq(_T_499, UInt<1>(0h0))
when _T_502 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_499, UInt<1>(0h1), "") : assert_77
node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_504 = or(_T_503, io.in.d.bits.corrupt)
node _T_505 = asUInt(reset)
node _T_506 = eq(_T_505, UInt<1>(0h0))
when _T_506 :
node _T_507 = eq(_T_504, UInt<1>(0h0))
when _T_507 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_504, UInt<1>(0h1), "") : assert_78
node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_509 = or(UInt<1>(0h0), _T_508)
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_T_509, UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_509, UInt<1>(0h1), "") : assert_79
node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_513 :
node _T_514 = asUInt(reset)
node _T_515 = eq(_T_514, UInt<1>(0h0))
when _T_515 :
node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_516 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_518 = asUInt(reset)
node _T_519 = eq(_T_518, UInt<1>(0h0))
when _T_519 :
node _T_520 = eq(_T_517, UInt<1>(0h0))
when _T_520 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_517, UInt<1>(0h1), "") : assert_81
node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_522 = asUInt(reset)
node _T_523 = eq(_T_522, UInt<1>(0h0))
when _T_523 :
node _T_524 = eq(_T_521, UInt<1>(0h0))
when _T_524 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_521, UInt<1>(0h1), "") : assert_82
node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_526 = or(UInt<1>(0h0), _T_525)
node _T_527 = asUInt(reset)
node _T_528 = eq(_T_527, UInt<1>(0h0))
when _T_528 :
node _T_529 = eq(_T_526, UInt<1>(0h0))
when _T_529 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_526, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<28>(0h0)
connect _WIRE.bits.source, UInt<4>(0h0)
connect _WIRE.bits.size, UInt<3>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_531 = asUInt(reset)
node _T_532 = eq(_T_531, UInt<1>(0h0))
when _T_532 :
node _T_533 = eq(_T_530, UInt<1>(0h0))
when _T_533 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_530, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<28>(0h0)
connect _WIRE_2.bits.source, UInt<4>(0h0)
connect _WIRE_2.bits.size, UInt<3>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_535 = asUInt(reset)
node _T_536 = eq(_T_535, UInt<1>(0h0))
when _T_536 :
node _T_537 = eq(_T_534, UInt<1>(0h0))
when _T_537 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_534, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_539 = asUInt(reset)
node _T_540 = eq(_T_539, UInt<1>(0h0))
when _T_540 :
node _T_541 = eq(_T_538, UInt<1>(0h0))
when _T_541 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_538, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_542 = eq(a_first, UInt<1>(0h0))
node _T_543 = and(io.in.a.valid, _T_542)
when _T_543 :
node _T_544 = eq(io.in.a.bits.opcode, opcode)
node _T_545 = asUInt(reset)
node _T_546 = eq(_T_545, UInt<1>(0h0))
when _T_546 :
node _T_547 = eq(_T_544, UInt<1>(0h0))
when _T_547 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_544, UInt<1>(0h1), "") : assert_87
node _T_548 = eq(io.in.a.bits.param, param)
node _T_549 = asUInt(reset)
node _T_550 = eq(_T_549, UInt<1>(0h0))
when _T_550 :
node _T_551 = eq(_T_548, UInt<1>(0h0))
when _T_551 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_548, UInt<1>(0h1), "") : assert_88
node _T_552 = eq(io.in.a.bits.size, size)
node _T_553 = asUInt(reset)
node _T_554 = eq(_T_553, UInt<1>(0h0))
when _T_554 :
node _T_555 = eq(_T_552, UInt<1>(0h0))
when _T_555 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_552, UInt<1>(0h1), "") : assert_89
node _T_556 = eq(io.in.a.bits.source, source)
node _T_557 = asUInt(reset)
node _T_558 = eq(_T_557, UInt<1>(0h0))
when _T_558 :
node _T_559 = eq(_T_556, UInt<1>(0h0))
when _T_559 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_556, UInt<1>(0h1), "") : assert_90
node _T_560 = eq(io.in.a.bits.address, address)
node _T_561 = asUInt(reset)
node _T_562 = eq(_T_561, UInt<1>(0h0))
when _T_562 :
node _T_563 = eq(_T_560, UInt<1>(0h0))
when _T_563 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_560, UInt<1>(0h1), "") : assert_91
node _T_564 = and(io.in.a.ready, io.in.a.valid)
node _T_565 = and(_T_564, a_first)
when _T_565 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_566 = eq(d_first, UInt<1>(0h0))
node _T_567 = and(io.in.d.valid, _T_566)
when _T_567 :
node _T_568 = eq(io.in.d.bits.opcode, opcode_1)
node _T_569 = asUInt(reset)
node _T_570 = eq(_T_569, UInt<1>(0h0))
when _T_570 :
node _T_571 = eq(_T_568, UInt<1>(0h0))
when _T_571 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_568, UInt<1>(0h1), "") : assert_92
node _T_572 = eq(io.in.d.bits.param, param_1)
node _T_573 = asUInt(reset)
node _T_574 = eq(_T_573, UInt<1>(0h0))
when _T_574 :
node _T_575 = eq(_T_572, UInt<1>(0h0))
when _T_575 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_572, UInt<1>(0h1), "") : assert_93
node _T_576 = eq(io.in.d.bits.size, size_1)
node _T_577 = asUInt(reset)
node _T_578 = eq(_T_577, UInt<1>(0h0))
when _T_578 :
node _T_579 = eq(_T_576, UInt<1>(0h0))
when _T_579 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_576, UInt<1>(0h1), "") : assert_94
node _T_580 = eq(io.in.d.bits.source, source_1)
node _T_581 = asUInt(reset)
node _T_582 = eq(_T_581, UInt<1>(0h0))
when _T_582 :
node _T_583 = eq(_T_580, UInt<1>(0h0))
when _T_583 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_580, UInt<1>(0h1), "") : assert_95
node _T_584 = eq(io.in.d.bits.sink, sink)
node _T_585 = asUInt(reset)
node _T_586 = eq(_T_585, UInt<1>(0h0))
when _T_586 :
node _T_587 = eq(_T_584, UInt<1>(0h0))
when _T_587 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_584, UInt<1>(0h1), "") : assert_96
node _T_588 = eq(io.in.d.bits.denied, denied)
node _T_589 = asUInt(reset)
node _T_590 = eq(_T_589, UInt<1>(0h0))
when _T_590 :
node _T_591 = eq(_T_588, UInt<1>(0h0))
when _T_591 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_588, UInt<1>(0h1), "") : assert_97
node _T_592 = and(io.in.d.ready, io.in.d.valid)
node _T_593 = and(_T_592, d_first)
when _T_593 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<10>, clock, reset, UInt<10>(0h0)
regreset inflight_opcodes : UInt<40>, clock, reset, UInt<40>(0h0)
regreset inflight_sizes : UInt<40>, clock, reset, UInt<40>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<10>
connect a_set, UInt<10>(0h0)
wire a_set_wo_ready : UInt<10>
connect a_set_wo_ready, UInt<10>(0h0)
wire a_opcodes_set : UInt<40>
connect a_opcodes_set, UInt<40>(0h0)
wire a_sizes_set : UInt<40>
connect a_sizes_set, UInt<40>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_594 = and(io.in.a.valid, a_first_1)
node _T_595 = and(_T_594, UInt<1>(0h1))
when _T_595 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_596 = and(io.in.a.ready, io.in.a.valid)
node _T_597 = and(_T_596, a_first_1)
node _T_598 = and(_T_597, UInt<1>(0h1))
when _T_598 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_599 = dshr(inflight, io.in.a.bits.source)
node _T_600 = bits(_T_599, 0, 0)
node _T_601 = eq(_T_600, UInt<1>(0h0))
node _T_602 = asUInt(reset)
node _T_603 = eq(_T_602, UInt<1>(0h0))
when _T_603 :
node _T_604 = eq(_T_601, UInt<1>(0h0))
when _T_604 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_601, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<10>
connect d_clr, UInt<10>(0h0)
wire d_clr_wo_ready : UInt<10>
connect d_clr_wo_ready, UInt<10>(0h0)
wire d_opcodes_clr : UInt<40>
connect d_opcodes_clr, UInt<40>(0h0)
wire d_sizes_clr : UInt<40>
connect d_sizes_clr, UInt<40>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_605 = and(io.in.d.valid, d_first_1)
node _T_606 = and(_T_605, UInt<1>(0h1))
node _T_607 = eq(d_release_ack, UInt<1>(0h0))
node _T_608 = and(_T_606, _T_607)
when _T_608 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_609 = and(io.in.d.ready, io.in.d.valid)
node _T_610 = and(_T_609, d_first_1)
node _T_611 = and(_T_610, UInt<1>(0h1))
node _T_612 = eq(d_release_ack, UInt<1>(0h0))
node _T_613 = and(_T_611, _T_612)
when _T_613 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_614 = and(io.in.d.valid, d_first_1)
node _T_615 = and(_T_614, UInt<1>(0h1))
node _T_616 = eq(d_release_ack, UInt<1>(0h0))
node _T_617 = and(_T_615, _T_616)
when _T_617 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_618 = dshr(inflight, io.in.d.bits.source)
node _T_619 = bits(_T_618, 0, 0)
node _T_620 = or(_T_619, same_cycle_resp)
node _T_621 = asUInt(reset)
node _T_622 = eq(_T_621, UInt<1>(0h0))
when _T_622 :
node _T_623 = eq(_T_620, UInt<1>(0h0))
when _T_623 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_620, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_626 = or(_T_624, _T_625)
node _T_627 = asUInt(reset)
node _T_628 = eq(_T_627, UInt<1>(0h0))
when _T_628 :
node _T_629 = eq(_T_626, UInt<1>(0h0))
when _T_629 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_626, UInt<1>(0h1), "") : assert_100
node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_631 = asUInt(reset)
node _T_632 = eq(_T_631, UInt<1>(0h0))
when _T_632 :
node _T_633 = eq(_T_630, UInt<1>(0h0))
when _T_633 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_630, UInt<1>(0h1), "") : assert_101
else :
node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_636 = or(_T_634, _T_635)
node _T_637 = asUInt(reset)
node _T_638 = eq(_T_637, UInt<1>(0h0))
when _T_638 :
node _T_639 = eq(_T_636, UInt<1>(0h0))
when _T_639 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_636, UInt<1>(0h1), "") : assert_102
node _T_640 = eq(io.in.d.bits.size, a_size_lookup)
node _T_641 = asUInt(reset)
node _T_642 = eq(_T_641, UInt<1>(0h0))
when _T_642 :
node _T_643 = eq(_T_640, UInt<1>(0h0))
when _T_643 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_640, UInt<1>(0h1), "") : assert_103
node _T_644 = and(io.in.d.valid, d_first_1)
node _T_645 = and(_T_644, a_first_1)
node _T_646 = and(_T_645, io.in.a.valid)
node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_648 = and(_T_646, _T_647)
node _T_649 = eq(d_release_ack, UInt<1>(0h0))
node _T_650 = and(_T_648, _T_649)
when _T_650 :
node _T_651 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_652 = or(_T_651, io.in.a.ready)
node _T_653 = asUInt(reset)
node _T_654 = eq(_T_653, UInt<1>(0h0))
when _T_654 :
node _T_655 = eq(_T_652, UInt<1>(0h0))
when _T_655 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_652, UInt<1>(0h1), "") : assert_104
node _T_656 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_657 = orr(a_set_wo_ready)
node _T_658 = eq(_T_657, UInt<1>(0h0))
node _T_659 = or(_T_656, _T_658)
node _T_660 = asUInt(reset)
node _T_661 = eq(_T_660, UInt<1>(0h0))
when _T_661 :
node _T_662 = eq(_T_659, UInt<1>(0h0))
when _T_662 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_659, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_109
node _T_663 = orr(inflight)
node _T_664 = eq(_T_663, UInt<1>(0h0))
node _T_665 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_666 = or(_T_664, _T_665)
node _T_667 = lt(watchdog, plusarg_reader.out)
node _T_668 = or(_T_666, _T_667)
node _T_669 = asUInt(reset)
node _T_670 = eq(_T_669, UInt<1>(0h0))
when _T_670 :
node _T_671 = eq(_T_668, UInt<1>(0h0))
when _T_671 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_668, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_672 = and(io.in.a.ready, io.in.a.valid)
node _T_673 = and(io.in.d.ready, io.in.d.valid)
node _T_674 = or(_T_672, _T_673)
when _T_674 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<10>, clock, reset, UInt<10>(0h0)
regreset inflight_opcodes_1 : UInt<40>, clock, reset, UInt<40>(0h0)
regreset inflight_sizes_1 : UInt<40>, clock, reset, UInt<40>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<28>(0h0)
connect _c_first_WIRE.bits.source, UInt<4>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<28>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<10>
connect c_set, UInt<10>(0h0)
wire c_set_wo_ready : UInt<10>
connect c_set_wo_ready, UInt<10>(0h0)
wire c_opcodes_set : UInt<40>
connect c_opcodes_set, UInt<40>(0h0)
wire c_sizes_set : UInt<40>
connect c_sizes_set, UInt<40>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<28>(0h0)
connect _WIRE_6.bits.source, UInt<4>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_675 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<28>(0h0)
connect _WIRE_8.bits.source, UInt<4>(0h0)
connect _WIRE_8.bits.size, UInt<3>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_676 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_677 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_678 = and(_T_676, _T_677)
node _T_679 = and(_T_675, _T_678)
when _T_679 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<28>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<28>(0h0)
connect _WIRE_10.bits.source, UInt<4>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_680 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_681 = and(_T_680, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<28>(0h0)
connect _WIRE_12.bits.source, UInt<4>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_682 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_683 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_684 = and(_T_682, _T_683)
node _T_685 = and(_T_681, _T_684)
when _T_685 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<28>(0h0)
connect _c_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<28>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<28>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<28>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<28>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<28>(0h0)
connect _WIRE_14.bits.source, UInt<4>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_686 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_687 = bits(_T_686, 0, 0)
node _T_688 = eq(_T_687, UInt<1>(0h0))
node _T_689 = asUInt(reset)
node _T_690 = eq(_T_689, UInt<1>(0h0))
when _T_690 :
node _T_691 = eq(_T_688, UInt<1>(0h0))
when _T_691 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_688, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<28>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<28>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<10>
connect d_clr_1, UInt<10>(0h0)
wire d_clr_wo_ready_1 : UInt<10>
connect d_clr_wo_ready_1, UInt<10>(0h0)
wire d_opcodes_clr_1 : UInt<40>
connect d_opcodes_clr_1, UInt<40>(0h0)
wire d_sizes_clr_1 : UInt<40>
connect d_sizes_clr_1, UInt<40>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_692 = and(io.in.d.valid, d_first_2)
node _T_693 = and(_T_692, UInt<1>(0h1))
node _T_694 = and(_T_693, d_release_ack_1)
when _T_694 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_695 = and(io.in.d.ready, io.in.d.valid)
node _T_696 = and(_T_695, d_first_2)
node _T_697 = and(_T_696, UInt<1>(0h1))
node _T_698 = and(_T_697, d_release_ack_1)
when _T_698 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_699 = and(io.in.d.valid, d_first_2)
node _T_700 = and(_T_699, UInt<1>(0h1))
node _T_701 = and(_T_700, d_release_ack_1)
when _T_701 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<28>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<28>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<28>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_702 = dshr(inflight_1, io.in.d.bits.source)
node _T_703 = bits(_T_702, 0, 0)
node _T_704 = or(_T_703, same_cycle_resp_1)
node _T_705 = asUInt(reset)
node _T_706 = eq(_T_705, UInt<1>(0h0))
when _T_706 :
node _T_707 = eq(_T_704, UInt<1>(0h0))
when _T_707 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_704, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<28>(0h0)
connect _WIRE_16.bits.source, UInt<4>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_708 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_709 = asUInt(reset)
node _T_710 = eq(_T_709, UInt<1>(0h0))
when _T_710 :
node _T_711 = eq(_T_708, UInt<1>(0h0))
when _T_711 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_708, UInt<1>(0h1), "") : assert_109
else :
node _T_712 = eq(io.in.d.bits.size, c_size_lookup)
node _T_713 = asUInt(reset)
node _T_714 = eq(_T_713, UInt<1>(0h0))
when _T_714 :
node _T_715 = eq(_T_712, UInt<1>(0h0))
when _T_715 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_712, UInt<1>(0h1), "") : assert_110
node _T_716 = and(io.in.d.valid, d_first_2)
node _T_717 = and(_T_716, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<28>(0h0)
connect _WIRE_18.bits.source, UInt<4>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_718 = and(_T_717, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<28>(0h0)
connect _WIRE_20.bits.source, UInt<4>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_719 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_720 = and(_T_718, _T_719)
node _T_721 = and(_T_720, d_release_ack_1)
node _T_722 = eq(c_probe_ack, UInt<1>(0h0))
node _T_723 = and(_T_721, _T_722)
when _T_723 :
node _T_724 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<28>(0h0)
connect _WIRE_22.bits.source, UInt<4>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_725 = or(_T_724, _WIRE_23.ready)
node _T_726 = asUInt(reset)
node _T_727 = eq(_T_726, UInt<1>(0h0))
when _T_727 :
node _T_728 = eq(_T_725, UInt<1>(0h0))
when _T_728 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_725, UInt<1>(0h1), "") : assert_111
node _T_729 = orr(c_set_wo_ready)
when _T_729 :
node _T_730 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_731 = asUInt(reset)
node _T_732 = eq(_T_731, UInt<1>(0h0))
when _T_732 :
node _T_733 = eq(_T_730, UInt<1>(0h0))
when _T_733 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_730, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_110
node _T_734 = orr(inflight_1)
node _T_735 = eq(_T_734, UInt<1>(0h0))
node _T_736 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_737 = or(_T_735, _T_736)
node _T_738 = lt(watchdog_1, plusarg_reader_1.out)
node _T_739 = or(_T_737, _T_738)
node _T_740 = asUInt(reset)
node _T_741 = eq(_T_740, UInt<1>(0h0))
when _T_741 :
node _T_742 = eq(_T_739, UInt<1>(0h0))
when _T_742 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_739, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<28>(0h0)
connect _WIRE_24.bits.source, UInt<4>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_743 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_744 = and(io.in.d.ready, io.in.d.valid)
node _T_745 = or(_T_743, _T_744)
when _T_745 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_54( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [27:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10]
wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_first_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_first_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_first_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_first_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_set_wo_ready_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_set_wo_ready_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_opcodes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_opcodes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_sizes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_sizes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_opcodes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_opcodes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_sizes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_sizes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_probe_ack_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_probe_ack_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_probe_ack_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_probe_ack_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _same_cycle_resp_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _same_cycle_resp_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _same_cycle_resp_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _same_cycle_resp_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _same_cycle_resp_WIRE_4_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _same_cycle_resp_WIRE_5_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [130:0] _c_opcodes_set_T_1 = 131'h0; // @[Monitor.scala:767:54]
wire [130:0] _c_sizes_set_T_1 = 131'h0; // @[Monitor.scala:768:52]
wire [6:0] _c_opcodes_set_T = 7'h0; // @[Monitor.scala:767:79]
wire [6:0] _c_sizes_set_T = 7'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [15:0] _c_set_wo_ready_T = 16'h1; // @[OneHot.scala:58:35]
wire [15:0] _c_set_T = 16'h1; // @[OneHot.scala:58:35]
wire [39:0] c_opcodes_set = 40'h0; // @[Monitor.scala:740:34]
wire [39:0] c_sizes_set = 40'h0; // @[Monitor.scala:741:34]
wire [9:0] c_set = 10'h0; // @[Monitor.scala:738:34]
wire [9:0] c_set_wo_ready = 10'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_4 = source_ok_uncommonBits < 4'hA; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [27:0] _is_aligned_T = {22'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 28'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [3:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}]
wire [3:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_10 = source_ok_uncommonBits_1 < 4'hA; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31]
wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_672; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_672; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [3:0] source; // @[Monitor.scala:390:22]
reg [27:0] address; // @[Monitor.scala:391:22]
wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_745; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_745; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_745; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [3:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [9:0] inflight; // @[Monitor.scala:614:27]
reg [39:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [39:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [9:0] a_set; // @[Monitor.scala:626:34]
wire [9:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [39:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [39:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [6:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [6:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [6:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [6:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [6:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [6:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [6:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [6:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [6:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [39:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [39:0] _a_opcode_lookup_T_6 = {36'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [39:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [39:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [39:0] _a_size_lookup_T_6 = {36'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [39:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[39:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [15:0] _GEN_2 = 16'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [15:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [15:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire _T_598 = _T_672 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_598 ? _a_set_T[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [6:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [6:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [6:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [130:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [9:0] d_clr; // @[Monitor.scala:664:34]
wire [9:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [39:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [39:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [15:0] _GEN_5 = 16'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire _T_613 = _T_745 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_613 ? _d_clr_T[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [142:0] _d_sizes_clr_T_5 = 143'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [9:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [9:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [9:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [39:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [39:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [39:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [39:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [39:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [39:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [9:0] inflight_1; // @[Monitor.scala:726:35]
wire [9:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [39:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [39:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [39:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [39:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [39:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [39:0] _c_opcode_lookup_T_6 = {36'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [39:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [39:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [39:0] _c_size_lookup_T_6 = {36'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [39:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[39:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [9:0] d_clr_1; // @[Monitor.scala:774:34]
wire [9:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [39:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [39:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_716 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire _T_698 = _T_745 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_698 ? _d_clr_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [142:0] _d_sizes_clr_T_11 = 143'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 4'h0; // @[Monitor.scala:36:7, :795:113]
wire [9:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [9:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [39:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [39:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [39:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [39:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module TLBusBypassBar :
input clock : Clock
input reset : Reset
output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}}
output io : { flip bypass : UInt<1>, pending : UInt<1>}
wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}
invalidate nodeIn.d.bits.corrupt
invalidate nodeIn.d.bits.data
invalidate nodeIn.d.bits.denied
invalidate nodeIn.d.bits.sink
invalidate nodeIn.d.bits.source
invalidate nodeIn.d.bits.size
invalidate nodeIn.d.bits.param
invalidate nodeIn.d.bits.opcode
invalidate nodeIn.d.valid
invalidate nodeIn.d.ready
invalidate nodeIn.a.bits.corrupt
invalidate nodeIn.a.bits.data
invalidate nodeIn.a.bits.mask
invalidate nodeIn.a.bits.address
invalidate nodeIn.a.bits.source
invalidate nodeIn.a.bits.size
invalidate nodeIn.a.bits.param
invalidate nodeIn.a.bits.opcode
invalidate nodeIn.a.valid
invalidate nodeIn.a.ready
inst monitor of TLMonitor_60
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, nodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, nodeIn.d.bits.source
connect monitor.io.in.d.bits.size, nodeIn.d.bits.size
connect monitor.io.in.d.bits.param, nodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode
connect monitor.io.in.d.valid, nodeIn.d.valid
connect monitor.io.in.d.ready, nodeIn.d.ready
connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, nodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, nodeIn.a.bits.address
connect monitor.io.in.a.bits.source, nodeIn.a.bits.source
connect monitor.io.in.a.bits.size, nodeIn.a.bits.size
connect monitor.io.in.a.bits.param, nodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode
connect monitor.io.in.a.valid, nodeIn.a.valid
connect monitor.io.in.a.ready, nodeIn.a.ready
wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}
invalidate nodeOut.d.bits.corrupt
invalidate nodeOut.d.bits.data
invalidate nodeOut.d.bits.denied
invalidate nodeOut.d.bits.sink
invalidate nodeOut.d.bits.source
invalidate nodeOut.d.bits.size
invalidate nodeOut.d.bits.param
invalidate nodeOut.d.bits.opcode
invalidate nodeOut.d.valid
invalidate nodeOut.d.ready
invalidate nodeOut.a.bits.corrupt
invalidate nodeOut.a.bits.data
invalidate nodeOut.a.bits.mask
invalidate nodeOut.a.bits.address
invalidate nodeOut.a.bits.source
invalidate nodeOut.a.bits.size
invalidate nodeOut.a.bits.param
invalidate nodeOut.a.bits.opcode
invalidate nodeOut.a.valid
invalidate nodeOut.a.ready
wire x1_nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}
invalidate x1_nodeOut.d.bits.corrupt
invalidate x1_nodeOut.d.bits.data
invalidate x1_nodeOut.d.bits.denied
invalidate x1_nodeOut.d.bits.sink
invalidate x1_nodeOut.d.bits.source
invalidate x1_nodeOut.d.bits.size
invalidate x1_nodeOut.d.bits.param
invalidate x1_nodeOut.d.bits.opcode
invalidate x1_nodeOut.d.valid
invalidate x1_nodeOut.d.ready
invalidate x1_nodeOut.a.bits.corrupt
invalidate x1_nodeOut.a.bits.data
invalidate x1_nodeOut.a.bits.mask
invalidate x1_nodeOut.a.bits.address
invalidate x1_nodeOut.a.bits.source
invalidate x1_nodeOut.a.bits.size
invalidate x1_nodeOut.a.bits.param
invalidate x1_nodeOut.a.bits.opcode
invalidate x1_nodeOut.a.valid
invalidate x1_nodeOut.a.ready
connect auto.out_0, nodeOut
connect auto.out_1, x1_nodeOut
connect nodeIn, auto.in
regreset in_reset : UInt<1>, clock, reset, UInt<1>(0h1)
connect in_reset, UInt<1>(0h0)
reg bypass_reg : UInt<1>, clock
node bypass = mux(in_reset, io.bypass, bypass_reg)
regreset flight : UInt<2>, clock, reset, UInt<2>(0h0)
node _T = and(nodeIn.a.ready, nodeIn.a.valid)
node _r_beats1_decode_T = dshl(UInt<2>(0h3), nodeIn.a.bits.size)
node _r_beats1_decode_T_1 = bits(_r_beats1_decode_T, 1, 0)
node _r_beats1_decode_T_2 = not(_r_beats1_decode_T_1)
node r_beats1_decode = shr(_r_beats1_decode_T_2, 2)
node _r_beats1_opdata_T = bits(nodeIn.a.bits.opcode, 2, 2)
node r_beats1_opdata = eq(_r_beats1_opdata_T, UInt<1>(0h0))
node r_beats1 = mux(r_beats1_opdata, r_beats1_decode, UInt<1>(0h0))
regreset r_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _r_counter1_T = sub(r_counter, UInt<1>(0h1))
node r_counter1 = tail(_r_counter1_T, 1)
node a_first = eq(r_counter, UInt<1>(0h0))
node _r_last_T = eq(r_counter, UInt<1>(0h1))
node _r_last_T_1 = eq(r_beats1, UInt<1>(0h0))
node a_last = or(_r_last_T, _r_last_T_1)
node r_3 = and(a_last, _T)
node _r_count_T = not(r_counter1)
node r_4 = and(r_beats1, _r_count_T)
when _T :
node _r_counter_T = mux(a_first, r_beats1, r_counter1)
connect r_counter, _r_counter_T
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<32>(0h0)
connect _WIRE.bits.mask, UInt<4>(0h0)
connect _WIRE.bits.address, UInt<9>(0h0)
connect _WIRE.bits.source, UInt<1>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_1 = and(_WIRE_1.ready, _WIRE_1.valid)
node _r_beats1_decode_T_3 = dshl(UInt<2>(0h3), _WIRE_1.bits.size)
node _r_beats1_decode_T_4 = bits(_r_beats1_decode_T_3, 1, 0)
node _r_beats1_decode_T_5 = not(_r_beats1_decode_T_4)
node r_beats1_decode_1 = shr(_r_beats1_decode_T_5, 2)
node _r_beats1_opdata_T_1 = bits(_WIRE_1.bits.opcode, 2, 2)
node r_beats1_opdata_1 = eq(_r_beats1_opdata_T_1, UInt<1>(0h0))
node r_beats1_1 = mux(UInt<1>(0h0), r_beats1_decode_1, UInt<1>(0h0))
regreset r_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _r_counter1_T_1 = sub(r_counter_1, UInt<1>(0h1))
node r_counter1_1 = tail(_r_counter1_T_1, 1)
node b_first = eq(r_counter_1, UInt<1>(0h0))
node _r_last_T_2 = eq(r_counter_1, UInt<1>(0h1))
node _r_last_T_3 = eq(r_beats1_1, UInt<1>(0h0))
node b_last = or(_r_last_T_2, _r_last_T_3)
node r_3_1 = and(b_last, _T_1)
node _r_count_T_1 = not(r_counter1_1)
node r_4_1 = and(r_beats1_1, _r_count_T_1)
when _T_1 :
node _r_counter_T_1 = mux(b_first, r_beats1_1, r_counter1_1)
connect r_counter_1, _r_counter_T_1
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<32>(0h0)
connect _WIRE_2.bits.address, UInt<9>(0h0)
connect _WIRE_2.bits.source, UInt<1>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_2 = and(_WIRE_3.ready, _WIRE_3.valid)
node _r_beats1_decode_T_6 = dshl(UInt<2>(0h3), _WIRE_3.bits.size)
node _r_beats1_decode_T_7 = bits(_r_beats1_decode_T_6, 1, 0)
node _r_beats1_decode_T_8 = not(_r_beats1_decode_T_7)
node r_beats1_decode_2 = shr(_r_beats1_decode_T_8, 2)
node r_beats1_opdata_2 = bits(_WIRE_3.bits.opcode, 0, 0)
node r_beats1_2 = mux(UInt<1>(0h0), r_beats1_decode_2, UInt<1>(0h0))
regreset r_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _r_counter1_T_2 = sub(r_counter_2, UInt<1>(0h1))
node r_counter1_2 = tail(_r_counter1_T_2, 1)
node c_first = eq(r_counter_2, UInt<1>(0h0))
node _r_last_T_4 = eq(r_counter_2, UInt<1>(0h1))
node _r_last_T_5 = eq(r_beats1_2, UInt<1>(0h0))
node c_last = or(_r_last_T_4, _r_last_T_5)
node r_3_2 = and(c_last, _T_2)
node _r_count_T_2 = not(r_counter1_2)
node r_4_2 = and(r_beats1_2, _r_count_T_2)
when _T_2 :
node _r_counter_T_2 = mux(c_first, r_beats1_2, r_counter1_2)
connect r_counter_2, _r_counter_T_2
node _T_3 = and(nodeIn.d.ready, nodeIn.d.valid)
node _r_beats1_decode_T_9 = dshl(UInt<2>(0h3), nodeIn.d.bits.size)
node _r_beats1_decode_T_10 = bits(_r_beats1_decode_T_9, 1, 0)
node _r_beats1_decode_T_11 = not(_r_beats1_decode_T_10)
node r_beats1_decode_3 = shr(_r_beats1_decode_T_11, 2)
node r_beats1_opdata_3 = bits(nodeIn.d.bits.opcode, 0, 0)
node r_beats1_3 = mux(r_beats1_opdata_3, r_beats1_decode_3, UInt<1>(0h0))
regreset r_counter_3 : UInt<1>, clock, reset, UInt<1>(0h0)
node _r_counter1_T_3 = sub(r_counter_3, UInt<1>(0h1))
node r_counter1_3 = tail(_r_counter1_T_3, 1)
node d_first = eq(r_counter_3, UInt<1>(0h0))
node _r_last_T_6 = eq(r_counter_3, UInt<1>(0h1))
node _r_last_T_7 = eq(r_beats1_3, UInt<1>(0h0))
node d_last = or(_r_last_T_6, _r_last_T_7)
node r_3_3 = and(d_last, _T_3)
node _r_count_T_3 = not(r_counter1_3)
node r_4_3 = and(r_beats1_3, _r_count_T_3)
when _T_3 :
node _r_counter_T_3 = mux(d_first, r_beats1_3, r_counter1_3)
connect r_counter_3, _r_counter_T_3
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_4 = and(_WIRE_5.ready, _WIRE_5.valid)
regreset r_counter_4 : UInt<1>, clock, reset, UInt<1>(0h0)
node _r_counter1_T_4 = sub(r_counter_4, UInt<1>(0h1))
node r_counter1_4 = tail(_r_counter1_T_4, 1)
node e_first = eq(r_counter_4, UInt<1>(0h0))
node _r_last_T_8 = eq(r_counter_4, UInt<1>(0h1))
node _r_last_T_9 = eq(UInt<1>(0h0), UInt<1>(0h0))
node e_last = or(_r_last_T_8, _r_last_T_9)
node r_3_4 = and(e_last, _T_4)
node _r_count_T_4 = not(r_counter1_4)
node r_4_4 = and(UInt<1>(0h0), _r_count_T_4)
when _T_4 :
node _r_counter_T_4 = mux(e_first, UInt<1>(0h0), r_counter1_4)
connect r_counter_4, _r_counter_T_4
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<32>(0h0)
connect _WIRE_6.bits.mask, UInt<4>(0h0)
connect _WIRE_6.bits.address, UInt<9>(0h0)
connect _WIRE_6.bits.source, UInt<1>(0h0)
connect _WIRE_6.bits.size, UInt<2>(0h0)
connect _WIRE_6.bits.param, UInt<2>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<32>(0h0)
connect _WIRE_8.bits.mask, UInt<4>(0h0)
connect _WIRE_8.bits.address, UInt<9>(0h0)
connect _WIRE_8.bits.source, UInt<1>(0h0)
connect _WIRE_8.bits.size, UInt<2>(0h0)
connect _WIRE_8.bits.param, UInt<2>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<32>(0h0)
connect _WIRE_10.bits.address, UInt<9>(0h0)
connect _WIRE_10.bits.source, UInt<1>(0h0)
connect _WIRE_10.bits.size, UInt<2>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_5 = bits(_WIRE_11.bits.opcode, 2, 2)
node _T_6 = bits(_WIRE_11.bits.opcode, 1, 1)
node c_request = and(_T_5, _T_6)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<32>(0h0)
connect _WIRE_12.bits.address, UInt<9>(0h0)
connect _WIRE_12.bits.source, UInt<1>(0h0)
connect _WIRE_12.bits.size, UInt<2>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_7 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_8 = eq(_T_7, UInt<1>(0h0))
node _T_9 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node c_response = or(_T_8, _T_10)
node _T_11 = bits(nodeIn.d.bits.opcode, 2, 2)
node _T_12 = bits(nodeIn.d.bits.opcode, 1, 1)
node _T_13 = eq(_T_12, UInt<1>(0h0))
node d_request = and(_T_11, _T_13)
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_14.bits.sink, UInt<1>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_16.bits.sink, UInt<1>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _a_inc_T = and(nodeIn.a.ready, nodeIn.a.valid)
node _a_inc_T_1 = and(_a_inc_T, a_first)
node a_inc = and(_a_inc_T_1, UInt<1>(0h1))
wire _b_inc_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _b_inc_WIRE.bits.corrupt, UInt<1>(0h0)
connect _b_inc_WIRE.bits.data, UInt<32>(0h0)
connect _b_inc_WIRE.bits.mask, UInt<4>(0h0)
connect _b_inc_WIRE.bits.address, UInt<9>(0h0)
connect _b_inc_WIRE.bits.source, UInt<1>(0h0)
connect _b_inc_WIRE.bits.size, UInt<2>(0h0)
connect _b_inc_WIRE.bits.param, UInt<2>(0h0)
connect _b_inc_WIRE.bits.opcode, UInt<3>(0h0)
connect _b_inc_WIRE.valid, UInt<1>(0h0)
connect _b_inc_WIRE.ready, UInt<1>(0h0)
wire _b_inc_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _b_inc_WIRE_1.bits, _b_inc_WIRE.bits
connect _b_inc_WIRE_1.valid, _b_inc_WIRE.valid
connect _b_inc_WIRE_1.ready, _b_inc_WIRE.ready
node _b_inc_T = and(_b_inc_WIRE_1.ready, _b_inc_WIRE_1.valid)
node _b_inc_T_1 = and(_b_inc_T, b_first)
node b_inc = and(_b_inc_T_1, UInt<1>(0h1))
wire _c_inc_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_inc_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_inc_WIRE.bits.data, UInt<32>(0h0)
connect _c_inc_WIRE.bits.address, UInt<9>(0h0)
connect _c_inc_WIRE.bits.source, UInt<1>(0h0)
connect _c_inc_WIRE.bits.size, UInt<2>(0h0)
connect _c_inc_WIRE.bits.param, UInt<3>(0h0)
connect _c_inc_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_inc_WIRE.valid, UInt<1>(0h0)
connect _c_inc_WIRE.ready, UInt<1>(0h0)
wire _c_inc_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_inc_WIRE_1.bits, _c_inc_WIRE.bits
connect _c_inc_WIRE_1.valid, _c_inc_WIRE.valid
connect _c_inc_WIRE_1.ready, _c_inc_WIRE.ready
node _c_inc_T = and(_c_inc_WIRE_1.ready, _c_inc_WIRE_1.valid)
node _c_inc_T_1 = and(_c_inc_T, c_first)
node c_inc = and(_c_inc_T_1, c_request)
node _d_inc_T = and(nodeIn.d.ready, nodeIn.d.valid)
node _d_inc_T_1 = and(_d_inc_T, d_first)
node d_inc = and(_d_inc_T_1, d_request)
wire _e_inc_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _e_inc_WIRE.bits.sink, UInt<1>(0h0)
connect _e_inc_WIRE.valid, UInt<1>(0h0)
connect _e_inc_WIRE.ready, UInt<1>(0h0)
wire _e_inc_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _e_inc_WIRE_1.bits, _e_inc_WIRE.bits
connect _e_inc_WIRE_1.valid, _e_inc_WIRE.valid
connect _e_inc_WIRE_1.ready, _e_inc_WIRE.ready
node _e_inc_T = and(_e_inc_WIRE_1.ready, _e_inc_WIRE_1.valid)
node _e_inc_T_1 = and(_e_inc_T, e_first)
node e_inc = and(_e_inc_T_1, UInt<1>(0h0))
node inc = cat(a_inc, d_inc)
node _a_dec_T = and(nodeIn.a.ready, nodeIn.a.valid)
node _a_dec_T_1 = and(_a_dec_T, a_last)
node a_dec = and(_a_dec_T_1, UInt<1>(0h0))
wire _b_dec_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _b_dec_WIRE.bits.corrupt, UInt<1>(0h0)
connect _b_dec_WIRE.bits.data, UInt<32>(0h0)
connect _b_dec_WIRE.bits.mask, UInt<4>(0h0)
connect _b_dec_WIRE.bits.address, UInt<9>(0h0)
connect _b_dec_WIRE.bits.source, UInt<1>(0h0)
connect _b_dec_WIRE.bits.size, UInt<2>(0h0)
connect _b_dec_WIRE.bits.param, UInt<2>(0h0)
connect _b_dec_WIRE.bits.opcode, UInt<3>(0h0)
connect _b_dec_WIRE.valid, UInt<1>(0h0)
connect _b_dec_WIRE.ready, UInt<1>(0h0)
wire _b_dec_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _b_dec_WIRE_1.bits, _b_dec_WIRE.bits
connect _b_dec_WIRE_1.valid, _b_dec_WIRE.valid
connect _b_dec_WIRE_1.ready, _b_dec_WIRE.ready
node _b_dec_T = and(_b_dec_WIRE_1.ready, _b_dec_WIRE_1.valid)
node _b_dec_T_1 = and(_b_dec_T, b_last)
node b_dec = and(_b_dec_T_1, UInt<1>(0h0))
wire _c_dec_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_dec_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_dec_WIRE.bits.data, UInt<32>(0h0)
connect _c_dec_WIRE.bits.address, UInt<9>(0h0)
connect _c_dec_WIRE.bits.source, UInt<1>(0h0)
connect _c_dec_WIRE.bits.size, UInt<2>(0h0)
connect _c_dec_WIRE.bits.param, UInt<3>(0h0)
connect _c_dec_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_dec_WIRE.valid, UInt<1>(0h0)
connect _c_dec_WIRE.ready, UInt<1>(0h0)
wire _c_dec_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_dec_WIRE_1.bits, _c_dec_WIRE.bits
connect _c_dec_WIRE_1.valid, _c_dec_WIRE.valid
connect _c_dec_WIRE_1.ready, _c_dec_WIRE.ready
node _c_dec_T = and(_c_dec_WIRE_1.ready, _c_dec_WIRE_1.valid)
node _c_dec_T_1 = and(_c_dec_T, c_last)
node c_dec = and(_c_dec_T_1, c_response)
node _d_dec_T = and(nodeIn.d.ready, nodeIn.d.valid)
node _d_dec_T_1 = and(_d_dec_T, d_last)
node d_dec = and(_d_dec_T_1, UInt<1>(0h1))
wire _e_dec_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _e_dec_WIRE.bits.sink, UInt<1>(0h0)
connect _e_dec_WIRE.valid, UInt<1>(0h0)
connect _e_dec_WIRE.ready, UInt<1>(0h0)
wire _e_dec_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _e_dec_WIRE_1.bits, _e_dec_WIRE.bits
connect _e_dec_WIRE_1.valid, _e_dec_WIRE.valid
connect _e_dec_WIRE_1.ready, _e_dec_WIRE.ready
node _e_dec_T = and(_e_dec_WIRE_1.ready, _e_dec_WIRE_1.valid)
node _e_dec_T_1 = and(_e_dec_T, e_last)
node e_dec = and(_e_dec_T_1, UInt<1>(0h1))
node dec = cat(a_dec, d_dec)
node _next_flight_T = bits(inc, 0, 0)
node _next_flight_T_1 = bits(inc, 1, 1)
node _next_flight_T_2 = add(_next_flight_T, _next_flight_T_1)
node _next_flight_T_3 = bits(_next_flight_T_2, 1, 0)
node _next_flight_T_4 = add(flight, _next_flight_T_3)
node _next_flight_T_5 = tail(_next_flight_T_4, 1)
node _next_flight_T_6 = bits(dec, 0, 0)
node _next_flight_T_7 = bits(dec, 1, 1)
node _next_flight_T_8 = add(_next_flight_T_6, _next_flight_T_7)
node _next_flight_T_9 = bits(_next_flight_T_8, 1, 0)
node _next_flight_T_10 = sub(_next_flight_T_5, _next_flight_T_9)
node next_flight = tail(_next_flight_T_10, 1)
connect flight, next_flight
node _io_pending_T = gt(flight, UInt<1>(0h0))
connect io.pending, _io_pending_T
node _T_14 = eq(next_flight, UInt<1>(0h0))
node _T_15 = or(in_reset, _T_14)
when _T_15 :
connect bypass_reg, io.bypass
node _stall_T = neq(bypass, io.bypass)
node _stall_T_1 = and(nodeIn.a.ready, nodeIn.a.valid)
node _stall_beats1_decode_T = dshl(UInt<2>(0h3), nodeIn.a.bits.size)
node _stall_beats1_decode_T_1 = bits(_stall_beats1_decode_T, 1, 0)
node _stall_beats1_decode_T_2 = not(_stall_beats1_decode_T_1)
node stall_beats1_decode = shr(_stall_beats1_decode_T_2, 2)
node _stall_beats1_opdata_T = bits(nodeIn.a.bits.opcode, 2, 2)
node stall_beats1_opdata = eq(_stall_beats1_opdata_T, UInt<1>(0h0))
node stall_beats1 = mux(stall_beats1_opdata, stall_beats1_decode, UInt<1>(0h0))
regreset stall_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _stall_counter1_T = sub(stall_counter, UInt<1>(0h1))
node stall_counter1 = tail(_stall_counter1_T, 1)
node stall_first = eq(stall_counter, UInt<1>(0h0))
node _stall_last_T = eq(stall_counter, UInt<1>(0h1))
node _stall_last_T_1 = eq(stall_beats1, UInt<1>(0h0))
node stall_last = or(_stall_last_T, _stall_last_T_1)
node stall_done = and(stall_last, _stall_T_1)
node _stall_count_T = not(stall_counter1)
node stall_count = and(stall_beats1, _stall_count_T)
when _stall_T_1 :
node _stall_counter_T = mux(stall_first, stall_beats1, stall_counter1)
connect stall_counter, _stall_counter_T
node stall = and(_stall_T, stall_first)
node _nodeOut_a_valid_T = eq(stall, UInt<1>(0h0))
node _nodeOut_a_valid_T_1 = and(_nodeOut_a_valid_T, nodeIn.a.valid)
node _nodeOut_a_valid_T_2 = and(_nodeOut_a_valid_T_1, bypass)
connect nodeOut.a.valid, _nodeOut_a_valid_T_2
node _nodeOut_a_valid_T_3 = eq(stall, UInt<1>(0h0))
node _nodeOut_a_valid_T_4 = and(_nodeOut_a_valid_T_3, nodeIn.a.valid)
node _nodeOut_a_valid_T_5 = eq(bypass, UInt<1>(0h0))
node _nodeOut_a_valid_T_6 = and(_nodeOut_a_valid_T_4, _nodeOut_a_valid_T_5)
connect x1_nodeOut.a.valid, _nodeOut_a_valid_T_6
node _nodeIn_a_ready_T = eq(stall, UInt<1>(0h0))
node _nodeIn_a_ready_T_1 = mux(bypass, nodeOut.a.ready, x1_nodeOut.a.ready)
node _nodeIn_a_ready_T_2 = and(_nodeIn_a_ready_T, _nodeIn_a_ready_T_1)
connect nodeIn.a.ready, _nodeIn_a_ready_T_2
connect nodeOut.a.bits, nodeIn.a.bits
connect x1_nodeOut.a.bits, nodeIn.a.bits
node _nodeOut_d_ready_T = and(nodeIn.d.ready, bypass)
connect nodeOut.d.ready, _nodeOut_d_ready_T
node _nodeOut_d_ready_T_1 = eq(bypass, UInt<1>(0h0))
node _nodeOut_d_ready_T_2 = and(nodeIn.d.ready, _nodeOut_d_ready_T_1)
connect x1_nodeOut.d.ready, _nodeOut_d_ready_T_2
node _nodeIn_d_valid_T = mux(bypass, nodeOut.d.valid, x1_nodeOut.d.valid)
connect nodeIn.d.valid, _nodeIn_d_valid_T
wire nodeIn_d_bits_out : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}
connect nodeIn_d_bits_out, nodeIn.d.bits
connect nodeIn_d_bits_out, nodeOut.d.bits
wire nodeIn_d_bits_out_1 : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}
connect nodeIn_d_bits_out_1, nodeIn.d.bits
connect nodeIn_d_bits_out_1, x1_nodeOut.d.bits
node _nodeIn_d_bits_T = mux(bypass, nodeIn_d_bits_out, nodeIn_d_bits_out_1)
connect nodeIn.d.bits.corrupt, _nodeIn_d_bits_T.corrupt
connect nodeIn.d.bits.data, _nodeIn_d_bits_T.data
connect nodeIn.d.bits.denied, _nodeIn_d_bits_T.denied
connect nodeIn.d.bits.sink, _nodeIn_d_bits_T.sink
connect nodeIn.d.bits.source, _nodeIn_d_bits_T.source
connect nodeIn.d.bits.size, _nodeIn_d_bits_T.size
connect nodeIn.d.bits.param, _nodeIn_d_bits_T.param
connect nodeIn.d.bits.opcode, _nodeIn_d_bits_T.opcode
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<32>(0h0)
connect _WIRE_18.bits.mask, UInt<4>(0h0)
connect _WIRE_18.bits.address, UInt<9>(0h0)
connect _WIRE_18.bits.source, UInt<1>(0h0)
connect _WIRE_18.bits.size, UInt<2>(0h0)
connect _WIRE_18.bits.param, UInt<2>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
connect _WIRE_19.valid, UInt<1>(0h0)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<32>(0h0)
connect _WIRE_20.bits.address, UInt<9>(0h0)
connect _WIRE_20.bits.source, UInt<1>(0h0)
connect _WIRE_20.bits.size, UInt<2>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
connect _WIRE_21.ready, UInt<1>(0h1)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_22.bits.sink, UInt<1>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
connect _WIRE_23.ready, UInt<1>(0h1)
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<128>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<32>(0h0)
connect _WIRE_24.bits.mask, UInt<4>(0h0)
connect _WIRE_24.bits.address, UInt<128>(0h0)
connect _WIRE_24.bits.source, UInt<1>(0h0)
connect _WIRE_24.bits.size, UInt<2>(0h0)
connect _WIRE_24.bits.param, UInt<2>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<128>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
connect _WIRE_25.ready, UInt<1>(0h1)
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<32>(0h0)
connect _WIRE_26.bits.address, UInt<128>(0h0)
connect _WIRE_26.bits.source, UInt<1>(0h0)
connect _WIRE_26.bits.size, UInt<2>(0h0)
connect _WIRE_26.bits.param, UInt<3>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
connect _WIRE_27.valid, UInt<1>(0h0)
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_28.bits.sink, UInt<1>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
connect _WIRE_29.valid, UInt<1>(0h0)
wire _WIRE_30 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_30.bits.corrupt, UInt<1>(0h0)
connect _WIRE_30.bits.data, UInt<32>(0h0)
connect _WIRE_30.bits.mask, UInt<4>(0h0)
connect _WIRE_30.bits.address, UInt<9>(0h0)
connect _WIRE_30.bits.source, UInt<1>(0h0)
connect _WIRE_30.bits.size, UInt<2>(0h0)
connect _WIRE_30.bits.param, UInt<2>(0h0)
connect _WIRE_30.bits.opcode, UInt<3>(0h0)
connect _WIRE_30.valid, UInt<1>(0h0)
connect _WIRE_30.ready, UInt<1>(0h0)
wire _WIRE_31 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_31.bits, _WIRE_30.bits
connect _WIRE_31.valid, _WIRE_30.valid
connect _WIRE_31.ready, _WIRE_30.ready
connect _WIRE_31.ready, UInt<1>(0h1)
wire _WIRE_32 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_32.bits.corrupt, UInt<1>(0h0)
connect _WIRE_32.bits.data, UInt<32>(0h0)
connect _WIRE_32.bits.address, UInt<9>(0h0)
connect _WIRE_32.bits.source, UInt<1>(0h0)
connect _WIRE_32.bits.size, UInt<2>(0h0)
connect _WIRE_32.bits.param, UInt<3>(0h0)
connect _WIRE_32.bits.opcode, UInt<3>(0h0)
connect _WIRE_32.valid, UInt<1>(0h0)
connect _WIRE_32.ready, UInt<1>(0h0)
wire _WIRE_33 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_33.bits, _WIRE_32.bits
connect _WIRE_33.valid, _WIRE_32.valid
connect _WIRE_33.ready, _WIRE_32.ready
connect _WIRE_33.valid, UInt<1>(0h0)
wire _WIRE_34 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_34.bits.sink, UInt<1>(0h0)
connect _WIRE_34.valid, UInt<1>(0h0)
connect _WIRE_34.ready, UInt<1>(0h0)
wire _WIRE_35 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_35.bits, _WIRE_34.bits
connect _WIRE_35.valid, _WIRE_34.valid
connect _WIRE_35.ready, _WIRE_34.ready
connect _WIRE_35.valid, UInt<1>(0h0)
extmodule plusarg_reader_123 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_124 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLBusBypassBar( // @[BusBypass.scala:66:9]
input clock, // @[BusBypass.scala:66:9]
input reset, // @[BusBypass.scala:66:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [8:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_1_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_1_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [8:0] auto_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_1_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_1_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
input auto_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_0_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_0_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_0_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_0_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_0_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
input auto_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input auto_out_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input io_bypass // @[BusBypass.scala:67:16]
);
wire auto_in_a_valid_0 = auto_in_a_valid; // @[BusBypass.scala:66:9]
wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[BusBypass.scala:66:9]
wire [8:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[BusBypass.scala:66:9]
wire [31:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[BusBypass.scala:66:9]
wire auto_in_d_ready_0 = auto_in_d_ready; // @[BusBypass.scala:66:9]
wire auto_out_1_a_ready_0 = auto_out_1_a_ready; // @[BusBypass.scala:66:9]
wire auto_out_1_d_valid_0 = auto_out_1_d_valid; // @[BusBypass.scala:66:9]
wire [2:0] auto_out_1_d_bits_opcode_0 = auto_out_1_d_bits_opcode; // @[BusBypass.scala:66:9]
wire [1:0] auto_out_1_d_bits_param_0 = auto_out_1_d_bits_param; // @[BusBypass.scala:66:9]
wire [1:0] auto_out_1_d_bits_size_0 = auto_out_1_d_bits_size; // @[BusBypass.scala:66:9]
wire auto_out_1_d_bits_source_0 = auto_out_1_d_bits_source; // @[BusBypass.scala:66:9]
wire auto_out_1_d_bits_sink_0 = auto_out_1_d_bits_sink; // @[BusBypass.scala:66:9]
wire auto_out_1_d_bits_denied_0 = auto_out_1_d_bits_denied; // @[BusBypass.scala:66:9]
wire [31:0] auto_out_1_d_bits_data_0 = auto_out_1_d_bits_data; // @[BusBypass.scala:66:9]
wire auto_out_1_d_bits_corrupt_0 = auto_out_1_d_bits_corrupt; // @[BusBypass.scala:66:9]
wire auto_out_0_a_ready_0 = auto_out_0_a_ready; // @[BusBypass.scala:66:9]
wire auto_out_0_d_valid_0 = auto_out_0_d_valid; // @[BusBypass.scala:66:9]
wire [2:0] auto_out_0_d_bits_opcode_0 = auto_out_0_d_bits_opcode; // @[BusBypass.scala:66:9]
wire [1:0] auto_out_0_d_bits_param_0 = auto_out_0_d_bits_param; // @[BusBypass.scala:66:9]
wire [1:0] auto_out_0_d_bits_size_0 = auto_out_0_d_bits_size; // @[BusBypass.scala:66:9]
wire auto_out_0_d_bits_denied_0 = auto_out_0_d_bits_denied; // @[BusBypass.scala:66:9]
wire auto_out_0_d_bits_corrupt_0 = auto_out_0_d_bits_corrupt; // @[BusBypass.scala:66:9]
wire io_bypass_0 = io_bypass; // @[BusBypass.scala:66:9]
wire [4:0] _r_beats1_decode_T_3 = 5'h3; // @[package.scala:243:71]
wire [4:0] _r_beats1_decode_T_6 = 5'h3; // @[package.scala:243:71]
wire [3:0] _b_inc_WIRE_bits_mask = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _b_inc_WIRE_1_bits_mask = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] _b_dec_WIRE_bits_mask = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _b_dec_WIRE_1_bits_mask = 4'h0; // @[Bundles.scala:264:61]
wire [8:0] _b_inc_WIRE_bits_address = 9'h0; // @[Bundles.scala:264:74]
wire [8:0] _b_inc_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:264:61]
wire [8:0] _c_inc_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_inc_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _b_dec_WIRE_bits_address = 9'h0; // @[Bundles.scala:264:74]
wire [8:0] _b_dec_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:264:61]
wire [8:0] _c_dec_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_dec_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [4:0] _r_beats1_decode_T = 5'hC; // @[package.scala:243:71]
wire [4:0] _stall_beats1_decode_T = 5'hC; // @[package.scala:243:71]
wire [1:0] _r_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76]
wire [1:0] _r_beats1_decode_T_5 = 2'h0; // @[package.scala:243:46]
wire [1:0] _r_beats1_decode_T_8 = 2'h0; // @[package.scala:243:46]
wire [1:0] _b_inc_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _b_inc_WIRE_bits_size = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _b_inc_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _b_inc_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _c_inc_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_inc_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _b_dec_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _b_dec_WIRE_bits_size = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _b_dec_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _b_dec_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _c_dec_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_dec_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _stall_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76]
wire [31:0] auto_out_0_d_bits_data = 32'h0; // @[BusBypass.scala:66:9]
wire [31:0] nodeOut_d_bits_data = 32'h0; // @[MixedNode.scala:542:17]
wire [31:0] _b_inc_WIRE_bits_data = 32'h0; // @[Bundles.scala:264:74]
wire [31:0] _b_inc_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:264:61]
wire [31:0] _c_inc_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_inc_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _b_dec_WIRE_bits_data = 32'h0; // @[Bundles.scala:264:74]
wire [31:0] _b_dec_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:264:61]
wire [31:0] _c_dec_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_dec_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] nodeIn_d_bits_out_data = 32'h0; // @[BusBypass.scala:97:53]
wire [3:0] auto_in_a_bits_mask = 4'hF; // @[Nodes.scala:27:25]
wire [3:0] auto_out_1_a_bits_mask = 4'hF; // @[Nodes.scala:27:25]
wire [3:0] auto_out_0_a_bits_mask = 4'hF; // @[Nodes.scala:27:25]
wire [3:0] nodeIn_a_bits_mask = 4'hF; // @[Nodes.scala:27:25]
wire [3:0] nodeOut_a_bits_mask = 4'hF; // @[Nodes.scala:27:25]
wire [3:0] x1_nodeOut_a_bits_mask = 4'hF; // @[Nodes.scala:27:25]
wire [1:0] auto_in_a_bits_size = 2'h2; // @[Nodes.scala:27:25]
wire [1:0] auto_out_1_a_bits_size = 2'h2; // @[Nodes.scala:27:25]
wire [1:0] auto_out_0_a_bits_size = 2'h2; // @[Nodes.scala:27:25]
wire [1:0] nodeIn_a_bits_size = 2'h2; // @[Nodes.scala:27:25]
wire [1:0] nodeOut_a_bits_size = 2'h2; // @[Nodes.scala:27:25]
wire [1:0] x1_nodeOut_a_bits_size = 2'h2; // @[Nodes.scala:27:25]
wire [2:0] auto_in_a_bits_param = 3'h0; // @[BusBypass.scala:66:9]
wire [2:0] auto_out_1_a_bits_param = 3'h0; // @[BusBypass.scala:66:9]
wire [2:0] auto_out_0_a_bits_param = 3'h0; // @[BusBypass.scala:66:9]
wire [2:0] nodeIn_a_bits_param = 3'h0; // @[MixedNode.scala:551:17]
wire [2:0] nodeOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] x1_nodeOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] _b_inc_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _b_inc_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] _c_inc_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_inc_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_inc_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_inc_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _b_dec_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _b_dec_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] _c_dec_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_dec_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_dec_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_dec_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [1:0] _r_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46]
wire [1:0] _r_beats1_decode_T_4 = 2'h3; // @[package.scala:243:76]
wire [1:0] _r_counter1_T_1 = 2'h3; // @[Edges.scala:230:28]
wire [1:0] _r_beats1_decode_T_7 = 2'h3; // @[package.scala:243:76]
wire [1:0] _r_counter1_T_2 = 2'h3; // @[Edges.scala:230:28]
wire [1:0] _r_counter1_T_4 = 2'h3; // @[Edges.scala:230:28]
wire [1:0] _stall_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46]
wire _r_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire a_last = 1'h1; // @[Edges.scala:232:33]
wire r_beats1_opdata_1 = 1'h1; // @[Edges.scala:97:28]
wire r_counter1_1 = 1'h1; // @[Edges.scala:230:28]
wire b_first = 1'h1; // @[Edges.scala:231:25]
wire _r_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire b_last = 1'h1; // @[Edges.scala:232:33]
wire r_counter1_2 = 1'h1; // @[Edges.scala:230:28]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _r_last_T_5 = 1'h1; // @[Edges.scala:232:43]
wire c_last = 1'h1; // @[Edges.scala:232:33]
wire _r_last_T_7 = 1'h1; // @[Edges.scala:232:43]
wire d_last = 1'h1; // @[Edges.scala:232:33]
wire r_counter1_4 = 1'h1; // @[Edges.scala:230:28]
wire e_first = 1'h1; // @[Edges.scala:231:25]
wire _r_last_T_9 = 1'h1; // @[Edges.scala:232:43]
wire e_last = 1'h1; // @[Edges.scala:232:33]
wire c_response = 1'h1; // @[Edges.scala:82:41]
wire _stall_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire stall_last = 1'h1; // @[Edges.scala:232:33]
wire auto_in_a_bits_source = 1'h0; // @[BusBypass.scala:66:9]
wire auto_in_a_bits_corrupt = 1'h0; // @[BusBypass.scala:66:9]
wire auto_out_1_a_bits_source = 1'h0; // @[BusBypass.scala:66:9]
wire auto_out_1_a_bits_corrupt = 1'h0; // @[BusBypass.scala:66:9]
wire auto_out_0_a_bits_source = 1'h0; // @[BusBypass.scala:66:9]
wire auto_out_0_a_bits_corrupt = 1'h0; // @[BusBypass.scala:66:9]
wire auto_out_0_d_bits_source = 1'h0; // @[BusBypass.scala:66:9]
wire auto_out_0_d_bits_sink = 1'h0; // @[BusBypass.scala:66:9]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire nodeIn_a_bits_source = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire nodeOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_d_bits_source = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17]
wire x1_nodeOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17]
wire x1_nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire r_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire r_beats1 = 1'h0; // @[Edges.scala:221:14]
wire r_4 = 1'h0; // @[Edges.scala:234:25]
wire r_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire _r_beats1_opdata_T_1 = 1'h0; // @[Edges.scala:97:37]
wire r_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire _r_last_T_2 = 1'h0; // @[Edges.scala:232:25]
wire r_3_1 = 1'h0; // @[Edges.scala:233:22]
wire _r_count_T_1 = 1'h0; // @[Edges.scala:234:27]
wire r_4_1 = 1'h0; // @[Edges.scala:234:25]
wire _r_counter_T_1 = 1'h0; // @[Edges.scala:236:21]
wire r_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59]
wire r_beats1_opdata_2 = 1'h0; // @[Edges.scala:102:36]
wire r_beats1_2 = 1'h0; // @[Edges.scala:221:14]
wire _r_last_T_4 = 1'h0; // @[Edges.scala:232:25]
wire r_3_2 = 1'h0; // @[Edges.scala:233:22]
wire _r_count_T_2 = 1'h0; // @[Edges.scala:234:27]
wire r_4_2 = 1'h0; // @[Edges.scala:234:25]
wire _r_counter_T_2 = 1'h0; // @[Edges.scala:236:21]
wire r_beats1_decode_3 = 1'h0; // @[Edges.scala:220:59]
wire r_beats1_3 = 1'h0; // @[Edges.scala:221:14]
wire r_4_3 = 1'h0; // @[Edges.scala:234:25]
wire _r_last_T_8 = 1'h0; // @[Edges.scala:232:25]
wire r_3_4 = 1'h0; // @[Edges.scala:233:22]
wire _r_count_T_4 = 1'h0; // @[Edges.scala:234:27]
wire r_4_4 = 1'h0; // @[Edges.scala:234:25]
wire _r_counter_T_4 = 1'h0; // @[Edges.scala:236:21]
wire c_request = 1'h0; // @[Edges.scala:68:40]
wire _b_inc_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire _b_inc_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire _b_inc_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74]
wire _b_inc_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _b_inc_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire _b_inc_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61]
wire _b_inc_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61]
wire _b_inc_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire _b_inc_T = 1'h0; // @[Decoupled.scala:51:35]
wire _b_inc_T_1 = 1'h0; // @[Edges.scala:311:26]
wire b_inc = 1'h0; // @[Edges.scala:311:37]
wire _c_inc_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_inc_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_inc_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_inc_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_inc_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_inc_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_inc_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_inc_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_inc_T = 1'h0; // @[Decoupled.scala:51:35]
wire _c_inc_T_1 = 1'h0; // @[Edges.scala:312:26]
wire c_inc = 1'h0; // @[Edges.scala:312:37]
wire _e_inc_WIRE_ready = 1'h0; // @[Bundles.scala:267:74]
wire _e_inc_WIRE_valid = 1'h0; // @[Bundles.scala:267:74]
wire _e_inc_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire _e_inc_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61]
wire _e_inc_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61]
wire _e_inc_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire _e_inc_T = 1'h0; // @[Decoupled.scala:51:35]
wire _e_inc_T_1 = 1'h0; // @[Edges.scala:314:26]
wire e_inc = 1'h0; // @[Edges.scala:314:37]
wire a_dec = 1'h0; // @[Edges.scala:317:36]
wire _b_dec_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire _b_dec_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire _b_dec_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74]
wire _b_dec_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _b_dec_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire _b_dec_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61]
wire _b_dec_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61]
wire _b_dec_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire _b_dec_T = 1'h0; // @[Decoupled.scala:51:35]
wire _b_dec_T_1 = 1'h0; // @[Edges.scala:318:26]
wire b_dec = 1'h0; // @[Edges.scala:318:36]
wire _c_dec_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_dec_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_dec_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_dec_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_dec_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_dec_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_dec_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_dec_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_dec_T = 1'h0; // @[Decoupled.scala:51:35]
wire _c_dec_T_1 = 1'h0; // @[Edges.scala:319:26]
wire c_dec = 1'h0; // @[Edges.scala:319:36]
wire _e_dec_WIRE_ready = 1'h0; // @[Bundles.scala:267:74]
wire _e_dec_WIRE_valid = 1'h0; // @[Bundles.scala:267:74]
wire _e_dec_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire _e_dec_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61]
wire _e_dec_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61]
wire _e_dec_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire _e_dec_T = 1'h0; // @[Decoupled.scala:51:35]
wire _e_dec_T_1 = 1'h0; // @[Edges.scala:321:26]
wire e_dec = 1'h0; // @[Edges.scala:321:36]
wire stall_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire stall_beats1 = 1'h0; // @[Edges.scala:221:14]
wire stall_count = 1'h0; // @[Edges.scala:234:25]
wire nodeIn_d_bits_out_source = 1'h0; // @[BusBypass.scala:97:53]
wire nodeIn_d_bits_out_sink = 1'h0; // @[BusBypass.scala:97:53]
wire nodeIn_a_valid = auto_in_a_valid_0; // @[BusBypass.scala:66:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[BusBypass.scala:66:9]
wire [8:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[BusBypass.scala:66:9]
wire [31:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[BusBypass.scala:66:9]
wire nodeIn_d_ready = auto_in_d_ready_0; // @[BusBypass.scala:66:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [31:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire x1_nodeOut_a_ready = auto_out_1_a_ready_0; // @[BusBypass.scala:66:9]
wire x1_nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [8:0] x1_nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [31:0] x1_nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire x1_nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire x1_nodeOut_d_valid = auto_out_1_d_valid_0; // @[BusBypass.scala:66:9]
wire [2:0] x1_nodeOut_d_bits_opcode = auto_out_1_d_bits_opcode_0; // @[BusBypass.scala:66:9]
wire [1:0] x1_nodeOut_d_bits_param = auto_out_1_d_bits_param_0; // @[BusBypass.scala:66:9]
wire [1:0] x1_nodeOut_d_bits_size = auto_out_1_d_bits_size_0; // @[BusBypass.scala:66:9]
wire x1_nodeOut_d_bits_source = auto_out_1_d_bits_source_0; // @[BusBypass.scala:66:9]
wire x1_nodeOut_d_bits_sink = auto_out_1_d_bits_sink_0; // @[BusBypass.scala:66:9]
wire x1_nodeOut_d_bits_denied = auto_out_1_d_bits_denied_0; // @[BusBypass.scala:66:9]
wire [31:0] x1_nodeOut_d_bits_data = auto_out_1_d_bits_data_0; // @[BusBypass.scala:66:9]
wire x1_nodeOut_d_bits_corrupt = auto_out_1_d_bits_corrupt_0; // @[BusBypass.scala:66:9]
wire nodeOut_a_ready = auto_out_0_a_ready_0; // @[BusBypass.scala:66:9]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [127:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire nodeOut_d_valid = auto_out_0_d_valid_0; // @[BusBypass.scala:66:9]
wire [2:0] nodeOut_d_bits_opcode = auto_out_0_d_bits_opcode_0; // @[BusBypass.scala:66:9]
wire [1:0] nodeOut_d_bits_param = auto_out_0_d_bits_param_0; // @[BusBypass.scala:66:9]
wire [1:0] nodeOut_d_bits_size = auto_out_0_d_bits_size_0; // @[BusBypass.scala:66:9]
wire nodeOut_d_bits_denied = auto_out_0_d_bits_denied_0; // @[BusBypass.scala:66:9]
wire nodeOut_d_bits_corrupt = auto_out_0_d_bits_corrupt_0; // @[BusBypass.scala:66:9]
wire _io_pending_T; // @[BusBypass.scala:84:27]
wire auto_in_a_ready_0; // @[BusBypass.scala:66:9]
wire [2:0] auto_in_d_bits_opcode_0; // @[BusBypass.scala:66:9]
wire [1:0] auto_in_d_bits_param_0; // @[BusBypass.scala:66:9]
wire [1:0] auto_in_d_bits_size_0; // @[BusBypass.scala:66:9]
wire auto_in_d_bits_source_0; // @[BusBypass.scala:66:9]
wire auto_in_d_bits_sink_0; // @[BusBypass.scala:66:9]
wire auto_in_d_bits_denied_0; // @[BusBypass.scala:66:9]
wire [31:0] auto_in_d_bits_data_0; // @[BusBypass.scala:66:9]
wire auto_in_d_bits_corrupt_0; // @[BusBypass.scala:66:9]
wire auto_in_d_valid_0; // @[BusBypass.scala:66:9]
wire [2:0] auto_out_1_a_bits_opcode_0; // @[BusBypass.scala:66:9]
wire [8:0] auto_out_1_a_bits_address_0; // @[BusBypass.scala:66:9]
wire [31:0] auto_out_1_a_bits_data_0; // @[BusBypass.scala:66:9]
wire auto_out_1_a_valid_0; // @[BusBypass.scala:66:9]
wire auto_out_1_d_ready_0; // @[BusBypass.scala:66:9]
wire [2:0] auto_out_0_a_bits_opcode_0; // @[BusBypass.scala:66:9]
wire [127:0] auto_out_0_a_bits_address_0; // @[BusBypass.scala:66:9]
wire [31:0] auto_out_0_a_bits_data_0; // @[BusBypass.scala:66:9]
wire auto_out_0_a_valid_0; // @[BusBypass.scala:66:9]
wire auto_out_0_d_ready_0; // @[BusBypass.scala:66:9]
wire io_pending; // @[BusBypass.scala:66:9]
wire _nodeIn_a_ready_T_2; // @[BusBypass.scala:90:28]
assign auto_in_a_ready_0 = nodeIn_a_ready; // @[BusBypass.scala:66:9]
assign nodeOut_a_bits_opcode = nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_a_bits_opcode = nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_a_bits_address = nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_a_bits_data = nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_a_bits_data = nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire _nodeIn_d_valid_T; // @[BusBypass.scala:96:24]
assign auto_in_d_valid_0 = nodeIn_d_valid; // @[BusBypass.scala:66:9]
wire [2:0] _nodeIn_d_bits_T_opcode; // @[BusBypass.scala:98:21]
assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[BusBypass.scala:66:9]
wire [1:0] _nodeIn_d_bits_T_param; // @[BusBypass.scala:98:21]
assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[BusBypass.scala:66:9]
wire [1:0] _nodeIn_d_bits_T_size; // @[BusBypass.scala:98:21]
assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[BusBypass.scala:66:9]
wire _nodeIn_d_bits_T_source; // @[BusBypass.scala:98:21]
assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[BusBypass.scala:66:9]
wire _nodeIn_d_bits_T_sink; // @[BusBypass.scala:98:21]
assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[BusBypass.scala:66:9]
wire _nodeIn_d_bits_T_denied; // @[BusBypass.scala:98:21]
assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[BusBypass.scala:66:9]
wire [31:0] _nodeIn_d_bits_T_data; // @[BusBypass.scala:98:21]
assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[BusBypass.scala:66:9]
wire _nodeIn_d_bits_T_corrupt; // @[BusBypass.scala:98:21]
assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[BusBypass.scala:66:9]
wire _nodeOut_a_valid_T_2; // @[BusBypass.scala:88:42]
assign auto_out_0_a_valid_0 = nodeOut_a_valid; // @[BusBypass.scala:66:9]
assign auto_out_0_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[BusBypass.scala:66:9]
assign auto_out_0_a_bits_address_0 = nodeOut_a_bits_address; // @[BusBypass.scala:66:9]
assign auto_out_0_a_bits_data_0 = nodeOut_a_bits_data; // @[BusBypass.scala:66:9]
wire _nodeOut_d_ready_T; // @[BusBypass.scala:94:32]
assign auto_out_0_d_ready_0 = nodeOut_d_ready; // @[BusBypass.scala:66:9]
wire [2:0] nodeIn_d_bits_out_opcode = nodeOut_d_bits_opcode; // @[BusBypass.scala:97:53]
wire [1:0] nodeIn_d_bits_out_param = nodeOut_d_bits_param; // @[BusBypass.scala:97:53]
wire [1:0] nodeIn_d_bits_out_size = nodeOut_d_bits_size; // @[BusBypass.scala:97:53]
wire nodeIn_d_bits_out_denied = nodeOut_d_bits_denied; // @[BusBypass.scala:97:53]
wire nodeIn_d_bits_out_corrupt = nodeOut_d_bits_corrupt; // @[BusBypass.scala:97:53]
wire _nodeOut_a_valid_T_6; // @[BusBypass.scala:89:42]
assign auto_out_1_a_valid_0 = x1_nodeOut_a_valid; // @[BusBypass.scala:66:9]
assign auto_out_1_a_bits_opcode_0 = x1_nodeOut_a_bits_opcode; // @[BusBypass.scala:66:9]
assign auto_out_1_a_bits_address_0 = x1_nodeOut_a_bits_address; // @[BusBypass.scala:66:9]
assign auto_out_1_a_bits_data_0 = x1_nodeOut_a_bits_data; // @[BusBypass.scala:66:9]
wire _nodeOut_d_ready_T_2; // @[BusBypass.scala:95:32]
assign auto_out_1_d_ready_0 = x1_nodeOut_d_ready; // @[BusBypass.scala:66:9]
wire [2:0] nodeIn_d_bits_out_1_opcode = x1_nodeOut_d_bits_opcode; // @[BusBypass.scala:97:53]
wire [1:0] nodeIn_d_bits_out_1_param = x1_nodeOut_d_bits_param; // @[BusBypass.scala:97:53]
wire [1:0] nodeIn_d_bits_out_1_size = x1_nodeOut_d_bits_size; // @[BusBypass.scala:97:53]
wire nodeIn_d_bits_out_1_source = x1_nodeOut_d_bits_source; // @[BusBypass.scala:97:53]
wire nodeIn_d_bits_out_1_sink = x1_nodeOut_d_bits_sink; // @[BusBypass.scala:97:53]
wire nodeIn_d_bits_out_1_denied = x1_nodeOut_d_bits_denied; // @[BusBypass.scala:97:53]
wire [31:0] nodeIn_d_bits_out_1_data = x1_nodeOut_d_bits_data; // @[BusBypass.scala:97:53]
wire nodeIn_d_bits_out_1_corrupt = x1_nodeOut_d_bits_corrupt; // @[BusBypass.scala:97:53]
reg in_reset; // @[BusBypass.scala:79:27]
reg bypass_reg; // @[BusBypass.scala:80:25]
wire bypass = in_reset ? io_bypass_0 : bypass_reg; // @[BusBypass.scala:66:9, :79:27, :80:25, :81:21]
reg [1:0] flight; // @[Edges.scala:295:25]
wire _T = nodeIn_a_ready & nodeIn_a_valid; // @[Decoupled.scala:51:35]
wire r_3; // @[Edges.scala:233:22]
assign r_3 = _T; // @[Decoupled.scala:51:35]
wire _a_inc_T; // @[Decoupled.scala:51:35]
assign _a_inc_T = _T; // @[Decoupled.scala:51:35]
wire _a_dec_T; // @[Decoupled.scala:51:35]
assign _a_dec_T = _T; // @[Decoupled.scala:51:35]
wire _stall_T_1; // @[Decoupled.scala:51:35]
assign _stall_T_1 = _T; // @[Decoupled.scala:51:35]
wire _r_beats1_opdata_T = nodeIn_a_bits_opcode[2]; // @[Edges.scala:92:37]
wire _stall_beats1_opdata_T = nodeIn_a_bits_opcode[2]; // @[Edges.scala:92:37]
wire r_beats1_opdata = ~_r_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
reg r_counter; // @[Edges.scala:229:27]
wire _r_last_T = r_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _r_counter1_T = {1'h0, r_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire r_counter1 = _r_counter1_T[0]; // @[Edges.scala:230:28]
wire a_first = ~r_counter; // @[Edges.scala:229:27, :231:25]
wire _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27]
wire _r_counter_T = ~a_first & r_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
wire _T_3 = nodeIn_d_ready & nodeIn_d_valid; // @[Decoupled.scala:51:35]
wire r_3_3; // @[Edges.scala:233:22]
assign r_3_3 = _T_3; // @[Decoupled.scala:51:35]
wire _d_inc_T; // @[Decoupled.scala:51:35]
assign _d_inc_T = _T_3; // @[Decoupled.scala:51:35]
wire _d_dec_T; // @[Decoupled.scala:51:35]
assign _d_dec_T = _T_3; // @[Decoupled.scala:51:35]
wire [4:0] _r_beats1_decode_T_9 = 5'h3 << nodeIn_d_bits_size; // @[package.scala:243:71]
wire [1:0] _r_beats1_decode_T_10 = _r_beats1_decode_T_9[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _r_beats1_decode_T_11 = ~_r_beats1_decode_T_10; // @[package.scala:243:{46,76}]
wire r_beats1_opdata_3 = nodeIn_d_bits_opcode[0]; // @[Edges.scala:106:36]
reg r_counter_3; // @[Edges.scala:229:27]
wire _r_last_T_6 = r_counter_3; // @[Edges.scala:229:27, :232:25]
wire [1:0] _r_counter1_T_3 = {1'h0, r_counter_3} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire r_counter1_3 = _r_counter1_T_3[0]; // @[Edges.scala:230:28]
wire d_first = ~r_counter_3; // @[Edges.scala:229:27, :231:25]
wire _r_count_T_3 = ~r_counter1_3; // @[Edges.scala:230:28, :234:27]
wire _r_counter_T_3 = ~d_first & r_counter1_3; // @[Edges.scala:230:28, :231:25, :236:21]
wire d_request = nodeIn_d_bits_opcode[2] & ~(nodeIn_d_bits_opcode[1]); // @[Edges.scala:71:{36,40,43,52}]
wire _a_inc_T_1 = _a_inc_T & a_first; // @[Decoupled.scala:51:35]
wire a_inc = _a_inc_T_1; // @[Edges.scala:310:{26,37}]
wire _d_inc_T_1 = _d_inc_T & d_first; // @[Decoupled.scala:51:35]
wire d_inc = _d_inc_T_1 & d_request; // @[Edges.scala:71:40, :313:{26,37}]
wire [1:0] inc = {a_inc, d_inc}; // @[Edges.scala:310:37, :313:37, :315:18]
wire _a_dec_T_1 = _a_dec_T; // @[Decoupled.scala:51:35]
wire _d_dec_T_1 = _d_dec_T; // @[Decoupled.scala:51:35]
wire d_dec = _d_dec_T_1; // @[Edges.scala:320:{26,36}]
wire [1:0] dec = {1'h0, d_dec}; // @[Edges.scala:320:36, :322:18]
wire _next_flight_T = inc[0]; // @[Edges.scala:315:18, :324:40]
wire _next_flight_T_1 = inc[1]; // @[Edges.scala:315:18, :324:40]
wire [1:0] _next_flight_T_2 = {1'h0, _next_flight_T} + {1'h0, _next_flight_T_1}; // @[Edges.scala:324:40]
wire [1:0] _next_flight_T_3 = _next_flight_T_2; // @[Edges.scala:324:40]
wire [2:0] _next_flight_T_4 = {1'h0, flight} + {1'h0, _next_flight_T_3}; // @[Edges.scala:295:25, :324:{30,40}]
wire [1:0] _next_flight_T_5 = _next_flight_T_4[1:0]; // @[Edges.scala:324:30]
wire _next_flight_T_6 = dec[0]; // @[Edges.scala:322:18, :324:56]
wire _next_flight_T_7 = dec[1]; // @[Edges.scala:322:18, :324:56]
wire [1:0] _next_flight_T_8 = {1'h0, _next_flight_T_6} + {1'h0, _next_flight_T_7}; // @[Edges.scala:324:56]
wire [1:0] _next_flight_T_9 = _next_flight_T_8; // @[Edges.scala:324:56]
wire [2:0] _next_flight_T_10 = {1'h0, _next_flight_T_5} - {1'h0, _next_flight_T_9}; // @[Edges.scala:324:{30,46,56}]
wire [1:0] next_flight = _next_flight_T_10[1:0]; // @[Edges.scala:324:46]
assign _io_pending_T = |flight; // @[Edges.scala:295:25]
assign io_pending = _io_pending_T; // @[BusBypass.scala:66:9, :84:27]
wire _stall_T = bypass != io_bypass_0; // @[BusBypass.scala:66:9, :81:21, :86:25]
wire stall_done = _stall_T_1; // @[Decoupled.scala:51:35]
wire stall_beats1_opdata = ~_stall_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
reg stall_counter; // @[Edges.scala:229:27]
wire _stall_last_T = stall_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _stall_counter1_T = {1'h0, stall_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire stall_counter1 = _stall_counter1_T[0]; // @[Edges.scala:230:28]
wire stall_first = ~stall_counter; // @[Edges.scala:229:27, :231:25]
wire _stall_count_T = ~stall_counter1; // @[Edges.scala:230:28, :234:27]
wire _stall_counter_T = ~stall_first & stall_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
wire stall = _stall_T & stall_first; // @[Edges.scala:231:25]
wire _nodeOut_a_valid_T = ~stall; // @[BusBypass.scala:86:40, :88:21]
wire _nodeOut_a_valid_T_1 = _nodeOut_a_valid_T & nodeIn_a_valid; // @[BusBypass.scala:88:{21,28}]
assign _nodeOut_a_valid_T_2 = _nodeOut_a_valid_T_1 & bypass; // @[BusBypass.scala:81:21, :88:{28,42}]
assign nodeOut_a_valid = _nodeOut_a_valid_T_2; // @[BusBypass.scala:88:42]
wire _nodeOut_a_valid_T_3 = ~stall; // @[BusBypass.scala:86:40, :88:21, :89:21]
wire _nodeOut_a_valid_T_4 = _nodeOut_a_valid_T_3 & nodeIn_a_valid; // @[BusBypass.scala:89:{21,28}]
wire _nodeOut_a_valid_T_5 = ~bypass; // @[BusBypass.scala:81:21, :89:45]
assign _nodeOut_a_valid_T_6 = _nodeOut_a_valid_T_4 & _nodeOut_a_valid_T_5; // @[BusBypass.scala:89:{28,42,45}]
assign x1_nodeOut_a_valid = _nodeOut_a_valid_T_6; // @[BusBypass.scala:89:42]
wire _nodeIn_a_ready_T = ~stall; // @[BusBypass.scala:86:40, :88:21, :90:21]
wire _nodeIn_a_ready_T_1 = bypass ? nodeOut_a_ready : x1_nodeOut_a_ready; // @[BusBypass.scala:81:21, :90:34]
assign _nodeIn_a_ready_T_2 = _nodeIn_a_ready_T & _nodeIn_a_ready_T_1; // @[BusBypass.scala:90:{21,28,34}]
assign nodeIn_a_ready = _nodeIn_a_ready_T_2; // @[BusBypass.scala:90:28]
assign nodeOut_a_bits_address = {119'h0, nodeIn_a_bits_address}; // @[BusBypass.scala:91:18]
assign _nodeOut_d_ready_T = nodeIn_d_ready & bypass; // @[BusBypass.scala:81:21, :94:32]
assign nodeOut_d_ready = _nodeOut_d_ready_T; // @[BusBypass.scala:94:32]
wire _nodeOut_d_ready_T_1 = ~bypass; // @[BusBypass.scala:81:21, :89:45, :95:35]
assign _nodeOut_d_ready_T_2 = nodeIn_d_ready & _nodeOut_d_ready_T_1; // @[BusBypass.scala:95:{32,35}]
assign x1_nodeOut_d_ready = _nodeOut_d_ready_T_2; // @[BusBypass.scala:95:32]
assign _nodeIn_d_valid_T = bypass ? nodeOut_d_valid : x1_nodeOut_d_valid; // @[BusBypass.scala:81:21, :96:24]
assign nodeIn_d_valid = _nodeIn_d_valid_T; // @[BusBypass.scala:96:24]
assign _nodeIn_d_bits_T_opcode = bypass ? nodeIn_d_bits_out_opcode : nodeIn_d_bits_out_1_opcode; // @[BusBypass.scala:81:21, :97:53, :98:21]
assign _nodeIn_d_bits_T_param = bypass ? nodeIn_d_bits_out_param : nodeIn_d_bits_out_1_param; // @[BusBypass.scala:81:21, :97:53, :98:21]
assign _nodeIn_d_bits_T_size = bypass ? nodeIn_d_bits_out_size : nodeIn_d_bits_out_1_size; // @[BusBypass.scala:81:21, :97:53, :98:21]
assign _nodeIn_d_bits_T_source = ~bypass & nodeIn_d_bits_out_1_source; // @[BusBypass.scala:81:21, :97:53, :98:21]
assign _nodeIn_d_bits_T_sink = ~bypass & nodeIn_d_bits_out_1_sink; // @[BusBypass.scala:81:21, :97:53, :98:21]
assign _nodeIn_d_bits_T_denied = bypass ? nodeIn_d_bits_out_denied : nodeIn_d_bits_out_1_denied; // @[BusBypass.scala:81:21, :97:53, :98:21]
assign _nodeIn_d_bits_T_data = bypass ? 32'h0 : nodeIn_d_bits_out_1_data; // @[BusBypass.scala:81:21, :97:53, :98:21]
assign _nodeIn_d_bits_T_corrupt = bypass ? nodeIn_d_bits_out_corrupt : nodeIn_d_bits_out_1_corrupt; // @[BusBypass.scala:81:21, :97:53, :98:21]
assign nodeIn_d_bits_opcode = _nodeIn_d_bits_T_opcode; // @[BusBypass.scala:98:21]
assign nodeIn_d_bits_param = _nodeIn_d_bits_T_param; // @[BusBypass.scala:98:21]
assign nodeIn_d_bits_size = _nodeIn_d_bits_T_size; // @[BusBypass.scala:98:21]
assign nodeIn_d_bits_source = _nodeIn_d_bits_T_source; // @[BusBypass.scala:98:21]
assign nodeIn_d_bits_sink = _nodeIn_d_bits_T_sink; // @[BusBypass.scala:98:21]
assign nodeIn_d_bits_denied = _nodeIn_d_bits_T_denied; // @[BusBypass.scala:98:21]
assign nodeIn_d_bits_data = _nodeIn_d_bits_T_data; // @[BusBypass.scala:98:21]
assign nodeIn_d_bits_corrupt = _nodeIn_d_bits_T_corrupt; // @[BusBypass.scala:98:21]
always @(posedge clock) begin // @[BusBypass.scala:66:9]
if (reset) begin // @[BusBypass.scala:66:9]
in_reset <= 1'h1; // @[BusBypass.scala:79:27]
flight <= 2'h0; // @[Edges.scala:295:25]
r_counter <= 1'h0; // @[Edges.scala:229:27]
r_counter_3 <= 1'h0; // @[Edges.scala:229:27]
stall_counter <= 1'h0; // @[Edges.scala:229:27]
end
else begin // @[BusBypass.scala:66:9]
in_reset <= 1'h0; // @[BusBypass.scala:79:27]
flight <= next_flight; // @[Edges.scala:295:25, :324:46]
if (_T) // @[Decoupled.scala:51:35]
r_counter <= _r_counter_T; // @[Edges.scala:229:27, :236:21]
if (_T_3) // @[Decoupled.scala:51:35]
r_counter_3 <= _r_counter_T_3; // @[Edges.scala:229:27, :236:21]
if (_stall_T_1) // @[Decoupled.scala:51:35]
stall_counter <= _stall_counter_T; // @[Edges.scala:229:27, :236:21]
end
if (in_reset | next_flight == 2'h0) // @[Edges.scala:324:46]
bypass_reg <= io_bypass_0; // @[BusBypass.scala:66:9, :80:25]
always @(posedge)
TLMonitor_60 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
assign auto_in_a_ready = auto_in_a_ready_0; // @[BusBypass.scala:66:9]
assign auto_in_d_valid = auto_in_d_valid_0; // @[BusBypass.scala:66:9]
assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[BusBypass.scala:66:9]
assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[BusBypass.scala:66:9]
assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[BusBypass.scala:66:9]
assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[BusBypass.scala:66:9]
assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[BusBypass.scala:66:9]
assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[BusBypass.scala:66:9]
assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[BusBypass.scala:66:9]
assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[BusBypass.scala:66:9]
assign auto_out_1_a_valid = auto_out_1_a_valid_0; // @[BusBypass.scala:66:9]
assign auto_out_1_a_bits_opcode = auto_out_1_a_bits_opcode_0; // @[BusBypass.scala:66:9]
assign auto_out_1_a_bits_address = auto_out_1_a_bits_address_0; // @[BusBypass.scala:66:9]
assign auto_out_1_a_bits_data = auto_out_1_a_bits_data_0; // @[BusBypass.scala:66:9]
assign auto_out_1_d_ready = auto_out_1_d_ready_0; // @[BusBypass.scala:66:9]
assign auto_out_0_a_valid = auto_out_0_a_valid_0; // @[BusBypass.scala:66:9]
assign auto_out_0_a_bits_opcode = auto_out_0_a_bits_opcode_0; // @[BusBypass.scala:66:9]
assign auto_out_0_a_bits_address = auto_out_0_a_bits_address_0; // @[BusBypass.scala:66:9]
assign auto_out_0_a_bits_data = auto_out_0_a_bits_data_0; // @[BusBypass.scala:66:9]
assign auto_out_0_d_ready = auto_out_0_d_ready_0; // @[BusBypass.scala:66:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_21 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<6>(0h30))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<4>(0h8))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<4>(0h9))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<4>(0ha))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<4>(0hb))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 2, 0)
node _source_ok_T_25 = shr(io.in.a.bits.source, 3)
node _source_ok_T_26 = eq(_source_ok_T_25, UInt<2>(0h2))
node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27)
node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<3>(0h7))
node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29)
node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 2, 0)
node _source_ok_T_31 = shr(io.in.a.bits.source, 3)
node _source_ok_T_32 = eq(_source_ok_T_31, UInt<1>(0h1))
node _source_ok_T_33 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_34 = and(_source_ok_T_32, _source_ok_T_33)
node _source_ok_T_35 = leq(source_ok_uncommonBits_5, UInt<3>(0h7))
node _source_ok_T_36 = and(_source_ok_T_34, _source_ok_T_35)
node _source_ok_uncommonBits_T_6 = or(io.in.a.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 2, 0)
node _source_ok_T_37 = shr(io.in.a.bits.source, 3)
node _source_ok_T_38 = eq(_source_ok_T_37, UInt<1>(0h0))
node _source_ok_T_39 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39)
node _source_ok_T_41 = leq(source_ok_uncommonBits_6, UInt<3>(0h7))
node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41)
node _source_ok_T_43 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE : UInt<1>[9]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_30
connect _source_ok_WIRE[6], _source_ok_T_36
connect _source_ok_WIRE[7], _source_ok_T_42
connect _source_ok_WIRE[8], _source_ok_T_43
node _source_ok_T_44 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_45 = or(_source_ok_T_44, _source_ok_WIRE[2])
node _source_ok_T_46 = or(_source_ok_T_45, _source_ok_WIRE[3])
node _source_ok_T_47 = or(_source_ok_T_46, _source_ok_WIRE[4])
node _source_ok_T_48 = or(_source_ok_T_47, _source_ok_WIRE[5])
node _source_ok_T_49 = or(_source_ok_T_48, _source_ok_WIRE[6])
node _source_ok_T_50 = or(_source_ok_T_49, _source_ok_WIRE[7])
node source_ok = or(_source_ok_T_50, _source_ok_WIRE[8])
node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<4>(0h8))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<4>(0h9))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<4>(0ha))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<4>(0hb))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 2, 0)
node _T_64 = shr(io.in.a.bits.source, 3)
node _T_65 = eq(_T_64, UInt<2>(0h2))
node _T_66 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_67 = and(_T_65, _T_66)
node _T_68 = leq(uncommonBits_4, UInt<3>(0h7))
node _T_69 = and(_T_67, _T_68)
node _T_70 = eq(_T_69, UInt<1>(0h0))
node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_72 = cvt(_T_71)
node _T_73 = and(_T_72, asSInt(UInt<1>(0h0)))
node _T_74 = asSInt(_T_73)
node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0)))
node _T_76 = or(_T_70, _T_75)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 2, 0)
node _T_77 = shr(io.in.a.bits.source, 3)
node _T_78 = eq(_T_77, UInt<1>(0h1))
node _T_79 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_80 = and(_T_78, _T_79)
node _T_81 = leq(uncommonBits_5, UInt<3>(0h7))
node _T_82 = and(_T_80, _T_81)
node _T_83 = eq(_T_82, UInt<1>(0h0))
node _T_84 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_85 = cvt(_T_84)
node _T_86 = and(_T_85, asSInt(UInt<1>(0h0)))
node _T_87 = asSInt(_T_86)
node _T_88 = eq(_T_87, asSInt(UInt<1>(0h0)))
node _T_89 = or(_T_83, _T_88)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 2, 0)
node _T_90 = shr(io.in.a.bits.source, 3)
node _T_91 = eq(_T_90, UInt<1>(0h0))
node _T_92 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_93 = and(_T_91, _T_92)
node _T_94 = leq(uncommonBits_6, UInt<3>(0h7))
node _T_95 = and(_T_93, _T_94)
node _T_96 = eq(_T_95, UInt<1>(0h0))
node _T_97 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_98 = cvt(_T_97)
node _T_99 = and(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = asSInt(_T_99)
node _T_101 = eq(_T_100, asSInt(UInt<1>(0h0)))
node _T_102 = or(_T_96, _T_101)
node _T_103 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_104 = eq(_T_103, UInt<1>(0h0))
node _T_105 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_106 = cvt(_T_105)
node _T_107 = and(_T_106, asSInt(UInt<1>(0h0)))
node _T_108 = asSInt(_T_107)
node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0)))
node _T_110 = or(_T_104, _T_109)
node _T_111 = and(_T_11, _T_24)
node _T_112 = and(_T_111, _T_37)
node _T_113 = and(_T_112, _T_50)
node _T_114 = and(_T_113, _T_63)
node _T_115 = and(_T_114, _T_76)
node _T_116 = and(_T_115, _T_89)
node _T_117 = and(_T_116, _T_102)
node _T_118 = and(_T_117, _T_110)
node _T_119 = asUInt(reset)
node _T_120 = eq(_T_119, UInt<1>(0h0))
when _T_120 :
node _T_121 = eq(_T_118, UInt<1>(0h0))
when _T_121 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_118, UInt<1>(0h1), "") : assert_1
node _T_122 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_122 :
node _T_123 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_124 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_125 = and(_T_123, _T_124)
node _T_126 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_127 = shr(io.in.a.bits.source, 2)
node _T_128 = eq(_T_127, UInt<4>(0h8))
node _T_129 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_130 = and(_T_128, _T_129)
node _T_131 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_132 = and(_T_130, _T_131)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_133 = shr(io.in.a.bits.source, 2)
node _T_134 = eq(_T_133, UInt<4>(0h9))
node _T_135 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_136 = and(_T_134, _T_135)
node _T_137 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_138 = and(_T_136, _T_137)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_139 = shr(io.in.a.bits.source, 2)
node _T_140 = eq(_T_139, UInt<4>(0ha))
node _T_141 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_142 = and(_T_140, _T_141)
node _T_143 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_144 = and(_T_142, _T_143)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0)
node _T_145 = shr(io.in.a.bits.source, 2)
node _T_146 = eq(_T_145, UInt<4>(0hb))
node _T_147 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_148 = and(_T_146, _T_147)
node _T_149 = leq(uncommonBits_10, UInt<2>(0h3))
node _T_150 = and(_T_148, _T_149)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 2, 0)
node _T_151 = shr(io.in.a.bits.source, 3)
node _T_152 = eq(_T_151, UInt<2>(0h2))
node _T_153 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_154 = and(_T_152, _T_153)
node _T_155 = leq(uncommonBits_11, UInt<3>(0h7))
node _T_156 = and(_T_154, _T_155)
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 2, 0)
node _T_157 = shr(io.in.a.bits.source, 3)
node _T_158 = eq(_T_157, UInt<1>(0h1))
node _T_159 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_160 = and(_T_158, _T_159)
node _T_161 = leq(uncommonBits_12, UInt<3>(0h7))
node _T_162 = and(_T_160, _T_161)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 2, 0)
node _T_163 = shr(io.in.a.bits.source, 3)
node _T_164 = eq(_T_163, UInt<1>(0h0))
node _T_165 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_166 = and(_T_164, _T_165)
node _T_167 = leq(uncommonBits_13, UInt<3>(0h7))
node _T_168 = and(_T_166, _T_167)
node _T_169 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_170 = or(_T_126, _T_132)
node _T_171 = or(_T_170, _T_138)
node _T_172 = or(_T_171, _T_144)
node _T_173 = or(_T_172, _T_150)
node _T_174 = or(_T_173, _T_156)
node _T_175 = or(_T_174, _T_162)
node _T_176 = or(_T_175, _T_168)
node _T_177 = or(_T_176, _T_169)
node _T_178 = and(_T_125, _T_177)
node _T_179 = or(UInt<1>(0h0), _T_178)
node _T_180 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_181 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_182 = cvt(_T_181)
node _T_183 = and(_T_182, asSInt(UInt<14>(0h2000)))
node _T_184 = asSInt(_T_183)
node _T_185 = eq(_T_184, asSInt(UInt<1>(0h0)))
node _T_186 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_187 = cvt(_T_186)
node _T_188 = and(_T_187, asSInt(UInt<13>(0h1000)))
node _T_189 = asSInt(_T_188)
node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0)))
node _T_191 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_192 = cvt(_T_191)
node _T_193 = and(_T_192, asSInt(UInt<17>(0h10000)))
node _T_194 = asSInt(_T_193)
node _T_195 = eq(_T_194, asSInt(UInt<1>(0h0)))
node _T_196 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_197 = cvt(_T_196)
node _T_198 = and(_T_197, asSInt(UInt<18>(0h2f000)))
node _T_199 = asSInt(_T_198)
node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0)))
node _T_201 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_202 = cvt(_T_201)
node _T_203 = and(_T_202, asSInt(UInt<17>(0h10000)))
node _T_204 = asSInt(_T_203)
node _T_205 = eq(_T_204, asSInt(UInt<1>(0h0)))
node _T_206 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_207 = cvt(_T_206)
node _T_208 = and(_T_207, asSInt(UInt<13>(0h1000)))
node _T_209 = asSInt(_T_208)
node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0)))
node _T_211 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_212 = cvt(_T_211)
node _T_213 = and(_T_212, asSInt(UInt<27>(0h4000000)))
node _T_214 = asSInt(_T_213)
node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0)))
node _T_216 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_217 = cvt(_T_216)
node _T_218 = and(_T_217, asSInt(UInt<13>(0h1000)))
node _T_219 = asSInt(_T_218)
node _T_220 = eq(_T_219, asSInt(UInt<1>(0h0)))
node _T_221 = or(_T_185, _T_190)
node _T_222 = or(_T_221, _T_195)
node _T_223 = or(_T_222, _T_200)
node _T_224 = or(_T_223, _T_205)
node _T_225 = or(_T_224, _T_210)
node _T_226 = or(_T_225, _T_215)
node _T_227 = or(_T_226, _T_220)
node _T_228 = and(_T_180, _T_227)
node _T_229 = or(UInt<1>(0h0), _T_228)
node _T_230 = and(_T_179, _T_229)
node _T_231 = asUInt(reset)
node _T_232 = eq(_T_231, UInt<1>(0h0))
when _T_232 :
node _T_233 = eq(_T_230, UInt<1>(0h0))
when _T_233 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_230, UInt<1>(0h1), "") : assert_2
node _T_234 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_235 = shr(io.in.a.bits.source, 2)
node _T_236 = eq(_T_235, UInt<4>(0h8))
node _T_237 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_238 = and(_T_236, _T_237)
node _T_239 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_240 = and(_T_238, _T_239)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_241 = shr(io.in.a.bits.source, 2)
node _T_242 = eq(_T_241, UInt<4>(0h9))
node _T_243 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_244 = and(_T_242, _T_243)
node _T_245 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_246 = and(_T_244, _T_245)
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0)
node _T_247 = shr(io.in.a.bits.source, 2)
node _T_248 = eq(_T_247, UInt<4>(0ha))
node _T_249 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_250 = and(_T_248, _T_249)
node _T_251 = leq(uncommonBits_16, UInt<2>(0h3))
node _T_252 = and(_T_250, _T_251)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0)
node _T_253 = shr(io.in.a.bits.source, 2)
node _T_254 = eq(_T_253, UInt<4>(0hb))
node _T_255 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_256 = and(_T_254, _T_255)
node _T_257 = leq(uncommonBits_17, UInt<2>(0h3))
node _T_258 = and(_T_256, _T_257)
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 2, 0)
node _T_259 = shr(io.in.a.bits.source, 3)
node _T_260 = eq(_T_259, UInt<2>(0h2))
node _T_261 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_262 = and(_T_260, _T_261)
node _T_263 = leq(uncommonBits_18, UInt<3>(0h7))
node _T_264 = and(_T_262, _T_263)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 2, 0)
node _T_265 = shr(io.in.a.bits.source, 3)
node _T_266 = eq(_T_265, UInt<1>(0h1))
node _T_267 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_268 = and(_T_266, _T_267)
node _T_269 = leq(uncommonBits_19, UInt<3>(0h7))
node _T_270 = and(_T_268, _T_269)
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 2, 0)
node _T_271 = shr(io.in.a.bits.source, 3)
node _T_272 = eq(_T_271, UInt<1>(0h0))
node _T_273 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_274 = and(_T_272, _T_273)
node _T_275 = leq(uncommonBits_20, UInt<3>(0h7))
node _T_276 = and(_T_274, _T_275)
node _T_277 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _WIRE : UInt<1>[9]
connect _WIRE[0], _T_234
connect _WIRE[1], _T_240
connect _WIRE[2], _T_246
connect _WIRE[3], _T_252
connect _WIRE[4], _T_258
connect _WIRE[5], _T_264
connect _WIRE[6], _T_270
connect _WIRE[7], _T_276
connect _WIRE[8], _T_277
node _T_278 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_279 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_280 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_281 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_282 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_283 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_284 = mux(_WIRE[5], _T_278, UInt<1>(0h0))
node _T_285 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_286 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_287 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_288 = or(_T_279, _T_280)
node _T_289 = or(_T_288, _T_281)
node _T_290 = or(_T_289, _T_282)
node _T_291 = or(_T_290, _T_283)
node _T_292 = or(_T_291, _T_284)
node _T_293 = or(_T_292, _T_285)
node _T_294 = or(_T_293, _T_286)
node _T_295 = or(_T_294, _T_287)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_295
node _T_296 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_297 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_298 = and(_T_296, _T_297)
node _T_299 = or(UInt<1>(0h0), _T_298)
node _T_300 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_301 = cvt(_T_300)
node _T_302 = and(_T_301, asSInt(UInt<14>(0h2000)))
node _T_303 = asSInt(_T_302)
node _T_304 = eq(_T_303, asSInt(UInt<1>(0h0)))
node _T_305 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_306 = cvt(_T_305)
node _T_307 = and(_T_306, asSInt(UInt<13>(0h1000)))
node _T_308 = asSInt(_T_307)
node _T_309 = eq(_T_308, asSInt(UInt<1>(0h0)))
node _T_310 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_311 = cvt(_T_310)
node _T_312 = and(_T_311, asSInt(UInt<17>(0h10000)))
node _T_313 = asSInt(_T_312)
node _T_314 = eq(_T_313, asSInt(UInt<1>(0h0)))
node _T_315 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_316 = cvt(_T_315)
node _T_317 = and(_T_316, asSInt(UInt<18>(0h2f000)))
node _T_318 = asSInt(_T_317)
node _T_319 = eq(_T_318, asSInt(UInt<1>(0h0)))
node _T_320 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_321 = cvt(_T_320)
node _T_322 = and(_T_321, asSInt(UInt<17>(0h10000)))
node _T_323 = asSInt(_T_322)
node _T_324 = eq(_T_323, asSInt(UInt<1>(0h0)))
node _T_325 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_326 = cvt(_T_325)
node _T_327 = and(_T_326, asSInt(UInt<13>(0h1000)))
node _T_328 = asSInt(_T_327)
node _T_329 = eq(_T_328, asSInt(UInt<1>(0h0)))
node _T_330 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_331 = cvt(_T_330)
node _T_332 = and(_T_331, asSInt(UInt<27>(0h4000000)))
node _T_333 = asSInt(_T_332)
node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0)))
node _T_335 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_336 = cvt(_T_335)
node _T_337 = and(_T_336, asSInt(UInt<13>(0h1000)))
node _T_338 = asSInt(_T_337)
node _T_339 = eq(_T_338, asSInt(UInt<1>(0h0)))
node _T_340 = or(_T_304, _T_309)
node _T_341 = or(_T_340, _T_314)
node _T_342 = or(_T_341, _T_319)
node _T_343 = or(_T_342, _T_324)
node _T_344 = or(_T_343, _T_329)
node _T_345 = or(_T_344, _T_334)
node _T_346 = or(_T_345, _T_339)
node _T_347 = and(_T_299, _T_346)
node _T_348 = or(UInt<1>(0h0), _T_347)
node _T_349 = and(_WIRE_1, _T_348)
node _T_350 = asUInt(reset)
node _T_351 = eq(_T_350, UInt<1>(0h0))
when _T_351 :
node _T_352 = eq(_T_349, UInt<1>(0h0))
when _T_352 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_349, UInt<1>(0h1), "") : assert_3
node _T_353 = asUInt(reset)
node _T_354 = eq(_T_353, UInt<1>(0h0))
when _T_354 :
node _T_355 = eq(source_ok, UInt<1>(0h0))
when _T_355 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_356 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_357 = asUInt(reset)
node _T_358 = eq(_T_357, UInt<1>(0h0))
when _T_358 :
node _T_359 = eq(_T_356, UInt<1>(0h0))
when _T_359 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_356, UInt<1>(0h1), "") : assert_5
node _T_360 = asUInt(reset)
node _T_361 = eq(_T_360, UInt<1>(0h0))
when _T_361 :
node _T_362 = eq(is_aligned, UInt<1>(0h0))
when _T_362 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_363 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_364 = asUInt(reset)
node _T_365 = eq(_T_364, UInt<1>(0h0))
when _T_365 :
node _T_366 = eq(_T_363, UInt<1>(0h0))
when _T_366 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_363, UInt<1>(0h1), "") : assert_7
node _T_367 = not(io.in.a.bits.mask)
node _T_368 = eq(_T_367, UInt<1>(0h0))
node _T_369 = asUInt(reset)
node _T_370 = eq(_T_369, UInt<1>(0h0))
when _T_370 :
node _T_371 = eq(_T_368, UInt<1>(0h0))
when _T_371 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_368, UInt<1>(0h1), "") : assert_8
node _T_372 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_373 = asUInt(reset)
node _T_374 = eq(_T_373, UInt<1>(0h0))
when _T_374 :
node _T_375 = eq(_T_372, UInt<1>(0h0))
when _T_375 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_372, UInt<1>(0h1), "") : assert_9
node _T_376 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_376 :
node _T_377 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_378 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_379 = and(_T_377, _T_378)
node _T_380 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_381 = shr(io.in.a.bits.source, 2)
node _T_382 = eq(_T_381, UInt<4>(0h8))
node _T_383 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_384 = and(_T_382, _T_383)
node _T_385 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_386 = and(_T_384, _T_385)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0)
node _T_387 = shr(io.in.a.bits.source, 2)
node _T_388 = eq(_T_387, UInt<4>(0h9))
node _T_389 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_390 = and(_T_388, _T_389)
node _T_391 = leq(uncommonBits_22, UInt<2>(0h3))
node _T_392 = and(_T_390, _T_391)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0)
node _T_393 = shr(io.in.a.bits.source, 2)
node _T_394 = eq(_T_393, UInt<4>(0ha))
node _T_395 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_396 = and(_T_394, _T_395)
node _T_397 = leq(uncommonBits_23, UInt<2>(0h3))
node _T_398 = and(_T_396, _T_397)
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_399 = shr(io.in.a.bits.source, 2)
node _T_400 = eq(_T_399, UInt<4>(0hb))
node _T_401 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_402 = and(_T_400, _T_401)
node _T_403 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_404 = and(_T_402, _T_403)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 2, 0)
node _T_405 = shr(io.in.a.bits.source, 3)
node _T_406 = eq(_T_405, UInt<2>(0h2))
node _T_407 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_408 = and(_T_406, _T_407)
node _T_409 = leq(uncommonBits_25, UInt<3>(0h7))
node _T_410 = and(_T_408, _T_409)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 2, 0)
node _T_411 = shr(io.in.a.bits.source, 3)
node _T_412 = eq(_T_411, UInt<1>(0h1))
node _T_413 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_414 = and(_T_412, _T_413)
node _T_415 = leq(uncommonBits_26, UInt<3>(0h7))
node _T_416 = and(_T_414, _T_415)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 2, 0)
node _T_417 = shr(io.in.a.bits.source, 3)
node _T_418 = eq(_T_417, UInt<1>(0h0))
node _T_419 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_420 = and(_T_418, _T_419)
node _T_421 = leq(uncommonBits_27, UInt<3>(0h7))
node _T_422 = and(_T_420, _T_421)
node _T_423 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_424 = or(_T_380, _T_386)
node _T_425 = or(_T_424, _T_392)
node _T_426 = or(_T_425, _T_398)
node _T_427 = or(_T_426, _T_404)
node _T_428 = or(_T_427, _T_410)
node _T_429 = or(_T_428, _T_416)
node _T_430 = or(_T_429, _T_422)
node _T_431 = or(_T_430, _T_423)
node _T_432 = and(_T_379, _T_431)
node _T_433 = or(UInt<1>(0h0), _T_432)
node _T_434 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_435 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_436 = cvt(_T_435)
node _T_437 = and(_T_436, asSInt(UInt<14>(0h2000)))
node _T_438 = asSInt(_T_437)
node _T_439 = eq(_T_438, asSInt(UInt<1>(0h0)))
node _T_440 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_441 = cvt(_T_440)
node _T_442 = and(_T_441, asSInt(UInt<13>(0h1000)))
node _T_443 = asSInt(_T_442)
node _T_444 = eq(_T_443, asSInt(UInt<1>(0h0)))
node _T_445 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_446 = cvt(_T_445)
node _T_447 = and(_T_446, asSInt(UInt<17>(0h10000)))
node _T_448 = asSInt(_T_447)
node _T_449 = eq(_T_448, asSInt(UInt<1>(0h0)))
node _T_450 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_451 = cvt(_T_450)
node _T_452 = and(_T_451, asSInt(UInt<18>(0h2f000)))
node _T_453 = asSInt(_T_452)
node _T_454 = eq(_T_453, asSInt(UInt<1>(0h0)))
node _T_455 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_456 = cvt(_T_455)
node _T_457 = and(_T_456, asSInt(UInt<17>(0h10000)))
node _T_458 = asSInt(_T_457)
node _T_459 = eq(_T_458, asSInt(UInt<1>(0h0)))
node _T_460 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_461 = cvt(_T_460)
node _T_462 = and(_T_461, asSInt(UInt<13>(0h1000)))
node _T_463 = asSInt(_T_462)
node _T_464 = eq(_T_463, asSInt(UInt<1>(0h0)))
node _T_465 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_466 = cvt(_T_465)
node _T_467 = and(_T_466, asSInt(UInt<27>(0h4000000)))
node _T_468 = asSInt(_T_467)
node _T_469 = eq(_T_468, asSInt(UInt<1>(0h0)))
node _T_470 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_471 = cvt(_T_470)
node _T_472 = and(_T_471, asSInt(UInt<13>(0h1000)))
node _T_473 = asSInt(_T_472)
node _T_474 = eq(_T_473, asSInt(UInt<1>(0h0)))
node _T_475 = or(_T_439, _T_444)
node _T_476 = or(_T_475, _T_449)
node _T_477 = or(_T_476, _T_454)
node _T_478 = or(_T_477, _T_459)
node _T_479 = or(_T_478, _T_464)
node _T_480 = or(_T_479, _T_469)
node _T_481 = or(_T_480, _T_474)
node _T_482 = and(_T_434, _T_481)
node _T_483 = or(UInt<1>(0h0), _T_482)
node _T_484 = and(_T_433, _T_483)
node _T_485 = asUInt(reset)
node _T_486 = eq(_T_485, UInt<1>(0h0))
when _T_486 :
node _T_487 = eq(_T_484, UInt<1>(0h0))
when _T_487 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_484, UInt<1>(0h1), "") : assert_10
node _T_488 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0)
node _T_489 = shr(io.in.a.bits.source, 2)
node _T_490 = eq(_T_489, UInt<4>(0h8))
node _T_491 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_492 = and(_T_490, _T_491)
node _T_493 = leq(uncommonBits_28, UInt<2>(0h3))
node _T_494 = and(_T_492, _T_493)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0)
node _T_495 = shr(io.in.a.bits.source, 2)
node _T_496 = eq(_T_495, UInt<4>(0h9))
node _T_497 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_498 = and(_T_496, _T_497)
node _T_499 = leq(uncommonBits_29, UInt<2>(0h3))
node _T_500 = and(_T_498, _T_499)
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_501 = shr(io.in.a.bits.source, 2)
node _T_502 = eq(_T_501, UInt<4>(0ha))
node _T_503 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_504 = and(_T_502, _T_503)
node _T_505 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_506 = and(_T_504, _T_505)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_507 = shr(io.in.a.bits.source, 2)
node _T_508 = eq(_T_507, UInt<4>(0hb))
node _T_509 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_510 = and(_T_508, _T_509)
node _T_511 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_512 = and(_T_510, _T_511)
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 2, 0)
node _T_513 = shr(io.in.a.bits.source, 3)
node _T_514 = eq(_T_513, UInt<2>(0h2))
node _T_515 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_516 = and(_T_514, _T_515)
node _T_517 = leq(uncommonBits_32, UInt<3>(0h7))
node _T_518 = and(_T_516, _T_517)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 2, 0)
node _T_519 = shr(io.in.a.bits.source, 3)
node _T_520 = eq(_T_519, UInt<1>(0h1))
node _T_521 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_522 = and(_T_520, _T_521)
node _T_523 = leq(uncommonBits_33, UInt<3>(0h7))
node _T_524 = and(_T_522, _T_523)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 2, 0)
node _T_525 = shr(io.in.a.bits.source, 3)
node _T_526 = eq(_T_525, UInt<1>(0h0))
node _T_527 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_528 = and(_T_526, _T_527)
node _T_529 = leq(uncommonBits_34, UInt<3>(0h7))
node _T_530 = and(_T_528, _T_529)
node _T_531 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _WIRE_2 : UInt<1>[9]
connect _WIRE_2[0], _T_488
connect _WIRE_2[1], _T_494
connect _WIRE_2[2], _T_500
connect _WIRE_2[3], _T_506
connect _WIRE_2[4], _T_512
connect _WIRE_2[5], _T_518
connect _WIRE_2[6], _T_524
connect _WIRE_2[7], _T_530
connect _WIRE_2[8], _T_531
node _T_532 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_533 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_534 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_535 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_536 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_537 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_538 = mux(_WIRE_2[5], _T_532, UInt<1>(0h0))
node _T_539 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_540 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_541 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_542 = or(_T_533, _T_534)
node _T_543 = or(_T_542, _T_535)
node _T_544 = or(_T_543, _T_536)
node _T_545 = or(_T_544, _T_537)
node _T_546 = or(_T_545, _T_538)
node _T_547 = or(_T_546, _T_539)
node _T_548 = or(_T_547, _T_540)
node _T_549 = or(_T_548, _T_541)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_549
node _T_550 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_551 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_552 = and(_T_550, _T_551)
node _T_553 = or(UInt<1>(0h0), _T_552)
node _T_554 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_555 = cvt(_T_554)
node _T_556 = and(_T_555, asSInt(UInt<14>(0h2000)))
node _T_557 = asSInt(_T_556)
node _T_558 = eq(_T_557, asSInt(UInt<1>(0h0)))
node _T_559 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_560 = cvt(_T_559)
node _T_561 = and(_T_560, asSInt(UInt<13>(0h1000)))
node _T_562 = asSInt(_T_561)
node _T_563 = eq(_T_562, asSInt(UInt<1>(0h0)))
node _T_564 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_565 = cvt(_T_564)
node _T_566 = and(_T_565, asSInt(UInt<17>(0h10000)))
node _T_567 = asSInt(_T_566)
node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0)))
node _T_569 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_570 = cvt(_T_569)
node _T_571 = and(_T_570, asSInt(UInt<18>(0h2f000)))
node _T_572 = asSInt(_T_571)
node _T_573 = eq(_T_572, asSInt(UInt<1>(0h0)))
node _T_574 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_575 = cvt(_T_574)
node _T_576 = and(_T_575, asSInt(UInt<17>(0h10000)))
node _T_577 = asSInt(_T_576)
node _T_578 = eq(_T_577, asSInt(UInt<1>(0h0)))
node _T_579 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_580 = cvt(_T_579)
node _T_581 = and(_T_580, asSInt(UInt<13>(0h1000)))
node _T_582 = asSInt(_T_581)
node _T_583 = eq(_T_582, asSInt(UInt<1>(0h0)))
node _T_584 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_585 = cvt(_T_584)
node _T_586 = and(_T_585, asSInt(UInt<27>(0h4000000)))
node _T_587 = asSInt(_T_586)
node _T_588 = eq(_T_587, asSInt(UInt<1>(0h0)))
node _T_589 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_590 = cvt(_T_589)
node _T_591 = and(_T_590, asSInt(UInt<13>(0h1000)))
node _T_592 = asSInt(_T_591)
node _T_593 = eq(_T_592, asSInt(UInt<1>(0h0)))
node _T_594 = or(_T_558, _T_563)
node _T_595 = or(_T_594, _T_568)
node _T_596 = or(_T_595, _T_573)
node _T_597 = or(_T_596, _T_578)
node _T_598 = or(_T_597, _T_583)
node _T_599 = or(_T_598, _T_588)
node _T_600 = or(_T_599, _T_593)
node _T_601 = and(_T_553, _T_600)
node _T_602 = or(UInt<1>(0h0), _T_601)
node _T_603 = and(_WIRE_3, _T_602)
node _T_604 = asUInt(reset)
node _T_605 = eq(_T_604, UInt<1>(0h0))
when _T_605 :
node _T_606 = eq(_T_603, UInt<1>(0h0))
when _T_606 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_603, UInt<1>(0h1), "") : assert_11
node _T_607 = asUInt(reset)
node _T_608 = eq(_T_607, UInt<1>(0h0))
when _T_608 :
node _T_609 = eq(source_ok, UInt<1>(0h0))
when _T_609 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_610 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_611 = asUInt(reset)
node _T_612 = eq(_T_611, UInt<1>(0h0))
when _T_612 :
node _T_613 = eq(_T_610, UInt<1>(0h0))
when _T_613 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_610, UInt<1>(0h1), "") : assert_13
node _T_614 = asUInt(reset)
node _T_615 = eq(_T_614, UInt<1>(0h0))
when _T_615 :
node _T_616 = eq(is_aligned, UInt<1>(0h0))
when _T_616 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_617 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_618 = asUInt(reset)
node _T_619 = eq(_T_618, UInt<1>(0h0))
when _T_619 :
node _T_620 = eq(_T_617, UInt<1>(0h0))
when _T_620 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_617, UInt<1>(0h1), "") : assert_15
node _T_621 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_622 = asUInt(reset)
node _T_623 = eq(_T_622, UInt<1>(0h0))
when _T_623 :
node _T_624 = eq(_T_621, UInt<1>(0h0))
when _T_624 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_621, UInt<1>(0h1), "") : assert_16
node _T_625 = not(io.in.a.bits.mask)
node _T_626 = eq(_T_625, UInt<1>(0h0))
node _T_627 = asUInt(reset)
node _T_628 = eq(_T_627, UInt<1>(0h0))
when _T_628 :
node _T_629 = eq(_T_626, UInt<1>(0h0))
when _T_629 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_626, UInt<1>(0h1), "") : assert_17
node _T_630 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_631 = asUInt(reset)
node _T_632 = eq(_T_631, UInt<1>(0h0))
when _T_632 :
node _T_633 = eq(_T_630, UInt<1>(0h0))
when _T_633 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_630, UInt<1>(0h1), "") : assert_18
node _T_634 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_634 :
node _T_635 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_636 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_637 = and(_T_635, _T_636)
node _T_638 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0)
node _T_639 = shr(io.in.a.bits.source, 2)
node _T_640 = eq(_T_639, UInt<4>(0h8))
node _T_641 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_642 = and(_T_640, _T_641)
node _T_643 = leq(uncommonBits_35, UInt<2>(0h3))
node _T_644 = and(_T_642, _T_643)
node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0)
node _T_645 = shr(io.in.a.bits.source, 2)
node _T_646 = eq(_T_645, UInt<4>(0h9))
node _T_647 = leq(UInt<1>(0h0), uncommonBits_36)
node _T_648 = and(_T_646, _T_647)
node _T_649 = leq(uncommonBits_36, UInt<2>(0h3))
node _T_650 = and(_T_648, _T_649)
node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0)
node _T_651 = shr(io.in.a.bits.source, 2)
node _T_652 = eq(_T_651, UInt<4>(0ha))
node _T_653 = leq(UInt<1>(0h0), uncommonBits_37)
node _T_654 = and(_T_652, _T_653)
node _T_655 = leq(uncommonBits_37, UInt<2>(0h3))
node _T_656 = and(_T_654, _T_655)
node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0)
node _T_657 = shr(io.in.a.bits.source, 2)
node _T_658 = eq(_T_657, UInt<4>(0hb))
node _T_659 = leq(UInt<1>(0h0), uncommonBits_38)
node _T_660 = and(_T_658, _T_659)
node _T_661 = leq(uncommonBits_38, UInt<2>(0h3))
node _T_662 = and(_T_660, _T_661)
node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_39 = bits(_uncommonBits_T_39, 2, 0)
node _T_663 = shr(io.in.a.bits.source, 3)
node _T_664 = eq(_T_663, UInt<2>(0h2))
node _T_665 = leq(UInt<1>(0h0), uncommonBits_39)
node _T_666 = and(_T_664, _T_665)
node _T_667 = leq(uncommonBits_39, UInt<3>(0h7))
node _T_668 = and(_T_666, _T_667)
node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_40 = bits(_uncommonBits_T_40, 2, 0)
node _T_669 = shr(io.in.a.bits.source, 3)
node _T_670 = eq(_T_669, UInt<1>(0h1))
node _T_671 = leq(UInt<1>(0h0), uncommonBits_40)
node _T_672 = and(_T_670, _T_671)
node _T_673 = leq(uncommonBits_40, UInt<3>(0h7))
node _T_674 = and(_T_672, _T_673)
node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_41 = bits(_uncommonBits_T_41, 2, 0)
node _T_675 = shr(io.in.a.bits.source, 3)
node _T_676 = eq(_T_675, UInt<1>(0h0))
node _T_677 = leq(UInt<1>(0h0), uncommonBits_41)
node _T_678 = and(_T_676, _T_677)
node _T_679 = leq(uncommonBits_41, UInt<3>(0h7))
node _T_680 = and(_T_678, _T_679)
node _T_681 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_682 = or(_T_638, _T_644)
node _T_683 = or(_T_682, _T_650)
node _T_684 = or(_T_683, _T_656)
node _T_685 = or(_T_684, _T_662)
node _T_686 = or(_T_685, _T_668)
node _T_687 = or(_T_686, _T_674)
node _T_688 = or(_T_687, _T_680)
node _T_689 = or(_T_688, _T_681)
node _T_690 = and(_T_637, _T_689)
node _T_691 = or(UInt<1>(0h0), _T_690)
node _T_692 = asUInt(reset)
node _T_693 = eq(_T_692, UInt<1>(0h0))
when _T_693 :
node _T_694 = eq(_T_691, UInt<1>(0h0))
when _T_694 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_691, UInt<1>(0h1), "") : assert_19
node _T_695 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_696 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_697 = and(_T_695, _T_696)
node _T_698 = or(UInt<1>(0h0), _T_697)
node _T_699 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_700 = cvt(_T_699)
node _T_701 = and(_T_700, asSInt(UInt<13>(0h1000)))
node _T_702 = asSInt(_T_701)
node _T_703 = eq(_T_702, asSInt(UInt<1>(0h0)))
node _T_704 = and(_T_698, _T_703)
node _T_705 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_706 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_707 = and(_T_705, _T_706)
node _T_708 = or(UInt<1>(0h0), _T_707)
node _T_709 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_710 = cvt(_T_709)
node _T_711 = and(_T_710, asSInt(UInt<14>(0h2000)))
node _T_712 = asSInt(_T_711)
node _T_713 = eq(_T_712, asSInt(UInt<1>(0h0)))
node _T_714 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_715 = cvt(_T_714)
node _T_716 = and(_T_715, asSInt(UInt<17>(0h10000)))
node _T_717 = asSInt(_T_716)
node _T_718 = eq(_T_717, asSInt(UInt<1>(0h0)))
node _T_719 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_720 = cvt(_T_719)
node _T_721 = and(_T_720, asSInt(UInt<18>(0h2f000)))
node _T_722 = asSInt(_T_721)
node _T_723 = eq(_T_722, asSInt(UInt<1>(0h0)))
node _T_724 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_725 = cvt(_T_724)
node _T_726 = and(_T_725, asSInt(UInt<17>(0h10000)))
node _T_727 = asSInt(_T_726)
node _T_728 = eq(_T_727, asSInt(UInt<1>(0h0)))
node _T_729 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_730 = cvt(_T_729)
node _T_731 = and(_T_730, asSInt(UInt<13>(0h1000)))
node _T_732 = asSInt(_T_731)
node _T_733 = eq(_T_732, asSInt(UInt<1>(0h0)))
node _T_734 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_735 = cvt(_T_734)
node _T_736 = and(_T_735, asSInt(UInt<27>(0h4000000)))
node _T_737 = asSInt(_T_736)
node _T_738 = eq(_T_737, asSInt(UInt<1>(0h0)))
node _T_739 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_740 = cvt(_T_739)
node _T_741 = and(_T_740, asSInt(UInt<13>(0h1000)))
node _T_742 = asSInt(_T_741)
node _T_743 = eq(_T_742, asSInt(UInt<1>(0h0)))
node _T_744 = or(_T_713, _T_718)
node _T_745 = or(_T_744, _T_723)
node _T_746 = or(_T_745, _T_728)
node _T_747 = or(_T_746, _T_733)
node _T_748 = or(_T_747, _T_738)
node _T_749 = or(_T_748, _T_743)
node _T_750 = and(_T_708, _T_749)
node _T_751 = or(UInt<1>(0h0), _T_704)
node _T_752 = or(_T_751, _T_750)
node _T_753 = asUInt(reset)
node _T_754 = eq(_T_753, UInt<1>(0h0))
when _T_754 :
node _T_755 = eq(_T_752, UInt<1>(0h0))
when _T_755 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_752, UInt<1>(0h1), "") : assert_20
node _T_756 = asUInt(reset)
node _T_757 = eq(_T_756, UInt<1>(0h0))
when _T_757 :
node _T_758 = eq(source_ok, UInt<1>(0h0))
when _T_758 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_759 = asUInt(reset)
node _T_760 = eq(_T_759, UInt<1>(0h0))
when _T_760 :
node _T_761 = eq(is_aligned, UInt<1>(0h0))
when _T_761 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_762 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_763 = asUInt(reset)
node _T_764 = eq(_T_763, UInt<1>(0h0))
when _T_764 :
node _T_765 = eq(_T_762, UInt<1>(0h0))
when _T_765 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_762, UInt<1>(0h1), "") : assert_23
node _T_766 = eq(io.in.a.bits.mask, mask)
node _T_767 = asUInt(reset)
node _T_768 = eq(_T_767, UInt<1>(0h0))
when _T_768 :
node _T_769 = eq(_T_766, UInt<1>(0h0))
when _T_769 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_766, UInt<1>(0h1), "") : assert_24
node _T_770 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_771 = asUInt(reset)
node _T_772 = eq(_T_771, UInt<1>(0h0))
when _T_772 :
node _T_773 = eq(_T_770, UInt<1>(0h0))
when _T_773 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_770, UInt<1>(0h1), "") : assert_25
node _T_774 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_774 :
node _T_775 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_776 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_777 = and(_T_775, _T_776)
node _T_778 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0)
node _T_779 = shr(io.in.a.bits.source, 2)
node _T_780 = eq(_T_779, UInt<4>(0h8))
node _T_781 = leq(UInt<1>(0h0), uncommonBits_42)
node _T_782 = and(_T_780, _T_781)
node _T_783 = leq(uncommonBits_42, UInt<2>(0h3))
node _T_784 = and(_T_782, _T_783)
node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0)
node _T_785 = shr(io.in.a.bits.source, 2)
node _T_786 = eq(_T_785, UInt<4>(0h9))
node _T_787 = leq(UInt<1>(0h0), uncommonBits_43)
node _T_788 = and(_T_786, _T_787)
node _T_789 = leq(uncommonBits_43, UInt<2>(0h3))
node _T_790 = and(_T_788, _T_789)
node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0)
node _T_791 = shr(io.in.a.bits.source, 2)
node _T_792 = eq(_T_791, UInt<4>(0ha))
node _T_793 = leq(UInt<1>(0h0), uncommonBits_44)
node _T_794 = and(_T_792, _T_793)
node _T_795 = leq(uncommonBits_44, UInt<2>(0h3))
node _T_796 = and(_T_794, _T_795)
node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0)
node _T_797 = shr(io.in.a.bits.source, 2)
node _T_798 = eq(_T_797, UInt<4>(0hb))
node _T_799 = leq(UInt<1>(0h0), uncommonBits_45)
node _T_800 = and(_T_798, _T_799)
node _T_801 = leq(uncommonBits_45, UInt<2>(0h3))
node _T_802 = and(_T_800, _T_801)
node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_46 = bits(_uncommonBits_T_46, 2, 0)
node _T_803 = shr(io.in.a.bits.source, 3)
node _T_804 = eq(_T_803, UInt<2>(0h2))
node _T_805 = leq(UInt<1>(0h0), uncommonBits_46)
node _T_806 = and(_T_804, _T_805)
node _T_807 = leq(uncommonBits_46, UInt<3>(0h7))
node _T_808 = and(_T_806, _T_807)
node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_47 = bits(_uncommonBits_T_47, 2, 0)
node _T_809 = shr(io.in.a.bits.source, 3)
node _T_810 = eq(_T_809, UInt<1>(0h1))
node _T_811 = leq(UInt<1>(0h0), uncommonBits_47)
node _T_812 = and(_T_810, _T_811)
node _T_813 = leq(uncommonBits_47, UInt<3>(0h7))
node _T_814 = and(_T_812, _T_813)
node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_48 = bits(_uncommonBits_T_48, 2, 0)
node _T_815 = shr(io.in.a.bits.source, 3)
node _T_816 = eq(_T_815, UInt<1>(0h0))
node _T_817 = leq(UInt<1>(0h0), uncommonBits_48)
node _T_818 = and(_T_816, _T_817)
node _T_819 = leq(uncommonBits_48, UInt<3>(0h7))
node _T_820 = and(_T_818, _T_819)
node _T_821 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_822 = or(_T_778, _T_784)
node _T_823 = or(_T_822, _T_790)
node _T_824 = or(_T_823, _T_796)
node _T_825 = or(_T_824, _T_802)
node _T_826 = or(_T_825, _T_808)
node _T_827 = or(_T_826, _T_814)
node _T_828 = or(_T_827, _T_820)
node _T_829 = or(_T_828, _T_821)
node _T_830 = and(_T_777, _T_829)
node _T_831 = or(UInt<1>(0h0), _T_830)
node _T_832 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_833 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_834 = and(_T_832, _T_833)
node _T_835 = or(UInt<1>(0h0), _T_834)
node _T_836 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_837 = cvt(_T_836)
node _T_838 = and(_T_837, asSInt(UInt<13>(0h1000)))
node _T_839 = asSInt(_T_838)
node _T_840 = eq(_T_839, asSInt(UInt<1>(0h0)))
node _T_841 = and(_T_835, _T_840)
node _T_842 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_843 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_844 = and(_T_842, _T_843)
node _T_845 = or(UInt<1>(0h0), _T_844)
node _T_846 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_847 = cvt(_T_846)
node _T_848 = and(_T_847, asSInt(UInt<14>(0h2000)))
node _T_849 = asSInt(_T_848)
node _T_850 = eq(_T_849, asSInt(UInt<1>(0h0)))
node _T_851 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_852 = cvt(_T_851)
node _T_853 = and(_T_852, asSInt(UInt<18>(0h2f000)))
node _T_854 = asSInt(_T_853)
node _T_855 = eq(_T_854, asSInt(UInt<1>(0h0)))
node _T_856 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_857 = cvt(_T_856)
node _T_858 = and(_T_857, asSInt(UInt<17>(0h10000)))
node _T_859 = asSInt(_T_858)
node _T_860 = eq(_T_859, asSInt(UInt<1>(0h0)))
node _T_861 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_862 = cvt(_T_861)
node _T_863 = and(_T_862, asSInt(UInt<13>(0h1000)))
node _T_864 = asSInt(_T_863)
node _T_865 = eq(_T_864, asSInt(UInt<1>(0h0)))
node _T_866 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_867 = cvt(_T_866)
node _T_868 = and(_T_867, asSInt(UInt<27>(0h4000000)))
node _T_869 = asSInt(_T_868)
node _T_870 = eq(_T_869, asSInt(UInt<1>(0h0)))
node _T_871 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_872 = cvt(_T_871)
node _T_873 = and(_T_872, asSInt(UInt<13>(0h1000)))
node _T_874 = asSInt(_T_873)
node _T_875 = eq(_T_874, asSInt(UInt<1>(0h0)))
node _T_876 = or(_T_850, _T_855)
node _T_877 = or(_T_876, _T_860)
node _T_878 = or(_T_877, _T_865)
node _T_879 = or(_T_878, _T_870)
node _T_880 = or(_T_879, _T_875)
node _T_881 = and(_T_845, _T_880)
node _T_882 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_883 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_884 = cvt(_T_883)
node _T_885 = and(_T_884, asSInt(UInt<17>(0h10000)))
node _T_886 = asSInt(_T_885)
node _T_887 = eq(_T_886, asSInt(UInt<1>(0h0)))
node _T_888 = and(_T_882, _T_887)
node _T_889 = or(UInt<1>(0h0), _T_841)
node _T_890 = or(_T_889, _T_881)
node _T_891 = or(_T_890, _T_888)
node _T_892 = and(_T_831, _T_891)
node _T_893 = asUInt(reset)
node _T_894 = eq(_T_893, UInt<1>(0h0))
when _T_894 :
node _T_895 = eq(_T_892, UInt<1>(0h0))
when _T_895 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_892, UInt<1>(0h1), "") : assert_26
node _T_896 = asUInt(reset)
node _T_897 = eq(_T_896, UInt<1>(0h0))
when _T_897 :
node _T_898 = eq(source_ok, UInt<1>(0h0))
when _T_898 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_899 = asUInt(reset)
node _T_900 = eq(_T_899, UInt<1>(0h0))
when _T_900 :
node _T_901 = eq(is_aligned, UInt<1>(0h0))
when _T_901 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_902 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_903 = asUInt(reset)
node _T_904 = eq(_T_903, UInt<1>(0h0))
when _T_904 :
node _T_905 = eq(_T_902, UInt<1>(0h0))
when _T_905 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_902, UInt<1>(0h1), "") : assert_29
node _T_906 = eq(io.in.a.bits.mask, mask)
node _T_907 = asUInt(reset)
node _T_908 = eq(_T_907, UInt<1>(0h0))
when _T_908 :
node _T_909 = eq(_T_906, UInt<1>(0h0))
when _T_909 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_906, UInt<1>(0h1), "") : assert_30
node _T_910 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_910 :
node _T_911 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_912 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_913 = and(_T_911, _T_912)
node _T_914 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0)
node _T_915 = shr(io.in.a.bits.source, 2)
node _T_916 = eq(_T_915, UInt<4>(0h8))
node _T_917 = leq(UInt<1>(0h0), uncommonBits_49)
node _T_918 = and(_T_916, _T_917)
node _T_919 = leq(uncommonBits_49, UInt<2>(0h3))
node _T_920 = and(_T_918, _T_919)
node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0)
node _T_921 = shr(io.in.a.bits.source, 2)
node _T_922 = eq(_T_921, UInt<4>(0h9))
node _T_923 = leq(UInt<1>(0h0), uncommonBits_50)
node _T_924 = and(_T_922, _T_923)
node _T_925 = leq(uncommonBits_50, UInt<2>(0h3))
node _T_926 = and(_T_924, _T_925)
node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0)
node _T_927 = shr(io.in.a.bits.source, 2)
node _T_928 = eq(_T_927, UInt<4>(0ha))
node _T_929 = leq(UInt<1>(0h0), uncommonBits_51)
node _T_930 = and(_T_928, _T_929)
node _T_931 = leq(uncommonBits_51, UInt<2>(0h3))
node _T_932 = and(_T_930, _T_931)
node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_52 = bits(_uncommonBits_T_52, 1, 0)
node _T_933 = shr(io.in.a.bits.source, 2)
node _T_934 = eq(_T_933, UInt<4>(0hb))
node _T_935 = leq(UInt<1>(0h0), uncommonBits_52)
node _T_936 = and(_T_934, _T_935)
node _T_937 = leq(uncommonBits_52, UInt<2>(0h3))
node _T_938 = and(_T_936, _T_937)
node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_53 = bits(_uncommonBits_T_53, 2, 0)
node _T_939 = shr(io.in.a.bits.source, 3)
node _T_940 = eq(_T_939, UInt<2>(0h2))
node _T_941 = leq(UInt<1>(0h0), uncommonBits_53)
node _T_942 = and(_T_940, _T_941)
node _T_943 = leq(uncommonBits_53, UInt<3>(0h7))
node _T_944 = and(_T_942, _T_943)
node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_54 = bits(_uncommonBits_T_54, 2, 0)
node _T_945 = shr(io.in.a.bits.source, 3)
node _T_946 = eq(_T_945, UInt<1>(0h1))
node _T_947 = leq(UInt<1>(0h0), uncommonBits_54)
node _T_948 = and(_T_946, _T_947)
node _T_949 = leq(uncommonBits_54, UInt<3>(0h7))
node _T_950 = and(_T_948, _T_949)
node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_55 = bits(_uncommonBits_T_55, 2, 0)
node _T_951 = shr(io.in.a.bits.source, 3)
node _T_952 = eq(_T_951, UInt<1>(0h0))
node _T_953 = leq(UInt<1>(0h0), uncommonBits_55)
node _T_954 = and(_T_952, _T_953)
node _T_955 = leq(uncommonBits_55, UInt<3>(0h7))
node _T_956 = and(_T_954, _T_955)
node _T_957 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_958 = or(_T_914, _T_920)
node _T_959 = or(_T_958, _T_926)
node _T_960 = or(_T_959, _T_932)
node _T_961 = or(_T_960, _T_938)
node _T_962 = or(_T_961, _T_944)
node _T_963 = or(_T_962, _T_950)
node _T_964 = or(_T_963, _T_956)
node _T_965 = or(_T_964, _T_957)
node _T_966 = and(_T_913, _T_965)
node _T_967 = or(UInt<1>(0h0), _T_966)
node _T_968 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_969 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_970 = and(_T_968, _T_969)
node _T_971 = or(UInt<1>(0h0), _T_970)
node _T_972 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_973 = cvt(_T_972)
node _T_974 = and(_T_973, asSInt(UInt<13>(0h1000)))
node _T_975 = asSInt(_T_974)
node _T_976 = eq(_T_975, asSInt(UInt<1>(0h0)))
node _T_977 = and(_T_971, _T_976)
node _T_978 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_979 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_980 = and(_T_978, _T_979)
node _T_981 = or(UInt<1>(0h0), _T_980)
node _T_982 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_983 = cvt(_T_982)
node _T_984 = and(_T_983, asSInt(UInt<14>(0h2000)))
node _T_985 = asSInt(_T_984)
node _T_986 = eq(_T_985, asSInt(UInt<1>(0h0)))
node _T_987 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_988 = cvt(_T_987)
node _T_989 = and(_T_988, asSInt(UInt<18>(0h2f000)))
node _T_990 = asSInt(_T_989)
node _T_991 = eq(_T_990, asSInt(UInt<1>(0h0)))
node _T_992 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_993 = cvt(_T_992)
node _T_994 = and(_T_993, asSInt(UInt<17>(0h10000)))
node _T_995 = asSInt(_T_994)
node _T_996 = eq(_T_995, asSInt(UInt<1>(0h0)))
node _T_997 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_998 = cvt(_T_997)
node _T_999 = and(_T_998, asSInt(UInt<13>(0h1000)))
node _T_1000 = asSInt(_T_999)
node _T_1001 = eq(_T_1000, asSInt(UInt<1>(0h0)))
node _T_1002 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1003 = cvt(_T_1002)
node _T_1004 = and(_T_1003, asSInt(UInt<27>(0h4000000)))
node _T_1005 = asSInt(_T_1004)
node _T_1006 = eq(_T_1005, asSInt(UInt<1>(0h0)))
node _T_1007 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1008 = cvt(_T_1007)
node _T_1009 = and(_T_1008, asSInt(UInt<13>(0h1000)))
node _T_1010 = asSInt(_T_1009)
node _T_1011 = eq(_T_1010, asSInt(UInt<1>(0h0)))
node _T_1012 = or(_T_986, _T_991)
node _T_1013 = or(_T_1012, _T_996)
node _T_1014 = or(_T_1013, _T_1001)
node _T_1015 = or(_T_1014, _T_1006)
node _T_1016 = or(_T_1015, _T_1011)
node _T_1017 = and(_T_981, _T_1016)
node _T_1018 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1019 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1020 = cvt(_T_1019)
node _T_1021 = and(_T_1020, asSInt(UInt<17>(0h10000)))
node _T_1022 = asSInt(_T_1021)
node _T_1023 = eq(_T_1022, asSInt(UInt<1>(0h0)))
node _T_1024 = and(_T_1018, _T_1023)
node _T_1025 = or(UInt<1>(0h0), _T_977)
node _T_1026 = or(_T_1025, _T_1017)
node _T_1027 = or(_T_1026, _T_1024)
node _T_1028 = and(_T_967, _T_1027)
node _T_1029 = asUInt(reset)
node _T_1030 = eq(_T_1029, UInt<1>(0h0))
when _T_1030 :
node _T_1031 = eq(_T_1028, UInt<1>(0h0))
when _T_1031 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_1028, UInt<1>(0h1), "") : assert_31
node _T_1032 = asUInt(reset)
node _T_1033 = eq(_T_1032, UInt<1>(0h0))
when _T_1033 :
node _T_1034 = eq(source_ok, UInt<1>(0h0))
when _T_1034 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_1035 = asUInt(reset)
node _T_1036 = eq(_T_1035, UInt<1>(0h0))
when _T_1036 :
node _T_1037 = eq(is_aligned, UInt<1>(0h0))
when _T_1037 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_1038 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_1039 = asUInt(reset)
node _T_1040 = eq(_T_1039, UInt<1>(0h0))
when _T_1040 :
node _T_1041 = eq(_T_1038, UInt<1>(0h0))
when _T_1041 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_1038, UInt<1>(0h1), "") : assert_34
node _T_1042 = not(mask)
node _T_1043 = and(io.in.a.bits.mask, _T_1042)
node _T_1044 = eq(_T_1043, UInt<1>(0h0))
node _T_1045 = asUInt(reset)
node _T_1046 = eq(_T_1045, UInt<1>(0h0))
when _T_1046 :
node _T_1047 = eq(_T_1044, UInt<1>(0h0))
when _T_1047 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_1044, UInt<1>(0h1), "") : assert_35
node _T_1048 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_1048 :
node _T_1049 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1050 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1051 = and(_T_1049, _T_1050)
node _T_1052 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0)
node _T_1053 = shr(io.in.a.bits.source, 2)
node _T_1054 = eq(_T_1053, UInt<4>(0h8))
node _T_1055 = leq(UInt<1>(0h0), uncommonBits_56)
node _T_1056 = and(_T_1054, _T_1055)
node _T_1057 = leq(uncommonBits_56, UInt<2>(0h3))
node _T_1058 = and(_T_1056, _T_1057)
node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0)
node _T_1059 = shr(io.in.a.bits.source, 2)
node _T_1060 = eq(_T_1059, UInt<4>(0h9))
node _T_1061 = leq(UInt<1>(0h0), uncommonBits_57)
node _T_1062 = and(_T_1060, _T_1061)
node _T_1063 = leq(uncommonBits_57, UInt<2>(0h3))
node _T_1064 = and(_T_1062, _T_1063)
node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_58 = bits(_uncommonBits_T_58, 1, 0)
node _T_1065 = shr(io.in.a.bits.source, 2)
node _T_1066 = eq(_T_1065, UInt<4>(0ha))
node _T_1067 = leq(UInt<1>(0h0), uncommonBits_58)
node _T_1068 = and(_T_1066, _T_1067)
node _T_1069 = leq(uncommonBits_58, UInt<2>(0h3))
node _T_1070 = and(_T_1068, _T_1069)
node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_59 = bits(_uncommonBits_T_59, 1, 0)
node _T_1071 = shr(io.in.a.bits.source, 2)
node _T_1072 = eq(_T_1071, UInt<4>(0hb))
node _T_1073 = leq(UInt<1>(0h0), uncommonBits_59)
node _T_1074 = and(_T_1072, _T_1073)
node _T_1075 = leq(uncommonBits_59, UInt<2>(0h3))
node _T_1076 = and(_T_1074, _T_1075)
node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_60 = bits(_uncommonBits_T_60, 2, 0)
node _T_1077 = shr(io.in.a.bits.source, 3)
node _T_1078 = eq(_T_1077, UInt<2>(0h2))
node _T_1079 = leq(UInt<1>(0h0), uncommonBits_60)
node _T_1080 = and(_T_1078, _T_1079)
node _T_1081 = leq(uncommonBits_60, UInt<3>(0h7))
node _T_1082 = and(_T_1080, _T_1081)
node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_61 = bits(_uncommonBits_T_61, 2, 0)
node _T_1083 = shr(io.in.a.bits.source, 3)
node _T_1084 = eq(_T_1083, UInt<1>(0h1))
node _T_1085 = leq(UInt<1>(0h0), uncommonBits_61)
node _T_1086 = and(_T_1084, _T_1085)
node _T_1087 = leq(uncommonBits_61, UInt<3>(0h7))
node _T_1088 = and(_T_1086, _T_1087)
node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_62 = bits(_uncommonBits_T_62, 2, 0)
node _T_1089 = shr(io.in.a.bits.source, 3)
node _T_1090 = eq(_T_1089, UInt<1>(0h0))
node _T_1091 = leq(UInt<1>(0h0), uncommonBits_62)
node _T_1092 = and(_T_1090, _T_1091)
node _T_1093 = leq(uncommonBits_62, UInt<3>(0h7))
node _T_1094 = and(_T_1092, _T_1093)
node _T_1095 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_1096 = or(_T_1052, _T_1058)
node _T_1097 = or(_T_1096, _T_1064)
node _T_1098 = or(_T_1097, _T_1070)
node _T_1099 = or(_T_1098, _T_1076)
node _T_1100 = or(_T_1099, _T_1082)
node _T_1101 = or(_T_1100, _T_1088)
node _T_1102 = or(_T_1101, _T_1094)
node _T_1103 = or(_T_1102, _T_1095)
node _T_1104 = and(_T_1051, _T_1103)
node _T_1105 = or(UInt<1>(0h0), _T_1104)
node _T_1106 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1107 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_1108 = and(_T_1106, _T_1107)
node _T_1109 = or(UInt<1>(0h0), _T_1108)
node _T_1110 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_1111 = cvt(_T_1110)
node _T_1112 = and(_T_1111, asSInt(UInt<15>(0h5000)))
node _T_1113 = asSInt(_T_1112)
node _T_1114 = eq(_T_1113, asSInt(UInt<1>(0h0)))
node _T_1115 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1116 = cvt(_T_1115)
node _T_1117 = and(_T_1116, asSInt(UInt<13>(0h1000)))
node _T_1118 = asSInt(_T_1117)
node _T_1119 = eq(_T_1118, asSInt(UInt<1>(0h0)))
node _T_1120 = or(_T_1114, _T_1119)
node _T_1121 = and(_T_1109, _T_1120)
node _T_1122 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1123 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1124 = cvt(_T_1123)
node _T_1125 = and(_T_1124, asSInt(UInt<13>(0h1000)))
node _T_1126 = asSInt(_T_1125)
node _T_1127 = eq(_T_1126, asSInt(UInt<1>(0h0)))
node _T_1128 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1129 = cvt(_T_1128)
node _T_1130 = and(_T_1129, asSInt(UInt<17>(0h10000)))
node _T_1131 = asSInt(_T_1130)
node _T_1132 = eq(_T_1131, asSInt(UInt<1>(0h0)))
node _T_1133 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1134 = cvt(_T_1133)
node _T_1135 = and(_T_1134, asSInt(UInt<18>(0h2f000)))
node _T_1136 = asSInt(_T_1135)
node _T_1137 = eq(_T_1136, asSInt(UInt<1>(0h0)))
node _T_1138 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1139 = cvt(_T_1138)
node _T_1140 = and(_T_1139, asSInt(UInt<17>(0h10000)))
node _T_1141 = asSInt(_T_1140)
node _T_1142 = eq(_T_1141, asSInt(UInt<1>(0h0)))
node _T_1143 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1144 = cvt(_T_1143)
node _T_1145 = and(_T_1144, asSInt(UInt<13>(0h1000)))
node _T_1146 = asSInt(_T_1145)
node _T_1147 = eq(_T_1146, asSInt(UInt<1>(0h0)))
node _T_1148 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1149 = cvt(_T_1148)
node _T_1150 = and(_T_1149, asSInt(UInt<27>(0h4000000)))
node _T_1151 = asSInt(_T_1150)
node _T_1152 = eq(_T_1151, asSInt(UInt<1>(0h0)))
node _T_1153 = or(_T_1127, _T_1132)
node _T_1154 = or(_T_1153, _T_1137)
node _T_1155 = or(_T_1154, _T_1142)
node _T_1156 = or(_T_1155, _T_1147)
node _T_1157 = or(_T_1156, _T_1152)
node _T_1158 = and(_T_1122, _T_1157)
node _T_1159 = or(UInt<1>(0h0), _T_1121)
node _T_1160 = or(_T_1159, _T_1158)
node _T_1161 = and(_T_1105, _T_1160)
node _T_1162 = asUInt(reset)
node _T_1163 = eq(_T_1162, UInt<1>(0h0))
when _T_1163 :
node _T_1164 = eq(_T_1161, UInt<1>(0h0))
when _T_1164 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_1161, UInt<1>(0h1), "") : assert_36
node _T_1165 = asUInt(reset)
node _T_1166 = eq(_T_1165, UInt<1>(0h0))
when _T_1166 :
node _T_1167 = eq(source_ok, UInt<1>(0h0))
when _T_1167 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_1168 = asUInt(reset)
node _T_1169 = eq(_T_1168, UInt<1>(0h0))
when _T_1169 :
node _T_1170 = eq(is_aligned, UInt<1>(0h0))
when _T_1170 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_1171 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_1172 = asUInt(reset)
node _T_1173 = eq(_T_1172, UInt<1>(0h0))
when _T_1173 :
node _T_1174 = eq(_T_1171, UInt<1>(0h0))
when _T_1174 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_1171, UInt<1>(0h1), "") : assert_39
node _T_1175 = eq(io.in.a.bits.mask, mask)
node _T_1176 = asUInt(reset)
node _T_1177 = eq(_T_1176, UInt<1>(0h0))
when _T_1177 :
node _T_1178 = eq(_T_1175, UInt<1>(0h0))
when _T_1178 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_1175, UInt<1>(0h1), "") : assert_40
node _T_1179 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_1179 :
node _T_1180 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1181 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1182 = and(_T_1180, _T_1181)
node _T_1183 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0)
node _T_1184 = shr(io.in.a.bits.source, 2)
node _T_1185 = eq(_T_1184, UInt<4>(0h8))
node _T_1186 = leq(UInt<1>(0h0), uncommonBits_63)
node _T_1187 = and(_T_1185, _T_1186)
node _T_1188 = leq(uncommonBits_63, UInt<2>(0h3))
node _T_1189 = and(_T_1187, _T_1188)
node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_64 = bits(_uncommonBits_T_64, 1, 0)
node _T_1190 = shr(io.in.a.bits.source, 2)
node _T_1191 = eq(_T_1190, UInt<4>(0h9))
node _T_1192 = leq(UInt<1>(0h0), uncommonBits_64)
node _T_1193 = and(_T_1191, _T_1192)
node _T_1194 = leq(uncommonBits_64, UInt<2>(0h3))
node _T_1195 = and(_T_1193, _T_1194)
node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_65 = bits(_uncommonBits_T_65, 1, 0)
node _T_1196 = shr(io.in.a.bits.source, 2)
node _T_1197 = eq(_T_1196, UInt<4>(0ha))
node _T_1198 = leq(UInt<1>(0h0), uncommonBits_65)
node _T_1199 = and(_T_1197, _T_1198)
node _T_1200 = leq(uncommonBits_65, UInt<2>(0h3))
node _T_1201 = and(_T_1199, _T_1200)
node _uncommonBits_T_66 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_66 = bits(_uncommonBits_T_66, 1, 0)
node _T_1202 = shr(io.in.a.bits.source, 2)
node _T_1203 = eq(_T_1202, UInt<4>(0hb))
node _T_1204 = leq(UInt<1>(0h0), uncommonBits_66)
node _T_1205 = and(_T_1203, _T_1204)
node _T_1206 = leq(uncommonBits_66, UInt<2>(0h3))
node _T_1207 = and(_T_1205, _T_1206)
node _uncommonBits_T_67 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_67 = bits(_uncommonBits_T_67, 2, 0)
node _T_1208 = shr(io.in.a.bits.source, 3)
node _T_1209 = eq(_T_1208, UInt<2>(0h2))
node _T_1210 = leq(UInt<1>(0h0), uncommonBits_67)
node _T_1211 = and(_T_1209, _T_1210)
node _T_1212 = leq(uncommonBits_67, UInt<3>(0h7))
node _T_1213 = and(_T_1211, _T_1212)
node _uncommonBits_T_68 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_68 = bits(_uncommonBits_T_68, 2, 0)
node _T_1214 = shr(io.in.a.bits.source, 3)
node _T_1215 = eq(_T_1214, UInt<1>(0h1))
node _T_1216 = leq(UInt<1>(0h0), uncommonBits_68)
node _T_1217 = and(_T_1215, _T_1216)
node _T_1218 = leq(uncommonBits_68, UInt<3>(0h7))
node _T_1219 = and(_T_1217, _T_1218)
node _uncommonBits_T_69 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_69 = bits(_uncommonBits_T_69, 2, 0)
node _T_1220 = shr(io.in.a.bits.source, 3)
node _T_1221 = eq(_T_1220, UInt<1>(0h0))
node _T_1222 = leq(UInt<1>(0h0), uncommonBits_69)
node _T_1223 = and(_T_1221, _T_1222)
node _T_1224 = leq(uncommonBits_69, UInt<3>(0h7))
node _T_1225 = and(_T_1223, _T_1224)
node _T_1226 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_1227 = or(_T_1183, _T_1189)
node _T_1228 = or(_T_1227, _T_1195)
node _T_1229 = or(_T_1228, _T_1201)
node _T_1230 = or(_T_1229, _T_1207)
node _T_1231 = or(_T_1230, _T_1213)
node _T_1232 = or(_T_1231, _T_1219)
node _T_1233 = or(_T_1232, _T_1225)
node _T_1234 = or(_T_1233, _T_1226)
node _T_1235 = and(_T_1182, _T_1234)
node _T_1236 = or(UInt<1>(0h0), _T_1235)
node _T_1237 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1238 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_1239 = and(_T_1237, _T_1238)
node _T_1240 = or(UInt<1>(0h0), _T_1239)
node _T_1241 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_1242 = cvt(_T_1241)
node _T_1243 = and(_T_1242, asSInt(UInt<15>(0h5000)))
node _T_1244 = asSInt(_T_1243)
node _T_1245 = eq(_T_1244, asSInt(UInt<1>(0h0)))
node _T_1246 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1247 = cvt(_T_1246)
node _T_1248 = and(_T_1247, asSInt(UInt<13>(0h1000)))
node _T_1249 = asSInt(_T_1248)
node _T_1250 = eq(_T_1249, asSInt(UInt<1>(0h0)))
node _T_1251 = or(_T_1245, _T_1250)
node _T_1252 = and(_T_1240, _T_1251)
node _T_1253 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1254 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1255 = cvt(_T_1254)
node _T_1256 = and(_T_1255, asSInt(UInt<13>(0h1000)))
node _T_1257 = asSInt(_T_1256)
node _T_1258 = eq(_T_1257, asSInt(UInt<1>(0h0)))
node _T_1259 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1260 = cvt(_T_1259)
node _T_1261 = and(_T_1260, asSInt(UInt<17>(0h10000)))
node _T_1262 = asSInt(_T_1261)
node _T_1263 = eq(_T_1262, asSInt(UInt<1>(0h0)))
node _T_1264 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1265 = cvt(_T_1264)
node _T_1266 = and(_T_1265, asSInt(UInt<18>(0h2f000)))
node _T_1267 = asSInt(_T_1266)
node _T_1268 = eq(_T_1267, asSInt(UInt<1>(0h0)))
node _T_1269 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1270 = cvt(_T_1269)
node _T_1271 = and(_T_1270, asSInt(UInt<17>(0h10000)))
node _T_1272 = asSInt(_T_1271)
node _T_1273 = eq(_T_1272, asSInt(UInt<1>(0h0)))
node _T_1274 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1275 = cvt(_T_1274)
node _T_1276 = and(_T_1275, asSInt(UInt<13>(0h1000)))
node _T_1277 = asSInt(_T_1276)
node _T_1278 = eq(_T_1277, asSInt(UInt<1>(0h0)))
node _T_1279 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1280 = cvt(_T_1279)
node _T_1281 = and(_T_1280, asSInt(UInt<27>(0h4000000)))
node _T_1282 = asSInt(_T_1281)
node _T_1283 = eq(_T_1282, asSInt(UInt<1>(0h0)))
node _T_1284 = or(_T_1258, _T_1263)
node _T_1285 = or(_T_1284, _T_1268)
node _T_1286 = or(_T_1285, _T_1273)
node _T_1287 = or(_T_1286, _T_1278)
node _T_1288 = or(_T_1287, _T_1283)
node _T_1289 = and(_T_1253, _T_1288)
node _T_1290 = or(UInt<1>(0h0), _T_1252)
node _T_1291 = or(_T_1290, _T_1289)
node _T_1292 = and(_T_1236, _T_1291)
node _T_1293 = asUInt(reset)
node _T_1294 = eq(_T_1293, UInt<1>(0h0))
when _T_1294 :
node _T_1295 = eq(_T_1292, UInt<1>(0h0))
when _T_1295 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_1292, UInt<1>(0h1), "") : assert_41
node _T_1296 = asUInt(reset)
node _T_1297 = eq(_T_1296, UInt<1>(0h0))
when _T_1297 :
node _T_1298 = eq(source_ok, UInt<1>(0h0))
when _T_1298 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_1299 = asUInt(reset)
node _T_1300 = eq(_T_1299, UInt<1>(0h0))
when _T_1300 :
node _T_1301 = eq(is_aligned, UInt<1>(0h0))
when _T_1301 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_1302 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_1303 = asUInt(reset)
node _T_1304 = eq(_T_1303, UInt<1>(0h0))
when _T_1304 :
node _T_1305 = eq(_T_1302, UInt<1>(0h0))
when _T_1305 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_1302, UInt<1>(0h1), "") : assert_44
node _T_1306 = eq(io.in.a.bits.mask, mask)
node _T_1307 = asUInt(reset)
node _T_1308 = eq(_T_1307, UInt<1>(0h0))
when _T_1308 :
node _T_1309 = eq(_T_1306, UInt<1>(0h0))
when _T_1309 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_1306, UInt<1>(0h1), "") : assert_45
node _T_1310 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_1310 :
node _T_1311 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1312 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1313 = and(_T_1311, _T_1312)
node _T_1314 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _uncommonBits_T_70 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_70 = bits(_uncommonBits_T_70, 1, 0)
node _T_1315 = shr(io.in.a.bits.source, 2)
node _T_1316 = eq(_T_1315, UInt<4>(0h8))
node _T_1317 = leq(UInt<1>(0h0), uncommonBits_70)
node _T_1318 = and(_T_1316, _T_1317)
node _T_1319 = leq(uncommonBits_70, UInt<2>(0h3))
node _T_1320 = and(_T_1318, _T_1319)
node _uncommonBits_T_71 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_71 = bits(_uncommonBits_T_71, 1, 0)
node _T_1321 = shr(io.in.a.bits.source, 2)
node _T_1322 = eq(_T_1321, UInt<4>(0h9))
node _T_1323 = leq(UInt<1>(0h0), uncommonBits_71)
node _T_1324 = and(_T_1322, _T_1323)
node _T_1325 = leq(uncommonBits_71, UInt<2>(0h3))
node _T_1326 = and(_T_1324, _T_1325)
node _uncommonBits_T_72 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_72 = bits(_uncommonBits_T_72, 1, 0)
node _T_1327 = shr(io.in.a.bits.source, 2)
node _T_1328 = eq(_T_1327, UInt<4>(0ha))
node _T_1329 = leq(UInt<1>(0h0), uncommonBits_72)
node _T_1330 = and(_T_1328, _T_1329)
node _T_1331 = leq(uncommonBits_72, UInt<2>(0h3))
node _T_1332 = and(_T_1330, _T_1331)
node _uncommonBits_T_73 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_73 = bits(_uncommonBits_T_73, 1, 0)
node _T_1333 = shr(io.in.a.bits.source, 2)
node _T_1334 = eq(_T_1333, UInt<4>(0hb))
node _T_1335 = leq(UInt<1>(0h0), uncommonBits_73)
node _T_1336 = and(_T_1334, _T_1335)
node _T_1337 = leq(uncommonBits_73, UInt<2>(0h3))
node _T_1338 = and(_T_1336, _T_1337)
node _uncommonBits_T_74 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_74 = bits(_uncommonBits_T_74, 2, 0)
node _T_1339 = shr(io.in.a.bits.source, 3)
node _T_1340 = eq(_T_1339, UInt<2>(0h2))
node _T_1341 = leq(UInt<1>(0h0), uncommonBits_74)
node _T_1342 = and(_T_1340, _T_1341)
node _T_1343 = leq(uncommonBits_74, UInt<3>(0h7))
node _T_1344 = and(_T_1342, _T_1343)
node _uncommonBits_T_75 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_75 = bits(_uncommonBits_T_75, 2, 0)
node _T_1345 = shr(io.in.a.bits.source, 3)
node _T_1346 = eq(_T_1345, UInt<1>(0h1))
node _T_1347 = leq(UInt<1>(0h0), uncommonBits_75)
node _T_1348 = and(_T_1346, _T_1347)
node _T_1349 = leq(uncommonBits_75, UInt<3>(0h7))
node _T_1350 = and(_T_1348, _T_1349)
node _uncommonBits_T_76 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_76 = bits(_uncommonBits_T_76, 2, 0)
node _T_1351 = shr(io.in.a.bits.source, 3)
node _T_1352 = eq(_T_1351, UInt<1>(0h0))
node _T_1353 = leq(UInt<1>(0h0), uncommonBits_76)
node _T_1354 = and(_T_1352, _T_1353)
node _T_1355 = leq(uncommonBits_76, UInt<3>(0h7))
node _T_1356 = and(_T_1354, _T_1355)
node _T_1357 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_1358 = or(_T_1314, _T_1320)
node _T_1359 = or(_T_1358, _T_1326)
node _T_1360 = or(_T_1359, _T_1332)
node _T_1361 = or(_T_1360, _T_1338)
node _T_1362 = or(_T_1361, _T_1344)
node _T_1363 = or(_T_1362, _T_1350)
node _T_1364 = or(_T_1363, _T_1356)
node _T_1365 = or(_T_1364, _T_1357)
node _T_1366 = and(_T_1313, _T_1365)
node _T_1367 = or(UInt<1>(0h0), _T_1366)
node _T_1368 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1369 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1370 = and(_T_1368, _T_1369)
node _T_1371 = or(UInt<1>(0h0), _T_1370)
node _T_1372 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_1373 = cvt(_T_1372)
node _T_1374 = and(_T_1373, asSInt(UInt<13>(0h1000)))
node _T_1375 = asSInt(_T_1374)
node _T_1376 = eq(_T_1375, asSInt(UInt<1>(0h0)))
node _T_1377 = and(_T_1371, _T_1376)
node _T_1378 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1379 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1380 = cvt(_T_1379)
node _T_1381 = and(_T_1380, asSInt(UInt<14>(0h2000)))
node _T_1382 = asSInt(_T_1381)
node _T_1383 = eq(_T_1382, asSInt(UInt<1>(0h0)))
node _T_1384 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1385 = cvt(_T_1384)
node _T_1386 = and(_T_1385, asSInt(UInt<17>(0h10000)))
node _T_1387 = asSInt(_T_1386)
node _T_1388 = eq(_T_1387, asSInt(UInt<1>(0h0)))
node _T_1389 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1390 = cvt(_T_1389)
node _T_1391 = and(_T_1390, asSInt(UInt<18>(0h2f000)))
node _T_1392 = asSInt(_T_1391)
node _T_1393 = eq(_T_1392, asSInt(UInt<1>(0h0)))
node _T_1394 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1395 = cvt(_T_1394)
node _T_1396 = and(_T_1395, asSInt(UInt<17>(0h10000)))
node _T_1397 = asSInt(_T_1396)
node _T_1398 = eq(_T_1397, asSInt(UInt<1>(0h0)))
node _T_1399 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1400 = cvt(_T_1399)
node _T_1401 = and(_T_1400, asSInt(UInt<13>(0h1000)))
node _T_1402 = asSInt(_T_1401)
node _T_1403 = eq(_T_1402, asSInt(UInt<1>(0h0)))
node _T_1404 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1405 = cvt(_T_1404)
node _T_1406 = and(_T_1405, asSInt(UInt<27>(0h4000000)))
node _T_1407 = asSInt(_T_1406)
node _T_1408 = eq(_T_1407, asSInt(UInt<1>(0h0)))
node _T_1409 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1410 = cvt(_T_1409)
node _T_1411 = and(_T_1410, asSInt(UInt<13>(0h1000)))
node _T_1412 = asSInt(_T_1411)
node _T_1413 = eq(_T_1412, asSInt(UInt<1>(0h0)))
node _T_1414 = or(_T_1383, _T_1388)
node _T_1415 = or(_T_1414, _T_1393)
node _T_1416 = or(_T_1415, _T_1398)
node _T_1417 = or(_T_1416, _T_1403)
node _T_1418 = or(_T_1417, _T_1408)
node _T_1419 = or(_T_1418, _T_1413)
node _T_1420 = and(_T_1378, _T_1419)
node _T_1421 = or(UInt<1>(0h0), _T_1377)
node _T_1422 = or(_T_1421, _T_1420)
node _T_1423 = and(_T_1367, _T_1422)
node _T_1424 = asUInt(reset)
node _T_1425 = eq(_T_1424, UInt<1>(0h0))
when _T_1425 :
node _T_1426 = eq(_T_1423, UInt<1>(0h0))
when _T_1426 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_1423, UInt<1>(0h1), "") : assert_46
node _T_1427 = asUInt(reset)
node _T_1428 = eq(_T_1427, UInt<1>(0h0))
when _T_1428 :
node _T_1429 = eq(source_ok, UInt<1>(0h0))
when _T_1429 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_1430 = asUInt(reset)
node _T_1431 = eq(_T_1430, UInt<1>(0h0))
when _T_1431 :
node _T_1432 = eq(is_aligned, UInt<1>(0h0))
when _T_1432 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_1433 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_1434 = asUInt(reset)
node _T_1435 = eq(_T_1434, UInt<1>(0h0))
when _T_1435 :
node _T_1436 = eq(_T_1433, UInt<1>(0h0))
when _T_1436 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_1433, UInt<1>(0h1), "") : assert_49
node _T_1437 = eq(io.in.a.bits.mask, mask)
node _T_1438 = asUInt(reset)
node _T_1439 = eq(_T_1438, UInt<1>(0h0))
when _T_1439 :
node _T_1440 = eq(_T_1437, UInt<1>(0h0))
when _T_1440 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_1437, UInt<1>(0h1), "") : assert_50
node _T_1441 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1442 = asUInt(reset)
node _T_1443 = eq(_T_1442, UInt<1>(0h0))
when _T_1443 :
node _T_1444 = eq(_T_1441, UInt<1>(0h0))
when _T_1444 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_1441, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_1445 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1446 = asUInt(reset)
node _T_1447 = eq(_T_1446, UInt<1>(0h0))
when _T_1447 :
node _T_1448 = eq(_T_1445, UInt<1>(0h0))
when _T_1448 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_1445, UInt<1>(0h1), "") : assert_52
node _source_ok_T_51 = eq(io.in.d.bits.source, UInt<6>(0h30))
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_52 = shr(io.in.d.bits.source, 2)
node _source_ok_T_53 = eq(_source_ok_T_52, UInt<4>(0h8))
node _source_ok_T_54 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_55 = and(_source_ok_T_53, _source_ok_T_54)
node _source_ok_T_56 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_57 = and(_source_ok_T_55, _source_ok_T_56)
node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0)
node _source_ok_T_58 = shr(io.in.d.bits.source, 2)
node _source_ok_T_59 = eq(_source_ok_T_58, UInt<4>(0h9))
node _source_ok_T_60 = leq(UInt<1>(0h0), source_ok_uncommonBits_8)
node _source_ok_T_61 = and(_source_ok_T_59, _source_ok_T_60)
node _source_ok_T_62 = leq(source_ok_uncommonBits_8, UInt<2>(0h3))
node _source_ok_T_63 = and(_source_ok_T_61, _source_ok_T_62)
node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0)
node _source_ok_T_64 = shr(io.in.d.bits.source, 2)
node _source_ok_T_65 = eq(_source_ok_T_64, UInt<4>(0ha))
node _source_ok_T_66 = leq(UInt<1>(0h0), source_ok_uncommonBits_9)
node _source_ok_T_67 = and(_source_ok_T_65, _source_ok_T_66)
node _source_ok_T_68 = leq(source_ok_uncommonBits_9, UInt<2>(0h3))
node _source_ok_T_69 = and(_source_ok_T_67, _source_ok_T_68)
node _source_ok_uncommonBits_T_10 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 1, 0)
node _source_ok_T_70 = shr(io.in.d.bits.source, 2)
node _source_ok_T_71 = eq(_source_ok_T_70, UInt<4>(0hb))
node _source_ok_T_72 = leq(UInt<1>(0h0), source_ok_uncommonBits_10)
node _source_ok_T_73 = and(_source_ok_T_71, _source_ok_T_72)
node _source_ok_T_74 = leq(source_ok_uncommonBits_10, UInt<2>(0h3))
node _source_ok_T_75 = and(_source_ok_T_73, _source_ok_T_74)
node _source_ok_uncommonBits_T_11 = or(io.in.d.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 2, 0)
node _source_ok_T_76 = shr(io.in.d.bits.source, 3)
node _source_ok_T_77 = eq(_source_ok_T_76, UInt<2>(0h2))
node _source_ok_T_78 = leq(UInt<1>(0h0), source_ok_uncommonBits_11)
node _source_ok_T_79 = and(_source_ok_T_77, _source_ok_T_78)
node _source_ok_T_80 = leq(source_ok_uncommonBits_11, UInt<3>(0h7))
node _source_ok_T_81 = and(_source_ok_T_79, _source_ok_T_80)
node _source_ok_uncommonBits_T_12 = or(io.in.d.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_12 = bits(_source_ok_uncommonBits_T_12, 2, 0)
node _source_ok_T_82 = shr(io.in.d.bits.source, 3)
node _source_ok_T_83 = eq(_source_ok_T_82, UInt<1>(0h1))
node _source_ok_T_84 = leq(UInt<1>(0h0), source_ok_uncommonBits_12)
node _source_ok_T_85 = and(_source_ok_T_83, _source_ok_T_84)
node _source_ok_T_86 = leq(source_ok_uncommonBits_12, UInt<3>(0h7))
node _source_ok_T_87 = and(_source_ok_T_85, _source_ok_T_86)
node _source_ok_uncommonBits_T_13 = or(io.in.d.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_13 = bits(_source_ok_uncommonBits_T_13, 2, 0)
node _source_ok_T_88 = shr(io.in.d.bits.source, 3)
node _source_ok_T_89 = eq(_source_ok_T_88, UInt<1>(0h0))
node _source_ok_T_90 = leq(UInt<1>(0h0), source_ok_uncommonBits_13)
node _source_ok_T_91 = and(_source_ok_T_89, _source_ok_T_90)
node _source_ok_T_92 = leq(source_ok_uncommonBits_13, UInt<3>(0h7))
node _source_ok_T_93 = and(_source_ok_T_91, _source_ok_T_92)
node _source_ok_T_94 = eq(io.in.d.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE_1 : UInt<1>[9]
connect _source_ok_WIRE_1[0], _source_ok_T_51
connect _source_ok_WIRE_1[1], _source_ok_T_57
connect _source_ok_WIRE_1[2], _source_ok_T_63
connect _source_ok_WIRE_1[3], _source_ok_T_69
connect _source_ok_WIRE_1[4], _source_ok_T_75
connect _source_ok_WIRE_1[5], _source_ok_T_81
connect _source_ok_WIRE_1[6], _source_ok_T_87
connect _source_ok_WIRE_1[7], _source_ok_T_93
connect _source_ok_WIRE_1[8], _source_ok_T_94
node _source_ok_T_95 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_96 = or(_source_ok_T_95, _source_ok_WIRE_1[2])
node _source_ok_T_97 = or(_source_ok_T_96, _source_ok_WIRE_1[3])
node _source_ok_T_98 = or(_source_ok_T_97, _source_ok_WIRE_1[4])
node _source_ok_T_99 = or(_source_ok_T_98, _source_ok_WIRE_1[5])
node _source_ok_T_100 = or(_source_ok_T_99, _source_ok_WIRE_1[6])
node _source_ok_T_101 = or(_source_ok_T_100, _source_ok_WIRE_1[7])
node source_ok_1 = or(_source_ok_T_101, _source_ok_WIRE_1[8])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_1449 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1449 :
node _T_1450 = asUInt(reset)
node _T_1451 = eq(_T_1450, UInt<1>(0h0))
when _T_1451 :
node _T_1452 = eq(source_ok_1, UInt<1>(0h0))
when _T_1452 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_1453 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1454 = asUInt(reset)
node _T_1455 = eq(_T_1454, UInt<1>(0h0))
when _T_1455 :
node _T_1456 = eq(_T_1453, UInt<1>(0h0))
when _T_1456 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1453, UInt<1>(0h1), "") : assert_54
node _T_1457 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1458 = asUInt(reset)
node _T_1459 = eq(_T_1458, UInt<1>(0h0))
when _T_1459 :
node _T_1460 = eq(_T_1457, UInt<1>(0h0))
when _T_1460 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1457, UInt<1>(0h1), "") : assert_55
node _T_1461 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1462 = asUInt(reset)
node _T_1463 = eq(_T_1462, UInt<1>(0h0))
when _T_1463 :
node _T_1464 = eq(_T_1461, UInt<1>(0h0))
when _T_1464 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1461, UInt<1>(0h1), "") : assert_56
node _T_1465 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1466 = asUInt(reset)
node _T_1467 = eq(_T_1466, UInt<1>(0h0))
when _T_1467 :
node _T_1468 = eq(_T_1465, UInt<1>(0h0))
when _T_1468 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1465, UInt<1>(0h1), "") : assert_57
node _T_1469 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1469 :
node _T_1470 = asUInt(reset)
node _T_1471 = eq(_T_1470, UInt<1>(0h0))
when _T_1471 :
node _T_1472 = eq(source_ok_1, UInt<1>(0h0))
when _T_1472 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1473 = asUInt(reset)
node _T_1474 = eq(_T_1473, UInt<1>(0h0))
when _T_1474 :
node _T_1475 = eq(sink_ok, UInt<1>(0h0))
when _T_1475 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1476 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1477 = asUInt(reset)
node _T_1478 = eq(_T_1477, UInt<1>(0h0))
when _T_1478 :
node _T_1479 = eq(_T_1476, UInt<1>(0h0))
when _T_1479 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1476, UInt<1>(0h1), "") : assert_60
node _T_1480 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1481 = asUInt(reset)
node _T_1482 = eq(_T_1481, UInt<1>(0h0))
when _T_1482 :
node _T_1483 = eq(_T_1480, UInt<1>(0h0))
when _T_1483 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1480, UInt<1>(0h1), "") : assert_61
node _T_1484 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1485 = asUInt(reset)
node _T_1486 = eq(_T_1485, UInt<1>(0h0))
when _T_1486 :
node _T_1487 = eq(_T_1484, UInt<1>(0h0))
when _T_1487 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1484, UInt<1>(0h1), "") : assert_62
node _T_1488 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1489 = asUInt(reset)
node _T_1490 = eq(_T_1489, UInt<1>(0h0))
when _T_1490 :
node _T_1491 = eq(_T_1488, UInt<1>(0h0))
when _T_1491 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1488, UInt<1>(0h1), "") : assert_63
node _T_1492 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1493 = or(UInt<1>(0h1), _T_1492)
node _T_1494 = asUInt(reset)
node _T_1495 = eq(_T_1494, UInt<1>(0h0))
when _T_1495 :
node _T_1496 = eq(_T_1493, UInt<1>(0h0))
when _T_1496 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1493, UInt<1>(0h1), "") : assert_64
node _T_1497 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1497 :
node _T_1498 = asUInt(reset)
node _T_1499 = eq(_T_1498, UInt<1>(0h0))
when _T_1499 :
node _T_1500 = eq(source_ok_1, UInt<1>(0h0))
when _T_1500 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1501 = asUInt(reset)
node _T_1502 = eq(_T_1501, UInt<1>(0h0))
when _T_1502 :
node _T_1503 = eq(sink_ok, UInt<1>(0h0))
when _T_1503 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1504 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1505 = asUInt(reset)
node _T_1506 = eq(_T_1505, UInt<1>(0h0))
when _T_1506 :
node _T_1507 = eq(_T_1504, UInt<1>(0h0))
when _T_1507 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1504, UInt<1>(0h1), "") : assert_67
node _T_1508 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1509 = asUInt(reset)
node _T_1510 = eq(_T_1509, UInt<1>(0h0))
when _T_1510 :
node _T_1511 = eq(_T_1508, UInt<1>(0h0))
when _T_1511 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1508, UInt<1>(0h1), "") : assert_68
node _T_1512 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1513 = asUInt(reset)
node _T_1514 = eq(_T_1513, UInt<1>(0h0))
when _T_1514 :
node _T_1515 = eq(_T_1512, UInt<1>(0h0))
when _T_1515 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1512, UInt<1>(0h1), "") : assert_69
node _T_1516 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1517 = or(_T_1516, io.in.d.bits.corrupt)
node _T_1518 = asUInt(reset)
node _T_1519 = eq(_T_1518, UInt<1>(0h0))
when _T_1519 :
node _T_1520 = eq(_T_1517, UInt<1>(0h0))
when _T_1520 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1517, UInt<1>(0h1), "") : assert_70
node _T_1521 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1522 = or(UInt<1>(0h1), _T_1521)
node _T_1523 = asUInt(reset)
node _T_1524 = eq(_T_1523, UInt<1>(0h0))
when _T_1524 :
node _T_1525 = eq(_T_1522, UInt<1>(0h0))
when _T_1525 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1522, UInt<1>(0h1), "") : assert_71
node _T_1526 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1526 :
node _T_1527 = asUInt(reset)
node _T_1528 = eq(_T_1527, UInt<1>(0h0))
when _T_1528 :
node _T_1529 = eq(source_ok_1, UInt<1>(0h0))
when _T_1529 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1530 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1531 = asUInt(reset)
node _T_1532 = eq(_T_1531, UInt<1>(0h0))
when _T_1532 :
node _T_1533 = eq(_T_1530, UInt<1>(0h0))
when _T_1533 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1530, UInt<1>(0h1), "") : assert_73
node _T_1534 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1535 = asUInt(reset)
node _T_1536 = eq(_T_1535, UInt<1>(0h0))
when _T_1536 :
node _T_1537 = eq(_T_1534, UInt<1>(0h0))
when _T_1537 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1534, UInt<1>(0h1), "") : assert_74
node _T_1538 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1539 = or(UInt<1>(0h1), _T_1538)
node _T_1540 = asUInt(reset)
node _T_1541 = eq(_T_1540, UInt<1>(0h0))
when _T_1541 :
node _T_1542 = eq(_T_1539, UInt<1>(0h0))
when _T_1542 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1539, UInt<1>(0h1), "") : assert_75
node _T_1543 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1543 :
node _T_1544 = asUInt(reset)
node _T_1545 = eq(_T_1544, UInt<1>(0h0))
when _T_1545 :
node _T_1546 = eq(source_ok_1, UInt<1>(0h0))
when _T_1546 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1547 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1548 = asUInt(reset)
node _T_1549 = eq(_T_1548, UInt<1>(0h0))
when _T_1549 :
node _T_1550 = eq(_T_1547, UInt<1>(0h0))
when _T_1550 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1547, UInt<1>(0h1), "") : assert_77
node _T_1551 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1552 = or(_T_1551, io.in.d.bits.corrupt)
node _T_1553 = asUInt(reset)
node _T_1554 = eq(_T_1553, UInt<1>(0h0))
when _T_1554 :
node _T_1555 = eq(_T_1552, UInt<1>(0h0))
when _T_1555 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1552, UInt<1>(0h1), "") : assert_78
node _T_1556 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1557 = or(UInt<1>(0h1), _T_1556)
node _T_1558 = asUInt(reset)
node _T_1559 = eq(_T_1558, UInt<1>(0h0))
when _T_1559 :
node _T_1560 = eq(_T_1557, UInt<1>(0h0))
when _T_1560 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1557, UInt<1>(0h1), "") : assert_79
node _T_1561 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1561 :
node _T_1562 = asUInt(reset)
node _T_1563 = eq(_T_1562, UInt<1>(0h0))
when _T_1563 :
node _T_1564 = eq(source_ok_1, UInt<1>(0h0))
when _T_1564 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1565 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1566 = asUInt(reset)
node _T_1567 = eq(_T_1566, UInt<1>(0h0))
when _T_1567 :
node _T_1568 = eq(_T_1565, UInt<1>(0h0))
when _T_1568 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1565, UInt<1>(0h1), "") : assert_81
node _T_1569 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1570 = asUInt(reset)
node _T_1571 = eq(_T_1570, UInt<1>(0h0))
when _T_1571 :
node _T_1572 = eq(_T_1569, UInt<1>(0h0))
when _T_1572 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1569, UInt<1>(0h1), "") : assert_82
node _T_1573 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1574 = or(UInt<1>(0h1), _T_1573)
node _T_1575 = asUInt(reset)
node _T_1576 = eq(_T_1575, UInt<1>(0h0))
when _T_1576 :
node _T_1577 = eq(_T_1574, UInt<1>(0h0))
when _T_1577 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1574, UInt<1>(0h1), "") : assert_83
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.mask, UInt<8>(0h0)
connect _WIRE_4.bits.address, UInt<29>(0h0)
connect _WIRE_4.bits.source, UInt<7>(0h0)
connect _WIRE_4.bits.size, UInt<4>(0h0)
connect _WIRE_4.bits.param, UInt<2>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1578 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1579 = asUInt(reset)
node _T_1580 = eq(_T_1579, UInt<1>(0h0))
when _T_1580 :
node _T_1581 = eq(_T_1578, UInt<1>(0h0))
when _T_1581 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1578, UInt<1>(0h1), "") : assert_84
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<29>(0h0)
connect _WIRE_6.bits.source, UInt<7>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1582 = eq(_WIRE_7.valid, UInt<1>(0h0))
node _T_1583 = asUInt(reset)
node _T_1584 = eq(_T_1583, UInt<1>(0h0))
when _T_1584 :
node _T_1585 = eq(_T_1582, UInt<1>(0h0))
when _T_1585 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1582, UInt<1>(0h1), "") : assert_85
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_8.bits.sink, UInt<1>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1586 = eq(_WIRE_9.valid, UInt<1>(0h0))
node _T_1587 = asUInt(reset)
node _T_1588 = eq(_T_1587, UInt<1>(0h0))
when _T_1588 :
node _T_1589 = eq(_T_1586, UInt<1>(0h0))
when _T_1589 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1586, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1590 = eq(a_first, UInt<1>(0h0))
node _T_1591 = and(io.in.a.valid, _T_1590)
when _T_1591 :
node _T_1592 = eq(io.in.a.bits.opcode, opcode)
node _T_1593 = asUInt(reset)
node _T_1594 = eq(_T_1593, UInt<1>(0h0))
when _T_1594 :
node _T_1595 = eq(_T_1592, UInt<1>(0h0))
when _T_1595 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1592, UInt<1>(0h1), "") : assert_87
node _T_1596 = eq(io.in.a.bits.param, param)
node _T_1597 = asUInt(reset)
node _T_1598 = eq(_T_1597, UInt<1>(0h0))
when _T_1598 :
node _T_1599 = eq(_T_1596, UInt<1>(0h0))
when _T_1599 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1596, UInt<1>(0h1), "") : assert_88
node _T_1600 = eq(io.in.a.bits.size, size)
node _T_1601 = asUInt(reset)
node _T_1602 = eq(_T_1601, UInt<1>(0h0))
when _T_1602 :
node _T_1603 = eq(_T_1600, UInt<1>(0h0))
when _T_1603 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1600, UInt<1>(0h1), "") : assert_89
node _T_1604 = eq(io.in.a.bits.source, source)
node _T_1605 = asUInt(reset)
node _T_1606 = eq(_T_1605, UInt<1>(0h0))
when _T_1606 :
node _T_1607 = eq(_T_1604, UInt<1>(0h0))
when _T_1607 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1604, UInt<1>(0h1), "") : assert_90
node _T_1608 = eq(io.in.a.bits.address, address)
node _T_1609 = asUInt(reset)
node _T_1610 = eq(_T_1609, UInt<1>(0h0))
when _T_1610 :
node _T_1611 = eq(_T_1608, UInt<1>(0h0))
when _T_1611 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1608, UInt<1>(0h1), "") : assert_91
node _T_1612 = and(io.in.a.ready, io.in.a.valid)
node _T_1613 = and(_T_1612, a_first)
when _T_1613 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1614 = eq(d_first, UInt<1>(0h0))
node _T_1615 = and(io.in.d.valid, _T_1614)
when _T_1615 :
node _T_1616 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1617 = asUInt(reset)
node _T_1618 = eq(_T_1617, UInt<1>(0h0))
when _T_1618 :
node _T_1619 = eq(_T_1616, UInt<1>(0h0))
when _T_1619 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1616, UInt<1>(0h1), "") : assert_92
node _T_1620 = eq(io.in.d.bits.param, param_1)
node _T_1621 = asUInt(reset)
node _T_1622 = eq(_T_1621, UInt<1>(0h0))
when _T_1622 :
node _T_1623 = eq(_T_1620, UInt<1>(0h0))
when _T_1623 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1620, UInt<1>(0h1), "") : assert_93
node _T_1624 = eq(io.in.d.bits.size, size_1)
node _T_1625 = asUInt(reset)
node _T_1626 = eq(_T_1625, UInt<1>(0h0))
when _T_1626 :
node _T_1627 = eq(_T_1624, UInt<1>(0h0))
when _T_1627 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1624, UInt<1>(0h1), "") : assert_94
node _T_1628 = eq(io.in.d.bits.source, source_1)
node _T_1629 = asUInt(reset)
node _T_1630 = eq(_T_1629, UInt<1>(0h0))
when _T_1630 :
node _T_1631 = eq(_T_1628, UInt<1>(0h0))
when _T_1631 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1628, UInt<1>(0h1), "") : assert_95
node _T_1632 = eq(io.in.d.bits.sink, sink)
node _T_1633 = asUInt(reset)
node _T_1634 = eq(_T_1633, UInt<1>(0h0))
when _T_1634 :
node _T_1635 = eq(_T_1632, UInt<1>(0h0))
when _T_1635 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1632, UInt<1>(0h1), "") : assert_96
node _T_1636 = eq(io.in.d.bits.denied, denied)
node _T_1637 = asUInt(reset)
node _T_1638 = eq(_T_1637, UInt<1>(0h0))
when _T_1638 :
node _T_1639 = eq(_T_1636, UInt<1>(0h0))
when _T_1639 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1636, UInt<1>(0h1), "") : assert_97
node _T_1640 = and(io.in.d.ready, io.in.d.valid)
node _T_1641 = and(_T_1640, d_first)
when _T_1641 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes : UInt<520>, clock, reset, UInt<520>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<65>
connect a_set, UInt<65>(0h0)
wire a_set_wo_ready : UInt<65>
connect a_set_wo_ready, UInt<65>(0h0)
wire a_opcodes_set : UInt<260>
connect a_opcodes_set, UInt<260>(0h0)
wire a_sizes_set : UInt<520>
connect a_sizes_set, UInt<520>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<8>
connect a_size_lookup, UInt<8>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<5>
connect a_sizes_set_interm, UInt<5>(0h0)
node _T_1642 = and(io.in.a.valid, a_first_1)
node _T_1643 = and(_T_1642, UInt<1>(0h1))
when _T_1643 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1644 = and(io.in.a.ready, io.in.a.valid)
node _T_1645 = and(_T_1644, a_first_1)
node _T_1646 = and(_T_1645, UInt<1>(0h1))
when _T_1646 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1647 = dshr(inflight, io.in.a.bits.source)
node _T_1648 = bits(_T_1647, 0, 0)
node _T_1649 = eq(_T_1648, UInt<1>(0h0))
node _T_1650 = asUInt(reset)
node _T_1651 = eq(_T_1650, UInt<1>(0h0))
when _T_1651 :
node _T_1652 = eq(_T_1649, UInt<1>(0h0))
when _T_1652 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1649, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<65>
connect d_clr, UInt<65>(0h0)
wire d_clr_wo_ready : UInt<65>
connect d_clr_wo_ready, UInt<65>(0h0)
wire d_opcodes_clr : UInt<260>
connect d_opcodes_clr, UInt<260>(0h0)
wire d_sizes_clr : UInt<520>
connect d_sizes_clr, UInt<520>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1653 = and(io.in.d.valid, d_first_1)
node _T_1654 = and(_T_1653, UInt<1>(0h1))
node _T_1655 = eq(d_release_ack, UInt<1>(0h0))
node _T_1656 = and(_T_1654, _T_1655)
when _T_1656 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1657 = and(io.in.d.ready, io.in.d.valid)
node _T_1658 = and(_T_1657, d_first_1)
node _T_1659 = and(_T_1658, UInt<1>(0h1))
node _T_1660 = eq(d_release_ack, UInt<1>(0h0))
node _T_1661 = and(_T_1659, _T_1660)
when _T_1661 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1662 = and(io.in.d.valid, d_first_1)
node _T_1663 = and(_T_1662, UInt<1>(0h1))
node _T_1664 = eq(d_release_ack, UInt<1>(0h0))
node _T_1665 = and(_T_1663, _T_1664)
when _T_1665 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1666 = dshr(inflight, io.in.d.bits.source)
node _T_1667 = bits(_T_1666, 0, 0)
node _T_1668 = or(_T_1667, same_cycle_resp)
node _T_1669 = asUInt(reset)
node _T_1670 = eq(_T_1669, UInt<1>(0h0))
when _T_1670 :
node _T_1671 = eq(_T_1668, UInt<1>(0h0))
when _T_1671 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1668, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1672 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1673 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1674 = or(_T_1672, _T_1673)
node _T_1675 = asUInt(reset)
node _T_1676 = eq(_T_1675, UInt<1>(0h0))
when _T_1676 :
node _T_1677 = eq(_T_1674, UInt<1>(0h0))
when _T_1677 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1674, UInt<1>(0h1), "") : assert_100
node _T_1678 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1679 = asUInt(reset)
node _T_1680 = eq(_T_1679, UInt<1>(0h0))
when _T_1680 :
node _T_1681 = eq(_T_1678, UInt<1>(0h0))
when _T_1681 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1678, UInt<1>(0h1), "") : assert_101
else :
node _T_1682 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1683 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1684 = or(_T_1682, _T_1683)
node _T_1685 = asUInt(reset)
node _T_1686 = eq(_T_1685, UInt<1>(0h0))
when _T_1686 :
node _T_1687 = eq(_T_1684, UInt<1>(0h0))
when _T_1687 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1684, UInt<1>(0h1), "") : assert_102
node _T_1688 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1689 = asUInt(reset)
node _T_1690 = eq(_T_1689, UInt<1>(0h0))
when _T_1690 :
node _T_1691 = eq(_T_1688, UInt<1>(0h0))
when _T_1691 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1688, UInt<1>(0h1), "") : assert_103
node _T_1692 = and(io.in.d.valid, d_first_1)
node _T_1693 = and(_T_1692, a_first_1)
node _T_1694 = and(_T_1693, io.in.a.valid)
node _T_1695 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1696 = and(_T_1694, _T_1695)
node _T_1697 = eq(d_release_ack, UInt<1>(0h0))
node _T_1698 = and(_T_1696, _T_1697)
when _T_1698 :
node _T_1699 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1700 = or(_T_1699, io.in.a.ready)
node _T_1701 = asUInt(reset)
node _T_1702 = eq(_T_1701, UInt<1>(0h0))
when _T_1702 :
node _T_1703 = eq(_T_1700, UInt<1>(0h0))
when _T_1703 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1700, UInt<1>(0h1), "") : assert_104
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_42
node _T_1704 = orr(inflight)
node _T_1705 = eq(_T_1704, UInt<1>(0h0))
node _T_1706 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1707 = or(_T_1705, _T_1706)
node _T_1708 = lt(watchdog, plusarg_reader.out)
node _T_1709 = or(_T_1707, _T_1708)
node _T_1710 = asUInt(reset)
node _T_1711 = eq(_T_1710, UInt<1>(0h0))
when _T_1711 :
node _T_1712 = eq(_T_1709, UInt<1>(0h0))
when _T_1712 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_1709, UInt<1>(0h1), "") : assert_105
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1713 = and(io.in.a.ready, io.in.a.valid)
node _T_1714 = and(io.in.d.ready, io.in.d.valid)
node _T_1715 = or(_T_1713, _T_1714)
when _T_1715 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes_1 : UInt<520>, clock, reset, UInt<520>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<29>(0h0)
connect _c_first_WIRE.bits.source, UInt<7>(0h0)
connect _c_first_WIRE.bits.size, UInt<4>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<29>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<65>
connect c_set, UInt<65>(0h0)
wire c_set_wo_ready : UInt<65>
connect c_set_wo_ready, UInt<65>(0h0)
wire c_opcodes_set : UInt<260>
connect c_opcodes_set, UInt<260>(0h0)
wire c_sizes_set : UInt<520>
connect c_sizes_set, UInt<520>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<8>
connect c_size_lookup, UInt<8>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<5>
connect c_sizes_set_interm, UInt<5>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<29>(0h0)
connect _WIRE_10.bits.source, UInt<7>(0h0)
connect _WIRE_10.bits.size, UInt<4>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1716 = and(_WIRE_11.valid, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<29>(0h0)
connect _WIRE_12.bits.source, UInt<7>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1717 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1718 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1719 = and(_T_1717, _T_1718)
node _T_1720 = and(_T_1716, _T_1719)
when _T_1720 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<29>(0h0)
connect _WIRE_14.bits.source, UInt<7>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1721 = and(_WIRE_15.ready, _WIRE_15.valid)
node _T_1722 = and(_T_1721, c_first)
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<29>(0h0)
connect _WIRE_16.bits.source, UInt<7>(0h0)
connect _WIRE_16.bits.size, UInt<4>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1723 = bits(_WIRE_17.bits.opcode, 2, 2)
node _T_1724 = bits(_WIRE_17.bits.opcode, 1, 1)
node _T_1725 = and(_T_1723, _T_1724)
node _T_1726 = and(_T_1722, _T_1725)
when _T_1726 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<29>(0h0)
connect _WIRE_18.bits.source, UInt<7>(0h0)
connect _WIRE_18.bits.size, UInt<4>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1727 = dshr(inflight_1, _WIRE_19.bits.source)
node _T_1728 = bits(_T_1727, 0, 0)
node _T_1729 = eq(_T_1728, UInt<1>(0h0))
node _T_1730 = asUInt(reset)
node _T_1731 = eq(_T_1730, UInt<1>(0h0))
when _T_1731 :
node _T_1732 = eq(_T_1729, UInt<1>(0h0))
when _T_1732 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1729, UInt<1>(0h1), "") : assert_106
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<65>
connect d_clr_1, UInt<65>(0h0)
wire d_clr_wo_ready_1 : UInt<65>
connect d_clr_wo_ready_1, UInt<65>(0h0)
wire d_opcodes_clr_1 : UInt<260>
connect d_opcodes_clr_1, UInt<260>(0h0)
wire d_sizes_clr_1 : UInt<520>
connect d_sizes_clr_1, UInt<520>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1733 = and(io.in.d.valid, d_first_2)
node _T_1734 = and(_T_1733, UInt<1>(0h1))
node _T_1735 = and(_T_1734, d_release_ack_1)
when _T_1735 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1736 = and(io.in.d.ready, io.in.d.valid)
node _T_1737 = and(_T_1736, d_first_2)
node _T_1738 = and(_T_1737, UInt<1>(0h1))
node _T_1739 = and(_T_1738, d_release_ack_1)
when _T_1739 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1740 = and(io.in.d.valid, d_first_2)
node _T_1741 = and(_T_1740, UInt<1>(0h1))
node _T_1742 = and(_T_1741, d_release_ack_1)
when _T_1742 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1743 = dshr(inflight_1, io.in.d.bits.source)
node _T_1744 = bits(_T_1743, 0, 0)
node _T_1745 = or(_T_1744, same_cycle_resp_1)
node _T_1746 = asUInt(reset)
node _T_1747 = eq(_T_1746, UInt<1>(0h0))
when _T_1747 :
node _T_1748 = eq(_T_1745, UInt<1>(0h0))
when _T_1748 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107
assert(clock, _T_1745, UInt<1>(0h1), "") : assert_107
when same_cycle_resp_1 :
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<29>(0h0)
connect _WIRE_20.bits.source, UInt<7>(0h0)
connect _WIRE_20.bits.size, UInt<4>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1749 = eq(io.in.d.bits.size, _WIRE_21.bits.size)
node _T_1750 = asUInt(reset)
node _T_1751 = eq(_T_1750, UInt<1>(0h0))
when _T_1751 :
node _T_1752 = eq(_T_1749, UInt<1>(0h0))
when _T_1752 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1749, UInt<1>(0h1), "") : assert_108
else :
node _T_1753 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1754 = asUInt(reset)
node _T_1755 = eq(_T_1754, UInt<1>(0h0))
when _T_1755 :
node _T_1756 = eq(_T_1753, UInt<1>(0h0))
when _T_1756 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1753, UInt<1>(0h1), "") : assert_109
node _T_1757 = and(io.in.d.valid, d_first_2)
node _T_1758 = and(_T_1757, c_first)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<29>(0h0)
connect _WIRE_22.bits.source, UInt<7>(0h0)
connect _WIRE_22.bits.size, UInt<4>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1759 = and(_T_1758, _WIRE_23.valid)
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<29>(0h0)
connect _WIRE_24.bits.source, UInt<7>(0h0)
connect _WIRE_24.bits.size, UInt<4>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1760 = eq(_WIRE_25.bits.source, io.in.d.bits.source)
node _T_1761 = and(_T_1759, _T_1760)
node _T_1762 = and(_T_1761, d_release_ack_1)
node _T_1763 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1764 = and(_T_1762, _T_1763)
when _T_1764 :
node _T_1765 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<64>(0h0)
connect _WIRE_26.bits.address, UInt<29>(0h0)
connect _WIRE_26.bits.source, UInt<7>(0h0)
connect _WIRE_26.bits.size, UInt<4>(0h0)
connect _WIRE_26.bits.param, UInt<3>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
node _T_1766 = or(_T_1765, _WIRE_27.ready)
node _T_1767 = asUInt(reset)
node _T_1768 = eq(_T_1767, UInt<1>(0h0))
when _T_1768 :
node _T_1769 = eq(_T_1766, UInt<1>(0h0))
when _T_1769 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1766, UInt<1>(0h1), "") : assert_110
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_43
node _T_1770 = orr(inflight_1)
node _T_1771 = eq(_T_1770, UInt<1>(0h0))
node _T_1772 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1773 = or(_T_1771, _T_1772)
node _T_1774 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1775 = or(_T_1773, _T_1774)
node _T_1776 = asUInt(reset)
node _T_1777 = eq(_T_1776, UInt<1>(0h0))
when _T_1777 :
node _T_1778 = eq(_T_1775, UInt<1>(0h0))
when _T_1778 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_1775, UInt<1>(0h1), "") : assert_111
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<64>(0h0)
connect _WIRE_28.bits.address, UInt<29>(0h0)
connect _WIRE_28.bits.source, UInt<7>(0h0)
connect _WIRE_28.bits.size, UInt<4>(0h0)
connect _WIRE_28.bits.param, UInt<3>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
node _T_1779 = and(_WIRE_29.ready, _WIRE_29.valid)
node _T_1780 = and(io.in.d.ready, io.in.d.valid)
node _T_1781 = or(_T_1779, _T_1780)
when _T_1781 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_21( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27]
wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_54 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_56 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_60 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_62 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_66 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_68 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_72 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_74 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_78 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_80 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_84 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_86 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_90 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_92 = 1'h1; // @[Parameters.scala:57:20]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28]
wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [1027:0] _c_sizes_set_T_1 = 1028'h0; // @[Monitor.scala:768:52]
wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79]
wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77]
wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35]
wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35]
wire [519:0] c_sizes_set = 520'h0; // @[Monitor.scala:741:34]
wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34]
wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34]
wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_66 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_67 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_68 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_69 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_70 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_71 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_72 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_73 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_74 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_75 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_76 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_12 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_13 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 7'h30; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 5'h8; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 5'h9; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 5'hA; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 5'hB; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _source_ok_T_25 = io_in_a_bits_source_0[6:3]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_31 = io_in_a_bits_source_0[6:3]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_37 = io_in_a_bits_source_0[6:3]; // @[Monitor.scala:36:7]
wire _source_ok_T_26 = _source_ok_T_25 == 4'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_32 = _source_ok_T_31 == 4'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_6 = _source_ok_T_36; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_38 = _source_ok_T_37 == 4'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_7 = _source_ok_T_42; // @[Parameters.scala:1138:31]
wire _source_ok_T_43 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_8 = _source_ok_T_43; // @[Parameters.scala:1138:31]
wire _source_ok_T_44 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_45 = _source_ok_T_44 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_46 = _source_ok_T_45 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_47 = _source_ok_T_46 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_48 = _source_ok_T_47 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_49 = _source_ok_T_48 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_50 = _source_ok_T_49 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_50 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [28:0] _is_aligned_T = {17'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_5 = _uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_6 = _uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_11 = _uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_12 = _uncommonBits_T_12[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_13 = _uncommonBits_T_13[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_18 = _uncommonBits_T_18[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_19 = _uncommonBits_T_19[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_20 = _uncommonBits_T_20[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_25 = _uncommonBits_T_25[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_26 = _uncommonBits_T_26[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_27 = _uncommonBits_T_27[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_32 = _uncommonBits_T_32[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_33 = _uncommonBits_T_33[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_34 = _uncommonBits_T_34[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_39 = _uncommonBits_T_39[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_40 = _uncommonBits_T_40[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_41 = _uncommonBits_T_41[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_46 = _uncommonBits_T_46[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_47 = _uncommonBits_T_47[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_48 = _uncommonBits_T_48[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_53 = _uncommonBits_T_53[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_54 = _uncommonBits_T_54[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_55 = _uncommonBits_T_55[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_58 = _uncommonBits_T_58[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_59 = _uncommonBits_T_59[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_60 = _uncommonBits_T_60[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_61 = _uncommonBits_T_61[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_62 = _uncommonBits_T_62[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_64 = _uncommonBits_T_64[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_65 = _uncommonBits_T_65[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_66 = _uncommonBits_T_66[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_67 = _uncommonBits_T_67[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_68 = _uncommonBits_T_68[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_69 = _uncommonBits_T_69[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_70 = _uncommonBits_T_70[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_71 = _uncommonBits_T_71[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_72 = _uncommonBits_T_72[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_73 = _uncommonBits_T_73[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_74 = _uncommonBits_T_74[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_75 = _uncommonBits_T_75[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_76 = _uncommonBits_T_76[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_51 = io_in_d_bits_source_0 == 7'h30; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_51; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_52 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_58 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_64 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_70 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_53 = _source_ok_T_52 == 5'h8; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_55 = _source_ok_T_53; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_57 = _source_ok_T_55; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_57; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_59 = _source_ok_T_58 == 5'h9; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_61 = _source_ok_T_59; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_63 = _source_ok_T_61; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_63; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_65 = _source_ok_T_64 == 5'hA; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_67 = _source_ok_T_65; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_69 = _source_ok_T_67; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_69; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_71 = _source_ok_T_70 == 5'hB; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_73 = _source_ok_T_71; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_75 = _source_ok_T_73; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_75; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _source_ok_T_76 = io_in_d_bits_source_0[6:3]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_82 = io_in_d_bits_source_0[6:3]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_88 = io_in_d_bits_source_0[6:3]; // @[Monitor.scala:36:7]
wire _source_ok_T_77 = _source_ok_T_76 == 4'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_79 = _source_ok_T_77; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_81 = _source_ok_T_79; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_5 = _source_ok_T_81; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_12 = _source_ok_uncommonBits_T_12[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_83 = _source_ok_T_82 == 4'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_85 = _source_ok_T_83; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_87 = _source_ok_T_85; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_6 = _source_ok_T_87; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_13 = _source_ok_uncommonBits_T_13[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_89 = _source_ok_T_88 == 4'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_91 = _source_ok_T_89; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_93 = _source_ok_T_91; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_7 = _source_ok_T_93; // @[Parameters.scala:1138:31]
wire _source_ok_T_94 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_8 = _source_ok_T_94; // @[Parameters.scala:1138:31]
wire _source_ok_T_95 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_96 = _source_ok_T_95 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_97 = _source_ok_T_96 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_98 = _source_ok_T_97 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_99 = _source_ok_T_98 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_100 = _source_ok_T_99 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_101 = _source_ok_T_100 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_101 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1713 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1713; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1713; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [6:0] source; // @[Monitor.scala:390:22]
reg [28:0] address; // @[Monitor.scala:391:22]
wire _T_1781 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1781; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1781; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1781; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [6:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [64:0] inflight; // @[Monitor.scala:614:27]
reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [519:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [64:0] a_set; // @[Monitor.scala:626:34]
wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [519:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [9:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [519:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [519:0] _a_size_lookup_T_6 = {512'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}]
wire [519:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[519:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [127:0] _GEN_3 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35]
wire [127:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1646 = _T_1713 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1646 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1646 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1646 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [9:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1646 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [9:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [1027:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1646 ? _a_sizes_set_T_1[519:0] : 520'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [64:0] d_clr; // @[Monitor.scala:664:34]
wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [519:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1692 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1692 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1661 = _T_1781 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1661 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1661 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [1038:0] _d_sizes_clr_T_5 = 1039'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1661 ? _d_sizes_clr_T_5[519:0] : 520'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [519:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [519:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [519:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [64:0] inflight_1; // @[Monitor.scala:726:35]
wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [519:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [519:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [519:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [519:0] _c_size_lookup_T_6 = {512'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}]
wire [519:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[519:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [64:0] d_clr_1; // @[Monitor.scala:774:34]
wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [519:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1757 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1757 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1739 = _T_1781 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1739 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1739 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [1038:0] _d_sizes_clr_T_11 = 1039'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1739 ? _d_sizes_clr_T_11[519:0] : 520'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113]
wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [519:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [519:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
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